IEMAllThreadedFunctions.cpp@ 100089

Last change on this file since 100089 was 100089, checked in by vboxsync, 18 months ago
VMM/IEM: Reworking the variations generated by the python script to match part of the fExec mode better. bugref:10369
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1	/* $Id: IEMAllThreadedFunctions.cpp 100089 2023-06-07 01:39:11Z vboxsync $ */
2	/** @file
3	* IEM - Instruction Decoding and Emulation, Threaded Functions.
4	*/
5
6	/*
7	* Copyright (C) 2011-2023 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28
29	/*********************************************************************************************************************************
30	* Header Files *
31	*********************************************************************************************************************************/
32	#ifndef LOG_GROUP /* defined when included by tstIEMCheckMc.cpp */
33	# define LOG_GROUP LOG_GROUP_IEM
34	#endif
35	#define VMCPU_INCL_CPUM_GST_CTX
36	#define IEM_WITH_OPAQUE_DECODER_STATE
37	#include <VBox/vmm/iem.h>
38	#include <VBox/vmm/cpum.h>
39	#include <VBox/vmm/apic.h>
40	#include <VBox/vmm/pdm.h>
41	#include <VBox/vmm/pgm.h>
42	#include <VBox/vmm/iom.h>
43	#include <VBox/vmm/em.h>
44	#include <VBox/vmm/hm.h>
45	#include <VBox/vmm/nem.h>
46	#include <VBox/vmm/gim.h>
47	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
48	# include <VBox/vmm/em.h>
49	# include <VBox/vmm/hm_svm.h>
50	#endif
51	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
52	# include <VBox/vmm/hmvmxinline.h>
53	#endif
54	#include <VBox/vmm/tm.h>
55	#include <VBox/vmm/dbgf.h>
56	#include <VBox/vmm/dbgftrace.h>
57	#include "IEMInternal.h"
58	#include <VBox/vmm/vmcc.h>
59	#include <VBox/log.h>
60	#include <VBox/err.h>
61	#include <VBox/param.h>
62	#include <VBox/dis.h>
63	#include <VBox/disopcode-x86-amd64.h>
64	#include <iprt/asm-math.h>
65	#include <iprt/assert.h>
66	#include <iprt/string.h>
67	#include <iprt/x86.h>
68
69	#include "IEMInline.h"
70	#include "IEMMc.h"
71
72	#include "IEMThreadedFunctions.h"
73
74
75	/*********************************************************************************************************************************
76	* Defined Constants And Macros *
77	*********************************************************************************************************************************/
78
79	/** Variant of IEM_MC_ADVANCE_RIP_AND_FINISH with instruction length as param
80	* and only used when we're in 16-bit code on a pre-386 CPU. */
81	#define IEM_MC_ADVANCE_RIP_AND_FINISH_THREADED_PC16(a_cbInstr) \
82	return iemRegAddToIp16AndFinishingClearingRF(pVCpu, a_cbInstr)
83
84	/** Variant of IEM_MC_ADVANCE_RIP_AND_FINISH with instruction length as param
85	* and used for 16-bit and 32-bit code on 386 and later CPUs. */
86	#define IEM_MC_ADVANCE_RIP_AND_FINISH_THREADED_PC32(a_cbInstr) \
87	return iemRegAddToEip32AndFinishingClearingRF(pVCpu, a_cbInstr)
88
89	/** Variant of IEM_MC_ADVANCE_RIP_AND_FINISH with instruction length as param
90	* and only used when we're in 64-bit code. */
91	#define IEM_MC_ADVANCE_RIP_AND_FINISH_THREADED_PC64(a_cbInstr) \
92	return iemRegAddToRip64AndFinishingClearingRF(pVCpu, a_cbInstr)
93
94	#undef IEM_MC_ADVANCE_RIP_AND_FINISH
95
96
97	/** Variant of IEM_MC_REL_JMP_S8_AND_FINISH with instruction length as param. */
98	#define IEM_MC_REL_JMP_S8_AND_FINISH_THREADED(a_i8, a_cbInstr, a_enmEffOpSize) \
99	return iemRegRipRelativeJumpS8AndFinishClearingRF(pVCpu, a_cbInstr, (a_i8), a_enmEffOpSize)
100	#undef IEM_MC_REL_JMP_S8_AND_FINISH
101
102	/** Variant of IEM_MC_REL_JMP_S16_AND_FINISH with instruction length as param. */
103	#define IEM_MC_REL_JMP_S16_AND_FINISH_THREADED(a_i16, a_cbInstr) \
104	return iemRegRipRelativeJumpS16AndFinishClearingRF(pVCpu, a_cbInstr, (a_i16))
105	#undef IEM_MC_REL_JMP_S16_AND_FINISH
106
107	/** Variant of IEM_MC_REL_JMP_S32_AND_FINISH with instruction length as param. */
108	#define IEM_MC_REL_JMP_S32_AND_FINISH_THREADED(a_i32, a_cbInstr, a_enmEffOpSize) \
109	return iemRegRipRelativeJumpS32AndFinishClearingRF(pVCpu, a_cbInstr, (a_i32), a_enmEffOpSize)
110	#undef IEM_MC_REL_JMP_S32_AND_FINISH
111
112
113	/** Variant of IEM_MC_CALC_RM_EFF_ADDR with additional parameters, 16-bit. */
114	#define IEM_MC_CALC_RM_EFF_ADDR_THREADED_16(a_GCPtrEff, a_bRm, a_u16Disp) \
115	(a_GCPtrEff) = iemOpHlpCalcRmEffAddrThreadedAddr16(pVCpu, a_bRm, a_u16Disp)
116
117	/** Variant of IEM_MC_CALC_RM_EFF_ADDR with additional parameters, pre-386 16-bit. */
118	#define IEM_MC_CALC_RM_EFF_ADDR_THREADED_16_PRE386(a_GCPtrEff, a_bRm, a_u16Disp) \
119	IEM_MC_CALC_RM_EFF_ADDR_THREADED_16(a_GCPtrEff, a_bRm, a_u16Disp)
120
121	/** Variant of IEM_MC_CALC_RM_EFF_ADDR with additional parameters, 32-bit with address prefix. */
122	#define IEM_MC_CALC_RM_EFF_ADDR_THREADED_32_ADDR16(a_GCPtrEff, a_bRm, a_u16Disp) \
123	IEM_MC_CALC_RM_EFF_ADDR_THREADED_16(a_GCPtrEff, a_bRm, a_u16Disp)
124
125
126	/** Variant of IEM_MC_CALC_RM_EFF_ADDR with additional parameters, 32-bit. */
127	#define IEM_MC_CALC_RM_EFF_ADDR_THREADED_32(a_GCPtrEff, a_bRm, a_bSib, a_u32Disp) \
128	(a_GCPtrEff) = iemOpHlpCalcRmEffAddrThreadedAddr32(pVCpu, a_bRm, a_bSib, a_u32Disp)
129
130	/** Variant of IEM_MC_CALC_RM_EFF_ADDR with additional parameters, 32-bit flat. */
131	#define IEM_MC_CALC_RM_EFF_ADDR_THREADED_32_FLAT(a_GCPtrEff, a_bRm, a_bSib, a_u32Disp) \
132	(a_GCPtrEff) = iemOpHlpCalcRmEffAddrThreadedAddr32(pVCpu, a_bRm, a_bSib, a_u32Disp)
133
134	/** Variant of IEM_MC_CALC_RM_EFF_ADDR with additional parameters, 16-bit with address prefix. */
135	#define IEM_MC_CALC_RM_EFF_ADDR_THREADED_16_ADDR32(a_GCPtrEff, a_bRm, a_bSib, a_u32Disp) \
136	(a_GCPtrEff) = iemOpHlpCalcRmEffAddrThreadedAddr32(pVCpu, a_bRm, a_bSib, a_u32Disp)
137
138
139	/** Variant of IEM_MC_CALC_RM_EFF_ADDR with additional parameters. */
140	#define IEM_MC_CALC_RM_EFF_ADDR_THREADED_64(a_GCPtrEff, a_bRmEx, a_bSib, a_u32Disp, a_cbImm) \
141	(a_GCPtrEff) = iemOpHlpCalcRmEffAddrThreadedAddr64(pVCpu, a_bRmEx, a_bSib, a_u32Disp, a_cbImm)
142
143	/** Variant of IEM_MC_CALC_RM_EFF_ADDR with additional parameters.
144	* @todo How did that address prefix thing work for 64-bit code again? */
145	#define IEM_MC_CALC_RM_EFF_ADDR_THREADED_64_ADDR32(a_GCPtrEff, a_bRmEx, a_bSib, a_u32Disp, a_cbImm) \
146	(a_GCPtrEff) = (uint32_t)iemOpHlpCalcRmEffAddrThreadedAddr64(pVCpu, a_bRmEx, a_bSib, a_u32Disp, a_cbImm)
147
148	#undef IEM_MC_CALC_RM_EFF_ADDR
149
150
151	/** Variant of IEM_MC_CALL_CIMPL_1 with explicit instruction length parameter. */
152	#define IEM_MC_CALL_CIMPL_1_THREADED(a_cbInstr, a_fFlags, a_pfnCImpl, a0) \
153	return (a_pfnCImpl)(pVCpu, (a_cbInstr), a0)
154	#undef IEM_MC_CALL_CIMPL_1
155
156	/** Variant of IEM_MC_CALL_CIMPL_2 with explicit instruction length parameter. */
157	#define IEM_MC_CALL_CIMPL_2_THREADED(a_cbInstr, a_fFlags, a_pfnCImpl, a0, a1) \
158	return (a_pfnCImpl)(pVCpu, (a_cbInstr), a0, a1)
159	#undef IEM_MC_CALL_CIMPL_2
160
161	/** Variant of IEM_MC_CALL_CIMPL_3 with explicit instruction length parameter. */
162	#define IEM_MC_CALL_CIMPL_3_THREADED(a_cbInstr, a_fFlags, a_pfnCImpl, a0, a1, a2) \
163	return (a_pfnCImpl)(pVCpu, (a_cbInstr), a0, a1, a2)
164	#undef IEM_MC_CALL_CIMPL_3
165
166	/** Variant of IEM_MC_CALL_CIMPL_4 with explicit instruction length parameter. */
167	#define IEM_MC_CALL_CIMPL_4_THREADED(a_cbInstr, a_fFlags, a_pfnCImpl, a0, a1, a2, a3) \
168	return (a_pfnCImpl)(pVCpu, (a_cbInstr), a0, a1, a2, a3)
169	#undef IEM_MC_CALL_CIMPL_4
170
171	/** Variant of IEM_MC_CALL_CIMPL_5 with explicit instruction length parameter. */
172	#define IEM_MC_CALL_CIMPL_5_THREADED(a_cbInstr, a_fFlags, a_pfnCImpl, a0, a1, a2, a3, a4) \
173	return (a_pfnCImpl)(pVCpu, (a_cbInstr), a0, a1, a2, a3, a4)
174	#undef IEM_MC_CALL_CIMPL_5
175
176	/** Variant of IEM_MC_FETCH_GREG_U8 with extended (20) register index. */
177	#define IEM_MC_FETCH_GREG_U8_THREADED(a_u8Dst, a_iGRegEx) \
178	(a_u8Dst) = iemGRegFetchU8Ex(pVCpu, (a_iGRegEx))
179
180	/** Variant of IEM_MC_FETCH_GREG_U8_ZX_U16 with extended (20) register index. */
181	#define IEM_MC_FETCH_GREG_U8_ZX_U16_THREADED(a_u16Dst, a_iGRegEx) \
182	(a_u16Dst) = iemGRegFetchU8Ex(pVCpu, (a_iGRegEx))
183
184	/** Variant of IEM_MC_FETCH_GREG_U8_ZX_U32 with extended (20) register index. */
185	#define IEM_MC_FETCH_GREG_U8_ZX_U32_THREADED(a_u32Dst, a_iGRegEx) \
186	(a_u32Dst) = iemGRegFetchU8Ex(pVCpu, (a_iGRegEx))
187
188	/** Variant of IEM_MC_FETCH_GREG_U8_ZX_U64 with extended (20) register index. */
189	#define IEM_MC_FETCH_GREG_U8_ZX_U64_THREADED(a_u64Dst, a_iGRegEx) \
190	(a_u64Dst) = iemGRegFetchU8Ex(pVCpu, (a_iGRegEx))
191
192	/** Variant of IEM_MC_FETCH_GREG_U8_SX_U16 with extended (20) register index. */
193	#define IEM_MC_FETCH_GREG_U8_SX_U16_THREADED(a_u16Dst, a_iGRegEx) \
194	(a_u16Dst) = (int8_t)iemGRegFetchU8Ex(pVCpu, (a_iGRegEx))
195
196	/** Variant of IEM_MC_FETCH_GREG_U8_SX_U32 with extended (20) register index. */
197	#define IEM_MC_FETCH_GREG_U8_SX_U32_THREADED(a_u32Dst, a_iGRegEx) \
198	(a_u32Dst) = (int8_t)iemGRegFetchU8Ex(pVCpu, (a_iGRegEx))
199	#undef IEM_MC_FETCH_GREG_U8_SX_U32
200
201	/** Variant of IEM_MC_FETCH_GREG_U8_SX_U64 with extended (20) register index. */
202	#define IEM_MC_FETCH_GREG_U8_SX_U64_THREADED(a_u64Dst, a_iGRegEx) \
203	(a_u64Dst) = (int8_t)iemGRegFetchU8Ex(pVCpu, (a_iGRegEx))
204	#undef IEM_MC_FETCH_GREG_U8_SX_U64
205
206	/** Variant of IEM_MC_STORE_GREG_U8 with extended (20) register index. */
207	#define IEM_MC_STORE_GREG_U8_THREADED(a_iGRegEx, a_u8Value) \
208	*iemGRegRefU8Ex(pVCpu, (a_iGRegEx)) = (a_u8Value)
209	#undef IEM_MC_STORE_GREG_U8
210
211	/** Variant of IEM_MC_STORE_GREG_U8 with extended (20) register index. */
212	#define IEM_MC_STORE_GREG_U8_CONST_THREADED(a_iGRegEx, a_u8Value) \
213	*iemGRegRefU8Ex(pVCpu, (a_iGRegEx)) = (a_u8Value)
214	#undef IEM_MC_STORE_GREG_U8
215
216	/** Variant of IEM_MC_REF_GREG_U8 with extended (20) register index. */
217	#define IEM_MC_REF_GREG_U8_THREADED(a_pu8Dst, a_iGRegEx) \
218	(a_pu8Dst) = iemGRegRefU8Ex(pVCpu, (a_iGRegEx))
219	#undef IEM_MC_REF_GREG_U8
220
221	/** Variant of IEM_MC_ADD_GREG_U8 with extended (20) register index. */
222	#define IEM_MC_ADD_GREG_U8_THREADED(a_iGRegEx, a_u8Value) \
223	*iemGRegRefU8Ex(pVCpu, (a_iGRegEx)) += (a_u8Value)
224	#undef IEM_MC_ADD_GREG_U8
225
226	/** Variant of IEM_MC_SUB_GREG_U8 with extended (20) register index. */
227	#define IEM_MC_SUB_GREG_U8_THREADED(a_iGRegEx, a_u8Value) \
228	*iemGRegRefU8Ex(pVCpu, (a_iGRegEx)) -= (a_u8Value)
229	#undef IEM_MC_SUB_GREG_U8
230
231	/** Variant of IEM_MC_ADD_GREG_U8_TO_LOCAL with extended (20) register index. */
232	#define IEM_MC_ADD_GREG_U8_TO_LOCAL_THREADED(a_u8Value, a_iGRegEx) \
233	do { (a_u8Value) += iemGRegFetchU8Ex(pVCpu, (a_iGRegEx)); } while (0)
234	#undef IEM_MC_ADD_GREG_U8_TO_LOCAL
235
236	/** Variant of IEM_MC_AND_GREG_U8 with extended (20) register index. */
237	#define IEM_MC_AND_GREG_U8_THREADED(a_iGRegEx, a_u8Value) \
238	*iemGRegRefU8Ex(pVCpu, (a_iGRegEx)) &= (a_u8Value)
239	#undef IEM_MC_AND_GREG_U8
240
241	/** Variant of IEM_MC_OR_GREG_U8 with extended (20) register index. */
242	#define IEM_MC_OR_GREG_U8_THREADED(a_iGRegEx, a_u8Value) \
243	*iemGRegRefU8Ex(pVCpu, (a_iGRegEx)) \|= (a_u8Value)
244	#undef IEM_MC_OR_GREG_U8
245
246	/**
247	* Calculates the effective address of a ModR/M memory operand, 16-bit
248	* addressing variant.
249	*
250	* Meant to be used via IEM_MC_CALC_RM_EFF_ADDR_THREADED_ADDR16.
251	*
252	* @returns The effective address.
253	* @param pVCpu The cross context virtual CPU structure of the calling thread.
254	* @param bRm The ModRM byte.
255	* @param u16Disp The displacement byte/word, if any.
256	* RIP relative addressing.
257	*/
258	static RTGCPTR iemOpHlpCalcRmEffAddrThreadedAddr16(PVMCPUCC pVCpu, uint8_t bRm, uint16_t u16Disp) RT_NOEXCEPT
259	{
260	Log5(("iemOpHlpCalcRmEffAddrThreadedAddr16: bRm=%#x\n", bRm));
261	Assert(!IEM_IS_64BIT_CODE(pVCpu));
262
263	/* Handle the disp16 form with no registers first. */
264	if ((bRm & (X86_MODRM_MOD_MASK \| X86_MODRM_RM_MASK)) == 6)
265	{
266	Log5(("iemOpHlpCalcRmEffAddrThreadedAddr16: EffAddr=%#010RGv\n", (RTGCPTR)u16Disp));
267	return u16Disp;
268	}
269
270	/* Get the displacment. */
271	/** @todo we can eliminate this step by making u16Disp have this value
272	* already! */
273	uint16_t u16EffAddr;
274	switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
275	{
276	case 0: u16EffAddr = 0; break;
277	case 1: u16EffAddr = (int16_t)(int8_t)u16Disp; break;
278	case 2: u16EffAddr = u16Disp; break;
279	default: AssertFailedStmt(u16EffAddr = 0);
280	}
281
282	/* Add the base and index registers to the disp. */
283	switch (bRm & X86_MODRM_RM_MASK)
284	{
285	case 0: u16EffAddr += pVCpu->cpum.GstCtx.bx + pVCpu->cpum.GstCtx.si; break;
286	case 1: u16EffAddr += pVCpu->cpum.GstCtx.bx + pVCpu->cpum.GstCtx.di; break;
287	case 2: u16EffAddr += pVCpu->cpum.GstCtx.bp + pVCpu->cpum.GstCtx.si; break;
288	case 3: u16EffAddr += pVCpu->cpum.GstCtx.bp + pVCpu->cpum.GstCtx.di; break;
289	case 4: u16EffAddr += pVCpu->cpum.GstCtx.si; break;
290	case 5: u16EffAddr += pVCpu->cpum.GstCtx.di; break;
291	case 6: u16EffAddr += pVCpu->cpum.GstCtx.bp; break;
292	case 7: u16EffAddr += pVCpu->cpum.GstCtx.bx; break;
293	}
294
295	Log5(("iemOpHlpCalcRmEffAddrThreadedAddr16: EffAddr=%#010RGv\n", (RTGCPTR)u16EffAddr));
296	return u16EffAddr;
297	}
298
299
300	/**
301	* Calculates the effective address of a ModR/M memory operand, 32-bit
302	* addressing variant.
303	*
304	* Meant to be used via IEM_MC_CALC_RM_EFF_ADDR_THREADED_ADDR32 and
305	* IEM_MC_CALC_RM_EFF_ADDR_THREADED_ADDR32FLAT.
306	*
307	* @returns The effective address.
308	* @param pVCpu The cross context virtual CPU structure of the calling thread.
309	* @param bRm The ModRM byte.
310	* @param bSib The SIB byte, if any.
311	* @param u32Disp The displacement byte/dword, if any.
312	*/
313	static RTGCPTR iemOpHlpCalcRmEffAddrThreadedAddr32(PVMCPUCC pVCpu, uint8_t bRm, uint8_t bSib, uint32_t u32Disp) RT_NOEXCEPT
314	{
315	Log5(("iemOpHlpCalcRmEffAddrThreadedAddr32: bRm=%#x\n", bRm));
316
317	/* Handle the disp32 form with no registers first. */
318	if ((bRm & (X86_MODRM_MOD_MASK \| X86_MODRM_RM_MASK)) == 5)
319	{
320	Log5(("iemOpHlpCalcRmEffAddrThreadedAddr32: EffAddr=%#010RGv\n", (RTGCPTR)u32Disp));
321	return u32Disp;
322	}
323
324	/* Get the register (or SIB) value. */
325	uint32_t u32EffAddr;
326	#ifdef _MSC_VER
327	u32EffAddr = 0;/* MSC uninitialized variable analysis is too simple, it seems. */
328	#endif
329	switch (bRm & X86_MODRM_RM_MASK)
330	{
331	case 0: u32EffAddr = pVCpu->cpum.GstCtx.eax; break;
332	case 1: u32EffAddr = pVCpu->cpum.GstCtx.ecx; break;
333	case 2: u32EffAddr = pVCpu->cpum.GstCtx.edx; break;
334	case 3: u32EffAddr = pVCpu->cpum.GstCtx.ebx; break;
335	case 4: /* SIB */
336	{
337	/* Get the index and scale it. */
338	switch ((bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK)
339	{
340	case 0: u32EffAddr = pVCpu->cpum.GstCtx.eax; break;
341	case 1: u32EffAddr = pVCpu->cpum.GstCtx.ecx; break;
342	case 2: u32EffAddr = pVCpu->cpum.GstCtx.edx; break;
343	case 3: u32EffAddr = pVCpu->cpum.GstCtx.ebx; break;
344	case 4: u32EffAddr = 0; /none / break;
345	case 5: u32EffAddr = pVCpu->cpum.GstCtx.ebp; break;
346	case 6: u32EffAddr = pVCpu->cpum.GstCtx.esi; break;
347	case 7: u32EffAddr = pVCpu->cpum.GstCtx.edi; break;
348	}
349	u32EffAddr <<= (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
350
351	/* add base */
352	switch (bSib & X86_SIB_BASE_MASK)
353	{
354	case 0: u32EffAddr += pVCpu->cpum.GstCtx.eax; break;
355	case 1: u32EffAddr += pVCpu->cpum.GstCtx.ecx; break;
356	case 2: u32EffAddr += pVCpu->cpum.GstCtx.edx; break;
357	case 3: u32EffAddr += pVCpu->cpum.GstCtx.ebx; break;
358	case 4: u32EffAddr += pVCpu->cpum.GstCtx.esp; break;
359	case 5:
360	if ((bRm & X86_MODRM_MOD_MASK) != 0)
361	u32EffAddr += pVCpu->cpum.GstCtx.ebp;
362	else
363	u32EffAddr += u32Disp;
364	break;
365	case 6: u32EffAddr += pVCpu->cpum.GstCtx.esi; break;
366	case 7: u32EffAddr += pVCpu->cpum.GstCtx.edi; break;
367	}
368	break;
369	}
370	case 5: u32EffAddr = pVCpu->cpum.GstCtx.ebp; break;
371	case 6: u32EffAddr = pVCpu->cpum.GstCtx.esi; break;
372	case 7: u32EffAddr = pVCpu->cpum.GstCtx.edi; break;
373	}
374
375	/* Get and add the displacement. */
376	switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
377	{
378	case 0: break;
379	case 1: u32EffAddr += (int8_t)u32Disp; break;
380	case 2: u32EffAddr += u32Disp; break;
381	default: AssertFailed();
382	}
383
384	Log5(("iemOpHlpCalcRmEffAddrThreadedAddr32: EffAddr=%#010RGv\n", (RTGCPTR)u32EffAddr));
385	return u32EffAddr;
386	}
387
388
389	/**
390	* Calculates the effective address of a ModR/M memory operand.
391	*
392	* Meant to be used via IEM_MC_CALC_RM_EFF_ADDR_THREADED_ADDR64.
393	*
394	* @returns The effective address.
395	* @param pVCpu The cross context virtual CPU structure of the calling thread.
396	* @param bRmEx The ModRM byte but with bit 3 set to REX.B and
397	* bit 4 to REX.X. The two bits are part of the
398	* REG sub-field, which isn't needed in this
399	* function.
400	* @param bSib The SIB byte, if any.
401	* @param u32Disp The displacement byte/word/dword, if any.
402	* @param cbInstr The size of the fully decoded instruction. Used
403	* for RIP relative addressing.
404	* @todo combine cbInstr and cbImm!
405	*/
406	static RTGCPTR iemOpHlpCalcRmEffAddrThreadedAddr64(PVMCPUCC pVCpu, uint8_t bRmEx, uint8_t bSib,
407	uint32_t u32Disp, uint8_t cbInstr) RT_NOEXCEPT
408	{
409	Log5(("iemOpHlpCalcRmEffAddrThreadedAddr64: bRmEx=%#x\n", bRmEx));
410	Assert(IEM_IS_64BIT_CODE(pVCpu));
411
412	uint64_t u64EffAddr;
413
414	/* Handle the rip+disp32 form with no registers first. */
415	if ((bRmEx & (X86_MODRM_MOD_MASK \| X86_MODRM_RM_MASK)) == 5)
416	{
417	u64EffAddr = (int32_t)u32Disp;
418	u64EffAddr += pVCpu->cpum.GstCtx.rip + cbInstr;
419	}
420	else
421	{
422	/* Get the register (or SIB) value. */
423	#ifdef _MSC_VER
424	u64EffAddr = 0; /* MSC uninitialized variable analysis is too simple, it seems. */
425	#endif
426	switch (bRmEx & (X86_MODRM_RM_MASK \| 0x8)) /* bRmEx[bit 3] = REX.B */
427	{
428	default:
429	case 0: u64EffAddr = pVCpu->cpum.GstCtx.rax; break;
430	case 1: u64EffAddr = pVCpu->cpum.GstCtx.rcx; break;
431	case 2: u64EffAddr = pVCpu->cpum.GstCtx.rdx; break;
432	case 3: u64EffAddr = pVCpu->cpum.GstCtx.rbx; break;
433	case 5: u64EffAddr = pVCpu->cpum.GstCtx.rbp; break;
434	case 6: u64EffAddr = pVCpu->cpum.GstCtx.rsi; break;
435	case 7: u64EffAddr = pVCpu->cpum.GstCtx.rdi; break;
436	case 8: u64EffAddr = pVCpu->cpum.GstCtx.r8; break;
437	case 9: u64EffAddr = pVCpu->cpum.GstCtx.r9; break;
438	case 10: u64EffAddr = pVCpu->cpum.GstCtx.r10; break;
439	case 11: u64EffAddr = pVCpu->cpum.GstCtx.r11; break;
440	case 13: u64EffAddr = pVCpu->cpum.GstCtx.r13; break;
441	case 14: u64EffAddr = pVCpu->cpum.GstCtx.r14; break;
442	case 15: u64EffAddr = pVCpu->cpum.GstCtx.r15; break;
443	/* SIB */
444	case 4:
445	case 12:
446	{
447	/* Get the index and scale it. */
448	switch (((bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK) \| ((bRmEx & 0x10) >> 1)) /* bRmEx[bit 4] = REX.X */
449	{
450	case 0: u64EffAddr = pVCpu->cpum.GstCtx.rax; break;
451	case 1: u64EffAddr = pVCpu->cpum.GstCtx.rcx; break;
452	case 2: u64EffAddr = pVCpu->cpum.GstCtx.rdx; break;
453	case 3: u64EffAddr = pVCpu->cpum.GstCtx.rbx; break;
454	case 4: u64EffAddr = 0; /none / break;
455	case 5: u64EffAddr = pVCpu->cpum.GstCtx.rbp; break;
456	case 6: u64EffAddr = pVCpu->cpum.GstCtx.rsi; break;
457	case 7: u64EffAddr = pVCpu->cpum.GstCtx.rdi; break;
458	case 8: u64EffAddr = pVCpu->cpum.GstCtx.r8; break;
459	case 9: u64EffAddr = pVCpu->cpum.GstCtx.r9; break;
460	case 10: u64EffAddr = pVCpu->cpum.GstCtx.r10; break;
461	case 11: u64EffAddr = pVCpu->cpum.GstCtx.r11; break;
462	case 12: u64EffAddr = pVCpu->cpum.GstCtx.r12; break;
463	case 13: u64EffAddr = pVCpu->cpum.GstCtx.r13; break;
464	case 14: u64EffAddr = pVCpu->cpum.GstCtx.r14; break;
465	case 15: u64EffAddr = pVCpu->cpum.GstCtx.r15; break;
466	}
467	u64EffAddr <<= (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
468
469	/* add base */
470	switch ((bSib & X86_SIB_BASE_MASK) \| (bRmEx & 0x8)) /* bRmEx[bit 3] = REX.B */
471	{
472	case 0: u64EffAddr += pVCpu->cpum.GstCtx.rax; break;
473	case 1: u64EffAddr += pVCpu->cpum.GstCtx.rcx; break;
474	case 2: u64EffAddr += pVCpu->cpum.GstCtx.rdx; break;
475	case 3: u64EffAddr += pVCpu->cpum.GstCtx.rbx; break;
476	case 4: u64EffAddr += pVCpu->cpum.GstCtx.rsp; break;
477	case 6: u64EffAddr += pVCpu->cpum.GstCtx.rsi; break;
478	case 7: u64EffAddr += pVCpu->cpum.GstCtx.rdi; break;
479	case 8: u64EffAddr += pVCpu->cpum.GstCtx.r8; break;
480	case 9: u64EffAddr += pVCpu->cpum.GstCtx.r9; break;
481	case 10: u64EffAddr += pVCpu->cpum.GstCtx.r10; break;
482	case 11: u64EffAddr += pVCpu->cpum.GstCtx.r11; break;
483	case 12: u64EffAddr += pVCpu->cpum.GstCtx.r12; break;
484	case 14: u64EffAddr += pVCpu->cpum.GstCtx.r14; break;
485	case 15: u64EffAddr += pVCpu->cpum.GstCtx.r15; break;
486	/* complicated encodings */
487	case 5:
488	if ((bRmEx & X86_MODRM_MOD_MASK) != 0)
489	u64EffAddr += pVCpu->cpum.GstCtx.rbp;
490	else
491	u64EffAddr += (int32_t)u32Disp;
492	break;
493	case 13:
494	if ((bRmEx & X86_MODRM_MOD_MASK) != 0)
495	u64EffAddr += pVCpu->cpum.GstCtx.r13;
496	else
497	u64EffAddr += (int32_t)u32Disp;
498	break;
499	}
500	break;
501	}
502	}
503
504	/* Get and add the displacement. */
505	switch ((bRmEx >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
506	{
507	case 0: break;
508	case 1: u64EffAddr += (int8_t)u32Disp; break;
509	case 2: u64EffAddr += (int32_t)u32Disp; break;
510	default: AssertFailed();
511	}
512	}
513
514	Log5(("iemOpHlpCalcRmEffAddrThreadedAddr64: EffAddr=%#010RGv\n", u64EffAddr));
515	return u64EffAddr;
516	}
517
518
519
520	/*
521	* The threaded functions.
522	*/
523	#include "IEMThreadedFunctions.cpp.h"
524

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source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllThreadedFunctions.cpp@ 100089

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