IEMAllThreadedFunctions.cpp@ 99748

Last change on this file since 99748 was 99301, checked in by vboxsync, 21 months ago
VMM/IEM: IEMThreadedFunctions.cpp -> IEMAllThreadedFunctions.cpp. bugref:10369
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1	/* $Id: IEMAllThreadedFunctions.cpp 99301 2023-04-06 00:09:21Z vboxsync $ */
2	/** @file
3	* IEM - Instruction Decoding and Emulation, Threaded Functions.
4	*/
5
6	/*
7	* Copyright (C) 2011-2023 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28
29	/*********************************************************************************************************************************
30	* Header Files *
31	*********************************************************************************************************************************/
32	#ifndef LOG_GROUP /* defined when included by tstIEMCheckMc.cpp */
33	# define LOG_GROUP LOG_GROUP_IEM
34	#endif
35	#define VMCPU_INCL_CPUM_GST_CTX
36	#define IEM_WITH_OPAQUE_DECODER_STATE
37	#include <VBox/vmm/iem.h>
38	#include <VBox/vmm/cpum.h>
39	#include <VBox/vmm/apic.h>
40	#include <VBox/vmm/pdm.h>
41	#include <VBox/vmm/pgm.h>
42	#include <VBox/vmm/iom.h>
43	#include <VBox/vmm/em.h>
44	#include <VBox/vmm/hm.h>
45	#include <VBox/vmm/nem.h>
46	#include <VBox/vmm/gim.h>
47	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
48	# include <VBox/vmm/em.h>
49	# include <VBox/vmm/hm_svm.h>
50	#endif
51	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
52	# include <VBox/vmm/hmvmxinline.h>
53	#endif
54	#include <VBox/vmm/tm.h>
55	#include <VBox/vmm/dbgf.h>
56	#include <VBox/vmm/dbgftrace.h>
57	#include "IEMInternal.h"
58	#include <VBox/vmm/vmcc.h>
59	#include <VBox/log.h>
60	#include <VBox/err.h>
61	#include <VBox/param.h>
62	#include <VBox/dis.h>
63	#include <VBox/disopcode-x86-amd64.h>
64	#include <iprt/asm-math.h>
65	#include <iprt/assert.h>
66	#include <iprt/string.h>
67	#include <iprt/x86.h>
68
69	#include "IEMInline.h"
70	#include "IEMMc.h"
71
72	#include "IEMThreadedFunctions.h"
73
74
75	/*********************************************************************************************************************************
76	* Defined Constants And Macros *
77	*********************************************************************************************************************************/
78
79	/** Variant of IEM_MC_ADVANCE_RIP_AND_FINISH with instruction length as param. */
80	#define IEM_MC_ADVANCE_RIP_AND_FINISH_THREADED(a_cbInstr) \
81	return iemRegAddToRipAndFinishingClearingRF(pVCpu, a_cbInstr)
82	#undef IEM_MC_ADVANCE_RIP_AND_FINISH
83
84	/** Variant of IEM_MC_ADVANCE_RIP_AND_FINISH with instruction length as param
85	* and only used when we're in 64-bit code. */
86	#define IEM_MC_ADVANCE_RIP_AND_FINISH_THREADED_LM64(a_cbInstr) \
87	return iemRegAddToRip64AndFinishingClearingRF(pVCpu, a_cbInstr)
88	#undef IEM_MC_ADVANCE_RIP_AND_FINISH
89
90	/** Variant of IEM_MC_ADVANCE_RIP_AND_FINISH with instruction length as param
91	* and never used in 64-bit code. */
92	#define IEM_MC_ADVANCE_RIP_AND_FINISH_THREADED_NOT64(a_cbInstr) \
93	return iemRegAddToEip32AndFinishingClearingRF(pVCpu, a_cbInstr)
94	#undef IEM_MC_ADVANCE_RIP_AND_FINISH
95
96	/** Variant of IEM_MC_REL_JMP_S8_AND_FINISH with instruction length as param. */
97	#define IEM_MC_REL_JMP_S8_AND_FINISH_THREADED(a_i8, a_cbInstr, a_enmEffOpSize) \
98	return iemRegRipRelativeJumpS8AndFinishClearingRF(pVCpu, a_cbInstr, (a_i8), a_enmEffOpSize)
99	#undef IEM_MC_REL_JMP_S8_AND_FINISH
100
101	/** Variant of IEM_MC_REL_JMP_S16_AND_FINISH with instruction length as param. */
102	#define IEM_MC_REL_JMP_S16_AND_FINISH_THREADED(a_i16, a_cbInstr) \
103	return iemRegRipRelativeJumpS16AndFinishClearingRF(pVCpu, a_cbInstr, (a_i16))
104	#undef IEM_MC_REL_JMP_S16_AND_FINISH
105
106	/** Variant of IEM_MC_REL_JMP_S32_AND_FINISH with instruction length as param. */
107	#define IEM_MC_REL_JMP_S32_AND_FINISH_THREADED(a_i32, a_cbInstr, a_enmEffOpSize) \
108	return iemRegRipRelativeJumpS32AndFinishClearingRF(pVCpu, a_cbInstr, (a_i32), a_enmEffOpSize)
109	#undef IEM_MC_REL_JMP_S32_AND_FINISH
110
111	/** Variant of IEM_MC_CALC_RM_EFF_ADDR with additional parameters. */
112	#define IEM_MC_CALC_RM_EFF_ADDR_THREADED_ADDR16(a_GCPtrEff, a_bRm, a_u16Disp) \
113	(a_GCPtrEff) = iemOpHlpCalcRmEffAddrThreadedAddr16(pVCpu, a_bRm, a_u16Disp)
114	#undef IEM_MC_CALC_RM_EFF_ADDR
115
116	/** Variant of IEM_MC_CALC_RM_EFF_ADDR with additional parameters. */
117	#define IEM_MC_CALC_RM_EFF_ADDR_THREADED_ADDR32(a_GCPtrEff, a_bRm, a_bSib, a_u32Disp) \
118	(a_GCPtrEff) = iemOpHlpCalcRmEffAddrThreadedAddr32(pVCpu, a_bRm, a_bSib, a_u32Disp)
119	#undef IEM_MC_CALC_RM_EFF_ADDR
120
121	/** Variant of IEM_MC_CALC_RM_EFF_ADDR with additional parameters. */
122	#define IEM_MC_CALC_RM_EFF_ADDR_THREADED_ADDR32FLAT(a_GCPtrEff, a_bRm, a_bSib, a_u32Disp) \
123	(a_GCPtrEff) = iemOpHlpCalcRmEffAddrThreadedAddr32(pVCpu, a_bRm, a_bSib, a_u32Disp)
124	#undef IEM_MC_CALC_RM_EFF_ADDR
125
126	/** Variant of IEM_MC_CALC_RM_EFF_ADDR with additional parameters. */
127	#define IEM_MC_CALC_RM_EFF_ADDR_THREADED_ADDR64(a_GCPtrEff, a_bRmEx, a_bSib, a_u32Disp, a_cbImm) \
128	(a_GCPtrEff) = iemOpHlpCalcRmEffAddrThreadedAddr64(pVCpu, a_bRmEx, a_bSib, a_u32Disp, a_cbImm)
129	#undef IEM_MC_CALC_RM_EFF_ADDR
130
131	/** Variant of IEM_MC_CALC_RM_EFF_ADDR with additional parameters. */
132	#define IEM_MC_CALC_RM_EFF_ADDR_THREADED_ADDR6432(a_GCPtrEff, a_bRmEx, a_bSib, a_u32Disp, a_cbImm) \
133	(a_GCPtrEff) = (uint32_t)iemOpHlpCalcRmEffAddrThreadedAddr64(pVCpu, a_bRmEx, a_bSib, a_u32Disp, a_cbImm)
134	#undef IEM_MC_CALC_RM_EFF_ADDR
135
136	/** Variant of IEM_MC_CALL_CIMPL_1 with explicit instruction length parameter. */
137	#define IEM_MC_CALL_CIMPL_1_THREADED(a_cbInstr, a_pfnCImpl, a0) \
138	return (a_pfnCImpl)(pVCpu, (a_cbInstr), a0)
139	#undef IEM_MC_CALL_CIMPL_1
140
141	/** Variant of IEM_MC_CALL_CIMPL_2 with explicit instruction length parameter. */
142	#define IEM_MC_CALL_CIMPL_2_THREADED(a_cbInstr, a_pfnCImpl, a0, a1) \
143	return (a_pfnCImpl)(pVCpu, (a_cbInstr), a0, a1)
144	#undef IEM_MC_CALL_CIMPL_2
145
146	/** Variant of IEM_MC_CALL_CIMPL_3 with explicit instruction length parameter. */
147	#define IEM_MC_CALL_CIMPL_3_THREADED(a_cbInstr, a_pfnCImpl, a0, a1, a2) \
148	return (a_pfnCImpl)(pVCpu, (a_cbInstr), a0, a1, a2)
149	#undef IEM_MC_CALL_CIMPL_3
150
151	/** Variant of IEM_MC_CALL_CIMPL_4 with explicit instruction length parameter. */
152	#define IEM_MC_CALL_CIMPL_4_THREADED(a_cbInstr, a_pfnCImpl, a0, a1, a2, a3) \
153	return (a_pfnCImpl)(pVCpu, (a_cbInstr), a0, a1, a2, a3)
154	#undef IEM_MC_CALL_CIMPL_4
155
156	/** Variant of IEM_MC_CALL_CIMPL_5 with explicit instruction length parameter. */
157	#define IEM_MC_CALL_CIMPL_5_THREADED(a_cbInstr, a_pfnCImpl, a0, a1, a2, a3, a4) \
158	return (a_pfnCImpl)(pVCpu, (a_cbInstr), a0, a1, a2, a3, a4)
159	#undef IEM_MC_CALL_CIMPL_5
160
161	/** Variant of IEM_MC_FETCH_GREG_U8 with extended (20) register index. */
162	#define IEM_MC_FETCH_GREG_U8_THREADED(a_u8Dst, a_iGRegEx) \
163	(a_u8Dst) = iemGRegFetchU8Ex(pVCpu, (a_iGRegEx))
164
165	/** Variant of IEM_MC_FETCH_GREG_U8_ZX_U16 with extended (20) register index. */
166	#define IEM_MC_FETCH_GREG_U8_ZX_U16_THREADED(a_u16Dst, a_iGRegEx) \
167	(a_u16Dst) = iemGRegFetchU8Ex(pVCpu, (a_iGRegEx))
168
169	/** Variant of IEM_MC_FETCH_GREG_U8_ZX_U32 with extended (20) register index. */
170	#define IEM_MC_FETCH_GREG_U8_ZX_U32_THREADED(a_u32Dst, a_iGRegEx) \
171	(a_u32Dst) = iemGRegFetchU8Ex(pVCpu, (a_iGRegEx))
172
173	/** Variant of IEM_MC_FETCH_GREG_U8_ZX_U64 with extended (20) register index. */
174	#define IEM_MC_FETCH_GREG_U8_ZX_U64_THREADED(a_u64Dst, a_iGRegEx) \
175	(a_u64Dst) = iemGRegFetchU8Ex(pVCpu, (a_iGRegEx))
176
177	/** Variant of IEM_MC_FETCH_GREG_U8_SX_U16 with extended (20) register index. */
178	#define IEM_MC_FETCH_GREG_U8_SX_U16_THREADED(a_u16Dst, a_iGRegEx) \
179	(a_u16Dst) = (int8_t)iemGRegFetchU8Ex(pVCpu, (a_iGRegEx))
180
181	/** Variant of IEM_MC_FETCH_GREG_U8_SX_U32 with extended (20) register index. */
182	#define IEM_MC_FETCH_GREG_U8_SX_U32_THREADED(a_u32Dst, a_iGRegEx) \
183	(a_u32Dst) = (int8_t)iemGRegFetchU8Ex(pVCpu, (a_iGRegEx))
184	#undef IEM_MC_FETCH_GREG_U8_SX_U32
185
186	/** Variant of IEM_MC_FETCH_GREG_U8_SX_U64 with extended (20) register index. */
187	#define IEM_MC_FETCH_GREG_U8_SX_U64_THREADED(a_u64Dst, a_iGRegEx) \
188	(a_u64Dst) = (int8_t)iemGRegFetchU8Ex(pVCpu, (a_iGRegEx))
189	#undef IEM_MC_FETCH_GREG_U8_SX_U64
190
191	/** Variant of IEM_MC_STORE_GREG_U8 with extended (20) register index. */
192	#define IEM_MC_STORE_GREG_U8_THREADED(a_iGRegEx, a_u8Value) \
193	*iemGRegRefU8Ex(pVCpu, (a_iGRegEx)) = (a_u8Value)
194	#undef IEM_MC_STORE_GREG_U8
195
196	/** Variant of IEM_MC_STORE_GREG_U8 with extended (20) register index. */
197	#define IEM_MC_STORE_GREG_U8_CONST_THREADED(a_iGRegEx, a_u8Value) \
198	*iemGRegRefU8Ex(pVCpu, (a_iGRegEx)) = (a_u8Value)
199	#undef IEM_MC_STORE_GREG_U8
200
201	/** Variant of IEM_MC_REF_GREG_U8 with extended (20) register index. */
202	#define IEM_MC_REF_GREG_U8_THREADED(a_pu8Dst, a_iGRegEx) \
203	(a_pu8Dst) = iemGRegRefU8Ex(pVCpu, (a_iGRegEx))
204	#undef IEM_MC_REF_GREG_U8
205
206	/** Variant of IEM_MC_ADD_GREG_U8 with extended (20) register index. */
207	#define IEM_MC_ADD_GREG_U8_THREADED(a_iGRegEx, a_u8Value) \
208	*iemGRegRefU8Ex(pVCpu, (a_iGRegEx)) += (a_u8Value)
209	#undef IEM_MC_ADD_GREG_U8
210
211	/** Variant of IEM_MC_SUB_GREG_U8 with extended (20) register index. */
212	#define IEM_MC_SUB_GREG_U8_THREADED(a_iGRegEx, a_u8Value) \
213	*iemGRegRefU8Ex(pVCpu, (a_iGRegEx)) -= (a_u8Value)
214	#undef IEM_MC_SUB_GREG_U8
215
216	/** Variant of IEM_MC_ADD_GREG_U8_TO_LOCAL with extended (20) register index. */
217	#define IEM_MC_ADD_GREG_U8_TO_LOCAL_THREADED(a_u8Value, a_iGRegEx) \
218	do { (a_u8Value) += iemGRegFetchU8Ex(pVCpu, (a_iGRegEx)); } while (0)
219	#undef IEM_MC_ADD_GREG_U8_TO_LOCAL
220
221	/** Variant of IEM_MC_AND_GREG_U8 with extended (20) register index. */
222	#define IEM_MC_AND_GREG_U8_THREADED(a_iGRegEx, a_u8Value) \
223	*iemGRegRefU8Ex(pVCpu, (a_iGRegEx)) &= (a_u8Value)
224	#undef IEM_MC_AND_GREG_U8
225
226	/** Variant of IEM_MC_OR_GREG_U8 with extended (20) register index. */
227	#define IEM_MC_OR_GREG_U8_THREADED(a_iGRegEx, a_u8Value) \
228	*iemGRegRefU8Ex(pVCpu, (a_iGRegEx)) \|= (a_u8Value)
229	#undef IEM_MC_OR_GREG_U8
230
231	/**
232	* Calculates the effective address of a ModR/M memory operand, 16-bit
233	* addressing variant.
234	*
235	* Meant to be used via IEM_MC_CALC_RM_EFF_ADDR_THREADED_ADDR16.
236	*
237	* @returns The effective address.
238	* @param pVCpu The cross context virtual CPU structure of the calling thread.
239	* @param bRm The ModRM byte.
240	* @param u16Disp The displacement byte/word, if any.
241	* RIP relative addressing.
242	*/
243	static RTGCPTR iemOpHlpCalcRmEffAddrThreadedAddr16(PVMCPUCC pVCpu, uint8_t bRm, uint16_t u16Disp) RT_NOEXCEPT
244	{
245	Log5(("iemOpHlpCalcRmEffAddrThreadedAddr16: bRm=%#x\n", bRm));
246	Assert(pVCpu->iem.s.enmCpuMode != IEMMODE_64BIT);
247
248	/* Handle the disp16 form with no registers first. */
249	if ((bRm & (X86_MODRM_MOD_MASK \| X86_MODRM_RM_MASK)) == 6)
250	{
251	Log5(("iemOpHlpCalcRmEffAddrThreadedAddr16: EffAddr=%#010RGv\n", (RTGCPTR)u16Disp));
252	return u16Disp;
253	}
254
255	/* Get the displacment. */
256	/** @todo we can eliminate this step by making u16Disp have this value
257	* already! */
258	uint16_t u16EffAddr;
259	switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
260	{
261	case 0: u16EffAddr = 0; break;
262	case 1: u16EffAddr = (int16_t)(int8_t)u16Disp; break;
263	case 2: u16EffAddr = u16Disp; break;
264	default: AssertFailedStmt(u16EffAddr = 0);
265	}
266
267	/* Add the base and index registers to the disp. */
268	switch (bRm & X86_MODRM_RM_MASK)
269	{
270	case 0: u16EffAddr += pVCpu->cpum.GstCtx.bx + pVCpu->cpum.GstCtx.si; break;
271	case 1: u16EffAddr += pVCpu->cpum.GstCtx.bx + pVCpu->cpum.GstCtx.di; break;
272	case 2: u16EffAddr += pVCpu->cpum.GstCtx.bp + pVCpu->cpum.GstCtx.si; break;
273	case 3: u16EffAddr += pVCpu->cpum.GstCtx.bp + pVCpu->cpum.GstCtx.di; break;
274	case 4: u16EffAddr += pVCpu->cpum.GstCtx.si; break;
275	case 5: u16EffAddr += pVCpu->cpum.GstCtx.di; break;
276	case 6: u16EffAddr += pVCpu->cpum.GstCtx.bp; break;
277	case 7: u16EffAddr += pVCpu->cpum.GstCtx.bx; break;
278	}
279
280	Log5(("iemOpHlpCalcRmEffAddrThreadedAddr16: EffAddr=%#010RGv\n", (RTGCPTR)u16EffAddr));
281	return u16EffAddr;
282	}
283
284
285	/**
286	* Calculates the effective address of a ModR/M memory operand, 32-bit
287	* addressing variant.
288	*
289	* Meant to be used via IEM_MC_CALC_RM_EFF_ADDR_THREADED_ADDR32 and
290	* IEM_MC_CALC_RM_EFF_ADDR_THREADED_ADDR32FLAT.
291	*
292	* @returns The effective address.
293	* @param pVCpu The cross context virtual CPU structure of the calling thread.
294	* @param bRm The ModRM byte.
295	* @param bSib The SIB byte, if any.
296	* @param u32Disp The displacement byte/dword, if any.
297	*/
298	static RTGCPTR iemOpHlpCalcRmEffAddrThreadedAddr32(PVMCPUCC pVCpu, uint8_t bRm, uint8_t bSib, uint32_t u32Disp) RT_NOEXCEPT
299	{
300	Log5(("iemOpHlpCalcRmEffAddrThreadedAddr32: bRm=%#x\n", bRm));
301	Assert(pVCpu->iem.s.enmCpuMode != IEMMODE_64BIT);
302
303	/* Handle the disp32 form with no registers first. */
304	if ((bRm & (X86_MODRM_MOD_MASK \| X86_MODRM_RM_MASK)) == 5)
305	{
306	Log5(("iemOpHlpCalcRmEffAddrThreadedAddr32: EffAddr=%#010RGv\n", (RTGCPTR)u32Disp));
307	return u32Disp;
308	}
309
310	/* Get the register (or SIB) value. */
311	uint32_t u32EffAddr;
312	#ifdef _MSC_VER
313	u32EffAddr = 0;/* MSC uninitialized variable analysis is too simple, it seems. */
314	#endif
315	switch (bRm & X86_MODRM_RM_MASK)
316	{
317	case 0: u32EffAddr = pVCpu->cpum.GstCtx.eax; break;
318	case 1: u32EffAddr = pVCpu->cpum.GstCtx.ecx; break;
319	case 2: u32EffAddr = pVCpu->cpum.GstCtx.edx; break;
320	case 3: u32EffAddr = pVCpu->cpum.GstCtx.ebx; break;
321	case 4: /* SIB */
322	{
323	/* Get the index and scale it. */
324	switch ((bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK)
325	{
326	case 0: u32EffAddr = pVCpu->cpum.GstCtx.eax; break;
327	case 1: u32EffAddr = pVCpu->cpum.GstCtx.ecx; break;
328	case 2: u32EffAddr = pVCpu->cpum.GstCtx.edx; break;
329	case 3: u32EffAddr = pVCpu->cpum.GstCtx.ebx; break;
330	case 4: u32EffAddr = 0; /none / break;
331	case 5: u32EffAddr = pVCpu->cpum.GstCtx.ebp; break;
332	case 6: u32EffAddr = pVCpu->cpum.GstCtx.esi; break;
333	case 7: u32EffAddr = pVCpu->cpum.GstCtx.edi; break;
334	}
335	u32EffAddr <<= (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
336
337	/* add base */
338	switch (bSib & X86_SIB_BASE_MASK)
339	{
340	case 0: u32EffAddr += pVCpu->cpum.GstCtx.eax; break;
341	case 1: u32EffAddr += pVCpu->cpum.GstCtx.ecx; break;
342	case 2: u32EffAddr += pVCpu->cpum.GstCtx.edx; break;
343	case 3: u32EffAddr += pVCpu->cpum.GstCtx.ebx; break;
344	case 4: u32EffAddr += pVCpu->cpum.GstCtx.esp; break;
345	case 5:
346	if ((bRm & X86_MODRM_MOD_MASK) != 0)
347	u32EffAddr += pVCpu->cpum.GstCtx.ebp;
348	else
349	u32EffAddr += u32Disp;
350	break;
351	case 6: u32EffAddr += pVCpu->cpum.GstCtx.esi; break;
352	case 7: u32EffAddr += pVCpu->cpum.GstCtx.edi; break;
353	}
354	break;
355	}
356	case 5: u32EffAddr = pVCpu->cpum.GstCtx.ebp; break;
357	case 6: u32EffAddr = pVCpu->cpum.GstCtx.esi; break;
358	case 7: u32EffAddr = pVCpu->cpum.GstCtx.edi; break;
359	}
360
361	/* Get and add the displacement. */
362	switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
363	{
364	case 0: break;
365	case 1: u32EffAddr += (int8_t)u32Disp; break;
366	case 2: u32EffAddr += u32Disp; break;
367	default: AssertFailed();
368	}
369
370	Log5(("iemOpHlpCalcRmEffAddrThreadedAddr32: EffAddr=%#010RGv\n", (RTGCPTR)u32EffAddr));
371	return u32EffAddr;
372	}
373
374
375	/**
376	* Calculates the effective address of a ModR/M memory operand.
377	*
378	* Meant to be used via IEM_MC_CALC_RM_EFF_ADDR_THREADED_ADDR64.
379	*
380	* @returns The effective address.
381	* @param pVCpu The cross context virtual CPU structure of the calling thread.
382	* @param bRmEx The ModRM byte but with bit 3 set to REX.B and
383	* bit 4 to REX.X. The two bits are part of the
384	* REG sub-field, which isn't needed in this
385	* function.
386	* @param bSib The SIB byte, if any.
387	* @param u32Disp The displacement byte/word/dword, if any.
388	* @param cbInstr The size of the fully decoded instruction. Used
389	* for RIP relative addressing.
390	* @todo combine cbInstr and cbImm!
391	*/
392	static RTGCPTR iemOpHlpCalcRmEffAddrThreadedAddr64(PVMCPUCC pVCpu, uint8_t bRmEx, uint8_t bSib,
393	uint32_t u32Disp, uint8_t cbInstr) RT_NOEXCEPT
394	{
395	Log5(("iemOpHlpCalcRmEffAddrThreadedAddr64: bRmEx=%#x\n", bRmEx));
396	Assert(pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT);
397
398	uint64_t u64EffAddr;
399
400	/* Handle the rip+disp32 form with no registers first. */
401	if ((bRmEx & (X86_MODRM_MOD_MASK \| X86_MODRM_RM_MASK)) == 5)
402	{
403	u64EffAddr = (int32_t)u32Disp;
404	u64EffAddr += pVCpu->cpum.GstCtx.rip + cbInstr;
405	}
406	else
407	{
408	/* Get the register (or SIB) value. */
409	#ifdef _MSC_VER
410	u64EffAddr = 0; /* MSC uninitialized variable analysis is too simple, it seems. */
411	#endif
412	switch (bRmEx & (X86_MODRM_RM_MASK \| 0x8)) /* bRmEx[bit 3] = REX.B */
413	{
414	default:
415	case 0: u64EffAddr = pVCpu->cpum.GstCtx.rax; break;
416	case 1: u64EffAddr = pVCpu->cpum.GstCtx.rcx; break;
417	case 2: u64EffAddr = pVCpu->cpum.GstCtx.rdx; break;
418	case 3: u64EffAddr = pVCpu->cpum.GstCtx.rbx; break;
419	case 5: u64EffAddr = pVCpu->cpum.GstCtx.rbp; break;
420	case 6: u64EffAddr = pVCpu->cpum.GstCtx.rsi; break;
421	case 7: u64EffAddr = pVCpu->cpum.GstCtx.rdi; break;
422	case 8: u64EffAddr = pVCpu->cpum.GstCtx.r8; break;
423	case 9: u64EffAddr = pVCpu->cpum.GstCtx.r9; break;
424	case 10: u64EffAddr = pVCpu->cpum.GstCtx.r10; break;
425	case 11: u64EffAddr = pVCpu->cpum.GstCtx.r11; break;
426	case 13: u64EffAddr = pVCpu->cpum.GstCtx.r13; break;
427	case 14: u64EffAddr = pVCpu->cpum.GstCtx.r14; break;
428	case 15: u64EffAddr = pVCpu->cpum.GstCtx.r15; break;
429	/* SIB */
430	case 4:
431	case 12:
432	{
433	/* Get the index and scale it. */
434	switch (((bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK) \| ((bRmEx & 0x10) >> 1)) /* bRmEx[bit 4] = REX.X */
435	{
436	case 0: u64EffAddr = pVCpu->cpum.GstCtx.rax; break;
437	case 1: u64EffAddr = pVCpu->cpum.GstCtx.rcx; break;
438	case 2: u64EffAddr = pVCpu->cpum.GstCtx.rdx; break;
439	case 3: u64EffAddr = pVCpu->cpum.GstCtx.rbx; break;
440	case 4: u64EffAddr = 0; /none / break;
441	case 5: u64EffAddr = pVCpu->cpum.GstCtx.rbp; break;
442	case 6: u64EffAddr = pVCpu->cpum.GstCtx.rsi; break;
443	case 7: u64EffAddr = pVCpu->cpum.GstCtx.rdi; break;
444	case 8: u64EffAddr = pVCpu->cpum.GstCtx.r8; break;
445	case 9: u64EffAddr = pVCpu->cpum.GstCtx.r9; break;
446	case 10: u64EffAddr = pVCpu->cpum.GstCtx.r10; break;
447	case 11: u64EffAddr = pVCpu->cpum.GstCtx.r11; break;
448	case 12: u64EffAddr = pVCpu->cpum.GstCtx.r12; break;
449	case 13: u64EffAddr = pVCpu->cpum.GstCtx.r13; break;
450	case 14: u64EffAddr = pVCpu->cpum.GstCtx.r14; break;
451	case 15: u64EffAddr = pVCpu->cpum.GstCtx.r15; break;
452	}
453	u64EffAddr <<= (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
454
455	/* add base */
456	switch ((bSib & X86_SIB_BASE_MASK) \| (bRmEx & 0x8)) /* bRmEx[bit 3] = REX.B */
457	{
458	case 0: u64EffAddr += pVCpu->cpum.GstCtx.rax; break;
459	case 1: u64EffAddr += pVCpu->cpum.GstCtx.rcx; break;
460	case 2: u64EffAddr += pVCpu->cpum.GstCtx.rdx; break;
461	case 3: u64EffAddr += pVCpu->cpum.GstCtx.rbx; break;
462	case 4: u64EffAddr += pVCpu->cpum.GstCtx.rsp; break;
463	case 6: u64EffAddr += pVCpu->cpum.GstCtx.rsi; break;
464	case 7: u64EffAddr += pVCpu->cpum.GstCtx.rdi; break;
465	case 8: u64EffAddr += pVCpu->cpum.GstCtx.r8; break;
466	case 9: u64EffAddr += pVCpu->cpum.GstCtx.r9; break;
467	case 10: u64EffAddr += pVCpu->cpum.GstCtx.r10; break;
468	case 11: u64EffAddr += pVCpu->cpum.GstCtx.r11; break;
469	case 12: u64EffAddr += pVCpu->cpum.GstCtx.r12; break;
470	case 14: u64EffAddr += pVCpu->cpum.GstCtx.r14; break;
471	case 15: u64EffAddr += pVCpu->cpum.GstCtx.r15; break;
472	/* complicated encodings */
473	case 5:
474	if ((bRmEx & X86_MODRM_MOD_MASK) != 0)
475	u64EffAddr += pVCpu->cpum.GstCtx.rbp;
476	else
477	u64EffAddr += (int32_t)u32Disp;
478	break;
479	case 13:
480	if ((bRmEx & X86_MODRM_MOD_MASK) != 0)
481	u64EffAddr += pVCpu->cpum.GstCtx.r13;
482	else
483	u64EffAddr += (int32_t)u32Disp;
484	break;
485	}
486	break;
487	}
488	}
489
490	/* Get and add the displacement. */
491	switch ((bRmEx >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
492	{
493	case 0: break;
494	case 1: u64EffAddr += (int8_t)u32Disp; break;
495	case 2: u64EffAddr += (int32_t)u32Disp; break;
496	default: AssertFailed();
497	}
498	}
499
500	Log5(("iemOpHlpCalcRmEffAddrThreadedAddr64: EffAddr=%#010RGv\n", u64EffAddr));
501	return u64EffAddr;
502	}
503
504
505
506	/*
507	* The threaded functions.
508	*/
509	#include "IEMThreadedFunctions.cpp.h"
510

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source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllThreadedFunctions.cpp@ 99748

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