IOMAllMMIO.cpp@ 20563

Last change on this file since 20563 was 20530, checked in by vboxsync, 16 years ago
VMM: remove DISCPUSTATE from the stack.
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1	/* $Id: IOMAllMMIO.cpp 20530 2009-06-13 20:53:44Z vboxsync $ */
2	/** @file
3	* IOM - Input / Output Monitor - Any Context, MMIO & String I/O.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_IOM
27	#include <VBox/iom.h>
28	#include <VBox/cpum.h>
29	#include <VBox/pgm.h>
30	#include <VBox/selm.h>
31	#include <VBox/mm.h>
32	#include <VBox/em.h>
33	#include <VBox/pgm.h>
34	#include <VBox/trpm.h>
35	#include "IOMInternal.h"
36	#include <VBox/vm.h>
37	#include <VBox/vmm.h>
38	#include <VBox/hwaccm.h>
39
40	#include <VBox/dis.h>
41	#include <VBox/disopcode.h>
42	#include <VBox/param.h>
43	#include <VBox/err.h>
44	#include <iprt/assert.h>
45	#include <VBox/log.h>
46	#include <iprt/asm.h>
47	#include <iprt/string.h>
48
49
50	/*******************************************************************************
51	* Global Variables *
52	*******************************************************************************/
53
54	/**
55	* Array for fast recode of the operand size (1/2/4/8 bytes) to bit shift value.
56	*/
57	static const unsigned g_aSize2Shift[] =
58	{
59	~0, /* 0 - invalid */
60	0, /* 1 == 2^0 /
61	1, /* 2 == 2^1 /
62	~0, /* 3 - invalid */
63	2, /* 4 == 2^2 /
64	~0, /* 5 - invalid */
65	~0, /* 6 - invalid */
66	~0, /* 7 - invalid */
67	3 /* 8 == 2^3 /
68	};
69
70	/**
71	* Macro for fast recode of the operand size (1/2/4/8 bytes) to bit shift value.
72	*/
73	#define SIZE_2_SHIFT(cb) (g_aSize2Shift[cb])
74
75
76	/**
77	* Wrapper which does the write and updates range statistics when such are enabled.
78	* @warning RT_SUCCESS(rc=VINF_IOM_HC_MMIO_WRITE) is TRUE!
79	*/
80	DECLINLINE(int) iomMMIODoWrite(PVM pVM, PIOMMMIORANGE pRange, RTGCPHYS GCPhysFault, const void *pvData, unsigned cb)
81	{
82	#ifdef VBOX_WITH_STATISTICS
83	PIOMMMIOSTATS pStats = iomMMIOGetStats(&pVM->iom.s, GCPhysFault, pRange);
84	Assert(pStats);
85	#endif
86
87	int rc;
88	if (RT_LIKELY(pRange->CTX_SUFF(pfnWriteCallback)))
89	rc = pRange->CTX_SUFF(pfnWriteCallback)(pRange->CTX_SUFF(pDevIns), pRange->CTX_SUFF(pvUser), GCPhysFault, (void )pvData, cb); / @todo fix const!! */
90	else
91	rc = VINF_SUCCESS;
92	if (rc != VINF_IOM_HC_MMIO_WRITE)
93	STAM_COUNTER_INC(&pStats->CTX_SUFF_Z(Write));
94	return rc;
95	}
96
97
98	/**
99	* Wrapper which does the read and updates range statistics when such are enabled.
100	*/
101	DECLINLINE(int) iomMMIODoRead(PVM pVM, PIOMMMIORANGE pRange, RTGCPHYS GCPhys, void *pvValue, unsigned cbValue)
102	{
103	#ifdef VBOX_WITH_STATISTICS
104	PIOMMMIOSTATS pStats = iomMMIOGetStats(&pVM->iom.s, GCPhys, pRange);
105	Assert(pStats);
106	#endif
107
108	int rc;
109	if (RT_LIKELY(pRange->CTX_SUFF(pfnReadCallback)))
110	rc = pRange->CTX_SUFF(pfnReadCallback)(pRange->CTX_SUFF(pDevIns), pRange->CTX_SUFF(pvUser), GCPhys, pvValue, cbValue);
111	else
112	rc = VINF_IOM_MMIO_UNUSED_FF;
113	if (rc != VINF_SUCCESS)
114	{
115	switch (rc)
116	{
117	case VINF_IOM_MMIO_UNUSED_FF:
118	switch (cbValue)
119	{
120	case 1: (uint8_t )pvValue = UINT8_C(0xff); break;
121	case 2: (uint16_t )pvValue = UINT16_C(0xffff); break;
122	case 4: (uint32_t )pvValue = UINT32_C(0xffffffff); break;
123	case 8: (uint64_t )pvValue = UINT64_C(0xffffffffffffffff); break;
124	default: AssertReleaseMsgFailed(("cbValue=%d GCPhys=%RGp\n", cbValue, GCPhys)); break;
125	}
126	rc = VINF_SUCCESS;
127	break;
128
129	case VINF_IOM_MMIO_UNUSED_00:
130	switch (cbValue)
131	{
132	case 1: (uint8_t )pvValue = UINT8_C(0x00); break;
133	case 2: (uint16_t )pvValue = UINT16_C(0x0000); break;
134	case 4: (uint32_t )pvValue = UINT32_C(0x00000000); break;
135	case 8: (uint64_t )pvValue = UINT64_C(0x0000000000000000); break;
136	default: AssertReleaseMsgFailed(("cbValue=%d GCPhys=%RGp\n", cbValue, GCPhys)); break;
137	}
138	rc = VINF_SUCCESS;
139	break;
140	}
141	if (rc != VINF_IOM_HC_MMIO_READ)
142	STAM_COUNTER_INC(&pStats->CTX_SUFF_Z(Read));
143	}
144	return rc;
145	}
146
147
148	/**
149	* Internal - statistics only.
150	*/
151	DECLINLINE(void) iomMMIOStatLength(PVM pVM, unsigned cb)
152	{
153	#ifdef VBOX_WITH_STATISTICS
154	switch (cb)
155	{
156	case 1:
157	STAM_COUNTER_INC(&pVM->iom.s.StatRZMMIO1Byte);
158	break;
159	case 2:
160	STAM_COUNTER_INC(&pVM->iom.s.StatRZMMIO2Bytes);
161	break;
162	case 4:
163	STAM_COUNTER_INC(&pVM->iom.s.StatRZMMIO4Bytes);
164	break;
165	case 8:
166	STAM_COUNTER_INC(&pVM->iom.s.StatRZMMIO8Bytes);
167	break;
168	default:
169	/* No way. */
170	AssertMsgFailed(("Invalid data length %d\n", cb));
171	break;
172	}
173	#else
174	NOREF(pVM); NOREF(cb);
175	#endif
176	}
177
178
179	/**
180	* MOV reg, mem (read)
181	* MOVZX reg, mem (read)
182	* MOVSX reg, mem (read)
183	*
184	* @returns VBox status code.
185	*
186	* @param pVM The virtual machine.
187	* @param pRegFrame Pointer to CPUMCTXCORE guest registers structure.
188	* @param pCpu Disassembler CPU state.
189	* @param pRange Pointer MMIO range.
190	* @param GCPhysFault The GC physical address corresponding to pvFault.
191	*/
192	static int iomInterpretMOVxXRead(PVM pVM, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu, PIOMMMIORANGE pRange, RTGCPHYS GCPhysFault)
193	{
194	Assert(pRange->CTX_SUFF(pfnReadCallback) \|\| !pRange->pfnReadCallbackR3);
195
196	/*
197	* Get the data size from parameter 2,
198	* and call the handler function to get the data.
199	*/
200	unsigned cb = DISGetParamSize(pCpu, &pCpu->param2);
201	AssertMsg(cb > 0 && cb <= sizeof(uint64_t), ("cb=%d\n", cb));
202
203	uint64_t u64Data = 0;
204	int rc = iomMMIODoRead(pVM, pRange, GCPhysFault, &u64Data, cb);
205	if (rc == VINF_SUCCESS)
206	{
207	/*
208	* Do sign extension for MOVSX.
209	*/
210	/** @todo checkup MOVSX implementation! */
211	if (pCpu->pCurInstr->opcode == OP_MOVSX)
212	{
213	if (cb == 1)
214	{
215	/* DWORD <- BYTE */
216	int64_t iData = (int8_t)u64Data;
217	u64Data = (uint64_t)iData;
218	}
219	else
220	{
221	/* DWORD <- WORD */
222	int64_t iData = (int16_t)u64Data;
223	u64Data = (uint64_t)iData;
224	}
225	}
226
227	/*
228	* Store the result to register (parameter 1).
229	*/
230	bool fRc = iomSaveDataToReg(pCpu, &pCpu->param1, pRegFrame, u64Data);
231	AssertMsg(fRc, ("Failed to store register value!\n")); NOREF(fRc);
232	}
233
234	if (rc == VINF_SUCCESS)
235	iomMMIOStatLength(pVM, cb);
236	return rc;
237	}
238
239
240	/**
241	* MOV mem, reg\|imm (write)
242	*
243	* @returns VBox status code.
244	*
245	* @param pVM The virtual machine.
246	* @param pRegFrame Pointer to CPUMCTXCORE guest registers structure.
247	* @param pCpu Disassembler CPU state.
248	* @param pRange Pointer MMIO range.
249	* @param GCPhysFault The GC physical address corresponding to pvFault.
250	*/
251	static int iomInterpretMOVxXWrite(PVM pVM, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu, PIOMMMIORANGE pRange, RTGCPHYS GCPhysFault)
252	{
253	Assert(pRange->CTX_SUFF(pfnWriteCallback) \|\| !pRange->pfnWriteCallbackR3);
254
255	/*
256	* Get data to write from second parameter,
257	* and call the callback to write it.
258	*/
259	unsigned cb = 0;
260	uint64_t u64Data = 0;
261	bool fRc = iomGetRegImmData(pCpu, &pCpu->param2, pRegFrame, &u64Data, &cb);
262	AssertMsg(fRc, ("Failed to get reg/imm port number!\n")); NOREF(fRc);
263
264	int rc = iomMMIODoWrite(pVM, pRange, GCPhysFault, &u64Data, cb);
265	if (rc == VINF_SUCCESS)
266	iomMMIOStatLength(pVM, cb);
267	return rc;
268	}
269
270
271	/** Wrapper for reading virtual memory. */
272	DECLINLINE(int) iomRamRead(PVMCPU pVCpu, void *pDest, RTGCPTR GCSrc, uint32_t cb)
273	{
274	/* Note: This will fail in R0 or RC if it hits an access handler. That
275	isn't a problem though since the operation can be restarted in REM. */
276	#ifdef IN_RC
277	return MMGCRamReadNoTrapHandler(pDest, (void *)GCSrc, cb);
278	#else
279	return PGMPhysReadGCPtr(pVCpu, pDest, GCSrc, cb);
280	#endif
281	}
282
283
284	/** Wrapper for writing virtual memory. */
285	DECLINLINE(int) iomRamWrite(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, RTGCPTR GCPtrDst, void *pvSrc, uint32_t cb)
286	{
287	/** @todo Need to update PGMVerifyAccess to take access handlers into account for Ring-0 and
288	* raw mode code. Some thought needs to be spent on theoretical concurrency issues as
289	* as well since we're not behind the pgm lock and handler may change between calls.
290	* MMGCRamWriteNoTrapHandler may also trap if the page isn't shadowed, or was kicked
291	* out from both the shadow pt (SMP or our changes) and TLB.
292	*
293	* Currently MMGCRamWriteNoTrapHandler may also fail when it hits a write access handler.
294	* PGMPhysInterpretedWriteNoHandlers/PGMPhysWriteGCPtr OTOH may mess up the state
295	* of some shadowed structure in R0. */
296	#ifdef IN_RC
297	NOREF(pCtxCore);
298	return MMGCRamWriteNoTrapHandler((void *)GCPtrDst, pvSrc, cb);
299	#elif IN_RING0
300	return PGMPhysInterpretedWriteNoHandlers(pVCpu, pCtxCore, GCPtrDst, pvSrc, cb, false /fRaiseTrap/);
301	#else
302	NOREF(pCtxCore);
303	return PGMPhysWriteGCPtr(pVCpu, GCPtrDst, pvSrc, cb);
304	#endif
305	}
306
307
308	#ifdef IOM_WITH_MOVS_SUPPORT
309	/**
310	* [REP] MOVSB
311	* [REP] MOVSW
312	* [REP] MOVSD
313	*
314	* Restricted implementation.
315	*
316	*
317	* @returns VBox status code.
318	*
319	* @param pVM The virtual machine.
320	* @param uErrorCode CPU Error code.
321	* @param pRegFrame Trap register frame.
322	* @param GCPhysFault The GC physical address corresponding to pvFault.
323	* @param pCpu Disassembler CPU state.
324	* @param pRange Pointer MMIO range.
325	* @param ppStat Which sub-sample to attribute this call to.
326	*/
327	static int iomInterpretMOVS(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, PDISCPUSTATE pCpu, PIOMMMIORANGE pRange, PSTAMPROFILE *ppStat)
328	{
329	/*
330	* We do not support segment prefixes or REPNE.
331	*/
332	if (pCpu->prefix & (PREFIX_SEG \| PREFIX_REPNE))
333	return VINF_IOM_HC_MMIO_READ_WRITE; /** @todo -> interpret whatever. */
334
335	PVMCPU pVCpu = VMMGetCpu(pVM);
336
337	/*
338	* Get bytes/words/dwords/qword count to copy.
339	*/
340	uint32_t cTransfers = 1;
341	if (pCpu->prefix & PREFIX_REP)
342	{
343	#ifndef IN_RC
344	if ( CPUMIsGuestIn64BitCode(pVCpu, pRegFrame)
345	&& pRegFrame->rcx >= _4G)
346	return VINF_EM_RAW_EMULATE_INSTR;
347	#endif
348
349	cTransfers = pRegFrame->ecx;
350	if (SELMGetCpuModeFromSelector(pVM, pRegFrame->eflags, pRegFrame->cs, &pRegFrame->csHid) == CPUMODE_16BIT)
351	cTransfers &= 0xffff;
352
353	if (!cTransfers)
354	return VINF_SUCCESS;
355	}
356
357	/* Get the current privilege level. */
358	uint32_t cpl = CPUMGetGuestCPL(pVCpu, pRegFrame);
359
360	/*
361	* Get data size.
362	*/
363	unsigned cb = DISGetParamSize(pCpu, &pCpu->param1);
364	AssertMsg(cb > 0 && cb <= sizeof(uint64_t), ("cb=%d\n", cb));
365	int offIncrement = pRegFrame->eflags.Bits.u1DF ? -(signed)cb : (signed)cb;
366
367	#ifdef VBOX_WITH_STATISTICS
368	if (pVM->iom.s.cMovsMaxBytes < (cTransfers << SIZE_2_SHIFT(cb)))
369	pVM->iom.s.cMovsMaxBytes = cTransfers << SIZE_2_SHIFT(cb);
370	#endif
371
372	/** @todo re-evaluate on page boundraries. */
373
374	RTGCPHYS Phys = GCPhysFault;
375	int rc;
376	if (uErrorCode & X86_TRAP_PF_RW)
377	{
378	/*
379	* Write operation: [Mem] -> [MMIO]
380	* ds:esi (Virt Src) -> es:edi (Phys Dst)
381	*/
382	STAM_STATS({ *ppStat = &pVM->iom.s.StatRZInstMovsToMMIO; });
383
384	/* Check callback. */
385	if (!pRange->CTX_SUFF(pfnWriteCallback))
386	return VINF_IOM_HC_MMIO_WRITE;
387
388	/* Convert source address ds:esi. */
389	RTGCUINTPTR pu8Virt;
390	rc = SELMToFlatEx(pVM, DIS_SELREG_DS, pRegFrame, (RTGCPTR)pRegFrame->rsi,
391	SELMTOFLAT_FLAGS_HYPER \| SELMTOFLAT_FLAGS_NO_PL,
392	(PRTGCPTR)&pu8Virt);
393	if (RT_SUCCESS(rc))
394	{
395
396	/* Access verification first; we currently can't recover properly from traps inside this instruction */
397	rc = PGMVerifyAccess(pVCpu, pu8Virt, cTransfers * cb, (cpl == 3) ? X86_PTE_US : 0);
398	if (rc != VINF_SUCCESS)
399	{
400	Log(("MOVS will generate a trap -> recompiler, rc=%d\n", rc));
401	return VINF_EM_RAW_EMULATE_INSTR;
402	}
403
404	#ifdef IN_RC
405	MMGCRamRegisterTrapHandler(pVM);
406	#endif
407
408	/* copy loop. */
409	while (cTransfers)
410	{
411	uint32_t u32Data = 0;
412	rc = iomRamRead(pVCpu, &u32Data, (RTGCPTR)pu8Virt, cb);
413	if (rc != VINF_SUCCESS)
414	break;
415	rc = iomMMIODoWrite(pVM, pRange, Phys, &u32Data, cb);
416	if (rc != VINF_SUCCESS)
417	break;
418
419	pu8Virt += offIncrement;
420	Phys += offIncrement;
421	pRegFrame->rsi += offIncrement;
422	pRegFrame->rdi += offIncrement;
423	cTransfers--;
424	}
425	#ifdef IN_RC
426	MMGCRamDeregisterTrapHandler(pVM);
427	#endif
428	/* Update ecx. */
429	if (pCpu->prefix & PREFIX_REP)
430	pRegFrame->ecx = cTransfers;
431	}
432	else
433	rc = VINF_IOM_HC_MMIO_READ_WRITE;
434	}
435	else
436	{
437	/*
438	* Read operation: [MMIO] -> [mem] or [MMIO] -> [MMIO]
439	* ds:[eSI] (Phys Src) -> es:[eDI] (Virt Dst)
440	*/
441	STAM_STATS({ *ppStat = &pVM->iom.s.StatRZInstMovsFromMMIO; });
442
443	/* Check callback. */
444	if (!pRange->CTX_SUFF(pfnReadCallback))
445	return VINF_IOM_HC_MMIO_READ;
446
447	/* Convert destination address. */
448	RTGCUINTPTR pu8Virt;
449	rc = SELMToFlatEx(pVM, DIS_SELREG_ES, pRegFrame, (RTGCPTR)pRegFrame->rdi,
450	SELMTOFLAT_FLAGS_HYPER \| SELMTOFLAT_FLAGS_NO_PL,
451	(RTGCPTR *)&pu8Virt);
452	if (RT_FAILURE(rc))
453	return VINF_IOM_HC_MMIO_READ;
454
455	/* Check if destination address is MMIO. */
456	PIOMMMIORANGE pMMIODst;
457	RTGCPHYS PhysDst;
458	rc = PGMGstGetPage(pVCpu, (RTGCPTR)pu8Virt, NULL, &PhysDst);
459	PhysDst \|= (RTGCUINTPTR)pu8Virt & PAGE_OFFSET_MASK;
460	if ( RT_SUCCESS(rc)
461	&& (pMMIODst = iomMMIOGetRange(&pVM->iom.s, PhysDst)))
462	{
463	/*
464	* Extra: [MMIO] -> [MMIO]
465	*/
466	STAM_STATS({ *ppStat = &pVM->iom.s.StatRZInstMovsMMIO; });
467	if (!pMMIODst->CTX_SUFF(pfnWriteCallback) && pMMIODst->pfnWriteCallbackR3)
468	return VINF_IOM_HC_MMIO_READ_WRITE;
469
470	/* copy loop. */
471	while (cTransfers)
472	{
473	uint32_t u32Data;
474	rc = iomMMIODoRead(pVM, pRange, Phys, &u32Data, cb);
475	if (rc != VINF_SUCCESS)
476	break;
477	rc = iomMMIODoWrite(pVM, pMMIODst, PhysDst, &u32Data, cb);
478	if (rc != VINF_SUCCESS)
479	break;
480
481	Phys += offIncrement;
482	PhysDst += offIncrement;
483	pRegFrame->rsi += offIncrement;
484	pRegFrame->rdi += offIncrement;
485	cTransfers--;
486	}
487	}
488	else
489	{
490	/*
491	* Normal: [MMIO] -> [Mem]
492	*/
493	/* Access verification first; we currently can't recover properly from traps inside this instruction */
494	rc = PGMVerifyAccess(pVCpu, pu8Virt, cTransfers * cb, X86_PTE_RW \| ((cpl == 3) ? X86_PTE_US : 0));
495	if (rc != VINF_SUCCESS)
496	{
497	Log(("MOVS will generate a trap -> recompiler, rc=%d\n", rc));
498	return VINF_EM_RAW_EMULATE_INSTR;
499	}
500
501	/* copy loop. */
502	#ifdef IN_RC
503	MMGCRamRegisterTrapHandler(pVM);
504	#endif
505	while (cTransfers)
506	{
507	uint32_t u32Data;
508	rc = iomMMIODoRead(pVM, pRange, Phys, &u32Data, cb);
509	if (rc != VINF_SUCCESS)
510	break;
511	rc = iomRamWrite(pVCpu, pRegFrame, (RTGCPTR)pu8Virt, &u32Data, cb);
512	if (rc != VINF_SUCCESS)
513	{
514	Log(("iomRamWrite %08X size=%d failed with %d\n", pu8Virt, cb, rc));
515	break;
516	}
517
518	pu8Virt += offIncrement;
519	Phys += offIncrement;
520	pRegFrame->rsi += offIncrement;
521	pRegFrame->rdi += offIncrement;
522	cTransfers--;
523	}
524	#ifdef IN_RC
525	MMGCRamDeregisterTrapHandler(pVM);
526	#endif
527	}
528
529	/* Update ecx on exit. */
530	if (pCpu->prefix & PREFIX_REP)
531	pRegFrame->ecx = cTransfers;
532	}
533
534	/* work statistics. */
535	if (rc == VINF_SUCCESS)
536	iomMMIOStatLength(pVM, cb);
537	NOREF(ppStat);
538	return rc;
539	}
540	#endif /* IOM_WITH_MOVS_SUPPORT */
541
542
543	/**
544	* [REP] STOSB
545	* [REP] STOSW
546	* [REP] STOSD
547	*
548	* Restricted implementation.
549	*
550	*
551	* @returns VBox status code.
552	*
553	* @param pVM The virtual machine.
554	* @param pRegFrame Trap register frame.
555	* @param GCPhysFault The GC physical address corresponding to pvFault.
556	* @param pCpu Disassembler CPU state.
557	* @param pRange Pointer MMIO range.
558	*/
559	static int iomInterpretSTOS(PVM pVM, PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, PDISCPUSTATE pCpu, PIOMMMIORANGE pRange)
560	{
561	/*
562	* We do not support segment prefixes or REPNE..
563	*/
564	if (pCpu->prefix & (PREFIX_SEG \| PREFIX_REPNE))
565	return VINF_IOM_HC_MMIO_READ_WRITE; /** @todo -> REM instead of HC */
566
567	/*
568	* Get bytes/words/dwords count to copy.
569	*/
570	uint32_t cTransfers = 1;
571	if (pCpu->prefix & PREFIX_REP)
572	{
573	#ifndef IN_RC
574	if ( CPUMIsGuestIn64BitCode(VMMGetCpu(pVM), pRegFrame)
575	&& pRegFrame->rcx >= _4G)
576	return VINF_EM_RAW_EMULATE_INSTR;
577	#endif
578
579	cTransfers = pRegFrame->ecx;
580	if (SELMGetCpuModeFromSelector(pVM, pRegFrame->eflags, pRegFrame->cs, &pRegFrame->csHid) == CPUMODE_16BIT)
581	cTransfers &= 0xffff;
582
583	if (!cTransfers)
584	return VINF_SUCCESS;
585	}
586
587	/** @todo r=bird: bounds checks! */
588
589	/*
590	* Get data size.
591	*/
592	unsigned cb = DISGetParamSize(pCpu, &pCpu->param1);
593	AssertMsg(cb > 0 && cb <= sizeof(uint64_t), ("cb=%d\n", cb));
594	int offIncrement = pRegFrame->eflags.Bits.u1DF ? -(signed)cb : (signed)cb;
595
596	#ifdef VBOX_WITH_STATISTICS
597	if (pVM->iom.s.cStosMaxBytes < (cTransfers << SIZE_2_SHIFT(cb)))
598	pVM->iom.s.cStosMaxBytes = cTransfers << SIZE_2_SHIFT(cb);
599	#endif
600
601
602	RTGCPHYS Phys = GCPhysFault;
603	uint32_t u32Data = pRegFrame->eax;
604	int rc;
605	if (pRange->CTX_SUFF(pfnFillCallback))
606	{
607	/*
608	* Use the fill callback.
609	*/
610	/** @todo pfnFillCallback must return number of bytes successfully written!!! */
611	if (offIncrement > 0)
612	{
613	/* addr++ variant. */
614	rc = pRange->CTX_SUFF(pfnFillCallback)(pRange->CTX_SUFF(pDevIns), pRange->CTX_SUFF(pvUser), Phys, u32Data, cb, cTransfers);
615	if (rc == VINF_SUCCESS)
616	{
617	/* Update registers. */
618	pRegFrame->rdi += cTransfers << SIZE_2_SHIFT(cb);
619	if (pCpu->prefix & PREFIX_REP)
620	pRegFrame->ecx = 0;
621	}
622	}
623	else
624	{
625	/* addr-- variant. */
626	rc = pRange->CTX_SUFF(pfnFillCallback)(pRange->CTX_SUFF(pDevIns), pRange->CTX_SUFF(pvUser), (Phys - (cTransfers - 1)) << SIZE_2_SHIFT(cb), u32Data, cb, cTransfers);
627	if (rc == VINF_SUCCESS)
628	{
629	/* Update registers. */
630	pRegFrame->rdi -= cTransfers << SIZE_2_SHIFT(cb);
631	if (pCpu->prefix & PREFIX_REP)
632	pRegFrame->ecx = 0;
633	}
634	}
635	}
636	else
637	{
638	/*
639	* Use the write callback.
640	*/
641	Assert(pRange->CTX_SUFF(pfnWriteCallback) \|\| !pRange->pfnWriteCallbackR3);
642
643	/* fill loop. */
644	do
645	{
646	rc = iomMMIODoWrite(pVM, pRange, Phys, &u32Data, cb);
647	if (rc != VINF_SUCCESS)
648	break;
649
650	Phys += offIncrement;
651	pRegFrame->rdi += offIncrement;
652	cTransfers--;
653	} while (cTransfers);
654
655	/* Update ecx on exit. */
656	if (pCpu->prefix & PREFIX_REP)
657	pRegFrame->ecx = cTransfers;
658	}
659
660	/*
661	* Work statistics and return.
662	*/
663	if (rc == VINF_SUCCESS)
664	iomMMIOStatLength(pVM, cb);
665	return rc;
666	}
667
668
669	/**
670	* [REP] LODSB
671	* [REP] LODSW
672	* [REP] LODSD
673	*
674	* Restricted implementation.
675	*
676	*
677	* @returns VBox status code.
678	*
679	* @param pVM The virtual machine.
680	* @param pRegFrame Trap register frame.
681	* @param GCPhysFault The GC physical address corresponding to pvFault.
682	* @param pCpu Disassembler CPU state.
683	* @param pRange Pointer MMIO range.
684	*/
685	static int iomInterpretLODS(PVM pVM, PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, PDISCPUSTATE pCpu, PIOMMMIORANGE pRange)
686	{
687	Assert(pRange->CTX_SUFF(pfnReadCallback) \|\| !pRange->pfnReadCallbackR3);
688
689	/*
690	* We do not support segment prefixes or REP*.
691	*/
692	if (pCpu->prefix & (PREFIX_SEG \| PREFIX_REP \| PREFIX_REPNE))
693	return VINF_IOM_HC_MMIO_READ_WRITE; /** @todo -> REM instead of HC */
694
695	/*
696	* Get data size.
697	*/
698	unsigned cb = DISGetParamSize(pCpu, &pCpu->param2);
699	AssertMsg(cb > 0 && cb <= sizeof(uint64_t), ("cb=%d\n", cb));
700	int offIncrement = pRegFrame->eflags.Bits.u1DF ? -(signed)cb : (signed)cb;
701
702	/*
703	* Perform read.
704	*/
705	int rc = iomMMIODoRead(pVM, pRange, GCPhysFault, &pRegFrame->rax, cb);
706	if (rc == VINF_SUCCESS)
707	pRegFrame->rsi += offIncrement;
708
709	/*
710	* Work statistics and return.
711	*/
712	if (rc == VINF_SUCCESS)
713	iomMMIOStatLength(pVM, cb);
714	return rc;
715	}
716
717
718	/**
719	* CMP [MMIO], reg\|imm
720	* CMP reg\|imm, [MMIO]
721	*
722	* Restricted implementation.
723	*
724	*
725	* @returns VBox status code.
726	*
727	* @param pVM The virtual machine.
728	* @param pRegFrame Trap register frame.
729	* @param GCPhysFault The GC physical address corresponding to pvFault.
730	* @param pCpu Disassembler CPU state.
731	* @param pRange Pointer MMIO range.
732	*/
733	static int iomInterpretCMP(PVM pVM, PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, PDISCPUSTATE pCpu, PIOMMMIORANGE pRange)
734	{
735	Assert(pRange->CTX_SUFF(pfnReadCallback) \|\| !pRange->pfnReadCallbackR3);
736
737	/*
738	* Get the operands.
739	*/
740	unsigned cb = 0;
741	uint64_t uData1 = 0;
742	uint64_t uData2 = 0;
743	int rc;
744	if (iomGetRegImmData(pCpu, &pCpu->param1, pRegFrame, &uData1, &cb))
745	/* cmp reg, [MMIO]. */
746	rc = iomMMIODoRead(pVM, pRange, GCPhysFault, &uData2, cb);
747	else if (iomGetRegImmData(pCpu, &pCpu->param2, pRegFrame, &uData2, &cb))
748	/* cmp [MMIO], reg\|imm. */
749	rc = iomMMIODoRead(pVM, pRange, GCPhysFault, &uData1, cb);
750	else
751	{
752	AssertMsgFailed(("Disassember CMP problem..\n"));
753	rc = VERR_IOM_MMIO_HANDLER_DISASM_ERROR;
754	}
755
756	if (rc == VINF_SUCCESS)
757	{
758	/* Emulate CMP and update guest flags. */
759	uint32_t eflags = EMEmulateCmp(uData1, uData2, cb);
760	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
761	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
762	iomMMIOStatLength(pVM, cb);
763	}
764
765	return rc;
766	}
767
768
769	/**
770	* AND [MMIO], reg\|imm
771	* AND reg, [MMIO]
772	* OR [MMIO], reg\|imm
773	* OR reg, [MMIO]
774	*
775	* Restricted implementation.
776	*
777	*
778	* @returns VBox status code.
779	*
780	* @param pVM The virtual machine.
781	* @param pRegFrame Trap register frame.
782	* @param GCPhysFault The GC physical address corresponding to pvFault.
783	* @param pCpu Disassembler CPU state.
784	* @param pRange Pointer MMIO range.
785	* @param pfnEmulate Instruction emulation function.
786	*/
787	static int iomInterpretOrXorAnd(PVM pVM, PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, PDISCPUSTATE pCpu, PIOMMMIORANGE pRange, PFNEMULATEPARAM3 pfnEmulate)
788	{
789	unsigned cb = 0;
790	uint64_t uData1 = 0;
791	uint64_t uData2 = 0;
792	bool fAndWrite;
793	int rc;
794
795	#ifdef LOG_ENABLED
796	const char *pszInstr;
797
798	if (pCpu->pCurInstr->opcode == OP_XOR)
799	pszInstr = "Xor";
800	else if (pCpu->pCurInstr->opcode == OP_OR)
801	pszInstr = "Or";
802	else if (pCpu->pCurInstr->opcode == OP_AND)
803	pszInstr = "And";
804	else
805	pszInstr = "OrXorAnd??";
806	#endif
807
808	if (iomGetRegImmData(pCpu, &pCpu->param1, pRegFrame, &uData1, &cb))
809	{
810	/* and reg, [MMIO]. */
811	Assert(pRange->CTX_SUFF(pfnReadCallback) \|\| !pRange->pfnReadCallbackR3);
812	fAndWrite = false;
813	rc = iomMMIODoRead(pVM, pRange, GCPhysFault, &uData2, cb);
814	}
815	else if (iomGetRegImmData(pCpu, &pCpu->param2, pRegFrame, &uData2, &cb))
816	{
817	/* and [MMIO], reg\|imm. */
818	fAndWrite = true;
819	if ( (pRange->CTX_SUFF(pfnReadCallback) \|\| !pRange->pfnReadCallbackR3)
820	&& (pRange->CTX_SUFF(pfnWriteCallback) \|\| !pRange->pfnWriteCallbackR3))
821	rc = iomMMIODoRead(pVM, pRange, GCPhysFault, &uData1, cb);
822	else
823	rc = VINF_IOM_HC_MMIO_READ_WRITE;
824	}
825	else
826	{
827	AssertMsgFailed(("Disassember AND problem..\n"));
828	return VERR_IOM_MMIO_HANDLER_DISASM_ERROR;
829	}
830
831	if (rc == VINF_SUCCESS)
832	{
833	/* Emulate AND and update guest flags. */
834	uint32_t eflags = pfnEmulate((uint32_t *)&uData1, uData2, cb);
835
836	LogFlow(("iomInterpretOrXorAnd %s result %RX64\n", pszInstr, uData1));
837
838	if (fAndWrite)
839	/* Store result to MMIO. */
840	rc = iomMMIODoWrite(pVM, pRange, GCPhysFault, &uData1, cb);
841	else
842	{
843	/* Store result to register. */
844	bool fRc = iomSaveDataToReg(pCpu, &pCpu->param1, pRegFrame, uData1);
845	AssertMsg(fRc, ("Failed to store register value!\n")); NOREF(fRc);
846	}
847	if (rc == VINF_SUCCESS)
848	{
849	/* Update guest's eflags and finish. */
850	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
851	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
852	iomMMIOStatLength(pVM, cb);
853	}
854	}
855
856	return rc;
857	}
858
859
860	/**
861	* TEST [MMIO], reg\|imm
862	* TEST reg, [MMIO]
863	*
864	* Restricted implementation.
865	*
866	*
867	* @returns VBox status code.
868	*
869	* @param pVM The virtual machine.
870	* @param pRegFrame Trap register frame.
871	* @param GCPhysFault The GC physical address corresponding to pvFault.
872	* @param pCpu Disassembler CPU state.
873	* @param pRange Pointer MMIO range.
874	*/
875	static int iomInterpretTEST(PVM pVM, PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, PDISCPUSTATE pCpu, PIOMMMIORANGE pRange)
876	{
877	Assert(pRange->CTX_SUFF(pfnReadCallback) \|\| !pRange->pfnReadCallbackR3);
878
879	unsigned cb = 0;
880	uint64_t uData1 = 0;
881	uint64_t uData2 = 0;
882	int rc;
883
884	if (iomGetRegImmData(pCpu, &pCpu->param1, pRegFrame, &uData1, &cb))
885	{
886	/* and test, [MMIO]. */
887	rc = iomMMIODoRead(pVM, pRange, GCPhysFault, &uData2, cb);
888	}
889	else if (iomGetRegImmData(pCpu, &pCpu->param2, pRegFrame, &uData2, &cb))
890	{
891	/* test [MMIO], reg\|imm. */
892	rc = iomMMIODoRead(pVM, pRange, GCPhysFault, &uData1, cb);
893	}
894	else
895	{
896	AssertMsgFailed(("Disassember TEST problem..\n"));
897	return VERR_IOM_MMIO_HANDLER_DISASM_ERROR;
898	}
899
900	if (rc == VINF_SUCCESS)
901	{
902	/* Emulate TEST (=AND without write back) and update guest EFLAGS. */
903	uint32_t eflags = EMEmulateAnd((uint32_t *)&uData1, uData2, cb);
904	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
905	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
906	iomMMIOStatLength(pVM, cb);
907	}
908
909	return rc;
910	}
911
912
913	/**
914	* BT [MMIO], reg\|imm
915	*
916	* Restricted implementation.
917	*
918	*
919	* @returns VBox status code.
920	*
921	* @param pVM The virtual machine.
922	* @param pRegFrame Trap register frame.
923	* @param GCPhysFault The GC physical address corresponding to pvFault.
924	* @param pCpu Disassembler CPU state.
925	* @param pRange Pointer MMIO range.
926	*/
927	static int iomInterpretBT(PVM pVM, PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, PDISCPUSTATE pCpu, PIOMMMIORANGE pRange)
928	{
929	Assert(pRange->CTX_SUFF(pfnReadCallback) \|\| !pRange->pfnReadCallbackR3);
930
931	uint64_t uBit = 0;
932	uint64_t uData1 = 0;
933	unsigned cb = 0;
934	int rc;
935
936	if (iomGetRegImmData(pCpu, &pCpu->param2, pRegFrame, &uBit, &cb))
937	{
938	/* bt [MMIO], reg\|imm. */
939	rc = iomMMIODoRead(pVM, pRange, GCPhysFault, &uData1, cb);
940	}
941	else
942	{
943	AssertMsgFailed(("Disassember BT problem..\n"));
944	return VERR_IOM_MMIO_HANDLER_DISASM_ERROR;
945	}
946
947	if (rc == VINF_SUCCESS)
948	{
949	/* The size of the memory operand only matters here. */
950	cb = DISGetParamSize(pCpu, &pCpu->param1);
951
952	/* Find the bit inside the faulting address */
953	uBit &= (cb*8 - 1);
954
955	pRegFrame->eflags.Bits.u1CF = (uData1 >> uBit);
956	iomMMIOStatLength(pVM, cb);
957	}
958
959	return rc;
960	}
961
962	/**
963	* XCHG [MMIO], reg
964	* XCHG reg, [MMIO]
965	*
966	* Restricted implementation.
967	*
968	*
969	* @returns VBox status code.
970	*
971	* @param pVM The virtual machine.
972	* @param pRegFrame Trap register frame.
973	* @param GCPhysFault The GC physical address corresponding to pvFault.
974	* @param pCpu Disassembler CPU state.
975	* @param pRange Pointer MMIO range.
976	*/
977	static int iomInterpretXCHG(PVM pVM, PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, PDISCPUSTATE pCpu, PIOMMMIORANGE pRange)
978	{
979	/* Check for read & write handlers since IOMMMIOHandler doesn't cover this. */
980	if ( (!pRange->CTX_SUFF(pfnReadCallback) && pRange->pfnReadCallbackR3)
981	\|\| (!pRange->CTX_SUFF(pfnWriteCallback) && pRange->pfnWriteCallbackR3))
982	return VINF_IOM_HC_MMIO_READ_WRITE;
983
984	int rc;
985	unsigned cb = 0;
986	uint64_t uData1 = 0;
987	uint64_t uData2 = 0;
988	if (iomGetRegImmData(pCpu, &pCpu->param1, pRegFrame, &uData1, &cb))
989	{
990	/* xchg reg, [MMIO]. */
991	rc = iomMMIODoRead(pVM, pRange, GCPhysFault, &uData2, cb);
992	if (rc == VINF_SUCCESS)
993	{
994	/* Store result to MMIO. */
995	rc = iomMMIODoWrite(pVM, pRange, GCPhysFault, &uData1, cb);
996
997	if (rc == VINF_SUCCESS)
998	{
999	/* Store result to register. */
1000	bool fRc = iomSaveDataToReg(pCpu, &pCpu->param1, pRegFrame, uData2);
1001	AssertMsg(fRc, ("Failed to store register value!\n")); NOREF(fRc);
1002	}
1003	else
1004	Assert(rc == VINF_IOM_HC_MMIO_WRITE \|\| rc == VINF_PATM_HC_MMIO_PATCH_WRITE);
1005	}
1006	else
1007	Assert(rc == VINF_IOM_HC_MMIO_READ \|\| rc == VINF_PATM_HC_MMIO_PATCH_READ);
1008	}
1009	else if (iomGetRegImmData(pCpu, &pCpu->param2, pRegFrame, &uData2, &cb))
1010	{
1011	/* xchg [MMIO], reg. */
1012	rc = iomMMIODoRead(pVM, pRange, GCPhysFault, &uData1, cb);
1013	if (rc == VINF_SUCCESS)
1014	{
1015	/* Store result to MMIO. */
1016	rc = iomMMIODoWrite(pVM, pRange, GCPhysFault, &uData2, cb);
1017	if (rc == VINF_SUCCESS)
1018	{
1019	/* Store result to register. */
1020	bool fRc = iomSaveDataToReg(pCpu, &pCpu->param2, pRegFrame, uData1);
1021	AssertMsg(fRc, ("Failed to store register value!\n")); NOREF(fRc);
1022	}
1023	else
1024	AssertMsg(rc == VINF_IOM_HC_MMIO_READ_WRITE \|\| rc == VINF_IOM_HC_MMIO_WRITE \|\| rc == VINF_PATM_HC_MMIO_PATCH_WRITE, ("rc=%Vrc\n", rc));
1025	}
1026	else
1027	AssertMsg(rc == VINF_IOM_HC_MMIO_READ_WRITE \|\| rc == VINF_IOM_HC_MMIO_READ \|\| rc == VINF_PATM_HC_MMIO_PATCH_READ, ("rc=%Vrc\n", rc));
1028	}
1029	else
1030	{
1031	AssertMsgFailed(("Disassember XCHG problem..\n"));
1032	rc = VERR_IOM_MMIO_HANDLER_DISASM_ERROR;
1033	}
1034	return rc;
1035	}
1036
1037
1038	/**
1039	* \#PF Handler callback for MMIO ranges.
1040	*
1041	* @returns VBox status code (appropriate for GC return).
1042	* @param pVM VM Handle.
1043	* @param uErrorCode CPU Error code.
1044	* @param pCtxCore Trap register frame.
1045	* @param GCPhysFault The GC physical address corresponding to pvFault.
1046	* @param pvUser Pointer to the MMIO ring-3 range entry.
1047	*/
1048	int iomMMIOHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pCtxCore, RTGCPHYS GCPhysFault, void *pvUser)
1049	{
1050	/* Take the IOM lock before performing any MMIO. */
1051	int rc = iomLock(pVM);
1052	#ifndef IN_RING3
1053	if (rc == VERR_SEM_BUSY)
1054	return (uErrorCode & X86_TRAP_PF_RW) ? VINF_IOM_HC_MMIO_WRITE : VINF_IOM_HC_MMIO_READ;
1055	#endif
1056	AssertRC(rc);
1057
1058	STAM_PROFILE_START(&pVM->iom.s.StatRZMMIOHandler, a);
1059	Log(("iomMMIOHandler: GCPhys=%RGp uErr=%#x pvFault=%RGv rip=%RGv\n",
1060	GCPhysFault, (uint32_t)uErrorCode, (RTGCPTR)pCtxCore->rip));
1061
1062	PIOMMMIORANGE pRange = (PIOMMMIORANGE)pvUser;
1063	Assert(pRange);
1064	Assert(pRange == iomMMIOGetRange(&pVM->iom.s, GCPhysFault));
1065
1066	#ifdef VBOX_WITH_STATISTICS
1067	/*
1068	* Locate the statistics, if > PAGE_SIZE we'll use the first byte for everything.
1069	*/
1070	PIOMMMIOSTATS pStats = iomMMIOGetStats(&pVM->iom.s, GCPhysFault, pRange);
1071	if (!pStats)
1072	{
1073	# ifdef IN_RING3
1074	iomUnlock(pVM);
1075	return VERR_NO_MEMORY;
1076	# else
1077	STAM_PROFILE_STOP(&pVM->iom.s.StatRZMMIOHandler, a);
1078	STAM_COUNTER_INC(&pVM->iom.s.StatRZMMIOFailures);
1079	iomUnlock(pVM);
1080	return (uErrorCode & X86_TRAP_PF_RW) ? VINF_IOM_HC_MMIO_WRITE : VINF_IOM_HC_MMIO_READ;
1081	# endif
1082	}
1083	#endif
1084
1085	#ifndef IN_RING3
1086	/*
1087	* Should we defer the request right away?
1088	*/
1089	if (uErrorCode & X86_TRAP_PF_RW
1090	? !pRange->CTX_SUFF(pfnWriteCallback) && pRange->pfnWriteCallbackR3
1091	: !pRange->CTX_SUFF(pfnReadCallback) && pRange->pfnReadCallbackR3)
1092	{
1093	# ifdef VBOX_WITH_STATISTICS
1094	if (uErrorCode & X86_TRAP_PF_RW)
1095	STAM_COUNTER_INC(&pStats->CTX_MID_Z(Write,ToR3));
1096	else
1097	STAM_COUNTER_INC(&pStats->CTX_MID_Z(Read,ToR3));
1098	# endif
1099
1100	STAM_PROFILE_STOP(&pVM->iom.s.StatRZMMIOHandler, a);
1101	STAM_COUNTER_INC(&pVM->iom.s.StatRZMMIOFailures);
1102	iomUnlock(pVM);
1103	return (uErrorCode & X86_TRAP_PF_RW ? VINF_IOM_HC_MMIO_WRITE : VINF_IOM_HC_MMIO_READ);
1104	}
1105	#endif /* !IN_RING3 */
1106
1107	/*
1108	* Disassemble the instruction and interpret it.
1109	*/
1110	PVMCPU pVCpu = VMMGetCpu(pVM);
1111	PDISCPUSTATE pDis = &pVCpu->iom.s.DisState;
1112	unsigned cbOp;
1113	rc = EMInterpretDisasOne(pVM, pVCpu, pCtxCore, pDis, &cbOp);
1114	AssertRC(rc);
1115	if (RT_FAILURE(rc))
1116	{
1117	iomUnlock(pVM);
1118	return rc;
1119	}
1120	switch (pDis->pCurInstr->opcode)
1121	{
1122	case OP_MOV:
1123	case OP_MOVZX:
1124	case OP_MOVSX:
1125	{
1126	STAM_PROFILE_START(&pVM->iom.s.StatRZInstMov, b);
1127	if (uErrorCode & X86_TRAP_PF_RW)
1128	rc = iomInterpretMOVxXWrite(pVM, pCtxCore, pDis, pRange, GCPhysFault);
1129	else
1130	rc = iomInterpretMOVxXRead(pVM, pCtxCore, pDis, pRange, GCPhysFault);
1131	STAM_PROFILE_STOP(&pVM->iom.s.StatRZInstMov, b);
1132	break;
1133	}
1134
1135
1136	#ifdef IOM_WITH_MOVS_SUPPORT
1137	case OP_MOVSB:
1138	case OP_MOVSWD:
1139	{
1140	STAM_PROFILE_ADV_START(&pVM->iom.s.StatRZInstMovs, c);
1141	PSTAMPROFILE pStat = NULL;
1142	rc = iomInterpretMOVS(pVM, uErrorCode, pCtxCore, GCPhysFault, pDis, pRange, &pStat);
1143	STAM_PROFILE_ADV_STOP_EX(&pVM->iom.s.StatRZInstMovs, pStat, c);
1144	break;
1145	}
1146	#endif
1147
1148	case OP_STOSB:
1149	case OP_STOSWD:
1150	Assert(uErrorCode & X86_TRAP_PF_RW);
1151	STAM_PROFILE_START(&pVM->iom.s.StatRZInstStos, d);
1152	rc = iomInterpretSTOS(pVM, pCtxCore, GCPhysFault, pDis, pRange);
1153	STAM_PROFILE_STOP(&pVM->iom.s.StatRZInstStos, d);
1154	break;
1155
1156	case OP_LODSB:
1157	case OP_LODSWD:
1158	Assert(!(uErrorCode & X86_TRAP_PF_RW));
1159	STAM_PROFILE_START(&pVM->iom.s.StatRZInstLods, e);
1160	rc = iomInterpretLODS(pVM, pCtxCore, GCPhysFault, pDis, pRange);
1161	STAM_PROFILE_STOP(&pVM->iom.s.StatRZInstLods, e);
1162	break;
1163
1164	case OP_CMP:
1165	Assert(!(uErrorCode & X86_TRAP_PF_RW));
1166	STAM_PROFILE_START(&pVM->iom.s.StatRZInstCmp, f);
1167	rc = iomInterpretCMP(pVM, pCtxCore, GCPhysFault, pDis, pRange);
1168	STAM_PROFILE_STOP(&pVM->iom.s.StatRZInstCmp, f);
1169	break;
1170
1171	case OP_AND:
1172	STAM_PROFILE_START(&pVM->iom.s.StatRZInstAnd, g);
1173	rc = iomInterpretOrXorAnd(pVM, pCtxCore, GCPhysFault, pDis, pRange, EMEmulateAnd);
1174	STAM_PROFILE_STOP(&pVM->iom.s.StatRZInstAnd, g);
1175	break;
1176
1177	case OP_OR:
1178	STAM_PROFILE_START(&pVM->iom.s.StatRZInstOr, k);
1179	rc = iomInterpretOrXorAnd(pVM, pCtxCore, GCPhysFault, pDis, pRange, EMEmulateOr);
1180	STAM_PROFILE_STOP(&pVM->iom.s.StatRZInstOr, k);
1181	break;
1182
1183	case OP_XOR:
1184	STAM_PROFILE_START(&pVM->iom.s.StatRZInstXor, m);
1185	rc = iomInterpretOrXorAnd(pVM, pCtxCore, GCPhysFault, pDis, pRange, EMEmulateXor);
1186	STAM_PROFILE_STOP(&pVM->iom.s.StatRZInstXor, m);
1187	break;
1188
1189	case OP_TEST:
1190	Assert(!(uErrorCode & X86_TRAP_PF_RW));
1191	STAM_PROFILE_START(&pVM->iom.s.StatRZInstTest, h);
1192	rc = iomInterpretTEST(pVM, pCtxCore, GCPhysFault, pDis, pRange);
1193	STAM_PROFILE_STOP(&pVM->iom.s.StatRZInstTest, h);
1194	break;
1195
1196	case OP_BT:
1197	Assert(!(uErrorCode & X86_TRAP_PF_RW));
1198	STAM_PROFILE_START(&pVM->iom.s.StatRZInstBt, l);
1199	rc = iomInterpretBT(pVM, pCtxCore, GCPhysFault, pDis, pRange);
1200	STAM_PROFILE_STOP(&pVM->iom.s.StatRZInstBt, l);
1201	break;
1202
1203	case OP_XCHG:
1204	STAM_PROFILE_START(&pVM->iom.s.StatRZInstXchg, i);
1205	rc = iomInterpretXCHG(pVM, pCtxCore, GCPhysFault, pDis, pRange);
1206	STAM_PROFILE_STOP(&pVM->iom.s.StatRZInstXchg, i);
1207	break;
1208
1209
1210	/*
1211	* The instruction isn't supported. Hand it on to ring-3.
1212	*/
1213	default:
1214	STAM_COUNTER_INC(&pVM->iom.s.StatRZInstOther);
1215	rc = (uErrorCode & X86_TRAP_PF_RW) ? VINF_IOM_HC_MMIO_WRITE : VINF_IOM_HC_MMIO_READ;
1216	break;
1217	}
1218
1219	/*
1220	* On success advance EIP.
1221	*/
1222	if (rc == VINF_SUCCESS)
1223	pCtxCore->rip += cbOp;
1224	else
1225	{
1226	STAM_COUNTER_INC(&pVM->iom.s.StatRZMMIOFailures);
1227	#if defined(VBOX_WITH_STATISTICS) && !defined(IN_RING3)
1228	switch (rc)
1229	{
1230	case VINF_IOM_HC_MMIO_READ:
1231	case VINF_IOM_HC_MMIO_READ_WRITE:
1232	STAM_COUNTER_INC(&pStats->CTX_MID_Z(Read,ToR3));
1233	break;
1234	case VINF_IOM_HC_MMIO_WRITE:
1235	STAM_COUNTER_INC(&pStats->CTX_MID_Z(Write,ToR3));
1236	break;
1237	}
1238	#endif
1239	}
1240
1241	STAM_PROFILE_STOP(&pVM->iom.s.StatRZMMIOHandler, a);
1242	iomUnlock(pVM);
1243	return rc;
1244	}
1245
1246	/**
1247	* \#PF Handler callback for MMIO ranges.
1248	*
1249	* @returns VBox status code (appropriate for GC return).
1250	* @param pVM VM Handle.
1251	* @param uErrorCode CPU Error code.
1252	* @param pCtxCore Trap register frame.
1253	* @param pvFault The fault address (cr2).
1254	* @param GCPhysFault The GC physical address corresponding to pvFault.
1255	* @param pvUser Pointer to the MMIO ring-3 range entry.
1256	*/
1257	VMMDECL(int) IOMMMIOHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pCtxCore, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser)
1258	{
1259	LogFlow(("IOMMMIOHandler: GCPhys=%RGp uErr=%#x pvFault=%RGv rip=%RGv\n",
1260	GCPhysFault, (uint32_t)uErrorCode, pvFault, (RTGCPTR)pCtxCore->rip));
1261	return iomMMIOHandler(pVM, uErrorCode, pCtxCore, GCPhysFault, pvUser);
1262	}
1263
1264	/**
1265	* Physical access handler for MMIO ranges.
1266	*
1267	* @returns VBox status code (appropriate for GC return).
1268	* @param pVM VM Handle.
1269	* @param uErrorCode CPU Error code.
1270	* @param pCtxCore Trap register frame.
1271	* @param GCPhysFault The GC physical address.
1272	*/
1273	VMMDECL(int) IOMMMIOPhysHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pCtxCore, RTGCPHYS GCPhysFault)
1274	{
1275	return iomMMIOHandler(pVM, uErrorCode, pCtxCore, GCPhysFault, iomMMIOGetRange(&pVM->iom.s, GCPhysFault));
1276	}
1277
1278	#ifdef IN_RING3
1279	/**
1280	* \#PF Handler callback for MMIO ranges.
1281	*
1282	* @returns VINF_SUCCESS if the handler have carried out the operation.
1283	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
1284	* @param pVM VM Handle.
1285	* @param GCPhys The physical address the guest is writing to.
1286	* @param pvPhys The HC mapping of that address.
1287	* @param pvBuf What the guest is reading/writing.
1288	* @param cbBuf How much it's reading/writing.
1289	* @param enmAccessType The access type.
1290	* @param pvUser Pointer to the MMIO range entry.
1291	*/
1292	DECLCALLBACK(int) IOMR3MMIOHandler(PVM pVM, RTGCPHYS GCPhysFault, void pvPhys, void pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser)
1293	{
1294	PIOMMMIORANGE pRange = (PIOMMMIORANGE)pvUser;
1295	STAM_COUNTER_INC(&pVM->iom.s.StatR3MMIOHandler);
1296
1297	/* Take the IOM lock before performing any MMIO. */
1298	int rc = iomLock(pVM);
1299	AssertRC(rc);
1300
1301	AssertMsg(cbBuf == 1 \|\| cbBuf == 2 \|\| cbBuf == 4 \|\| cbBuf == 8, ("%zu\n", cbBuf));
1302
1303	Assert(pRange);
1304	Assert(pRange == iomMMIOGetRange(&pVM->iom.s, GCPhysFault));
1305
1306	if (enmAccessType == PGMACCESSTYPE_READ)
1307	rc = iomMMIODoRead(pVM, pRange, GCPhysFault, pvBuf, (unsigned)cbBuf);
1308	else
1309	rc = iomMMIODoWrite(pVM, pRange, GCPhysFault, pvBuf, (unsigned)cbBuf);
1310
1311	AssertRC(rc);
1312	iomUnlock(pVM);
1313	return rc;
1314	}
1315	#endif /* IN_RING3 */
1316
1317	/**
1318	* Reads a MMIO register.
1319	*
1320	* @returns VBox status code.
1321	*
1322	* @param pVM VM handle.
1323	* @param GCPhys The physical address to read.
1324	* @param pu32Value Where to store the value read.
1325	* @param cbValue The size of the register to read in bytes. 1, 2 or 4 bytes.
1326	*/
1327	VMMDECL(int) IOMMMIORead(PVM pVM, RTGCPHYS GCPhys, uint32_t *pu32Value, size_t cbValue)
1328	{
1329	/* Take the IOM lock before performing any MMIO. */
1330	int rc = iomLock(pVM);
1331	#ifndef IN_RING3
1332	if (rc == VERR_SEM_BUSY)
1333	return VINF_IOM_HC_MMIO_WRITE;
1334	#endif
1335	AssertRC(rc);
1336
1337	/*
1338	* Lookup the current context range node and statistics.
1339	*/
1340	PIOMMMIORANGE pRange = iomMMIOGetRange(&pVM->iom.s, GCPhys);
1341	AssertMsg(pRange, ("Handlers and page tables are out of sync or something! GCPhys=%RGp cbValue=%d\n", GCPhys, cbValue));
1342	if (!pRange)
1343	{
1344	iomUnlock(pVM);
1345	return VERR_INTERNAL_ERROR;
1346	}
1347	#ifdef VBOX_WITH_STATISTICS
1348	PIOMMMIOSTATS pStats = iomMMIOGetStats(&pVM->iom.s, GCPhys, pRange);
1349	if (!pStats)
1350	{
1351	iomUnlock(pVM);
1352	# ifdef IN_RING3
1353	return VERR_NO_MEMORY;
1354	# else
1355	return VINF_IOM_HC_MMIO_READ;
1356	# endif
1357	}
1358	#endif /* VBOX_WITH_STATISTICS */
1359	if (pRange->CTX_SUFF(pfnReadCallback))
1360	{
1361	/*
1362	* Perform the read and deal with the result.
1363	*/
1364	#ifdef VBOX_WITH_STATISTICS
1365	STAM_PROFILE_ADV_START(&pStats->CTX_SUFF_Z(ProfRead), a);
1366	#endif
1367	rc = pRange->CTX_SUFF(pfnReadCallback)(pRange->CTX_SUFF(pDevIns), pRange->CTX_SUFF(pvUser), GCPhys, pu32Value, (unsigned)cbValue);
1368	#ifdef VBOX_WITH_STATISTICS
1369	STAM_PROFILE_ADV_STOP(&pStats->CTX_SUFF_Z(ProfRead), a);
1370	if (rc != VINF_IOM_HC_MMIO_READ)
1371	STAM_COUNTER_INC(&pStats->CTX_SUFF_Z(Read));
1372	#endif
1373	switch (rc)
1374	{
1375	case VINF_SUCCESS:
1376	default:
1377	Log4(("IOMMMIORead: GCPhys=%RGp pu32=%08RX32 cb=%d rc=%Rrc\n", GCPhys, pu32Value, cbValue, rc));
1378	iomUnlock(pVM);
1379	return rc;
1380
1381	case VINF_IOM_MMIO_UNUSED_00:
1382	switch (cbValue)
1383	{
1384	case 1: (uint8_t )pu32Value = UINT8_C(0x00); break;
1385	case 2: (uint16_t )pu32Value = UINT16_C(0x0000); break;
1386	case 4: (uint32_t )pu32Value = UINT32_C(0x00000000); break;
1387	case 8: (uint64_t )pu32Value = UINT64_C(0x0000000000000000); break;
1388	default: AssertReleaseMsgFailed(("cbValue=%d GCPhys=%RGp\n", cbValue, GCPhys)); break;
1389	}
1390	Log4(("IOMMMIORead: GCPhys=%RGp pu32=%08RX32 cb=%d rc=%Rrc\n", GCPhys, pu32Value, cbValue, rc));
1391	iomUnlock(pVM);
1392	return VINF_SUCCESS;
1393
1394	case VINF_IOM_MMIO_UNUSED_FF:
1395	switch (cbValue)
1396	{
1397	case 1: (uint8_t )pu32Value = UINT8_C(0xff); break;
1398	case 2: (uint16_t )pu32Value = UINT16_C(0xffff); break;
1399	case 4: (uint32_t )pu32Value = UINT32_C(0xffffffff); break;
1400	case 8: (uint64_t )pu32Value = UINT64_C(0xffffffffffffffff); break;
1401	default: AssertReleaseMsgFailed(("cbValue=%d GCPhys=%RGp\n", cbValue, GCPhys)); break;
1402	}
1403	Log4(("IOMMMIORead: GCPhys=%RGp pu32=%08RX32 cb=%d rc=%Rrc\n", GCPhys, pu32Value, cbValue, rc));
1404	iomUnlock(pVM);
1405	return VINF_SUCCESS;
1406	}
1407	}
1408	#ifndef IN_RING3
1409	if (pRange->pfnReadCallbackR3)
1410	{
1411	STAM_COUNTER_INC(&pStats->CTX_MID_Z(Read,ToR3));
1412	iomUnlock(pVM);
1413	return VINF_IOM_HC_MMIO_READ;
1414	}
1415	#endif
1416
1417	/*
1418	* Lookup the ring-3 range.
1419	*/
1420	#ifdef VBOX_WITH_STATISTICS
1421	STAM_COUNTER_INC(&pStats->CTX_SUFF_Z(Read));
1422	#endif
1423	/* Unassigned memory; this is actually not supposed to happen. */
1424	switch (cbValue)
1425	{
1426	case 1: (uint8_t )pu32Value = UINT8_C(0xff); break;
1427	case 2: (uint16_t )pu32Value = UINT16_C(0xffff); break;
1428	case 4: (uint32_t )pu32Value = UINT32_C(0xffffffff); break;
1429	case 8: (uint64_t )pu32Value = UINT64_C(0xffffffffffffffff); break;
1430	default: AssertReleaseMsgFailed(("cbValue=%d GCPhys=%RGp\n", cbValue, GCPhys)); break;
1431	}
1432	Log4(("IOMMMIORead: GCPhys=%RGp pu32=%08RX32 cb=%d rc=VINF_SUCCESS\n", GCPhys, pu32Value, cbValue));
1433	iomUnlock(pVM);
1434	return VINF_SUCCESS;
1435	}
1436
1437
1438	/**
1439	* Writes to a MMIO register.
1440	*
1441	* @returns VBox status code.
1442	*
1443	* @param pVM VM handle.
1444	* @param GCPhys The physical address to write to.
1445	* @param u32Value The value to write.
1446	* @param cbValue The size of the register to read in bytes. 1, 2 or 4 bytes.
1447	*/
1448	VMMDECL(int) IOMMMIOWrite(PVM pVM, RTGCPHYS GCPhys, uint32_t u32Value, size_t cbValue)
1449	{
1450	/* Take the IOM lock before performing any MMIO. */
1451	int rc = iomLock(pVM);
1452	#ifndef IN_RING3
1453	if (rc == VERR_SEM_BUSY)
1454	return VINF_IOM_HC_MMIO_WRITE;
1455	#endif
1456	AssertRC(rc);
1457
1458	/*
1459	* Lookup the current context range node.
1460	*/
1461	PIOMMMIORANGE pRange = iomMMIOGetRange(&pVM->iom.s, GCPhys);
1462	AssertMsg(pRange, ("Handlers and page tables are out of sync or something! GCPhys=%RGp cbValue=%d\n", GCPhys, cbValue));
1463	if (!pRange)
1464	{
1465	iomUnlock(pVM);
1466	return VERR_INTERNAL_ERROR;
1467	}
1468	#ifdef VBOX_WITH_STATISTICS
1469	PIOMMMIOSTATS pStats = iomMMIOGetStats(&pVM->iom.s, GCPhys, pRange);
1470	if (!pStats)
1471	{
1472	iomUnlock(pVM);
1473	# ifdef IN_RING3
1474	return VERR_NO_MEMORY;
1475	# else
1476	return VINF_IOM_HC_MMIO_WRITE;
1477	# endif
1478	}
1479	#endif /* VBOX_WITH_STATISTICS */
1480
1481	/*
1482	* Perform the write if there's a write handler. R0/GC may have
1483	* to defer it to ring-3.
1484	*/
1485	if (pRange->CTX_SUFF(pfnWriteCallback))
1486	{
1487	#ifdef VBOX_WITH_STATISTICS
1488	STAM_PROFILE_ADV_START(&pStats->CTX_SUFF_Z(ProfWrite), a);
1489	#endif
1490	rc = pRange->CTX_SUFF(pfnWriteCallback)(pRange->CTX_SUFF(pDevIns), pRange->CTX_SUFF(pvUser), GCPhys, &u32Value, (unsigned)cbValue);
1491	#ifdef VBOX_WITH_STATISTICS
1492	STAM_PROFILE_ADV_STOP(&pStats->CTX_SUFF_Z(ProfWrite), a);
1493	if (rc != VINF_IOM_HC_MMIO_WRITE)
1494	STAM_COUNTER_INC(&pStats->CTX_SUFF_Z(Write));
1495	#endif
1496	Log4(("IOMMMIOWrite: GCPhys=%RGp u32=%08RX32 cb=%d rc=%Rrc\n", GCPhys, u32Value, cbValue, rc));
1497	iomUnlock(pVM);
1498	return rc;
1499	}
1500	#ifndef IN_RING3
1501	if (pRange->pfnWriteCallbackR3)
1502	{
1503	STAM_COUNTER_INC(&pStats->CTX_MID_Z(Write,ToR3));
1504	iomUnlock(pVM);
1505	return VINF_IOM_HC_MMIO_WRITE;
1506	}
1507	#endif
1508
1509	/*
1510	* No write handler, nothing to do.
1511	*/
1512	#ifdef VBOX_WITH_STATISTICS
1513	STAM_COUNTER_INC(&pStats->CTX_SUFF_Z(Write));
1514	#endif
1515	Log4(("IOMMMIOWrite: GCPhys=%RGp u32=%08RX32 cb=%d rc=%Rrc\n", GCPhys, u32Value, cbValue, VINF_SUCCESS));
1516	iomUnlock(pVM);
1517	return VINF_SUCCESS;
1518	}
1519
1520	/**
1521	* [REP*] INSB/INSW/INSD
1522	* ES:EDI,DX[,ECX]
1523	*
1524	* @remark Assumes caller checked the access privileges (IOMInterpretCheckPortIOAccess)
1525	*
1526	* @returns Strict VBox status code. Informational status codes other than the one documented
1527	* here are to be treated as internal failure. Use IOM_SUCCESS() to check for success.
1528	* @retval VINF_SUCCESS Success.
1529	* @retval VINF_EM_FIRST-VINF_EM_LAST Success with some exceptions (see IOM_SUCCESS()), the
1530	* status code must be passed on to EM.
1531	* @retval VINF_IOM_HC_IOPORT_READ Defer the read to ring-3. (R0/GC only)
1532	* @retval VINF_EM_RAW_EMULATE_INSTR Defer the read to the REM.
1533	* @retval VINF_EM_RAW_GUEST_TRAP The exception was left pending. (TRPMRaiseXcptErr)
1534	* @retval VINF_TRPM_XCPT_DISPATCHED The exception was raised and dispatched for raw-mode execution. (TRPMRaiseXcptErr)
1535	* @retval VINF_EM_RESCHEDULE_REM The exception was dispatched and cannot be executed in raw-mode. (TRPMRaiseXcptErr)
1536	*
1537	* @param pVM The virtual machine.
1538	* @param pRegFrame Pointer to CPUMCTXCORE guest registers structure.
1539	* @param uPort IO Port
1540	* @param uPrefix IO instruction prefix
1541	* @param cbTransfer Size of transfer unit
1542	*/
1543	VMMDECL(int) IOMInterpretINSEx(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t uPort, uint32_t uPrefix, uint32_t cbTransfer)
1544	{
1545	#ifdef VBOX_WITH_STATISTICS
1546	STAM_COUNTER_INC(&pVM->iom.s.StatInstIns);
1547	#endif
1548
1549	/*
1550	* We do not support REPNE or decrementing destination
1551	* pointer. Segment prefixes are deliberately ignored, as per the instruction specification.
1552	*/
1553	if ( (uPrefix & PREFIX_REPNE)
1554	\|\| pRegFrame->eflags.Bits.u1DF)
1555	return VINF_EM_RAW_EMULATE_INSTR;
1556
1557	PVMCPU pVCpu = VMMGetCpu(pVM);
1558
1559	/*
1560	* Get bytes/words/dwords count to transfer.
1561	*/
1562	RTGCUINTREG cTransfers = 1;
1563	if (uPrefix & PREFIX_REP)
1564	{
1565	#ifndef IN_RC
1566	if ( CPUMIsGuestIn64BitCode(pVCpu, pRegFrame)
1567	&& pRegFrame->rcx >= _4G)
1568	return VINF_EM_RAW_EMULATE_INSTR;
1569	#endif
1570	cTransfers = pRegFrame->ecx;
1571
1572	if (SELMGetCpuModeFromSelector(pVM, pRegFrame->eflags, pRegFrame->cs, &pRegFrame->csHid) == CPUMODE_16BIT)
1573	cTransfers &= 0xffff;
1574
1575	if (!cTransfers)
1576	return VINF_SUCCESS;
1577	}
1578
1579	/* Convert destination address es:edi. */
1580	RTGCPTR GCPtrDst;
1581	int rc = SELMToFlatEx(pVM, DIS_SELREG_ES, pRegFrame, (RTGCPTR)pRegFrame->rdi,
1582	SELMTOFLAT_FLAGS_HYPER \| SELMTOFLAT_FLAGS_NO_PL,
1583	&GCPtrDst);
1584	if (RT_FAILURE(rc))
1585	{
1586	Log(("INS destination address conversion failed -> fallback, rc=%d\n", rc));
1587	return VINF_EM_RAW_EMULATE_INSTR;
1588	}
1589
1590	/* Access verification first; we can't recover from traps inside this instruction, as the port read cannot be repeated. */
1591	uint32_t cpl = CPUMGetGuestCPL(pVCpu, pRegFrame);
1592
1593	rc = PGMVerifyAccess(pVCpu, (RTGCUINTPTR)GCPtrDst, cTransfers * cbTransfer,
1594	X86_PTE_RW \| ((cpl == 3) ? X86_PTE_US : 0));
1595	if (rc != VINF_SUCCESS)
1596	{
1597	Log(("INS will generate a trap -> fallback, rc=%d\n", rc));
1598	return VINF_EM_RAW_EMULATE_INSTR;
1599	}
1600
1601	Log(("IOM: rep ins%d port %#x count %d\n", cbTransfer * 8, uPort, cTransfers));
1602	if (cTransfers > 1)
1603	{
1604	/* If the device supports string transfers, ask it to do as
1605	* much as it wants. The rest is done with single-word transfers. */
1606	const RTGCUINTREG cTransfersOrg = cTransfers;
1607	rc = IOMIOPortReadString(pVM, uPort, &GCPtrDst, &cTransfers, cbTransfer);
1608	AssertRC(rc); Assert(cTransfers <= cTransfersOrg);
1609	pRegFrame->rdi += (cTransfersOrg - cTransfers) * cbTransfer;
1610	}
1611
1612	#ifdef IN_RC
1613	MMGCRamRegisterTrapHandler(pVM);
1614	#endif
1615
1616	while (cTransfers && rc == VINF_SUCCESS)
1617	{
1618	uint32_t u32Value;
1619	rc = IOMIOPortRead(pVM, uPort, &u32Value, cbTransfer);
1620	if (!IOM_SUCCESS(rc))
1621	break;
1622	int rc2 = iomRamWrite(pVCpu, pRegFrame, GCPtrDst, &u32Value, cbTransfer);
1623	Assert(rc2 == VINF_SUCCESS); NOREF(rc2);
1624	GCPtrDst = (RTGCPTR)((RTGCUINTPTR)GCPtrDst + cbTransfer);
1625	pRegFrame->rdi += cbTransfer;
1626	cTransfers--;
1627	}
1628	#ifdef IN_RC
1629	MMGCRamDeregisterTrapHandler(pVM);
1630	#endif
1631
1632	/* Update ecx on exit. */
1633	if (uPrefix & PREFIX_REP)
1634	pRegFrame->ecx = cTransfers;
1635
1636	AssertMsg(rc == VINF_SUCCESS \|\| rc == VINF_IOM_HC_IOPORT_READ \|\| (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST) \|\| RT_FAILURE(rc), ("%Rrc\n", rc));
1637	return rc;
1638	}
1639
1640
1641	/**
1642	* [REP*] INSB/INSW/INSD
1643	* ES:EDI,DX[,ECX]
1644	*
1645	* @returns Strict VBox status code. Informational status codes other than the one documented
1646	* here are to be treated as internal failure. Use IOM_SUCCESS() to check for success.
1647	* @retval VINF_SUCCESS Success.
1648	* @retval VINF_EM_FIRST-VINF_EM_LAST Success with some exceptions (see IOM_SUCCESS()), the
1649	* status code must be passed on to EM.
1650	* @retval VINF_IOM_HC_IOPORT_READ Defer the read to ring-3. (R0/GC only)
1651	* @retval VINF_EM_RAW_EMULATE_INSTR Defer the read to the REM.
1652	* @retval VINF_EM_RAW_GUEST_TRAP The exception was left pending. (TRPMRaiseXcptErr)
1653	* @retval VINF_TRPM_XCPT_DISPATCHED The exception was raised and dispatched for raw-mode execution. (TRPMRaiseXcptErr)
1654	* @retval VINF_EM_RESCHEDULE_REM The exception was dispatched and cannot be executed in raw-mode. (TRPMRaiseXcptErr)
1655	*
1656	* @param pVM The virtual machine.
1657	* @param pRegFrame Pointer to CPUMCTXCORE guest registers structure.
1658	* @param pCpu Disassembler CPU state.
1659	*/
1660	VMMDECL(int) IOMInterpretINS(PVM pVM, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu)
1661	{
1662	/*
1663	* Get port number directly from the register (no need to bother the
1664	* disassembler). And get the I/O register size from the opcode / prefix.
1665	*/
1666	RTIOPORT Port = pRegFrame->edx & 0xffff;
1667	unsigned cb = 0;
1668	if (pCpu->pCurInstr->opcode == OP_INSB)
1669	cb = 1;
1670	else
1671	cb = (pCpu->opmode == CPUMODE_16BIT) ? 2 : 4; /* dword in both 32 & 64 bits mode */
1672
1673	int rc = IOMInterpretCheckPortIOAccess(pVM, pRegFrame, Port, cb);
1674	if (RT_UNLIKELY(rc != VINF_SUCCESS))
1675	{
1676	AssertMsg(rc == VINF_EM_RAW_GUEST_TRAP \|\| rc == VINF_TRPM_XCPT_DISPATCHED \|\| rc == VINF_TRPM_XCPT_DISPATCHED \|\| RT_FAILURE(rc), ("%Rrc\n", rc));
1677	return rc;
1678	}
1679
1680	return IOMInterpretINSEx(pVM, pRegFrame, Port, pCpu->prefix, cb);
1681	}
1682
1683
1684	/**
1685	* [REP*] OUTSB/OUTSW/OUTSD
1686	* DS:ESI,DX[,ECX]
1687	*
1688	* @remark Assumes caller checked the access privileges (IOMInterpretCheckPortIOAccess)
1689	*
1690	* @returns Strict VBox status code. Informational status codes other than the one documented
1691	* here are to be treated as internal failure. Use IOM_SUCCESS() to check for success.
1692	* @retval VINF_SUCCESS Success.
1693	* @retval VINF_EM_FIRST-VINF_EM_LAST Success with some exceptions (see IOM_SUCCESS()), the
1694	* status code must be passed on to EM.
1695	* @retval VINF_IOM_HC_IOPORT_WRITE Defer the write to ring-3. (R0/GC only)
1696	* @retval VINF_EM_RAW_GUEST_TRAP The exception was left pending. (TRPMRaiseXcptErr)
1697	* @retval VINF_TRPM_XCPT_DISPATCHED The exception was raised and dispatched for raw-mode execution. (TRPMRaiseXcptErr)
1698	* @retval VINF_EM_RESCHEDULE_REM The exception was dispatched and cannot be executed in raw-mode. (TRPMRaiseXcptErr)
1699	*
1700	* @param pVM The virtual machine.
1701	* @param pRegFrame Pointer to CPUMCTXCORE guest registers structure.
1702	* @param uPort IO Port
1703	* @param uPrefix IO instruction prefix
1704	* @param cbTransfer Size of transfer unit
1705	*/
1706	VMMDECL(int) IOMInterpretOUTSEx(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t uPort, uint32_t uPrefix, uint32_t cbTransfer)
1707	{
1708	#ifdef VBOX_WITH_STATISTICS
1709	STAM_COUNTER_INC(&pVM->iom.s.StatInstOuts);
1710	#endif
1711
1712	/*
1713	* We do not support segment prefixes, REPNE or
1714	* decrementing source pointer.
1715	*/
1716	if ( (uPrefix & (PREFIX_SEG \| PREFIX_REPNE))
1717	\|\| pRegFrame->eflags.Bits.u1DF)
1718	return VINF_EM_RAW_EMULATE_INSTR;
1719
1720	PVMCPU pVCpu = VMMGetCpu(pVM);
1721
1722	/*
1723	* Get bytes/words/dwords count to transfer.
1724	*/
1725	RTGCUINTREG cTransfers = 1;
1726	if (uPrefix & PREFIX_REP)
1727	{
1728	#ifndef IN_RC
1729	if ( CPUMIsGuestIn64BitCode(pVCpu, pRegFrame)
1730	&& pRegFrame->rcx >= _4G)
1731	return VINF_EM_RAW_EMULATE_INSTR;
1732	#endif
1733	cTransfers = pRegFrame->ecx;
1734	if (SELMGetCpuModeFromSelector(pVM, pRegFrame->eflags, pRegFrame->cs, &pRegFrame->csHid) == CPUMODE_16BIT)
1735	cTransfers &= 0xffff;
1736
1737	if (!cTransfers)
1738	return VINF_SUCCESS;
1739	}
1740
1741	/* Convert source address ds:esi. */
1742	RTGCPTR GCPtrSrc;
1743	int rc = SELMToFlatEx(pVM, DIS_SELREG_DS, pRegFrame, (RTGCPTR)pRegFrame->rsi,
1744	SELMTOFLAT_FLAGS_HYPER \| SELMTOFLAT_FLAGS_NO_PL,
1745	&GCPtrSrc);
1746	if (RT_FAILURE(rc))
1747	{
1748	Log(("OUTS source address conversion failed -> fallback, rc=%Rrc\n", rc));
1749	return VINF_EM_RAW_EMULATE_INSTR;
1750	}
1751
1752	/* Access verification first; we currently can't recover properly from traps inside this instruction */
1753	uint32_t cpl = CPUMGetGuestCPL(pVCpu, pRegFrame);
1754	rc = PGMVerifyAccess(pVCpu, (RTGCUINTPTR)GCPtrSrc, cTransfers * cbTransfer,
1755	(cpl == 3) ? X86_PTE_US : 0);
1756	if (rc != VINF_SUCCESS)
1757	{
1758	Log(("OUTS will generate a trap -> fallback, rc=%Rrc\n", rc));
1759	return VINF_EM_RAW_EMULATE_INSTR;
1760	}
1761
1762	Log(("IOM: rep outs%d port %#x count %d\n", cbTransfer * 8, uPort, cTransfers));
1763	if (cTransfers > 1)
1764	{
1765	/*
1766	* If the device supports string transfers, ask it to do as
1767	* much as it wants. The rest is done with single-word transfers.
1768	*/
1769	const RTGCUINTREG cTransfersOrg = cTransfers;
1770	rc = IOMIOPortWriteString(pVM, uPort, &GCPtrSrc, &cTransfers, cbTransfer);
1771	AssertRC(rc); Assert(cTransfers <= cTransfersOrg);
1772	pRegFrame->rsi += (cTransfersOrg - cTransfers) * cbTransfer;
1773	}
1774
1775	#ifdef IN_RC
1776	MMGCRamRegisterTrapHandler(pVM);
1777	#endif
1778
1779	while (cTransfers && rc == VINF_SUCCESS)
1780	{
1781	uint32_t u32Value;
1782	rc = iomRamRead(pVCpu, &u32Value, GCPtrSrc, cbTransfer);
1783	if (rc != VINF_SUCCESS)
1784	break;
1785	rc = IOMIOPortWrite(pVM, uPort, u32Value, cbTransfer);
1786	if (!IOM_SUCCESS(rc))
1787	break;
1788	GCPtrSrc = (RTGCPTR)((RTUINTPTR)GCPtrSrc + cbTransfer);
1789	pRegFrame->rsi += cbTransfer;
1790	cTransfers--;
1791	}
1792
1793	#ifdef IN_RC
1794	MMGCRamDeregisterTrapHandler(pVM);
1795	#endif
1796
1797	/* Update ecx on exit. */
1798	if (uPrefix & PREFIX_REP)
1799	pRegFrame->ecx = cTransfers;
1800
1801	AssertMsg(rc == VINF_SUCCESS \|\| rc == VINF_IOM_HC_IOPORT_WRITE \|\| (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST) \|\| RT_FAILURE(rc), ("%Rrc\n", rc));
1802	return rc;
1803	}
1804
1805
1806	/**
1807	* [REP*] OUTSB/OUTSW/OUTSD
1808	* DS:ESI,DX[,ECX]
1809	*
1810	* @returns Strict VBox status code. Informational status codes other than the one documented
1811	* here are to be treated as internal failure. Use IOM_SUCCESS() to check for success.
1812	* @retval VINF_SUCCESS Success.
1813	* @retval VINF_EM_FIRST-VINF_EM_LAST Success with some exceptions (see IOM_SUCCESS()), the
1814	* status code must be passed on to EM.
1815	* @retval VINF_IOM_HC_IOPORT_WRITE Defer the write to ring-3. (R0/GC only)
1816	* @retval VINF_EM_RAW_EMULATE_INSTR Defer the write to the REM.
1817	* @retval VINF_EM_RAW_GUEST_TRAP The exception was left pending. (TRPMRaiseXcptErr)
1818	* @retval VINF_TRPM_XCPT_DISPATCHED The exception was raised and dispatched for raw-mode execution. (TRPMRaiseXcptErr)
1819	* @retval VINF_EM_RESCHEDULE_REM The exception was dispatched and cannot be executed in raw-mode. (TRPMRaiseXcptErr)
1820	*
1821	* @param pVM The virtual machine.
1822	* @param pRegFrame Pointer to CPUMCTXCORE guest registers structure.
1823	* @param pCpu Disassembler CPU state.
1824	*/
1825	VMMDECL(int) IOMInterpretOUTS(PVM pVM, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu)
1826	{
1827	/*
1828	* Get port number from the first parameter.
1829	* And get the I/O register size from the opcode / prefix.
1830	*/
1831	uint64_t Port = 0;
1832	unsigned cb = 0;
1833	bool fRc = iomGetRegImmData(pCpu, &pCpu->param1, pRegFrame, &Port, &cb);
1834	AssertMsg(fRc, ("Failed to get reg/imm port number!\n")); NOREF(fRc);
1835	if (pCpu->pCurInstr->opcode == OP_OUTSB)
1836	cb = 1;
1837	else
1838	cb = (pCpu->opmode == CPUMODE_16BIT) ? 2 : 4; /* dword in both 32 & 64 bits mode */
1839
1840	int rc = IOMInterpretCheckPortIOAccess(pVM, pRegFrame, Port, cb);
1841	if (RT_UNLIKELY(rc != VINF_SUCCESS))
1842	{
1843	AssertMsg(rc == VINF_EM_RAW_GUEST_TRAP \|\| rc == VINF_TRPM_XCPT_DISPATCHED \|\| rc == VINF_TRPM_XCPT_DISPATCHED \|\| RT_FAILURE(rc), ("%Rrc\n", rc));
1844	return rc;
1845	}
1846
1847	return IOMInterpretOUTSEx(pVM, pRegFrame, Port, pCpu->prefix, cb);
1848	}
1849
1850
1851	#ifndef IN_RC
1852	/**
1853	* Mapping an MMIO2 page in place of an MMIO page for direct access.
1854	*
1855	* (This is a special optimization used by the VGA device.)
1856	*
1857	* @returns VBox status code.
1858	*
1859	* @param pVM The virtual machine.
1860	* @param GCPhys The address of the MMIO page to be changed.
1861	* @param GCPhysRemapped The address of the MMIO2 page.
1862	* @param fPageFlags Page flags to set. Must be (X86_PTE_RW \| X86_PTE_P)
1863	* for the time being.
1864	*/
1865	VMMDECL(int) IOMMMIOMapMMIO2Page(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysRemapped, uint64_t fPageFlags)
1866	{
1867	Log(("IOMMMIOMapMMIO2Page %RGp -> %RGp flags=%RX64\n", GCPhys, GCPhysRemapped, fPageFlags));
1868
1869	AssertReturn(fPageFlags == (X86_PTE_RW \| X86_PTE_P), VERR_INVALID_PARAMETER);
1870
1871	PVMCPU pVCpu = VMMGetCpu(pVM);
1872
1873	/* This currently only works in real mode, protected mode without paging or with nested paging. */
1874	if ( !HWACCMIsEnabled(pVM) /* useless without VT-x/AMD-V */
1875	\|\| ( CPUMIsGuestInPagedProtectedMode(pVCpu)
1876	&& !HWACCMIsNestedPagingActive(pVM)))
1877	return VINF_SUCCESS; /* ignore */
1878
1879	/*
1880	* Lookup the context range node the page belongs to.
1881	*/
1882	PIOMMMIORANGE pRange = iomMMIOGetRange(&pVM->iom.s, GCPhys);
1883	AssertMsgReturn(pRange,
1884	("Handlers and page tables are out of sync or something! GCPhys=%RGp\n", GCPhys),
1885	VERR_IOM_MMIO_RANGE_NOT_FOUND);
1886	Assert((pRange->GCPhys & PAGE_OFFSET_MASK) == 0);
1887	Assert((pRange->Core.KeyLast & PAGE_OFFSET_MASK) == PAGE_OFFSET_MASK);
1888
1889	/*
1890	* Do the aliasing; page align the addresses since PGM is picky.
1891	*/
1892	GCPhys &= ~(RTGCPHYS)PAGE_OFFSET_MASK;
1893	GCPhysRemapped &= ~(RTGCPHYS)PAGE_OFFSET_MASK;
1894
1895	int rc = PGMHandlerPhysicalPageAlias(pVM, pRange->GCPhys, GCPhys, GCPhysRemapped);
1896	AssertRCReturn(rc, rc);
1897
1898	/*
1899	* Modify the shadow page table. Since it's an MMIO page it won't be present and we
1900	* can simply prefetch it.
1901	*
1902	* Note: This is a NOP in the EPT case; we'll just let it fault again to resync the page.
1903	*/
1904	#if 0 /* The assertion is wrong for the PGM_SYNC_CLEAR_PGM_POOL and VINF_PGM_HANDLER_ALREADY_ALIASED cases. */
1905	# ifdef VBOX_STRICT
1906	uint64_t fFlags;
1907	RTHCPHYS HCPhys;
1908	rc = PGMShwGetPage(pVCpu, (RTGCPTR)GCPhys, &fFlags, &HCPhys);
1909	Assert(rc == VERR_PAGE_NOT_PRESENT \|\| rc == VERR_PAGE_TABLE_NOT_PRESENT);
1910	# endif
1911	#endif
1912	rc = PGMPrefetchPage(pVCpu, (RTGCPTR)GCPhys);
1913	Assert(rc == VINF_SUCCESS \|\| rc == VERR_PAGE_NOT_PRESENT \|\| rc == VERR_PAGE_TABLE_NOT_PRESENT);
1914	return VINF_SUCCESS;
1915	}
1916
1917	/**
1918	* Mapping a HC page in place of an MMIO page for direct access.
1919	*
1920	* (This is a special optimization used by the APIC in the VT-x case.)
1921	*
1922	* @returns VBox status code.
1923	*
1924	* @param pVM The virtual machine.
1925	* @param GCPhys The address of the MMIO page to be changed.
1926	* @param HCPhys The address of the host physical page.
1927	* @param fPageFlags Page flags to set. Must be (X86_PTE_RW \| X86_PTE_P)
1928	* for the time being.
1929	*/
1930	VMMDECL(int) IOMMMIOMapMMIOHCPage(PVM pVM, RTGCPHYS GCPhys, RTHCPHYS HCPhys, uint64_t fPageFlags)
1931	{
1932	Log(("IOMMMIOMapMMIOHCPage %RGp -> %RGp flags=%RX64\n", GCPhys, HCPhys, fPageFlags));
1933
1934	AssertReturn(fPageFlags == (X86_PTE_RW \| X86_PTE_P), VERR_INVALID_PARAMETER);
1935	Assert(HWACCMIsEnabled(pVM));
1936
1937	PVMCPU pVCpu = VMMGetCpu(pVM);
1938
1939	/*
1940	* Lookup the context range node the page belongs to.
1941	*/
1942	PIOMMMIORANGE pRange = iomMMIOGetRange(&pVM->iom.s, GCPhys);
1943	AssertMsgReturn(pRange,
1944	("Handlers and page tables are out of sync or something! GCPhys=%RGp\n", GCPhys),
1945	VERR_IOM_MMIO_RANGE_NOT_FOUND);
1946	Assert((pRange->GCPhys & PAGE_OFFSET_MASK) == 0);
1947	Assert((pRange->Core.KeyLast & PAGE_OFFSET_MASK) == PAGE_OFFSET_MASK);
1948
1949	/*
1950	* Do the aliasing; page align the addresses since PGM is picky.
1951	*/
1952	GCPhys &= ~(RTGCPHYS)PAGE_OFFSET_MASK;
1953	HCPhys &= ~(RTHCPHYS)PAGE_OFFSET_MASK;
1954
1955	int rc = PGMHandlerPhysicalPageAliasHC(pVM, pRange->GCPhys, GCPhys, HCPhys);
1956	AssertRCReturn(rc, rc);
1957
1958	/*
1959	* Modify the shadow page table. Since it's an MMIO page it won't be present and we
1960	* can simply prefetch it.
1961	*
1962	* Note: This is a NOP in the EPT case; we'll just let it fault again to resync the page.
1963	*/
1964	rc = PGMPrefetchPage(pVCpu, (RTGCPTR)GCPhys);
1965	Assert(rc == VINF_SUCCESS \|\| rc == VERR_PAGE_NOT_PRESENT \|\| rc == VERR_PAGE_TABLE_NOT_PRESENT);
1966	return VINF_SUCCESS;
1967	}
1968
1969	/**
1970	* Reset a previously modified MMIO region; restore the access flags.
1971	*
1972	* @returns VBox status code.
1973	*
1974	* @param pVM The virtual machine.
1975	* @param GCPhys Physical address that's part of the MMIO region to be reset.
1976	*/
1977	VMMDECL(int) IOMMMIOResetRegion(PVM pVM, RTGCPHYS GCPhys)
1978	{
1979	Log(("IOMMMIOResetRegion %RGp\n", GCPhys));
1980
1981	PVMCPU pVCpu = VMMGetCpu(pVM);
1982
1983	/* This currently only works in real mode, protected mode without paging or with nested paging. */
1984	if ( !HWACCMIsEnabled(pVM) /* useless without VT-x/AMD-V */
1985	\|\| ( CPUMIsGuestInPagedProtectedMode(pVCpu)
1986	&& !HWACCMIsNestedPagingActive(pVM)))
1987	return VINF_SUCCESS; /* ignore */
1988
1989	/*
1990	* Lookup the context range node the page belongs to.
1991	*/
1992	PIOMMMIORANGE pRange = iomMMIOGetRange(&pVM->iom.s, GCPhys);
1993	AssertMsgReturn(pRange,
1994	("Handlers and page tables are out of sync or something! GCPhys=%RGp\n", GCPhys),
1995	VERR_IOM_MMIO_RANGE_NOT_FOUND);
1996
1997	/*
1998	* Call PGM to do the job work.
1999	*
2000	* After the call, all the pages should be non-present... unless there is
2001	* a page pool flush pending (unlikely).
2002	*/
2003	int rc = PGMHandlerPhysicalReset(pVM, pRange->GCPhys);
2004	AssertRC(rc);
2005
2006	#ifdef VBOX_STRICT
2007	if (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3))
2008	{
2009	uint32_t cb = pRange->cb;
2010	GCPhys = pRange->GCPhys;
2011	while (cb)
2012	{
2013	uint64_t fFlags;
2014	RTHCPHYS HCPhys;
2015	rc = PGMShwGetPage(pVCpu, (RTGCPTR)GCPhys, &fFlags, &HCPhys);
2016	Assert(rc == VERR_PAGE_NOT_PRESENT \|\| rc == VERR_PAGE_TABLE_NOT_PRESENT);
2017	cb -= PAGE_SIZE;
2018	GCPhys += PAGE_SIZE;
2019	}
2020	}
2021	#endif
2022	return rc;
2023	}
2024	#endif /* !IN_RC */
2025

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source: vbox/trunk/src/VBox/VMM/VMMAll/IOMAllMMIO.cpp@ 20563

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