IOMAllMMIO.cpp@ 6537

Last change on this file since 6537 was 5999, checked in by vboxsync, 17 years ago
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1	/* $Id: IOMAllMMIO.cpp 5999 2007-12-07 15:05:06Z vboxsync $ */
2	/** @file
3	* IOM - Input / Output Monitor - Guest Context.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 innotek GmbH
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*******************************************************************************
20	* Header Files *
21	*******************************************************************************/
22	#define LOG_GROUP LOG_GROUP_IOM
23	#include <VBox/iom.h>
24	#include <VBox/cpum.h>
25	#include <VBox/pgm.h>
26	#include <VBox/selm.h>
27	#include <VBox/mm.h>
28	#include <VBox/em.h>
29	#include <VBox/pgm.h>
30	#include <VBox/trpm.h>
31	#include "IOMInternal.h"
32	#include <VBox/vm.h>
33
34	#include <VBox/dis.h>
35	#include <VBox/disopcode.h>
36	#include <VBox/param.h>
37	#include <VBox/err.h>
38	#include <iprt/assert.h>
39	#include <VBox/log.h>
40	#include <iprt/asm.h>
41	#include <iprt/string.h>
42
43	/*******************************************************************************
44	* Internal Functions *
45	*******************************************************************************/
46	static bool iomGCGetRegImmData(PDISCPUSTATE pCpu, PCOP_PARAMETER pParam, PCPUMCTXCORE pRegFrame, uint32_t pu32Data, unsigned pcbSize);
47	static bool iomGCSaveDataToReg(PDISCPUSTATE pCpu, PCOP_PARAMETER pParam, PCPUMCTXCORE pRegFrame, uint32_t u32Data);
48
49
50	/*******************************************************************************
51	* Global Variables *
52	*******************************************************************************/
53	/**
54	* Array for accessing 32-bit general registers in VMMREGFRAME structure
55	* by register's index from disasm.
56	*/
57	static unsigned g_aReg32Index[] =
58	{
59	RT_OFFSETOF(CPUMCTXCORE, eax), /* USE_REG_EAX */
60	RT_OFFSETOF(CPUMCTXCORE, ecx), /* USE_REG_ECX */
61	RT_OFFSETOF(CPUMCTXCORE, edx), /* USE_REG_EDX */
62	RT_OFFSETOF(CPUMCTXCORE, ebx), /* USE_REG_EBX */
63	RT_OFFSETOF(CPUMCTXCORE, esp), /* USE_REG_ESP */
64	RT_OFFSETOF(CPUMCTXCORE, ebp), /* USE_REG_EBP */
65	RT_OFFSETOF(CPUMCTXCORE, esi), /* USE_REG_ESI */
66	RT_OFFSETOF(CPUMCTXCORE, edi) /* USE_REG_EDI */
67	};
68
69	/**
70	* Macro for accessing 32-bit general purpose registers in CPUMCTXCORE structure.
71	*/
72	#define ACCESS_REG32(p, idx) (((uint32_t )((char *)(p) + g_aReg32Index[idx])))
73
74	/**
75	* Array for accessing 16-bit general registers in CPUMCTXCORE structure
76	* by register's index from disasm.
77	*/
78	static unsigned g_aReg16Index[] =
79	{
80	RT_OFFSETOF(CPUMCTXCORE, eax), /* USE_REG_AX */
81	RT_OFFSETOF(CPUMCTXCORE, ecx), /* USE_REG_CX */
82	RT_OFFSETOF(CPUMCTXCORE, edx), /* USE_REG_DX */
83	RT_OFFSETOF(CPUMCTXCORE, ebx), /* USE_REG_BX */
84	RT_OFFSETOF(CPUMCTXCORE, esp), /* USE_REG_SP */
85	RT_OFFSETOF(CPUMCTXCORE, ebp), /* USE_REG_BP */
86	RT_OFFSETOF(CPUMCTXCORE, esi), /* USE_REG_SI */
87	RT_OFFSETOF(CPUMCTXCORE, edi) /* USE_REG_DI */
88	};
89
90	/**
91	* Macro for accessing 16-bit general purpose registers in CPUMCTXCORE structure.
92	*/
93	#define ACCESS_REG16(p, idx) (((uint16_t )((char *)(p) + g_aReg16Index[idx])))
94
95	/**
96	* Array for accessing 8-bit general registers in CPUMCTXCORE structure
97	* by register's index from disasm.
98	*/
99	static unsigned g_aReg8Index[] =
100	{
101	RT_OFFSETOF(CPUMCTXCORE, eax), /* USE_REG_AL */
102	RT_OFFSETOF(CPUMCTXCORE, ecx), /* USE_REG_CL */
103	RT_OFFSETOF(CPUMCTXCORE, edx), /* USE_REG_DL */
104	RT_OFFSETOF(CPUMCTXCORE, ebx), /* USE_REG_BL */
105	RT_OFFSETOF(CPUMCTXCORE, eax) + 1, /* USE_REG_AH */
106	RT_OFFSETOF(CPUMCTXCORE, ecx) + 1, /* USE_REG_CH */
107	RT_OFFSETOF(CPUMCTXCORE, edx) + 1, /* USE_REG_DH */
108	RT_OFFSETOF(CPUMCTXCORE, ebx) + 1 /* USE_REG_BH */
109	};
110
111	/**
112	* Macro for accessing 8-bit general purpose registers in CPUMCTXCORE structure.
113	*/
114	#define ACCESS_REG8(p, idx) (((uint8_t )((char *)(p) + g_aReg8Index[idx])))
115
116	/**
117	* Array for accessing segment registers in CPUMCTXCORE structure
118	* by register's index from disasm.
119	*/
120	static unsigned g_aRegSegIndex[] =
121	{
122	RT_OFFSETOF(CPUMCTXCORE, es), /* USE_REG_ES */
123	RT_OFFSETOF(CPUMCTXCORE, cs), /* USE_REG_CS */
124	RT_OFFSETOF(CPUMCTXCORE, ss), /* USE_REG_SS */
125	RT_OFFSETOF(CPUMCTXCORE, ds), /* USE_REG_DS */
126	RT_OFFSETOF(CPUMCTXCORE, fs), /* USE_REG_FS */
127	RT_OFFSETOF(CPUMCTXCORE, gs) /* USE_REG_GS */
128	};
129
130	/**
131	* Macro for accessing segment registers in CPUMCTXCORE structure.
132	*/
133	#define ACCESS_REGSEG(p, idx) (((uint16_t )((char *)(p) + g_aRegSegIndex[idx])))
134
135	/**
136	* Array for fast recode of the operand size (1/2/4/8 bytes) to bit shift value.
137	*/
138	static const unsigned g_aSize2Shift[] =
139	{
140	~0, /* 0 - invalid */
141	0, /* 1 == 2^0 /
142	1, /* 2 == 2^1 /
143	~0, /* 3 - invalid */
144	2, /* 4 == 2^2 /
145	~0, /* 5 - invalid */
146	~0, /* 6 - invalid */
147	~0, /* 7 - invalid */
148	3 /* 8 == 2^3 /
149	};
150
151	/**
152	* Macro for fast recode of the operand size (1/2/4/8 bytes) to bit shift value.
153	*/
154	#define SIZE2SHIFT(cb) (g_aSize2Shift[cb])
155
156
157	/**
158	* Wrapper which does the write and updates range statistics when such are enabled.
159	* @warning VBOX_SUCCESS(rc=VINF_IOM_HC_MMIO_WRITE) is TRUE!
160	*/
161	inline int iomGCMMIODoWrite(PVM pVM, CTXALLSUFF(PIOMMMIORANGE) pRange, RTGCPHYS GCPhysFault, const void *pvData, unsigned cbSize)
162	{
163	#ifdef VBOX_WITH_STATISTICS
164	if (pRange->cbSize <= PAGE_SIZE)
165	{
166	PIOMMMIOSTATS pStats = iomMMIOGetStats(&pVM->iom.s, GCPhysFault);
167	if (!pStats)
168	return VINF_IOM_HC_MMIO_WRITE;
169
170	int rc = pRange->pfnWriteCallback(pRange->pDevIns, pRange->pvUser, GCPhysFault, (void )pvData, cbSize); / @todo fix const!! */
171	if (rc != VINF_IOM_HC_MMIO_WRITE)
172	STAM_COUNTER_INC(&pStats->WriteGC);
173	return rc;
174	}
175	#endif
176	return pRange->pfnWriteCallback(pRange->pDevIns, pRange->pvUser, GCPhysFault, (void *)pvData, cbSize);
177	}
178
179	/**
180	* Wrapper which does the read and updates range statistics when such are enabled.
181	*/
182	inline int iomGCMMIODoRead(PVM pVM, CTXALLSUFF(PIOMMMIORANGE) pRange, RTGCPHYS GCPhysFault, void *pvData, unsigned cbSize)
183	{
184	#ifdef VBOX_WITH_STATISTICS
185	if (pRange->cbSize <= PAGE_SIZE)
186	{
187	PIOMMMIOSTATS pStats = iomMMIOGetStats(&pVM->iom.s, GCPhysFault);
188	if (!pStats)
189	return VINF_IOM_HC_MMIO_READ;
190
191	int rc = pRange->pfnReadCallback(pRange->pDevIns, pRange->pvUser, GCPhysFault, pvData, cbSize);
192	if (rc != VINF_IOM_HC_MMIO_READ)
193	STAM_COUNTER_INC(&pStats->ReadGC);
194	return rc;
195	}
196	#endif
197	return pRange->pfnReadCallback(pRange->pDevIns, pRange->pvUser, GCPhysFault, pvData, cbSize);
198	}
199
200
201	/**
202	* Returns the contents of register or immediate data of instruction's parameter.
203	*
204	* @returns true on success.
205	*
206	* @param pCpu Pointer to current disassembler context.
207	* @param pParam Pointer to parameter of instruction to proccess.
208	* @param pRegFrame Pointer to CPUMCTXCORE guest structure.
209	* @param pu32Data Where to store retrieved data.
210	* @param pcbSize Where to store the size of data (1, 2, 4).
211	*/
212	static bool iomGCGetRegImmData(PDISCPUSTATE pCpu, PCOP_PARAMETER pParam, PCPUMCTXCORE pRegFrame, uint32_t pu32Data, unsigned pcbSize)
213	{
214	if (pParam->flags & (USE_BASE \| USE_INDEX \| USE_SCALE \| USE_DISPLACEMENT8 \| USE_DISPLACEMENT16 \| USE_DISPLACEMENT32))
215	{
216	*pcbSize = 0;
217	*pu32Data = 0;
218	return false;
219	}
220
221	if (pParam->flags & USE_REG_GEN32)
222	{
223	*pcbSize = 4;
224	*pu32Data = ACCESS_REG32(pRegFrame, pParam->base.reg_gen32);
225	return true;
226	}
227
228	if (pParam->flags & USE_REG_GEN16)
229	{
230	*pcbSize = 2;
231	*pu32Data = ACCESS_REG16(pRegFrame, pParam->base.reg_gen16);
232	return true;
233	}
234
235	if (pParam->flags & USE_REG_GEN8)
236	{
237	*pcbSize = 1;
238	*pu32Data = ACCESS_REG8(pRegFrame, pParam->base.reg_gen8);
239	return true;
240	}
241
242	if (pParam->flags & (USE_IMMEDIATE32\|USE_IMMEDIATE32_SX8))
243	{
244	*pcbSize = 4;
245	*pu32Data = (uint32_t)pParam->parval;
246	return true;
247	}
248
249	if (pParam->flags & (USE_IMMEDIATE16\|USE_IMMEDIATE16_SX8))
250	{
251	*pcbSize = 2;
252	*pu32Data = (uint16_t)pParam->parval;
253	return true;
254	}
255
256	if (pParam->flags & USE_IMMEDIATE8)
257	{
258	*pcbSize = 1;
259	*pu32Data = (uint8_t)pParam->parval;
260	return true;
261	}
262
263	if (pParam->flags & USE_REG_SEG)
264	{
265	*pcbSize = 2;
266	*pu32Data = ACCESS_REGSEG(pRegFrame, pParam->base.reg_seg);
267	return true;
268	} /* Else - error. */
269
270	*pcbSize = 0;
271	*pu32Data = 0;
272	return false;
273	}
274
275
276	/**
277	* Saves data to 8/16/32 general purpose or segment register defined by
278	* instruction's parameter.
279	*
280	* @returns true on success.
281	* @param pCpu Pointer to current disassembler context.
282	* @param pParam Pointer to parameter of instruction to proccess.
283	* @param pRegFrame Pointer to CPUMCTXCORE guest structure.
284	* @param u32Data 8/16/32 bit data to store.
285	*/
286	static bool iomGCSaveDataToReg(PDISCPUSTATE pCpu, PCOP_PARAMETER pParam, PCPUMCTXCORE pRegFrame, unsigned u32Data)
287	{
288	if (pParam->flags & (USE_BASE \| USE_INDEX \| USE_SCALE \| USE_DISPLACEMENT8 \| USE_DISPLACEMENT16 \| USE_DISPLACEMENT32 \| USE_IMMEDIATE8 \| USE_IMMEDIATE16 \| USE_IMMEDIATE32 \| USE_IMMEDIATE32_SX8 \| USE_IMMEDIATE16_SX8))
289	{
290	return false;
291	}
292
293	if (pParam->flags & USE_REG_GEN32)
294	{
295	ACCESS_REG32(pRegFrame, pParam->base.reg_gen32) = u32Data;
296	return true;
297	}
298
299	if (pParam->flags & USE_REG_GEN16)
300	{
301	ACCESS_REG16(pRegFrame, pParam->base.reg_gen16) = (uint16_t)u32Data;
302	return true;
303	}
304
305	if (pParam->flags & USE_REG_GEN8)
306	{
307	ACCESS_REG8(pRegFrame, pParam->base.reg_gen8) = (uint8_t)u32Data;
308	return true;
309	}
310
311	if (pParam->flags & USE_REG_SEG)
312	{
313	ACCESS_REGSEG(pRegFrame, pParam->base.reg_seg) = (uint16_t)u32Data;
314	return true;
315	}
316
317	/* Else - error. */
318	return false;
319	}
320
321
322	/*
323	* Internal - statistics only.
324	*/
325	inline void iomGCMMIOStatLength(PVM pVM, unsigned cb)
326	{
327	#ifdef VBOX_WITH_STATISTICS
328	switch (cb)
329	{
330	case 1:
331	STAM_COUNTER_INC(&pVM->iom.s.StatGCMMIO1Byte);
332	break;
333	case 2:
334	STAM_COUNTER_INC(&pVM->iom.s.StatGCMMIO2Bytes);
335	break;
336	case 4:
337	STAM_COUNTER_INC(&pVM->iom.s.StatGCMMIO4Bytes);
338	break;
339	default:
340	/* No way. */
341	AssertMsgFailed(("Invalid data length %d\n", cb));
342	break;
343	}
344	#else
345	NOREF(pVM); NOREF(cb);
346	#endif
347	}
348
349
350	/**
351	* MOV reg, mem (read)
352	* MOVZX reg, mem (read)
353	* MOVSX reg, mem (read)
354	*
355	* @returns VBox status code.
356	*
357	* @param pVM The virtual machine (GC pointer ofcourse).
358	* @param pRegFrame Pointer to CPUMCTXCORE guest registers structure.
359	* @param pCpu Disassembler CPU state.
360	* @param pRange Pointer MMIO range.
361	* @param GCPhysFault The GC physical address corresponding to pvFault.
362	*/
363	static int iomGCInterpretMOVxXRead(PVM pVM, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu, CTXALLSUFF(PIOMMMIORANGE) pRange, RTGCPHYS GCPhysFault)
364	{
365	/*
366	* If no read handler then go to ring-3 and handle it there.
367	*/
368	if (!pRange->pfnReadCallback)
369	return VINF_IOM_HC_MMIO_READ;
370
371	/*
372	* Get the data size from parameter 2,
373	* and call the handler function to get the data.
374	*/
375	unsigned cbSize = DISGetParamSize(pCpu, &pCpu->param2);
376	AssertMsg(cbSize > 0 && cbSize <= sizeof(uint32_t), ("cbSize=%d\n", cbSize));
377
378	uint32_t u32Data = 0;
379	int rc = iomGCMMIODoRead(pVM, pRange, GCPhysFault, &u32Data, cbSize);
380	if (rc == VINF_SUCCESS)
381	{
382	/*
383	* Do sign extension for MOVSX.
384	*/
385	/** @todo checkup MOVSX implementation! */
386	if (pCpu->pCurInstr->opcode == OP_MOVSX)
387	{
388	if (cbSize == 1)
389	{
390	/* DWORD <- BYTE */
391	int32_t iData = (int8_t)u32Data;
392	u32Data = (uint32_t)iData;
393	}
394	else
395	{
396	/* DWORD <- WORD */
397	int32_t iData = (int16_t)u32Data;
398	u32Data = (uint32_t)iData;
399	}
400	}
401
402	/*
403	* Store the result to register (parameter 1).
404	*/
405	bool fRc = iomGCSaveDataToReg(pCpu, &pCpu->param1, pRegFrame, u32Data);
406	AssertMsg(fRc, ("Failed to store register value!\n")); NOREF(fRc);
407	}
408
409	if (rc == VINF_SUCCESS)
410	iomGCMMIOStatLength(pVM, cbSize);
411	return rc;
412	}
413
414
415	/**
416	* MOV mem, reg\|imm (write)
417	*
418	* @returns VBox status code.
419	*
420	* @param pVM The virtual machine (GC pointer ofcourse).
421	* @param pRegFrame Pointer to CPUMCTXCORE guest registers structure.
422	* @param pCpu Disassembler CPU state.
423	* @param pRange Pointer MMIO range.
424	* @param GCPhysFault The GC physical address corresponding to pvFault.
425	*/
426	static int iomGCInterpretMOVxXWrite(PVM pVM, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu, CTXALLSUFF(PIOMMMIORANGE) pRange, RTGCPHYS GCPhysFault)
427	{
428	/*
429	* If no write handler then go to ring-3 and handle it there.
430	*/
431	if (!pRange->pfnWriteCallback)
432	return VINF_IOM_HC_MMIO_WRITE;
433
434	/*
435	* Get data to write from second parameter,
436	* and call the callback to write it.
437	*/
438	unsigned cbSize = 0;
439	uint32_t u32Data = 0;
440	bool fRc = iomGCGetRegImmData(pCpu, &pCpu->param2, pRegFrame, &u32Data, &cbSize);
441	AssertMsg(fRc, ("Failed to get reg/imm port number!\n")); NOREF(fRc);
442
443	int rc = iomGCMMIODoWrite(pVM, pRange, GCPhysFault, &u32Data, cbSize);
444	if (rc == VINF_SUCCESS)
445	iomGCMMIOStatLength(pVM, cbSize);
446	return rc;
447	}
448
449
450	/** @todo All the string MMIO stuff can do terrible things since physical contiguous mappings are
451	* assumed all over the place! This must be addressed in a general way, like for example let EM do
452	* all the interpretation and checking of selectors and addresses.
453	*
454	* -> I don't see the problem here. MMIO ranges are by definition linear ranges. The virtual source or destination is read/written properly.
455	*/
456
457
458	DECLINLINE(int) iomRamRead(PVM pVM, void *pDest, RTGCPTR GCSrc, uint32_t cb)
459	{
460	#ifdef IN_GC
461	return MMGCRamReadNoTrapHandler(pDest, GCSrc, cb);
462	#else
463	return PGMPhysReadGCPtrSafe(pVM, pDest, GCSrc, cb);
464	#endif
465	}
466
467	DECLINLINE(int) iomRamWrite(PVM pVM, RTGCPTR GCDest, void *pSrc, uint32_t cb)
468	{
469	#ifdef IN_GC
470	return MMGCRamWriteNoTrapHandler(GCDest, pSrc, cb);
471	#else
472	return PGMPhysWriteGCPtrSafe(pVM, GCDest, pSrc, cb);
473	#endif
474	}
475
476	/**
477	* [REP] MOVSB
478	* [REP] MOVSW
479	* [REP] MOVSD
480	*
481	* Restricted implementation.
482	*
483	*
484	* @returns VBox status code.
485	*
486	* @param pVM The virtual machine (GC pointer ofcourse).
487	* @param uErrorCode CPU Error code.
488	* @param pRegFrame Trap register frame.
489	* @param GCPhysFault The GC physical address corresponding to pvFault.
490	* @param pCpu Disassembler CPU state.
491	* @param pRange Pointer MMIO range.
492	*/
493	#ifdef IOMGC_MOVS_SUPPORT
494	static int iomGCInterpretMOVS(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, PDISCPUSTATE pCpu, CTXALLSUFF(PIOMMMIORANGE) pRange)
495	{
496	STAM_PROFILE_START(&pVM->iom.s.StatGCInstMovs, a);
497
498	/*
499	* We do not support segment prefixes or REPNE.
500	*/
501	if (pCpu->prefix & (PREFIX_SEG \| PREFIX_REPNE))
502	return VINF_IOM_HC_MMIO_READ_WRITE;
503
504
505	/*
506	* Get bytes/words/dwords count to copy.
507	*/
508	uint32_t cTransfers = 1;
509	if (pCpu->prefix & PREFIX_REP)
510	{
511	cTransfers = pRegFrame->ecx;
512	if (!SELMIsSelector32Bit(pVM, pRegFrame->eflags, pRegFrame->cs, &pRegFrame->csHid))
513	cTransfers &= 0xffff;
514
515	if (!cTransfers)
516	return VINF_SUCCESS;
517	}
518
519	/* Get the current privilege level. */
520	uint32_t cpl = CPUMGetGuestCPL(pVM, pRegFrame);
521
522	/*
523	* Get data size.
524	*/
525	unsigned cbSize = DISGetParamSize(pCpu, &pCpu->param1);
526	Assert(cbSize);
527	int offIncrement = pRegFrame->eflags.Bits.u1DF ? -(signed)cbSize : (signed)cbSize;
528
529	#ifdef VBOX_WITH_STATISTICS
530	if (pVM->iom.s.cMovsMaxBytes < (cTransfers << SIZE2SHIFT(cbSize)))
531	pVM->iom.s.cMovsMaxBytes = cTransfers << SIZE2SHIFT(cbSize);
532	#endif
533
534	RTGCPHYS Phys = GCPhysFault;
535	int rc;
536	if (uErrorCode & X86_TRAP_PF_RW)
537	{
538	/*
539	* Write operation: [Mem] -> [MMIO]
540	* ds:esi (Virt Src) -> es:edi (Phys Dst)
541	*/
542	STAM_PROFILE_START(&pVM->iom.s.StatGCInstMovsToMMIO, a2);
543
544	/* Check callback. */
545	if (!pRange->pfnWriteCallback)
546	{
547	STAM_PROFILE_STOP(&pVM->iom.s.StatGCInstMovsToMMIO, a2);
548	return VINF_IOM_HC_MMIO_WRITE;
549	}
550
551	/* Convert source address ds:esi. */
552	RTGCUINTPTR pu8Virt;
553	rc = SELMToFlatEx(pVM, pRegFrame->eflags, pRegFrame->ds, (RTGCPTR)pRegFrame->esi, &pRegFrame->dsHid,
554	SELMTOFLAT_FLAGS_HYPER \| SELMTOFLAT_FLAGS_NO_PL,
555	(PRTGCPTR)&pu8Virt, NULL);
556	if (VBOX_SUCCESS(rc))
557	{
558
559	/* Access verification first; we currently can't recover properly from traps inside this instruction */
560	rc = PGMVerifyAccess(pVM, pu8Virt, cTransfers * cbSize, (cpl == 3) ? X86_PTE_US : 0);
561	if (rc != VINF_SUCCESS)
562	{
563	Log(("MOVS will generate a trap -> recompiler, rc=%d\n", rc));
564	STAM_PROFILE_STOP(&pVM->iom.s.StatGCInstMovsToMMIO, a2);
565	return VINF_EM_RAW_EMULATE_INSTR;
566	}
567
568	#ifdef IN_GC
569	MMGCRamRegisterTrapHandler(pVM);
570	#endif
571
572	/* copy loop. */
573	while (cTransfers)
574	{
575	uint32_t u32Data = 0;
576	rc = iomRamRead(pVM, &u32Data, (RTGCPTR)pu8Virt, cbSize);
577	if (rc != VINF_SUCCESS)
578	break;
579	rc = iomGCMMIODoWrite(pVM, pRange, Phys, &u32Data, cbSize);
580	if (rc != VINF_SUCCESS)
581	break;
582
583	pu8Virt += offIncrement;
584	Phys += offIncrement;
585	pRegFrame->esi += offIncrement;
586	pRegFrame->edi += offIncrement;
587	cTransfers--;
588	}
589	#ifdef IN_GC
590	MMGCRamDeregisterTrapHandler(pVM);
591	#endif
592	/* Update ecx. */
593	if (pCpu->prefix & PREFIX_REP)
594	pRegFrame->ecx = cTransfers;
595	STAM_PROFILE_STOP(&pVM->iom.s.StatGCInstMovsToMMIO, a2);
596	}
597	else
598	rc = VINF_IOM_HC_MMIO_READ_WRITE;
599	}
600	else
601	{
602	/*
603	* Read operation: [MMIO] -> [mem] or [MMIO] -> [MMIO]
604	* ds:[eSI] (Phys Src) -> es:[eDI] (Virt Dst)
605	*/
606	/* Check callback. */
607	if (!pRange->pfnReadCallback)
608	return VINF_IOM_HC_MMIO_READ;
609
610	/* Convert destination address. */
611	RTGCUINTPTR pu8Virt;
612	rc = SELMToFlatEx(pVM, pRegFrame->eflags, pRegFrame->es, (RTGCPTR)pRegFrame->edi, &pRegFrame->esHid,
613	SELMTOFLAT_FLAGS_HYPER \| SELMTOFLAT_FLAGS_NO_PL,
614	(RTGCPTR *)&pu8Virt, NULL);
615	if (VBOX_FAILURE(rc))
616	return VINF_EM_RAW_GUEST_TRAP;
617
618	/* Check if destination address is MMIO. */
619	RTGCPHYS PhysDst;
620	rc = PGMGstGetPage(pVM, (RTGCPTR)pu8Virt, NULL, &PhysDst);
621	if ( VBOX_SUCCESS(rc)
622	&& iomMMIOGetRangeHC(&pVM->iom.s, PhysDst))
623	{
624	/*
625	* Extra: [MMIO] -> [MMIO]
626	*/
627	STAM_PROFILE_START(&pVM->iom.s.StatGCInstMovsMMIO, d);
628	STAM_PROFILE_START(&pVM->iom.s.StatGCInstMovsFromMMIO, c);
629
630	PhysDst \|= (RTGCUINTPTR)pu8Virt & PAGE_OFFSET_MASK;
631	CTXALLSUFF(PIOMMMIORANGE) pMMIODst = iomMMIOGetRange(&pVM->iom.s, PhysDst);
632	if ( !pMMIODst
633	\|\| !pMMIODst->pfnWriteCallback)
634	{
635	STAM_PROFILE_STOP(&pVM->iom.s.StatGCInstMovsMMIO, d);
636	STAM_PROFILE_STOP(&pVM->iom.s.StatGCInstMovsFromMMIO, c);
637	return VINF_IOM_HC_MMIO_READ_WRITE;
638	}
639
640	/* copy loop. */
641	while (cTransfers)
642	{
643	uint32_t u32Data;
644	rc = iomGCMMIODoRead(pVM, pRange, Phys, &u32Data, cbSize);
645	if (rc != VINF_SUCCESS)
646	break;
647	rc = iomGCMMIODoWrite(pVM, pMMIODst, PhysDst, &u32Data, cbSize);
648	if (rc != VINF_SUCCESS)
649	break;
650
651	Phys += offIncrement;
652	PhysDst += offIncrement;
653	pRegFrame->esi += offIncrement;
654	pRegFrame->edi += offIncrement;
655	cTransfers--;
656	}
657	STAM_PROFILE_STOP(&pVM->iom.s.StatGCInstMovsMMIO, d);
658	STAM_PROFILE_STOP(&pVM->iom.s.StatGCInstMovsFromMMIO, c);
659	}
660	else
661	{
662	/*
663	* Normal: [MMIO] -> [Mem]
664	*/
665	STAM_PROFILE_START(&pVM->iom.s.StatGCInstMovsFromMMIO, c);
666
667	/* Access verification first; we currently can't recover properly from traps inside this instruction */
668	rc = PGMVerifyAccess(pVM, pu8Virt, cTransfers * cbSize, X86_PTE_RW \| ((cpl == 3) ? X86_PTE_US : 0));
669	if (rc != VINF_SUCCESS)
670	{
671	Log(("MOVS will generate a trap -> recompiler, rc=%d\n", rc));
672	STAM_PROFILE_STOP(&pVM->iom.s.StatGCInstMovsFromMMIO, c);
673	return VINF_EM_RAW_EMULATE_INSTR;
674	}
675
676	/* copy loop. */
677	#ifdef IN_GC
678	MMGCRamRegisterTrapHandler(pVM);
679	#endif
680	while (cTransfers)
681	{
682	uint32_t u32Data;
683	rc = iomGCMMIODoRead(pVM, pRange, Phys, &u32Data, cbSize);
684	if (rc != VINF_SUCCESS)
685	break;
686	rc = iomRamWrite(pVM, (RTGCPTR)pu8Virt, &u32Data, cbSize);
687	if (rc != VINF_SUCCESS)
688	{
689	Log(("iomRamWrite %08X size=%d failed with %d\n", pu8Virt, cbSize, rc));
690	break;
691	}
692
693	pu8Virt += offIncrement;
694	Phys += offIncrement;
695	pRegFrame->esi += offIncrement;
696	pRegFrame->edi += offIncrement;
697	cTransfers--;
698	}
699	#ifdef IN_GC
700	MMGCRamDeregisterTrapHandler(pVM);
701	#endif
702	STAM_PROFILE_STOP(&pVM->iom.s.StatGCInstMovsFromMMIO, c);
703	}
704
705	/* Update ecx on exit. */
706	if (pCpu->prefix & PREFIX_REP)
707	pRegFrame->ecx = cTransfers;
708	}
709
710	/* work statistics. */
711	if (rc == VINF_SUCCESS)
712	{
713	STAM_PROFILE_STOP(&pVM->iom.s.StatGCInstMovs, a);
714	iomGCMMIOStatLength(pVM, cbSize);
715	}
716	return rc;
717	}
718	#endif
719
720
721
722	/**
723	* [REP] STOSB
724	* [REP] STOSW
725	* [REP] STOSD
726	*
727	* Restricted implementation.
728	*
729	*
730	* @returns VBox status code.
731	*
732	* @param pVM The virtual machine (GC pointer ofcourse).
733	* @param pRegFrame Trap register frame.
734	* @param GCPhysFault The GC physical address corresponding to pvFault.
735	* @param pCpu Disassembler CPU state.
736	* @param pRange Pointer MMIO range.
737	*/
738	static int iomGCInterpretSTOS(PVM pVM, PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, PDISCPUSTATE pCpu, CTXALLSUFF(PIOMMMIORANGE) pRange)
739	{
740	STAM_PROFILE_START(&pVM->iom.s.StatGCInstStos, a);
741
742	/*
743	* We do not support segment prefixes or REPNE..
744	*/
745	if (pCpu->prefix & (PREFIX_SEG \| PREFIX_REPNE))
746	return VINF_IOM_HC_MMIO_READ_WRITE;
747
748	/*
749	* Get bytes/words/dwords count to copy.
750	*/
751	uint32_t cTransfers = 1;
752	if (pCpu->prefix & PREFIX_REP)
753	{
754	cTransfers = pRegFrame->ecx;
755	if (!SELMIsSelector32Bit(pVM, pRegFrame->eflags, pRegFrame->cs, &pRegFrame->csHid))
756	cTransfers &= 0xffff;
757
758	if (!cTransfers)
759	return VINF_SUCCESS;
760	}
761
762	/*
763	* Get data size.
764	*/
765	unsigned cbSize = DISGetParamSize(pCpu, &pCpu->param1);
766	Assert(cbSize);
767	int offIncrement = pRegFrame->eflags.Bits.u1DF ? -(signed)cbSize : (signed)cbSize;
768
769	#ifdef VBOX_WITH_STATISTICS
770	if (pVM->iom.s.cStosMaxBytes < (cTransfers << SIZE2SHIFT(cbSize)))
771	pVM->iom.s.cStosMaxBytes = cTransfers << SIZE2SHIFT(cbSize);
772	#endif
773
774
775	RTGCPHYS Phys = GCPhysFault;
776	uint32_t u32Data = pRegFrame->eax;
777	int rc;
778	if (pRange->pfnFillCallback)
779	{
780	/*
781	* Use the fill callback.
782	*/
783	/** @todo pfnFillCallback must return number of bytes successfully written!!! */
784	if (offIncrement > 0)
785	{
786	/* addr++ variant. */
787	rc = pRange->pfnFillCallback(pRange->pDevIns, pRange->pvUser, Phys, u32Data, cbSize, cTransfers);
788	if (rc == VINF_SUCCESS)
789	{
790	/* Update registers. */
791	pRegFrame->edi += cTransfers << SIZE2SHIFT(cbSize);
792	if (pCpu->prefix & PREFIX_REP)
793	pRegFrame->ecx = 0;
794	}
795	}
796	else
797	{
798	/* addr-- variant. */
799	rc = pRange->pfnFillCallback(pRange->pDevIns, pRange->pvUser, (Phys - (cTransfers - 1)) << SIZE2SHIFT(cbSize), u32Data, cbSize, cTransfers);
800	if (rc == VINF_SUCCESS)
801	{
802	/* Update registers. */
803	pRegFrame->edi -= cTransfers << SIZE2SHIFT(cbSize);
804	if (pCpu->prefix & PREFIX_REP)
805	pRegFrame->ecx = 0;
806	}
807	}
808	}
809	else
810	{
811	/*
812	* Use the write callback.
813	*/
814	/* Check write callback. */
815	if (!pRange->pfnWriteCallback)
816	return VINF_IOM_HC_MMIO_WRITE;
817
818	/* fill loop. */
819	do
820	{
821	rc = iomGCMMIODoWrite(pVM, pRange, Phys, &u32Data, cbSize);
822	if (rc != VINF_SUCCESS)
823	break;
824
825	Phys += offIncrement;
826	pRegFrame->edi += offIncrement;
827	cTransfers--;
828	} while (cTransfers);
829
830	/* Update ecx on exit. */
831	if (pCpu->prefix & PREFIX_REP)
832	pRegFrame->ecx = cTransfers;
833	}
834
835	/*
836	* Work statistics and return.
837	*/
838	if (rc == VINF_SUCCESS)
839	{
840	STAM_PROFILE_STOP(&pVM->iom.s.StatGCInstStos, a);
841	iomGCMMIOStatLength(pVM, cbSize);
842	}
843	return rc;
844	}
845
846
847	/**
848	* [REP] LODSB
849	* [REP] LODSW
850	* [REP] LODSD
851	*
852	* Restricted implementation.
853	*
854	*
855	* @returns VBox status code.
856	*
857	* @param pVM The virtual machine (GC pointer ofcourse).
858	* @param pRegFrame Trap register frame.
859	* @param GCPhysFault The GC physical address corresponding to pvFault.
860	* @param pCpu Disassembler CPU state.
861	* @param pRange Pointer MMIO range.
862	*/
863	static int iomGCInterpretLODS(PVM pVM, PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, PDISCPUSTATE pCpu, CTXALLSUFF(PIOMMMIORANGE) pRange)
864	{
865	STAM_PROFILE_START(&pVM->iom.s.StatGCInstLods, a1);
866
867	/*
868	* We do not support segment prefixes or REP*.
869	*/
870	if (pCpu->prefix & (PREFIX_SEG \| PREFIX_REP \| PREFIX_REPNE))
871	return VINF_IOM_HC_MMIO_READ_WRITE;
872
873	/* Check that we can handle it. */
874	if (!pRange->pfnReadCallback)
875	return VINF_IOM_HC_MMIO_READ;
876
877	/*
878	* Get data size.
879	*/
880	unsigned cbSize = DISGetParamSize(pCpu, &pCpu->param2);
881	Assert(cbSize);
882	int offIncrement = pRegFrame->eflags.Bits.u1DF ? -(signed)cbSize : (signed)cbSize;
883
884	/*
885	* Perform read.
886	*/
887	int rc = iomGCMMIODoRead(pVM, pRange, GCPhysFault, &pRegFrame->eax, cbSize);
888	if (rc == VINF_SUCCESS)
889	pRegFrame->esi += offIncrement;
890
891	/*
892	* Work statistics and return.
893	*/
894	if (rc == VINF_SUCCESS)
895	{
896	STAM_PROFILE_STOP(&pVM->iom.s.StatGCInstLods, a1);
897	iomGCMMIOStatLength(pVM, cbSize);
898	}
899	return rc;
900	}
901
902
903	/**
904	* CMP [MMIO], reg\|imm
905	* CMP reg\|imm, [MMIO]
906	*
907	* Restricted implementation.
908	*
909	*
910	* @returns VBox status code.
911	*
912	* @param pVM The virtual machine (GC pointer ofcourse).
913	* @param pRegFrame Trap register frame.
914	* @param GCPhysFault The GC physical address corresponding to pvFault.
915	* @param pCpu Disassembler CPU state.
916	* @param pRange Pointer MMIO range.
917	*/
918	static int iomGCInterpretCMP(PVM pVM, PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, PDISCPUSTATE pCpu, CTXALLSUFF(PIOMMMIORANGE) pRange)
919	{
920	STAM_PROFILE_START(&pVM->iom.s.StatGCInstCmp, a1);
921
922	/* Check read callback. */
923	if (!pRange->pfnReadCallback)
924	return VINF_EM_RAW_GUEST_TRAP;
925
926	/*
927	* Get the operands.
928	*/
929	unsigned cbSize = 0;
930	uint32_t uData1;
931	uint32_t uData2;
932	int rc;
933	if (iomGCGetRegImmData(pCpu, &pCpu->param1, pRegFrame, &uData1, &cbSize))
934	/* cmp reg, [MMIO]. */
935	rc = iomGCMMIODoRead(pVM, pRange, GCPhysFault, &uData2, cbSize);
936	else if (iomGCGetRegImmData(pCpu, &pCpu->param2, pRegFrame, &uData2, &cbSize))
937	/* cmp [MMIO], reg\|imm. */
938	rc = iomGCMMIODoRead(pVM, pRange, GCPhysFault, &uData1, cbSize);
939	else
940	{
941	AssertMsgFailed(("Disassember CMP problem..\n"));
942	rc = VERR_IOM_MMIO_HANDLER_DISASM_ERROR;
943	}
944
945	if (rc == VINF_SUCCESS)
946	{
947	/* Emulate CMP and update guest flags. */
948	uint32_t eflags = EMEmulateCmp(uData1, uData2, cbSize);
949	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
950	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
951
952	STAM_PROFILE_STOP(&pVM->iom.s.StatGCInstCmp, a1);
953	iomGCMMIOStatLength(pVM, cbSize);
954	}
955
956	return rc;
957	}
958
959
960	/**
961	* AND [MMIO], reg\|imm
962	* AND reg, [MMIO]
963	*
964	* Restricted implementation.
965	*
966	*
967	* @returns VBox status code.
968	*
969	* @param pVM The virtual machine (GC pointer ofcourse).
970	* @param pRegFrame Trap register frame.
971	* @param GCPhysFault The GC physical address corresponding to pvFault.
972	* @param pCpu Disassembler CPU state.
973	* @param pRange Pointer MMIO range.
974	*/
975	static int iomGCInterpretAND(PVM pVM, PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, PDISCPUSTATE pCpu, CTXALLSUFF(PIOMMMIORANGE) pRange)
976	{
977	STAM_PROFILE_START(&pVM->iom.s.StatGCInstAnd, a1);
978
979	/* Check read callback. */
980
981	unsigned cbSize = 0;
982	uint32_t uData1;
983	uint32_t uData2;
984	bool fAndWrite;
985	int rc;
986	if (iomGCGetRegImmData(pCpu, &pCpu->param1, pRegFrame, &uData1, &cbSize))
987	{
988	/* and reg, [MMIO]. */
989	fAndWrite = false;
990	if (pRange->pfnReadCallback)
991	rc = iomGCMMIODoRead(pVM, pRange, GCPhysFault, &uData2, cbSize);
992	else
993	rc = VINF_IOM_HC_MMIO_READ;
994	}
995	else if (iomGCGetRegImmData(pCpu, &pCpu->param2, pRegFrame, &uData2, &cbSize))
996	{
997	/* and [MMIO], reg\|imm. */
998	fAndWrite = true;
999	if (pRange->pfnReadCallback && pRange->pfnWriteCallback)
1000	rc = iomGCMMIODoRead(pVM, pRange, GCPhysFault, &uData1, cbSize);
1001	else
1002	rc = VINF_IOM_HC_MMIO_READ_WRITE;
1003	}
1004	else
1005	{
1006	AssertMsgFailed(("Disassember AND problem..\n"));
1007	return VERR_IOM_MMIO_HANDLER_DISASM_ERROR;
1008	}
1009
1010	if (rc == VINF_SUCCESS)
1011	{
1012	/* Emulate AND and update guest flags. */
1013	uint32_t eflags = EMEmulateAnd(&uData1, uData2, cbSize);
1014	if (fAndWrite)
1015	/* Store result to MMIO. */
1016	rc = iomGCMMIODoWrite(pVM, pRange, GCPhysFault, &uData1, cbSize);
1017	else
1018	{
1019	/* Store result to register. */
1020	bool fRc = iomGCSaveDataToReg(pCpu, &pCpu->param1, pRegFrame, uData1);
1021	AssertMsg(fRc, ("Failed to store register value!\n")); NOREF(fRc);
1022	}
1023	if (rc == VINF_SUCCESS)
1024	{
1025	/* Update guest's eflags and finish. */
1026	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
1027	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
1028	STAM_PROFILE_STOP(&pVM->iom.s.StatGCInstAnd, a1);
1029	iomGCMMIOStatLength(pVM, cbSize);
1030	}
1031	}
1032
1033	return rc;
1034	}
1035
1036
1037
1038	/**
1039	* TEST [MMIO], reg\|imm
1040	* TEST reg, [MMIO]
1041	*
1042	* Restricted implementation.
1043	*
1044	*
1045	* @returns VBox status code.
1046	*
1047	* @param pVM The virtual machine (GC pointer ofcourse).
1048	* @param pRegFrame Trap register frame.
1049	* @param GCPhysFault The GC physical address corresponding to pvFault.
1050	* @param pCpu Disassembler CPU state.
1051	* @param pRange Pointer MMIO range.
1052	*/
1053	static int iomGCInterpretTEST(PVM pVM, PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, PDISCPUSTATE pCpu, CTXALLSUFF(PIOMMMIORANGE) pRange)
1054	{
1055	STAM_PROFILE_START(&pVM->iom.s.StatGCInstTest, a1);
1056
1057	/* Check read callback. */
1058
1059	unsigned cbSize = 0;
1060	uint32_t uData1;
1061	uint32_t uData2;
1062	int rc;
1063
1064	if (iomGCGetRegImmData(pCpu, &pCpu->param1, pRegFrame, &uData1, &cbSize))
1065	{
1066	/* and test, [MMIO]. */
1067	if (pRange->pfnReadCallback)
1068	rc = iomGCMMIODoRead(pVM, pRange, GCPhysFault, &uData2, cbSize);
1069	else
1070	rc = VINF_IOM_HC_MMIO_READ;
1071	}
1072	else if (iomGCGetRegImmData(pCpu, &pCpu->param2, pRegFrame, &uData2, &cbSize))
1073	{
1074	/* test [MMIO], reg\|imm. */
1075	if (pRange->pfnReadCallback)
1076	rc = iomGCMMIODoRead(pVM, pRange, GCPhysFault, &uData1, cbSize);
1077	else
1078	rc = VINF_IOM_HC_MMIO_READ;
1079	}
1080	else
1081	{
1082	AssertMsgFailed(("Disassember TEST problem..\n"));
1083	return VERR_IOM_MMIO_HANDLER_DISASM_ERROR;
1084	}
1085
1086	if (rc == VINF_SUCCESS)
1087	{
1088	/* Emulate TEST (=AND without write back) and update guest EFLAGS. */
1089	uint32_t eflags = EMEmulateAnd(&uData1, uData2, cbSize);
1090	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
1091	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
1092	STAM_PROFILE_STOP(&pVM->iom.s.StatGCInstTest, a1);
1093	iomGCMMIOStatLength(pVM, cbSize);
1094	}
1095
1096	return rc;
1097	}
1098
1099	/**
1100	* XCHG [MMIO], reg
1101	* XCHG reg, [MMIO]
1102	*
1103	* Restricted implementation.
1104	*
1105	*
1106	* @returns VBox status code.
1107	*
1108	* @param pVM The virtual machine (GC pointer ofcourse).
1109	* @param pRegFrame Trap register frame.
1110	* @param GCPhysFault The GC physical address corresponding to pvFault.
1111	* @param pCpu Disassembler CPU state.
1112	* @param pRange Pointer MMIO range.
1113	*/
1114	static int iomGCInterpretXCHG(PVM pVM, PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, PDISCPUSTATE pCpu, CTXALLSUFF(PIOMMMIORANGE) pRange)
1115	{
1116	STAM_PROFILE_START(&pVM->iom.s.StatGCInstTest, a1);
1117
1118	/* Check read callback. */
1119	unsigned cbSize = 0;
1120	uint32_t uData1;
1121	uint32_t uData2;
1122	int rc;
1123
1124	if (!pRange->pfnReadCallback \|\| !pRange->pfnWriteCallback)
1125	{
1126	rc = VINF_IOM_HC_MMIO_READ;
1127	goto end;
1128	}
1129
1130	if (iomGCGetRegImmData(pCpu, &pCpu->param1, pRegFrame, &uData1, &cbSize))
1131	{
1132	/* xchg reg, [MMIO]. */
1133	rc = iomGCMMIODoRead(pVM, pRange, GCPhysFault, &uData2, cbSize);
1134	if (rc == VINF_SUCCESS)
1135	{
1136	/* Store result to MMIO. */
1137	rc = iomGCMMIODoWrite(pVM, pRange, GCPhysFault, &uData1, cbSize);
1138
1139	if (rc == VINF_SUCCESS)
1140	{
1141	/* Store result to register. */
1142	bool fRc = iomGCSaveDataToReg(pCpu, &pCpu->param1, pRegFrame, uData2);
1143	AssertMsg(fRc, ("Failed to store register value!\n")); NOREF(fRc);
1144	}
1145	else
1146	Assert(rc == VINF_IOM_HC_MMIO_WRITE \|\| rc == VINF_PATM_HC_MMIO_PATCH_WRITE);
1147	}
1148	else
1149	Assert(rc == VINF_IOM_HC_MMIO_READ \|\| rc == VINF_PATM_HC_MMIO_PATCH_READ);
1150	}
1151	else
1152	if (iomGCGetRegImmData(pCpu, &pCpu->param2, pRegFrame, &uData2, &cbSize))
1153	{
1154	/* xchg [MMIO], reg. */
1155	rc = iomGCMMIODoRead(pVM, pRange, GCPhysFault, &uData1, cbSize);
1156	if (rc == VINF_SUCCESS)
1157	{
1158	/* Store result to MMIO. */
1159	rc = iomGCMMIODoWrite(pVM, pRange, GCPhysFault, &uData2, cbSize);
1160
1161	if (rc == VINF_SUCCESS)
1162	{
1163	/* Store result to register. */
1164	bool fRc = iomGCSaveDataToReg(pCpu, &pCpu->param2, pRegFrame, uData1);
1165	AssertMsg(fRc, ("Failed to store register value!\n")); NOREF(fRc);
1166	}
1167	else
1168	Assert(rc == VINF_IOM_HC_MMIO_WRITE \|\| rc == VINF_PATM_HC_MMIO_PATCH_WRITE);
1169	}
1170	else
1171	Assert(rc == VINF_IOM_HC_MMIO_READ \|\| rc == VINF_PATM_HC_MMIO_PATCH_READ);
1172	}
1173	else
1174	{
1175	AssertMsgFailed(("Disassember XCHG problem..\n"));
1176	rc = VERR_IOM_MMIO_HANDLER_DISASM_ERROR;
1177	goto end;
1178	}
1179
1180	end:
1181	STAM_PROFILE_STOP(&pVM->iom.s.StatGCInstTest, a1);
1182	return rc;
1183	}
1184
1185
1186	#ifdef IN_RING0
1187
1188	/**
1189	* Read callback for disassembly function; supports reading bytes that cross a page boundary
1190	*
1191	* @returns VBox status code.
1192	* @param pSrc GC source pointer
1193	* @param pDest HC destination pointer
1194	* @param size Number of bytes to read
1195	* @param pvUserdata Callback specific user data (pCpu)
1196	*
1197	*/
1198	DECLCALLBACK(int) iomReadBytes(RTHCUINTPTR pSrc, uint8_t pDest, unsigned size, void pvUserdata)
1199	{
1200	DISCPUSTATE pCpu = (DISCPUSTATE )pvUserdata;
1201	PVM pVM = (PVM)pCpu->apvUserData[0];
1202
1203	int rc = PGMPhysReadGCPtr(pVM, pDest, pSrc, size);
1204	AssertRC(rc);
1205	return rc;
1206	}
1207
1208	inline bool iomDisCoreOne(PVM pVM, DISCPUSTATE pCpu, RTGCUINTPTR InstrGC, uint32_t pOpsize)
1209	{
1210	return VBOX_SUCCESS(DISCoreOneEx(InstrGC, pCpu->mode, iomReadBytes, pVM, pCpu, pOpsize));
1211	}
1212	#else
1213	inline bool iomDisCoreOne(PVM pVM, DISCPUSTATE pCpu, RTGCUINTPTR InstrGC, uint32_t pOpsize)
1214	{
1215	return VBOX_SUCCESS(DISCoreOne(pCpu, InstrGC, pOpsize));
1216	}
1217
1218	#endif
1219
1220	/**
1221	* \#PF Handler callback for MMIO ranges.
1222	* Note: we are on ring0 in Hypervisor and interrupts are disabled.
1223	*
1224	* @returns VBox status code (appropriate for GC return).
1225	* @param pVM VM Handle.
1226	* @param uErrorCode CPU Error code.
1227	* @param pRegFrame Trap register frame.
1228	* @param pvFault The fault address (cr2).
1229	* @param GCPhysFault The GC physical address corresponding to pvFault.
1230	* @param pvUser Pointer to the MMIO ring-3 range entry.
1231	*/
1232	IOMDECL(int) IOMMMIOHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, void pvFault, RTGCPHYS GCPhysFault, void pvUser)
1233	{
1234	STAM_PROFILE_START(&pVM->iom.s.StatGCMMIOHandler, a);
1235	NOREF(pvUser); /** @todo implement pvUser usage! */
1236	Log3(("IOMMMIOHandler: GCPhys=%RGp uErr=%#x pvFault=%p eip=%RGv\n",
1237	GCPhysFault, uErrorCode, pvFault, pRegFrame->eip));
1238
1239	/*
1240	* Find the corresponding MMIO range.
1241	*/
1242	CTXALLSUFF(PIOMMMIORANGE) pRange = iomMMIOGetRange(&pVM->iom.s, GCPhysFault);
1243	if (!pRange)
1244	{
1245	#ifdef VBOX_WITH_STATISTICS
1246	PIOMMMIOSTATS pStats = iomMMIOGetStats(&pVM->iom.s, GCPhysFault);
1247	if (pStats)
1248	{
1249	if (uErrorCode & X86_TRAP_PF_RW)
1250	STAM_COUNTER_INC(&pStats->WriteGCToR3);
1251	else
1252	STAM_COUNTER_INC(&pStats->ReadGCToR3);
1253	}
1254	#endif
1255	PIOMMMIORANGER3 pRangeR3 = iomMMIOGetRangeHC(&pVM->iom.s, GCPhysFault);
1256	if (pRangeR3)
1257	{
1258	STAM_PROFILE_START(&pVM->iom.s.StatGCMMIOHandler, a);
1259	STAM_COUNTER_INC(&pVM->iom.s.StatGCMMIOFailures);
1260	return (uErrorCode & X86_TRAP_PF_RW) ? VINF_IOM_HC_MMIO_WRITE : VINF_IOM_HC_MMIO_READ;
1261	}
1262
1263	/*
1264	* Now, why are we here...
1265	*/
1266	AssertMsgFailed(("Internal error! GCPhysFault=%x\n", GCPhysFault));
1267	return VERR_IOM_MMIO_HANDLER_BOGUS_CALL;
1268	}
1269
1270	/*
1271	* Convert CS:EIP to linear address and initialize the disassembler.
1272	*/
1273	DISCPUSTATE cpu;
1274	cpu.mode = SELMIsSelector32Bit(pVM, pRegFrame->eflags, pRegFrame->cs, &pRegFrame->csHid) ? CPUMODE_32BIT : CPUMODE_16BIT;
1275
1276	RTGCPTR pvCode;
1277	int rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)(cpu.mode == CPUMODE_32BIT ? pRegFrame->eip : pRegFrame->eip & 0xffff), &pvCode);
1278	if (VBOX_FAILURE(rc))
1279	{
1280	AssertMsgFailed(("Internal error! cs:eip=%04x:%08x rc=%Vrc\n", pRegFrame->cs, pRegFrame->eip, rc));
1281	return VERR_IOM_MMIO_HANDLER_BOGUS_CALL;
1282	}
1283
1284	/*
1285	* Disassemble the instruction and interprete it.
1286	*/
1287	unsigned cbOp;
1288	if (iomDisCoreOne(pVM, &cpu, (RTGCUINTPTR)pvCode, &cbOp))
1289	{
1290	switch (cpu.pCurInstr->opcode)
1291	{
1292	case OP_MOV:
1293	case OP_MOVZX:
1294	case OP_MOVSX:
1295	{
1296	STAM_PROFILE_START(&pVM->iom.s.StatGCInstMov, b);
1297	if (uErrorCode & X86_TRAP_PF_RW)
1298	rc = iomGCInterpretMOVxXWrite(pVM, pRegFrame, &cpu, pRange, GCPhysFault);
1299	else
1300	rc = iomGCInterpretMOVxXRead(pVM, pRegFrame, &cpu, pRange, GCPhysFault);
1301	if (rc == VINF_SUCCESS)
1302	STAM_PROFILE_STOP(&pVM->iom.s.StatGCInstMov, b);
1303	break;
1304	}
1305
1306
1307	#ifdef IOMGC_MOVS_SUPPORT
1308	case OP_MOVSB:
1309	case OP_MOVSWD:
1310	rc = iomGCInterpretMOVS(pVM, uErrorCode, pRegFrame, GCPhysFault, &cpu, pRange);
1311	break;
1312	#endif
1313
1314	case OP_STOSB:
1315	case OP_STOSWD:
1316	Assert(uErrorCode & X86_TRAP_PF_RW);
1317	rc = iomGCInterpretSTOS(pVM, pRegFrame, GCPhysFault, &cpu, pRange);
1318	break;
1319
1320	case OP_LODSB:
1321	case OP_LODSWD:
1322	Assert(!(uErrorCode & X86_TRAP_PF_RW));
1323	rc = iomGCInterpretLODS(pVM, pRegFrame, GCPhysFault, &cpu, pRange);
1324	break;
1325
1326
1327	case OP_CMP:
1328	Assert(!(uErrorCode & X86_TRAP_PF_RW));
1329	rc = iomGCInterpretCMP(pVM, pRegFrame, GCPhysFault, &cpu, pRange);
1330	break;
1331
1332	case OP_AND:
1333	rc = iomGCInterpretAND(pVM, pRegFrame, GCPhysFault, &cpu, pRange);
1334	break;
1335
1336	case OP_TEST:
1337	Assert(!(uErrorCode & X86_TRAP_PF_RW));
1338	rc = iomGCInterpretTEST(pVM, pRegFrame, GCPhysFault, &cpu, pRange);
1339	break;
1340
1341	case OP_XCHG:
1342	rc = iomGCInterpretXCHG(pVM, pRegFrame, GCPhysFault, &cpu, pRange);
1343	break;
1344
1345
1346	/*
1347	* The instruction isn't supported. Hand it on to ring-3.
1348	*/
1349	default:
1350	STAM_COUNTER_INC(&pVM->iom.s.StatGCInstOther);
1351	rc = (uErrorCode & X86_TRAP_PF_RW) ? VINF_IOM_HC_MMIO_WRITE : VINF_IOM_HC_MMIO_READ;
1352	break;
1353	}
1354	}
1355	else
1356	{
1357	AssertMsgFailed(("Disassembler freaked out!\n"));
1358	rc = VERR_IOM_MMIO_HANDLER_DISASM_ERROR;
1359	}
1360
1361	/*
1362	* On success advance EIP.
1363	*/
1364	if (rc == VINF_SUCCESS)
1365	pRegFrame->eip += cbOp;
1366	else
1367	{
1368	STAM_COUNTER_INC(&pVM->iom.s.StatGCMMIOFailures);
1369	#ifdef VBOX_WITH_STATISTICS
1370	switch (rc)
1371	{
1372	case VINF_IOM_HC_MMIO_READ:
1373	case VINF_IOM_HC_MMIO_WRITE:
1374	case VINF_IOM_HC_MMIO_READ_WRITE:
1375	{
1376	PIOMMMIOSTATS pStats = iomMMIOGetStats(&pVM->iom.s, GCPhysFault);
1377	if (pStats)
1378	{
1379	if (uErrorCode & X86_TRAP_PF_RW)
1380	STAM_COUNTER_INC(&pStats->WriteGCToR3);
1381	else
1382	STAM_COUNTER_INC(&pStats->ReadGCToR3);
1383	}
1384	}
1385	break;
1386	}
1387	#endif
1388	}
1389	STAM_PROFILE_STOP(&pVM->iom.s.StatGCMMIOHandler, a);
1390	return rc;
1391	}
1392
1393
1394	/**
1395	* Reads a MMIO register.
1396	*
1397	* @returns VBox status code.
1398	*
1399	* @param pVM VM handle.
1400	* @param GCPhys The physical address to read.
1401	* @param pu32Value Where to store the value read.
1402	* @param cbValue The size of the register to read in bytes. 1, 2 or 4 bytes.
1403	*/
1404	IOMDECL(int) IOMMMIORead(PVM pVM, RTGCPHYS GCPhys, uint32_t *pu32Value, size_t cbValue)
1405	{
1406	/** @todo add return to ring-3 statistics when this function is used in GC! */
1407
1408	/*
1409	* Lookup the current context range node and statistics.
1410	*/
1411	CTXALLSUFF(PIOMMMIORANGE) pRange = iomMMIOGetRange(&pVM->iom.s, GCPhys);
1412	#ifdef VBOX_WITH_STATISTICS
1413	PIOMMMIOSTATS pStats = iomMMIOGetStats(&pVM->iom.s, GCPhys);
1414	if (!pStats && (!pRange \|\| pRange->cbSize <= PAGE_SIZE))
1415	# ifdef IN_RING3
1416	pStats = iomR3MMIOStatsCreate(pVM, GCPhys, pRange ? pRange->pszDesc : NULL);
1417	# else
1418	return VINF_IOM_HC_MMIO_READ;
1419	# endif
1420	#endif /* VBOX_WITH_STATISTICS */
1421	#ifdef IN_RING3
1422	if (pRange)
1423	#else /* !IN_RING3 */
1424	if (pRange && pRange->pfnReadCallback)
1425	#endif /* !IN_RING3 */
1426	{
1427	/*
1428	* Perform the read and deal with the result.
1429	*/
1430	#ifdef VBOX_WITH_STATISTICS
1431	if (pStats)
1432	STAM_PROFILE_ADV_START(&pStats->CTXALLSUFF(ProfRead), a);
1433	#endif
1434	int rc = pRange->pfnReadCallback(pRange->pDevIns, pRange->pvUser, GCPhys, pu32Value, cbValue);
1435	#ifdef VBOX_WITH_STATISTICS
1436	if (pStats)
1437	STAM_PROFILE_ADV_STOP(&pStats->CTXALLSUFF(ProfRead), a);
1438	if (pStats && rc != VINF_IOM_HC_MMIO_READ)
1439	STAM_COUNTER_INC(&pStats->CTXALLSUFF(Read));
1440	#endif
1441	switch (rc)
1442	{
1443	case VINF_SUCCESS:
1444	default:
1445	Log4(("IOMMMIORead: GCPhys=%RGp pu32=%08RX32 cb=%d rc=%Vrc\n", GCPhys, pu32Value, cbValue, rc));
1446	return rc;
1447
1448	case VINF_IOM_MMIO_UNUSED_00:
1449	switch (cbValue)
1450	{
1451	case 1: (uint8_t )pu32Value = 0x00; break;
1452	case 2: (uint16_t )pu32Value = 0x0000; break;
1453	case 4: (uint32_t )pu32Value = 0x00000000; break;
1454	default: AssertReleaseMsgFailed(("cbValue=%d GCPhys=%VGp\n", cbValue, GCPhys)); break;
1455	}
1456	Log4(("IOMMMIORead: GCPhys=%RGp pu32=%08RX32 cb=%d rc=%Vrc\n", GCPhys, pu32Value, cbValue, rc));
1457	return VINF_SUCCESS;
1458
1459	case VINF_IOM_MMIO_UNUSED_FF:
1460	switch (cbValue)
1461	{
1462	case 1: (uint8_t )pu32Value = 0xff; break;
1463	case 2: (uint16_t )pu32Value = 0xffff; break;
1464	case 4: (uint32_t )pu32Value = 0xffffffff; break;
1465	default: AssertReleaseMsgFailed(("cbValue=%d GCPhys=%VGp\n", cbValue, GCPhys)); break;
1466	}
1467	Log4(("IOMMMIORead: GCPhys=%RGp pu32=%08RX32 cb=%d rc=%Vrc\n", GCPhys, pu32Value, cbValue, rc));
1468	return VINF_SUCCESS;
1469	}
1470	}
1471
1472	#ifndef IN_RING3
1473	/*
1474	* Lookup the ring-3 range.
1475	*/
1476	PIOMMMIORANGER3 pRangeR3 = iomMMIOGetRangeHC(&pVM->iom.s, GCPhys);
1477	if (pRangeR3)
1478	{
1479	if (pRangeR3->pfnReadCallback)
1480	return VINF_IOM_HC_MMIO_READ;
1481	# ifdef VBOX_WITH_STATISTICS
1482	if (pStats)
1483	STAM_COUNTER_INC(&pStats->CTXALLSUFF(Read));
1484	# endif
1485	*pu32Value = 0;
1486	Log4(("IOMMMIORead: GCPhys=%RGp pu32=%08RX32 cb=%d rc=VINF_SUCCESS\n", GCPhys, pu32Value, cbValue));
1487	return VINF_SUCCESS;
1488	}
1489	#endif
1490
1491	AssertMsgFailed(("Handlers and page tables are out of sync or something! GCPhys=%VGp cbValue=%d\n", GCPhys, cbValue));
1492	return VERR_INTERNAL_ERROR;
1493	}
1494
1495
1496	/**
1497	* Writes to a MMIO register.
1498	*
1499	* @returns VBox status code.
1500	*
1501	* @param pVM VM handle.
1502	* @param GCPhys The physical address to write to.
1503	* @param u32Value The value to write.
1504	* @param cbValue The size of the register to read in bytes. 1, 2 or 4 bytes.
1505	*/
1506	IOMDECL(int) IOMMMIOWrite(PVM pVM, RTGCPHYS GCPhys, uint32_t u32Value, size_t cbValue)
1507	{
1508	/** @todo add return to ring-3 statistics when this function is used in GC! */
1509	/*
1510	* Lookup the current context range node.
1511	*/
1512	CTXALLSUFF(PIOMMMIORANGE) pRange = iomMMIOGetRange(&pVM->iom.s, GCPhys);
1513	#ifdef VBOX_WITH_STATISTICS
1514	PIOMMMIOSTATS pStats = iomMMIOGetStats(&pVM->iom.s, GCPhys);
1515	if (!pStats && (!pRange \|\| pRange->cbSize <= PAGE_SIZE))
1516	# ifdef IN_RING3
1517	pStats = iomR3MMIOStatsCreate(pVM, GCPhys, pRange ? pRange->pszDesc : NULL);
1518	# else
1519	return VINF_IOM_HC_MMIO_WRITE;
1520	# endif
1521	#endif /* VBOX_WITH_STATISTICS */
1522
1523	/*
1524	* Perform the write if we found a range.
1525	*/
1526	#ifdef IN_RING3
1527	if (pRange)
1528	#else /* !IN_RING3 */
1529	if (pRange && pRange->pfnWriteCallback)
1530	#endif /* !IN_RING3 */
1531	{
1532	#ifdef VBOX_WITH_STATISTICS
1533	if (pStats)
1534	STAM_PROFILE_ADV_START(&pStats->CTXALLSUFF(ProfWrite), a);
1535	#endif
1536	int rc = pRange->pfnWriteCallback(pRange->pDevIns, pRange->pvUser, GCPhys, &u32Value, cbValue);
1537	#ifdef VBOX_WITH_STATISTICS
1538	if (pStats)
1539	STAM_PROFILE_ADV_STOP(&pStats->CTXALLSUFF(ProfWrite), a);
1540	if (pStats && rc != VINF_IOM_HC_MMIO_WRITE)
1541	STAM_COUNTER_INC(&pStats->CTXALLSUFF(Write));
1542	#endif
1543	Log4(("IOMMMIOWrite: GCPhys=%RGp u32=%08RX32 cb=%d rc=%Vrc\n", GCPhys, u32Value, cbValue, rc));
1544	return rc;
1545	}
1546
1547	#ifndef IN_RING3
1548	/*
1549	* Lookup the ring-3 range.
1550	*/
1551	PIOMMMIORANGER3 pRangeR3 = iomMMIOGetRangeHC(&pVM->iom.s, GCPhys);
1552	if (pRangeR3)
1553	{
1554	if (pRangeR3->pfnWriteCallback)
1555	return VINF_IOM_HC_MMIO_WRITE;
1556	# ifdef VBOX_WITH_STATISTICS
1557	if (pStats)
1558	STAM_COUNTER_INC(&pStats->CTXALLSUFF(Write));
1559	# endif
1560	Log4(("IOMMMIOWrite: GCPhys=%RGp u32=%08RX32 cb=%d rc=%Vrc\n", GCPhys, u32Value, cbValue));
1561	return VINF_SUCCESS;
1562	}
1563	#endif
1564
1565	AssertMsgFailed(("Handlers and page tables are out of sync or something! GCPhys=%VGp cbValue=%d\n", GCPhys, cbValue));
1566	return VERR_INTERNAL_ERROR;
1567	}
1568
1569
1570	/**
1571	* [REP*] INSB/INSW/INSD
1572	* ES:EDI,DX[,ECX]
1573	*
1574	* @remark Assumes caller checked the access privileges (IOMInterpretCheckPortIOAccess)
1575	*
1576	* @returns Strict VBox status code. Informational status codes other than the one documented
1577	* here are to be treated as internal failure. Use IOM_SUCCESS() to check for success.
1578	* @retval VINF_SUCCESS Success.
1579	* @retval VINF_EM_FIRST-VINF_EM_LAST Success with some exceptions (see IOM_SUCCESS()), the
1580	* status code must be passed on to EM.
1581	* @retval VINF_IOM_HC_IOPORT_READ Defer the read to ring-3. (R0/GC only)
1582	* @retval VINF_EM_RAW_EMULATE_INSTR Defer the read to the REM.
1583	* @retval VINF_EM_RAW_GUEST_TRAP The exception was left pending. (TRPMRaiseXcptErr)
1584	* @retval VINF_TRPM_XCPT_DISPATCHED The exception was raised and dispatched for raw-mode execution. (TRPMRaiseXcptErr)
1585	* @retval VINF_EM_RESCHEDULE_REM The exception was dispatched and cannot be executed in raw-mode. (TRPMRaiseXcptErr)
1586	*
1587	* @param pVM The virtual machine (GC pointer ofcourse).
1588	* @param pRegFrame Pointer to CPUMCTXCORE guest registers structure.
1589	* @param uPort IO Port
1590	* @param uPrefix IO instruction prefix
1591	* @param cbTransfer Size of transfer unit
1592	*/
1593	IOMDECL(int) IOMInterpretINSEx(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t uPort, uint32_t uPrefix, uint32_t cbTransfer)
1594	{
1595	#ifdef VBOX_WITH_STATISTICS
1596	STAM_COUNTER_INC(&pVM->iom.s.StatGCInstIns);
1597	#endif
1598
1599	/*
1600	* We do not support REPNE or decrementing destination
1601	* pointer. Segment prefixes are deliberately ignored, as per the instruction specification.
1602	*/
1603	if ( (uPrefix & PREFIX_REPNE)
1604	\|\| pRegFrame->eflags.Bits.u1DF)
1605	return VINF_EM_RAW_EMULATE_INSTR;
1606
1607	/*
1608	* Get bytes/words/dwords count to transfer.
1609	*/
1610	RTGCUINTREG cTransfers = 1;
1611	if (uPrefix & PREFIX_REP)
1612	{
1613	cTransfers = pRegFrame->ecx;
1614
1615	if (!SELMIsSelector32Bit(pVM, pRegFrame->eflags, pRegFrame->cs, &pRegFrame->csHid))
1616	cTransfers &= 0xffff;
1617
1618	if (!cTransfers)
1619	return VINF_SUCCESS;
1620	}
1621
1622	/* Convert destination address es:edi. */
1623	RTGCPTR GCPtrDst;
1624	int rc = SELMToFlatEx(pVM, pRegFrame->eflags, pRegFrame->es, (RTGCPTR)pRegFrame->edi, &pRegFrame->esHid,
1625	SELMTOFLAT_FLAGS_HYPER \| SELMTOFLAT_FLAGS_NO_PL,
1626	&GCPtrDst, NULL);
1627	if (VBOX_FAILURE(rc))
1628	{
1629	Log(("INS destination address conversion failed -> fallback, rc=%d\n", rc));
1630	return VINF_EM_RAW_EMULATE_INSTR;
1631	}
1632
1633	/* Access verification first; we can't recover from traps inside this instruction, as the port read cannot be repeated. */
1634	uint32_t cpl = CPUMGetGuestCPL(pVM, pRegFrame);
1635
1636	rc = PGMVerifyAccess(pVM, (RTGCUINTPTR)GCPtrDst, cTransfers * cbTransfer,
1637	X86_PTE_RW \| ((cpl == 3) ? X86_PTE_US : 0));
1638	if (rc != VINF_SUCCESS)
1639	{
1640	Log(("INS will generate a trap -> fallback, rc=%d\n", rc));
1641	return VINF_EM_RAW_EMULATE_INSTR;
1642	}
1643
1644	Log(("IOM: rep ins%d port %#x count %d\n", cbTransfer * 8, uPort, cTransfers));
1645	if (cTransfers > 1)
1646	{
1647	/* If the device supports string transfers, ask it to do as
1648	* much as it wants. The rest is done with single-word transfers. */
1649	const RTGCUINTREG cTransfersOrg = cTransfers;
1650	rc = IOMIOPortReadString(pVM, uPort, &GCPtrDst, &cTransfers, cbTransfer);
1651	AssertRC(rc); Assert(cTransfers <= cTransfersOrg);
1652	pRegFrame->edi += (cTransfersOrg - cTransfers) * cbTransfer;
1653	}
1654
1655	#ifdef IN_GC
1656	MMGCRamRegisterTrapHandler(pVM);
1657	#endif
1658
1659	while (cTransfers && rc == VINF_SUCCESS)
1660	{
1661	uint32_t u32Value;
1662	rc = IOMIOPortRead(pVM, uPort, &u32Value, cbTransfer);
1663	if (!IOM_SUCCESS(rc))
1664	break;
1665	int rc2 = iomRamWrite(pVM, GCPtrDst, &u32Value, cbTransfer);
1666	Assert(rc2 == VINF_SUCCESS); NOREF(rc2);
1667	GCPtrDst = (RTGCPTR)((RTGCUINTPTR)GCPtrDst + cbTransfer);
1668	pRegFrame->edi += cbTransfer;
1669	cTransfers--;
1670	}
1671	#ifdef IN_GC
1672	MMGCRamDeregisterTrapHandler(pVM);
1673	#endif
1674
1675	/* Update ecx on exit. */
1676	if (uPrefix & PREFIX_REP)
1677	pRegFrame->ecx = cTransfers;
1678
1679	AssertMsg(rc == VINF_SUCCESS \|\| rc == VINF_IOM_HC_IOPORT_READ \|\| (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST) \|\| VBOX_FAILURE(rc), ("%Vrc\n", rc));
1680	return rc;
1681	}
1682
1683
1684	/**
1685	* [REP*] INSB/INSW/INSD
1686	* ES:EDI,DX[,ECX]
1687	*
1688	* @returns Strict VBox status code. Informational status codes other than the one documented
1689	* here are to be treated as internal failure. Use IOM_SUCCESS() to check for success.
1690	* @retval VINF_SUCCESS Success.
1691	* @retval VINF_EM_FIRST-VINF_EM_LAST Success with some exceptions (see IOM_SUCCESS()), the
1692	* status code must be passed on to EM.
1693	* @retval VINF_IOM_HC_IOPORT_READ Defer the read to ring-3. (R0/GC only)
1694	* @retval VINF_EM_RAW_EMULATE_INSTR Defer the read to the REM.
1695	* @retval VINF_EM_RAW_GUEST_TRAP The exception was left pending. (TRPMRaiseXcptErr)
1696	* @retval VINF_TRPM_XCPT_DISPATCHED The exception was raised and dispatched for raw-mode execution. (TRPMRaiseXcptErr)
1697	* @retval VINF_EM_RESCHEDULE_REM The exception was dispatched and cannot be executed in raw-mode. (TRPMRaiseXcptErr)
1698	*
1699	* @param pVM The virtual machine (GC pointer ofcourse).
1700	* @param pRegFrame Pointer to CPUMCTXCORE guest registers structure.
1701	* @param pCpu Disassembler CPU state.
1702	*/
1703	IOMDECL(int) IOMInterpretINS(PVM pVM, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu)
1704	{
1705	/*
1706	* Get port number directly from the register (no need to bother the
1707	* disassembler). And get the I/O register size from the opcode / prefix.
1708	*/
1709	uint32_t uPort = pRegFrame->edx & 0xffff;
1710	unsigned cbSize = 0;
1711	if (pCpu->pCurInstr->opcode == OP_INSB)
1712	cbSize = 1;
1713	else
1714	cbSize = pCpu->opmode == CPUMODE_32BIT ? 4 : 2;
1715
1716	int rc = IOMInterpretCheckPortIOAccess(pVM, pRegFrame, uPort, cbSize);
1717	if (RT_UNLIKELY(rc != VINF_SUCCESS))
1718	{
1719	AssertMsg(rc == VINF_EM_RAW_GUEST_TRAP \|\| rc == VINF_TRPM_XCPT_DISPATCHED \|\| rc == VINF_TRPM_XCPT_DISPATCHED \|\| VBOX_FAILURE(rc), ("%Vrc\n", rc));
1720	return rc;
1721	}
1722
1723	return IOMInterpretINSEx(pVM, pRegFrame, uPort, pCpu->prefix, cbSize);
1724	}
1725
1726
1727	/**
1728	* [REP*] OUTSB/OUTSW/OUTSD
1729	* DS:ESI,DX[,ECX]
1730	*
1731	* @remark Assumes caller checked the access privileges (IOMInterpretCheckPortIOAccess)
1732	*
1733	* @returns Strict VBox status code. Informational status codes other than the one documented
1734	* here are to be treated as internal failure. Use IOM_SUCCESS() to check for success.
1735	* @retval VINF_SUCCESS Success.
1736	* @retval VINF_EM_FIRST-VINF_EM_LAST Success with some exceptions (see IOM_SUCCESS()), the
1737	* status code must be passed on to EM.
1738	* @retval VINF_IOM_HC_IOPORT_WRITE Defer the write to ring-3. (R0/GC only)
1739	* @retval VINF_EM_RAW_GUEST_TRAP The exception was left pending. (TRPMRaiseXcptErr)
1740	* @retval VINF_TRPM_XCPT_DISPATCHED The exception was raised and dispatched for raw-mode execution. (TRPMRaiseXcptErr)
1741	* @retval VINF_EM_RESCHEDULE_REM The exception was dispatched and cannot be executed in raw-mode. (TRPMRaiseXcptErr)
1742	*
1743	* @param pVM The virtual machine (GC pointer ofcourse).
1744	* @param pRegFrame Pointer to CPUMCTXCORE guest registers structure.
1745	* @param uPort IO Port
1746	* @param uPrefix IO instruction prefix
1747	* @param cbTransfer Size of transfer unit
1748	*/
1749	IOMDECL(int) IOMInterpretOUTSEx(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t uPort, uint32_t uPrefix, uint32_t cbTransfer)
1750	{
1751	#ifdef VBOX_WITH_STATISTICS
1752	STAM_COUNTER_INC(&pVM->iom.s.StatGCInstOuts);
1753	#endif
1754
1755	/*
1756	* We do not support segment prefixes, REPNE or
1757	* decrementing source pointer.
1758	*/
1759	if ( (uPrefix & (PREFIX_SEG \| PREFIX_REPNE))
1760	\|\| pRegFrame->eflags.Bits.u1DF)
1761	return VINF_EM_RAW_EMULATE_INSTR;
1762
1763	/*
1764	* Get bytes/words/dwords count to transfer.
1765	*/
1766	RTGCUINTREG cTransfers = 1;
1767	if (uPrefix & PREFIX_REP)
1768	{
1769	cTransfers = pRegFrame->ecx;
1770	if (!SELMIsSelector32Bit(pVM, pRegFrame->eflags, pRegFrame->cs, &pRegFrame->csHid))
1771	cTransfers &= 0xffff;
1772
1773	if (!cTransfers)
1774	return VINF_SUCCESS;
1775	}
1776
1777	/* Convert source address ds:esi. */
1778	RTGCPTR GCPtrSrc;
1779	int rc = SELMToFlatEx(pVM, pRegFrame->eflags, pRegFrame->ds, (RTGCPTR)pRegFrame->esi, &pRegFrame->dsHid,
1780	SELMTOFLAT_FLAGS_HYPER \| SELMTOFLAT_FLAGS_NO_PL,
1781	&GCPtrSrc, NULL);
1782	if (VBOX_FAILURE(rc))
1783	{
1784	Log(("OUTS source address conversion failed -> fallback, rc=%Vrc\n", rc));
1785	return VINF_EM_RAW_EMULATE_INSTR;
1786	}
1787
1788	/* Access verification first; we currently can't recover properly from traps inside this instruction */
1789	uint32_t cpl = CPUMGetGuestCPL(pVM, pRegFrame);
1790	rc = PGMVerifyAccess(pVM, (RTGCUINTPTR)GCPtrSrc, cTransfers * cbTransfer,
1791	(cpl == 3) ? X86_PTE_US : 0);
1792	if (rc != VINF_SUCCESS)
1793	{
1794	Log(("OUTS will generate a trap -> fallback, rc=%Vrc\n", rc));
1795	return VINF_EM_RAW_EMULATE_INSTR;
1796	}
1797
1798	Log(("IOM: rep outs%d port %#x count %d\n", cbTransfer * 8, uPort, cTransfers));
1799	if (cTransfers > 1)
1800	{
1801	/*
1802	* If the device supports string transfers, ask it to do as
1803	* much as it wants. The rest is done with single-word transfers.
1804	*/
1805	const RTGCUINTREG cTransfersOrg = cTransfers;
1806	rc = IOMIOPortWriteString(pVM, uPort, &GCPtrSrc, &cTransfers, cbTransfer);
1807	AssertRC(rc); Assert(cTransfers <= cTransfersOrg);
1808	pRegFrame->esi += (cTransfersOrg - cTransfers) * cbTransfer;
1809	}
1810
1811	#ifdef IN_GC
1812	MMGCRamRegisterTrapHandler(pVM);
1813	#endif
1814
1815	while (cTransfers && rc == VINF_SUCCESS)
1816	{
1817	uint32_t u32Value;
1818	rc = iomRamRead(pVM, &u32Value, GCPtrSrc, cbTransfer);
1819	if (rc != VINF_SUCCESS)
1820	break;
1821	rc = IOMIOPortWrite(pVM, uPort, u32Value, cbTransfer);
1822	if (!IOM_SUCCESS(rc))
1823	break;
1824	GCPtrSrc = (RTGCPTR)((RTUINTPTR)GCPtrSrc + cbTransfer);
1825	pRegFrame->esi += cbTransfer;
1826	cTransfers--;
1827	}
1828
1829	#ifdef IN_GC
1830	MMGCRamDeregisterTrapHandler(pVM);
1831	#endif
1832
1833	/* Update ecx on exit. */
1834	if (uPrefix & PREFIX_REP)
1835	pRegFrame->ecx = cTransfers;
1836
1837	AssertMsg(rc == VINF_SUCCESS \|\| rc == VINF_IOM_HC_IOPORT_WRITE \|\| (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST) \|\| VBOX_FAILURE(rc), ("%Vrc\n", rc));
1838	return rc;
1839	}
1840
1841
1842	/**
1843	* [REP*] OUTSB/OUTSW/OUTSD
1844	* DS:ESI,DX[,ECX]
1845	*
1846	* @returns Strict VBox status code. Informational status codes other than the one documented
1847	* here are to be treated as internal failure. Use IOM_SUCCESS() to check for success.
1848	* @retval VINF_SUCCESS Success.
1849	* @retval VINF_EM_FIRST-VINF_EM_LAST Success with some exceptions (see IOM_SUCCESS()), the
1850	* status code must be passed on to EM.
1851	* @retval VINF_IOM_HC_IOPORT_WRITE Defer the write to ring-3. (R0/GC only)
1852	* @retval VINF_EM_RAW_EMULATE_INSTR Defer the write to the REM.
1853	* @retval VINF_EM_RAW_GUEST_TRAP The exception was left pending. (TRPMRaiseXcptErr)
1854	* @retval VINF_TRPM_XCPT_DISPATCHED The exception was raised and dispatched for raw-mode execution. (TRPMRaiseXcptErr)
1855	* @retval VINF_EM_RESCHEDULE_REM The exception was dispatched and cannot be executed in raw-mode. (TRPMRaiseXcptErr)
1856	*
1857	* @param pVM The virtual machine (GC pointer ofcourse).
1858	* @param pRegFrame Pointer to CPUMCTXCORE guest registers structure.
1859	* @param pCpu Disassembler CPU state.
1860	*/
1861	IOMDECL(int) IOMInterpretOUTS(PVM pVM, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu)
1862	{
1863	/*
1864	* Get port number from the first parameter.
1865	* And get the I/O register size from the opcode / prefix.
1866	*/
1867	uint32_t uPort = 0;
1868	unsigned cbSize = 0;
1869	bool fRc = iomGCGetRegImmData(pCpu, &pCpu->param1, pRegFrame, &uPort, &cbSize);
1870	AssertMsg(fRc, ("Failed to get reg/imm port number!\n")); NOREF(fRc);
1871	if (pCpu->pCurInstr->opcode == OP_OUTSB)
1872	cbSize = 1;
1873	else
1874	cbSize = (pCpu->opmode == CPUMODE_32BIT) ? 4 : 2;
1875
1876	int rc = IOMInterpretCheckPortIOAccess(pVM, pRegFrame, uPort, cbSize);
1877	if (RT_UNLIKELY(rc != VINF_SUCCESS))
1878	{
1879	AssertMsg(rc == VINF_EM_RAW_GUEST_TRAP \|\| rc == VINF_TRPM_XCPT_DISPATCHED \|\| rc == VINF_TRPM_XCPT_DISPATCHED \|\| VBOX_FAILURE(rc), ("%Vrc\n", rc));
1880	return rc;
1881	}
1882
1883	return IOMInterpretOUTSEx(pVM, pRegFrame, uPort, pCpu->prefix, cbSize);
1884	}
1885

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source: vbox/trunk/src/VBox/VMM/VMMAll/IOMAllMMIO.cpp@ 6537

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