VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/NEMAllNativeTemplate-win.cpp.h@ 71293

Last change on this file since 71293 was 71293, checked in by vboxsync, 7 years ago

NEM: Some stats; doc updates. bugref:9044
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1/* $Id: NEMAllNativeTemplate-win.cpp.h 71293 2018-03-09 21:11:20Z vboxsync $ */
2/** @file
3 * NEM - Native execution manager, Windows code template ring-0/3.
4 */
5
6/*
7 * Copyright (C) 2018 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Defined Constants And Macros *
21*********************************************************************************************************************************/
22/** Copy back a segment from hyper-V. */
23#define NEM_WIN_COPY_BACK_SEG(a_Dst, a_Src) \
24 do { \
25 (a_Dst).u64Base = (a_Src).Base; \
26 (a_Dst).u32Limit = (a_Src).Limit; \
27 (a_Dst).ValidSel = (a_Dst).Sel = (a_Src).Selector; \
28 (a_Dst).Attr.u = (a_Src).Attributes; \
29 (a_Dst).fFlags = CPUMSELREG_FLAGS_VALID; \
30 } while (0)
31
32
33/*********************************************************************************************************************************
34* Global Variables *
35*********************************************************************************************************************************/
36/** NEM_WIN_PAGE_STATE_XXX names. */
37NEM_TMPL_STATIC const char * const g_apszPageStates[4] = { "not-set", "unmapped", "readable", "writable" };
38
39/** HV_INTERCEPT_ACCESS_TYPE names. */
40static const char * const g_apszHvInterceptAccessTypes[4] = { "read", "write", "exec", "!undefined!" };
41
42
43/*********************************************************************************************************************************
44* Internal Functions *
45*********************************************************************************************************************************/
46NEM_TMPL_STATIC int nemHCNativeSetPhysPage(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhysSrc, RTGCPHYS GCPhysDst,
47 uint32_t fPageProt, uint8_t *pu2State, bool fBackingChanged);
48
49
50#ifdef NEM_WIN_USE_HYPERCALLS_FOR_PAGES
51
52/**
53 * Wrapper around VMMR0_DO_NEM_MAP_PAGES for a single page.
54 *
55 * @returns VBox status code.
56 * @param pVM The cross context VM structure.
57 * @param pVCpu The cross context virtual CPU structure of the caller.
58 * @param GCPhysSrc The source page. Does not need to be page aligned.
59 * @param GCPhysDst The destination page. Same as @a GCPhysSrc except for
60 * when A20 is disabled.
61 * @param fFlags HV_MAP_GPA_XXX.
62 */
63DECLINLINE(int) nemHCWinHypercallMapPage(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhysSrc, RTGCPHYS GCPhysDst, uint32_t fFlags)
64{
65#ifdef IN_RING0
66 /** @todo optimize further, caller generally has the physical address. */
67 PGVM pGVM = GVMMR0FastGetGVMByVM(pVM);
68 AssertReturn(pGVM, VERR_INVALID_VM_HANDLE);
69 return nemR0WinMapPages(pGVM, pVM, &pGVM->aCpus[pVCpu->idCpu],
70 GCPhysSrc & ~(RTGCPHYS)X86_PAGE_OFFSET_MASK,
71 GCPhysDst & ~(RTGCPHYS)X86_PAGE_OFFSET_MASK,
72 1, fFlags);
73#else
74 pVCpu->nem.s.Hypercall.MapPages.GCPhysSrc = GCPhysSrc & ~(RTGCPHYS)X86_PAGE_OFFSET_MASK;
75 pVCpu->nem.s.Hypercall.MapPages.GCPhysDst = GCPhysDst & ~(RTGCPHYS)X86_PAGE_OFFSET_MASK;
76 pVCpu->nem.s.Hypercall.MapPages.cPages = 1;
77 pVCpu->nem.s.Hypercall.MapPages.fFlags = fFlags;
78 return VMMR3CallR0Emt(pVM, pVCpu, VMMR0_DO_NEM_MAP_PAGES, 0, NULL);
79#endif
80}
81
82
83/**
84 * Wrapper around VMMR0_DO_NEM_UNMAP_PAGES for a single page.
85 *
86 * @returns VBox status code.
87 * @param pVM The cross context VM structure.
88 * @param pVCpu The cross context virtual CPU structure of the caller.
89 * @param GCPhys The page to unmap. Does not need to be page aligned.
90 */
91DECLINLINE(int) nemHCWinHypercallUnmapPage(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys)
92{
93# ifdef IN_RING0
94 PGVM pGVM = GVMMR0FastGetGVMByVM(pVM);
95 AssertReturn(pGVM, VERR_INVALID_VM_HANDLE);
96 return nemR0WinUnmapPages(pGVM, &pGVM->aCpus[pVCpu->idCpu], GCPhys & ~(RTGCPHYS)X86_PAGE_OFFSET_MASK, 1);
97# else
98 pVCpu->nem.s.Hypercall.UnmapPages.GCPhys = GCPhys & ~(RTGCPHYS)X86_PAGE_OFFSET_MASK;
99 pVCpu->nem.s.Hypercall.UnmapPages.cPages = 1;
100 return VMMR3CallR0Emt(pVM, pVCpu, VMMR0_DO_NEM_UNMAP_PAGES, 0, NULL);
101# endif
102}
103
104#endif /* NEM_WIN_USE_HYPERCALLS_FOR_PAGES */
105#ifndef IN_RING0
106
107NEM_TMPL_STATIC int nemHCWinCopyStateToHyperV(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
108{
109# ifdef NEM_WIN_USE_HYPERCALLS_FOR_REGISTERS
110 NOREF(pCtx);
111 int rc = VMMR3CallR0Emt(pVM, pVCpu, VMMR0_DO_NEM_EXPORT_STATE, 0, NULL);
112 AssertLogRelRCReturn(rc, rc);
113 return rc;
114
115# else
116 WHV_REGISTER_NAME aenmNames[128];
117 WHV_REGISTER_VALUE aValues[128];
118
119 /* GPRs */
120 aenmNames[0] = WHvX64RegisterRax;
121 aValues[0].Reg64 = pCtx->rax;
122 aenmNames[1] = WHvX64RegisterRcx;
123 aValues[1].Reg64 = pCtx->rcx;
124 aenmNames[2] = WHvX64RegisterRdx;
125 aValues[2].Reg64 = pCtx->rdx;
126 aenmNames[3] = WHvX64RegisterRbx;
127 aValues[3].Reg64 = pCtx->rbx;
128 aenmNames[4] = WHvX64RegisterRsp;
129 aValues[4].Reg64 = pCtx->rsp;
130 aenmNames[5] = WHvX64RegisterRbp;
131 aValues[5].Reg64 = pCtx->rbp;
132 aenmNames[6] = WHvX64RegisterRsi;
133 aValues[6].Reg64 = pCtx->rsi;
134 aenmNames[7] = WHvX64RegisterRdi;
135 aValues[7].Reg64 = pCtx->rdi;
136 aenmNames[8] = WHvX64RegisterR8;
137 aValues[8].Reg64 = pCtx->r8;
138 aenmNames[9] = WHvX64RegisterR9;
139 aValues[9].Reg64 = pCtx->r9;
140 aenmNames[10] = WHvX64RegisterR10;
141 aValues[10].Reg64 = pCtx->r10;
142 aenmNames[11] = WHvX64RegisterR11;
143 aValues[11].Reg64 = pCtx->r11;
144 aenmNames[12] = WHvX64RegisterR12;
145 aValues[12].Reg64 = pCtx->r12;
146 aenmNames[13] = WHvX64RegisterR13;
147 aValues[13].Reg64 = pCtx->r13;
148 aenmNames[14] = WHvX64RegisterR14;
149 aValues[14].Reg64 = pCtx->r14;
150 aenmNames[15] = WHvX64RegisterR15;
151 aValues[15].Reg64 = pCtx->r15;
152
153 /* RIP & Flags */
154 aenmNames[16] = WHvX64RegisterRip;
155 aValues[16].Reg64 = pCtx->rip;
156 aenmNames[17] = WHvX64RegisterRflags;
157 aValues[17].Reg64 = pCtx->rflags.u;
158
159 /* Segments */
160# define COPY_OUT_SEG(a_idx, a_enmName, a_SReg) \
161 do { \
162 aenmNames[a_idx] = a_enmName; \
163 aValues[a_idx].Segment.Base = (a_SReg).u64Base; \
164 aValues[a_idx].Segment.Limit = (a_SReg).u32Limit; \
165 aValues[a_idx].Segment.Selector = (a_SReg).Sel; \
166 aValues[a_idx].Segment.Attributes = (a_SReg).Attr.u; \
167 } while (0)
168 COPY_OUT_SEG(18, WHvX64RegisterEs, pCtx->es);
169 COPY_OUT_SEG(19, WHvX64RegisterCs, pCtx->cs);
170 COPY_OUT_SEG(20, WHvX64RegisterSs, pCtx->ss);
171 COPY_OUT_SEG(21, WHvX64RegisterDs, pCtx->ds);
172 COPY_OUT_SEG(22, WHvX64RegisterFs, pCtx->fs);
173 COPY_OUT_SEG(23, WHvX64RegisterGs, pCtx->gs);
174 COPY_OUT_SEG(24, WHvX64RegisterLdtr, pCtx->ldtr);
175 COPY_OUT_SEG(25, WHvX64RegisterTr, pCtx->tr);
176
177 uintptr_t iReg = 26;
178 /* Descriptor tables. */
179 aenmNames[iReg] = WHvX64RegisterIdtr;
180 aValues[iReg].Table.Limit = pCtx->idtr.cbIdt;
181 aValues[iReg].Table.Base = pCtx->idtr.pIdt;
182 iReg++;
183 aenmNames[iReg] = WHvX64RegisterGdtr;
184 aValues[iReg].Table.Limit = pCtx->gdtr.cbGdt;
185 aValues[iReg].Table.Base = pCtx->gdtr.pGdt;
186 iReg++;
187
188 /* Control registers. */
189 aenmNames[iReg] = WHvX64RegisterCr0;
190 aValues[iReg].Reg64 = pCtx->cr0;
191 iReg++;
192 aenmNames[iReg] = WHvX64RegisterCr2;
193 aValues[iReg].Reg64 = pCtx->cr2;
194 iReg++;
195 aenmNames[iReg] = WHvX64RegisterCr3;
196 aValues[iReg].Reg64 = pCtx->cr3;
197 iReg++;
198 aenmNames[iReg] = WHvX64RegisterCr4;
199 aValues[iReg].Reg64 = pCtx->cr4;
200 iReg++;
201 aenmNames[iReg] = WHvX64RegisterCr8;
202 aValues[iReg].Reg64 = CPUMGetGuestCR8(pVCpu);
203 iReg++;
204
205 /* Debug registers. */
206/** @todo fixme. Figure out what the hyper-v version of KVM_SET_GUEST_DEBUG would be. */
207 aenmNames[iReg] = WHvX64RegisterDr0;
208 //aValues[iReg].Reg64 = CPUMGetHyperDR0(pVCpu);
209 aValues[iReg].Reg64 = pCtx->dr[0];
210 iReg++;
211 aenmNames[iReg] = WHvX64RegisterDr1;
212 //aValues[iReg].Reg64 = CPUMGetHyperDR1(pVCpu);
213 aValues[iReg].Reg64 = pCtx->dr[1];
214 iReg++;
215 aenmNames[iReg] = WHvX64RegisterDr2;
216 //aValues[iReg].Reg64 = CPUMGetHyperDR2(pVCpu);
217 aValues[iReg].Reg64 = pCtx->dr[2];
218 iReg++;
219 aenmNames[iReg] = WHvX64RegisterDr3;
220 //aValues[iReg].Reg64 = CPUMGetHyperDR3(pVCpu);
221 aValues[iReg].Reg64 = pCtx->dr[3];
222 iReg++;
223 aenmNames[iReg] = WHvX64RegisterDr6;
224 //aValues[iReg].Reg64 = CPUMGetHyperDR6(pVCpu);
225 aValues[iReg].Reg64 = pCtx->dr[6];
226 iReg++;
227 aenmNames[iReg] = WHvX64RegisterDr7;
228 //aValues[iReg].Reg64 = CPUMGetHyperDR7(pVCpu);
229 aValues[iReg].Reg64 = pCtx->dr[7];
230 iReg++;
231
232 /* Vector state. */
233 aenmNames[iReg] = WHvX64RegisterXmm0;
234 aValues[iReg].Reg128.Low64 = pCtx->pXStateR3->x87.aXMM[0].uXmm.s.Lo;
235 aValues[iReg].Reg128.High64 = pCtx->pXStateR3->x87.aXMM[0].uXmm.s.Hi;
236 iReg++;
237 aenmNames[iReg] = WHvX64RegisterXmm1;
238 aValues[iReg].Reg128.Low64 = pCtx->pXStateR3->x87.aXMM[1].uXmm.s.Lo;
239 aValues[iReg].Reg128.High64 = pCtx->pXStateR3->x87.aXMM[1].uXmm.s.Hi;
240 iReg++;
241 aenmNames[iReg] = WHvX64RegisterXmm2;
242 aValues[iReg].Reg128.Low64 = pCtx->pXStateR3->x87.aXMM[2].uXmm.s.Lo;
243 aValues[iReg].Reg128.High64 = pCtx->pXStateR3->x87.aXMM[2].uXmm.s.Hi;
244 iReg++;
245 aenmNames[iReg] = WHvX64RegisterXmm3;
246 aValues[iReg].Reg128.Low64 = pCtx->pXStateR3->x87.aXMM[3].uXmm.s.Lo;
247 aValues[iReg].Reg128.High64 = pCtx->pXStateR3->x87.aXMM[3].uXmm.s.Hi;
248 iReg++;
249 aenmNames[iReg] = WHvX64RegisterXmm4;
250 aValues[iReg].Reg128.Low64 = pCtx->pXStateR3->x87.aXMM[4].uXmm.s.Lo;
251 aValues[iReg].Reg128.High64 = pCtx->pXStateR3->x87.aXMM[4].uXmm.s.Hi;
252 iReg++;
253 aenmNames[iReg] = WHvX64RegisterXmm5;
254 aValues[iReg].Reg128.Low64 = pCtx->pXStateR3->x87.aXMM[5].uXmm.s.Lo;
255 aValues[iReg].Reg128.High64 = pCtx->pXStateR3->x87.aXMM[5].uXmm.s.Hi;
256 iReg++;
257 aenmNames[iReg] = WHvX64RegisterXmm6;
258 aValues[iReg].Reg128.Low64 = pCtx->pXStateR3->x87.aXMM[6].uXmm.s.Lo;
259 aValues[iReg].Reg128.High64 = pCtx->pXStateR3->x87.aXMM[6].uXmm.s.Hi;
260 iReg++;
261 aenmNames[iReg] = WHvX64RegisterXmm7;
262 aValues[iReg].Reg128.Low64 = pCtx->pXStateR3->x87.aXMM[7].uXmm.s.Lo;
263 aValues[iReg].Reg128.High64 = pCtx->pXStateR3->x87.aXMM[7].uXmm.s.Hi;
264 iReg++;
265 aenmNames[iReg] = WHvX64RegisterXmm8;
266 aValues[iReg].Reg128.Low64 = pCtx->pXStateR3->x87.aXMM[8].uXmm.s.Lo;
267 aValues[iReg].Reg128.High64 = pCtx->pXStateR3->x87.aXMM[8].uXmm.s.Hi;
268 iReg++;
269 aenmNames[iReg] = WHvX64RegisterXmm9;
270 aValues[iReg].Reg128.Low64 = pCtx->pXStateR3->x87.aXMM[9].uXmm.s.Lo;
271 aValues[iReg].Reg128.High64 = pCtx->pXStateR3->x87.aXMM[9].uXmm.s.Hi;
272 iReg++;
273 aenmNames[iReg] = WHvX64RegisterXmm10;
274 aValues[iReg].Reg128.Low64 = pCtx->pXStateR3->x87.aXMM[10].uXmm.s.Lo;
275 aValues[iReg].Reg128.High64 = pCtx->pXStateR3->x87.aXMM[10].uXmm.s.Hi;
276 iReg++;
277 aenmNames[iReg] = WHvX64RegisterXmm11;
278 aValues[iReg].Reg128.Low64 = pCtx->pXStateR3->x87.aXMM[11].uXmm.s.Lo;
279 aValues[iReg].Reg128.High64 = pCtx->pXStateR3->x87.aXMM[11].uXmm.s.Hi;
280 iReg++;
281 aenmNames[iReg] = WHvX64RegisterXmm12;
282 aValues[iReg].Reg128.Low64 = pCtx->pXStateR3->x87.aXMM[12].uXmm.s.Lo;
283 aValues[iReg].Reg128.High64 = pCtx->pXStateR3->x87.aXMM[12].uXmm.s.Hi;
284 iReg++;
285 aenmNames[iReg] = WHvX64RegisterXmm13;
286 aValues[iReg].Reg128.Low64 = pCtx->pXStateR3->x87.aXMM[13].uXmm.s.Lo;
287 aValues[iReg].Reg128.High64 = pCtx->pXStateR3->x87.aXMM[13].uXmm.s.Hi;
288 iReg++;
289 aenmNames[iReg] = WHvX64RegisterXmm14;
290 aValues[iReg].Reg128.Low64 = pCtx->pXStateR3->x87.aXMM[14].uXmm.s.Lo;
291 aValues[iReg].Reg128.High64 = pCtx->pXStateR3->x87.aXMM[14].uXmm.s.Hi;
292 iReg++;
293 aenmNames[iReg] = WHvX64RegisterXmm15;
294 aValues[iReg].Reg128.Low64 = pCtx->pXStateR3->x87.aXMM[15].uXmm.s.Lo;
295 aValues[iReg].Reg128.High64 = pCtx->pXStateR3->x87.aXMM[15].uXmm.s.Hi;
296 iReg++;
297
298 /* Floating point state. */
299 aenmNames[iReg] = WHvX64RegisterFpMmx0;
300 aValues[iReg].Fp.AsUINT128.Low64 = pCtx->pXStateR3->x87.aRegs[0].au64[0];
301 aValues[iReg].Fp.AsUINT128.High64 = pCtx->pXStateR3->x87.aRegs[0].au64[1];
302 iReg++;
303 aenmNames[iReg] = WHvX64RegisterFpMmx1;
304 aValues[iReg].Fp.AsUINT128.Low64 = pCtx->pXStateR3->x87.aRegs[1].au64[0];
305 aValues[iReg].Fp.AsUINT128.High64 = pCtx->pXStateR3->x87.aRegs[1].au64[1];
306 iReg++;
307 aenmNames[iReg] = WHvX64RegisterFpMmx2;
308 aValues[iReg].Fp.AsUINT128.Low64 = pCtx->pXStateR3->x87.aRegs[2].au64[0];
309 aValues[iReg].Fp.AsUINT128.High64 = pCtx->pXStateR3->x87.aRegs[2].au64[1];
310 iReg++;
311 aenmNames[iReg] = WHvX64RegisterFpMmx3;
312 aValues[iReg].Fp.AsUINT128.Low64 = pCtx->pXStateR3->x87.aRegs[3].au64[0];
313 aValues[iReg].Fp.AsUINT128.High64 = pCtx->pXStateR3->x87.aRegs[3].au64[1];
314 iReg++;
315 aenmNames[iReg] = WHvX64RegisterFpMmx4;
316 aValues[iReg].Fp.AsUINT128.Low64 = pCtx->pXStateR3->x87.aRegs[4].au64[0];
317 aValues[iReg].Fp.AsUINT128.High64 = pCtx->pXStateR3->x87.aRegs[4].au64[1];
318 iReg++;
319 aenmNames[iReg] = WHvX64RegisterFpMmx5;
320 aValues[iReg].Fp.AsUINT128.Low64 = pCtx->pXStateR3->x87.aRegs[5].au64[0];
321 aValues[iReg].Fp.AsUINT128.High64 = pCtx->pXStateR3->x87.aRegs[5].au64[1];
322 iReg++;
323 aenmNames[iReg] = WHvX64RegisterFpMmx6;
324 aValues[iReg].Fp.AsUINT128.Low64 = pCtx->pXStateR3->x87.aRegs[6].au64[0];
325 aValues[iReg].Fp.AsUINT128.High64 = pCtx->pXStateR3->x87.aRegs[6].au64[1];
326 iReg++;
327 aenmNames[iReg] = WHvX64RegisterFpMmx7;
328 aValues[iReg].Fp.AsUINT128.Low64 = pCtx->pXStateR3->x87.aRegs[7].au64[0];
329 aValues[iReg].Fp.AsUINT128.High64 = pCtx->pXStateR3->x87.aRegs[7].au64[1];
330 iReg++;
331
332 aenmNames[iReg] = WHvX64RegisterFpControlStatus;
333 aValues[iReg].FpControlStatus.FpControl = pCtx->pXStateR3->x87.FCW;
334 aValues[iReg].FpControlStatus.FpStatus = pCtx->pXStateR3->x87.FSW;
335 aValues[iReg].FpControlStatus.FpTag = pCtx->pXStateR3->x87.FTW;
336 aValues[iReg].FpControlStatus.Reserved = pCtx->pXStateR3->x87.FTW >> 8;
337 aValues[iReg].FpControlStatus.LastFpOp = pCtx->pXStateR3->x87.FOP;
338 aValues[iReg].FpControlStatus.LastFpRip = (pCtx->pXStateR3->x87.FPUIP)
339 | ((uint64_t)pCtx->pXStateR3->x87.CS << 32)
340 | ((uint64_t)pCtx->pXStateR3->x87.Rsrvd1 << 48);
341 iReg++;
342
343 aenmNames[iReg] = WHvX64RegisterXmmControlStatus;
344 aValues[iReg].XmmControlStatus.LastFpRdp = (pCtx->pXStateR3->x87.FPUDP)
345 | ((uint64_t)pCtx->pXStateR3->x87.DS << 32)
346 | ((uint64_t)pCtx->pXStateR3->x87.Rsrvd2 << 48);
347 aValues[iReg].XmmControlStatus.XmmStatusControl = pCtx->pXStateR3->x87.MXCSR;
348 aValues[iReg].XmmControlStatus.XmmStatusControlMask = pCtx->pXStateR3->x87.MXCSR_MASK; /** @todo ??? (Isn't this an output field?) */
349 iReg++;
350
351 /* MSRs */
352 // WHvX64RegisterTsc - don't touch
353 aenmNames[iReg] = WHvX64RegisterEfer;
354 aValues[iReg].Reg64 = pCtx->msrEFER;
355 iReg++;
356 aenmNames[iReg] = WHvX64RegisterKernelGsBase;
357 aValues[iReg].Reg64 = pCtx->msrKERNELGSBASE;
358 iReg++;
359 aenmNames[iReg] = WHvX64RegisterApicBase;
360 aValues[iReg].Reg64 = APICGetBaseMsrNoCheck(pVCpu);
361 iReg++;
362 aenmNames[iReg] = WHvX64RegisterPat;
363 aValues[iReg].Reg64 = pCtx->msrPAT;
364 iReg++;
365 /// @todo WHvX64RegisterSysenterCs
366 /// @todo WHvX64RegisterSysenterEip
367 /// @todo WHvX64RegisterSysenterEsp
368 aenmNames[iReg] = WHvX64RegisterStar;
369 aValues[iReg].Reg64 = pCtx->msrSTAR;
370 iReg++;
371 aenmNames[iReg] = WHvX64RegisterLstar;
372 aValues[iReg].Reg64 = pCtx->msrLSTAR;
373 iReg++;
374 aenmNames[iReg] = WHvX64RegisterCstar;
375 aValues[iReg].Reg64 = pCtx->msrCSTAR;
376 iReg++;
377 aenmNames[iReg] = WHvX64RegisterSfmask;
378 aValues[iReg].Reg64 = pCtx->msrSFMASK;
379 iReg++;
380
381 /* event injection (always clear it). */
382 aenmNames[iReg] = WHvRegisterPendingInterruption;
383 aValues[iReg].Reg64 = 0;
384 iReg++;
385 /// @todo WHvRegisterInterruptState
386 /// @todo WHvRegisterPendingEvent0
387 /// @todo WHvRegisterPendingEvent1
388
389 /*
390 * Set the registers.
391 */
392 Assert(iReg < RT_ELEMENTS(aValues));
393 Assert(iReg < RT_ELEMENTS(aenmNames));
394# ifdef NEM_WIN_INTERCEPT_NT_IO_CTLS
395 Log12(("Calling WHvSetVirtualProcessorRegisters(%p, %u, %p, %u, %p)\n",
396 pVM->nem.s.hPartition, pVCpu->idCpu, aenmNames, iReg, aValues));
397# endif
398 HRESULT hrc = WHvSetVirtualProcessorRegisters(pVM->nem.s.hPartition, pVCpu->idCpu, aenmNames, iReg, aValues);
399 if (SUCCEEDED(hrc))
400 return VINF_SUCCESS;
401 AssertLogRelMsgFailed(("WHvSetVirtualProcessorRegisters(%p, %u,,%u,) -> %Rhrc (Last=%#x/%u)\n",
402 pVM->nem.s.hPartition, pVCpu->idCpu, iReg,
403 hrc, RTNtLastStatusValue(), RTNtLastErrorValue()));
404 return VERR_INTERNAL_ERROR;
405# endif /* !NEM_WIN_USE_HYPERCALLS_FOR_REGISTERS */
406}
407
408
409NEM_TMPL_STATIC int nemHCWinCopyStateFromHyperV(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, uint64_t fWhat)
410{
411# ifdef NEM_WIN_USE_HYPERCALLS_FOR_REGISTERS
412 /* See NEMR0ImportState */
413 NOREF(pCtx);
414 int rc = VMMR3CallR0Emt(pVM, pVCpu, VMMR0_DO_NEM_IMPORT_STATE, fWhat, NULL);
415 if (RT_SUCCESS(rc))
416 return rc;
417 if (rc == VERR_NEM_FLUSH_TLB)
418 return PGMFlushTLB(pVCpu, pCtx->cr3, true /*fGlobal*/);
419 if (rc == VERR_NEM_CHANGE_PGM_MODE)
420 return PGMChangeMode(pVCpu, pCtx->cr0, pCtx->cr4, pCtx->msrEFER);
421 AssertLogRelRCReturn(rc, rc);
422 return rc;
423
424# else
425 WHV_REGISTER_NAME aenmNames[128];
426
427 /* GPRs */
428 aenmNames[0] = WHvX64RegisterRax;
429 aenmNames[1] = WHvX64RegisterRcx;
430 aenmNames[2] = WHvX64RegisterRdx;
431 aenmNames[3] = WHvX64RegisterRbx;
432 aenmNames[4] = WHvX64RegisterRsp;
433 aenmNames[5] = WHvX64RegisterRbp;
434 aenmNames[6] = WHvX64RegisterRsi;
435 aenmNames[7] = WHvX64RegisterRdi;
436 aenmNames[8] = WHvX64RegisterR8;
437 aenmNames[9] = WHvX64RegisterR9;
438 aenmNames[10] = WHvX64RegisterR10;
439 aenmNames[11] = WHvX64RegisterR11;
440 aenmNames[12] = WHvX64RegisterR12;
441 aenmNames[13] = WHvX64RegisterR13;
442 aenmNames[14] = WHvX64RegisterR14;
443 aenmNames[15] = WHvX64RegisterR15;
444
445 /* RIP & Flags */
446 aenmNames[16] = WHvX64RegisterRip;
447 aenmNames[17] = WHvX64RegisterRflags;
448
449 /* Segments */
450 aenmNames[18] = WHvX64RegisterEs;
451 aenmNames[19] = WHvX64RegisterCs;
452 aenmNames[20] = WHvX64RegisterSs;
453 aenmNames[21] = WHvX64RegisterDs;
454 aenmNames[22] = WHvX64RegisterFs;
455 aenmNames[23] = WHvX64RegisterGs;
456 aenmNames[24] = WHvX64RegisterLdtr;
457 aenmNames[25] = WHvX64RegisterTr;
458
459 /* Descriptor tables. */
460 aenmNames[26] = WHvX64RegisterIdtr;
461 aenmNames[27] = WHvX64RegisterGdtr;
462
463 /* Control registers. */
464 aenmNames[28] = WHvX64RegisterCr0;
465 aenmNames[29] = WHvX64RegisterCr2;
466 aenmNames[30] = WHvX64RegisterCr3;
467 aenmNames[31] = WHvX64RegisterCr4;
468 aenmNames[32] = WHvX64RegisterCr8;
469
470 /* Debug registers. */
471 aenmNames[33] = WHvX64RegisterDr0;
472 aenmNames[34] = WHvX64RegisterDr1;
473 aenmNames[35] = WHvX64RegisterDr2;
474 aenmNames[36] = WHvX64RegisterDr3;
475 aenmNames[37] = WHvX64RegisterDr6;
476 aenmNames[38] = WHvX64RegisterDr7;
477
478 /* Vector state. */
479 aenmNames[39] = WHvX64RegisterXmm0;
480 aenmNames[40] = WHvX64RegisterXmm1;
481 aenmNames[41] = WHvX64RegisterXmm2;
482 aenmNames[42] = WHvX64RegisterXmm3;
483 aenmNames[43] = WHvX64RegisterXmm4;
484 aenmNames[44] = WHvX64RegisterXmm5;
485 aenmNames[45] = WHvX64RegisterXmm6;
486 aenmNames[46] = WHvX64RegisterXmm7;
487 aenmNames[47] = WHvX64RegisterXmm8;
488 aenmNames[48] = WHvX64RegisterXmm9;
489 aenmNames[49] = WHvX64RegisterXmm10;
490 aenmNames[50] = WHvX64RegisterXmm11;
491 aenmNames[51] = WHvX64RegisterXmm12;
492 aenmNames[52] = WHvX64RegisterXmm13;
493 aenmNames[53] = WHvX64RegisterXmm14;
494 aenmNames[54] = WHvX64RegisterXmm15;
495
496 /* Floating point state. */
497 aenmNames[55] = WHvX64RegisterFpMmx0;
498 aenmNames[56] = WHvX64RegisterFpMmx1;
499 aenmNames[57] = WHvX64RegisterFpMmx2;
500 aenmNames[58] = WHvX64RegisterFpMmx3;
501 aenmNames[59] = WHvX64RegisterFpMmx4;
502 aenmNames[60] = WHvX64RegisterFpMmx5;
503 aenmNames[61] = WHvX64RegisterFpMmx6;
504 aenmNames[62] = WHvX64RegisterFpMmx7;
505 aenmNames[63] = WHvX64RegisterFpControlStatus;
506 aenmNames[64] = WHvX64RegisterXmmControlStatus;
507
508 /* MSRs */
509 // WHvX64RegisterTsc - don't touch
510 aenmNames[65] = WHvX64RegisterEfer;
511 aenmNames[66] = WHvX64RegisterKernelGsBase;
512 aenmNames[67] = WHvX64RegisterApicBase;
513 aenmNames[68] = WHvX64RegisterPat;
514 aenmNames[69] = WHvX64RegisterSysenterCs;
515 aenmNames[70] = WHvX64RegisterSysenterEip;
516 aenmNames[71] = WHvX64RegisterSysenterEsp;
517 aenmNames[72] = WHvX64RegisterStar;
518 aenmNames[73] = WHvX64RegisterLstar;
519 aenmNames[74] = WHvX64RegisterCstar;
520 aenmNames[75] = WHvX64RegisterSfmask;
521
522 /* event injection */
523 aenmNames[76] = WHvRegisterPendingInterruption;
524 aenmNames[77] = WHvRegisterInterruptState;
525 aenmNames[78] = WHvRegisterInterruptState;
526 aenmNames[79] = WHvRegisterPendingEvent0;
527 aenmNames[80] = WHvRegisterPendingEvent1;
528 unsigned const cRegs = 81;
529
530 /*
531 * Get the registers.
532 */
533 WHV_REGISTER_VALUE aValues[cRegs];
534 RT_ZERO(aValues);
535 Assert(RT_ELEMENTS(aValues) >= cRegs);
536 Assert(RT_ELEMENTS(aenmNames) >= cRegs);
537# ifdef NEM_WIN_INTERCEPT_NT_IO_CTLS
538 Log12(("Calling WHvGetVirtualProcessorRegisters(%p, %u, %p, %u, %p)\n",
539 pVM->nem.s.hPartition, pVCpu->idCpu, aenmNames, cRegs, aValues));
540# endif
541 HRESULT hrc = WHvGetVirtualProcessorRegisters(pVM->nem.s.hPartition, pVCpu->idCpu, aenmNames, cRegs, aValues);
542 if (SUCCEEDED(hrc))
543 {
544 /* GPRs */
545 Assert(aenmNames[0] == WHvX64RegisterRax);
546 Assert(aenmNames[15] == WHvX64RegisterR15);
547 pCtx->rax = aValues[0].Reg64;
548 pCtx->rcx = aValues[1].Reg64;
549 pCtx->rdx = aValues[2].Reg64;
550 pCtx->rbx = aValues[3].Reg64;
551 pCtx->rsp = aValues[4].Reg64;
552 pCtx->rbp = aValues[5].Reg64;
553 pCtx->rsi = aValues[6].Reg64;
554 pCtx->rdi = aValues[7].Reg64;
555 pCtx->r8 = aValues[8].Reg64;
556 pCtx->r9 = aValues[9].Reg64;
557 pCtx->r10 = aValues[10].Reg64;
558 pCtx->r11 = aValues[11].Reg64;
559 pCtx->r12 = aValues[12].Reg64;
560 pCtx->r13 = aValues[13].Reg64;
561 pCtx->r14 = aValues[14].Reg64;
562 pCtx->r15 = aValues[15].Reg64;
563
564 /* RIP & Flags */
565 Assert(aenmNames[16] == WHvX64RegisterRip);
566 pCtx->rip = aValues[16].Reg64;
567 pCtx->rflags.u = aValues[17].Reg64;
568
569 /* Segments */
570# define COPY_BACK_SEG(a_idx, a_enmName, a_SReg) \
571 do { \
572 Assert(aenmNames[a_idx] == a_enmName); \
573 NEM_WIN_COPY_BACK_SEG(a_SReg, aValues[a_idx]); \
574 } while (0)
575 COPY_BACK_SEG(18, WHvX64RegisterEs, pCtx->es);
576 COPY_BACK_SEG(19, WHvX64RegisterCs, pCtx->cs);
577 COPY_BACK_SEG(20, WHvX64RegisterSs, pCtx->ss);
578 COPY_BACK_SEG(21, WHvX64RegisterDs, pCtx->ds);
579 COPY_BACK_SEG(22, WHvX64RegisterFs, pCtx->fs);
580 COPY_BACK_SEG(23, WHvX64RegisterGs, pCtx->gs);
581 COPY_BACK_SEG(24, WHvX64RegisterLdtr, pCtx->ldtr);
582 COPY_BACK_SEG(25, WHvX64RegisterTr, pCtx->tr);
583
584 /* Descriptor tables. */
585 Assert(aenmNames[26] == WHvX64RegisterIdtr);
586 pCtx->idtr.cbIdt = aValues[26].Table.Limit;
587 pCtx->idtr.pIdt = aValues[26].Table.Base;
588 Assert(aenmNames[27] == WHvX64RegisterGdtr);
589 pCtx->gdtr.cbGdt = aValues[27].Table.Limit;
590 pCtx->gdtr.pGdt = aValues[27].Table.Base;
591
592 /* Control registers. */
593 Assert(aenmNames[28] == WHvX64RegisterCr0);
594 bool fMaybeChangedMode = false;
595 bool fFlushTlb = false;
596 bool fFlushGlobalTlb = false;
597 if (pCtx->cr0 != aValues[28].Reg64)
598 {
599 CPUMSetGuestCR0(pVCpu, aValues[28].Reg64);
600 fMaybeChangedMode = true;
601 fFlushTlb = fFlushGlobalTlb = true; /// @todo fix this
602 }
603 Assert(aenmNames[29] == WHvX64RegisterCr2);
604 pCtx->cr2 = aValues[29].Reg64;
605 if (pCtx->cr3 != aValues[30].Reg64)
606 {
607 CPUMSetGuestCR3(pVCpu, aValues[30].Reg64);
608 fFlushTlb = true;
609 }
610 if (pCtx->cr4 != aValues[31].Reg64)
611 {
612 CPUMSetGuestCR4(pVCpu, aValues[31].Reg64);
613 fMaybeChangedMode = true;
614 fFlushTlb = fFlushGlobalTlb = true; /// @todo fix this
615 }
616 APICSetTpr(pVCpu, (uint8_t)aValues[32].Reg64 << 4);
617
618 /* Debug registers. */
619 Assert(aenmNames[33] == WHvX64RegisterDr0);
620 /** @todo fixme */
621 if (pCtx->dr[0] != aValues[33].Reg64)
622 CPUMSetGuestDR0(pVCpu, aValues[33].Reg64);
623 if (pCtx->dr[1] != aValues[34].Reg64)
624 CPUMSetGuestDR1(pVCpu, aValues[34].Reg64);
625 if (pCtx->dr[2] != aValues[35].Reg64)
626 CPUMSetGuestDR2(pVCpu, aValues[35].Reg64);
627 if (pCtx->dr[3] != aValues[36].Reg64)
628 CPUMSetGuestDR3(pVCpu, aValues[36].Reg64);
629 Assert(aenmNames[37] == WHvX64RegisterDr6);
630 Assert(aenmNames[38] == WHvX64RegisterDr7);
631 if (pCtx->dr[6] != aValues[37].Reg64)
632 CPUMSetGuestDR6(pVCpu, aValues[37].Reg64);
633 if (pCtx->dr[7] != aValues[38].Reg64)
634 CPUMSetGuestDR6(pVCpu, aValues[38].Reg64);
635
636 /* Vector state. */
637 Assert(aenmNames[39] == WHvX64RegisterXmm0);
638 Assert(aenmNames[54] == WHvX64RegisterXmm15);
639 pCtx->pXStateR3->x87.aXMM[0].uXmm.s.Lo = aValues[39].Reg128.Low64;
640 pCtx->pXStateR3->x87.aXMM[0].uXmm.s.Hi = aValues[39].Reg128.High64;
641 pCtx->pXStateR3->x87.aXMM[1].uXmm.s.Lo = aValues[40].Reg128.Low64;
642 pCtx->pXStateR3->x87.aXMM[1].uXmm.s.Hi = aValues[40].Reg128.High64;
643 pCtx->pXStateR3->x87.aXMM[2].uXmm.s.Lo = aValues[41].Reg128.Low64;
644 pCtx->pXStateR3->x87.aXMM[2].uXmm.s.Hi = aValues[41].Reg128.High64;
645 pCtx->pXStateR3->x87.aXMM[3].uXmm.s.Lo = aValues[42].Reg128.Low64;
646 pCtx->pXStateR3->x87.aXMM[3].uXmm.s.Hi = aValues[42].Reg128.High64;
647 pCtx->pXStateR3->x87.aXMM[4].uXmm.s.Lo = aValues[43].Reg128.Low64;
648 pCtx->pXStateR3->x87.aXMM[4].uXmm.s.Hi = aValues[43].Reg128.High64;
649 pCtx->pXStateR3->x87.aXMM[5].uXmm.s.Lo = aValues[44].Reg128.Low64;
650 pCtx->pXStateR3->x87.aXMM[5].uXmm.s.Hi = aValues[44].Reg128.High64;
651 pCtx->pXStateR3->x87.aXMM[6].uXmm.s.Lo = aValues[45].Reg128.Low64;
652 pCtx->pXStateR3->x87.aXMM[6].uXmm.s.Hi = aValues[45].Reg128.High64;
653 pCtx->pXStateR3->x87.aXMM[7].uXmm.s.Lo = aValues[46].Reg128.Low64;
654 pCtx->pXStateR3->x87.aXMM[7].uXmm.s.Hi = aValues[46].Reg128.High64;
655 pCtx->pXStateR3->x87.aXMM[8].uXmm.s.Lo = aValues[47].Reg128.Low64;
656 pCtx->pXStateR3->x87.aXMM[8].uXmm.s.Hi = aValues[47].Reg128.High64;
657 pCtx->pXStateR3->x87.aXMM[9].uXmm.s.Lo = aValues[48].Reg128.Low64;
658 pCtx->pXStateR3->x87.aXMM[9].uXmm.s.Hi = aValues[48].Reg128.High64;
659 pCtx->pXStateR3->x87.aXMM[10].uXmm.s.Lo = aValues[49].Reg128.Low64;
660 pCtx->pXStateR3->x87.aXMM[10].uXmm.s.Hi = aValues[49].Reg128.High64;
661 pCtx->pXStateR3->x87.aXMM[11].uXmm.s.Lo = aValues[50].Reg128.Low64;
662 pCtx->pXStateR3->x87.aXMM[11].uXmm.s.Hi = aValues[50].Reg128.High64;
663 pCtx->pXStateR3->x87.aXMM[12].uXmm.s.Lo = aValues[51].Reg128.Low64;
664 pCtx->pXStateR3->x87.aXMM[12].uXmm.s.Hi = aValues[51].Reg128.High64;
665 pCtx->pXStateR3->x87.aXMM[13].uXmm.s.Lo = aValues[52].Reg128.Low64;
666 pCtx->pXStateR3->x87.aXMM[13].uXmm.s.Hi = aValues[52].Reg128.High64;
667 pCtx->pXStateR3->x87.aXMM[14].uXmm.s.Lo = aValues[53].Reg128.Low64;
668 pCtx->pXStateR3->x87.aXMM[14].uXmm.s.Hi = aValues[53].Reg128.High64;
669 pCtx->pXStateR3->x87.aXMM[15].uXmm.s.Lo = aValues[54].Reg128.Low64;
670 pCtx->pXStateR3->x87.aXMM[15].uXmm.s.Hi = aValues[54].Reg128.High64;
671
672 /* Floating point state. */
673 Assert(aenmNames[55] == WHvX64RegisterFpMmx0);
674 Assert(aenmNames[62] == WHvX64RegisterFpMmx7);
675 pCtx->pXStateR3->x87.aRegs[0].au64[0] = aValues[55].Fp.AsUINT128.Low64;
676 pCtx->pXStateR3->x87.aRegs[0].au64[1] = aValues[55].Fp.AsUINT128.High64;
677 pCtx->pXStateR3->x87.aRegs[1].au64[0] = aValues[56].Fp.AsUINT128.Low64;
678 pCtx->pXStateR3->x87.aRegs[1].au64[1] = aValues[56].Fp.AsUINT128.High64;
679 pCtx->pXStateR3->x87.aRegs[2].au64[0] = aValues[57].Fp.AsUINT128.Low64;
680 pCtx->pXStateR3->x87.aRegs[2].au64[1] = aValues[57].Fp.AsUINT128.High64;
681 pCtx->pXStateR3->x87.aRegs[3].au64[0] = aValues[58].Fp.AsUINT128.Low64;
682 pCtx->pXStateR3->x87.aRegs[3].au64[1] = aValues[58].Fp.AsUINT128.High64;
683 pCtx->pXStateR3->x87.aRegs[4].au64[0] = aValues[59].Fp.AsUINT128.Low64;
684 pCtx->pXStateR3->x87.aRegs[4].au64[1] = aValues[59].Fp.AsUINT128.High64;
685 pCtx->pXStateR3->x87.aRegs[5].au64[0] = aValues[60].Fp.AsUINT128.Low64;
686 pCtx->pXStateR3->x87.aRegs[5].au64[1] = aValues[60].Fp.AsUINT128.High64;
687 pCtx->pXStateR3->x87.aRegs[6].au64[0] = aValues[61].Fp.AsUINT128.Low64;
688 pCtx->pXStateR3->x87.aRegs[6].au64[1] = aValues[61].Fp.AsUINT128.High64;
689 pCtx->pXStateR3->x87.aRegs[7].au64[0] = aValues[62].Fp.AsUINT128.Low64;
690 pCtx->pXStateR3->x87.aRegs[7].au64[1] = aValues[62].Fp.AsUINT128.High64;
691
692 Assert(aenmNames[63] == WHvX64RegisterFpControlStatus);
693 pCtx->pXStateR3->x87.FCW = aValues[63].FpControlStatus.FpControl;
694 pCtx->pXStateR3->x87.FSW = aValues[63].FpControlStatus.FpStatus;
695 pCtx->pXStateR3->x87.FTW = aValues[63].FpControlStatus.FpTag
696 /*| (aValues[63].FpControlStatus.Reserved << 8)*/;
697 pCtx->pXStateR3->x87.FOP = aValues[63].FpControlStatus.LastFpOp;
698 pCtx->pXStateR3->x87.FPUIP = (uint32_t)aValues[63].FpControlStatus.LastFpRip;
699 pCtx->pXStateR3->x87.CS = (uint16_t)(aValues[63].FpControlStatus.LastFpRip >> 32);
700 pCtx->pXStateR3->x87.Rsrvd1 = (uint16_t)(aValues[63].FpControlStatus.LastFpRip >> 48);
701
702 Assert(aenmNames[64] == WHvX64RegisterXmmControlStatus);
703 pCtx->pXStateR3->x87.FPUDP = (uint32_t)aValues[64].XmmControlStatus.LastFpRdp;
704 pCtx->pXStateR3->x87.DS = (uint16_t)(aValues[64].XmmControlStatus.LastFpRdp >> 32);
705 pCtx->pXStateR3->x87.Rsrvd2 = (uint16_t)(aValues[64].XmmControlStatus.LastFpRdp >> 48);
706 pCtx->pXStateR3->x87.MXCSR = aValues[64].XmmControlStatus.XmmStatusControl;
707 pCtx->pXStateR3->x87.MXCSR_MASK = aValues[64].XmmControlStatus.XmmStatusControlMask; /** @todo ??? (Isn't this an output field?) */
708
709 /* MSRs */
710 // WHvX64RegisterTsc - don't touch
711 Assert(aenmNames[65] == WHvX64RegisterEfer);
712 if (aValues[65].Reg64 != pCtx->msrEFER)
713 {
714 pCtx->msrEFER = aValues[65].Reg64;
715 fMaybeChangedMode = true;
716 }
717
718 Assert(aenmNames[66] == WHvX64RegisterKernelGsBase);
719 pCtx->msrKERNELGSBASE = aValues[66].Reg64;
720
721 Assert(aenmNames[67] == WHvX64RegisterApicBase);
722 if (aValues[67].Reg64 != APICGetBaseMsrNoCheck(pVCpu))
723 {
724 VBOXSTRICTRC rc2 = APICSetBaseMsr(pVCpu, aValues[67].Reg64);
725 Assert(rc2 == VINF_SUCCESS); NOREF(rc2);
726 }
727
728 Assert(aenmNames[68] == WHvX64RegisterPat);
729 pCtx->msrPAT = aValues[68].Reg64;
730 /// @todo WHvX64RegisterSysenterCs
731 /// @todo WHvX64RegisterSysenterEip
732 /// @todo WHvX64RegisterSysenterEsp
733 Assert(aenmNames[72] == WHvX64RegisterStar);
734 pCtx->msrSTAR = aValues[72].Reg64;
735 Assert(aenmNames[73] == WHvX64RegisterLstar);
736 pCtx->msrLSTAR = aValues[73].Reg64;
737 Assert(aenmNames[74] == WHvX64RegisterCstar);
738 pCtx->msrCSTAR = aValues[74].Reg64;
739 Assert(aenmNames[75] == WHvX64RegisterSfmask);
740 pCtx->msrSFMASK = aValues[75].Reg64;
741
742 /// @todo WHvRegisterPendingInterruption
743 Assert(aenmNames[76] == WHvRegisterPendingInterruption);
744 WHV_X64_PENDING_INTERRUPTION_REGISTER const * pPendingInt = (WHV_X64_PENDING_INTERRUPTION_REGISTER const *)&aValues[76];
745 if (pPendingInt->InterruptionPending)
746 {
747 Log7(("PendingInterruption: type=%u vector=%#x errcd=%RTbool/%#x instr-len=%u nested=%u\n",
748 pPendingInt->InterruptionType, pPendingInt->InterruptionVector, pPendingInt->DeliverErrorCode,
749 pPendingInt->ErrorCode, pPendingInt->InstructionLength, pPendingInt->NestedEvent));
750 AssertMsg((pPendingInt->AsUINT64 & UINT64_C(0xfc00)) == 0, ("%#RX64\n", pPendingInt->AsUINT64));
751 }
752
753 /// @todo WHvRegisterInterruptState
754 /// @todo WHvRegisterPendingEvent0
755 /// @todo WHvRegisterPendingEvent1
756
757 pCtx->fExtrn = 0;
758
759 if (fMaybeChangedMode)
760 {
761 int rc = PGMChangeMode(pVCpu, pCtx->cr0, pCtx->cr4, pCtx->msrEFER);
762 AssertRC(rc);
763 }
764 if (fFlushTlb)
765 {
766 int rc = PGMFlushTLB(pVCpu, pCtx->cr3, fFlushGlobalTlb);
767 AssertRC(rc);
768 }
769
770 return VINF_SUCCESS;
771 }
772
773 AssertLogRelMsgFailed(("WHvGetVirtualProcessorRegisters(%p, %u,,%u,) -> %Rhrc (Last=%#x/%u)\n",
774 pVM->nem.s.hPartition, pVCpu->idCpu, cRegs,
775 hrc, RTNtLastStatusValue(), RTNtLastErrorValue()));
776 return VERR_INTERNAL_ERROR;
777# endif /* !NEM_WIN_USE_HYPERCALLS_FOR_REGISTERS */
778}
779
780#endif /* !IN_RING0 */
781
782
783#ifdef LOG_ENABLED
784/**
785 * Get the virtual processor running status.
786 */
787DECLINLINE(VID_PROCESSOR_STATUS) nemHCWinCpuGetRunningStatus(PVMCPU pVCpu)
788{
789# ifdef IN_RING0
790 NOREF(pVCpu);
791 return VidProcessorStatusUndefined;
792# else
793 RTERRVARS Saved;
794 RTErrVarsSave(&Saved);
795
796 /*
797 * This API is disabled in release builds, it seems. On build 17101 it requires
798 * the following patch to be enabled (windbg): eb vid+12180 0f 84 98 00 00 00
799 */
800 VID_PROCESSOR_STATUS enmCpuStatus = VidProcessorStatusUndefined;
801 NTSTATUS rcNt = g_pfnVidGetVirtualProcessorRunningStatus(pVCpu->pVMR3->nem.s.hPartitionDevice, pVCpu->idCpu, &enmCpuStatus);
802 AssertRC(rcNt);
803
804 RTErrVarsRestore(&Saved);
805 return enmCpuStatus;
806# endif
807}
808#endif
809
810
811#ifdef NEM_WIN_USE_OUR_OWN_RUN_API
812# ifdef IN_RING3 /* hopefully not needed in ring-0, as we'd need KTHREADs and KeAlertThread. */
813/**
814 * Our own WHvCancelRunVirtualProcessor that can later be moved to ring-0.
815 *
816 * This is an experiment only.
817 *
818 * @returns VBox status code.
819 * @param pVM The cross context VM structure.
820 * @param pVCpu The cross context virtual CPU structure of the
821 * calling EMT.
822 */
823NEM_TMPL_STATIC int nemHCWinCancelRunVirtualProcessor(PVM pVM, PVMCPU pVCpu)
824{
825 /*
826 * Work the state.
827 *
828 * From the looks of things, we should let the EMT call VidStopVirtualProcessor.
829 * So, we just need to modify the state and kick the EMT if it's waiting on
830 * messages. For the latter we use QueueUserAPC / KeAlterThread.
831 */
832 for (;;)
833 {
834 VMCPUSTATE enmState = VMCPU_GET_STATE(pVCpu);
835 switch (enmState)
836 {
837 case VMCPUSTATE_STARTED_EXEC_NEM:
838 if (VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC_NEM_CANCELED, VMCPUSTATE_STARTED_EXEC_NEM))
839 {
840 Log8(("nemHCWinCancelRunVirtualProcessor: Switched %u to canceled state\n", pVCpu->idCpu));
841 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatCancelChangedState);
842 return VINF_SUCCESS;
843 }
844 break;
845
846 case VMCPUSTATE_STARTED_EXEC_NEM_WAIT:
847 if (VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC_NEM_CANCELED, VMCPUSTATE_STARTED_EXEC_NEM_WAIT))
848 {
849# ifdef IN_RING0
850 NTSTATUS rcNt = KeAlertThread(??);
851# else
852 NTSTATUS rcNt = NtAlertThread(pVCpu->nem.s.hNativeThreadHandle);
853# endif
854 Log8(("nemHCWinCancelRunVirtualProcessor: Alerted %u: %#x\n", pVCpu->idCpu, rcNt));
855 Assert(rcNt == STATUS_SUCCESS);
856 if (NT_SUCCESS(rcNt))
857 {
858 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatCancelAlertedThread);
859 return VINF_SUCCESS;
860 }
861 AssertLogRelMsgFailedReturn(("NtAlertThread failed: %#x\n", rcNt), RTErrConvertFromNtStatus(rcNt));
862 }
863 break;
864
865 default:
866 return VINF_SUCCESS;
867 }
868
869 ASMNopPause();
870 RT_NOREF(pVM);
871 }
872}
873# endif /* IN_RING3 */
874#endif /* NEM_WIN_USE_OUR_OWN_RUN_API */
875
876
877#ifdef LOG_ENABLED
878/**
879 * Logs the current CPU state.
880 */
881NEM_TMPL_STATIC void nemHCWinLogState(PVM pVM, PVMCPU pVCpu)
882{
883 if (LogIs3Enabled())
884 {
885# ifdef IN_RING3
886 char szRegs[4096];
887 DBGFR3RegPrintf(pVM->pUVM, pVCpu->idCpu, &szRegs[0], sizeof(szRegs),
888 "rax=%016VR{rax} rbx=%016VR{rbx} rcx=%016VR{rcx} rdx=%016VR{rdx}\n"
889 "rsi=%016VR{rsi} rdi=%016VR{rdi} r8 =%016VR{r8} r9 =%016VR{r9}\n"
890 "r10=%016VR{r10} r11=%016VR{r11} r12=%016VR{r12} r13=%016VR{r13}\n"
891 "r14=%016VR{r14} r15=%016VR{r15} %VRF{rflags}\n"
892 "rip=%016VR{rip} rsp=%016VR{rsp} rbp=%016VR{rbp}\n"
893 "cs={%04VR{cs} base=%016VR{cs_base} limit=%08VR{cs_lim} flags=%04VR{cs_attr}} cr0=%016VR{cr0}\n"
894 "ds={%04VR{ds} base=%016VR{ds_base} limit=%08VR{ds_lim} flags=%04VR{ds_attr}} cr2=%016VR{cr2}\n"
895 "es={%04VR{es} base=%016VR{es_base} limit=%08VR{es_lim} flags=%04VR{es_attr}} cr3=%016VR{cr3}\n"
896 "fs={%04VR{fs} base=%016VR{fs_base} limit=%08VR{fs_lim} flags=%04VR{fs_attr}} cr4=%016VR{cr4}\n"
897 "gs={%04VR{gs} base=%016VR{gs_base} limit=%08VR{gs_lim} flags=%04VR{gs_attr}} cr8=%016VR{cr8}\n"
898 "ss={%04VR{ss} base=%016VR{ss_base} limit=%08VR{ss_lim} flags=%04VR{ss_attr}}\n"
899 "dr0=%016VR{dr0} dr1=%016VR{dr1} dr2=%016VR{dr2} dr3=%016VR{dr3}\n"
900 "dr6=%016VR{dr6} dr7=%016VR{dr7}\n"
901 "gdtr=%016VR{gdtr_base}:%04VR{gdtr_lim} idtr=%016VR{idtr_base}:%04VR{idtr_lim} rflags=%08VR{rflags}\n"
902 "ldtr={%04VR{ldtr} base=%016VR{ldtr_base} limit=%08VR{ldtr_lim} flags=%08VR{ldtr_attr}}\n"
903 "tr ={%04VR{tr} base=%016VR{tr_base} limit=%08VR{tr_lim} flags=%08VR{tr_attr}}\n"
904 " sysenter={cs=%04VR{sysenter_cs} eip=%08VR{sysenter_eip} esp=%08VR{sysenter_esp}}\n"
905 " efer=%016VR{efer}\n"
906 " pat=%016VR{pat}\n"
907 " sf_mask=%016VR{sf_mask}\n"
908 "krnl_gs_base=%016VR{krnl_gs_base}\n"
909 " lstar=%016VR{lstar}\n"
910 " star=%016VR{star} cstar=%016VR{cstar}\n"
911 "fcw=%04VR{fcw} fsw=%04VR{fsw} ftw=%04VR{ftw} mxcsr=%04VR{mxcsr} mxcsr_mask=%04VR{mxcsr_mask}\n"
912 );
913
914 char szInstr[256];
915 DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, 0, 0,
916 DBGF_DISAS_FLAGS_CURRENT_GUEST | DBGF_DISAS_FLAGS_DEFAULT_MODE,
917 szInstr, sizeof(szInstr), NULL);
918 Log3(("%s%s\n", szRegs, szInstr));
919# else
920 /** @todo stat logging in ring-0 */
921 RT_NOREF(pVM, pVCpu);
922# endif
923 }
924}
925#endif /* LOG_ENABLED */
926
927
928/**
929 * Advances the guest RIP and clear EFLAGS.RF.
930 *
931 * This may clear VMCPU_FF_INHIBIT_INTERRUPTS.
932 *
933 * @param pVCpu The cross context virtual CPU structure.
934 * @param pCtx The CPU context to update.
935 * @param pExitCtx The exit context.
936 */
937DECLINLINE(void) nemHCWinAdvanceGuestRipAndClearRF(PVMCPU pVCpu, PCPUMCTX pCtx, HV_X64_INTERCEPT_MESSAGE_HEADER const *pMsgHdr)
938{
939 Assert(!(pCtx->fExtrn & (CPUMCTX_EXTRN_RIP | CPUMCTX_EXTRN_RFLAGS)));
940
941 /* Advance the RIP. */
942 Assert(pMsgHdr->InstructionLength > 0 && pMsgHdr->InstructionLength < 16);
943 pCtx->rip += pMsgHdr->InstructionLength;
944 pCtx->rflags.Bits.u1RF = 0;
945
946 /* Update interrupt inhibition. */
947 if (!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
948 { /* likely */ }
949 else if (pCtx->rip != EMGetInhibitInterruptsPC(pVCpu))
950 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
951}
952
953
954NEM_TMPL_STATIC VBOXSTRICTRC
955nemHCWinHandleHalt(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
956{
957 NOREF(pVM); NOREF(pVCpu); NOREF(pCtx);
958 LogFlow(("nemHCWinHandleHalt\n"));
959 return VINF_EM_HALT;
960}
961
962
963NEM_TMPL_STATIC DECLCALLBACK(int)
964nemHCWinUnmapOnePageCallback(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, uint8_t *pu2NemState, void *pvUser)
965{
966 RT_NOREF_PV(pvUser);
967#ifdef NEM_WIN_USE_HYPERCALLS_FOR_PAGES
968 int rc = nemHCWinHypercallUnmapPage(pVM, pVCpu, GCPhys);
969 AssertRC(rc);
970 if (RT_SUCCESS(rc))
971#else
972 RT_NOREF_PV(pVCpu);
973 HRESULT hrc = WHvUnmapGpaRange(pVM->nem.s.hPartition, GCPhys, X86_PAGE_SIZE);
974 if (SUCCEEDED(hrc))
975#endif
976 {
977 Log5(("NEM GPA unmap all: %RGp (cMappedPages=%u)\n", GCPhys, pVM->nem.s.cMappedPages - 1));
978 *pu2NemState = NEM_WIN_PAGE_STATE_UNMAPPED;
979 }
980 else
981 {
982#ifdef NEM_WIN_USE_HYPERCALLS_FOR_PAGES
983 LogRel(("nemR3WinUnmapOnePageCallback: GCPhys=%RGp rc=%Rrc\n", GCPhys, rc));
984#else
985 LogRel(("nemR3WinUnmapOnePageCallback: GCPhys=%RGp %s hrc=%Rhrc (%#x) Last=%#x/%u (cMappedPages=%u)\n",
986 GCPhys, g_apszPageStates[*pu2NemState], hrc, hrc, RTNtLastStatusValue(),
987 RTNtLastErrorValue(), pVM->nem.s.cMappedPages));
988#endif
989 *pu2NemState = NEM_WIN_PAGE_STATE_NOT_SET;
990 }
991 if (pVM->nem.s.cMappedPages > 0)
992 ASMAtomicDecU32(&pVM->nem.s.cMappedPages);
993 return VINF_SUCCESS;
994}
995
996
997/**
998 * State to pass between nemHCWinHandleMemoryAccess / nemR3WinWHvHandleMemoryAccess
999 * and nemHCWinHandleMemoryAccessPageCheckerCallback.
1000 */
1001typedef struct NEMHCWINHMACPCCSTATE
1002{
1003 /** Input: Write access. */
1004 bool fWriteAccess;
1005 /** Output: Set if we did something. */
1006 bool fDidSomething;
1007 /** Output: Set it we should resume. */
1008 bool fCanResume;
1009} NEMHCWINHMACPCCSTATE;
1010
1011/**
1012 * @callback_method_impl{FNPGMPHYSNEMCHECKPAGE,
1013 * Worker for nemR3WinHandleMemoryAccess; pvUser points to a
1014 * NEMHCWINHMACPCCSTATE structure. }
1015 */
1016NEM_TMPL_STATIC DECLCALLBACK(int)
1017nemHCWinHandleMemoryAccessPageCheckerCallback(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, PPGMPHYSNEMPAGEINFO pInfo, void *pvUser)
1018{
1019 NEMHCWINHMACPCCSTATE *pState = (NEMHCWINHMACPCCSTATE *)pvUser;
1020 pState->fDidSomething = false;
1021 pState->fCanResume = false;
1022
1023 /* If A20 is disabled, we may need to make another query on the masked
1024 page to get the correct protection information. */
1025 uint8_t u2State = pInfo->u2NemState;
1026 RTGCPHYS GCPhysSrc;
1027 if ( pVM->nem.s.fA20Enabled
1028 || !NEM_WIN_IS_SUBJECT_TO_A20(GCPhys))
1029 GCPhysSrc = GCPhys;
1030 else
1031 {
1032 GCPhysSrc = GCPhys & ~(RTGCPHYS)RT_BIT_32(20);
1033 PGMPHYSNEMPAGEINFO Info2;
1034 int rc = PGMPhysNemPageInfoChecker(pVM, pVCpu, GCPhysSrc, pState->fWriteAccess, &Info2, NULL, NULL);
1035 AssertRCReturn(rc, rc);
1036
1037 *pInfo = Info2;
1038 pInfo->u2NemState = u2State;
1039 }
1040
1041 /*
1042 * Consolidate current page state with actual page protection and access type.
1043 * We don't really consider downgrades here, as they shouldn't happen.
1044 */
1045#ifndef NEM_WIN_USE_HYPERCALLS_FOR_PAGES
1046 /** @todo Someone at microsoft please explain:
1047 * I'm not sure WTF was going on, but I ended up in a loop if I remapped a
1048 * readonly page as writable (unmap, then map again). Specifically, this was an
1049 * issue with the big VRAM mapping at 0xe0000000 when booing DSL 4.4.1. So, in
1050 * a hope to work around that we no longer pre-map anything, just unmap stuff
1051 * and do it lazily here. And here we will first unmap, restart, and then remap
1052 * with new protection or backing.
1053 */
1054#endif
1055 int rc;
1056 switch (u2State)
1057 {
1058 case NEM_WIN_PAGE_STATE_UNMAPPED:
1059 case NEM_WIN_PAGE_STATE_NOT_SET:
1060 if (pInfo->fNemProt == NEM_PAGE_PROT_NONE)
1061 {
1062 Log4(("nemHCWinHandleMemoryAccessPageCheckerCallback: %RGp - #1\n", GCPhys));
1063 return VINF_SUCCESS;
1064 }
1065
1066 /* Don't bother remapping it if it's a write request to a non-writable page. */
1067 if ( pState->fWriteAccess
1068 && !(pInfo->fNemProt & NEM_PAGE_PROT_WRITE))
1069 {
1070 Log4(("nemHCWinHandleMemoryAccessPageCheckerCallback: %RGp - #1w\n", GCPhys));
1071 return VINF_SUCCESS;
1072 }
1073
1074 /* Map the page. */
1075 rc = nemHCNativeSetPhysPage(pVM,
1076 pVCpu,
1077 GCPhysSrc & ~(RTGCPHYS)X86_PAGE_OFFSET_MASK,
1078 GCPhys & ~(RTGCPHYS)X86_PAGE_OFFSET_MASK,
1079 pInfo->fNemProt,
1080 &u2State,
1081 true /*fBackingState*/);
1082 pInfo->u2NemState = u2State;
1083 Log4(("nemHCWinHandleMemoryAccessPageCheckerCallback: %RGp - synced => %s + %Rrc\n",
1084 GCPhys, g_apszPageStates[u2State], rc));
1085 pState->fDidSomething = true;
1086 pState->fCanResume = true;
1087 return rc;
1088
1089 case NEM_WIN_PAGE_STATE_READABLE:
1090 if ( !(pInfo->fNemProt & NEM_PAGE_PROT_WRITE)
1091 && (pInfo->fNemProt & (NEM_PAGE_PROT_READ | NEM_PAGE_PROT_EXECUTE)))
1092 {
1093 Log4(("nemHCWinHandleMemoryAccessPageCheckerCallback: %RGp - #2\n", GCPhys));
1094 return VINF_SUCCESS;
1095 }
1096
1097#ifdef NEM_WIN_USE_HYPERCALLS_FOR_PAGES
1098 /* Upgrade page to writable. */
1099/** @todo test this*/
1100 if ( (pInfo->fNemProt & NEM_PAGE_PROT_WRITE)
1101 && pState->fWriteAccess)
1102 {
1103 rc = nemHCWinHypercallMapPage(pVM, pVCpu, GCPhysSrc, GCPhys,
1104 HV_MAP_GPA_READABLE | HV_MAP_GPA_WRITABLE
1105 | HV_MAP_GPA_EXECUTABLE | HV_MAP_GPA_EXECUTABLE_AGAIN);
1106 AssertRC(rc);
1107 if (RT_SUCCESS(rc))
1108 {
1109 pInfo->u2NemState = NEM_WIN_PAGE_STATE_WRITABLE;
1110 pState->fDidSomething = true;
1111 pState->fCanResume = true;
1112 Log5(("NEM GPA write-upgrade/exit: %RGp (was %s, cMappedPages=%u)\n",
1113 GCPhys, g_apszPageStates[u2State], pVM->nem.s.cMappedPages));
1114 }
1115 }
1116 else
1117 {
1118 /* Need to emulate the acces. */
1119 AssertBreak(pInfo->fNemProt != NEM_PAGE_PROT_NONE); /* There should be no downgrades. */
1120 rc = VINF_SUCCESS;
1121 }
1122 return rc;
1123#else
1124 break;
1125#endif
1126
1127 case NEM_WIN_PAGE_STATE_WRITABLE:
1128 if (pInfo->fNemProt & NEM_PAGE_PROT_WRITE)
1129 {
1130 Log4(("nemHCWinHandleMemoryAccessPageCheckerCallback: %RGp - #3\n", GCPhys));
1131 return VINF_SUCCESS;
1132 }
1133#ifdef NEM_WIN_USE_HYPERCALLS_FOR_PAGES
1134 AssertFailed(); /* There should be no downgrades. */
1135#endif
1136 break;
1137
1138 default:
1139 AssertLogRelMsgFailedReturn(("u2State=%#x\n", u2State), VERR_INTERNAL_ERROR_3);
1140 }
1141
1142 /*
1143 * Unmap and restart the instruction.
1144 * If this fails, which it does every so often, just unmap everything for now.
1145 */
1146#ifdef NEM_WIN_USE_HYPERCALLS_FOR_PAGES
1147 rc = nemHCWinHypercallUnmapPage(pVM, pVCpu, GCPhys);
1148 AssertRC(rc);
1149 if (RT_SUCCESS(rc))
1150#else
1151 /** @todo figure out whether we mess up the state or if it's WHv. */
1152 HRESULT hrc = WHvUnmapGpaRange(pVM->nem.s.hPartition, GCPhys, X86_PAGE_SIZE);
1153 if (SUCCEEDED(hrc))
1154#endif
1155 {
1156 pState->fDidSomething = true;
1157 pState->fCanResume = true;
1158 pInfo->u2NemState = NEM_WIN_PAGE_STATE_UNMAPPED;
1159 uint32_t cMappedPages = ASMAtomicDecU32(&pVM->nem.s.cMappedPages); NOREF(cMappedPages);
1160 Log5(("NEM GPA unmapped/exit: %RGp (was %s, cMappedPages=%u)\n", GCPhys, g_apszPageStates[u2State], cMappedPages));
1161 return VINF_SUCCESS;
1162 }
1163#ifdef NEM_WIN_USE_HYPERCALLS_FOR_PAGES
1164 LogRel(("nemHCWinHandleMemoryAccessPageCheckerCallback/unmap: GCPhysDst=%RGp rc=%Rrc\n", GCPhys, rc));
1165 return rc;
1166#else
1167 LogRel(("nemHCWinHandleMemoryAccessPageCheckerCallback/unmap: GCPhysDst=%RGp %s hrc=%Rhrc (%#x) Last=%#x/%u (cMappedPages=%u)\n",
1168 GCPhys, g_apszPageStates[u2State], hrc, hrc, RTNtLastStatusValue(), RTNtLastErrorValue(),
1169 pVM->nem.s.cMappedPages));
1170
1171 PGMPhysNemEnumPagesByState(pVM, pVCpu, NEM_WIN_PAGE_STATE_READABLE, nemR3WinUnmapOnePageCallback, NULL);
1172 Log(("nemHCWinHandleMemoryAccessPageCheckerCallback: Unmapped all (cMappedPages=%u)\n", pVM->nem.s.cMappedPages));
1173
1174 pState->fDidSomething = true;
1175 pState->fCanResume = true;
1176 pInfo->u2NemState = NEM_WIN_PAGE_STATE_UNMAPPED;
1177 return VINF_SUCCESS;
1178#endif
1179}
1180
1181
1182#ifdef NEM_WIN_USE_OUR_OWN_RUN_API
1183
1184# ifdef IN_RING0
1185/**
1186 * Wrapper around nemR0WinImportState that converts VERR_NEM_CHANGE_PGM_MODE and
1187 * VERR_NEM_FLUSH_TBL into informational status codes and logs+asserts statuses.
1188 *
1189 * @returns VBox strict status code.
1190 * @param pGVM The global (ring-0) VM structure.
1191 * @param pGVCpu The global (ring-0) per CPU structure.
1192 * @param pCtx The CPU context to import into.
1193 * @param fWhat What to import.
1194 * @param pszCaller Whoe is doing the importing.
1195 */
1196DECLINLINE(VBOXSTRICTRC) nemR0WinImportStateStrict(PGVM pGVM, PGVMCPU pGVCpu, PCPUMCTX pCtx, uint64_t fWhat, const char *pszCaller)
1197{
1198 int rc = nemR0WinImportState(pGVM, pGVCpu, pCtx, fWhat);
1199 if (RT_SUCCESS(rc))
1200 {
1201 Assert(rc == VINF_SUCCESS);
1202 return VINF_SUCCESS;
1203 }
1204
1205 if (rc == VERR_NEM_CHANGE_PGM_MODE || rc == VERR_NEM_FLUSH_TLB)
1206 {
1207 Log4(("%s/%u: nemR0WinImportState -> %Rrc\n", pszCaller, pGVCpu->idCpu, -rc));
1208 return -rc;
1209 }
1210 RT_NOREF(pszCaller);
1211 AssertMsgFailedReturn(("%s/%u: nemR0WinImportState failed: %Rrc\n", pszCaller, pGVCpu->idCpu, rc), rc);
1212}
1213# endif /* IN_RING0 */
1214
1215/**
1216 * Copies register state from the X64 intercept message header.
1217 *
1218 * ASSUMES no state copied yet.
1219 *
1220 * @param pCtx The registe rcontext.
1221 * @param pHdr The X64 intercept message header.
1222 */
1223DECLINLINE(void) nemHCWinCopyStateFromX64Header(PCPUMCTX pCtx, HV_X64_INTERCEPT_MESSAGE_HEADER const *pHdr)
1224{
1225 Assert( (pCtx->fExtrn & (CPUMCTX_EXTRN_RIP | CPUMCTX_EXTRN_RFLAGS | CPUMCTX_EXTRN_CS))
1226 == (CPUMCTX_EXTRN_RIP | CPUMCTX_EXTRN_RFLAGS | CPUMCTX_EXTRN_CS));
1227 NEM_WIN_COPY_BACK_SEG(pCtx->cs, pHdr->CsSegment);
1228 pCtx->rip = pHdr->Rip;
1229 pCtx->rflags.u = pHdr->Rflags;
1230 pCtx->fExtrn &= ~(CPUMCTX_EXTRN_RIP | CPUMCTX_EXTRN_RFLAGS | CPUMCTX_EXTRN_CS);
1231}
1232
1233
1234/**
1235 * Deals with memory intercept message.
1236 *
1237 * @returns Strict VBox status code.
1238 * @param pVM The cross context VM structure.
1239 * @param pVCpu The cross context per CPU structure.
1240 * @param pMsg The message.
1241 * @param pCtx The register context.
1242 * @param pGVCpu The global (ring-0) per CPU structure (NULL in r3).
1243 */
1244NEM_TMPL_STATIC VBOXSTRICTRC nemHCWinHandleMessageMemory(PVM pVM, PVMCPU pVCpu, HV_X64_MEMORY_INTERCEPT_MESSAGE const *pMsg,
1245 PCPUMCTX pCtx, PGVMCPU pGVCpu)
1246{
1247 Assert( pMsg->Header.InterceptAccessType == HV_INTERCEPT_ACCESS_READ
1248 || pMsg->Header.InterceptAccessType == HV_INTERCEPT_ACCESS_WRITE
1249 || pMsg->Header.InterceptAccessType == HV_INTERCEPT_ACCESS_EXECUTE);
1250
1251 /*
1252 * Whatever we do, we must clear pending event ejection upon resume.
1253 */
1254 if (pMsg->Header.ExecutionState.InterruptionPending)
1255 pCtx->fExtrn &= ~CPUMCTX_EXTRN_NEM_WIN_MASK;
1256
1257 /*
1258 * Ask PGM for information about the given GCPhys. We need to check if we're
1259 * out of sync first.
1260 */
1261 NEMHCWINHMACPCCSTATE State = { pMsg->Header.InterceptAccessType == HV_INTERCEPT_ACCESS_WRITE, false, false };
1262 PGMPHYSNEMPAGEINFO Info;
1263 int rc = PGMPhysNemPageInfoChecker(pVM, pVCpu, pMsg->GuestPhysicalAddress, State.fWriteAccess, &Info,
1264 nemHCWinHandleMemoryAccessPageCheckerCallback, &State);
1265 if (RT_SUCCESS(rc))
1266 {
1267 if (Info.fNemProt & ( pMsg->Header.InterceptAccessType == HV_INTERCEPT_ACCESS_WRITE
1268 ? NEM_PAGE_PROT_WRITE : NEM_PAGE_PROT_READ))
1269 {
1270 if (State.fCanResume)
1271 {
1272 Log4(("MemExit/%u: %04x:%08RX64: %RGp (=>%RHp) %s fProt=%u%s%s%s; restarting (%s)\n",
1273 pVCpu->idCpu, pMsg->Header.CsSegment.Selector, pMsg->Header.Rip,
1274 pMsg->GuestPhysicalAddress, Info.HCPhys, g_apszPageStates[Info.u2NemState], Info.fNemProt,
1275 Info.fHasHandlers ? " handlers" : "", Info.fZeroPage ? " zero-pg" : "",
1276 State.fDidSomething ? "" : " no-change", g_apszHvInterceptAccessTypes[pMsg->Header.InterceptAccessType]));
1277 return VINF_SUCCESS;
1278 }
1279 }
1280 Log4(("MemExit/%u: %04x:%08RX64: %RGp (=>%RHp) %s fProt=%u%s%s%s; emulating (%s)\n",
1281 pVCpu->idCpu, pMsg->Header.CsSegment.Selector, pMsg->Header.Rip,
1282 pMsg->GuestPhysicalAddress, Info.HCPhys, g_apszPageStates[Info.u2NemState], Info.fNemProt,
1283 Info.fHasHandlers ? " handlers" : "", Info.fZeroPage ? " zero-pg" : "",
1284 State.fDidSomething ? "" : " no-change", g_apszHvInterceptAccessTypes[pMsg->Header.InterceptAccessType]));
1285 }
1286 else
1287 Log4(("MemExit/%u: %04x:%08RX64: %RGp rc=%Rrc%s; emulating (%s)\n",
1288 pVCpu->idCpu, pMsg->Header.CsSegment.Selector, pMsg->Header.Rip, pMsg->GuestPhysicalAddress, rc,
1289 State.fDidSomething ? " modified-backing" : "", g_apszHvInterceptAccessTypes[pMsg->Header.InterceptAccessType]));
1290
1291 /*
1292 * Emulate the memory access, either access handler or special memory.
1293 */
1294 nemHCWinCopyStateFromX64Header(pCtx, &pMsg->Header);
1295 VBOXSTRICTRC rcStrict;
1296# ifdef IN_RING0
1297 rcStrict = nemR0WinImportStateStrict(pGVCpu->pGVM, pGVCpu, pCtx, NEM_WIN_CPUMCTX_EXTRN_MASK_FOR_IEM, "MemExit");
1298 if (rcStrict != VINF_SUCCESS)
1299 return rcStrict;
1300# else
1301 rc = nemHCWinCopyStateFromHyperV(pVM, pVCpu, pCtx, NEM_WIN_CPUMCTX_EXTRN_MASK_FOR_IEM);
1302 AssertRCReturn(rc, rc);
1303 NOREF(pGVCpu);
1304# endif
1305
1306 if (pMsg->InstructionByteCount > 0)
1307 rcStrict = IEMExecOneWithPrefetchedByPC(pVCpu, CPUMCTX2CORE(pCtx), pMsg->Header.Rip,
1308 pMsg->InstructionBytes, pMsg->InstructionByteCount);
1309 else
1310 rcStrict = IEMExecOne(pVCpu);
1311 /** @todo do we need to do anything wrt debugging here? */
1312 return rcStrict;
1313
1314}
1315
1316
1317/**
1318 * Deals with I/O port intercept message.
1319 *
1320 * @returns Strict VBox status code.
1321 * @param pVM The cross context VM structure.
1322 * @param pVCpu The cross context per CPU structure.
1323 * @param pMsg The message.
1324 * @param pGVCpu The global (ring-0) per CPU structure (NULL in r3).
1325 */
1326NEM_TMPL_STATIC VBOXSTRICTRC nemHCWinHandleMessageIoPort(PVM pVM, PVMCPU pVCpu, HV_X64_IO_PORT_INTERCEPT_MESSAGE const *pMsg,
1327 PCPUMCTX pCtx, PGVMCPU pGVCpu)
1328{
1329 Assert( pMsg->AccessInfo.AccessSize == 1
1330 || pMsg->AccessInfo.AccessSize == 2
1331 || pMsg->AccessInfo.AccessSize == 4);
1332 Assert( pMsg->Header.InterceptAccessType == HV_INTERCEPT_ACCESS_READ
1333 || pMsg->Header.InterceptAccessType == HV_INTERCEPT_ACCESS_WRITE);
1334
1335 /*
1336 * Whatever we do, we must clear pending event ejection upon resume.
1337 */
1338 if (pMsg->Header.ExecutionState.InterruptionPending)
1339 pCtx->fExtrn &= ~CPUMCTX_EXTRN_NEM_WIN_MASK;
1340
1341 VBOXSTRICTRC rcStrict;
1342 if (!pMsg->AccessInfo.StringOp)
1343 {
1344 /*
1345 * Simple port I/O.
1346 */
1347 static uint32_t const s_fAndMask[8] =
1348 { UINT32_MAX, UINT32_C(0xff), UINT32_C(0xffff), UINT32_MAX, UINT32_MAX, UINT32_MAX, UINT32_MAX, UINT32_MAX };
1349 uint32_t const fAndMask = s_fAndMask[pMsg->AccessInfo.AccessSize];
1350 if (pMsg->Header.InterceptAccessType == HV_INTERCEPT_ACCESS_WRITE)
1351 {
1352 rcStrict = IOMIOPortWrite(pVM, pVCpu, pMsg->PortNumber, (uint32_t)pMsg->Rax & fAndMask, pMsg->AccessInfo.AccessSize);
1353 Log4(("IOExit/%u: %04x:%08RX64: OUT %#x, %#x LB %u rcStrict=%Rrc\n",
1354 pVCpu->idCpu, pMsg->Header.CsSegment.Selector, pMsg->Header.Rip, pMsg->PortNumber,
1355 (uint32_t)pMsg->Rax & fAndMask, pMsg->AccessInfo.AccessSize, VBOXSTRICTRC_VAL(rcStrict) ));
1356 if (IOM_SUCCESS(rcStrict))
1357 {
1358 nemHCWinCopyStateFromX64Header(pCtx, &pMsg->Header);
1359 nemHCWinAdvanceGuestRipAndClearRF(pVCpu, pCtx, &pMsg->Header);
1360 }
1361 }
1362 else
1363 {
1364 uint32_t uValue = 0;
1365 rcStrict = IOMIOPortRead(pVM, pVCpu, pMsg->PortNumber, &uValue, pMsg->AccessInfo.AccessSize);
1366 Log4(("IOExit/%u: %04x:%08RX64: IN %#x LB %u -> %#x, rcStrict=%Rrc\n", pVCpu->idCpu, pMsg->Header.CsSegment.Selector,
1367 pMsg->Header.Rip, pMsg->PortNumber, pMsg->AccessInfo.AccessSize, uValue, VBOXSTRICTRC_VAL(rcStrict) ));
1368 if (IOM_SUCCESS(rcStrict))
1369 {
1370 if (pMsg->AccessInfo.AccessSize != 4)
1371 pCtx->rax = (pMsg->Rax & ~(uint64_t)fAndMask) | (uValue & fAndMask);
1372 else
1373 pCtx->rax = uValue;
1374 pCtx->fExtrn &= ~CPUMCTX_EXTRN_RAX;
1375 Log4(("IOExit/%u: RAX %#RX64 -> %#RX64\n", pVCpu->idCpu, pMsg->Rax, pCtx->rax));
1376 nemHCWinCopyStateFromX64Header(pCtx, &pMsg->Header);
1377 nemHCWinAdvanceGuestRipAndClearRF(pVCpu, pCtx, &pMsg->Header);
1378 }
1379 }
1380 }
1381 else
1382 {
1383 /*
1384 * String port I/O.
1385 */
1386 /** @todo Someone at Microsoft please explain how we can get the address mode
1387 * from the IoPortAccess.VpContext. CS.Attributes is only sufficient for
1388 * getting the default mode, it can always be overridden by a prefix. This
1389 * forces us to interpret the instruction from opcodes, which is suboptimal.
1390 * Both AMD-V and VT-x includes the address size in the exit info, at least on
1391 * CPUs that are reasonably new.
1392 *
1393 * Of course, it's possible this is an undocumented and we just need to do some
1394 * experiments to figure out how it's communicated. Alternatively, we can scan
1395 * the opcode bytes for possible evil prefixes.
1396 */
1397 nemHCWinCopyStateFromX64Header(pCtx, &pMsg->Header);
1398 pCtx->fExtrn &= ~( CPUMCTX_EXTRN_RAX | CPUMCTX_EXTRN_RCX | CPUMCTX_EXTRN_RDI | CPUMCTX_EXTRN_RSI
1399 | CPUMCTX_EXTRN_DS | CPUMCTX_EXTRN_ES);
1400 NEM_WIN_COPY_BACK_SEG(pCtx->ds, pMsg->DsSegment);
1401 NEM_WIN_COPY_BACK_SEG(pCtx->es, pMsg->EsSegment);
1402 pCtx->rax = pMsg->Rax;
1403 pCtx->rcx = pMsg->Rcx;
1404 pCtx->rdi = pMsg->Rdi;
1405 pCtx->rsi = pMsg->Rsi;
1406# ifdef IN_RING0
1407 rcStrict = nemR0WinImportStateStrict(pGVCpu->pGVM, pGVCpu, pCtx, NEM_WIN_CPUMCTX_EXTRN_MASK_FOR_IEM, "IOExit");
1408 if (rcStrict != VINF_SUCCESS)
1409 return rcStrict;
1410# else
1411 int rc = nemHCWinCopyStateFromHyperV(pVM, pVCpu, pCtx, NEM_WIN_CPUMCTX_EXTRN_MASK_FOR_IEM);
1412 AssertRCReturn(rc, rc);
1413 RT_NOREF(pGVCpu);
1414# endif
1415
1416 Log4(("IOExit/%u: %04x:%08RX64: %s%s %#x LB %u (emulating)\n",
1417 pVCpu->idCpu, pMsg->Header.CsSegment.Selector, pMsg->Header.Rip,
1418 pMsg->AccessInfo.RepPrefix ? "REP " : "",
1419 pMsg->Header.InterceptAccessType == HV_INTERCEPT_ACCESS_WRITE ? "OUTS" : "INS",
1420 pMsg->PortNumber, pMsg->AccessInfo.AccessSize ));
1421 rcStrict = IEMExecOne(pVCpu);
1422 }
1423 if (IOM_SUCCESS(rcStrict))
1424 {
1425 /*
1426 * Do debug checks.
1427 */
1428 if ( pMsg->Header.ExecutionState.DebugActive /** @todo Microsoft: Does DebugActive this only reflext DR7? */
1429 || (pMsg->Header.Rflags & X86_EFL_TF)
1430 || DBGFBpIsHwIoArmed(pVM) )
1431 {
1432 /** @todo Debugging. */
1433 }
1434 }
1435 return rcStrict;
1436}
1437
1438
1439/**
1440 * Handles messages (VM exits).
1441 *
1442 * @returns Strict VBox status code.
1443 * @param pVM The cross context VM structure.
1444 * @param pVCpu The cross context per CPU structure.
1445 * @param pMappingHeader The message slot mapping.
1446 * @param pCtx The register context.
1447 * @param pGVCpu The global (ring-0) per CPU structure (NULL in r3).
1448 */
1449NEM_TMPL_STATIC VBOXSTRICTRC nemHCWinHandleMessage(PVM pVM, PVMCPU pVCpu, VID_MESSAGE_MAPPING_HEADER volatile *pMappingHeader,
1450 PCPUMCTX pCtx, PGVMCPU pGVCpu)
1451{
1452 if (pMappingHeader->enmVidMsgType == VidMessageHypervisorMessage)
1453 {
1454 AssertMsg(pMappingHeader->cbMessage == HV_MESSAGE_SIZE, ("%#x\n", pMappingHeader->cbMessage));
1455 HV_MESSAGE const *pMsg = (HV_MESSAGE const *)(pMappingHeader + 1);
1456 switch (pMsg->Header.MessageType)
1457 {
1458 case HvMessageTypeUnmappedGpa:
1459 Assert(pMsg->Header.PayloadSize == RT_UOFFSETOF(HV_X64_MEMORY_INTERCEPT_MESSAGE, DsSegment));
1460 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitMemUnmapped);
1461 return nemHCWinHandleMessageMemory(pVM, pVCpu, &pMsg->X64MemoryIntercept, pCtx, pGVCpu);
1462
1463 case HvMessageTypeGpaIntercept:
1464 Assert(pMsg->Header.PayloadSize == RT_UOFFSETOF(HV_X64_MEMORY_INTERCEPT_MESSAGE, DsSegment));
1465 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitMemIntercept);
1466 return nemHCWinHandleMessageMemory(pVM, pVCpu, &pMsg->X64MemoryIntercept, pCtx, pGVCpu);
1467
1468 case HvMessageTypeX64IoPortIntercept:
1469 Assert(pMsg->Header.PayloadSize == sizeof(pMsg->X64IoPortIntercept));
1470 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitPortIo);
1471 return nemHCWinHandleMessageIoPort(pVM, pVCpu, &pMsg->X64IoPortIntercept, pCtx, pGVCpu);
1472
1473 case HvMessageTypeX64Halt:
1474 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitHalt);
1475 return VINF_EM_HALT;
1476
1477 case HvMessageTypeX64InterruptWindow:
1478 AssertLogRelMsgFailedReturn(("Message type %#x not implemented!\n", pMsg->Header.MessageType),
1479 VERR_INTERNAL_ERROR_2);
1480
1481 case HvMessageTypeInvalidVpRegisterValue:
1482 case HvMessageTypeUnrecoverableException:
1483 case HvMessageTypeUnsupportedFeature:
1484 case HvMessageTypeTlbPageSizeMismatch:
1485 AssertLogRelMsgFailedReturn(("Message type %#x not implemented!\n", pMsg->Header.MessageType),
1486 VERR_INTERNAL_ERROR_2);
1487
1488 case HvMessageTypeX64MsrIntercept:
1489 case HvMessageTypeX64CpuidIntercept:
1490 case HvMessageTypeX64ExceptionIntercept:
1491 case HvMessageTypeX64ApicEoi:
1492 case HvMessageTypeX64LegacyFpError:
1493 case HvMessageTypeX64RegisterIntercept:
1494 case HvMessageTypeApicEoi:
1495 case HvMessageTypeFerrAsserted:
1496 case HvMessageTypeEventLogBufferComplete:
1497 case HvMessageTimerExpired:
1498 AssertLogRelMsgFailedReturn(("Unexpected message on CPU #%u: #x\n", pVCpu->idCpu, pMsg->Header.MessageType),
1499 VERR_INTERNAL_ERROR_2);
1500
1501 default:
1502 AssertLogRelMsgFailedReturn(("Unknown message on CPU #%u: #x\n", pVCpu->idCpu, pMsg->Header.MessageType),
1503 VERR_INTERNAL_ERROR_2);
1504 }
1505 }
1506 else
1507 AssertLogRelMsgFailedReturn(("Unexpected VID message type on CPU #%u: %#x LB %u\n",
1508 pVCpu->idCpu, pMappingHeader->enmVidMsgType, pMappingHeader->cbMessage),
1509 VERR_INTERNAL_ERROR_3);
1510}
1511
1512
1513/**
1514 * Worker for nemHCWinRunGC that stops the execution on the way out.
1515 *
1516 * The CPU was running the last time we checked, no there are no messages that
1517 * needs being marked handled/whatever. Caller checks this.
1518 *
1519 * @returns rcStrict on success, error status on failure.
1520 * @param pVM The cross context VM structure.
1521 * @param pVCpu The cross context per CPU structure.
1522 * @param rcStrict The nemHCWinRunGC return status. This is a little
1523 * bit unnecessary, except in internal error cases,
1524 * since we won't need to stop the CPU if we took an
1525 * exit.
1526 * @param pMappingHeader The message slot mapping.
1527 * @param pGVM The global (ring-0) VM structure (NULL in r3).
1528 * @param pGVCpu The global (ring-0) per CPU structure (NULL in r3).
1529 */
1530NEM_TMPL_STATIC VBOXSTRICTRC nemHCWinStopCpu(PVM pVM, PVMCPU pVCpu, VBOXSTRICTRC rcStrict,
1531 VID_MESSAGE_MAPPING_HEADER volatile *pMappingHeader,
1532 PGVM pGVM, PGVMCPU pGVCpu)
1533{
1534 /*
1535 * Try stopping the processor. If we're lucky we manage to do this before it
1536 * does another VM exit.
1537 */
1538# ifdef IN_RING0
1539 pVCpu->nem.s.uIoCtlBuf.idCpu = pGVCpu->idCpu;
1540 NTSTATUS rcNt = nemR0NtPerformIoControl(pGVM, pGVM->nem.s.IoCtlStopVirtualProcessor.uFunction,
1541 &pVCpu->nem.s.uIoCtlBuf.idCpu, sizeof(pVCpu->nem.s.uIoCtlBuf.idCpu),
1542 NULL, 0);
1543 if (NT_SUCCESS(rcNt))
1544 {
1545 Log8(("nemHCWinStopCpu: Stopping CPU succeeded (cpu status %u)\n", nemHCWinCpuGetRunningStatus(pVCpu) ));
1546 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatStopCpuSuccess);
1547 return rcStrict;
1548 }
1549# else
1550 BOOL fRet = VidStopVirtualProcessor(pVM->nem.s.hPartitionDevice, pVCpu->idCpu);
1551 if (fRet)
1552 {
1553 Log8(("nemHCWinStopCpu: Stopping CPU succeeded (cpu status %u)\n", nemHCWinCpuGetRunningStatus(pVCpu) ));
1554 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatStopCpuSuccess);
1555 return rcStrict;
1556 }
1557 RT_NOREF(pGVM, pGVCpu);
1558# endif
1559
1560 /*
1561 * Dang. The CPU stopped by itself and we got a couple of message to deal with.
1562 */
1563# ifdef IN_RING0
1564 AssertLogRelMsgReturn(rcNt == ERROR_VID_STOP_PENDING, ("rcNt=%#x\n", rcNt),
1565 RT_SUCCESS(rcStrict) ? VERR_INTERNAL_ERROR_3 : rcStrict);
1566# else
1567 DWORD dwErr = RTNtLastErrorValue();
1568 AssertLogRelMsgReturn(dwErr == ERROR_VID_STOP_PENDING, ("dwErr=%#u (%#x)\n", dwErr, dwErr),
1569 RT_SUCCESS(rcStrict) ? VERR_INTERNAL_ERROR_3 : rcStrict);
1570# endif
1571 Log8(("nemHCWinStopCpu: Stopping CPU pending...\n"));
1572 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatStopCpuPending);
1573
1574 /*
1575 * First message: Exit or similar.
1576 * Note! We can safely ASSUME that rcStrict isn't an important information one.
1577 */
1578# ifdef IN_RING0
1579 pVCpu->nem.s.uIoCtlBuf.MsgSlotHandleAndGetNext.iCpu = pGVCpu->idCpu;
1580 pVCpu->nem.s.uIoCtlBuf.MsgSlotHandleAndGetNext.fFlags = VID_MSHAGN_F_GET_NEXT_MESSAGE;
1581 pVCpu->nem.s.uIoCtlBuf.MsgSlotHandleAndGetNext.cMillies = 30000; /*ms*/
1582 rcNt = nemR0NtPerformIoControl(pGVM, pGVM->nem.s.IoCtlMessageSlotHandleAndGetNext.uFunction,
1583 &pVCpu->nem.s.uIoCtlBuf.MsgSlotHandleAndGetNext,
1584 sizeof(pVCpu->nem.s.uIoCtlBuf.MsgSlotHandleAndGetNext),
1585 NULL, 0);
1586 AssertLogRelMsgReturn(NT_SUCCESS(rcNt), ("1st VidMessageSlotHandleAndGetNext after ERROR_VID_STOP_PENDING failed: %#x\n", rcNt),
1587 RT_SUCCESS(rcStrict) ? VERR_INTERNAL_ERROR_3 : rcStrict);
1588# else
1589 BOOL fWait = g_pfnVidMessageSlotHandleAndGetNext(pVM->nem.s.hPartitionDevice, pVCpu->idCpu,
1590 VID_MSHAGN_F_GET_NEXT_MESSAGE, 30000 /*ms*/);
1591 AssertLogRelMsgReturn(fWait, ("1st VidMessageSlotHandleAndGetNext after ERROR_VID_STOP_PENDING failed: %u\n", RTNtLastErrorValue()),
1592 RT_SUCCESS(rcStrict) ? VERR_INTERNAL_ERROR_3 : rcStrict);
1593# endif
1594
1595 /* It should be a hypervisor message and definitely not a stop request completed message. */
1596 VID_MESSAGE_TYPE enmVidMsgType = pMappingHeader->enmVidMsgType;
1597 AssertLogRelMsgReturn(enmVidMsgType != VidMessageStopRequestComplete,
1598 ("Unexpected 1st message following ERROR_VID_STOP_PENDING: %#x LB %#x\n",
1599 enmVidMsgType, pMappingHeader->cbMessage),
1600 RT_SUCCESS(rcStrict) ? VERR_INTERNAL_ERROR_3 : rcStrict);
1601
1602 VBOXSTRICTRC rcStrict2 = nemHCWinHandleMessage(pVM, pVCpu, pMappingHeader, CPUMQueryGuestCtxPtr(pVCpu), pGVCpu);
1603 if (rcStrict2 != VINF_SUCCESS && RT_SUCCESS(rcStrict))
1604 rcStrict = rcStrict2;
1605
1606 /*
1607 * Mark it as handled and get the stop request completed message, then mark
1608 * that as handled too. CPU is back into fully stopped stated then.
1609 */
1610# ifdef IN_RING0
1611 pVCpu->nem.s.uIoCtlBuf.MsgSlotHandleAndGetNext.iCpu = pGVCpu->idCpu;
1612 pVCpu->nem.s.uIoCtlBuf.MsgSlotHandleAndGetNext.fFlags = VID_MSHAGN_F_HANDLE_MESSAGE | VID_MSHAGN_F_GET_NEXT_MESSAGE;
1613 pVCpu->nem.s.uIoCtlBuf.MsgSlotHandleAndGetNext.cMillies = 30000; /*ms*/
1614 rcNt = nemR0NtPerformIoControl(pGVM, pGVM->nem.s.IoCtlMessageSlotHandleAndGetNext.uFunction,
1615 &pVCpu->nem.s.uIoCtlBuf.MsgSlotHandleAndGetNext,
1616 sizeof(pVCpu->nem.s.uIoCtlBuf.MsgSlotHandleAndGetNext),
1617 NULL, 0);
1618 AssertLogRelMsgReturn(NT_SUCCESS(rcNt), ("2st VidMessageSlotHandleAndGetNext after ERROR_VID_STOP_PENDING failed: %#x\n", rcNt),
1619 RT_SUCCESS(rcStrict) ? VERR_INTERNAL_ERROR_3 : rcStrict);
1620# else
1621 fWait = g_pfnVidMessageSlotHandleAndGetNext(pVM->nem.s.hPartitionDevice, pVCpu->idCpu,
1622 VID_MSHAGN_F_HANDLE_MESSAGE | VID_MSHAGN_F_GET_NEXT_MESSAGE, 30000 /*ms*/);
1623 AssertLogRelMsgReturn(fWait, ("2nd VidMessageSlotHandleAndGetNext after ERROR_VID_STOP_PENDING failed: %u\n", RTNtLastErrorValue()),
1624 RT_SUCCESS(rcStrict) ? VERR_INTERNAL_ERROR_3 : rcStrict);
1625# endif
1626
1627 /* It should be a stop request completed message. */
1628 enmVidMsgType = pMappingHeader->enmVidMsgType;
1629 AssertLogRelMsgReturn(enmVidMsgType == VidMessageStopRequestComplete,
1630 ("Unexpected 2nd message following ERROR_VID_STOP_PENDING: %#x LB %#x\n",
1631 enmVidMsgType, pMappingHeader->cbMessage),
1632 RT_SUCCESS(rcStrict) ? VERR_INTERNAL_ERROR_3 : rcStrict);
1633
1634 /* Mark this as handled. */
1635# ifdef IN_RING0
1636 pVCpu->nem.s.uIoCtlBuf.MsgSlotHandleAndGetNext.iCpu = pGVCpu->idCpu;
1637 pVCpu->nem.s.uIoCtlBuf.MsgSlotHandleAndGetNext.fFlags = VID_MSHAGN_F_HANDLE_MESSAGE;
1638 pVCpu->nem.s.uIoCtlBuf.MsgSlotHandleAndGetNext.cMillies = 30000; /*ms*/
1639 rcNt = nemR0NtPerformIoControl(pGVM, pGVM->nem.s.IoCtlMessageSlotHandleAndGetNext.uFunction,
1640 &pVCpu->nem.s.uIoCtlBuf.MsgSlotHandleAndGetNext,
1641 sizeof(pVCpu->nem.s.uIoCtlBuf.MsgSlotHandleAndGetNext),
1642 NULL, 0);
1643 AssertLogRelMsgReturn(NT_SUCCESS(rcNt), ("3rd VidMessageSlotHandleAndGetNext after ERROR_VID_STOP_PENDING failed: %#x\n", rcNt),
1644 RT_SUCCESS(rcStrict) ? VERR_INTERNAL_ERROR_3 : rcStrict);
1645# else
1646 fWait = g_pfnVidMessageSlotHandleAndGetNext(pVM->nem.s.hPartitionDevice, pVCpu->idCpu, VID_MSHAGN_F_HANDLE_MESSAGE, 30000 /*ms*/);
1647 AssertLogRelMsgReturn(fWait, ("3rd VidMessageSlotHandleAndGetNext after ERROR_VID_STOP_PENDING failed: %u\n", RTNtLastErrorValue()),
1648 RT_SUCCESS(rcStrict) ? VERR_INTERNAL_ERROR_3 : rcStrict);
1649# endif
1650 Log8(("nemHCWinStopCpu: Stopped the CPU (rcStrict=%Rrc)\n", VBOXSTRICTRC_VAL(rcStrict) ));
1651 return rcStrict;
1652}
1653
1654
1655NEM_TMPL_STATIC VBOXSTRICTRC nemHCWinRunGC(PVM pVM, PVMCPU pVCpu, PGVM pGVM, PGVMCPU pGVCpu)
1656{
1657 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1658 LogFlow(("NEM/%u: %04x:%08RX64 efl=%#08RX64 <=\n", pVCpu->idCpu, pCtx->cs.Sel, pCtx->rip, pCtx->rflags));
1659# ifdef LOG_ENABLED
1660 if (LogIs3Enabled())
1661 nemHCWinLogState(pVM, pVCpu);
1662# endif
1663
1664 /*
1665 * Try switch to NEM runloop state.
1666 */
1667 if (VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC_NEM, VMCPUSTATE_STARTED))
1668 { /* likely */ }
1669 else
1670 {
1671 VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC_NEM, VMCPUSTATE_STARTED_EXEC_NEM_CANCELED);
1672 LogFlow(("NEM/%u: returning immediately because canceled\n", pVCpu->idCpu));
1673 return VINF_SUCCESS;
1674 }
1675
1676 /*
1677 * The run loop.
1678 *
1679 * Current approach to state updating to use the sledgehammer and sync
1680 * everything every time. This will be optimized later.
1681 */
1682 VID_MESSAGE_MAPPING_HEADER volatile *pMappingHeader = (VID_MESSAGE_MAPPING_HEADER volatile *)pVCpu->nem.s.pvMsgSlotMapping;
1683 uint32_t cMillies = 5000; /** @todo lower this later... */
1684 const bool fSingleStepping = false; /** @todo get this from somewhere. */
1685 VBOXSTRICTRC rcStrict = VINF_SUCCESS;
1686 for (unsigned iLoop = 0;;iLoop++)
1687 {
1688 /*
1689 * Ensure that hyper-V has the whole state.
1690 */
1691 if ((pCtx->fExtrn & (CPUMCTX_EXTRN_ALL | CPUMCTX_EXTRN_NEM_WIN_MASK)) != (CPUMCTX_EXTRN_ALL | CPUMCTX_EXTRN_NEM_WIN_MASK))
1692 {
1693# ifdef IN_RING0
1694 int rc2 = nemR0WinExportState(pGVM, pGVCpu, pCtx);
1695# else
1696 int rc2 = nemHCWinCopyStateToHyperV(pVM, pVCpu, pCtx);
1697 RT_NOREF(pGVM, pGVCpu);
1698# endif
1699 AssertRCReturn(rc2, rc2);
1700 }
1701
1702 /*
1703 * Run a bit.
1704 */
1705 if ( !VM_FF_IS_PENDING(pVM, VM_FF_EMT_RENDEZVOUS | VM_FF_TM_VIRTUAL_SYNC)
1706 && !VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
1707 {
1708 if (pVCpu->nem.s.fHandleAndGetFlags)
1709 { /* Very likely that the CPU does NOT need starting (pending msg, running). */ }
1710 else
1711 {
1712# ifdef IN_RING0
1713 pVCpu->nem.s.uIoCtlBuf.idCpu = pGVCpu->idCpu;
1714 NTSTATUS rcNt = nemR0NtPerformIoControl(pGVM, pGVM->nem.s.IoCtlStartVirtualProcessor.uFunction,
1715 &pVCpu->nem.s.uIoCtlBuf.idCpu, sizeof(pVCpu->nem.s.uIoCtlBuf.idCpu),
1716 NULL, 0);
1717 LogFlow(("NEM/%u: IoCtlStartVirtualProcessor -> %#x\n", pVCpu->idCpu, rcNt));
1718 AssertLogRelMsgReturn(NT_SUCCESS(rcNt), ("VidStartVirtualProcessor failed for CPU #%u: %#x\n", pGVCpu->idCpu, rcNt),
1719 VERR_INTERNAL_ERROR_3);
1720# else
1721 AssertLogRelMsgReturn(g_pfnVidStartVirtualProcessor(pVM->nem.s.hPartitionDevice, pVCpu->idCpu),
1722 ("VidStartVirtualProcessor failed for CPU #%u: %u (%#x, rcNt=%#x)\n",
1723 pVCpu->idCpu, RTNtLastErrorValue(), RTNtLastErrorValue(), RTNtLastStatusValue()),
1724 VERR_INTERNAL_ERROR_3);
1725# endif
1726 pVCpu->nem.s.fHandleAndGetFlags = VID_MSHAGN_F_GET_NEXT_MESSAGE;
1727 }
1728
1729 if (VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC_NEM_WAIT, VMCPUSTATE_STARTED_EXEC_NEM))
1730 {
1731# ifdef IN_RING0
1732 pVCpu->nem.s.uIoCtlBuf.MsgSlotHandleAndGetNext.iCpu = pGVCpu->idCpu;
1733 pVCpu->nem.s.uIoCtlBuf.MsgSlotHandleAndGetNext.fFlags = pVCpu->nem.s.fHandleAndGetFlags;
1734 pVCpu->nem.s.uIoCtlBuf.MsgSlotHandleAndGetNext.cMillies = cMillies;
1735 NTSTATUS rcNt = nemR0NtPerformIoControl(pGVM, pGVM->nem.s.IoCtlMessageSlotHandleAndGetNext.uFunction,
1736 &pVCpu->nem.s.uIoCtlBuf.MsgSlotHandleAndGetNext,
1737 sizeof(pVCpu->nem.s.uIoCtlBuf.MsgSlotHandleAndGetNext),
1738 NULL, 0);
1739 VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC_NEM, VMCPUSTATE_STARTED_EXEC_NEM_WAIT);
1740 if (rcNt == STATUS_SUCCESS)
1741# else
1742 BOOL fRet = VidMessageSlotHandleAndGetNext(pVM->nem.s.hPartitionDevice, pVCpu->idCpu,
1743 pVCpu->nem.s.fHandleAndGetFlags, cMillies);
1744 VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC_NEM, VMCPUSTATE_STARTED_EXEC_NEM_WAIT);
1745 if (fRet)
1746# endif
1747 {
1748 /*
1749 * Deal with the message.
1750 */
1751 rcStrict = nemHCWinHandleMessage(pVM, pVCpu, pMappingHeader, pCtx, pGVCpu);
1752 pVCpu->nem.s.fHandleAndGetFlags |= VID_MSHAGN_F_HANDLE_MESSAGE;
1753 if (rcStrict == VINF_SUCCESS)
1754 { /* hopefully likely */ }
1755 else
1756 {
1757 LogFlow(("NEM/%u: breaking: nemHCWinHandleMessage -> %Rrc\n", pVCpu->idCpu, VBOXSTRICTRC_VAL(rcStrict) ));
1758 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatBreakOnStatus);
1759 break;
1760 }
1761 }
1762 else
1763 {
1764 /* VID.SYS merges STATUS_ALERTED and STATUS_USER_APC into STATUS_TIMEOUT,
1765 so after NtAlertThread we end up here with a STATUS_TIMEOUT. And yeah,
1766 the error code conversion is into WAIT_XXX, i.e. NT status codes. */
1767# ifndef IN_RING0
1768 DWORD rcNt = GetLastError();
1769# endif
1770 LogFlow(("NEM/%u: VidMessageSlotHandleAndGetNext -> %#x\n", pVCpu->idCpu, rcNt));
1771 AssertLogRelMsgReturn( rcNt == STATUS_TIMEOUT
1772 || rcNt == STATUS_ALERTED /* just in case */
1773 || rcNt == STATUS_USER_APC /* ditto */
1774 , ("VidMessageSlotHandleAndGetNext failed for CPU #%u: %#x (%u)\n", pVCpu->idCpu, rcNt, rcNt),
1775 VERR_INTERNAL_ERROR_3);
1776 pVCpu->nem.s.fHandleAndGetFlags = VID_MSHAGN_F_GET_NEXT_MESSAGE;
1777 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatGetMsgTimeout);
1778 }
1779
1780 /*
1781 * If no relevant FFs are pending, loop.
1782 */
1783 if ( !VM_FF_IS_PENDING( pVM, !fSingleStepping ? VM_FF_HP_R0_PRE_HM_MASK : VM_FF_HP_R0_PRE_HM_STEP_MASK)
1784 && !VMCPU_FF_IS_PENDING(pVCpu, !fSingleStepping ? VMCPU_FF_HP_R0_PRE_HM_MASK : VMCPU_FF_HP_R0_PRE_HM_STEP_MASK) )
1785 continue;
1786
1787 /** @todo Try handle pending flags, not just return to EM loops. Take care
1788 * not to set important RCs here unless we've handled a message. */
1789 LogFlow(("NEM/%u: breaking: pending FF (%#x / %#x)\n",
1790 pVCpu->idCpu, pVM->fGlobalForcedActions, pVCpu->fLocalForcedActions));
1791 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatBreakOnFFPost);
1792 }
1793 else
1794 {
1795 LogFlow(("NEM/%u: breaking: canceled %d (pre exec)\n", pVCpu->idCpu, VMCPU_GET_STATE(pVCpu) ));
1796 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatBreakOnCancel);
1797 }
1798 }
1799 else
1800 {
1801 LogFlow(("NEM/%u: breaking: pending FF (pre exec)\n", pVCpu->idCpu));
1802 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatBreakOnFFPre);
1803 }
1804 break;
1805 } /* the run loop */
1806
1807
1808 /*
1809 * If the CPU is running, make sure to stop it before we try sync back the
1810 * state and return to EM.
1811 */
1812 if (pVCpu->nem.s.fHandleAndGetFlags == VID_MSHAGN_F_GET_NEXT_MESSAGE)
1813 {
1814 pVCpu->nem.s.fHandleAndGetFlags = 0;
1815 rcStrict = nemHCWinStopCpu(pVM, pVCpu, rcStrict, pMappingHeader, pGVM, pGVCpu);
1816 }
1817
1818 if (!VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED, VMCPUSTATE_STARTED_EXEC_NEM))
1819 VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED, VMCPUSTATE_STARTED_EXEC_NEM_CANCELED);
1820
1821 if (pCtx->fExtrn & (CPUMCTX_EXTRN_ALL | (CPUMCTX_EXTRN_NEM_WIN_MASK & ~CPUMCTX_EXTRN_NEM_WIN_EVENT_INJECT)))
1822 {
1823# ifdef IN_RING0
1824 int rc2 = nemR0WinImportState(pGVM, pGVCpu, pCtx, CPUMCTX_EXTRN_ALL | CPUMCTX_EXTRN_NEM_WIN_MASK);
1825 if (RT_SUCCESS(rc2))
1826 pCtx->fExtrn = 0;
1827 else if (rc2 == VERR_NEM_CHANGE_PGM_MODE || rc2 == VERR_NEM_FLUSH_TLB)
1828 {
1829 pCtx->fExtrn = 0;
1830 if (rcStrict == VINF_SUCCESS || rcStrict == -rc2)
1831 rcStrict = -rc2;
1832 else
1833 {
1834 pVCpu->nem.s.rcPgmPending = -rc2;
1835 LogFlow(("NEM/%u: rcPgmPending=%Rrc (rcStrict=%Rrc)\n", pVCpu->idCpu, rc2, VBOXSTRICTRC_VAL(rcStrict) ));
1836 }
1837 }
1838# else
1839 int rc2 = nemHCWinCopyStateFromHyperV(pVM, pVCpu, pCtx, CPUMCTX_EXTRN_ALL | CPUMCTX_EXTRN_NEM_WIN_MASK);
1840 if (RT_SUCCESS(rc2))
1841 pCtx->fExtrn = 0;
1842# endif
1843 else if (RT_SUCCESS(rcStrict))
1844 rcStrict = rc2;
1845 }
1846 else
1847 pCtx->fExtrn = 0;
1848
1849 LogFlow(("NEM/%u: %04x:%08RX64 efl=%#08RX64 => %Rrc\n",
1850 pVCpu->idCpu, pCtx->cs.Sel, pCtx->rip, pCtx->rflags, VBOXSTRICTRC_VAL(rcStrict) ));
1851 return rcStrict;
1852}
1853
1854#endif /* NEM_WIN_USE_OUR_OWN_RUN_API */
1855
1856
1857/**
1858 * @callback_method_impl{FNPGMPHYSNEMCHECKPAGE}
1859 */
1860NEM_TMPL_STATIC DECLCALLBACK(int) nemHCWinUnsetForA20CheckerCallback(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys,
1861 PPGMPHYSNEMPAGEINFO pInfo, void *pvUser)
1862{
1863 /* We'll just unmap the memory. */
1864 if (pInfo->u2NemState > NEM_WIN_PAGE_STATE_UNMAPPED)
1865 {
1866#ifdef NEM_WIN_USE_HYPERCALLS_FOR_PAGES
1867 int rc = nemHCWinHypercallUnmapPage(pVM, pVCpu, GCPhys);
1868 AssertRC(rc);
1869 if (RT_SUCCESS(rc))
1870#else
1871 HRESULT hrc = WHvUnmapGpaRange(pVM->nem.s.hPartition, GCPhys, X86_PAGE_SIZE);
1872 if (SUCCEEDED(hrc))
1873#endif
1874 {
1875 uint32_t cMappedPages = ASMAtomicDecU32(&pVM->nem.s.cMappedPages); NOREF(cMappedPages);
1876 Log5(("NEM GPA unmapped/A20: %RGp (was %s, cMappedPages=%u)\n", GCPhys, g_apszPageStates[pInfo->u2NemState], cMappedPages));
1877 pInfo->u2NemState = NEM_WIN_PAGE_STATE_UNMAPPED;
1878 }
1879 else
1880 {
1881#ifdef NEM_WIN_USE_HYPERCALLS_FOR_PAGES
1882 LogRel(("nemHCWinUnsetForA20CheckerCallback/unmap: GCPhys=%RGp rc=%Rrc\n", GCPhys, rc));
1883 return rc;
1884#else
1885 LogRel(("nemHCWinUnsetForA20CheckerCallback/unmap: GCPhys=%RGp hrc=%Rhrc (%#x) Last=%#x/%u\n",
1886 GCPhys, hrc, hrc, RTNtLastStatusValue(), RTNtLastErrorValue()));
1887 return VERR_INTERNAL_ERROR_2;
1888#endif
1889 }
1890 }
1891 RT_NOREF(pVCpu, pvUser);
1892 return VINF_SUCCESS;
1893}
1894
1895
1896/**
1897 * Unmaps a page from Hyper-V for the purpose of emulating A20 gate behavior.
1898 *
1899 * @returns The PGMPhysNemQueryPageInfo result.
1900 * @param pVM The cross context VM structure.
1901 * @param pVCpu The cross context virtual CPU structure.
1902 * @param GCPhys The page to unmap.
1903 */
1904NEM_TMPL_STATIC int nemHCWinUnmapPageForA20Gate(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys)
1905{
1906 PGMPHYSNEMPAGEINFO Info;
1907 return PGMPhysNemPageInfoChecker(pVM, pVCpu, GCPhys, false /*fMakeWritable*/, &Info,
1908 nemHCWinUnsetForA20CheckerCallback, NULL);
1909}
1910
1911
1912void nemHCNativeNotifyHandlerPhysicalRegister(PVM pVM, PGMPHYSHANDLERKIND enmKind, RTGCPHYS GCPhys, RTGCPHYS cb)
1913{
1914 Log5(("nemHCNativeNotifyHandlerPhysicalRegister: %RGp LB %RGp enmKind=%d\n", GCPhys, cb, enmKind));
1915 NOREF(pVM); NOREF(enmKind); NOREF(GCPhys); NOREF(cb);
1916}
1917
1918
1919void nemHCNativeNotifyHandlerPhysicalDeregister(PVM pVM, PGMPHYSHANDLERKIND enmKind, RTGCPHYS GCPhys, RTGCPHYS cb,
1920 int fRestoreAsRAM, bool fRestoreAsRAM2)
1921{
1922 Log5(("nemHCNativeNotifyHandlerPhysicalDeregister: %RGp LB %RGp enmKind=%d fRestoreAsRAM=%d fRestoreAsRAM2=%d\n",
1923 GCPhys, cb, enmKind, fRestoreAsRAM, fRestoreAsRAM2));
1924 NOREF(pVM); NOREF(enmKind); NOREF(GCPhys); NOREF(cb); NOREF(fRestoreAsRAM); NOREF(fRestoreAsRAM2);
1925}
1926
1927
1928void nemHCNativeNotifyHandlerPhysicalModify(PVM pVM, PGMPHYSHANDLERKIND enmKind, RTGCPHYS GCPhysOld,
1929 RTGCPHYS GCPhysNew, RTGCPHYS cb, bool fRestoreAsRAM)
1930{
1931 Log5(("nemHCNativeNotifyHandlerPhysicalModify: %RGp LB %RGp -> %RGp enmKind=%d fRestoreAsRAM=%d\n",
1932 GCPhysOld, cb, GCPhysNew, enmKind, fRestoreAsRAM));
1933 NOREF(pVM); NOREF(enmKind); NOREF(GCPhysOld); NOREF(GCPhysNew); NOREF(cb); NOREF(fRestoreAsRAM);
1934}
1935
1936
1937/**
1938 * Worker that maps pages into Hyper-V.
1939 *
1940 * This is used by the PGM physical page notifications as well as the memory
1941 * access VMEXIT handlers.
1942 *
1943 * @returns VBox status code.
1944 * @param pVM The cross context VM structure.
1945 * @param pVCpu The cross context virtual CPU structure of the
1946 * calling EMT.
1947 * @param GCPhysSrc The source page address.
1948 * @param GCPhysDst The hyper-V destination page. This may differ from
1949 * GCPhysSrc when A20 is disabled.
1950 * @param fPageProt NEM_PAGE_PROT_XXX.
1951 * @param pu2State Our page state (input/output).
1952 * @param fBackingChanged Set if the page backing is being changed.
1953 * @thread EMT(pVCpu)
1954 */
1955NEM_TMPL_STATIC int nemHCNativeSetPhysPage(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhysSrc, RTGCPHYS GCPhysDst,
1956 uint32_t fPageProt, uint8_t *pu2State, bool fBackingChanged)
1957{
1958#ifdef NEM_WIN_USE_HYPERCALLS_FOR_PAGES
1959 /*
1960 * When using the hypercalls instead of the ring-3 APIs, we don't need to
1961 * unmap memory before modifying it. We still want to track the state though,
1962 * since unmap will fail when called an unmapped page and we don't want to redo
1963 * upgrades/downgrades.
1964 */
1965 uint8_t const u2OldState = *pu2State;
1966 int rc;
1967 if (fPageProt == NEM_PAGE_PROT_NONE)
1968 {
1969 if (u2OldState > NEM_WIN_PAGE_STATE_UNMAPPED)
1970 {
1971 rc = nemHCWinHypercallUnmapPage(pVM, pVCpu, GCPhysDst);
1972 if (RT_SUCCESS(rc))
1973 {
1974 *pu2State = NEM_WIN_PAGE_STATE_UNMAPPED;
1975 uint32_t cMappedPages = ASMAtomicDecU32(&pVM->nem.s.cMappedPages); NOREF(cMappedPages);
1976 Log5(("NEM GPA unmapped/set: %RGp (was %s, cMappedPages=%u)\n", GCPhysDst, g_apszPageStates[u2OldState], cMappedPages));
1977 }
1978 else
1979 AssertLogRelMsgFailed(("nemHCNativeSetPhysPage/unmap: GCPhysDst=%RGp rc=%Rrc\n", GCPhysDst, rc));
1980 }
1981 else
1982 rc = VINF_SUCCESS;
1983 }
1984 else if (fPageProt & NEM_PAGE_PROT_WRITE)
1985 {
1986 if (u2OldState != NEM_WIN_PAGE_STATE_WRITABLE || fBackingChanged)
1987 {
1988 rc = nemHCWinHypercallMapPage(pVM, pVCpu, GCPhysSrc, GCPhysDst,
1989 HV_MAP_GPA_READABLE | HV_MAP_GPA_WRITABLE
1990 | HV_MAP_GPA_EXECUTABLE | HV_MAP_GPA_EXECUTABLE_AGAIN);
1991 if (RT_SUCCESS(rc))
1992 {
1993 *pu2State = NEM_WIN_PAGE_STATE_WRITABLE;
1994 uint32_t cMappedPages = u2OldState <= NEM_WIN_PAGE_STATE_UNMAPPED
1995 ? ASMAtomicIncU32(&pVM->nem.s.cMappedPages) : pVM->nem.s.cMappedPages;
1996 Log5(("NEM GPA writable/set: %RGp (was %s, cMappedPages=%u)\n", GCPhysDst, g_apszPageStates[u2OldState], cMappedPages));
1997 NOREF(cMappedPages);
1998 }
1999 else
2000 AssertLogRelMsgFailed(("nemHCNativeSetPhysPage/writable: GCPhysDst=%RGp rc=%Rrc\n", GCPhysDst, rc));
2001 }
2002 else
2003 rc = VINF_SUCCESS;
2004 }
2005 else
2006 {
2007 if (u2OldState != NEM_WIN_PAGE_STATE_READABLE || fBackingChanged)
2008 {
2009 rc = nemHCWinHypercallMapPage(pVM, pVCpu, GCPhysSrc, GCPhysDst,
2010 HV_MAP_GPA_READABLE | HV_MAP_GPA_EXECUTABLE | HV_MAP_GPA_EXECUTABLE_AGAIN);
2011 if (RT_SUCCESS(rc))
2012 {
2013 *pu2State = NEM_WIN_PAGE_STATE_READABLE;
2014 uint32_t cMappedPages = u2OldState <= NEM_WIN_PAGE_STATE_UNMAPPED
2015 ? ASMAtomicIncU32(&pVM->nem.s.cMappedPages) : pVM->nem.s.cMappedPages;
2016 Log5(("NEM GPA read+exec/set: %RGp (was %s, cMappedPages=%u)\n", GCPhysDst, g_apszPageStates[u2OldState], cMappedPages));
2017 NOREF(cMappedPages);
2018 }
2019 else
2020 AssertLogRelMsgFailed(("nemHCNativeSetPhysPage/writable: GCPhysDst=%RGp rc=%Rrc\n", GCPhysDst, rc));
2021 }
2022 else
2023 rc = VINF_SUCCESS;
2024 }
2025
2026 return VINF_SUCCESS;
2027
2028#else
2029 /*
2030 * Looks like we need to unmap a page before we can change the backing
2031 * or even modify the protection. This is going to be *REALLY* efficient.
2032 * PGM lends us two bits to keep track of the state here.
2033 */
2034 uint8_t const u2OldState = *pu2State;
2035 uint8_t const u2NewState = fPageProt & NEM_PAGE_PROT_WRITE ? NEM_WIN_PAGE_STATE_WRITABLE
2036 : fPageProt & NEM_PAGE_PROT_READ ? NEM_WIN_PAGE_STATE_READABLE : NEM_WIN_PAGE_STATE_UNMAPPED;
2037 if ( fBackingChanged
2038 || u2NewState != u2OldState)
2039 {
2040 if (u2OldState > NEM_WIN_PAGE_STATE_UNMAPPED)
2041 {
2042# ifdef NEM_WIN_USE_HYPERCALLS_FOR_PAGES
2043 int rc = nemHCWinHypercallUnmapPage(pVM, pVCpu, GCPhysDst);
2044 AssertRC(rc);
2045 if (RT_SUCCESS(rc))
2046 {
2047 *pu2State = NEM_WIN_PAGE_STATE_UNMAPPED;
2048 uint32_t cMappedPages = ASMAtomicDecU32(&pVM->nem.s.cMappedPages); NOREF(cMappedPages);
2049 if (u2NewState == NEM_WIN_PAGE_STATE_UNMAPPED)
2050 {
2051 Log5(("NEM GPA unmapped/set: %RGp (was %s, cMappedPages=%u)\n",
2052 GCPhysDst, g_apszPageStates[u2OldState], cMappedPages));
2053 return VINF_SUCCESS;
2054 }
2055 }
2056 else
2057 {
2058 LogRel(("nemHCNativeSetPhysPage/unmap: GCPhysDst=%RGp rc=%Rrc\n", GCPhysDst, rc));
2059 return rc;
2060 }
2061# else
2062 HRESULT hrc = WHvUnmapGpaRange(pVM->nem.s.hPartition, GCPhysDst, X86_PAGE_SIZE);
2063 if (SUCCEEDED(hrc))
2064 {
2065 *pu2State = NEM_WIN_PAGE_STATE_UNMAPPED;
2066 uint32_t cMappedPages = ASMAtomicDecU32(&pVM->nem.s.cMappedPages); NOREF(cMappedPages);
2067 if (u2NewState == NEM_WIN_PAGE_STATE_UNMAPPED)
2068 {
2069 Log5(("NEM GPA unmapped/set: %RGp (was %s, cMappedPages=%u)\n",
2070 GCPhysDst, g_apszPageStates[u2OldState], cMappedPages));
2071 return VINF_SUCCESS;
2072 }
2073 }
2074 else
2075 {
2076 LogRel(("nemHCNativeSetPhysPage/unmap: GCPhysDst=%RGp hrc=%Rhrc (%#x) Last=%#x/%u\n",
2077 GCPhysDst, hrc, hrc, RTNtLastStatusValue(), RTNtLastErrorValue()));
2078 return VERR_NEM_INIT_FAILED;
2079 }
2080# endif
2081 }
2082 }
2083
2084 /*
2085 * Writeable mapping?
2086 */
2087 if (fPageProt & NEM_PAGE_PROT_WRITE)
2088 {
2089# ifdef NEM_WIN_USE_HYPERCALLS_FOR_PAGES
2090 int rc = nemHCWinHypercallMapPage(pVM, pVCpu, GCPhysSrc, GCPhysDst,
2091 HV_MAP_GPA_READABLE | HV_MAP_GPA_WRITABLE
2092 | HV_MAP_GPA_EXECUTABLE | HV_MAP_GPA_EXECUTABLE_AGAIN);
2093 AssertRC(rc);
2094 if (RT_SUCCESS(rc))
2095 {
2096 *pu2State = NEM_WIN_PAGE_STATE_WRITABLE;
2097 uint32_t cMappedPages = ASMAtomicIncU32(&pVM->nem.s.cMappedPages); NOREF(cMappedPages);
2098 Log5(("NEM GPA mapped/set: %RGp %s (was %s, cMappedPages=%u)\n",
2099 GCPhysDst, g_apszPageStates[u2NewState], g_apszPageStates[u2OldState], cMappedPages));
2100 return VINF_SUCCESS;
2101 }
2102 LogRel(("nemHCNativeSetPhysPage/writable: GCPhysDst=%RGp rc=%Rrc\n", GCPhysDst, rc));
2103 return rc;
2104# else
2105 void *pvPage;
2106 int rc = nemR3NativeGCPhys2R3PtrWriteable(pVM, GCPhysSrc, &pvPage);
2107 if (RT_SUCCESS(rc))
2108 {
2109 HRESULT hrc = WHvMapGpaRange(pVM->nem.s.hPartition, pvPage, GCPhysDst, X86_PAGE_SIZE,
2110 WHvMapGpaRangeFlagRead | WHvMapGpaRangeFlagExecute | WHvMapGpaRangeFlagWrite);
2111 if (SUCCEEDED(hrc))
2112 {
2113 *pu2State = NEM_WIN_PAGE_STATE_WRITABLE;
2114 uint32_t cMappedPages = ASMAtomicIncU32(&pVM->nem.s.cMappedPages); NOREF(cMappedPages);
2115 Log5(("NEM GPA mapped/set: %RGp %s (was %s, cMappedPages=%u)\n",
2116 GCPhysDst, g_apszPageStates[u2NewState], g_apszPageStates[u2OldState], cMappedPages));
2117 return VINF_SUCCESS;
2118 }
2119 LogRel(("nemHCNativeSetPhysPage/writable: GCPhysDst=%RGp hrc=%Rhrc (%#x) Last=%#x/%u\n",
2120 GCPhysDst, hrc, hrc, RTNtLastStatusValue(), RTNtLastErrorValue()));
2121 return VERR_NEM_INIT_FAILED;
2122 }
2123 LogRel(("nemHCNativeSetPhysPage/writable: GCPhysSrc=%RGp rc=%Rrc\n", GCPhysSrc, rc));
2124 return rc;
2125# endif
2126 }
2127
2128 if (fPageProt & NEM_PAGE_PROT_READ)
2129 {
2130# ifdef NEM_WIN_USE_HYPERCALLS_FOR_PAGES
2131 int rc = nemHCWinHypercallMapPage(pVM, pVCpu, GCPhysSrc, GCPhysDst,
2132 HV_MAP_GPA_READABLE | HV_MAP_GPA_EXECUTABLE | HV_MAP_GPA_EXECUTABLE_AGAIN);
2133 AssertRC(rc);
2134 if (RT_SUCCESS(rc))
2135 {
2136 *pu2State = NEM_WIN_PAGE_STATE_READABLE;
2137 uint32_t cMappedPages = ASMAtomicIncU32(&pVM->nem.s.cMappedPages); NOREF(cMappedPages);
2138 Log5(("NEM GPA mapped/set: %RGp %s (was %s, cMappedPages=%u)\n",
2139 GCPhysDst, g_apszPageStates[u2NewState], g_apszPageStates[u2OldState], cMappedPages));
2140 return VINF_SUCCESS;
2141 }
2142 LogRel(("nemHCNativeSetPhysPage/readonly: GCPhysDst=%RGp rc=%Rrc\n", GCPhysDst, rc));
2143 return rc;
2144# else
2145 const void *pvPage;
2146 int rc = nemR3NativeGCPhys2R3PtrReadOnly(pVM, GCPhysSrc, &pvPage);
2147 if (RT_SUCCESS(rc))
2148 {
2149 HRESULT hrc = WHvMapGpaRange(pVM->nem.s.hPartition, (void *)pvPage, GCPhysDst, X86_PAGE_SIZE,
2150 WHvMapGpaRangeFlagRead | WHvMapGpaRangeFlagExecute);
2151 if (SUCCEEDED(hrc))
2152 {
2153 *pu2State = NEM_WIN_PAGE_STATE_READABLE;
2154 uint32_t cMappedPages = ASMAtomicIncU32(&pVM->nem.s.cMappedPages); NOREF(cMappedPages);
2155 Log5(("NEM GPA mapped/set: %RGp %s (was %s, cMappedPages=%u)\n",
2156 GCPhysDst, g_apszPageStates[u2NewState], g_apszPageStates[u2OldState], cMappedPages));
2157 return VINF_SUCCESS;
2158 }
2159 LogRel(("nemHCNativeSetPhysPage/readonly: GCPhysDst=%RGp hrc=%Rhrc (%#x) Last=%#x/%u\n",
2160 GCPhysDst, hrc, hrc, RTNtLastStatusValue(), RTNtLastErrorValue()));
2161 return VERR_NEM_INIT_FAILED;
2162 }
2163 LogRel(("nemHCNativeSetPhysPage/readonly: GCPhysSrc=%RGp rc=%Rrc\n", GCPhysSrc, rc));
2164 return rc;
2165# endif
2166 }
2167
2168 /* We already unmapped it above. */
2169 *pu2State = NEM_WIN_PAGE_STATE_UNMAPPED;
2170 return VINF_SUCCESS;
2171#endif /* !NEM_WIN_USE_HYPERCALLS_FOR_PAGES */
2172}
2173
2174
2175NEM_TMPL_STATIC int nemHCJustUnmapPageFromHyperV(PVM pVM, RTGCPHYS GCPhysDst, uint8_t *pu2State)
2176{
2177 if (*pu2State <= NEM_WIN_PAGE_STATE_UNMAPPED)
2178 {
2179 Log5(("nemHCJustUnmapPageFromHyperV: %RGp == unmapped\n", GCPhysDst));
2180 *pu2State = NEM_WIN_PAGE_STATE_UNMAPPED;
2181 return VINF_SUCCESS;
2182 }
2183
2184#if defined(NEM_WIN_USE_HYPERCALLS_FOR_PAGES) || defined(IN_RING0)
2185 PVMCPU pVCpu = VMMGetCpu(pVM);
2186 int rc = nemHCWinHypercallUnmapPage(pVM, pVCpu, GCPhysDst);
2187 AssertRC(rc);
2188 if (RT_SUCCESS(rc))
2189 {
2190 uint32_t cMappedPages = ASMAtomicDecU32(&pVM->nem.s.cMappedPages); NOREF(cMappedPages);
2191 Log5(("NEM GPA unmapped/just: %RGp (was %s, cMappedPages=%u)\n", GCPhysDst, g_apszPageStates[*pu2State], cMappedPages));
2192 *pu2State = NEM_WIN_PAGE_STATE_UNMAPPED;
2193 return VINF_SUCCESS;
2194 }
2195 LogRel(("nemHCJustUnmapPageFromHyperV/unmap: GCPhysDst=%RGp rc=%Rrc\n", GCPhysDst, rc));
2196 return rc;
2197#else
2198 HRESULT hrc = WHvUnmapGpaRange(pVM->nem.s.hPartition, GCPhysDst & ~(RTGCPHYS)X86_PAGE_OFFSET_MASK, X86_PAGE_SIZE);
2199 if (SUCCEEDED(hrc))
2200 {
2201 uint32_t cMappedPages = ASMAtomicDecU32(&pVM->nem.s.cMappedPages); NOREF(cMappedPages);
2202 *pu2State = NEM_WIN_PAGE_STATE_UNMAPPED;
2203 Log5(("nemHCJustUnmapPageFromHyperV: %RGp => unmapped (total %u)\n", GCPhysDst, cMappedPages));
2204 return VINF_SUCCESS;
2205 }
2206 LogRel(("nemHCJustUnmapPageFromHyperV(%RGp): failed! hrc=%Rhrc (%#x) Last=%#x/%u\n",
2207 GCPhysDst, hrc, hrc, RTNtLastStatusValue(), RTNtLastErrorValue()));
2208 return VERR_INTERNAL_ERROR_3;
2209#endif
2210}
2211
2212
2213int nemHCNativeNotifyPhysPageAllocated(PVM pVM, RTGCPHYS GCPhys, RTHCPHYS HCPhys, uint32_t fPageProt,
2214 PGMPAGETYPE enmType, uint8_t *pu2State)
2215{
2216 Log5(("nemHCNativeNotifyPhysPageAllocated: %RGp HCPhys=%RHp fPageProt=%#x enmType=%d *pu2State=%d\n",
2217 GCPhys, HCPhys, fPageProt, enmType, *pu2State));
2218 RT_NOREF_PV(HCPhys); RT_NOREF_PV(enmType);
2219
2220 int rc;
2221#if defined(NEM_WIN_USE_HYPERCALLS_FOR_PAGES) || defined(IN_RING0)
2222 PVMCPU pVCpu = VMMGetCpu(pVM);
2223 if ( pVM->nem.s.fA20Enabled
2224 || !NEM_WIN_IS_RELEVANT_TO_A20(GCPhys))
2225 rc = nemHCNativeSetPhysPage(pVM, pVCpu, GCPhys, GCPhys, fPageProt, pu2State, true /*fBackingChanged*/);
2226 else
2227 {
2228 /* To keep effort at a minimum, we unmap the HMA page alias and resync it lazily when needed. */
2229 rc = nemHCWinUnmapPageForA20Gate(pVM, pVCpu, GCPhys | RT_BIT_32(20));
2230 if (!NEM_WIN_IS_SUBJECT_TO_A20(GCPhys) && RT_SUCCESS(rc))
2231 rc = nemHCNativeSetPhysPage(pVM, pVCpu, GCPhys, GCPhys, fPageProt, pu2State, true /*fBackingChanged*/);
2232
2233 }
2234#else
2235 RT_NOREF_PV(fPageProt);
2236 if ( pVM->nem.s.fA20Enabled
2237 || !NEM_WIN_IS_RELEVANT_TO_A20(GCPhys))
2238 rc = nemR3JustUnmapPageFromHyperV(pVM, GCPhys, pu2State);
2239 else if (!NEM_WIN_IS_SUBJECT_TO_A20(GCPhys))
2240 rc = nemR3JustUnmapPageFromHyperV(pVM, GCPhys, pu2State);
2241 else
2242 rc = VINF_SUCCESS; /* ignore since we've got the alias page at this address. */
2243#endif
2244 return rc;
2245}
2246
2247
2248void nemHCNativeNotifyPhysPageProtChanged(PVM pVM, RTGCPHYS GCPhys, RTHCPHYS HCPhys, uint32_t fPageProt,
2249 PGMPAGETYPE enmType, uint8_t *pu2State)
2250{
2251 Log5(("nemHCNativeNotifyPhysPageProtChanged: %RGp HCPhys=%RHp fPageProt=%#x enmType=%d *pu2State=%d\n",
2252 GCPhys, HCPhys, fPageProt, enmType, *pu2State));
2253 RT_NOREF_PV(HCPhys); RT_NOREF_PV(enmType);
2254
2255#if defined(NEM_WIN_USE_HYPERCALLS_FOR_PAGES) || defined(IN_RING0)
2256 PVMCPU pVCpu = VMMGetCpu(pVM);
2257 if ( pVM->nem.s.fA20Enabled
2258 || !NEM_WIN_IS_RELEVANT_TO_A20(GCPhys))
2259 nemHCNativeSetPhysPage(pVM, pVCpu, GCPhys, GCPhys, fPageProt, pu2State, false /*fBackingChanged*/);
2260 else
2261 {
2262 /* To keep effort at a minimum, we unmap the HMA page alias and resync it lazily when needed. */
2263 nemHCWinUnmapPageForA20Gate(pVM, pVCpu, GCPhys | RT_BIT_32(20));
2264 if (!NEM_WIN_IS_SUBJECT_TO_A20(GCPhys))
2265 nemHCNativeSetPhysPage(pVM, pVCpu, GCPhys, GCPhys, fPageProt, pu2State, false /*fBackingChanged*/);
2266 }
2267#else
2268 RT_NOREF_PV(fPageProt);
2269 if ( pVM->nem.s.fA20Enabled
2270 || !NEM_WIN_IS_RELEVANT_TO_A20(GCPhys))
2271 nemR3JustUnmapPageFromHyperV(pVM, GCPhys, pu2State);
2272 else if (!NEM_WIN_IS_SUBJECT_TO_A20(GCPhys))
2273 nemR3JustUnmapPageFromHyperV(pVM, GCPhys, pu2State);
2274 /* else: ignore since we've got the alias page at this address. */
2275#endif
2276}
2277
2278
2279void nemHCNativeNotifyPhysPageChanged(PVM pVM, RTGCPHYS GCPhys, RTHCPHYS HCPhysPrev, RTHCPHYS HCPhysNew,
2280 uint32_t fPageProt, PGMPAGETYPE enmType, uint8_t *pu2State)
2281{
2282 Log5(("nemHCNativeNotifyPhysPageChanged: %RGp HCPhys=%RHp->%RHp fPageProt=%#x enmType=%d *pu2State=%d\n",
2283 GCPhys, HCPhysPrev, HCPhysNew, fPageProt, enmType, *pu2State));
2284 RT_NOREF_PV(HCPhysPrev); RT_NOREF_PV(HCPhysNew); RT_NOREF_PV(enmType);
2285
2286#if defined(NEM_WIN_USE_HYPERCALLS_FOR_PAGES) || defined(IN_RING0)
2287 PVMCPU pVCpu = VMMGetCpu(pVM);
2288 if ( pVM->nem.s.fA20Enabled
2289 || !NEM_WIN_IS_RELEVANT_TO_A20(GCPhys))
2290 nemHCNativeSetPhysPage(pVM, pVCpu, GCPhys, GCPhys, fPageProt, pu2State, true /*fBackingChanged*/);
2291 else
2292 {
2293 /* To keep effort at a minimum, we unmap the HMA page alias and resync it lazily when needed. */
2294 nemHCWinUnmapPageForA20Gate(pVM, pVCpu, GCPhys | RT_BIT_32(20));
2295 if (!NEM_WIN_IS_SUBJECT_TO_A20(GCPhys))
2296 nemHCNativeSetPhysPage(pVM, pVCpu, GCPhys, GCPhys, fPageProt, pu2State, true /*fBackingChanged*/);
2297 }
2298#else
2299 RT_NOREF_PV(fPageProt);
2300 if ( pVM->nem.s.fA20Enabled
2301 || !NEM_WIN_IS_RELEVANT_TO_A20(GCPhys))
2302 nemR3JustUnmapPageFromHyperV(pVM, GCPhys, pu2State);
2303 else if (!NEM_WIN_IS_SUBJECT_TO_A20(GCPhys))
2304 nemR3JustUnmapPageFromHyperV(pVM, GCPhys, pu2State);
2305 /* else: ignore since we've got the alias page at this address. */
2306#endif
2307}
2308
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