VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/NEMAllNativeTemplate-win.cpp.h@ 72343

Last change on this file since 72343 was 72308, checked in by vboxsync, 7 years ago

NEM/win: Count cpuid and msr exits.
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1/* $Id: NEMAllNativeTemplate-win.cpp.h 72308 2018-05-23 17:53:43Z vboxsync $ */
2/** @file
3 * NEM - Native execution manager, Windows code template ring-0/3.
4 */
5
6/*
7 * Copyright (C) 2018 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Defined Constants And Macros *
21*********************************************************************************************************************************/
22/** Copy back a segment from hyper-V. */
23#define NEM_WIN_COPY_BACK_SEG(a_Dst, a_Src) \
24 do { \
25 (a_Dst).u64Base = (a_Src).Base; \
26 (a_Dst).u32Limit = (a_Src).Limit; \
27 (a_Dst).ValidSel = (a_Dst).Sel = (a_Src).Selector; \
28 (a_Dst).Attr.u = (a_Src).Attributes; \
29 (a_Dst).fFlags = CPUMSELREG_FLAGS_VALID; \
30 } while (0)
31
32
33/*********************************************************************************************************************************
34* Global Variables *
35*********************************************************************************************************************************/
36/** NEM_WIN_PAGE_STATE_XXX names. */
37NEM_TMPL_STATIC const char * const g_apszPageStates[4] = { "not-set", "unmapped", "readable", "writable" };
38
39/** HV_INTERCEPT_ACCESS_TYPE names. */
40static const char * const g_apszHvInterceptAccessTypes[4] = { "read", "write", "exec", "!undefined!" };
41
42
43/*********************************************************************************************************************************
44* Internal Functions *
45*********************************************************************************************************************************/
46NEM_TMPL_STATIC int nemHCNativeSetPhysPage(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhysSrc, RTGCPHYS GCPhysDst,
47 uint32_t fPageProt, uint8_t *pu2State, bool fBackingChanged);
48
49
50#ifdef NEM_WIN_USE_HYPERCALLS_FOR_PAGES
51
52/**
53 * Wrapper around VMMR0_DO_NEM_MAP_PAGES for a single page.
54 *
55 * @returns VBox status code.
56 * @param pVM The cross context VM structure.
57 * @param pVCpu The cross context virtual CPU structure of the caller.
58 * @param GCPhysSrc The source page. Does not need to be page aligned.
59 * @param GCPhysDst The destination page. Same as @a GCPhysSrc except for
60 * when A20 is disabled.
61 * @param fFlags HV_MAP_GPA_XXX.
62 */
63DECLINLINE(int) nemHCWinHypercallMapPage(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhysSrc, RTGCPHYS GCPhysDst, uint32_t fFlags)
64{
65#ifdef IN_RING0
66 /** @todo optimize further, caller generally has the physical address. */
67 PGVM pGVM = GVMMR0FastGetGVMByVM(pVM);
68 AssertReturn(pGVM, VERR_INVALID_VM_HANDLE);
69 return nemR0WinMapPages(pGVM, pVM, &pGVM->aCpus[pVCpu->idCpu],
70 GCPhysSrc & ~(RTGCPHYS)X86_PAGE_OFFSET_MASK,
71 GCPhysDst & ~(RTGCPHYS)X86_PAGE_OFFSET_MASK,
72 1, fFlags);
73#else
74 pVCpu->nem.s.Hypercall.MapPages.GCPhysSrc = GCPhysSrc & ~(RTGCPHYS)X86_PAGE_OFFSET_MASK;
75 pVCpu->nem.s.Hypercall.MapPages.GCPhysDst = GCPhysDst & ~(RTGCPHYS)X86_PAGE_OFFSET_MASK;
76 pVCpu->nem.s.Hypercall.MapPages.cPages = 1;
77 pVCpu->nem.s.Hypercall.MapPages.fFlags = fFlags;
78 return VMMR3CallR0Emt(pVM, pVCpu, VMMR0_DO_NEM_MAP_PAGES, 0, NULL);
79#endif
80}
81
82
83/**
84 * Wrapper around VMMR0_DO_NEM_UNMAP_PAGES for a single page.
85 *
86 * @returns VBox status code.
87 * @param pVM The cross context VM structure.
88 * @param pVCpu The cross context virtual CPU structure of the caller.
89 * @param GCPhys The page to unmap. Does not need to be page aligned.
90 */
91DECLINLINE(int) nemHCWinHypercallUnmapPage(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys)
92{
93# ifdef IN_RING0
94 PGVM pGVM = GVMMR0FastGetGVMByVM(pVM);
95 AssertReturn(pGVM, VERR_INVALID_VM_HANDLE);
96 return nemR0WinUnmapPages(pGVM, &pGVM->aCpus[pVCpu->idCpu], GCPhys & ~(RTGCPHYS)X86_PAGE_OFFSET_MASK, 1);
97# else
98 pVCpu->nem.s.Hypercall.UnmapPages.GCPhys = GCPhys & ~(RTGCPHYS)X86_PAGE_OFFSET_MASK;
99 pVCpu->nem.s.Hypercall.UnmapPages.cPages = 1;
100 return VMMR3CallR0Emt(pVM, pVCpu, VMMR0_DO_NEM_UNMAP_PAGES, 0, NULL);
101# endif
102}
103
104#endif /* NEM_WIN_USE_HYPERCALLS_FOR_PAGES */
105#ifndef IN_RING0
106
107NEM_TMPL_STATIC int nemHCWinCopyStateToHyperV(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
108{
109# ifdef NEM_WIN_USE_HYPERCALLS_FOR_REGISTERS
110 NOREF(pCtx);
111 int rc = VMMR3CallR0Emt(pVM, pVCpu, VMMR0_DO_NEM_EXPORT_STATE, 0, NULL);
112 AssertLogRelRCReturn(rc, rc);
113 return rc;
114
115# else
116 WHV_REGISTER_NAME aenmNames[128];
117 WHV_REGISTER_VALUE aValues[128];
118
119 /* GPRs */
120 aenmNames[0] = WHvX64RegisterRax;
121 aValues[0].Reg64 = pCtx->rax;
122 aenmNames[1] = WHvX64RegisterRcx;
123 aValues[1].Reg64 = pCtx->rcx;
124 aenmNames[2] = WHvX64RegisterRdx;
125 aValues[2].Reg64 = pCtx->rdx;
126 aenmNames[3] = WHvX64RegisterRbx;
127 aValues[3].Reg64 = pCtx->rbx;
128 aenmNames[4] = WHvX64RegisterRsp;
129 aValues[4].Reg64 = pCtx->rsp;
130 aenmNames[5] = WHvX64RegisterRbp;
131 aValues[5].Reg64 = pCtx->rbp;
132 aenmNames[6] = WHvX64RegisterRsi;
133 aValues[6].Reg64 = pCtx->rsi;
134 aenmNames[7] = WHvX64RegisterRdi;
135 aValues[7].Reg64 = pCtx->rdi;
136 aenmNames[8] = WHvX64RegisterR8;
137 aValues[8].Reg64 = pCtx->r8;
138 aenmNames[9] = WHvX64RegisterR9;
139 aValues[9].Reg64 = pCtx->r9;
140 aenmNames[10] = WHvX64RegisterR10;
141 aValues[10].Reg64 = pCtx->r10;
142 aenmNames[11] = WHvX64RegisterR11;
143 aValues[11].Reg64 = pCtx->r11;
144 aenmNames[12] = WHvX64RegisterR12;
145 aValues[12].Reg64 = pCtx->r12;
146 aenmNames[13] = WHvX64RegisterR13;
147 aValues[13].Reg64 = pCtx->r13;
148 aenmNames[14] = WHvX64RegisterR14;
149 aValues[14].Reg64 = pCtx->r14;
150 aenmNames[15] = WHvX64RegisterR15;
151 aValues[15].Reg64 = pCtx->r15;
152
153 /* RIP & Flags */
154 aenmNames[16] = WHvX64RegisterRip;
155 aValues[16].Reg64 = pCtx->rip;
156 aenmNames[17] = WHvX64RegisterRflags;
157 aValues[17].Reg64 = pCtx->rflags.u;
158
159 /* Segments */
160# define COPY_OUT_SEG(a_idx, a_enmName, a_SReg) \
161 do { \
162 aenmNames[a_idx] = a_enmName; \
163 aValues[a_idx].Segment.Base = (a_SReg).u64Base; \
164 aValues[a_idx].Segment.Limit = (a_SReg).u32Limit; \
165 aValues[a_idx].Segment.Selector = (a_SReg).Sel; \
166 aValues[a_idx].Segment.Attributes = (a_SReg).Attr.u; \
167 } while (0)
168 COPY_OUT_SEG(18, WHvX64RegisterEs, pCtx->es);
169 COPY_OUT_SEG(19, WHvX64RegisterCs, pCtx->cs);
170 COPY_OUT_SEG(20, WHvX64RegisterSs, pCtx->ss);
171 COPY_OUT_SEG(21, WHvX64RegisterDs, pCtx->ds);
172 COPY_OUT_SEG(22, WHvX64RegisterFs, pCtx->fs);
173 COPY_OUT_SEG(23, WHvX64RegisterGs, pCtx->gs);
174 COPY_OUT_SEG(24, WHvX64RegisterLdtr, pCtx->ldtr);
175 COPY_OUT_SEG(25, WHvX64RegisterTr, pCtx->tr);
176
177 uintptr_t iReg = 26;
178 /* Descriptor tables. */
179 aenmNames[iReg] = WHvX64RegisterIdtr;
180 aValues[iReg].Table.Limit = pCtx->idtr.cbIdt;
181 aValues[iReg].Table.Base = pCtx->idtr.pIdt;
182 iReg++;
183 aenmNames[iReg] = WHvX64RegisterGdtr;
184 aValues[iReg].Table.Limit = pCtx->gdtr.cbGdt;
185 aValues[iReg].Table.Base = pCtx->gdtr.pGdt;
186 iReg++;
187
188 /* Control registers. */
189 aenmNames[iReg] = WHvX64RegisterCr0;
190 aValues[iReg].Reg64 = pCtx->cr0;
191 iReg++;
192 aenmNames[iReg] = WHvX64RegisterCr2;
193 aValues[iReg].Reg64 = pCtx->cr2;
194 iReg++;
195 aenmNames[iReg] = WHvX64RegisterCr3;
196 aValues[iReg].Reg64 = pCtx->cr3;
197 iReg++;
198 aenmNames[iReg] = WHvX64RegisterCr4;
199 aValues[iReg].Reg64 = pCtx->cr4;
200 iReg++;
201 aenmNames[iReg] = WHvX64RegisterCr8;
202 aValues[iReg].Reg64 = CPUMGetGuestCR8(pVCpu);
203 iReg++;
204
205 /* Debug registers. */
206/** @todo fixme. Figure out what the hyper-v version of KVM_SET_GUEST_DEBUG would be. */
207 aenmNames[iReg] = WHvX64RegisterDr0;
208 //aValues[iReg].Reg64 = CPUMGetHyperDR0(pVCpu);
209 aValues[iReg].Reg64 = pCtx->dr[0];
210 iReg++;
211 aenmNames[iReg] = WHvX64RegisterDr1;
212 //aValues[iReg].Reg64 = CPUMGetHyperDR1(pVCpu);
213 aValues[iReg].Reg64 = pCtx->dr[1];
214 iReg++;
215 aenmNames[iReg] = WHvX64RegisterDr2;
216 //aValues[iReg].Reg64 = CPUMGetHyperDR2(pVCpu);
217 aValues[iReg].Reg64 = pCtx->dr[2];
218 iReg++;
219 aenmNames[iReg] = WHvX64RegisterDr3;
220 //aValues[iReg].Reg64 = CPUMGetHyperDR3(pVCpu);
221 aValues[iReg].Reg64 = pCtx->dr[3];
222 iReg++;
223 aenmNames[iReg] = WHvX64RegisterDr6;
224 //aValues[iReg].Reg64 = CPUMGetHyperDR6(pVCpu);
225 aValues[iReg].Reg64 = pCtx->dr[6];
226 iReg++;
227 aenmNames[iReg] = WHvX64RegisterDr7;
228 //aValues[iReg].Reg64 = CPUMGetHyperDR7(pVCpu);
229 aValues[iReg].Reg64 = pCtx->dr[7];
230 iReg++;
231
232 /* Vector state. */
233 aenmNames[iReg] = WHvX64RegisterXmm0;
234 aValues[iReg].Reg128.Low64 = pCtx->pXStateR3->x87.aXMM[0].uXmm.s.Lo;
235 aValues[iReg].Reg128.High64 = pCtx->pXStateR3->x87.aXMM[0].uXmm.s.Hi;
236 iReg++;
237 aenmNames[iReg] = WHvX64RegisterXmm1;
238 aValues[iReg].Reg128.Low64 = pCtx->pXStateR3->x87.aXMM[1].uXmm.s.Lo;
239 aValues[iReg].Reg128.High64 = pCtx->pXStateR3->x87.aXMM[1].uXmm.s.Hi;
240 iReg++;
241 aenmNames[iReg] = WHvX64RegisterXmm2;
242 aValues[iReg].Reg128.Low64 = pCtx->pXStateR3->x87.aXMM[2].uXmm.s.Lo;
243 aValues[iReg].Reg128.High64 = pCtx->pXStateR3->x87.aXMM[2].uXmm.s.Hi;
244 iReg++;
245 aenmNames[iReg] = WHvX64RegisterXmm3;
246 aValues[iReg].Reg128.Low64 = pCtx->pXStateR3->x87.aXMM[3].uXmm.s.Lo;
247 aValues[iReg].Reg128.High64 = pCtx->pXStateR3->x87.aXMM[3].uXmm.s.Hi;
248 iReg++;
249 aenmNames[iReg] = WHvX64RegisterXmm4;
250 aValues[iReg].Reg128.Low64 = pCtx->pXStateR3->x87.aXMM[4].uXmm.s.Lo;
251 aValues[iReg].Reg128.High64 = pCtx->pXStateR3->x87.aXMM[4].uXmm.s.Hi;
252 iReg++;
253 aenmNames[iReg] = WHvX64RegisterXmm5;
254 aValues[iReg].Reg128.Low64 = pCtx->pXStateR3->x87.aXMM[5].uXmm.s.Lo;
255 aValues[iReg].Reg128.High64 = pCtx->pXStateR3->x87.aXMM[5].uXmm.s.Hi;
256 iReg++;
257 aenmNames[iReg] = WHvX64RegisterXmm6;
258 aValues[iReg].Reg128.Low64 = pCtx->pXStateR3->x87.aXMM[6].uXmm.s.Lo;
259 aValues[iReg].Reg128.High64 = pCtx->pXStateR3->x87.aXMM[6].uXmm.s.Hi;
260 iReg++;
261 aenmNames[iReg] = WHvX64RegisterXmm7;
262 aValues[iReg].Reg128.Low64 = pCtx->pXStateR3->x87.aXMM[7].uXmm.s.Lo;
263 aValues[iReg].Reg128.High64 = pCtx->pXStateR3->x87.aXMM[7].uXmm.s.Hi;
264 iReg++;
265 aenmNames[iReg] = WHvX64RegisterXmm8;
266 aValues[iReg].Reg128.Low64 = pCtx->pXStateR3->x87.aXMM[8].uXmm.s.Lo;
267 aValues[iReg].Reg128.High64 = pCtx->pXStateR3->x87.aXMM[8].uXmm.s.Hi;
268 iReg++;
269 aenmNames[iReg] = WHvX64RegisterXmm9;
270 aValues[iReg].Reg128.Low64 = pCtx->pXStateR3->x87.aXMM[9].uXmm.s.Lo;
271 aValues[iReg].Reg128.High64 = pCtx->pXStateR3->x87.aXMM[9].uXmm.s.Hi;
272 iReg++;
273 aenmNames[iReg] = WHvX64RegisterXmm10;
274 aValues[iReg].Reg128.Low64 = pCtx->pXStateR3->x87.aXMM[10].uXmm.s.Lo;
275 aValues[iReg].Reg128.High64 = pCtx->pXStateR3->x87.aXMM[10].uXmm.s.Hi;
276 iReg++;
277 aenmNames[iReg] = WHvX64RegisterXmm11;
278 aValues[iReg].Reg128.Low64 = pCtx->pXStateR3->x87.aXMM[11].uXmm.s.Lo;
279 aValues[iReg].Reg128.High64 = pCtx->pXStateR3->x87.aXMM[11].uXmm.s.Hi;
280 iReg++;
281 aenmNames[iReg] = WHvX64RegisterXmm12;
282 aValues[iReg].Reg128.Low64 = pCtx->pXStateR3->x87.aXMM[12].uXmm.s.Lo;
283 aValues[iReg].Reg128.High64 = pCtx->pXStateR3->x87.aXMM[12].uXmm.s.Hi;
284 iReg++;
285 aenmNames[iReg] = WHvX64RegisterXmm13;
286 aValues[iReg].Reg128.Low64 = pCtx->pXStateR3->x87.aXMM[13].uXmm.s.Lo;
287 aValues[iReg].Reg128.High64 = pCtx->pXStateR3->x87.aXMM[13].uXmm.s.Hi;
288 iReg++;
289 aenmNames[iReg] = WHvX64RegisterXmm14;
290 aValues[iReg].Reg128.Low64 = pCtx->pXStateR3->x87.aXMM[14].uXmm.s.Lo;
291 aValues[iReg].Reg128.High64 = pCtx->pXStateR3->x87.aXMM[14].uXmm.s.Hi;
292 iReg++;
293 aenmNames[iReg] = WHvX64RegisterXmm15;
294 aValues[iReg].Reg128.Low64 = pCtx->pXStateR3->x87.aXMM[15].uXmm.s.Lo;
295 aValues[iReg].Reg128.High64 = pCtx->pXStateR3->x87.aXMM[15].uXmm.s.Hi;
296 iReg++;
297
298 /* Floating point state. */
299 aenmNames[iReg] = WHvX64RegisterFpMmx0;
300 aValues[iReg].Fp.AsUINT128.Low64 = pCtx->pXStateR3->x87.aRegs[0].au64[0];
301 aValues[iReg].Fp.AsUINT128.High64 = pCtx->pXStateR3->x87.aRegs[0].au64[1];
302 iReg++;
303 aenmNames[iReg] = WHvX64RegisterFpMmx1;
304 aValues[iReg].Fp.AsUINT128.Low64 = pCtx->pXStateR3->x87.aRegs[1].au64[0];
305 aValues[iReg].Fp.AsUINT128.High64 = pCtx->pXStateR3->x87.aRegs[1].au64[1];
306 iReg++;
307 aenmNames[iReg] = WHvX64RegisterFpMmx2;
308 aValues[iReg].Fp.AsUINT128.Low64 = pCtx->pXStateR3->x87.aRegs[2].au64[0];
309 aValues[iReg].Fp.AsUINT128.High64 = pCtx->pXStateR3->x87.aRegs[2].au64[1];
310 iReg++;
311 aenmNames[iReg] = WHvX64RegisterFpMmx3;
312 aValues[iReg].Fp.AsUINT128.Low64 = pCtx->pXStateR3->x87.aRegs[3].au64[0];
313 aValues[iReg].Fp.AsUINT128.High64 = pCtx->pXStateR3->x87.aRegs[3].au64[1];
314 iReg++;
315 aenmNames[iReg] = WHvX64RegisterFpMmx4;
316 aValues[iReg].Fp.AsUINT128.Low64 = pCtx->pXStateR3->x87.aRegs[4].au64[0];
317 aValues[iReg].Fp.AsUINT128.High64 = pCtx->pXStateR3->x87.aRegs[4].au64[1];
318 iReg++;
319 aenmNames[iReg] = WHvX64RegisterFpMmx5;
320 aValues[iReg].Fp.AsUINT128.Low64 = pCtx->pXStateR3->x87.aRegs[5].au64[0];
321 aValues[iReg].Fp.AsUINT128.High64 = pCtx->pXStateR3->x87.aRegs[5].au64[1];
322 iReg++;
323 aenmNames[iReg] = WHvX64RegisterFpMmx6;
324 aValues[iReg].Fp.AsUINT128.Low64 = pCtx->pXStateR3->x87.aRegs[6].au64[0];
325 aValues[iReg].Fp.AsUINT128.High64 = pCtx->pXStateR3->x87.aRegs[6].au64[1];
326 iReg++;
327 aenmNames[iReg] = WHvX64RegisterFpMmx7;
328 aValues[iReg].Fp.AsUINT128.Low64 = pCtx->pXStateR3->x87.aRegs[7].au64[0];
329 aValues[iReg].Fp.AsUINT128.High64 = pCtx->pXStateR3->x87.aRegs[7].au64[1];
330 iReg++;
331
332 aenmNames[iReg] = WHvX64RegisterFpControlStatus;
333 aValues[iReg].FpControlStatus.FpControl = pCtx->pXStateR3->x87.FCW;
334 aValues[iReg].FpControlStatus.FpStatus = pCtx->pXStateR3->x87.FSW;
335 aValues[iReg].FpControlStatus.FpTag = pCtx->pXStateR3->x87.FTW;
336 aValues[iReg].FpControlStatus.Reserved = pCtx->pXStateR3->x87.FTW >> 8;
337 aValues[iReg].FpControlStatus.LastFpOp = pCtx->pXStateR3->x87.FOP;
338 aValues[iReg].FpControlStatus.LastFpRip = (pCtx->pXStateR3->x87.FPUIP)
339 | ((uint64_t)pCtx->pXStateR3->x87.CS << 32)
340 | ((uint64_t)pCtx->pXStateR3->x87.Rsrvd1 << 48);
341 iReg++;
342
343 aenmNames[iReg] = WHvX64RegisterXmmControlStatus;
344 aValues[iReg].XmmControlStatus.LastFpRdp = (pCtx->pXStateR3->x87.FPUDP)
345 | ((uint64_t)pCtx->pXStateR3->x87.DS << 32)
346 | ((uint64_t)pCtx->pXStateR3->x87.Rsrvd2 << 48);
347 aValues[iReg].XmmControlStatus.XmmStatusControl = pCtx->pXStateR3->x87.MXCSR;
348 aValues[iReg].XmmControlStatus.XmmStatusControlMask = pCtx->pXStateR3->x87.MXCSR_MASK; /** @todo ??? (Isn't this an output field?) */
349 iReg++;
350
351 /* MSRs */
352 // WHvX64RegisterTsc - don't touch
353 aenmNames[iReg] = WHvX64RegisterEfer;
354 aValues[iReg].Reg64 = pCtx->msrEFER;
355 iReg++;
356 aenmNames[iReg] = WHvX64RegisterKernelGsBase;
357 aValues[iReg].Reg64 = pCtx->msrKERNELGSBASE;
358 iReg++;
359 aenmNames[iReg] = WHvX64RegisterApicBase;
360 aValues[iReg].Reg64 = APICGetBaseMsrNoCheck(pVCpu);
361 iReg++;
362 aenmNames[iReg] = WHvX64RegisterPat;
363 aValues[iReg].Reg64 = pCtx->msrPAT;
364 iReg++;
365 /// @todo WHvX64RegisterSysenterCs
366 /// @todo WHvX64RegisterSysenterEip
367 /// @todo WHvX64RegisterSysenterEsp
368 aenmNames[iReg] = WHvX64RegisterStar;
369 aValues[iReg].Reg64 = pCtx->msrSTAR;
370 iReg++;
371 aenmNames[iReg] = WHvX64RegisterLstar;
372 aValues[iReg].Reg64 = pCtx->msrLSTAR;
373 iReg++;
374 aenmNames[iReg] = WHvX64RegisterCstar;
375 aValues[iReg].Reg64 = pCtx->msrCSTAR;
376 iReg++;
377 aenmNames[iReg] = WHvX64RegisterSfmask;
378 aValues[iReg].Reg64 = pCtx->msrSFMASK;
379 iReg++;
380
381 /* event injection (always clear it). */
382 aenmNames[iReg] = WHvRegisterPendingInterruption;
383 aValues[iReg].Reg64 = 0;
384 iReg++;
385 /// @todo WHvRegisterInterruptState
386 /// @todo WHvRegisterPendingEvent0
387 /// @todo WHvRegisterPendingEvent1
388 /// @todo WHvX64RegisterDeliverabilityNotifications
389
390 /*
391 * Set the registers.
392 */
393 Assert(iReg < RT_ELEMENTS(aValues));
394 Assert(iReg < RT_ELEMENTS(aenmNames));
395# ifdef NEM_WIN_INTERCEPT_NT_IO_CTLS
396 Log12(("Calling WHvSetVirtualProcessorRegisters(%p, %u, %p, %u, %p)\n",
397 pVM->nem.s.hPartition, pVCpu->idCpu, aenmNames, iReg, aValues));
398# endif
399 HRESULT hrc = WHvSetVirtualProcessorRegisters(pVM->nem.s.hPartition, pVCpu->idCpu, aenmNames, iReg, aValues);
400 if (SUCCEEDED(hrc))
401 return VINF_SUCCESS;
402 AssertLogRelMsgFailed(("WHvSetVirtualProcessorRegisters(%p, %u,,%u,) -> %Rhrc (Last=%#x/%u)\n",
403 pVM->nem.s.hPartition, pVCpu->idCpu, iReg,
404 hrc, RTNtLastStatusValue(), RTNtLastErrorValue()));
405 return VERR_INTERNAL_ERROR;
406# endif /* !NEM_WIN_USE_HYPERCALLS_FOR_REGISTERS */
407}
408
409
410NEM_TMPL_STATIC int nemHCWinCopyStateFromHyperV(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, uint64_t fWhat)
411{
412# ifdef NEM_WIN_USE_HYPERCALLS_FOR_REGISTERS
413 /* See NEMR0ImportState */
414 NOREF(pCtx);
415 int rc = VMMR3CallR0Emt(pVM, pVCpu, VMMR0_DO_NEM_IMPORT_STATE, fWhat, NULL);
416 if (RT_SUCCESS(rc))
417 return rc;
418 if (rc == VERR_NEM_FLUSH_TLB)
419 return PGMFlushTLB(pVCpu, pCtx->cr3, true /*fGlobal*/);
420 if (rc == VERR_NEM_CHANGE_PGM_MODE)
421 return PGMChangeMode(pVCpu, pCtx->cr0, pCtx->cr4, pCtx->msrEFER);
422 AssertLogRelRCReturn(rc, rc);
423 return rc;
424
425# else
426 WHV_REGISTER_NAME aenmNames[128];
427AssertFailed(); /** @todo this code is out of date! */
428
429 /* GPRs */
430 aenmNames[0] = WHvX64RegisterRax;
431 aenmNames[1] = WHvX64RegisterRcx;
432 aenmNames[2] = WHvX64RegisterRdx;
433 aenmNames[3] = WHvX64RegisterRbx;
434 aenmNames[4] = WHvX64RegisterRsp;
435 aenmNames[5] = WHvX64RegisterRbp;
436 aenmNames[6] = WHvX64RegisterRsi;
437 aenmNames[7] = WHvX64RegisterRdi;
438 aenmNames[8] = WHvX64RegisterR8;
439 aenmNames[9] = WHvX64RegisterR9;
440 aenmNames[10] = WHvX64RegisterR10;
441 aenmNames[11] = WHvX64RegisterR11;
442 aenmNames[12] = WHvX64RegisterR12;
443 aenmNames[13] = WHvX64RegisterR13;
444 aenmNames[14] = WHvX64RegisterR14;
445 aenmNames[15] = WHvX64RegisterR15;
446
447 /* RIP & Flags */
448 aenmNames[16] = WHvX64RegisterRip;
449 aenmNames[17] = WHvX64RegisterRflags;
450
451 /* Segments */
452 aenmNames[18] = WHvX64RegisterEs;
453 aenmNames[19] = WHvX64RegisterCs;
454 aenmNames[20] = WHvX64RegisterSs;
455 aenmNames[21] = WHvX64RegisterDs;
456 aenmNames[22] = WHvX64RegisterFs;
457 aenmNames[23] = WHvX64RegisterGs;
458 aenmNames[24] = WHvX64RegisterLdtr;
459 aenmNames[25] = WHvX64RegisterTr;
460
461 /* Descriptor tables. */
462 aenmNames[26] = WHvX64RegisterIdtr;
463 aenmNames[27] = WHvX64RegisterGdtr;
464
465 /* Control registers. */
466 aenmNames[28] = WHvX64RegisterCr0;
467 aenmNames[29] = WHvX64RegisterCr2;
468 aenmNames[30] = WHvX64RegisterCr3;
469 aenmNames[31] = WHvX64RegisterCr4;
470 aenmNames[32] = WHvX64RegisterCr8;
471
472 /* Debug registers. */
473 aenmNames[33] = WHvX64RegisterDr0;
474 aenmNames[34] = WHvX64RegisterDr1;
475 aenmNames[35] = WHvX64RegisterDr2;
476 aenmNames[36] = WHvX64RegisterDr3;
477 aenmNames[37] = WHvX64RegisterDr6;
478 aenmNames[38] = WHvX64RegisterDr7;
479
480 /* Vector state. */
481 aenmNames[39] = WHvX64RegisterXmm0;
482 aenmNames[40] = WHvX64RegisterXmm1;
483 aenmNames[41] = WHvX64RegisterXmm2;
484 aenmNames[42] = WHvX64RegisterXmm3;
485 aenmNames[43] = WHvX64RegisterXmm4;
486 aenmNames[44] = WHvX64RegisterXmm5;
487 aenmNames[45] = WHvX64RegisterXmm6;
488 aenmNames[46] = WHvX64RegisterXmm7;
489 aenmNames[47] = WHvX64RegisterXmm8;
490 aenmNames[48] = WHvX64RegisterXmm9;
491 aenmNames[49] = WHvX64RegisterXmm10;
492 aenmNames[50] = WHvX64RegisterXmm11;
493 aenmNames[51] = WHvX64RegisterXmm12;
494 aenmNames[52] = WHvX64RegisterXmm13;
495 aenmNames[53] = WHvX64RegisterXmm14;
496 aenmNames[54] = WHvX64RegisterXmm15;
497
498 /* Floating point state. */
499 aenmNames[55] = WHvX64RegisterFpMmx0;
500 aenmNames[56] = WHvX64RegisterFpMmx1;
501 aenmNames[57] = WHvX64RegisterFpMmx2;
502 aenmNames[58] = WHvX64RegisterFpMmx3;
503 aenmNames[59] = WHvX64RegisterFpMmx4;
504 aenmNames[60] = WHvX64RegisterFpMmx5;
505 aenmNames[61] = WHvX64RegisterFpMmx6;
506 aenmNames[62] = WHvX64RegisterFpMmx7;
507 aenmNames[63] = WHvX64RegisterFpControlStatus;
508 aenmNames[64] = WHvX64RegisterXmmControlStatus;
509
510 /* MSRs */
511 // WHvX64RegisterTsc - don't touch
512 aenmNames[65] = WHvX64RegisterEfer;
513 aenmNames[66] = WHvX64RegisterKernelGsBase;
514 aenmNames[67] = WHvX64RegisterApicBase;
515 aenmNames[68] = WHvX64RegisterPat;
516 aenmNames[69] = WHvX64RegisterSysenterCs;
517 aenmNames[70] = WHvX64RegisterSysenterEip;
518 aenmNames[71] = WHvX64RegisterSysenterEsp;
519 aenmNames[72] = WHvX64RegisterStar;
520 aenmNames[73] = WHvX64RegisterLstar;
521 aenmNames[74] = WHvX64RegisterCstar;
522 aenmNames[75] = WHvX64RegisterSfmask;
523
524 /* event injection */
525 aenmNames[76] = WHvRegisterPendingInterruption;
526 aenmNames[77] = WHvRegisterInterruptState;
527 aenmNames[78] = WHvRegisterInterruptState;
528 aenmNames[79] = WHvRegisterPendingEvent0;
529 aenmNames[80] = WHvRegisterPendingEvent1;
530 unsigned const cRegs = 81;
531
532 /*
533 * Get the registers.
534 */
535 WHV_REGISTER_VALUE aValues[cRegs];
536 RT_ZERO(aValues);
537 Assert(RT_ELEMENTS(aValues) >= cRegs);
538 Assert(RT_ELEMENTS(aenmNames) >= cRegs);
539# ifdef NEM_WIN_INTERCEPT_NT_IO_CTLS
540 Log12(("Calling WHvGetVirtualProcessorRegisters(%p, %u, %p, %u, %p)\n",
541 pVM->nem.s.hPartition, pVCpu->idCpu, aenmNames, cRegs, aValues));
542# endif
543 HRESULT hrc = WHvGetVirtualProcessorRegisters(pVM->nem.s.hPartition, pVCpu->idCpu, aenmNames, cRegs, aValues);
544 if (SUCCEEDED(hrc))
545 {
546 /* GPRs */
547 Assert(aenmNames[0] == WHvX64RegisterRax);
548 Assert(aenmNames[15] == WHvX64RegisterR15);
549 pCtx->rax = aValues[0].Reg64;
550 pCtx->rcx = aValues[1].Reg64;
551 pCtx->rdx = aValues[2].Reg64;
552 pCtx->rbx = aValues[3].Reg64;
553 pCtx->rsp = aValues[4].Reg64;
554 pCtx->rbp = aValues[5].Reg64;
555 pCtx->rsi = aValues[6].Reg64;
556 pCtx->rdi = aValues[7].Reg64;
557 pCtx->r8 = aValues[8].Reg64;
558 pCtx->r9 = aValues[9].Reg64;
559 pCtx->r10 = aValues[10].Reg64;
560 pCtx->r11 = aValues[11].Reg64;
561 pCtx->r12 = aValues[12].Reg64;
562 pCtx->r13 = aValues[13].Reg64;
563 pCtx->r14 = aValues[14].Reg64;
564 pCtx->r15 = aValues[15].Reg64;
565
566 /* RIP & Flags */
567 Assert(aenmNames[16] == WHvX64RegisterRip);
568 pCtx->rip = aValues[16].Reg64;
569 pCtx->rflags.u = aValues[17].Reg64;
570
571 /* Segments */
572# define COPY_BACK_SEG(a_idx, a_enmName, a_SReg) \
573 do { \
574 Assert(aenmNames[a_idx] == a_enmName); \
575 NEM_WIN_COPY_BACK_SEG(a_SReg, aValues[a_idx]); \
576 } while (0)
577 COPY_BACK_SEG(18, WHvX64RegisterEs, pCtx->es);
578 COPY_BACK_SEG(19, WHvX64RegisterCs, pCtx->cs);
579 COPY_BACK_SEG(20, WHvX64RegisterSs, pCtx->ss);
580 COPY_BACK_SEG(21, WHvX64RegisterDs, pCtx->ds);
581 COPY_BACK_SEG(22, WHvX64RegisterFs, pCtx->fs);
582 COPY_BACK_SEG(23, WHvX64RegisterGs, pCtx->gs);
583 COPY_BACK_SEG(24, WHvX64RegisterLdtr, pCtx->ldtr);
584 /* AMD-V likes loading TR with in AVAIL state, whereas intel insists on BUSY. So,
585 avoid to trigger sanity assertions around the code, always fix this. */
586 COPY_BACK_SEG(25, WHvX64RegisterTr, pCtx->tr);
587 switch (pCtx->tr.Attr.n.u4Type)
588 {
589 case X86_SEL_TYPE_SYS_386_TSS_BUSY:
590 case X86_SEL_TYPE_SYS_286_TSS_BUSY:
591 break;
592 case X86_SEL_TYPE_SYS_386_TSS_AVAIL:
593 pCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
594 break;
595 case X86_SEL_TYPE_SYS_286_TSS_AVAIL:
596 pCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_286_TSS_BUSY;
597 break;
598 }
599
600 /* Descriptor tables. */
601 Assert(aenmNames[26] == WHvX64RegisterIdtr);
602 pCtx->idtr.cbIdt = aValues[26].Table.Limit;
603 pCtx->idtr.pIdt = aValues[26].Table.Base;
604 Assert(aenmNames[27] == WHvX64RegisterGdtr);
605 pCtx->gdtr.cbGdt = aValues[27].Table.Limit;
606 pCtx->gdtr.pGdt = aValues[27].Table.Base;
607
608 /* Control registers. */
609 Assert(aenmNames[28] == WHvX64RegisterCr0);
610 bool fMaybeChangedMode = false;
611 bool fFlushTlb = false;
612 bool fFlushGlobalTlb = false;
613 if (pCtx->cr0 != aValues[28].Reg64)
614 {
615 CPUMSetGuestCR0(pVCpu, aValues[28].Reg64);
616 fMaybeChangedMode = true;
617 fFlushTlb = fFlushGlobalTlb = true; /// @todo fix this
618 }
619 Assert(aenmNames[29] == WHvX64RegisterCr2);
620 pCtx->cr2 = aValues[29].Reg64;
621 if (pCtx->cr3 != aValues[30].Reg64)
622 {
623 CPUMSetGuestCR3(pVCpu, aValues[30].Reg64);
624 fFlushTlb = true;
625 }
626 if (pCtx->cr4 != aValues[31].Reg64)
627 {
628 CPUMSetGuestCR4(pVCpu, aValues[31].Reg64);
629 fMaybeChangedMode = true;
630 fFlushTlb = fFlushGlobalTlb = true; /// @todo fix this
631 }
632 APICSetTpr(pVCpu, (uint8_t)aValues[32].Reg64 << 4);
633
634 /* Debug registers. */
635 Assert(aenmNames[33] == WHvX64RegisterDr0);
636 /** @todo fixme */
637 if (pCtx->dr[0] != aValues[33].Reg64)
638 CPUMSetGuestDR0(pVCpu, aValues[33].Reg64);
639 if (pCtx->dr[1] != aValues[34].Reg64)
640 CPUMSetGuestDR1(pVCpu, aValues[34].Reg64);
641 if (pCtx->dr[2] != aValues[35].Reg64)
642 CPUMSetGuestDR2(pVCpu, aValues[35].Reg64);
643 if (pCtx->dr[3] != aValues[36].Reg64)
644 CPUMSetGuestDR3(pVCpu, aValues[36].Reg64);
645 Assert(aenmNames[37] == WHvX64RegisterDr6);
646 Assert(aenmNames[38] == WHvX64RegisterDr7);
647 if (pCtx->dr[6] != aValues[37].Reg64)
648 CPUMSetGuestDR6(pVCpu, aValues[37].Reg64);
649 if (pCtx->dr[7] != aValues[38].Reg64)
650 CPUMSetGuestDR6(pVCpu, aValues[38].Reg64);
651
652 /* Vector state. */
653 Assert(aenmNames[39] == WHvX64RegisterXmm0);
654 Assert(aenmNames[54] == WHvX64RegisterXmm15);
655 pCtx->pXStateR3->x87.aXMM[0].uXmm.s.Lo = aValues[39].Reg128.Low64;
656 pCtx->pXStateR3->x87.aXMM[0].uXmm.s.Hi = aValues[39].Reg128.High64;
657 pCtx->pXStateR3->x87.aXMM[1].uXmm.s.Lo = aValues[40].Reg128.Low64;
658 pCtx->pXStateR3->x87.aXMM[1].uXmm.s.Hi = aValues[40].Reg128.High64;
659 pCtx->pXStateR3->x87.aXMM[2].uXmm.s.Lo = aValues[41].Reg128.Low64;
660 pCtx->pXStateR3->x87.aXMM[2].uXmm.s.Hi = aValues[41].Reg128.High64;
661 pCtx->pXStateR3->x87.aXMM[3].uXmm.s.Lo = aValues[42].Reg128.Low64;
662 pCtx->pXStateR3->x87.aXMM[3].uXmm.s.Hi = aValues[42].Reg128.High64;
663 pCtx->pXStateR3->x87.aXMM[4].uXmm.s.Lo = aValues[43].Reg128.Low64;
664 pCtx->pXStateR3->x87.aXMM[4].uXmm.s.Hi = aValues[43].Reg128.High64;
665 pCtx->pXStateR3->x87.aXMM[5].uXmm.s.Lo = aValues[44].Reg128.Low64;
666 pCtx->pXStateR3->x87.aXMM[5].uXmm.s.Hi = aValues[44].Reg128.High64;
667 pCtx->pXStateR3->x87.aXMM[6].uXmm.s.Lo = aValues[45].Reg128.Low64;
668 pCtx->pXStateR3->x87.aXMM[6].uXmm.s.Hi = aValues[45].Reg128.High64;
669 pCtx->pXStateR3->x87.aXMM[7].uXmm.s.Lo = aValues[46].Reg128.Low64;
670 pCtx->pXStateR3->x87.aXMM[7].uXmm.s.Hi = aValues[46].Reg128.High64;
671 pCtx->pXStateR3->x87.aXMM[8].uXmm.s.Lo = aValues[47].Reg128.Low64;
672 pCtx->pXStateR3->x87.aXMM[8].uXmm.s.Hi = aValues[47].Reg128.High64;
673 pCtx->pXStateR3->x87.aXMM[9].uXmm.s.Lo = aValues[48].Reg128.Low64;
674 pCtx->pXStateR3->x87.aXMM[9].uXmm.s.Hi = aValues[48].Reg128.High64;
675 pCtx->pXStateR3->x87.aXMM[10].uXmm.s.Lo = aValues[49].Reg128.Low64;
676 pCtx->pXStateR3->x87.aXMM[10].uXmm.s.Hi = aValues[49].Reg128.High64;
677 pCtx->pXStateR3->x87.aXMM[11].uXmm.s.Lo = aValues[50].Reg128.Low64;
678 pCtx->pXStateR3->x87.aXMM[11].uXmm.s.Hi = aValues[50].Reg128.High64;
679 pCtx->pXStateR3->x87.aXMM[12].uXmm.s.Lo = aValues[51].Reg128.Low64;
680 pCtx->pXStateR3->x87.aXMM[12].uXmm.s.Hi = aValues[51].Reg128.High64;
681 pCtx->pXStateR3->x87.aXMM[13].uXmm.s.Lo = aValues[52].Reg128.Low64;
682 pCtx->pXStateR3->x87.aXMM[13].uXmm.s.Hi = aValues[52].Reg128.High64;
683 pCtx->pXStateR3->x87.aXMM[14].uXmm.s.Lo = aValues[53].Reg128.Low64;
684 pCtx->pXStateR3->x87.aXMM[14].uXmm.s.Hi = aValues[53].Reg128.High64;
685 pCtx->pXStateR3->x87.aXMM[15].uXmm.s.Lo = aValues[54].Reg128.Low64;
686 pCtx->pXStateR3->x87.aXMM[15].uXmm.s.Hi = aValues[54].Reg128.High64;
687
688 /* Floating point state. */
689 Assert(aenmNames[55] == WHvX64RegisterFpMmx0);
690 Assert(aenmNames[62] == WHvX64RegisterFpMmx7);
691 pCtx->pXStateR3->x87.aRegs[0].au64[0] = aValues[55].Fp.AsUINT128.Low64;
692 pCtx->pXStateR3->x87.aRegs[0].au64[1] = aValues[55].Fp.AsUINT128.High64;
693 pCtx->pXStateR3->x87.aRegs[1].au64[0] = aValues[56].Fp.AsUINT128.Low64;
694 pCtx->pXStateR3->x87.aRegs[1].au64[1] = aValues[56].Fp.AsUINT128.High64;
695 pCtx->pXStateR3->x87.aRegs[2].au64[0] = aValues[57].Fp.AsUINT128.Low64;
696 pCtx->pXStateR3->x87.aRegs[2].au64[1] = aValues[57].Fp.AsUINT128.High64;
697 pCtx->pXStateR3->x87.aRegs[3].au64[0] = aValues[58].Fp.AsUINT128.Low64;
698 pCtx->pXStateR3->x87.aRegs[3].au64[1] = aValues[58].Fp.AsUINT128.High64;
699 pCtx->pXStateR3->x87.aRegs[4].au64[0] = aValues[59].Fp.AsUINT128.Low64;
700 pCtx->pXStateR3->x87.aRegs[4].au64[1] = aValues[59].Fp.AsUINT128.High64;
701 pCtx->pXStateR3->x87.aRegs[5].au64[0] = aValues[60].Fp.AsUINT128.Low64;
702 pCtx->pXStateR3->x87.aRegs[5].au64[1] = aValues[60].Fp.AsUINT128.High64;
703 pCtx->pXStateR3->x87.aRegs[6].au64[0] = aValues[61].Fp.AsUINT128.Low64;
704 pCtx->pXStateR3->x87.aRegs[6].au64[1] = aValues[61].Fp.AsUINT128.High64;
705 pCtx->pXStateR3->x87.aRegs[7].au64[0] = aValues[62].Fp.AsUINT128.Low64;
706 pCtx->pXStateR3->x87.aRegs[7].au64[1] = aValues[62].Fp.AsUINT128.High64;
707
708 Assert(aenmNames[63] == WHvX64RegisterFpControlStatus);
709 pCtx->pXStateR3->x87.FCW = aValues[63].FpControlStatus.FpControl;
710 pCtx->pXStateR3->x87.FSW = aValues[63].FpControlStatus.FpStatus;
711 pCtx->pXStateR3->x87.FTW = aValues[63].FpControlStatus.FpTag
712 /*| (aValues[63].FpControlStatus.Reserved << 8)*/;
713 pCtx->pXStateR3->x87.FOP = aValues[63].FpControlStatus.LastFpOp;
714 pCtx->pXStateR3->x87.FPUIP = (uint32_t)aValues[63].FpControlStatus.LastFpRip;
715 pCtx->pXStateR3->x87.CS = (uint16_t)(aValues[63].FpControlStatus.LastFpRip >> 32);
716 pCtx->pXStateR3->x87.Rsrvd1 = (uint16_t)(aValues[63].FpControlStatus.LastFpRip >> 48);
717
718 Assert(aenmNames[64] == WHvX64RegisterXmmControlStatus);
719 pCtx->pXStateR3->x87.FPUDP = (uint32_t)aValues[64].XmmControlStatus.LastFpRdp;
720 pCtx->pXStateR3->x87.DS = (uint16_t)(aValues[64].XmmControlStatus.LastFpRdp >> 32);
721 pCtx->pXStateR3->x87.Rsrvd2 = (uint16_t)(aValues[64].XmmControlStatus.LastFpRdp >> 48);
722 pCtx->pXStateR3->x87.MXCSR = aValues[64].XmmControlStatus.XmmStatusControl;
723 pCtx->pXStateR3->x87.MXCSR_MASK = aValues[64].XmmControlStatus.XmmStatusControlMask; /** @todo ??? (Isn't this an output field?) */
724
725 /* MSRs */
726 // WHvX64RegisterTsc - don't touch
727 Assert(aenmNames[65] == WHvX64RegisterEfer);
728 if (aValues[65].Reg64 != pCtx->msrEFER)
729 {
730 pCtx->msrEFER = aValues[65].Reg64;
731 fMaybeChangedMode = true;
732 }
733
734 Assert(aenmNames[66] == WHvX64RegisterKernelGsBase);
735 pCtx->msrKERNELGSBASE = aValues[66].Reg64;
736
737 Assert(aenmNames[67] == WHvX64RegisterApicBase);
738 if (aValues[67].Reg64 != APICGetBaseMsrNoCheck(pVCpu))
739 {
740 VBOXSTRICTRC rc2 = APICSetBaseMsr(pVCpu, aValues[67].Reg64);
741 Assert(rc2 == VINF_SUCCESS); NOREF(rc2);
742 }
743
744 Assert(aenmNames[68] == WHvX64RegisterPat);
745 pCtx->msrPAT = aValues[68].Reg64;
746 /// @todo WHvX64RegisterSysenterCs
747 /// @todo WHvX64RegisterSysenterEip
748 /// @todo WHvX64RegisterSysenterEsp
749 Assert(aenmNames[72] == WHvX64RegisterStar);
750 pCtx->msrSTAR = aValues[72].Reg64;
751 Assert(aenmNames[73] == WHvX64RegisterLstar);
752 pCtx->msrLSTAR = aValues[73].Reg64;
753 Assert(aenmNames[74] == WHvX64RegisterCstar);
754 pCtx->msrCSTAR = aValues[74].Reg64;
755 Assert(aenmNames[75] == WHvX64RegisterSfmask);
756 pCtx->msrSFMASK = aValues[75].Reg64;
757
758 /// @todo WHvRegisterPendingInterruption
759 Assert(aenmNames[76] == WHvRegisterPendingInterruption);
760 WHV_X64_PENDING_INTERRUPTION_REGISTER const * pPendingInt = (WHV_X64_PENDING_INTERRUPTION_REGISTER const *)&aValues[76];
761 if (pPendingInt->InterruptionPending)
762 {
763 Log7(("PendingInterruption: type=%u vector=%#x errcd=%RTbool/%#x instr-len=%u nested=%u\n",
764 pPendingInt->InterruptionType, pPendingInt->InterruptionVector, pPendingInt->DeliverErrorCode,
765 pPendingInt->ErrorCode, pPendingInt->InstructionLength, pPendingInt->NestedEvent));
766 AssertMsg((pPendingInt->AsUINT64 & UINT64_C(0xfc00)) == 0, ("%#RX64\n", pPendingInt->AsUINT64));
767 }
768
769 /// @todo WHvRegisterInterruptState
770 /// @todo WHvRegisterPendingEvent0
771 /// @todo WHvRegisterPendingEvent1
772
773 pCtx->fExtrn = 0;
774
775 if (fMaybeChangedMode)
776 {
777 int rc = PGMChangeMode(pVCpu, pCtx->cr0, pCtx->cr4, pCtx->msrEFER);
778 AssertRC(rc);
779 }
780 if (fFlushTlb)
781 {
782 int rc = PGMFlushTLB(pVCpu, pCtx->cr3, fFlushGlobalTlb);
783 AssertRC(rc);
784 }
785
786 return VINF_SUCCESS;
787 }
788
789 AssertLogRelMsgFailed(("WHvGetVirtualProcessorRegisters(%p, %u,,%u,) -> %Rhrc (Last=%#x/%u)\n",
790 pVM->nem.s.hPartition, pVCpu->idCpu, cRegs,
791 hrc, RTNtLastStatusValue(), RTNtLastErrorValue()));
792 return VERR_INTERNAL_ERROR;
793# endif /* !NEM_WIN_USE_HYPERCALLS_FOR_REGISTERS */
794}
795
796#endif /* !IN_RING0 */
797
798
799#ifdef LOG_ENABLED
800/**
801 * Get the virtual processor running status.
802 */
803DECLINLINE(VID_PROCESSOR_STATUS) nemHCWinCpuGetRunningStatus(PVMCPU pVCpu)
804{
805# ifdef IN_RING0
806 NOREF(pVCpu);
807 return VidProcessorStatusUndefined;
808# else
809 RTERRVARS Saved;
810 RTErrVarsSave(&Saved);
811
812 /*
813 * This API is disabled in release builds, it seems. On build 17101 it requires
814 * the following patch to be enabled (windbg): eb vid+12180 0f 84 98 00 00 00
815 */
816 VID_PROCESSOR_STATUS enmCpuStatus = VidProcessorStatusUndefined;
817 NTSTATUS rcNt = g_pfnVidGetVirtualProcessorRunningStatus(pVCpu->pVMR3->nem.s.hPartitionDevice, pVCpu->idCpu, &enmCpuStatus);
818 AssertRC(rcNt);
819
820 RTErrVarsRestore(&Saved);
821 return enmCpuStatus;
822# endif
823}
824#endif
825
826
827#ifdef NEM_WIN_USE_OUR_OWN_RUN_API
828# ifdef IN_RING3 /* hopefully not needed in ring-0, as we'd need KTHREADs and KeAlertThread. */
829/**
830 * Our own WHvCancelRunVirtualProcessor that can later be moved to ring-0.
831 *
832 * This is an experiment only.
833 *
834 * @returns VBox status code.
835 * @param pVM The cross context VM structure.
836 * @param pVCpu The cross context virtual CPU structure of the
837 * calling EMT.
838 */
839NEM_TMPL_STATIC int nemHCWinCancelRunVirtualProcessor(PVM pVM, PVMCPU pVCpu)
840{
841 /*
842 * Work the state.
843 *
844 * From the looks of things, we should let the EMT call VidStopVirtualProcessor.
845 * So, we just need to modify the state and kick the EMT if it's waiting on
846 * messages. For the latter we use QueueUserAPC / KeAlterThread.
847 */
848 for (;;)
849 {
850 VMCPUSTATE enmState = VMCPU_GET_STATE(pVCpu);
851 switch (enmState)
852 {
853 case VMCPUSTATE_STARTED_EXEC_NEM:
854 if (VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC_NEM_CANCELED, VMCPUSTATE_STARTED_EXEC_NEM))
855 {
856 Log8(("nemHCWinCancelRunVirtualProcessor: Switched %u to canceled state\n", pVCpu->idCpu));
857 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatCancelChangedState);
858 return VINF_SUCCESS;
859 }
860 break;
861
862 case VMCPUSTATE_STARTED_EXEC_NEM_WAIT:
863 if (VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC_NEM_CANCELED, VMCPUSTATE_STARTED_EXEC_NEM_WAIT))
864 {
865# ifdef IN_RING0
866 NTSTATUS rcNt = KeAlertThread(??);
867# else
868 NTSTATUS rcNt = NtAlertThread(pVCpu->nem.s.hNativeThreadHandle);
869# endif
870 Log8(("nemHCWinCancelRunVirtualProcessor: Alerted %u: %#x\n", pVCpu->idCpu, rcNt));
871 Assert(rcNt == STATUS_SUCCESS);
872 if (NT_SUCCESS(rcNt))
873 {
874 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatCancelAlertedThread);
875 return VINF_SUCCESS;
876 }
877 AssertLogRelMsgFailedReturn(("NtAlertThread failed: %#x\n", rcNt), RTErrConvertFromNtStatus(rcNt));
878 }
879 break;
880
881 default:
882 return VINF_SUCCESS;
883 }
884
885 ASMNopPause();
886 RT_NOREF(pVM);
887 }
888}
889# endif /* IN_RING3 */
890#endif /* NEM_WIN_USE_OUR_OWN_RUN_API */
891
892
893#ifdef LOG_ENABLED
894/**
895 * Logs the current CPU state.
896 */
897NEM_TMPL_STATIC void nemHCWinLogState(PVM pVM, PVMCPU pVCpu)
898{
899 if (LogIs3Enabled())
900 {
901# ifdef IN_RING3
902 char szRegs[4096];
903 DBGFR3RegPrintf(pVM->pUVM, pVCpu->idCpu, &szRegs[0], sizeof(szRegs),
904 "rax=%016VR{rax} rbx=%016VR{rbx} rcx=%016VR{rcx} rdx=%016VR{rdx}\n"
905 "rsi=%016VR{rsi} rdi=%016VR{rdi} r8 =%016VR{r8} r9 =%016VR{r9}\n"
906 "r10=%016VR{r10} r11=%016VR{r11} r12=%016VR{r12} r13=%016VR{r13}\n"
907 "r14=%016VR{r14} r15=%016VR{r15} %VRF{rflags}\n"
908 "rip=%016VR{rip} rsp=%016VR{rsp} rbp=%016VR{rbp}\n"
909 "cs={%04VR{cs} base=%016VR{cs_base} limit=%08VR{cs_lim} flags=%04VR{cs_attr}} cr0=%016VR{cr0}\n"
910 "ds={%04VR{ds} base=%016VR{ds_base} limit=%08VR{ds_lim} flags=%04VR{ds_attr}} cr2=%016VR{cr2}\n"
911 "es={%04VR{es} base=%016VR{es_base} limit=%08VR{es_lim} flags=%04VR{es_attr}} cr3=%016VR{cr3}\n"
912 "fs={%04VR{fs} base=%016VR{fs_base} limit=%08VR{fs_lim} flags=%04VR{fs_attr}} cr4=%016VR{cr4}\n"
913 "gs={%04VR{gs} base=%016VR{gs_base} limit=%08VR{gs_lim} flags=%04VR{gs_attr}} cr8=%016VR{cr8}\n"
914 "ss={%04VR{ss} base=%016VR{ss_base} limit=%08VR{ss_lim} flags=%04VR{ss_attr}}\n"
915 "dr0=%016VR{dr0} dr1=%016VR{dr1} dr2=%016VR{dr2} dr3=%016VR{dr3}\n"
916 "dr6=%016VR{dr6} dr7=%016VR{dr7}\n"
917 "gdtr=%016VR{gdtr_base}:%04VR{gdtr_lim} idtr=%016VR{idtr_base}:%04VR{idtr_lim} rflags=%08VR{rflags}\n"
918 "ldtr={%04VR{ldtr} base=%016VR{ldtr_base} limit=%08VR{ldtr_lim} flags=%08VR{ldtr_attr}}\n"
919 "tr ={%04VR{tr} base=%016VR{tr_base} limit=%08VR{tr_lim} flags=%08VR{tr_attr}}\n"
920 " sysenter={cs=%04VR{sysenter_cs} eip=%08VR{sysenter_eip} esp=%08VR{sysenter_esp}}\n"
921 " efer=%016VR{efer}\n"
922 " pat=%016VR{pat}\n"
923 " sf_mask=%016VR{sf_mask}\n"
924 "krnl_gs_base=%016VR{krnl_gs_base}\n"
925 " lstar=%016VR{lstar}\n"
926 " star=%016VR{star} cstar=%016VR{cstar}\n"
927 "fcw=%04VR{fcw} fsw=%04VR{fsw} ftw=%04VR{ftw} mxcsr=%04VR{mxcsr} mxcsr_mask=%04VR{mxcsr_mask}\n"
928 );
929
930 char szInstr[256];
931 DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, 0, 0,
932 DBGF_DISAS_FLAGS_CURRENT_GUEST | DBGF_DISAS_FLAGS_DEFAULT_MODE,
933 szInstr, sizeof(szInstr), NULL);
934 Log3(("%s%s\n", szRegs, szInstr));
935# else
936 /** @todo stat logging in ring-0 */
937 RT_NOREF(pVM, pVCpu);
938# endif
939 }
940}
941#endif /* LOG_ENABLED */
942
943
944/**
945 * Advances the guest RIP and clear EFLAGS.RF.
946 *
947 * This may clear VMCPU_FF_INHIBIT_INTERRUPTS.
948 *
949 * @param pVCpu The cross context virtual CPU structure.
950 * @param pCtx The CPU context to update.
951 * @param pExitCtx The exit context.
952 */
953DECLINLINE(void) nemHCWinAdvanceGuestRipAndClearRF(PVMCPU pVCpu, PCPUMCTX pCtx, HV_X64_INTERCEPT_MESSAGE_HEADER const *pMsgHdr)
954{
955 Assert(!(pCtx->fExtrn & (CPUMCTX_EXTRN_RIP | CPUMCTX_EXTRN_RFLAGS)));
956
957 /* Advance the RIP. */
958 Assert(pMsgHdr->InstructionLength > 0 && pMsgHdr->InstructionLength < 16);
959 pCtx->rip += pMsgHdr->InstructionLength;
960 pCtx->rflags.Bits.u1RF = 0;
961
962 /* Update interrupt inhibition. */
963 if (!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
964 { /* likely */ }
965 else if (pCtx->rip != EMGetInhibitInterruptsPC(pVCpu))
966 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
967}
968
969
970NEM_TMPL_STATIC VBOXSTRICTRC
971nemHCWinHandleHalt(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
972{
973 NOREF(pVM); NOREF(pVCpu); NOREF(pCtx);
974 LogFlow(("nemHCWinHandleHalt\n"));
975 return VINF_EM_HALT;
976}
977
978
979NEM_TMPL_STATIC DECLCALLBACK(int)
980nemHCWinUnmapOnePageCallback(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, uint8_t *pu2NemState, void *pvUser)
981{
982 RT_NOREF_PV(pvUser);
983#ifdef NEM_WIN_USE_HYPERCALLS_FOR_PAGES
984 int rc = nemHCWinHypercallUnmapPage(pVM, pVCpu, GCPhys);
985 AssertRC(rc);
986 if (RT_SUCCESS(rc))
987#else
988 RT_NOREF_PV(pVCpu);
989 HRESULT hrc = WHvUnmapGpaRange(pVM->nem.s.hPartition, GCPhys, X86_PAGE_SIZE);
990 if (SUCCEEDED(hrc))
991#endif
992 {
993 Log5(("NEM GPA unmap all: %RGp (cMappedPages=%u)\n", GCPhys, pVM->nem.s.cMappedPages - 1));
994 *pu2NemState = NEM_WIN_PAGE_STATE_UNMAPPED;
995 }
996 else
997 {
998#ifdef NEM_WIN_USE_HYPERCALLS_FOR_PAGES
999 LogRel(("nemR3WinUnmapOnePageCallback: GCPhys=%RGp rc=%Rrc\n", GCPhys, rc));
1000#else
1001 LogRel(("nemR3WinUnmapOnePageCallback: GCPhys=%RGp %s hrc=%Rhrc (%#x) Last=%#x/%u (cMappedPages=%u)\n",
1002 GCPhys, g_apszPageStates[*pu2NemState], hrc, hrc, RTNtLastStatusValue(),
1003 RTNtLastErrorValue(), pVM->nem.s.cMappedPages));
1004#endif
1005 *pu2NemState = NEM_WIN_PAGE_STATE_NOT_SET;
1006 }
1007 if (pVM->nem.s.cMappedPages > 0)
1008 ASMAtomicDecU32(&pVM->nem.s.cMappedPages);
1009 return VINF_SUCCESS;
1010}
1011
1012
1013/**
1014 * State to pass between nemHCWinHandleMemoryAccess / nemR3WinWHvHandleMemoryAccess
1015 * and nemHCWinHandleMemoryAccessPageCheckerCallback.
1016 */
1017typedef struct NEMHCWINHMACPCCSTATE
1018{
1019 /** Input: Write access. */
1020 bool fWriteAccess;
1021 /** Output: Set if we did something. */
1022 bool fDidSomething;
1023 /** Output: Set it we should resume. */
1024 bool fCanResume;
1025} NEMHCWINHMACPCCSTATE;
1026
1027/**
1028 * @callback_method_impl{FNPGMPHYSNEMCHECKPAGE,
1029 * Worker for nemR3WinHandleMemoryAccess; pvUser points to a
1030 * NEMHCWINHMACPCCSTATE structure. }
1031 */
1032NEM_TMPL_STATIC DECLCALLBACK(int)
1033nemHCWinHandleMemoryAccessPageCheckerCallback(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, PPGMPHYSNEMPAGEINFO pInfo, void *pvUser)
1034{
1035 NEMHCWINHMACPCCSTATE *pState = (NEMHCWINHMACPCCSTATE *)pvUser;
1036 pState->fDidSomething = false;
1037 pState->fCanResume = false;
1038
1039 /* If A20 is disabled, we may need to make another query on the masked
1040 page to get the correct protection information. */
1041 uint8_t u2State = pInfo->u2NemState;
1042 RTGCPHYS GCPhysSrc;
1043 if ( pVM->nem.s.fA20Enabled
1044 || !NEM_WIN_IS_SUBJECT_TO_A20(GCPhys))
1045 GCPhysSrc = GCPhys;
1046 else
1047 {
1048 GCPhysSrc = GCPhys & ~(RTGCPHYS)RT_BIT_32(20);
1049 PGMPHYSNEMPAGEINFO Info2;
1050 int rc = PGMPhysNemPageInfoChecker(pVM, pVCpu, GCPhysSrc, pState->fWriteAccess, &Info2, NULL, NULL);
1051 AssertRCReturn(rc, rc);
1052
1053 *pInfo = Info2;
1054 pInfo->u2NemState = u2State;
1055 }
1056
1057 /*
1058 * Consolidate current page state with actual page protection and access type.
1059 * We don't really consider downgrades here, as they shouldn't happen.
1060 */
1061#ifndef NEM_WIN_USE_HYPERCALLS_FOR_PAGES
1062 /** @todo Someone at microsoft please explain:
1063 * I'm not sure WTF was going on, but I ended up in a loop if I remapped a
1064 * readonly page as writable (unmap, then map again). Specifically, this was an
1065 * issue with the big VRAM mapping at 0xe0000000 when booing DSL 4.4.1. So, in
1066 * a hope to work around that we no longer pre-map anything, just unmap stuff
1067 * and do it lazily here. And here we will first unmap, restart, and then remap
1068 * with new protection or backing.
1069 */
1070#endif
1071 int rc;
1072 switch (u2State)
1073 {
1074 case NEM_WIN_PAGE_STATE_UNMAPPED:
1075 case NEM_WIN_PAGE_STATE_NOT_SET:
1076 if (pInfo->fNemProt == NEM_PAGE_PROT_NONE)
1077 {
1078 Log4(("nemHCWinHandleMemoryAccessPageCheckerCallback: %RGp - #1\n", GCPhys));
1079 return VINF_SUCCESS;
1080 }
1081
1082 /* Don't bother remapping it if it's a write request to a non-writable page. */
1083 if ( pState->fWriteAccess
1084 && !(pInfo->fNemProt & NEM_PAGE_PROT_WRITE))
1085 {
1086 Log4(("nemHCWinHandleMemoryAccessPageCheckerCallback: %RGp - #1w\n", GCPhys));
1087 return VINF_SUCCESS;
1088 }
1089
1090 /* Map the page. */
1091 rc = nemHCNativeSetPhysPage(pVM,
1092 pVCpu,
1093 GCPhysSrc & ~(RTGCPHYS)X86_PAGE_OFFSET_MASK,
1094 GCPhys & ~(RTGCPHYS)X86_PAGE_OFFSET_MASK,
1095 pInfo->fNemProt,
1096 &u2State,
1097 true /*fBackingState*/);
1098 pInfo->u2NemState = u2State;
1099 Log4(("nemHCWinHandleMemoryAccessPageCheckerCallback: %RGp - synced => %s + %Rrc\n",
1100 GCPhys, g_apszPageStates[u2State], rc));
1101 pState->fDidSomething = true;
1102 pState->fCanResume = true;
1103 return rc;
1104
1105 case NEM_WIN_PAGE_STATE_READABLE:
1106 if ( !(pInfo->fNemProt & NEM_PAGE_PROT_WRITE)
1107 && (pInfo->fNemProt & (NEM_PAGE_PROT_READ | NEM_PAGE_PROT_EXECUTE)))
1108 {
1109 Log4(("nemHCWinHandleMemoryAccessPageCheckerCallback: %RGp - #2\n", GCPhys));
1110 return VINF_SUCCESS;
1111 }
1112
1113#ifdef NEM_WIN_USE_HYPERCALLS_FOR_PAGES
1114 /* Upgrade page to writable. */
1115/** @todo test this*/
1116 if ( (pInfo->fNemProt & NEM_PAGE_PROT_WRITE)
1117 && pState->fWriteAccess)
1118 {
1119 rc = nemHCWinHypercallMapPage(pVM, pVCpu, GCPhysSrc, GCPhys,
1120 HV_MAP_GPA_READABLE | HV_MAP_GPA_WRITABLE
1121 | HV_MAP_GPA_EXECUTABLE | HV_MAP_GPA_EXECUTABLE_AGAIN);
1122 AssertRC(rc);
1123 if (RT_SUCCESS(rc))
1124 {
1125 pInfo->u2NemState = NEM_WIN_PAGE_STATE_WRITABLE;
1126 pState->fDidSomething = true;
1127 pState->fCanResume = true;
1128 Log5(("NEM GPA write-upgrade/exit: %RGp (was %s, cMappedPages=%u)\n",
1129 GCPhys, g_apszPageStates[u2State], pVM->nem.s.cMappedPages));
1130 }
1131 }
1132 else
1133 {
1134 /* Need to emulate the acces. */
1135 AssertBreak(pInfo->fNemProt != NEM_PAGE_PROT_NONE); /* There should be no downgrades. */
1136 rc = VINF_SUCCESS;
1137 }
1138 return rc;
1139#else
1140 break;
1141#endif
1142
1143 case NEM_WIN_PAGE_STATE_WRITABLE:
1144 if (pInfo->fNemProt & NEM_PAGE_PROT_WRITE)
1145 {
1146 Log4(("nemHCWinHandleMemoryAccessPageCheckerCallback: %RGp - #3\n", GCPhys));
1147 return VINF_SUCCESS;
1148 }
1149#ifdef NEM_WIN_USE_HYPERCALLS_FOR_PAGES
1150 AssertFailed(); /* There should be no downgrades. */
1151#endif
1152 break;
1153
1154 default:
1155 AssertLogRelMsgFailedReturn(("u2State=%#x\n", u2State), VERR_INTERNAL_ERROR_3);
1156 }
1157
1158 /*
1159 * Unmap and restart the instruction.
1160 * If this fails, which it does every so often, just unmap everything for now.
1161 */
1162#ifdef NEM_WIN_USE_HYPERCALLS_FOR_PAGES
1163 rc = nemHCWinHypercallUnmapPage(pVM, pVCpu, GCPhys);
1164 AssertRC(rc);
1165 if (RT_SUCCESS(rc))
1166#else
1167 /** @todo figure out whether we mess up the state or if it's WHv. */
1168 HRESULT hrc = WHvUnmapGpaRange(pVM->nem.s.hPartition, GCPhys, X86_PAGE_SIZE);
1169 if (SUCCEEDED(hrc))
1170#endif
1171 {
1172 pState->fDidSomething = true;
1173 pState->fCanResume = true;
1174 pInfo->u2NemState = NEM_WIN_PAGE_STATE_UNMAPPED;
1175 uint32_t cMappedPages = ASMAtomicDecU32(&pVM->nem.s.cMappedPages); NOREF(cMappedPages);
1176 Log5(("NEM GPA unmapped/exit: %RGp (was %s, cMappedPages=%u)\n", GCPhys, g_apszPageStates[u2State], cMappedPages));
1177 return VINF_SUCCESS;
1178 }
1179#ifdef NEM_WIN_USE_HYPERCALLS_FOR_PAGES
1180 LogRel(("nemHCWinHandleMemoryAccessPageCheckerCallback/unmap: GCPhysDst=%RGp rc=%Rrc\n", GCPhys, rc));
1181 return rc;
1182#else
1183 LogRel(("nemHCWinHandleMemoryAccessPageCheckerCallback/unmap: GCPhysDst=%RGp %s hrc=%Rhrc (%#x) Last=%#x/%u (cMappedPages=%u)\n",
1184 GCPhys, g_apszPageStates[u2State], hrc, hrc, RTNtLastStatusValue(), RTNtLastErrorValue(),
1185 pVM->nem.s.cMappedPages));
1186
1187 PGMPhysNemEnumPagesByState(pVM, pVCpu, NEM_WIN_PAGE_STATE_READABLE, nemR3WinUnmapOnePageCallback, NULL);
1188 Log(("nemHCWinHandleMemoryAccessPageCheckerCallback: Unmapped all (cMappedPages=%u)\n", pVM->nem.s.cMappedPages));
1189
1190 pState->fDidSomething = true;
1191 pState->fCanResume = true;
1192 pInfo->u2NemState = NEM_WIN_PAGE_STATE_UNMAPPED;
1193 return VINF_SUCCESS;
1194#endif
1195}
1196
1197
1198#ifdef NEM_WIN_USE_OUR_OWN_RUN_API
1199
1200# ifdef IN_RING0
1201/**
1202 * Wrapper around nemR0WinImportState that converts VERR_NEM_CHANGE_PGM_MODE and
1203 * VERR_NEM_FLUSH_TBL into informational status codes and logs+asserts statuses.
1204 *
1205 * @returns VBox strict status code.
1206 * @param pGVM The global (ring-0) VM structure.
1207 * @param pGVCpu The global (ring-0) per CPU structure.
1208 * @param pCtx The CPU context to import into.
1209 * @param fWhat What to import.
1210 * @param pszCaller Who is doing the importing.
1211 */
1212DECLINLINE(VBOXSTRICTRC) nemR0WinImportStateStrict(PGVM pGVM, PGVMCPU pGVCpu, PCPUMCTX pCtx, uint64_t fWhat, const char *pszCaller)
1213{
1214 int rc = nemR0WinImportState(pGVM, pGVCpu, pCtx, fWhat);
1215 if (RT_SUCCESS(rc))
1216 {
1217 Assert(rc == VINF_SUCCESS);
1218 return VINF_SUCCESS;
1219 }
1220
1221 if (rc == VERR_NEM_CHANGE_PGM_MODE || rc == VERR_NEM_FLUSH_TLB)
1222 {
1223 Log4(("%s/%u: nemR0WinImportState -> %Rrc\n", pszCaller, pGVCpu->idCpu, -rc));
1224 return -rc;
1225 }
1226 RT_NOREF(pszCaller);
1227 AssertMsgFailedReturn(("%s/%u: nemR0WinImportState failed: %Rrc\n", pszCaller, pGVCpu->idCpu, rc), rc);
1228}
1229# endif /* IN_RING0 */
1230
1231
1232/**
1233 * Wrapper around nemR0WinImportStateStrict and nemHCWinCopyStateFromHyperV.
1234 *
1235 * Unlike the wrapped APIs, this checks whether it's necessary.
1236 *
1237 * @returns VBox strict status code.
1238 * @param pGVM The global (ring-0) VM structure.
1239 * @param pGVCpu The global (ring-0) per CPU structure.
1240 * @param pCtx The CPU context to import into.
1241 * @param fWhat What to import.
1242 * @param pszCaller Who is doing the importing.
1243 */
1244DECLINLINE(VBOXSTRICTRC) nemHCWinImportStateIfNeededStrict(PVMCPU pVCpu, PGVMCPU pGVCpu, PCPUMCTX pCtx,
1245 uint64_t fWhat, const char *pszCaller)
1246{
1247 if (pCtx->fExtrn & fWhat)
1248 {
1249# ifdef IN_RING0
1250 RT_NOREF(pVCpu);
1251 return nemR0WinImportStateStrict(pGVCpu->pGVM, pGVCpu, pCtx, fWhat, pszCaller);
1252# else
1253 RT_NOREF(pGVCpu, pszCaller);
1254 int rc = nemHCWinCopyStateFromHyperV(pVCpu->pVMR3, pVCpu, pCtx, NEM_WIN_CPUMCTX_EXTRN_MASK_FOR_IEM);
1255 AssertRCReturn(rc, rc);
1256# endif
1257 }
1258 return VINF_SUCCESS;
1259}
1260
1261
1262/**
1263 * Copies register state from the X64 intercept message header.
1264 *
1265 * ASSUMES no state copied yet.
1266 *
1267 * @param pVCpu The cross context per CPU structure.
1268 * @param pCtx The registe rcontext.
1269 * @param pHdr The X64 intercept message header.
1270 */
1271DECLINLINE(void) nemHCWinCopyStateFromX64Header(PVMCPU pVCpu, PCPUMCTX pCtx, HV_X64_INTERCEPT_MESSAGE_HEADER const *pHdr)
1272{
1273 Assert( (pCtx->fExtrn & (CPUMCTX_EXTRN_RIP | CPUMCTX_EXTRN_RFLAGS | CPUMCTX_EXTRN_CS | CPUMCTX_EXTRN_NEM_WIN_INHIBIT_INT))
1274 == (CPUMCTX_EXTRN_RIP | CPUMCTX_EXTRN_RFLAGS | CPUMCTX_EXTRN_CS | CPUMCTX_EXTRN_NEM_WIN_INHIBIT_INT));
1275 NEM_WIN_COPY_BACK_SEG(pCtx->cs, pHdr->CsSegment);
1276 pCtx->rip = pHdr->Rip;
1277 pCtx->rflags.u = pHdr->Rflags;
1278
1279 pVCpu->nem.s.fLastInterruptShadow = pHdr->ExecutionState.InterruptShadow;
1280 if (!pHdr->ExecutionState.InterruptShadow)
1281 {
1282 if (!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
1283 { /* likely */ }
1284 else
1285 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
1286 }
1287 else
1288 EMSetInhibitInterruptsPC(pVCpu, pHdr->Rip);
1289
1290 pCtx->fExtrn &= ~(CPUMCTX_EXTRN_RIP | CPUMCTX_EXTRN_RFLAGS | CPUMCTX_EXTRN_CS | CPUMCTX_EXTRN_NEM_WIN_INHIBIT_INT);
1291}
1292
1293
1294/**
1295 * Deals with memory intercept message.
1296 *
1297 * @returns Strict VBox status code.
1298 * @param pVM The cross context VM structure.
1299 * @param pVCpu The cross context per CPU structure.
1300 * @param pMsg The message.
1301 * @param pCtx The register context.
1302 * @param pGVCpu The global (ring-0) per CPU structure (NULL in r3).
1303 */
1304NEM_TMPL_STATIC VBOXSTRICTRC nemHCWinHandleMessageMemory(PVM pVM, PVMCPU pVCpu, HV_X64_MEMORY_INTERCEPT_MESSAGE const *pMsg,
1305 PCPUMCTX pCtx, PGVMCPU pGVCpu)
1306{
1307 Assert( pMsg->Header.InterceptAccessType == HV_INTERCEPT_ACCESS_READ
1308 || pMsg->Header.InterceptAccessType == HV_INTERCEPT_ACCESS_WRITE
1309 || pMsg->Header.InterceptAccessType == HV_INTERCEPT_ACCESS_EXECUTE);
1310 AssertMsg(pMsg->Header.InstructionLength < 0x10, ("%#x\n", pMsg->Header.InstructionLength));
1311
1312 /*
1313 * Whatever we do, we must clear pending event injection upon resume.
1314 */
1315 if (pMsg->Header.ExecutionState.InterruptionPending)
1316 pCtx->fExtrn &= ~CPUMCTX_EXTRN_NEM_WIN_EVENT_INJECT;
1317
1318#if 0 /* Experiment: 20K -> 34K exit/s. */
1319 if ( pMsg->Header.ExecutionState.EferLma
1320 && pMsg->Header.CsSegment.Long
1321 && pMsg->Header.InterceptAccessType == HV_INTERCEPT_ACCESS_WRITE)
1322 {
1323 if ( pMsg->Header.Rip - (uint64_t)0xf65a < (uint64_t)(0xf662 - 0xf65a)
1324 && pMsg->InstructionBytes[0] == 0x89
1325 && pMsg->InstructionBytes[1] == 0x03)
1326 {
1327 pCtx->rip = pMsg->Header.Rip + 2;
1328 pCtx->fExtrn &= ~CPUMCTX_EXTRN_RIP;
1329 AssertMsg(pMsg->Header.InstructionLength == 2, ("%#x\n", pMsg->Header.InstructionLength));
1330 //Log(("%RX64 msg:\n%.80Rhxd\n", pCtx->rip, pMsg));
1331 return VINF_SUCCESS;
1332 }
1333 }
1334#endif
1335
1336 /*
1337 * Ask PGM for information about the given GCPhys. We need to check if we're
1338 * out of sync first.
1339 */
1340 NEMHCWINHMACPCCSTATE State = { pMsg->Header.InterceptAccessType == HV_INTERCEPT_ACCESS_WRITE, false, false };
1341 PGMPHYSNEMPAGEINFO Info;
1342 int rc = PGMPhysNemPageInfoChecker(pVM, pVCpu, pMsg->GuestPhysicalAddress, State.fWriteAccess, &Info,
1343 nemHCWinHandleMemoryAccessPageCheckerCallback, &State);
1344 if (RT_SUCCESS(rc))
1345 {
1346 if (Info.fNemProt & ( pMsg->Header.InterceptAccessType == HV_INTERCEPT_ACCESS_WRITE
1347 ? NEM_PAGE_PROT_WRITE : NEM_PAGE_PROT_READ))
1348 {
1349 if (State.fCanResume)
1350 {
1351 Log4(("MemExit/%u: %04x:%08RX64: %RGp (=>%RHp) %s fProt=%u%s%s%s; restarting (%s)\n",
1352 pVCpu->idCpu, pMsg->Header.CsSegment.Selector, pMsg->Header.Rip,
1353 pMsg->GuestPhysicalAddress, Info.HCPhys, g_apszPageStates[Info.u2NemState], Info.fNemProt,
1354 Info.fHasHandlers ? " handlers" : "", Info.fZeroPage ? " zero-pg" : "",
1355 State.fDidSomething ? "" : " no-change", g_apszHvInterceptAccessTypes[pMsg->Header.InterceptAccessType]));
1356 return VINF_SUCCESS;
1357 }
1358 }
1359 Log4(("MemExit/%u: %04x:%08RX64: %RGp (=>%RHp) %s fProt=%u%s%s%s; emulating (%s)\n",
1360 pVCpu->idCpu, pMsg->Header.CsSegment.Selector, pMsg->Header.Rip,
1361 pMsg->GuestPhysicalAddress, Info.HCPhys, g_apszPageStates[Info.u2NemState], Info.fNemProt,
1362 Info.fHasHandlers ? " handlers" : "", Info.fZeroPage ? " zero-pg" : "",
1363 State.fDidSomething ? "" : " no-change", g_apszHvInterceptAccessTypes[pMsg->Header.InterceptAccessType]));
1364 }
1365 else
1366 Log4(("MemExit/%u: %04x:%08RX64: %RGp rc=%Rrc%s; emulating (%s)\n",
1367 pVCpu->idCpu, pMsg->Header.CsSegment.Selector, pMsg->Header.Rip, pMsg->GuestPhysicalAddress, rc,
1368 State.fDidSomething ? " modified-backing" : "", g_apszHvInterceptAccessTypes[pMsg->Header.InterceptAccessType]));
1369
1370 /*
1371 * Emulate the memory access, either access handler or special memory.
1372 */
1373 nemHCWinCopyStateFromX64Header(pVCpu, pCtx, &pMsg->Header);
1374 VBOXSTRICTRC rcStrict;
1375# ifdef IN_RING0
1376 rcStrict = nemR0WinImportStateStrict(pGVCpu->pGVM, pGVCpu, pCtx, NEM_WIN_CPUMCTX_EXTRN_MASK_FOR_IEM, "MemExit");
1377 if (rcStrict != VINF_SUCCESS)
1378 return rcStrict;
1379# else
1380 rc = nemHCWinCopyStateFromHyperV(pVM, pVCpu, pCtx, NEM_WIN_CPUMCTX_EXTRN_MASK_FOR_IEM);
1381 AssertRCReturn(rc, rc);
1382 NOREF(pGVCpu);
1383# endif
1384
1385 if (pMsg->Reserved1)
1386 Log(("MemExit/Reserved1=%#x\n", pMsg->Reserved1));
1387 if (pMsg->Header.ExecutionState.Reserved0 || pMsg->Header.ExecutionState.Reserved1)
1388 Log(("MemExit/Hdr/State: Reserved0=%#x Reserved1=%#x\n", pMsg->Header.ExecutionState.Reserved0, pMsg->Header.ExecutionState.Reserved1));
1389 //if (pMsg->InstructionByteCount > 0)
1390 // Log4(("InstructionByteCount=%#x %.16Rhxs\n", pMsg->InstructionByteCount, pMsg->InstructionBytes));
1391
1392 if (pMsg->InstructionByteCount > 0)
1393 rcStrict = IEMExecOneWithPrefetchedByPC(pVCpu, CPUMCTX2CORE(pCtx), pMsg->Header.Rip,
1394 pMsg->InstructionBytes, pMsg->InstructionByteCount);
1395 else
1396 rcStrict = IEMExecOne(pVCpu);
1397 /** @todo do we need to do anything wrt debugging here? */
1398 return rcStrict;
1399
1400}
1401
1402
1403/**
1404 * Deals with I/O port intercept message.
1405 *
1406 * @returns Strict VBox status code.
1407 * @param pVM The cross context VM structure.
1408 * @param pVCpu The cross context per CPU structure.
1409 * @param pMsg The message.
1410 * @param pCtx The register context.
1411 * @param pGVCpu The global (ring-0) per CPU structure (NULL in r3).
1412 */
1413NEM_TMPL_STATIC VBOXSTRICTRC nemHCWinHandleMessageIoPort(PVM pVM, PVMCPU pVCpu, HV_X64_IO_PORT_INTERCEPT_MESSAGE const *pMsg,
1414 PCPUMCTX pCtx, PGVMCPU pGVCpu)
1415{
1416 Assert( pMsg->AccessInfo.AccessSize == 1
1417 || pMsg->AccessInfo.AccessSize == 2
1418 || pMsg->AccessInfo.AccessSize == 4);
1419 Assert( pMsg->Header.InterceptAccessType == HV_INTERCEPT_ACCESS_READ
1420 || pMsg->Header.InterceptAccessType == HV_INTERCEPT_ACCESS_WRITE);
1421 AssertMsg(pMsg->Header.InstructionLength < 0x10, ("%#x\n", pMsg->Header.InstructionLength));
1422
1423 /*
1424 * Whatever we do, we must clear pending event injection upon resume.
1425 */
1426 if (pMsg->Header.ExecutionState.InterruptionPending)
1427 pCtx->fExtrn &= ~CPUMCTX_EXTRN_NEM_WIN_EVENT_INJECT;
1428
1429 VBOXSTRICTRC rcStrict;
1430 if (!pMsg->AccessInfo.StringOp)
1431 {
1432 /*
1433 * Simple port I/O.
1434 */
1435 static uint32_t const s_fAndMask[8] =
1436 { UINT32_MAX, UINT32_C(0xff), UINT32_C(0xffff), UINT32_MAX, UINT32_MAX, UINT32_MAX, UINT32_MAX, UINT32_MAX };
1437 uint32_t const fAndMask = s_fAndMask[pMsg->AccessInfo.AccessSize];
1438 if (pMsg->Header.InterceptAccessType == HV_INTERCEPT_ACCESS_WRITE)
1439 {
1440 rcStrict = IOMIOPortWrite(pVM, pVCpu, pMsg->PortNumber, (uint32_t)pMsg->Rax & fAndMask, pMsg->AccessInfo.AccessSize);
1441 Log4(("IOExit/%u: %04x:%08RX64: OUT %#x, %#x LB %u rcStrict=%Rrc\n",
1442 pVCpu->idCpu, pMsg->Header.CsSegment.Selector, pMsg->Header.Rip, pMsg->PortNumber,
1443 (uint32_t)pMsg->Rax & fAndMask, pMsg->AccessInfo.AccessSize, VBOXSTRICTRC_VAL(rcStrict) ));
1444 if (IOM_SUCCESS(rcStrict))
1445 {
1446 nemHCWinCopyStateFromX64Header(pVCpu, pCtx, &pMsg->Header);
1447 nemHCWinAdvanceGuestRipAndClearRF(pVCpu, pCtx, &pMsg->Header);
1448 }
1449 }
1450 else
1451 {
1452 uint32_t uValue = 0;
1453 rcStrict = IOMIOPortRead(pVM, pVCpu, pMsg->PortNumber, &uValue, pMsg->AccessInfo.AccessSize);
1454 Log4(("IOExit/%u: %04x:%08RX64: IN %#x LB %u -> %#x, rcStrict=%Rrc\n", pVCpu->idCpu, pMsg->Header.CsSegment.Selector,
1455 pMsg->Header.Rip, pMsg->PortNumber, pMsg->AccessInfo.AccessSize, uValue, VBOXSTRICTRC_VAL(rcStrict) ));
1456 if (IOM_SUCCESS(rcStrict))
1457 {
1458 if (pMsg->AccessInfo.AccessSize != 4)
1459 pCtx->rax = (pMsg->Rax & ~(uint64_t)fAndMask) | (uValue & fAndMask);
1460 else
1461 pCtx->rax = uValue;
1462 pCtx->fExtrn &= ~CPUMCTX_EXTRN_RAX;
1463 Log4(("IOExit/%u: RAX %#RX64 -> %#RX64\n", pVCpu->idCpu, pMsg->Rax, pCtx->rax));
1464 nemHCWinCopyStateFromX64Header(pVCpu, pCtx, &pMsg->Header);
1465 nemHCWinAdvanceGuestRipAndClearRF(pVCpu, pCtx, &pMsg->Header);
1466 }
1467 }
1468 }
1469 else
1470 {
1471 /*
1472 * String port I/O.
1473 */
1474 /** @todo Someone at Microsoft please explain how we can get the address mode
1475 * from the IoPortAccess.VpContext. CS.Attributes is only sufficient for
1476 * getting the default mode, it can always be overridden by a prefix. This
1477 * forces us to interpret the instruction from opcodes, which is suboptimal.
1478 * Both AMD-V and VT-x includes the address size in the exit info, at least on
1479 * CPUs that are reasonably new.
1480 *
1481 * Of course, it's possible this is an undocumented and we just need to do some
1482 * experiments to figure out how it's communicated. Alternatively, we can scan
1483 * the opcode bytes for possible evil prefixes.
1484 */
1485 nemHCWinCopyStateFromX64Header(pVCpu, pCtx, &pMsg->Header);
1486 pCtx->fExtrn &= ~( CPUMCTX_EXTRN_RAX | CPUMCTX_EXTRN_RCX | CPUMCTX_EXTRN_RDI | CPUMCTX_EXTRN_RSI
1487 | CPUMCTX_EXTRN_DS | CPUMCTX_EXTRN_ES);
1488 NEM_WIN_COPY_BACK_SEG(pCtx->ds, pMsg->DsSegment);
1489 NEM_WIN_COPY_BACK_SEG(pCtx->es, pMsg->EsSegment);
1490 pCtx->rax = pMsg->Rax;
1491 pCtx->rcx = pMsg->Rcx;
1492 pCtx->rdi = pMsg->Rdi;
1493 pCtx->rsi = pMsg->Rsi;
1494# ifdef IN_RING0
1495 rcStrict = nemR0WinImportStateStrict(pGVCpu->pGVM, pGVCpu, pCtx, NEM_WIN_CPUMCTX_EXTRN_MASK_FOR_IEM, "IOExit");
1496 if (rcStrict != VINF_SUCCESS)
1497 return rcStrict;
1498# else
1499 int rc = nemHCWinCopyStateFromHyperV(pVM, pVCpu, pCtx, NEM_WIN_CPUMCTX_EXTRN_MASK_FOR_IEM);
1500 AssertRCReturn(rc, rc);
1501 RT_NOREF(pGVCpu);
1502# endif
1503
1504 Log4(("IOExit/%u: %04x:%08RX64: %s%s %#x LB %u (emulating)\n",
1505 pVCpu->idCpu, pMsg->Header.CsSegment.Selector, pMsg->Header.Rip,
1506 pMsg->AccessInfo.RepPrefix ? "REP " : "",
1507 pMsg->Header.InterceptAccessType == HV_INTERCEPT_ACCESS_WRITE ? "OUTS" : "INS",
1508 pMsg->PortNumber, pMsg->AccessInfo.AccessSize ));
1509 rcStrict = IEMExecOne(pVCpu);
1510 }
1511 if (IOM_SUCCESS(rcStrict))
1512 {
1513 /*
1514 * Do debug checks.
1515 */
1516 if ( pMsg->Header.ExecutionState.DebugActive /** @todo Microsoft: Does DebugActive this only reflext DR7? */
1517 || (pMsg->Header.Rflags & X86_EFL_TF)
1518 || DBGFBpIsHwIoArmed(pVM) )
1519 {
1520 /** @todo Debugging. */
1521 }
1522 }
1523 return rcStrict;
1524}
1525
1526
1527/**
1528 * Deals with interrupt window message.
1529 *
1530 * @returns Strict VBox status code.
1531 * @param pVM The cross context VM structure.
1532 * @param pVCpu The cross context per CPU structure.
1533 * @param pMsg The message.
1534 * @param pCtx The register context.
1535 * @param pGVCpu The global (ring-0) per CPU structure (NULL in r3).
1536 */
1537NEM_TMPL_STATIC VBOXSTRICTRC nemHCWinHandleMessageInterruptWindow(PVM pVM, PVMCPU pVCpu,
1538 HV_X64_INTERRUPT_WINDOW_MESSAGE const *pMsg,
1539 PCPUMCTX pCtx, PGVMCPU pGVCpu)
1540{
1541 /*
1542 * Assert message sanity.
1543 */
1544 Assert( pMsg->Header.InterceptAccessType == HV_INTERCEPT_ACCESS_EXECUTE
1545 || pMsg->Header.InterceptAccessType == HV_INTERCEPT_ACCESS_READ // READ & WRITE are probably not used here
1546 || pMsg->Header.InterceptAccessType == HV_INTERCEPT_ACCESS_WRITE);
1547 AssertMsg(pMsg->Header.InstructionLength < 0x10, ("%#x\n", pMsg->Header.InstructionLength));
1548 AssertMsg(pMsg->Type == HvX64PendingInterrupt || pMsg->Type == HvX64PendingNmi, ("%#x\n", pMsg->Type));
1549
1550 /*
1551 * Just copy the state we've got and handle it in the loop for now.
1552 */
1553 nemHCWinCopyStateFromX64Header(pVCpu, pCtx, &pMsg->Header);
1554 Log4(("IntWinExit/%u: %04x:%08RX64: %u IF=%d InterruptShadow=%d\n", pVCpu->idCpu, pMsg->Header.CsSegment.Selector,
1555 pMsg->Header.Rip, pMsg->Type, RT_BOOL(pMsg->Header.Rflags & X86_EFL_IF), pMsg->Header.ExecutionState.InterruptShadow));
1556
1557 /** @todo call nemHCWinHandleInterruptFF */
1558 RT_NOREF(pVM, pGVCpu);
1559 return VINF_SUCCESS;
1560}
1561
1562
1563/**
1564 * Deals with CPUID intercept message.
1565 *
1566 * @returns Strict VBox status code.
1567 * @param pVCpu The cross context per CPU structure.
1568 * @param pMsg The message.
1569 * @param pCtx The register context.
1570 */
1571NEM_TMPL_STATIC VBOXSTRICTRC nemHCWinHandleMessageCpuId(PVMCPU pVCpu, HV_X64_CPUID_INTERCEPT_MESSAGE const *pMsg, PCPUMCTX pCtx)
1572{
1573 AssertMsg(pMsg->Header.InstructionLength < 0x10, ("%#x\n", pMsg->Header.InstructionLength));
1574
1575 /*
1576 * Soak up state and execute the instruction.
1577 *
1578 * Note! If this grows slightly more complicated, combine into an IEMExecDecodedCpuId
1579 * function and make everyone use it.
1580 */
1581 /** @todo Combine implementations into IEMExecDecodedCpuId as this will
1582 * only get weirder with nested VT-x and AMD-V support. */
1583 nemHCWinCopyStateFromX64Header(pVCpu, pCtx, &pMsg->Header);
1584
1585 /* Copy in the low register values (top is always cleared). */
1586 pCtx->rax = (uint32_t)pMsg->Rax;
1587 pCtx->rcx = (uint32_t)pMsg->Rcx;
1588 pCtx->rdx = (uint32_t)pMsg->Rdx;
1589 pCtx->rbx = (uint32_t)pMsg->Rbx;
1590 pCtx->fExtrn &= ~(CPUMCTX_EXTRN_RAX | CPUMCTX_EXTRN_RCX | CPUMCTX_EXTRN_RDX | CPUMCTX_EXTRN_RBX);
1591
1592 /* Get the correct values. */
1593 CPUMGetGuestCpuId(pVCpu, pCtx->eax, pCtx->ecx, &pCtx->eax, &pCtx->ebx, &pCtx->ecx, &pCtx->edx);
1594
1595 Log4(("CpuIdExit/%u: %04x:%08RX64: rax=%08RX64 / rcx=%08RX64 / rdx=%08RX64 / rbx=%08RX64 -> %08RX32 / %08RX32 / %08RX32 / %08RX32 (hv: %08RX64 / %08RX64 / %08RX64 / %08RX64)\n",
1596 pVCpu->idCpu, pMsg->Header.CsSegment.Selector, pMsg->Header.Rip,
1597 pMsg->Rax, pMsg->Rcx, pMsg->Rdx, pMsg->Rbx,
1598 pCtx->eax, pCtx->ecx, pCtx->edx, pCtx->ebx,
1599 pMsg->DefaultResultRax, pMsg->DefaultResultRcx, pMsg->DefaultResultRdx, pMsg->DefaultResultRbx));
1600
1601 /* Move RIP and we're done. */
1602 nemHCWinAdvanceGuestRipAndClearRF(pVCpu, pCtx, &pMsg->Header);
1603
1604 return VINF_SUCCESS;
1605}
1606
1607
1608/**
1609 * Deals with MSR intercept message.
1610 *
1611 * @returns Strict VBox status code.
1612 * @param pVCpu The cross context per CPU structure.
1613 * @param pMsg The message.
1614 * @param pCtx The register context.
1615 * @param pGVCpu The global (ring-0) per CPU structure (NULL in r3).
1616 */
1617NEM_TMPL_STATIC VBOXSTRICTRC nemHCWinHandleMessageMsr(PVMCPU pVCpu, HV_X64_MSR_INTERCEPT_MESSAGE const *pMsg,
1618 PCPUMCTX pCtx, PGVMCPU pGVCpu)
1619{
1620 /*
1621 * A wee bit of sanity first.
1622 */
1623 AssertMsg(pMsg->Header.InstructionLength < 0x10, ("%#x\n", pMsg->Header.InstructionLength));
1624 Assert( pMsg->Header.InterceptAccessType == HV_INTERCEPT_ACCESS_READ
1625 || pMsg->Header.InterceptAccessType == HV_INTERCEPT_ACCESS_WRITE);
1626
1627 /*
1628 * Check CPL as that's common to both RDMSR and WRMSR.
1629 */
1630 VBOXSTRICTRC rcStrict;
1631 if (pMsg->Header.CsSegment.DescriptorPrivilegeLevel == 0)
1632 {
1633 /*
1634 * Handle writes.
1635 */
1636 if (pMsg->Header.InterceptAccessType == HV_INTERCEPT_ACCESS_WRITE)
1637 {
1638 rcStrict = CPUMSetGuestMsr(pVCpu, pMsg->MsrNummber, RT_MAKE_U64((uint32_t)pMsg->Rax, (uint32_t)pMsg->Rdx));
1639 Log4(("MsrExit/%u: %04x:%08RX64: WRMSR %08x, %08x:%08x -> %Rrc\n",
1640 pVCpu->idCpu, pMsg->Header.CsSegment.Selector, pMsg->Header.Rip,
1641 pMsg->MsrNummber, (uint32_t)pMsg->Rax, (uint32_t)pMsg->Rdx, VBOXSTRICTRC_VAL(rcStrict) ));
1642 if (rcStrict == VINF_SUCCESS)
1643 {
1644 nemHCWinCopyStateFromX64Header(pVCpu, pCtx, &pMsg->Header);
1645 nemHCWinAdvanceGuestRipAndClearRF(pVCpu, pCtx, &pMsg->Header);
1646 return VINF_SUCCESS;
1647 }
1648#ifndef IN_RING3
1649 /* move to ring-3 and handle the trap/whatever there, as we want to LogRel this. */
1650 if (rcStrict == VERR_CPUM_RAISE_GP_0)
1651 rcStrict = VINF_CPUM_R3_MSR_WRITE;
1652 return rcStrict;
1653#else
1654 LogRel(("MsrExit/%u: %04x:%08RX64: WRMSR %08x, %08x:%08x -> %Rrc!\n",
1655 pVCpu->idCpu, pMsg->Header.CsSegment.Selector, pMsg->Header.Rip,
1656 pMsg->MsrNummber, (uint32_t)pMsg->Rax, (uint32_t)pMsg->Rdx, VBOXSTRICTRC_VAL(rcStrict) ));
1657#endif
1658 }
1659 /*
1660 * Handle reads.
1661 */
1662 else
1663 {
1664 uint64_t uValue = 0;
1665 rcStrict = CPUMQueryGuestMsr(pVCpu, pMsg->MsrNummber, &uValue);
1666 Log4(("MsrExit/%u: %04x:%08RX64: RDMSR %08x -> %08RX64 / %Rrc\n", pVCpu->idCpu, pMsg->Header.CsSegment.Selector,
1667 pMsg->Header.Rip, pMsg->MsrNummber, uValue, VBOXSTRICTRC_VAL(rcStrict) ));
1668 if (rcStrict == VINF_SUCCESS)
1669 {
1670 nemHCWinCopyStateFromX64Header(pVCpu, pCtx, &pMsg->Header);
1671 nemHCWinAdvanceGuestRipAndClearRF(pVCpu, pCtx, &pMsg->Header);
1672 return VINF_SUCCESS;
1673 }
1674#ifndef IN_RING3
1675 /* move to ring-3 and handle the trap/whatever there, as we want to LogRel this. */
1676 if (rcStrict == VERR_CPUM_RAISE_GP_0)
1677 rcStrict = VINF_CPUM_R3_MSR_READ;
1678 return rcStrict;
1679#else
1680 LogRel(("MsrExit/%u: %04x:%08RX64: RDMSR %08x -> %08RX64 / %Rrc\n", pVCpu->idCpu, pMsg->Header.CsSegment.Selector,
1681 pMsg->Header.Rip, pMsg->MsrNummber, uValue, VBOXSTRICTRC_VAL(rcStrict) ));
1682#endif
1683 }
1684 }
1685 else if (pMsg->Header.InterceptAccessType == HV_INTERCEPT_ACCESS_WRITE)
1686 Log4(("MsrExit/%u: CPL %u -> #GP(0); WRMSR %08x, %08x:%08x\n", pVCpu->idCpu,
1687 pMsg->Header.CsSegment.DescriptorPrivilegeLevel, pMsg->MsrNummber, (uint32_t)pMsg->Rax, (uint32_t)pMsg->Rdx ));
1688 else
1689 Log4(("MsrExit/%u: CPL %u -> #GP(0); RDMSR %08x\n",
1690 pVCpu->idCpu, pMsg->Header.CsSegment.DescriptorPrivilegeLevel, pMsg->MsrNummber));
1691
1692 /*
1693 * If we get down here, we're supposed to #GP(0).
1694 */
1695 rcStrict = nemHCWinImportStateIfNeededStrict(pVCpu, pGVCpu, pCtx, NEM_WIN_CPUMCTX_EXTRN_MASK_FOR_IEM, "NMI");
1696 if (rcStrict == VINF_SUCCESS)
1697 {
1698 rcStrict = IEMInjectTrap(pVCpu, X86_XCPT_GP, TRPM_TRAP, 0, 0, 0);
1699 if (rcStrict == VINF_IEM_RAISED_XCPT)
1700 rcStrict = VINF_SUCCESS;
1701 else if (rcStrict != VINF_SUCCESS)
1702 Log4(("MsrExit/%u: Injecting #GP(0) failed: %Rrc\n", VBOXSTRICTRC_VAL(rcStrict) ));
1703 }
1704 return rcStrict;
1705}
1706
1707
1708/**
1709 * Deals with unrecoverable exception (triple fault).
1710 *
1711 * @returns Strict VBox status code.
1712 * @param pVCpu The cross context per CPU structure.
1713 * @param pMsgHdr The message header.
1714 * @param pCtx The register context.
1715 */
1716NEM_TMPL_STATIC VBOXSTRICTRC nemHCWinHandleMessageUnrecoverableException(PVMCPU pVCpu,
1717 HV_X64_INTERCEPT_MESSAGE_HEADER const *pMsgHdr,
1718 PCPUMCTX pCtx)
1719{
1720 /*
1721 * Assert message sanity.
1722 */
1723 //Assert( pMsgHdr->InterceptAccessType == HV_INTERCEPT_ACCESS_EXECUTE
1724 // || pMsgHdr->InterceptAccessType == HV_INTERCEPT_ACCESS_READ // READ & WRITE are probably not used here
1725 // || pMsgHdr->InterceptAccessType == HV_INTERCEPT_ACCESS_WRITE);
1726 AssertMsg(pMsgHdr->InstructionLength < 0x10, ("%#x\n", pMsgHdr->InstructionLength));
1727
1728 /*
1729 * Just copy the state we've got and handle it in the loop for now.
1730 */
1731 nemHCWinCopyStateFromX64Header(pVCpu, pCtx, pMsgHdr);
1732 Log(("TripleExit/%u: %04x:%08RX64: RFL=%#RX64 -> VINF_EM_TRIPLE_FAULT\n",
1733 pVCpu->idCpu, pMsgHdr->CsSegment.Selector, pMsgHdr->Rip, pMsgHdr->Rflags));
1734 return VINF_EM_TRIPLE_FAULT;
1735}
1736
1737
1738/**
1739 * Handles messages (VM exits).
1740 *
1741 * @returns Strict VBox status code.
1742 * @param pVM The cross context VM structure.
1743 * @param pVCpu The cross context per CPU structure.
1744 * @param pMappingHeader The message slot mapping.
1745 * @param pCtx The register context.
1746 * @param pGVCpu The global (ring-0) per CPU structure (NULL in r3).
1747 */
1748NEM_TMPL_STATIC VBOXSTRICTRC nemHCWinHandleMessage(PVM pVM, PVMCPU pVCpu, VID_MESSAGE_MAPPING_HEADER volatile *pMappingHeader,
1749 PCPUMCTX pCtx, PGVMCPU pGVCpu)
1750{
1751 if (pMappingHeader->enmVidMsgType == VidMessageHypervisorMessage)
1752 {
1753 AssertMsg(pMappingHeader->cbMessage == HV_MESSAGE_SIZE, ("%#x\n", pMappingHeader->cbMessage));
1754 HV_MESSAGE const *pMsg = (HV_MESSAGE const *)(pMappingHeader + 1);
1755 switch (pMsg->Header.MessageType)
1756 {
1757 case HvMessageTypeUnmappedGpa:
1758 Assert(pMsg->Header.PayloadSize == RT_UOFFSETOF(HV_X64_MEMORY_INTERCEPT_MESSAGE, DsSegment));
1759 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitMemUnmapped);
1760 return nemHCWinHandleMessageMemory(pVM, pVCpu, &pMsg->X64MemoryIntercept, pCtx, pGVCpu);
1761
1762 case HvMessageTypeGpaIntercept:
1763 Assert(pMsg->Header.PayloadSize == RT_UOFFSETOF(HV_X64_MEMORY_INTERCEPT_MESSAGE, DsSegment));
1764 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitMemIntercept);
1765 return nemHCWinHandleMessageMemory(pVM, pVCpu, &pMsg->X64MemoryIntercept, pCtx, pGVCpu);
1766
1767 case HvMessageTypeX64IoPortIntercept:
1768 Assert(pMsg->Header.PayloadSize == sizeof(pMsg->X64IoPortIntercept));
1769 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitPortIo);
1770 return nemHCWinHandleMessageIoPort(pVM, pVCpu, &pMsg->X64IoPortIntercept, pCtx, pGVCpu);
1771
1772 case HvMessageTypeX64Halt:
1773 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitHalt);
1774 Log4(("HaltExit\n"));
1775 return VINF_EM_HALT;
1776
1777 case HvMessageTypeX64InterruptWindow:
1778 Assert(pMsg->Header.PayloadSize == sizeof(pMsg->X64InterruptWindow));
1779 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitInterruptWindow);
1780 return nemHCWinHandleMessageInterruptWindow(pVM, pVCpu, &pMsg->X64InterruptWindow, pCtx, pGVCpu);
1781
1782 case HvMessageTypeX64CpuidIntercept:
1783 Assert(pMsg->Header.PayloadSize == sizeof(pMsg->X64CpuIdIntercept));
1784 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitCpuId);
1785 return nemHCWinHandleMessageCpuId(pVCpu, &pMsg->X64CpuIdIntercept, pCtx);
1786
1787 case HvMessageTypeX64MsrIntercept:
1788 Assert(pMsg->Header.PayloadSize == sizeof(pMsg->X64MsrIntercept));
1789 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitMsr);
1790 return nemHCWinHandleMessageMsr(pVCpu, &pMsg->X64MsrIntercept, pCtx, pGVCpu);
1791
1792 case HvMessageTypeUnrecoverableException:
1793 Assert(pMsg->Header.PayloadSize == sizeof(pMsg->X64InterceptHeader));
1794 return nemHCWinHandleMessageUnrecoverableException(pVCpu, &pMsg->X64InterceptHeader, pCtx);
1795
1796 case HvMessageTypeInvalidVpRegisterValue:
1797 case HvMessageTypeUnsupportedFeature:
1798 case HvMessageTypeTlbPageSizeMismatch:
1799 LogRel(("Unimplemented msg:\n%.*Rhxd\n", (int)sizeof(*pMsg), pMsg));
1800 AssertLogRelMsgFailedReturn(("Message type %#x not implemented!\n%.32Rhxd\n", pMsg->Header.MessageType, pMsg),
1801 VERR_INTERNAL_ERROR_2);
1802
1803 case HvMessageTypeX64ExceptionIntercept:
1804 case HvMessageTypeX64ApicEoi:
1805 case HvMessageTypeX64LegacyFpError:
1806 case HvMessageTypeX64RegisterIntercept:
1807 case HvMessageTypeApicEoi:
1808 case HvMessageTypeFerrAsserted:
1809 case HvMessageTypeEventLogBufferComplete:
1810 case HvMessageTimerExpired:
1811 LogRel(("Unexpected msg:\n%.*Rhxd\n", (int)sizeof(*pMsg), pMsg));
1812 AssertLogRelMsgFailedReturn(("Unexpected message on CPU #%u: %#x\n", pVCpu->idCpu, pMsg->Header.MessageType),
1813 VERR_INTERNAL_ERROR_2);
1814
1815 default:
1816 LogRel(("Unknown msg:\n%.*Rhxd\n", (int)sizeof(*pMsg), pMsg));
1817 AssertLogRelMsgFailedReturn(("Unknown message on CPU #%u: %#x\n", pVCpu->idCpu, pMsg->Header.MessageType),
1818 VERR_INTERNAL_ERROR_2);
1819 }
1820 }
1821 else
1822 AssertLogRelMsgFailedReturn(("Unexpected VID message type on CPU #%u: %#x LB %u\n",
1823 pVCpu->idCpu, pMappingHeader->enmVidMsgType, pMappingHeader->cbMessage),
1824 VERR_INTERNAL_ERROR_3);
1825}
1826
1827
1828/**
1829 * Worker for nemHCWinRunGC that stops the execution on the way out.
1830 *
1831 * The CPU was running the last time we checked, no there are no messages that
1832 * needs being marked handled/whatever. Caller checks this.
1833 *
1834 * @returns rcStrict on success, error status on failure.
1835 * @param pVM The cross context VM structure.
1836 * @param pVCpu The cross context per CPU structure.
1837 * @param rcStrict The nemHCWinRunGC return status. This is a little
1838 * bit unnecessary, except in internal error cases,
1839 * since we won't need to stop the CPU if we took an
1840 * exit.
1841 * @param pMappingHeader The message slot mapping.
1842 * @param pGVM The global (ring-0) VM structure (NULL in r3).
1843 * @param pGVCpu The global (ring-0) per CPU structure (NULL in r3).
1844 */
1845NEM_TMPL_STATIC VBOXSTRICTRC nemHCWinStopCpu(PVM pVM, PVMCPU pVCpu, VBOXSTRICTRC rcStrict,
1846 VID_MESSAGE_MAPPING_HEADER volatile *pMappingHeader,
1847 PGVM pGVM, PGVMCPU pGVCpu)
1848{
1849 /*
1850 * Try stopping the processor. If we're lucky we manage to do this before it
1851 * does another VM exit.
1852 */
1853# ifdef IN_RING0
1854 pVCpu->nem.s.uIoCtlBuf.idCpu = pGVCpu->idCpu;
1855 NTSTATUS rcNt = nemR0NtPerformIoControl(pGVM, pGVM->nem.s.IoCtlStopVirtualProcessor.uFunction,
1856 &pVCpu->nem.s.uIoCtlBuf.idCpu, sizeof(pVCpu->nem.s.uIoCtlBuf.idCpu),
1857 NULL, 0);
1858 if (NT_SUCCESS(rcNt))
1859 {
1860 Log8(("nemHCWinStopCpu: Stopping CPU succeeded (cpu status %u)\n", nemHCWinCpuGetRunningStatus(pVCpu) ));
1861 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatStopCpuSuccess);
1862 return rcStrict;
1863 }
1864# else
1865 BOOL fRet = VidStopVirtualProcessor(pVM->nem.s.hPartitionDevice, pVCpu->idCpu);
1866 if (fRet)
1867 {
1868 Log8(("nemHCWinStopCpu: Stopping CPU succeeded (cpu status %u)\n", nemHCWinCpuGetRunningStatus(pVCpu) ));
1869 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatStopCpuSuccess);
1870 return rcStrict;
1871 }
1872 RT_NOREF(pGVM, pGVCpu);
1873# endif
1874
1875 /*
1876 * Dang. The CPU stopped by itself and we got a couple of message to deal with.
1877 */
1878# ifdef IN_RING0
1879 AssertLogRelMsgReturn(rcNt == ERROR_VID_STOP_PENDING, ("rcNt=%#x\n", rcNt),
1880 RT_SUCCESS(rcStrict) ? VERR_INTERNAL_ERROR_3 : rcStrict);
1881# else
1882 DWORD dwErr = RTNtLastErrorValue();
1883 AssertLogRelMsgReturn(dwErr == ERROR_VID_STOP_PENDING, ("dwErr=%#u (%#x)\n", dwErr, dwErr),
1884 RT_SUCCESS(rcStrict) ? VERR_INTERNAL_ERROR_3 : rcStrict);
1885# endif
1886 Log8(("nemHCWinStopCpu: Stopping CPU pending...\n"));
1887 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatStopCpuPending);
1888
1889 /*
1890 * First message: Exit or similar.
1891 * Note! We can safely ASSUME that rcStrict isn't an important information one.
1892 */
1893# ifdef IN_RING0
1894 pVCpu->nem.s.uIoCtlBuf.MsgSlotHandleAndGetNext.iCpu = pGVCpu->idCpu;
1895 pVCpu->nem.s.uIoCtlBuf.MsgSlotHandleAndGetNext.fFlags = VID_MSHAGN_F_GET_NEXT_MESSAGE;
1896 pVCpu->nem.s.uIoCtlBuf.MsgSlotHandleAndGetNext.cMillies = 30000; /*ms*/
1897 rcNt = nemR0NtPerformIoControl(pGVM, pGVM->nem.s.IoCtlMessageSlotHandleAndGetNext.uFunction,
1898 &pVCpu->nem.s.uIoCtlBuf.MsgSlotHandleAndGetNext,
1899 sizeof(pVCpu->nem.s.uIoCtlBuf.MsgSlotHandleAndGetNext),
1900 NULL, 0);
1901 AssertLogRelMsgReturn(NT_SUCCESS(rcNt), ("1st VidMessageSlotHandleAndGetNext after ERROR_VID_STOP_PENDING failed: %#x\n", rcNt),
1902 RT_SUCCESS(rcStrict) ? VERR_INTERNAL_ERROR_3 : rcStrict);
1903# else
1904 BOOL fWait = g_pfnVidMessageSlotHandleAndGetNext(pVM->nem.s.hPartitionDevice, pVCpu->idCpu,
1905 VID_MSHAGN_F_GET_NEXT_MESSAGE, 30000 /*ms*/);
1906 AssertLogRelMsgReturn(fWait, ("1st VidMessageSlotHandleAndGetNext after ERROR_VID_STOP_PENDING failed: %u\n", RTNtLastErrorValue()),
1907 RT_SUCCESS(rcStrict) ? VERR_INTERNAL_ERROR_3 : rcStrict);
1908# endif
1909
1910 /* It should be a hypervisor message and definitely not a stop request completed message. */
1911 VID_MESSAGE_TYPE enmVidMsgType = pMappingHeader->enmVidMsgType;
1912 AssertLogRelMsgReturn(enmVidMsgType != VidMessageStopRequestComplete,
1913 ("Unexpected 1st message following ERROR_VID_STOP_PENDING: %#x LB %#x\n",
1914 enmVidMsgType, pMappingHeader->cbMessage),
1915 RT_SUCCESS(rcStrict) ? VERR_INTERNAL_ERROR_3 : rcStrict);
1916
1917 VBOXSTRICTRC rcStrict2 = nemHCWinHandleMessage(pVM, pVCpu, pMappingHeader, CPUMQueryGuestCtxPtr(pVCpu), pGVCpu);
1918 if (rcStrict2 != VINF_SUCCESS && RT_SUCCESS(rcStrict))
1919 rcStrict = rcStrict2;
1920
1921 /*
1922 * Mark it as handled and get the stop request completed message, then mark
1923 * that as handled too. CPU is back into fully stopped stated then.
1924 */
1925# ifdef IN_RING0
1926 pVCpu->nem.s.uIoCtlBuf.MsgSlotHandleAndGetNext.iCpu = pGVCpu->idCpu;
1927 pVCpu->nem.s.uIoCtlBuf.MsgSlotHandleAndGetNext.fFlags = VID_MSHAGN_F_HANDLE_MESSAGE | VID_MSHAGN_F_GET_NEXT_MESSAGE;
1928 pVCpu->nem.s.uIoCtlBuf.MsgSlotHandleAndGetNext.cMillies = 30000; /*ms*/
1929 rcNt = nemR0NtPerformIoControl(pGVM, pGVM->nem.s.IoCtlMessageSlotHandleAndGetNext.uFunction,
1930 &pVCpu->nem.s.uIoCtlBuf.MsgSlotHandleAndGetNext,
1931 sizeof(pVCpu->nem.s.uIoCtlBuf.MsgSlotHandleAndGetNext),
1932 NULL, 0);
1933 AssertLogRelMsgReturn(NT_SUCCESS(rcNt), ("2st VidMessageSlotHandleAndGetNext after ERROR_VID_STOP_PENDING failed: %#x\n", rcNt),
1934 RT_SUCCESS(rcStrict) ? VERR_INTERNAL_ERROR_3 : rcStrict);
1935# else
1936 fWait = g_pfnVidMessageSlotHandleAndGetNext(pVM->nem.s.hPartitionDevice, pVCpu->idCpu,
1937 VID_MSHAGN_F_HANDLE_MESSAGE | VID_MSHAGN_F_GET_NEXT_MESSAGE, 30000 /*ms*/);
1938 AssertLogRelMsgReturn(fWait, ("2nd VidMessageSlotHandleAndGetNext after ERROR_VID_STOP_PENDING failed: %u\n", RTNtLastErrorValue()),
1939 RT_SUCCESS(rcStrict) ? VERR_INTERNAL_ERROR_3 : rcStrict);
1940# endif
1941
1942 /* It should be a stop request completed message. */
1943 enmVidMsgType = pMappingHeader->enmVidMsgType;
1944 AssertLogRelMsgReturn(enmVidMsgType == VidMessageStopRequestComplete,
1945 ("Unexpected 2nd message following ERROR_VID_STOP_PENDING: %#x LB %#x\n",
1946 enmVidMsgType, pMappingHeader->cbMessage),
1947 RT_SUCCESS(rcStrict) ? VERR_INTERNAL_ERROR_3 : rcStrict);
1948
1949 /* Mark this as handled. */
1950# ifdef IN_RING0
1951 pVCpu->nem.s.uIoCtlBuf.MsgSlotHandleAndGetNext.iCpu = pGVCpu->idCpu;
1952 pVCpu->nem.s.uIoCtlBuf.MsgSlotHandleAndGetNext.fFlags = VID_MSHAGN_F_HANDLE_MESSAGE;
1953 pVCpu->nem.s.uIoCtlBuf.MsgSlotHandleAndGetNext.cMillies = 30000; /*ms*/
1954 rcNt = nemR0NtPerformIoControl(pGVM, pGVM->nem.s.IoCtlMessageSlotHandleAndGetNext.uFunction,
1955 &pVCpu->nem.s.uIoCtlBuf.MsgSlotHandleAndGetNext,
1956 sizeof(pVCpu->nem.s.uIoCtlBuf.MsgSlotHandleAndGetNext),
1957 NULL, 0);
1958 AssertLogRelMsgReturn(NT_SUCCESS(rcNt), ("3rd VidMessageSlotHandleAndGetNext after ERROR_VID_STOP_PENDING failed: %#x\n", rcNt),
1959 RT_SUCCESS(rcStrict) ? VERR_INTERNAL_ERROR_3 : rcStrict);
1960# else
1961 fWait = g_pfnVidMessageSlotHandleAndGetNext(pVM->nem.s.hPartitionDevice, pVCpu->idCpu, VID_MSHAGN_F_HANDLE_MESSAGE, 30000 /*ms*/);
1962 AssertLogRelMsgReturn(fWait, ("3rd VidMessageSlotHandleAndGetNext after ERROR_VID_STOP_PENDING failed: %u\n", RTNtLastErrorValue()),
1963 RT_SUCCESS(rcStrict) ? VERR_INTERNAL_ERROR_3 : rcStrict);
1964# endif
1965 Log8(("nemHCWinStopCpu: Stopped the CPU (rcStrict=%Rrc)\n", VBOXSTRICTRC_VAL(rcStrict) ));
1966 return rcStrict;
1967}
1968
1969
1970/**
1971 * Deals with pending interrupt related force flags, may inject interrupt.
1972 *
1973 * @returns VBox strict status code.
1974 * @param pVM The cross context VM structure.
1975 * @param pVCpu The cross context per CPU structure.
1976 * @param pGVCpu The global (ring-0) per CPU structure.
1977 * @param pCtx The register context.
1978 * @param pfInterruptWindows Where to return interrupt window flags.
1979 */
1980NEM_TMPL_STATIC VBOXSTRICTRC nemHCWinHandleInterruptFF(PVM pVM, PVMCPU pVCpu, PGVMCPU pGVCpu, PCPUMCTX pCtx, uint8_t *pfInterruptWindows)
1981{
1982 Assert(!TRPMHasTrap(pVCpu));
1983 RT_NOREF_PV(pVM);
1984
1985 /*
1986 * First update APIC.
1987 */
1988 if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_UPDATE_APIC))
1989 {
1990 APICUpdatePendingInterrupts(pVCpu);
1991 if (!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC
1992 | VMCPU_FF_INTERRUPT_NMI | VMCPU_FF_INTERRUPT_SMI))
1993 return VINF_SUCCESS;
1994 }
1995
1996 /*
1997 * We don't currently implement SMIs.
1998 */
1999 AssertReturn(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_SMI), VINF_NEM_IPE_0);
2000
2001 /*
2002 * Check if we've got the minimum of state required for deciding whether we
2003 * can inject interrupts and NMIs. If we don't have it, get all we might require
2004 * for injection via IEM.
2005 */
2006 bool const fPendingNmi = VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_NMI);
2007 uint64_t fNeedExtrn = CPUMCTX_EXTRN_NEM_WIN_INHIBIT_INT | CPUMCTX_EXTRN_RIP | CPUMCTX_EXTRN_RFLAGS
2008 | (fPendingNmi ? CPUMCTX_EXTRN_NEM_WIN_INHIBIT_NMI : 0);
2009 if (pCtx->fExtrn & fNeedExtrn)
2010 {
2011 VBOXSTRICTRC rcStrict = nemHCWinImportStateIfNeededStrict(pVCpu, pGVCpu, pCtx, NEM_WIN_CPUMCTX_EXTRN_MASK_FOR_IEM, "IntFF");
2012 if (rcStrict != VINF_SUCCESS)
2013 return rcStrict;
2014 }
2015 bool const fInhibitInterrupts = VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
2016 && EMGetInhibitInterruptsPC(pVCpu) == pCtx->rip;
2017
2018 /*
2019 * NMI? Try deliver it first.
2020 */
2021 if (fPendingNmi)
2022 {
2023 if ( !fInhibitInterrupts
2024 && !VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS))
2025 {
2026 VBOXSTRICTRC rcStrict = nemHCWinImportStateIfNeededStrict(pVCpu, pGVCpu, pCtx, NEM_WIN_CPUMCTX_EXTRN_MASK_FOR_IEM, "NMI");
2027 if (rcStrict == VINF_SUCCESS)
2028 {
2029 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI);
2030 rcStrict = IEMInjectTrap(pVCpu, X86_XCPT_NMI, TRPM_HARDWARE_INT, 0, 0, 0);
2031 Log8(("Injected NMI on %u (%d)\n", pVCpu->idCpu, VBOXSTRICTRC_VAL(rcStrict) ));
2032 }
2033 return rcStrict;
2034 }
2035 *pfInterruptWindows |= NEM_WIN_INTW_F_NMI;
2036 Log8(("NMI window pending on %u\n", pVCpu->idCpu));
2037 }
2038
2039 /*
2040 * APIC or PIC interrupt?
2041 */
2042 if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC))
2043 {
2044 if ( !fInhibitInterrupts
2045 && pCtx->rflags.Bits.u1IF)
2046 {
2047 VBOXSTRICTRC rcStrict = nemHCWinImportStateIfNeededStrict(pVCpu, pGVCpu, pCtx, NEM_WIN_CPUMCTX_EXTRN_MASK_FOR_IEM, "NMI");
2048 if (rcStrict == VINF_SUCCESS)
2049 {
2050 uint8_t bInterrupt;
2051 int rc = PDMGetInterrupt(pVCpu, &bInterrupt);
2052 if (RT_SUCCESS(rc))
2053 {
2054 rcStrict = IEMInjectTrap(pVCpu, bInterrupt, TRPM_HARDWARE_INT, 0, 0, 0);
2055 Log8(("Injected interrupt %#x on %u (%d)\n", bInterrupt, pVCpu->idCpu, VBOXSTRICTRC_VAL(rcStrict) ));
2056 }
2057 else if (rc == VERR_APIC_INTR_MASKED_BY_TPR)
2058 {
2059 *pfInterruptWindows |= (bInterrupt >> 4 /*??*/) << NEM_WIN_INTW_F_PRIO_SHIFT;
2060 Log8(("VERR_APIC_INTR_MASKED_BY_TPR: *pfInterruptWindows=%#x\n", *pfInterruptWindows));
2061 }
2062 else
2063 Log8(("PDMGetInterrupt failed -> %d\n", rc));
2064 }
2065 return rcStrict;
2066 }
2067 *pfInterruptWindows |= NEM_WIN_INTW_F_REGULAR;
2068 Log8(("Interrupt window pending on %u\n", pVCpu->idCpu));
2069 }
2070
2071 return VINF_SUCCESS;
2072}
2073
2074
2075NEM_TMPL_STATIC VBOXSTRICTRC nemHCWinRunGC(PVM pVM, PVMCPU pVCpu, PGVM pGVM, PGVMCPU pGVCpu)
2076{
2077 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
2078 LogFlow(("NEM/%u: %04x:%08RX64 efl=%#08RX64 <=\n", pVCpu->idCpu, pCtx->cs.Sel, pCtx->rip, pCtx->rflags));
2079# ifdef LOG_ENABLED
2080 if (LogIs3Enabled())
2081 nemHCWinLogState(pVM, pVCpu);
2082# endif
2083
2084 /*
2085 * Try switch to NEM runloop state.
2086 */
2087 if (VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC_NEM, VMCPUSTATE_STARTED))
2088 { /* likely */ }
2089 else
2090 {
2091 VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC_NEM, VMCPUSTATE_STARTED_EXEC_NEM_CANCELED);
2092 LogFlow(("NEM/%u: returning immediately because canceled\n", pVCpu->idCpu));
2093 return VINF_SUCCESS;
2094 }
2095
2096 /*
2097 * The run loop.
2098 *
2099 * Current approach to state updating to use the sledgehammer and sync
2100 * everything every time. This will be optimized later.
2101 */
2102 VID_MESSAGE_MAPPING_HEADER volatile *pMappingHeader = (VID_MESSAGE_MAPPING_HEADER volatile *)pVCpu->nem.s.pvMsgSlotMapping;
2103 uint32_t cMillies = 5000; /** @todo lower this later... */
2104 const bool fSingleStepping = DBGFIsStepping(pVCpu);
2105// const uint32_t fCheckVmFFs = !fSingleStepping ? VM_FF_HP_R0_PRE_HM_MASK
2106// : VM_FF_HP_R0_PRE_HM_STEP_MASK;
2107// const uint32_t fCheckCpuFFs = !fSingleStepping ? VMCPU_FF_HP_R0_PRE_HM_MASK : VMCPU_FF_HP_R0_PRE_HM_STEP_MASK;
2108 VBOXSTRICTRC rcStrict = VINF_SUCCESS;
2109 for (unsigned iLoop = 0;; iLoop++)
2110 {
2111 /*
2112 * Pending interrupts or such? Need to check and deal with this prior
2113 * to the state syncing.
2114 */
2115 pVCpu->nem.s.fDesiredInterruptWindows = 0;
2116 if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_UPDATE_APIC | VMCPU_FF_INTERRUPT_PIC
2117 | VMCPU_FF_INTERRUPT_NMI | VMCPU_FF_INTERRUPT_SMI))
2118 {
2119 /* Make sure the CPU isn't executing. */
2120 if (pVCpu->nem.s.fHandleAndGetFlags == VID_MSHAGN_F_GET_NEXT_MESSAGE)
2121 {
2122 pVCpu->nem.s.fHandleAndGetFlags = 0;
2123 rcStrict = nemHCWinStopCpu(pVM, pVCpu, rcStrict, pMappingHeader, pGVM, pGVCpu);
2124 if (rcStrict == VINF_SUCCESS)
2125 { /* likely */ }
2126 else
2127 {
2128 LogFlow(("NEM/%u: breaking: nemHCWinStopCpu -> %Rrc\n", pVCpu->idCpu, VBOXSTRICTRC_VAL(rcStrict) ));
2129 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatBreakOnStatus);
2130 break;
2131 }
2132 }
2133
2134 /* Try inject interrupt. */
2135 rcStrict = nemHCWinHandleInterruptFF(pVM, pVCpu, pGVCpu, pCtx, &pVCpu->nem.s.fDesiredInterruptWindows);
2136 if (rcStrict == VINF_SUCCESS)
2137 { /* likely */ }
2138 else
2139 {
2140 LogFlow(("NEM/%u: breaking: nemHCWinHandleInterruptFF -> %Rrc\n", pVCpu->idCpu, VBOXSTRICTRC_VAL(rcStrict) ));
2141 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatBreakOnStatus);
2142 break;
2143 }
2144 }
2145
2146 /*
2147 * Ensure that hyper-V has the whole state.
2148 * (We always update the interrupt windows settings when active as hyper-V seems
2149 * to forget about it after an exit.)
2150 */
2151 if ( (pCtx->fExtrn & (CPUMCTX_EXTRN_ALL | CPUMCTX_EXTRN_NEM_WIN_MASK))
2152 != (CPUMCTX_EXTRN_ALL | CPUMCTX_EXTRN_NEM_WIN_MASK)
2153 || pVCpu->nem.s.fDesiredInterruptWindows
2154 || pVCpu->nem.s.fCurrentInterruptWindows != pVCpu->nem.s.fDesiredInterruptWindows)
2155 {
2156 Assert(pVCpu->nem.s.fHandleAndGetFlags != VID_MSHAGN_F_GET_NEXT_MESSAGE /* not running */);
2157# ifdef IN_RING0
2158 int rc2 = nemR0WinExportState(pGVM, pGVCpu, pCtx);
2159# else
2160 int rc2 = nemHCWinCopyStateToHyperV(pVM, pVCpu, pCtx);
2161 RT_NOREF(pGVM, pGVCpu);
2162# endif
2163 AssertRCReturn(rc2, rc2);
2164 }
2165
2166 /*
2167 * Run a bit.
2168 */
2169 if ( !VM_FF_IS_PENDING(pVM, VM_FF_EMT_RENDEZVOUS | VM_FF_TM_VIRTUAL_SYNC)
2170 && !VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
2171 {
2172 if (pVCpu->nem.s.fHandleAndGetFlags)
2173 { /* Very likely that the CPU does NOT need starting (pending msg, running). */ }
2174 else
2175 {
2176# ifdef IN_RING0
2177 pVCpu->nem.s.uIoCtlBuf.idCpu = pGVCpu->idCpu;
2178 NTSTATUS rcNt = nemR0NtPerformIoControl(pGVM, pGVM->nem.s.IoCtlStartVirtualProcessor.uFunction,
2179 &pVCpu->nem.s.uIoCtlBuf.idCpu, sizeof(pVCpu->nem.s.uIoCtlBuf.idCpu),
2180 NULL, 0);
2181 LogFlow(("NEM/%u: IoCtlStartVirtualProcessor -> %#x\n", pVCpu->idCpu, rcNt));
2182 AssertLogRelMsgReturn(NT_SUCCESS(rcNt), ("VidStartVirtualProcessor failed for CPU #%u: %#x\n", pGVCpu->idCpu, rcNt),
2183 VERR_INTERNAL_ERROR_3);
2184# else
2185 AssertLogRelMsgReturn(g_pfnVidStartVirtualProcessor(pVM->nem.s.hPartitionDevice, pVCpu->idCpu),
2186 ("VidStartVirtualProcessor failed for CPU #%u: %u (%#x, rcNt=%#x)\n",
2187 pVCpu->idCpu, RTNtLastErrorValue(), RTNtLastErrorValue(), RTNtLastStatusValue()),
2188 VERR_INTERNAL_ERROR_3);
2189# endif
2190 pVCpu->nem.s.fHandleAndGetFlags = VID_MSHAGN_F_GET_NEXT_MESSAGE;
2191 }
2192
2193 if (VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC_NEM_WAIT, VMCPUSTATE_STARTED_EXEC_NEM))
2194 {
2195# ifdef IN_RING0
2196 pVCpu->nem.s.uIoCtlBuf.MsgSlotHandleAndGetNext.iCpu = pGVCpu->idCpu;
2197 pVCpu->nem.s.uIoCtlBuf.MsgSlotHandleAndGetNext.fFlags = pVCpu->nem.s.fHandleAndGetFlags;
2198 pVCpu->nem.s.uIoCtlBuf.MsgSlotHandleAndGetNext.cMillies = cMillies;
2199 NTSTATUS rcNt = nemR0NtPerformIoControl(pGVM, pGVM->nem.s.IoCtlMessageSlotHandleAndGetNext.uFunction,
2200 &pVCpu->nem.s.uIoCtlBuf.MsgSlotHandleAndGetNext,
2201 sizeof(pVCpu->nem.s.uIoCtlBuf.MsgSlotHandleAndGetNext),
2202 NULL, 0);
2203 VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC_NEM, VMCPUSTATE_STARTED_EXEC_NEM_WAIT);
2204 if (rcNt == STATUS_SUCCESS)
2205# else
2206 BOOL fRet = VidMessageSlotHandleAndGetNext(pVM->nem.s.hPartitionDevice, pVCpu->idCpu,
2207 pVCpu->nem.s.fHandleAndGetFlags, cMillies);
2208 VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC_NEM, VMCPUSTATE_STARTED_EXEC_NEM_WAIT);
2209 if (fRet)
2210# endif
2211 {
2212 /*
2213 * Deal with the message.
2214 */
2215 rcStrict = nemHCWinHandleMessage(pVM, pVCpu, pMappingHeader, pCtx, pGVCpu);
2216 pVCpu->nem.s.fHandleAndGetFlags |= VID_MSHAGN_F_HANDLE_MESSAGE;
2217 if (rcStrict == VINF_SUCCESS)
2218 { /* hopefully likely */ }
2219 else
2220 {
2221 LogFlow(("NEM/%u: breaking: nemHCWinHandleMessage -> %Rrc\n", pVCpu->idCpu, VBOXSTRICTRC_VAL(rcStrict) ));
2222 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatBreakOnStatus);
2223 break;
2224 }
2225 }
2226 else
2227 {
2228 /* VID.SYS merges STATUS_ALERTED and STATUS_USER_APC into STATUS_TIMEOUT,
2229 so after NtAlertThread we end up here with a STATUS_TIMEOUT. And yeah,
2230 the error code conversion is into WAIT_XXX, i.e. NT status codes. */
2231# ifndef IN_RING0
2232 DWORD rcNt = GetLastError();
2233# endif
2234 LogFlow(("NEM/%u: VidMessageSlotHandleAndGetNext -> %#x\n", pVCpu->idCpu, rcNt));
2235 AssertLogRelMsgReturn( rcNt == STATUS_TIMEOUT
2236 || rcNt == STATUS_ALERTED /* just in case */
2237 || rcNt == STATUS_USER_APC /* ditto */
2238 , ("VidMessageSlotHandleAndGetNext failed for CPU #%u: %#x (%u)\n", pVCpu->idCpu, rcNt, rcNt),
2239 VERR_INTERNAL_ERROR_3);
2240 pVCpu->nem.s.fHandleAndGetFlags = VID_MSHAGN_F_GET_NEXT_MESSAGE;
2241 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatGetMsgTimeout);
2242 }
2243
2244 /*
2245 * If no relevant FFs are pending, loop.
2246 */
2247 if ( !VM_FF_IS_PENDING( pVM, !fSingleStepping ? VM_FF_HP_R0_PRE_HM_MASK : VM_FF_HP_R0_PRE_HM_STEP_MASK)
2248 && !VMCPU_FF_IS_PENDING(pVCpu, !fSingleStepping ? VMCPU_FF_HP_R0_PRE_HM_MASK : VMCPU_FF_HP_R0_PRE_HM_STEP_MASK) )
2249 continue;
2250
2251 /** @todo Try handle pending flags, not just return to EM loops. Take care
2252 * not to set important RCs here unless we've handled a message. */
2253 LogFlow(("NEM/%u: breaking: pending FF (%#x / %#x)\n",
2254 pVCpu->idCpu, pVM->fGlobalForcedActions, pVCpu->fLocalForcedActions));
2255 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatBreakOnFFPost);
2256 }
2257 else
2258 {
2259 LogFlow(("NEM/%u: breaking: canceled %d (pre exec)\n", pVCpu->idCpu, VMCPU_GET_STATE(pVCpu) ));
2260 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatBreakOnCancel);
2261 }
2262 }
2263 else
2264 {
2265 LogFlow(("NEM/%u: breaking: pending FF (pre exec)\n", pVCpu->idCpu));
2266 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatBreakOnFFPre);
2267 }
2268 break;
2269 } /* the run loop */
2270
2271
2272 /*
2273 * If the CPU is running, make sure to stop it before we try sync back the
2274 * state and return to EM.
2275 */
2276 if (pVCpu->nem.s.fHandleAndGetFlags == VID_MSHAGN_F_GET_NEXT_MESSAGE)
2277 {
2278 pVCpu->nem.s.fHandleAndGetFlags = 0;
2279 rcStrict = nemHCWinStopCpu(pVM, pVCpu, rcStrict, pMappingHeader, pGVM, pGVCpu);
2280 }
2281
2282 if (!VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED, VMCPUSTATE_STARTED_EXEC_NEM))
2283 VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED, VMCPUSTATE_STARTED_EXEC_NEM_CANCELED);
2284
2285 if (pCtx->fExtrn & (CPUMCTX_EXTRN_ALL | (CPUMCTX_EXTRN_NEM_WIN_MASK & ~CPUMCTX_EXTRN_NEM_WIN_EVENT_INJECT)))
2286 {
2287# ifdef IN_RING0
2288 int rc2 = nemR0WinImportState(pGVM, pGVCpu, pCtx, CPUMCTX_EXTRN_ALL | CPUMCTX_EXTRN_NEM_WIN_MASK);
2289 if (RT_SUCCESS(rc2))
2290 pCtx->fExtrn = 0;
2291 else if (rc2 == VERR_NEM_CHANGE_PGM_MODE || rc2 == VERR_NEM_FLUSH_TLB)
2292 {
2293 pCtx->fExtrn = 0;
2294 if (rcStrict == VINF_SUCCESS || rcStrict == -rc2)
2295 rcStrict = -rc2;
2296 else
2297 {
2298 pVCpu->nem.s.rcPgmPending = -rc2;
2299 LogFlow(("NEM/%u: rcPgmPending=%Rrc (rcStrict=%Rrc)\n", pVCpu->idCpu, rc2, VBOXSTRICTRC_VAL(rcStrict) ));
2300 }
2301 }
2302# else
2303 int rc2 = nemHCWinCopyStateFromHyperV(pVM, pVCpu, pCtx, CPUMCTX_EXTRN_ALL | CPUMCTX_EXTRN_NEM_WIN_MASK);
2304 if (RT_SUCCESS(rc2))
2305 pCtx->fExtrn = 0;
2306# endif
2307 else if (RT_SUCCESS(rcStrict))
2308 rcStrict = rc2;
2309 }
2310 else
2311 pCtx->fExtrn = 0;
2312
2313 LogFlow(("NEM/%u: %04x:%08RX64 efl=%#08RX64 => %Rrc\n",
2314 pVCpu->idCpu, pCtx->cs.Sel, pCtx->rip, pCtx->rflags, VBOXSTRICTRC_VAL(rcStrict) ));
2315 return rcStrict;
2316}
2317
2318#endif /* NEM_WIN_USE_OUR_OWN_RUN_API */
2319
2320
2321/**
2322 * @callback_method_impl{FNPGMPHYSNEMCHECKPAGE}
2323 */
2324NEM_TMPL_STATIC DECLCALLBACK(int) nemHCWinUnsetForA20CheckerCallback(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys,
2325 PPGMPHYSNEMPAGEINFO pInfo, void *pvUser)
2326{
2327 /* We'll just unmap the memory. */
2328 if (pInfo->u2NemState > NEM_WIN_PAGE_STATE_UNMAPPED)
2329 {
2330#ifdef NEM_WIN_USE_HYPERCALLS_FOR_PAGES
2331 int rc = nemHCWinHypercallUnmapPage(pVM, pVCpu, GCPhys);
2332 AssertRC(rc);
2333 if (RT_SUCCESS(rc))
2334#else
2335 HRESULT hrc = WHvUnmapGpaRange(pVM->nem.s.hPartition, GCPhys, X86_PAGE_SIZE);
2336 if (SUCCEEDED(hrc))
2337#endif
2338 {
2339 uint32_t cMappedPages = ASMAtomicDecU32(&pVM->nem.s.cMappedPages); NOREF(cMappedPages);
2340 Log5(("NEM GPA unmapped/A20: %RGp (was %s, cMappedPages=%u)\n", GCPhys, g_apszPageStates[pInfo->u2NemState], cMappedPages));
2341 pInfo->u2NemState = NEM_WIN_PAGE_STATE_UNMAPPED;
2342 }
2343 else
2344 {
2345#ifdef NEM_WIN_USE_HYPERCALLS_FOR_PAGES
2346 LogRel(("nemHCWinUnsetForA20CheckerCallback/unmap: GCPhys=%RGp rc=%Rrc\n", GCPhys, rc));
2347 return rc;
2348#else
2349 LogRel(("nemHCWinUnsetForA20CheckerCallback/unmap: GCPhys=%RGp hrc=%Rhrc (%#x) Last=%#x/%u\n",
2350 GCPhys, hrc, hrc, RTNtLastStatusValue(), RTNtLastErrorValue()));
2351 return VERR_INTERNAL_ERROR_2;
2352#endif
2353 }
2354 }
2355 RT_NOREF(pVCpu, pvUser);
2356 return VINF_SUCCESS;
2357}
2358
2359
2360/**
2361 * Unmaps a page from Hyper-V for the purpose of emulating A20 gate behavior.
2362 *
2363 * @returns The PGMPhysNemQueryPageInfo result.
2364 * @param pVM The cross context VM structure.
2365 * @param pVCpu The cross context virtual CPU structure.
2366 * @param GCPhys The page to unmap.
2367 */
2368NEM_TMPL_STATIC int nemHCWinUnmapPageForA20Gate(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys)
2369{
2370 PGMPHYSNEMPAGEINFO Info;
2371 return PGMPhysNemPageInfoChecker(pVM, pVCpu, GCPhys, false /*fMakeWritable*/, &Info,
2372 nemHCWinUnsetForA20CheckerCallback, NULL);
2373}
2374
2375
2376void nemHCNativeNotifyHandlerPhysicalRegister(PVM pVM, PGMPHYSHANDLERKIND enmKind, RTGCPHYS GCPhys, RTGCPHYS cb)
2377{
2378 Log5(("nemHCNativeNotifyHandlerPhysicalRegister: %RGp LB %RGp enmKind=%d\n", GCPhys, cb, enmKind));
2379 NOREF(pVM); NOREF(enmKind); NOREF(GCPhys); NOREF(cb);
2380}
2381
2382
2383void nemHCNativeNotifyHandlerPhysicalDeregister(PVM pVM, PGMPHYSHANDLERKIND enmKind, RTGCPHYS GCPhys, RTGCPHYS cb,
2384 int fRestoreAsRAM, bool fRestoreAsRAM2)
2385{
2386 Log5(("nemHCNativeNotifyHandlerPhysicalDeregister: %RGp LB %RGp enmKind=%d fRestoreAsRAM=%d fRestoreAsRAM2=%d\n",
2387 GCPhys, cb, enmKind, fRestoreAsRAM, fRestoreAsRAM2));
2388 NOREF(pVM); NOREF(enmKind); NOREF(GCPhys); NOREF(cb); NOREF(fRestoreAsRAM); NOREF(fRestoreAsRAM2);
2389}
2390
2391
2392void nemHCNativeNotifyHandlerPhysicalModify(PVM pVM, PGMPHYSHANDLERKIND enmKind, RTGCPHYS GCPhysOld,
2393 RTGCPHYS GCPhysNew, RTGCPHYS cb, bool fRestoreAsRAM)
2394{
2395 Log5(("nemHCNativeNotifyHandlerPhysicalModify: %RGp LB %RGp -> %RGp enmKind=%d fRestoreAsRAM=%d\n",
2396 GCPhysOld, cb, GCPhysNew, enmKind, fRestoreAsRAM));
2397 NOREF(pVM); NOREF(enmKind); NOREF(GCPhysOld); NOREF(GCPhysNew); NOREF(cb); NOREF(fRestoreAsRAM);
2398}
2399
2400
2401/**
2402 * Worker that maps pages into Hyper-V.
2403 *
2404 * This is used by the PGM physical page notifications as well as the memory
2405 * access VMEXIT handlers.
2406 *
2407 * @returns VBox status code.
2408 * @param pVM The cross context VM structure.
2409 * @param pVCpu The cross context virtual CPU structure of the
2410 * calling EMT.
2411 * @param GCPhysSrc The source page address.
2412 * @param GCPhysDst The hyper-V destination page. This may differ from
2413 * GCPhysSrc when A20 is disabled.
2414 * @param fPageProt NEM_PAGE_PROT_XXX.
2415 * @param pu2State Our page state (input/output).
2416 * @param fBackingChanged Set if the page backing is being changed.
2417 * @thread EMT(pVCpu)
2418 */
2419NEM_TMPL_STATIC int nemHCNativeSetPhysPage(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhysSrc, RTGCPHYS GCPhysDst,
2420 uint32_t fPageProt, uint8_t *pu2State, bool fBackingChanged)
2421{
2422#ifdef NEM_WIN_USE_HYPERCALLS_FOR_PAGES
2423 /*
2424 * When using the hypercalls instead of the ring-3 APIs, we don't need to
2425 * unmap memory before modifying it. We still want to track the state though,
2426 * since unmap will fail when called an unmapped page and we don't want to redo
2427 * upgrades/downgrades.
2428 */
2429 uint8_t const u2OldState = *pu2State;
2430 int rc;
2431 if (fPageProt == NEM_PAGE_PROT_NONE)
2432 {
2433 if (u2OldState > NEM_WIN_PAGE_STATE_UNMAPPED)
2434 {
2435 rc = nemHCWinHypercallUnmapPage(pVM, pVCpu, GCPhysDst);
2436 if (RT_SUCCESS(rc))
2437 {
2438 *pu2State = NEM_WIN_PAGE_STATE_UNMAPPED;
2439 uint32_t cMappedPages = ASMAtomicDecU32(&pVM->nem.s.cMappedPages); NOREF(cMappedPages);
2440 Log5(("NEM GPA unmapped/set: %RGp (was %s, cMappedPages=%u)\n", GCPhysDst, g_apszPageStates[u2OldState], cMappedPages));
2441 }
2442 else
2443 AssertLogRelMsgFailed(("nemHCNativeSetPhysPage/unmap: GCPhysDst=%RGp rc=%Rrc\n", GCPhysDst, rc));
2444 }
2445 else
2446 rc = VINF_SUCCESS;
2447 }
2448 else if (fPageProt & NEM_PAGE_PROT_WRITE)
2449 {
2450 if (u2OldState != NEM_WIN_PAGE_STATE_WRITABLE || fBackingChanged)
2451 {
2452 rc = nemHCWinHypercallMapPage(pVM, pVCpu, GCPhysSrc, GCPhysDst,
2453 HV_MAP_GPA_READABLE | HV_MAP_GPA_WRITABLE
2454 | HV_MAP_GPA_EXECUTABLE | HV_MAP_GPA_EXECUTABLE_AGAIN);
2455 if (RT_SUCCESS(rc))
2456 {
2457 *pu2State = NEM_WIN_PAGE_STATE_WRITABLE;
2458 uint32_t cMappedPages = u2OldState <= NEM_WIN_PAGE_STATE_UNMAPPED
2459 ? ASMAtomicIncU32(&pVM->nem.s.cMappedPages) : pVM->nem.s.cMappedPages;
2460 Log5(("NEM GPA writable/set: %RGp (was %s, cMappedPages=%u)\n", GCPhysDst, g_apszPageStates[u2OldState], cMappedPages));
2461 NOREF(cMappedPages);
2462 }
2463 else
2464 AssertLogRelMsgFailed(("nemHCNativeSetPhysPage/writable: GCPhysDst=%RGp rc=%Rrc\n", GCPhysDst, rc));
2465 }
2466 else
2467 rc = VINF_SUCCESS;
2468 }
2469 else
2470 {
2471 if (u2OldState != NEM_WIN_PAGE_STATE_READABLE || fBackingChanged)
2472 {
2473 rc = nemHCWinHypercallMapPage(pVM, pVCpu, GCPhysSrc, GCPhysDst,
2474 HV_MAP_GPA_READABLE | HV_MAP_GPA_EXECUTABLE | HV_MAP_GPA_EXECUTABLE_AGAIN);
2475 if (RT_SUCCESS(rc))
2476 {
2477 *pu2State = NEM_WIN_PAGE_STATE_READABLE;
2478 uint32_t cMappedPages = u2OldState <= NEM_WIN_PAGE_STATE_UNMAPPED
2479 ? ASMAtomicIncU32(&pVM->nem.s.cMappedPages) : pVM->nem.s.cMappedPages;
2480 Log5(("NEM GPA read+exec/set: %RGp (was %s, cMappedPages=%u)\n", GCPhysDst, g_apszPageStates[u2OldState], cMappedPages));
2481 NOREF(cMappedPages);
2482 }
2483 else
2484 AssertLogRelMsgFailed(("nemHCNativeSetPhysPage/writable: GCPhysDst=%RGp rc=%Rrc\n", GCPhysDst, rc));
2485 }
2486 else
2487 rc = VINF_SUCCESS;
2488 }
2489
2490 return VINF_SUCCESS;
2491
2492#else
2493 /*
2494 * Looks like we need to unmap a page before we can change the backing
2495 * or even modify the protection. This is going to be *REALLY* efficient.
2496 * PGM lends us two bits to keep track of the state here.
2497 */
2498 uint8_t const u2OldState = *pu2State;
2499 uint8_t const u2NewState = fPageProt & NEM_PAGE_PROT_WRITE ? NEM_WIN_PAGE_STATE_WRITABLE
2500 : fPageProt & NEM_PAGE_PROT_READ ? NEM_WIN_PAGE_STATE_READABLE : NEM_WIN_PAGE_STATE_UNMAPPED;
2501 if ( fBackingChanged
2502 || u2NewState != u2OldState)
2503 {
2504 if (u2OldState > NEM_WIN_PAGE_STATE_UNMAPPED)
2505 {
2506# ifdef NEM_WIN_USE_HYPERCALLS_FOR_PAGES
2507 int rc = nemHCWinHypercallUnmapPage(pVM, pVCpu, GCPhysDst);
2508 AssertRC(rc);
2509 if (RT_SUCCESS(rc))
2510 {
2511 *pu2State = NEM_WIN_PAGE_STATE_UNMAPPED;
2512 uint32_t cMappedPages = ASMAtomicDecU32(&pVM->nem.s.cMappedPages); NOREF(cMappedPages);
2513 if (u2NewState == NEM_WIN_PAGE_STATE_UNMAPPED)
2514 {
2515 Log5(("NEM GPA unmapped/set: %RGp (was %s, cMappedPages=%u)\n",
2516 GCPhysDst, g_apszPageStates[u2OldState], cMappedPages));
2517 return VINF_SUCCESS;
2518 }
2519 }
2520 else
2521 {
2522 LogRel(("nemHCNativeSetPhysPage/unmap: GCPhysDst=%RGp rc=%Rrc\n", GCPhysDst, rc));
2523 return rc;
2524 }
2525# else
2526 HRESULT hrc = WHvUnmapGpaRange(pVM->nem.s.hPartition, GCPhysDst, X86_PAGE_SIZE);
2527 if (SUCCEEDED(hrc))
2528 {
2529 *pu2State = NEM_WIN_PAGE_STATE_UNMAPPED;
2530 uint32_t cMappedPages = ASMAtomicDecU32(&pVM->nem.s.cMappedPages); NOREF(cMappedPages);
2531 if (u2NewState == NEM_WIN_PAGE_STATE_UNMAPPED)
2532 {
2533 Log5(("NEM GPA unmapped/set: %RGp (was %s, cMappedPages=%u)\n",
2534 GCPhysDst, g_apszPageStates[u2OldState], cMappedPages));
2535 return VINF_SUCCESS;
2536 }
2537 }
2538 else
2539 {
2540 LogRel(("nemHCNativeSetPhysPage/unmap: GCPhysDst=%RGp hrc=%Rhrc (%#x) Last=%#x/%u\n",
2541 GCPhysDst, hrc, hrc, RTNtLastStatusValue(), RTNtLastErrorValue()));
2542 return VERR_NEM_INIT_FAILED;
2543 }
2544# endif
2545 }
2546 }
2547
2548 /*
2549 * Writeable mapping?
2550 */
2551 if (fPageProt & NEM_PAGE_PROT_WRITE)
2552 {
2553# ifdef NEM_WIN_USE_HYPERCALLS_FOR_PAGES
2554 int rc = nemHCWinHypercallMapPage(pVM, pVCpu, GCPhysSrc, GCPhysDst,
2555 HV_MAP_GPA_READABLE | HV_MAP_GPA_WRITABLE
2556 | HV_MAP_GPA_EXECUTABLE | HV_MAP_GPA_EXECUTABLE_AGAIN);
2557 AssertRC(rc);
2558 if (RT_SUCCESS(rc))
2559 {
2560 *pu2State = NEM_WIN_PAGE_STATE_WRITABLE;
2561 uint32_t cMappedPages = ASMAtomicIncU32(&pVM->nem.s.cMappedPages); NOREF(cMappedPages);
2562 Log5(("NEM GPA mapped/set: %RGp %s (was %s, cMappedPages=%u)\n",
2563 GCPhysDst, g_apszPageStates[u2NewState], g_apszPageStates[u2OldState], cMappedPages));
2564 return VINF_SUCCESS;
2565 }
2566 LogRel(("nemHCNativeSetPhysPage/writable: GCPhysDst=%RGp rc=%Rrc\n", GCPhysDst, rc));
2567 return rc;
2568# else
2569 void *pvPage;
2570 int rc = nemR3NativeGCPhys2R3PtrWriteable(pVM, GCPhysSrc, &pvPage);
2571 if (RT_SUCCESS(rc))
2572 {
2573 HRESULT hrc = WHvMapGpaRange(pVM->nem.s.hPartition, pvPage, GCPhysDst, X86_PAGE_SIZE,
2574 WHvMapGpaRangeFlagRead | WHvMapGpaRangeFlagExecute | WHvMapGpaRangeFlagWrite);
2575 if (SUCCEEDED(hrc))
2576 {
2577 *pu2State = NEM_WIN_PAGE_STATE_WRITABLE;
2578 uint32_t cMappedPages = ASMAtomicIncU32(&pVM->nem.s.cMappedPages); NOREF(cMappedPages);
2579 Log5(("NEM GPA mapped/set: %RGp %s (was %s, cMappedPages=%u)\n",
2580 GCPhysDst, g_apszPageStates[u2NewState], g_apszPageStates[u2OldState], cMappedPages));
2581 return VINF_SUCCESS;
2582 }
2583 LogRel(("nemHCNativeSetPhysPage/writable: GCPhysDst=%RGp hrc=%Rhrc (%#x) Last=%#x/%u\n",
2584 GCPhysDst, hrc, hrc, RTNtLastStatusValue(), RTNtLastErrorValue()));
2585 return VERR_NEM_INIT_FAILED;
2586 }
2587 LogRel(("nemHCNativeSetPhysPage/writable: GCPhysSrc=%RGp rc=%Rrc\n", GCPhysSrc, rc));
2588 return rc;
2589# endif
2590 }
2591
2592 if (fPageProt & NEM_PAGE_PROT_READ)
2593 {
2594# ifdef NEM_WIN_USE_HYPERCALLS_FOR_PAGES
2595 int rc = nemHCWinHypercallMapPage(pVM, pVCpu, GCPhysSrc, GCPhysDst,
2596 HV_MAP_GPA_READABLE | HV_MAP_GPA_EXECUTABLE | HV_MAP_GPA_EXECUTABLE_AGAIN);
2597 AssertRC(rc);
2598 if (RT_SUCCESS(rc))
2599 {
2600 *pu2State = NEM_WIN_PAGE_STATE_READABLE;
2601 uint32_t cMappedPages = ASMAtomicIncU32(&pVM->nem.s.cMappedPages); NOREF(cMappedPages);
2602 Log5(("NEM GPA mapped/set: %RGp %s (was %s, cMappedPages=%u)\n",
2603 GCPhysDst, g_apszPageStates[u2NewState], g_apszPageStates[u2OldState], cMappedPages));
2604 return VINF_SUCCESS;
2605 }
2606 LogRel(("nemHCNativeSetPhysPage/readonly: GCPhysDst=%RGp rc=%Rrc\n", GCPhysDst, rc));
2607 return rc;
2608# else
2609 const void *pvPage;
2610 int rc = nemR3NativeGCPhys2R3PtrReadOnly(pVM, GCPhysSrc, &pvPage);
2611 if (RT_SUCCESS(rc))
2612 {
2613 HRESULT hrc = WHvMapGpaRange(pVM->nem.s.hPartition, (void *)pvPage, GCPhysDst, X86_PAGE_SIZE,
2614 WHvMapGpaRangeFlagRead | WHvMapGpaRangeFlagExecute);
2615 if (SUCCEEDED(hrc))
2616 {
2617 *pu2State = NEM_WIN_PAGE_STATE_READABLE;
2618 uint32_t cMappedPages = ASMAtomicIncU32(&pVM->nem.s.cMappedPages); NOREF(cMappedPages);
2619 Log5(("NEM GPA mapped/set: %RGp %s (was %s, cMappedPages=%u)\n",
2620 GCPhysDst, g_apszPageStates[u2NewState], g_apszPageStates[u2OldState], cMappedPages));
2621 return VINF_SUCCESS;
2622 }
2623 LogRel(("nemHCNativeSetPhysPage/readonly: GCPhysDst=%RGp hrc=%Rhrc (%#x) Last=%#x/%u\n",
2624 GCPhysDst, hrc, hrc, RTNtLastStatusValue(), RTNtLastErrorValue()));
2625 return VERR_NEM_INIT_FAILED;
2626 }
2627 LogRel(("nemHCNativeSetPhysPage/readonly: GCPhysSrc=%RGp rc=%Rrc\n", GCPhysSrc, rc));
2628 return rc;
2629# endif
2630 }
2631
2632 /* We already unmapped it above. */
2633 *pu2State = NEM_WIN_PAGE_STATE_UNMAPPED;
2634 return VINF_SUCCESS;
2635#endif /* !NEM_WIN_USE_HYPERCALLS_FOR_PAGES */
2636}
2637
2638
2639NEM_TMPL_STATIC int nemHCJustUnmapPageFromHyperV(PVM pVM, RTGCPHYS GCPhysDst, uint8_t *pu2State)
2640{
2641 if (*pu2State <= NEM_WIN_PAGE_STATE_UNMAPPED)
2642 {
2643 Log5(("nemHCJustUnmapPageFromHyperV: %RGp == unmapped\n", GCPhysDst));
2644 *pu2State = NEM_WIN_PAGE_STATE_UNMAPPED;
2645 return VINF_SUCCESS;
2646 }
2647
2648#if defined(NEM_WIN_USE_HYPERCALLS_FOR_PAGES) || defined(IN_RING0)
2649 PVMCPU pVCpu = VMMGetCpu(pVM);
2650 int rc = nemHCWinHypercallUnmapPage(pVM, pVCpu, GCPhysDst);
2651 AssertRC(rc);
2652 if (RT_SUCCESS(rc))
2653 {
2654 uint32_t cMappedPages = ASMAtomicDecU32(&pVM->nem.s.cMappedPages); NOREF(cMappedPages);
2655 Log5(("NEM GPA unmapped/just: %RGp (was %s, cMappedPages=%u)\n", GCPhysDst, g_apszPageStates[*pu2State], cMappedPages));
2656 *pu2State = NEM_WIN_PAGE_STATE_UNMAPPED;
2657 return VINF_SUCCESS;
2658 }
2659 LogRel(("nemHCJustUnmapPageFromHyperV/unmap: GCPhysDst=%RGp rc=%Rrc\n", GCPhysDst, rc));
2660 return rc;
2661#else
2662 HRESULT hrc = WHvUnmapGpaRange(pVM->nem.s.hPartition, GCPhysDst & ~(RTGCPHYS)X86_PAGE_OFFSET_MASK, X86_PAGE_SIZE);
2663 if (SUCCEEDED(hrc))
2664 {
2665 uint32_t cMappedPages = ASMAtomicDecU32(&pVM->nem.s.cMappedPages); NOREF(cMappedPages);
2666 *pu2State = NEM_WIN_PAGE_STATE_UNMAPPED;
2667 Log5(("nemHCJustUnmapPageFromHyperV: %RGp => unmapped (total %u)\n", GCPhysDst, cMappedPages));
2668 return VINF_SUCCESS;
2669 }
2670 LogRel(("nemHCJustUnmapPageFromHyperV(%RGp): failed! hrc=%Rhrc (%#x) Last=%#x/%u\n",
2671 GCPhysDst, hrc, hrc, RTNtLastStatusValue(), RTNtLastErrorValue()));
2672 return VERR_INTERNAL_ERROR_3;
2673#endif
2674}
2675
2676
2677int nemHCNativeNotifyPhysPageAllocated(PVM pVM, RTGCPHYS GCPhys, RTHCPHYS HCPhys, uint32_t fPageProt,
2678 PGMPAGETYPE enmType, uint8_t *pu2State)
2679{
2680 Log5(("nemHCNativeNotifyPhysPageAllocated: %RGp HCPhys=%RHp fPageProt=%#x enmType=%d *pu2State=%d\n",
2681 GCPhys, HCPhys, fPageProt, enmType, *pu2State));
2682 RT_NOREF_PV(HCPhys); RT_NOREF_PV(enmType);
2683
2684 int rc;
2685#if defined(NEM_WIN_USE_HYPERCALLS_FOR_PAGES) || defined(IN_RING0)
2686 PVMCPU pVCpu = VMMGetCpu(pVM);
2687 if ( pVM->nem.s.fA20Enabled
2688 || !NEM_WIN_IS_RELEVANT_TO_A20(GCPhys))
2689 rc = nemHCNativeSetPhysPage(pVM, pVCpu, GCPhys, GCPhys, fPageProt, pu2State, true /*fBackingChanged*/);
2690 else
2691 {
2692 /* To keep effort at a minimum, we unmap the HMA page alias and resync it lazily when needed. */
2693 rc = nemHCWinUnmapPageForA20Gate(pVM, pVCpu, GCPhys | RT_BIT_32(20));
2694 if (!NEM_WIN_IS_SUBJECT_TO_A20(GCPhys) && RT_SUCCESS(rc))
2695 rc = nemHCNativeSetPhysPage(pVM, pVCpu, GCPhys, GCPhys, fPageProt, pu2State, true /*fBackingChanged*/);
2696
2697 }
2698#else
2699 RT_NOREF_PV(fPageProt);
2700 if ( pVM->nem.s.fA20Enabled
2701 || !NEM_WIN_IS_RELEVANT_TO_A20(GCPhys))
2702 rc = nemR3JustUnmapPageFromHyperV(pVM, GCPhys, pu2State);
2703 else if (!NEM_WIN_IS_SUBJECT_TO_A20(GCPhys))
2704 rc = nemR3JustUnmapPageFromHyperV(pVM, GCPhys, pu2State);
2705 else
2706 rc = VINF_SUCCESS; /* ignore since we've got the alias page at this address. */
2707#endif
2708 return rc;
2709}
2710
2711
2712void nemHCNativeNotifyPhysPageProtChanged(PVM pVM, RTGCPHYS GCPhys, RTHCPHYS HCPhys, uint32_t fPageProt,
2713 PGMPAGETYPE enmType, uint8_t *pu2State)
2714{
2715 Log5(("nemHCNativeNotifyPhysPageProtChanged: %RGp HCPhys=%RHp fPageProt=%#x enmType=%d *pu2State=%d\n",
2716 GCPhys, HCPhys, fPageProt, enmType, *pu2State));
2717 RT_NOREF_PV(HCPhys); RT_NOREF_PV(enmType);
2718
2719#if defined(NEM_WIN_USE_HYPERCALLS_FOR_PAGES) || defined(IN_RING0)
2720 PVMCPU pVCpu = VMMGetCpu(pVM);
2721 if ( pVM->nem.s.fA20Enabled
2722 || !NEM_WIN_IS_RELEVANT_TO_A20(GCPhys))
2723 nemHCNativeSetPhysPage(pVM, pVCpu, GCPhys, GCPhys, fPageProt, pu2State, false /*fBackingChanged*/);
2724 else
2725 {
2726 /* To keep effort at a minimum, we unmap the HMA page alias and resync it lazily when needed. */
2727 nemHCWinUnmapPageForA20Gate(pVM, pVCpu, GCPhys | RT_BIT_32(20));
2728 if (!NEM_WIN_IS_SUBJECT_TO_A20(GCPhys))
2729 nemHCNativeSetPhysPage(pVM, pVCpu, GCPhys, GCPhys, fPageProt, pu2State, false /*fBackingChanged*/);
2730 }
2731#else
2732 RT_NOREF_PV(fPageProt);
2733 if ( pVM->nem.s.fA20Enabled
2734 || !NEM_WIN_IS_RELEVANT_TO_A20(GCPhys))
2735 nemR3JustUnmapPageFromHyperV(pVM, GCPhys, pu2State);
2736 else if (!NEM_WIN_IS_SUBJECT_TO_A20(GCPhys))
2737 nemR3JustUnmapPageFromHyperV(pVM, GCPhys, pu2State);
2738 /* else: ignore since we've got the alias page at this address. */
2739#endif
2740}
2741
2742
2743void nemHCNativeNotifyPhysPageChanged(PVM pVM, RTGCPHYS GCPhys, RTHCPHYS HCPhysPrev, RTHCPHYS HCPhysNew,
2744 uint32_t fPageProt, PGMPAGETYPE enmType, uint8_t *pu2State)
2745{
2746 Log5(("nemHCNativeNotifyPhysPageChanged: %RGp HCPhys=%RHp->%RHp fPageProt=%#x enmType=%d *pu2State=%d\n",
2747 GCPhys, HCPhysPrev, HCPhysNew, fPageProt, enmType, *pu2State));
2748 RT_NOREF_PV(HCPhysPrev); RT_NOREF_PV(HCPhysNew); RT_NOREF_PV(enmType);
2749
2750#if defined(NEM_WIN_USE_HYPERCALLS_FOR_PAGES) || defined(IN_RING0)
2751 PVMCPU pVCpu = VMMGetCpu(pVM);
2752 if ( pVM->nem.s.fA20Enabled
2753 || !NEM_WIN_IS_RELEVANT_TO_A20(GCPhys))
2754 nemHCNativeSetPhysPage(pVM, pVCpu, GCPhys, GCPhys, fPageProt, pu2State, true /*fBackingChanged*/);
2755 else
2756 {
2757 /* To keep effort at a minimum, we unmap the HMA page alias and resync it lazily when needed. */
2758 nemHCWinUnmapPageForA20Gate(pVM, pVCpu, GCPhys | RT_BIT_32(20));
2759 if (!NEM_WIN_IS_SUBJECT_TO_A20(GCPhys))
2760 nemHCNativeSetPhysPage(pVM, pVCpu, GCPhys, GCPhys, fPageProt, pu2State, true /*fBackingChanged*/);
2761 }
2762#else
2763 RT_NOREF_PV(fPageProt);
2764 if ( pVM->nem.s.fA20Enabled
2765 || !NEM_WIN_IS_RELEVANT_TO_A20(GCPhys))
2766 nemR3JustUnmapPageFromHyperV(pVM, GCPhys, pu2State);
2767 else if (!NEM_WIN_IS_SUBJECT_TO_A20(GCPhys))
2768 nemR3JustUnmapPageFromHyperV(pVM, GCPhys, pu2State);
2769 /* else: ignore since we've got the alias page at this address. */
2770#endif
2771}
2772
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