VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/PDMAll.cpp@ 27778

Last change on this file since 27778 was 27254, checked in by vboxsync, 15 years ago

HPET: correct interrupts delivery
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1/* $Id: PDMAll.cpp 27254 2010-03-10 15:03:11Z vboxsync $ */
2/** @file
3 * PDM Critical Sections
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22
23/*******************************************************************************
24* Header Files *
25*******************************************************************************/
26#define LOG_GROUP LOG_GROUP_PDM
27#include "PDMInternal.h"
28#include <VBox/pdm.h>
29#include <VBox/mm.h>
30#include <VBox/vm.h>
31#include <VBox/err.h>
32
33#include <VBox/log.h>
34#include <iprt/asm.h>
35#include <iprt/assert.h>
36
37
38/**
39 * Gets the pending interrupt.
40 *
41 * @returns VBox status code.
42 * @param pVCpu VMCPU handle.
43 * @param pu8Interrupt Where to store the interrupt on success.
44 */
45VMMDECL(int) PDMGetInterrupt(PVMCPU pVCpu, uint8_t *pu8Interrupt)
46{
47 PVM pVM = pVCpu->CTX_SUFF(pVM);
48
49 pdmLock(pVM);
50
51 /*
52 * The local APIC has a higer priority than the PIC.
53 */
54 if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INTERRUPT_APIC))
55 {
56 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_APIC);
57 Assert(pVM->pdm.s.Apic.CTX_SUFF(pDevIns));
58 Assert(pVM->pdm.s.Apic.CTX_SUFF(pfnGetInterrupt));
59 int i = pVM->pdm.s.Apic.CTX_SUFF(pfnGetInterrupt)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns));
60 AssertMsg(i <= 255 && i >= 0, ("i=%d\n", i));
61 if (i >= 0)
62 {
63 pdmUnlock(pVM);
64 *pu8Interrupt = (uint8_t)i;
65 return VINF_SUCCESS;
66 }
67 }
68
69 /*
70 * Check the PIC.
71 */
72 if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INTERRUPT_PIC))
73 {
74 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_PIC);
75 Assert(pVM->pdm.s.Pic.CTX_SUFF(pDevIns));
76 Assert(pVM->pdm.s.Pic.CTX_SUFF(pfnGetInterrupt));
77 int i = pVM->pdm.s.Pic.CTX_SUFF(pfnGetInterrupt)(pVM->pdm.s.Pic.CTX_SUFF(pDevIns));
78 AssertMsg(i <= 255 && i >= 0, ("i=%d\n", i));
79 if (i >= 0)
80 {
81 pdmUnlock(pVM);
82 *pu8Interrupt = (uint8_t)i;
83 return VINF_SUCCESS;
84 }
85 }
86
87 /** @todo Figure out exactly why we can get here without anything being set. (REM) */
88
89 pdmUnlock(pVM);
90 return VERR_NO_DATA;
91}
92
93
94/**
95 * Sets the pending interrupt coming from ISA source or HPET.
96 *
97 * @returns VBox status code.
98 * @param pVM VM handle.
99 * @param u8Irq The IRQ line.
100 * @param u8Level The new level.
101 */
102VMMDECL(int) PDMIsaSetIrq(PVM pVM, uint8_t u8Irq, uint8_t u8Level)
103{
104 pdmLock(pVM);
105
106 int rc = VERR_PDM_NO_PIC_INSTANCE;
107 if (pVM->pdm.s.Pic.CTX_SUFF(pDevIns))
108 {
109 Assert(pVM->pdm.s.Pic.CTX_SUFF(pfnSetIrq));
110 pVM->pdm.s.Pic.CTX_SUFF(pfnSetIrq)(pVM->pdm.s.Pic.CTX_SUFF(pDevIns), u8Irq, u8Level);
111 rc = VINF_SUCCESS;
112 }
113
114 if (pVM->pdm.s.IoApic.CTX_SUFF(pDevIns))
115 {
116 Assert(pVM->pdm.s.IoApic.CTX_SUFF(pfnSetIrq));
117
118 /**
119 * Apply Interrupt Source Override rules.
120 * See ACPI 4.0 specification 5.2.12.4 and 5.2.12.5 for details on
121 * interrupt source override.
122 * Shortly, ISA IRQ0 is electically connected to pin 2 on IO-APIC, and some OSes,
123 * notably recent OS X rely upon this configuration.
124 * If changing, also update override rules in MADT and MPS.
125 */
126 /* ISA IRQ0 routed to pin 2, all others ISA sources are identity mapped */
127 if (u8Irq == 0)
128 u8Irq = 2;
129
130 pVM->pdm.s.IoApic.CTX_SUFF(pfnSetIrq)(pVM->pdm.s.IoApic.CTX_SUFF(pDevIns), u8Irq, u8Level);
131 rc = VINF_SUCCESS;
132 }
133
134 pdmUnlock(pVM);
135 return rc;
136}
137
138
139/**
140 * Sets the pending I/O APIC interrupt.
141 *
142 * @returns VBox status code.
143 * @param pVM VM handle.
144 * @param u8Irq The IRQ line.
145 * @param u8Level The new level.
146 */
147VMMDECL(int) PDMIoApicSetIrq(PVM pVM, uint8_t u8Irq, uint8_t u8Level)
148{
149 if (pVM->pdm.s.IoApic.CTX_SUFF(pDevIns))
150 {
151 Assert(pVM->pdm.s.IoApic.CTX_SUFF(pfnSetIrq));
152 pdmLock(pVM);
153 pVM->pdm.s.IoApic.CTX_SUFF(pfnSetIrq)(pVM->pdm.s.IoApic.CTX_SUFF(pDevIns), u8Irq, u8Level);
154 pdmUnlock(pVM);
155 return VINF_SUCCESS;
156 }
157 return VERR_PDM_NO_PIC_INSTANCE;
158}
159
160
161/**
162 * Returns presence of an IO-APIC
163 *
164 * @returns VBox true if IO-APIC is present
165 * @param pVM VM handle.
166 */
167VMMDECL(bool) PDMHasIoApic(PVM pVM)
168{
169 return pVM->pdm.s.IoApic.CTX_SUFF(pDevIns) != NULL;
170}
171
172
173/**
174 * Set the APIC base.
175 *
176 * @returns VBox status code.
177 * @param pVM VM handle.
178 * @param u64Base The new base.
179 */
180VMMDECL(int) PDMApicSetBase(PVM pVM, uint64_t u64Base)
181{
182 if (pVM->pdm.s.Apic.CTX_SUFF(pDevIns))
183 {
184 Assert(pVM->pdm.s.Apic.CTX_SUFF(pfnSetBase));
185 pdmLock(pVM);
186 pVM->pdm.s.Apic.CTX_SUFF(pfnSetBase)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns), u64Base);
187 pdmUnlock(pVM);
188 return VINF_SUCCESS;
189 }
190 return VERR_PDM_NO_APIC_INSTANCE;
191}
192
193
194/**
195 * Get the APIC base.
196 *
197 * @returns VBox status code.
198 * @param pVM VM handle.
199 * @param pu64Base Where to store the APIC base.
200 */
201VMMDECL(int) PDMApicGetBase(PVM pVM, uint64_t *pu64Base)
202{
203 if (pVM->pdm.s.Apic.CTX_SUFF(pDevIns))
204 {
205 Assert(pVM->pdm.s.Apic.CTX_SUFF(pfnGetBase));
206 pdmLock(pVM);
207 *pu64Base = pVM->pdm.s.Apic.CTX_SUFF(pfnGetBase)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns));
208 pdmUnlock(pVM);
209 return VINF_SUCCESS;
210 }
211 *pu64Base = 0;
212 return VERR_PDM_NO_APIC_INSTANCE;
213}
214
215
216/**
217 * Check if the APIC has a pending interrupt/if a TPR change would active one.
218 *
219 * @returns VINF_SUCCESS or VERR_PDM_NO_APIC_INSTANCE.
220 * @param pDevIns Device instance of the APIC.
221 * @param pfPending Pending state (out).
222 */
223VMMDECL(int) PDMApicHasPendingIrq(PVM pVM, bool *pfPending)
224{
225 if (pVM->pdm.s.Apic.CTX_SUFF(pDevIns))
226 {
227 Assert(pVM->pdm.s.Apic.CTX_SUFF(pfnSetTPR));
228 pdmLock(pVM);
229 *pfPending = pVM->pdm.s.Apic.CTX_SUFF(pfnHasPendingIrq)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns));
230 pdmUnlock(pVM);
231 return VINF_SUCCESS;
232 }
233 return VERR_PDM_NO_APIC_INSTANCE;
234}
235
236
237/**
238 * Set the TPR (task priority register?).
239 *
240 * @returns VBox status code.
241 * @param pVCpu VMCPU handle.
242 * @param u8TPR The new TPR.
243 */
244VMMDECL(int) PDMApicSetTPR(PVMCPU pVCpu, uint8_t u8TPR)
245{
246 PVM pVM = pVCpu->CTX_SUFF(pVM);
247 if (pVM->pdm.s.Apic.CTX_SUFF(pDevIns))
248 {
249 Assert(pVM->pdm.s.Apic.CTX_SUFF(pfnSetTPR));
250 pdmLock(pVM);
251 pVM->pdm.s.Apic.CTX_SUFF(pfnSetTPR)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns), pVCpu->idCpu, u8TPR);
252 pdmUnlock(pVM);
253 return VINF_SUCCESS;
254 }
255 return VERR_PDM_NO_APIC_INSTANCE;
256}
257
258
259/**
260 * Get the TPR (task priority register).
261 *
262 * @returns The current TPR.
263 * @param pVCpu VMCPU handle.
264 * @param pu8TPR Where to store the TRP.
265 * @param pfPending Pending interrupt state (out).
266*/
267VMMDECL(int) PDMApicGetTPR(PVMCPU pVCpu, uint8_t *pu8TPR, bool *pfPending)
268{
269 PVM pVM = pVCpu->CTX_SUFF(pVM);
270 if (pVM->pdm.s.Apic.CTX_SUFF(pDevIns))
271 {
272 Assert(pVM->pdm.s.Apic.CTX_SUFF(pfnGetTPR));
273 /* We don't acquire the PDM lock here as we're just reading information. Doing so causes massive
274 * contention as this function is called very often by each and every VCPU.
275 */
276 *pu8TPR = pVM->pdm.s.Apic.CTX_SUFF(pfnGetTPR)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns), pVCpu->idCpu);
277 if (pfPending)
278 *pfPending = pVM->pdm.s.Apic.CTX_SUFF(pfnHasPendingIrq)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns));
279 return VINF_SUCCESS;
280 }
281 *pu8TPR = 0;
282 return VERR_PDM_NO_APIC_INSTANCE;
283}
284
285/**
286 * Write MSR in APIC range.
287 *
288 * @returns VBox status code.
289 * @param pVM VM handle.
290 * @param iCpu Target CPU.
291 * @param u32Reg MSR to write.
292 * @param u64Value Value to write.
293 */
294VMMDECL(int) PDMApicWriteMSR(PVM pVM, VMCPUID iCpu, uint32_t u32Reg, uint64_t u64Value)
295{
296 if (pVM->pdm.s.Apic.CTX_SUFF(pDevIns))
297 {
298 Assert(pVM->pdm.s.Apic.CTX_SUFF(pfnWriteMSR));
299 pdmLock(pVM);
300 pVM->pdm.s.Apic.CTX_SUFF(pfnWriteMSR)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns), iCpu, u32Reg, u64Value);
301 pdmUnlock(pVM);
302 return VINF_SUCCESS;
303 }
304 return VERR_PDM_NO_APIC_INSTANCE;
305}
306
307/**
308 * Read MSR in APIC range.
309 *
310 * @returns VBox status code.
311 * @param pVM VM handle.
312 * @param iCpu Target CPU.
313 * @param u32Reg MSR to read.
314 * @param pu64Value Value read.
315 */
316VMMDECL(int) PDMApicReadMSR(PVM pVM, VMCPUID iCpu, uint32_t u32Reg, uint64_t *pu64Value)
317{
318 if (pVM->pdm.s.Apic.CTX_SUFF(pDevIns))
319 {
320 Assert(pVM->pdm.s.Apic.CTX_SUFF(pfnReadMSR));
321 pdmLock(pVM);
322 pVM->pdm.s.Apic.CTX_SUFF(pfnReadMSR)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns), iCpu, u32Reg, pu64Value);
323 pdmUnlock(pVM);
324 return VINF_SUCCESS;
325 }
326 return VERR_PDM_NO_APIC_INSTANCE;
327}
328
329
330/**
331 * Locks PDM.
332 * This might call back to Ring-3 in order to deal with lock contention in GC and R3.
333 *
334 * @param pVM The VM handle.
335 */
336void pdmLock(PVM pVM)
337{
338#ifdef IN_RING3
339 int rc = PDMCritSectEnter(&pVM->pdm.s.CritSect, VERR_INTERNAL_ERROR);
340#else
341 int rc = PDMCritSectEnter(&pVM->pdm.s.CritSect, VERR_GENERAL_FAILURE);
342 if (rc == VERR_GENERAL_FAILURE)
343 rc = VMMRZCallRing3NoCpu(pVM, VMMCALLRING3_PDM_LOCK, 0);
344#endif
345 AssertRC(rc);
346}
347
348
349/**
350 * Locks PDM but don't go to ring-3 if it's owned by someone.
351 *
352 * @returns VINF_SUCCESS on success.
353 * @returns rc if we're in GC or R0 and can't get the lock.
354 * @param pVM The VM handle.
355 * @param rc The RC to return in GC or R0 when we can't get the lock.
356 */
357int pdmLockEx(PVM pVM, int rc)
358{
359 return PDMCritSectEnter(&pVM->pdm.s.CritSect, rc);
360}
361
362
363/**
364 * Unlocks PDM.
365 *
366 * @param pVM The VM handle.
367 */
368void pdmUnlock(PVM pVM)
369{
370 PDMCritSectLeave(&pVM->pdm.s.CritSect);
371}
372
373
374/**
375 * Converts ring 3 VMM heap pointer to a guest physical address
376 *
377 * @returns VBox status code.
378 * @param pVM VM handle.
379 * @param pv Ring-3 pointer.
380 * @param pGCPhys GC phys address (out).
381 */
382VMMDECL(int) PDMVMMDevHeapR3ToGCPhys(PVM pVM, RTR3PTR pv, RTGCPHYS *pGCPhys)
383{
384 /* Don't assert here as this is called before we can catch ring-0 assertions. */
385 if (RT_UNLIKELY((RTR3UINTPTR)pv - (RTR3UINTPTR)pVM->pdm.s.pvVMMDevHeap >= pVM->pdm.s.cbVMMDevHeap))
386 {
387 Log(("PDMVMMDevHeapR3ToGCPhys: pv=%p pvVMMDevHeap=%p cbVMMDevHeap=%#x\n",
388 pv, pVM->pdm.s.pvVMMDevHeap, pVM->pdm.s.cbVMMDevHeap));
389 return VERR_INTERNAL_ERROR_3;
390 }
391
392 *pGCPhys = (pVM->pdm.s.GCPhysVMMDevHeap + ((RTR3UINTPTR)pv - (RTR3UINTPTR)pVM->pdm.s.pvVMMDevHeap));
393 return VINF_SUCCESS;
394}
395
396/**
397 * Checks if the vmm device heap is enabled (== vmm device's pci region mapped)
398 *
399 * @returns dev heap enabled status (true/false)
400 * @param pVM VM handle.
401 */
402VMMDECL(bool) PDMVMMDevHeapIsEnabled(PVM pVM)
403{
404 return (pVM->pdm.s.pvVMMDevHeap != NULL);
405}
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