VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/PDMAll.cpp@ 58591

Last change on this file since 58591 was 58126, checked in by vboxsync, 9 years ago

VMM: Fixed almost all the Doxygen warnings.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id Revision
File size: 15.1 KB
Line 
1/* $Id: PDMAll.cpp 58126 2015-10-08 20:59:48Z vboxsync $ */
2/** @file
3 * PDM Critical Sections
4 */
5
6/*
7 * Copyright (C) 2006-2015 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_PDM
23#include "PDMInternal.h"
24#include <VBox/vmm/pdm.h>
25#include <VBox/vmm/mm.h>
26#include <VBox/vmm/vm.h>
27#include <VBox/err.h>
28
29#include <VBox/log.h>
30#include <iprt/asm.h>
31#include <iprt/assert.h>
32
33#include "PDMInline.h"
34#include "dtrace/VBoxVMM.h"
35
36
37
38/**
39 * Gets the pending interrupt.
40 *
41 * @returns VBox status code.
42 * @param pVCpu The cross context virtual CPU structure.
43 * @param pu8Interrupt Where to store the interrupt on success.
44 */
45VMMDECL(int) PDMGetInterrupt(PVMCPU pVCpu, uint8_t *pu8Interrupt)
46{
47 PVM pVM = pVCpu->CTX_SUFF(pVM);
48
49 pdmLock(pVM);
50
51 /*
52 * The local APIC has a higher priority than the PIC.
53 */
54 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC))
55 {
56 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_APIC);
57 Assert(pVM->pdm.s.Apic.CTX_SUFF(pDevIns));
58 Assert(pVM->pdm.s.Apic.CTX_SUFF(pfnGetInterrupt));
59 uint32_t uTagSrc;
60 int i = pVM->pdm.s.Apic.CTX_SUFF(pfnGetInterrupt)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns), pVCpu->idCpu, &uTagSrc);
61 AssertMsg(i <= 255 && i >= 0, ("i=%d\n", i));
62 if (i >= 0)
63 {
64 pdmUnlock(pVM);
65 *pu8Interrupt = (uint8_t)i;
66 VBOXVMM_PDM_IRQ_GET(pVCpu, RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc), i);
67 return VINF_SUCCESS;
68 }
69 }
70
71 /*
72 * Check the PIC.
73 */
74 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_PIC))
75 {
76 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_PIC);
77 Assert(pVM->pdm.s.Pic.CTX_SUFF(pDevIns));
78 Assert(pVM->pdm.s.Pic.CTX_SUFF(pfnGetInterrupt));
79 uint32_t uTagSrc;
80 int i = pVM->pdm.s.Pic.CTX_SUFF(pfnGetInterrupt)(pVM->pdm.s.Pic.CTX_SUFF(pDevIns), &uTagSrc);
81 AssertMsg(i <= 255 && i >= 0, ("i=%d\n", i));
82 if (i >= 0)
83 {
84 pdmUnlock(pVM);
85 *pu8Interrupt = (uint8_t)i;
86 VBOXVMM_PDM_IRQ_GET(pVCpu, RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc), i);
87 return VINF_SUCCESS;
88 }
89 }
90
91 /** @todo Figure out exactly why we can get here without anything being set. (REM) */
92
93 pdmUnlock(pVM);
94 return VERR_NO_DATA;
95}
96
97
98/**
99 * Sets the pending interrupt coming from ISA source or HPET.
100 *
101 * @returns VBox status code.
102 * @param pVM The cross context VM structure.
103 * @param u8Irq The IRQ line.
104 * @param u8Level The new level.
105 * @param uTagSrc The IRQ tag and source tracer ID.
106 */
107VMMDECL(int) PDMIsaSetIrq(PVM pVM, uint8_t u8Irq, uint8_t u8Level, uint32_t uTagSrc)
108{
109 pdmLock(pVM);
110
111 /** @todo put the IRQ13 code elsewhere to avoid this unnecessary bloat. */
112 if (!uTagSrc && (u8Level & PDM_IRQ_LEVEL_HIGH)) /* FPU IRQ */
113 {
114 if (u8Level == PDM_IRQ_LEVEL_HIGH)
115 VBOXVMM_PDM_IRQ_HIGH(VMMGetCpu(pVM), 0, 0);
116 else
117 VBOXVMM_PDM_IRQ_HILO(VMMGetCpu(pVM), 0, 0);
118 }
119
120 int rc = VERR_PDM_NO_PIC_INSTANCE;
121 if (pVM->pdm.s.Pic.CTX_SUFF(pDevIns))
122 {
123 Assert(pVM->pdm.s.Pic.CTX_SUFF(pfnSetIrq));
124 pVM->pdm.s.Pic.CTX_SUFF(pfnSetIrq)(pVM->pdm.s.Pic.CTX_SUFF(pDevIns), u8Irq, u8Level, uTagSrc);
125 rc = VINF_SUCCESS;
126 }
127
128 if (pVM->pdm.s.IoApic.CTX_SUFF(pDevIns))
129 {
130 Assert(pVM->pdm.s.IoApic.CTX_SUFF(pfnSetIrq));
131
132 /*
133 * Apply Interrupt Source Override rules.
134 * See ACPI 4.0 specification 5.2.12.4 and 5.2.12.5 for details on
135 * interrupt source override.
136 * Shortly, ISA IRQ0 is electically connected to pin 2 on IO-APIC, and some OSes,
137 * notably recent OS X rely upon this configuration.
138 * If changing, also update override rules in MADT and MPS.
139 */
140 /* ISA IRQ0 routed to pin 2, all others ISA sources are identity mapped */
141 if (u8Irq == 0)
142 u8Irq = 2;
143
144 pVM->pdm.s.IoApic.CTX_SUFF(pfnSetIrq)(pVM->pdm.s.IoApic.CTX_SUFF(pDevIns), u8Irq, u8Level, uTagSrc);
145 rc = VINF_SUCCESS;
146 }
147
148 if (!uTagSrc && u8Level == PDM_IRQ_LEVEL_LOW)
149 VBOXVMM_PDM_IRQ_LOW(VMMGetCpu(pVM), 0, 0);
150 pdmUnlock(pVM);
151 return rc;
152}
153
154
155/**
156 * Sets the pending I/O APIC interrupt.
157 *
158 * @returns VBox status code.
159 * @param pVM The cross context VM structure.
160 * @param u8Irq The IRQ line.
161 * @param u8Level The new level.
162 * @param uTagSrc The IRQ tag and source tracer ID.
163 */
164VMM_INT_DECL(int) PDMIoApicSetIrq(PVM pVM, uint8_t u8Irq, uint8_t u8Level, uint32_t uTagSrc)
165{
166 if (pVM->pdm.s.IoApic.CTX_SUFF(pDevIns))
167 {
168 Assert(pVM->pdm.s.IoApic.CTX_SUFF(pfnSetIrq));
169 pdmLock(pVM);
170 pVM->pdm.s.IoApic.CTX_SUFF(pfnSetIrq)(pVM->pdm.s.IoApic.CTX_SUFF(pDevIns), u8Irq, u8Level, uTagSrc);
171 pdmUnlock(pVM);
172 return VINF_SUCCESS;
173 }
174 return VERR_PDM_NO_PIC_INSTANCE;
175}
176
177/**
178 * Send a MSI to an I/O APIC.
179 *
180 * @returns VBox status code.
181 * @param pVM The cross context VM structure.
182 * @param GCAddr Request address.
183 * @param uValue Request value.
184 * @param uTagSrc The IRQ tag and source tracer ID.
185 */
186VMM_INT_DECL(int) PDMIoApicSendMsi(PVM pVM, RTGCPHYS GCAddr, uint32_t uValue, uint32_t uTagSrc)
187{
188 if (pVM->pdm.s.IoApic.CTX_SUFF(pDevIns))
189 {
190 Assert(pVM->pdm.s.IoApic.CTX_SUFF(pfnSendMsi));
191 pdmLock(pVM);
192 pVM->pdm.s.IoApic.CTX_SUFF(pfnSendMsi)(pVM->pdm.s.IoApic.CTX_SUFF(pDevIns), GCAddr, uValue, uTagSrc);
193 pdmUnlock(pVM);
194 return VINF_SUCCESS;
195 }
196 return VERR_PDM_NO_PIC_INSTANCE;
197}
198
199
200
201/**
202 * Returns the presence of an IO-APIC.
203 *
204 * @returns VBox true if an IO-APIC is present.
205 * @param pVM The cross context VM structure.
206 */
207VMM_INT_DECL(bool) PDMHasIoApic(PVM pVM)
208{
209 return pVM->pdm.s.IoApic.CTX_SUFF(pDevIns) != NULL;
210}
211
212
213/**
214 * Returns the presence of a Local APIC.
215 *
216 * @returns VBox true if a Local APIC is present.
217 * @param pVM The cross context VM structure.
218 */
219VMM_INT_DECL(bool) PDMHasApic(PVM pVM)
220{
221 return pVM->pdm.s.Apic.CTX_SUFF(pDevIns) != NULL;
222}
223
224
225/**
226 * Set the APIC base.
227 *
228 * @returns VBox status code.
229 * @param pVCpu The cross context virtual CPU structure.
230 * @param u64Base The new base.
231 */
232VMMDECL(int) PDMApicSetBase(PVMCPU pVCpu, uint64_t u64Base)
233{
234 PVM pVM = pVCpu->CTX_SUFF(pVM);
235 if (pVM->pdm.s.Apic.CTX_SUFF(pDevIns))
236 {
237 Assert(pVM->pdm.s.Apic.CTX_SUFF(pfnSetBase));
238 pdmLock(pVM);
239 pVM->pdm.s.Apic.CTX_SUFF(pfnSetBase)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns), pVCpu->idCpu, u64Base);
240
241 /* Update CPUM's copy of the APIC base. */
242 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
243 Assert(pCtx);
244 pCtx->msrApicBase = pVM->pdm.s.Apic.CTX_SUFF(pfnGetBase)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns), pVCpu->idCpu);
245
246 pdmUnlock(pVM);
247 return VINF_SUCCESS;
248 }
249 return VERR_PDM_NO_APIC_INSTANCE;
250}
251
252
253/**
254 * Get the APIC base from the APIC device. This is slow and involves
255 * taking the PDM lock, this is currently only used by CPUM to cache the APIC
256 * base once (during init./load state), all other callers should use
257 * PDMApicGetBase() and not this function.
258 *
259 * @returns VBox status code.
260 * @param pVCpu The cross context virtual CPU structure.
261 * @param pu64Base Where to store the APIC base.
262 */
263VMMDECL(int) PDMApicGetBase(PVMCPU pVCpu, uint64_t *pu64Base)
264{
265 PVM pVM = pVCpu->CTX_SUFF(pVM);
266 if (pVM->pdm.s.Apic.CTX_SUFF(pDevIns))
267 {
268 Assert(pVM->pdm.s.Apic.CTX_SUFF(pfnGetBase));
269 pdmLock(pVM);
270 *pu64Base = pVM->pdm.s.Apic.CTX_SUFF(pfnGetBase)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns), pVCpu->idCpu);
271 pdmUnlock(pVM);
272 return VINF_SUCCESS;
273 }
274 *pu64Base = 0;
275 return VERR_PDM_NO_APIC_INSTANCE;
276}
277
278
279/**
280 * Check if the APIC has a pending interrupt/if a TPR change would active one.
281 *
282 * @returns VINF_SUCCESS or VERR_PDM_NO_APIC_INSTANCE.
283 * @param pVCpu The cross context virtual CPU structure.
284 * @param pfPending Pending state (out).
285 */
286VMM_INT_DECL(int) PDMApicHasPendingIrq(PVMCPU pVCpu, bool *pfPending)
287{
288 PVM pVM = pVCpu->CTX_SUFF(pVM);
289 if (pVM->pdm.s.Apic.CTX_SUFF(pDevIns))
290 {
291 Assert(pVM->pdm.s.Apic.CTX_SUFF(pfnSetTPR));
292 pdmLock(pVM);
293 *pfPending = pVM->pdm.s.Apic.CTX_SUFF(pfnHasPendingIrq)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns), pVCpu->idCpu,
294 NULL /* pu8PendingIrq */);
295 pdmUnlock(pVM);
296 return VINF_SUCCESS;
297 }
298 return VERR_PDM_NO_APIC_INSTANCE;
299}
300
301
302/**
303 * Set the TPR (task priority register?).
304 *
305 * @returns VBox status code.
306 * @param pVCpu The cross context virtual CPU structure.
307 * @param u8TPR The new TPR.
308 */
309VMMDECL(int) PDMApicSetTPR(PVMCPU pVCpu, uint8_t u8TPR)
310{
311 PVM pVM = pVCpu->CTX_SUFF(pVM);
312 if (pVM->pdm.s.Apic.CTX_SUFF(pDevIns))
313 {
314 Assert(pVM->pdm.s.Apic.CTX_SUFF(pfnSetTPR));
315 pdmLock(pVM);
316 pVM->pdm.s.Apic.CTX_SUFF(pfnSetTPR)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns), pVCpu->idCpu, u8TPR);
317 pdmUnlock(pVM);
318 return VINF_SUCCESS;
319 }
320 return VERR_PDM_NO_APIC_INSTANCE;
321}
322
323
324/**
325 * Get the TPR (task priority register).
326 *
327 * @returns VINF_SUCCESS or VERR_PDM_NO_APIC_INSTANCE.
328 * @param pVCpu The cross context virtual CPU structure.
329 * @param pu8TPR Where to store the TRP.
330 * @param pfPending Pending interrupt state (out, optional).
331 * @param pu8PendingIrq Where to store the highest-priority pending IRQ
332 * (out, optional).
333 *
334 * @remarks No-long-jump zone!!!
335 */
336VMMDECL(int) PDMApicGetTPR(PVMCPU pVCpu, uint8_t *pu8TPR, bool *pfPending, uint8_t *pu8PendingIrq)
337{
338 PVM pVM = pVCpu->CTX_SUFF(pVM);
339 PPDMDEVINS pApicIns = pVM->pdm.s.Apic.CTX_SUFF(pDevIns);
340 if (pApicIns)
341 {
342 /*
343 * Note! We don't acquire the PDM lock here as we're just reading
344 * information. Doing so causes massive contention as this
345 * function is called very often by each and every VCPU.
346 */
347 Assert(pVM->pdm.s.Apic.CTX_SUFF(pfnGetTPR));
348 *pu8TPR = pVM->pdm.s.Apic.CTX_SUFF(pfnGetTPR)(pApicIns, pVCpu->idCpu);
349 if (pfPending)
350 *pfPending = pVM->pdm.s.Apic.CTX_SUFF(pfnHasPendingIrq)(pApicIns, pVCpu->idCpu, pu8PendingIrq);
351 return VINF_SUCCESS;
352 }
353 *pu8TPR = 0;
354 return VERR_PDM_NO_APIC_INSTANCE;
355}
356
357
358/**
359 * Write a MSR in APIC range.
360 *
361 * @returns VBox status code.
362 * @param pVM The cross context VM structure.
363 * @param iCpu Target CPU.
364 * @param u32Reg MSR to write.
365 * @param u64Value Value to write.
366 */
367VMM_INT_DECL(int) PDMApicWriteMSR(PVM pVM, VMCPUID iCpu, uint32_t u32Reg, uint64_t u64Value)
368{
369 if (pVM->pdm.s.Apic.CTX_SUFF(pDevIns))
370 {
371 AssertPtr(pVM->pdm.s.Apic.CTX_SUFF(pfnWriteMSR));
372 return pVM->pdm.s.Apic.CTX_SUFF(pfnWriteMSR)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns), iCpu, u32Reg, u64Value);
373 }
374 return VERR_PDM_NO_APIC_INSTANCE;
375}
376
377
378/**
379 * Read a MSR in APIC range.
380 *
381 * @returns VBox status code.
382 * @param pVM The cross context VM structure.
383 * @param iCpu Target CPU.
384 * @param u32Reg MSR to read.
385 * @param pu64Value Value read.
386 */
387VMM_INT_DECL(int) PDMApicReadMSR(PVM pVM, VMCPUID iCpu, uint32_t u32Reg, uint64_t *pu64Value)
388{
389 if (pVM->pdm.s.Apic.CTX_SUFF(pDevIns))
390 {
391 AssertPtr(pVM->pdm.s.Apic.CTX_SUFF(pfnReadMSR));
392 int rc = pVM->pdm.s.Apic.CTX_SUFF(pfnReadMSR)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns), iCpu, u32Reg, pu64Value);
393 return rc;
394 }
395 return VERR_PDM_NO_APIC_INSTANCE;
396}
397
398
399/**
400 * Gets the frequency of the APIC timer.
401 *
402 * @returns VBox status code.
403 * @param pVM The cross context VM structure.
404 * @param pu64Value Where to store the frequency.
405 */
406VMM_INT_DECL(int) PDMApicGetTimerFreq(PVM pVM, uint64_t *pu64Value)
407{
408 if (pVM->pdm.s.Apic.CTX_SUFF(pDevIns))
409 {
410 AssertPtr(pVM->pdm.s.Apic.CTX_SUFF(pfnGetTimerFreq));
411 *pu64Value = pVM->pdm.s.Apic.CTX_SUFF(pfnGetTimerFreq)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns));
412 return VINF_SUCCESS;
413 }
414 return VERR_PDM_NO_APIC_INSTANCE;
415}
416
417
418/**
419 * Locks PDM.
420 * This might call back to Ring-3 in order to deal with lock contention in GC and R3.
421 *
422 * @param pVM The cross context VM structure.
423 */
424void pdmLock(PVM pVM)
425{
426#ifdef IN_RING3
427 int rc = PDMCritSectEnter(&pVM->pdm.s.CritSect, VERR_IGNORED);
428#else
429 int rc = PDMCritSectEnter(&pVM->pdm.s.CritSect, VERR_GENERAL_FAILURE);
430 if (rc == VERR_GENERAL_FAILURE)
431 rc = VMMRZCallRing3NoCpu(pVM, VMMCALLRING3_PDM_LOCK, 0);
432#endif
433 AssertRC(rc);
434}
435
436
437/**
438 * Locks PDM but don't go to ring-3 if it's owned by someone.
439 *
440 * @returns VINF_SUCCESS on success.
441 * @returns rc if we're in GC or R0 and can't get the lock.
442 * @param pVM The cross context VM structure.
443 * @param rc The RC to return in GC or R0 when we can't get the lock.
444 */
445int pdmLockEx(PVM pVM, int rc)
446{
447 return PDMCritSectEnter(&pVM->pdm.s.CritSect, rc);
448}
449
450
451/**
452 * Unlocks PDM.
453 *
454 * @param pVM The cross context VM structure.
455 */
456void pdmUnlock(PVM pVM)
457{
458 PDMCritSectLeave(&pVM->pdm.s.CritSect);
459}
460
461
462/**
463 * Converts ring 3 VMM heap pointer to a guest physical address
464 *
465 * @returns VBox status code.
466 * @param pVM The cross context VM structure.
467 * @param pv Ring-3 pointer.
468 * @param pGCPhys GC phys address (out).
469 */
470VMM_INT_DECL(int) PDMVmmDevHeapR3ToGCPhys(PVM pVM, RTR3PTR pv, RTGCPHYS *pGCPhys)
471{
472 /* Don't assert here as this is called before we can catch ring-0 assertions. */
473 if (RT_UNLIKELY((RTR3UINTPTR)pv - (RTR3UINTPTR)pVM->pdm.s.pvVMMDevHeap >= pVM->pdm.s.cbVMMDevHeap))
474 {
475 Log(("PDMVmmDevHeapR3ToGCPhys: pv=%p pvVMMDevHeap=%p cbVMMDevHeap=%#x\n",
476 pv, pVM->pdm.s.pvVMMDevHeap, pVM->pdm.s.cbVMMDevHeap));
477 return VERR_PDM_DEV_HEAP_R3_TO_GCPHYS;
478 }
479
480 *pGCPhys = (pVM->pdm.s.GCPhysVMMDevHeap + ((RTR3UINTPTR)pv - (RTR3UINTPTR)pVM->pdm.s.pvVMMDevHeap));
481 return VINF_SUCCESS;
482}
483
484/**
485 * Checks if the vmm device heap is enabled (== vmm device's pci region mapped)
486 *
487 * @returns dev heap enabled status (true/false)
488 * @param pVM The cross context VM structure.
489 */
490VMM_INT_DECL(bool) PDMVmmDevHeapIsEnabled(PVM pVM)
491{
492 return (pVM->pdm.s.pvVMMDevHeap != NULL);
493}
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette