VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/PDMAll.cpp@ 19995

Last change on this file since 19995 was 19995, checked in by vboxsync, 16 years ago

Introduced PDMHasIoApic.
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File size: 10.2 KB
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1/* $Id: PDMAll.cpp 19995 2009-05-25 12:31:34Z vboxsync $ */
2/** @file
3 * PDM Critical Sections
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22
23/*******************************************************************************
24* Header Files *
25*******************************************************************************/
26#define LOG_GROUP LOG_GROUP_PDM
27#include "PDMInternal.h"
28#include <VBox/pdm.h>
29#include <VBox/mm.h>
30#include <VBox/vm.h>
31#include <VBox/err.h>
32
33#include <VBox/log.h>
34#include <iprt/asm.h>
35#include <iprt/assert.h>
36
37
38/**
39 * Gets the pending interrupt.
40 *
41 * @returns VBox status code.
42 * @param pVCpu VMCPU handle.
43 * @param pu8Interrupt Where to store the interrupt on success.
44 */
45VMMDECL(int) PDMGetInterrupt(PVMCPU pVCpu, uint8_t *pu8Interrupt)
46{
47 PVM pVM = pVCpu->CTX_SUFF(pVM);
48
49 pdmLock(pVM);
50
51 /*
52 * The local APIC has a higer priority than the PIC.
53 */
54 if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INTERRUPT_APIC))
55 {
56 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_APIC);
57 Assert(pVM->pdm.s.Apic.CTX_SUFF(pDevIns));
58 Assert(pVM->pdm.s.Apic.CTX_SUFF(pfnGetInterrupt));
59 int i = pVM->pdm.s.Apic.CTX_SUFF(pfnGetInterrupt)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns));
60 AssertMsg(i <= 255 && i >= 0, ("i=%d\n", i));
61 if (i >= 0)
62 {
63 pdmUnlock(pVM);
64 *pu8Interrupt = (uint8_t)i;
65 return VINF_SUCCESS;
66 }
67 }
68
69 /*
70 * Check the PIC.
71 */
72 if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INTERRUPT_PIC))
73 {
74 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_PIC);
75 Assert(pVM->pdm.s.Pic.CTX_SUFF(pDevIns));
76 Assert(pVM->pdm.s.Pic.CTX_SUFF(pfnGetInterrupt));
77 int i = pVM->pdm.s.Pic.CTX_SUFF(pfnGetInterrupt)(pVM->pdm.s.Pic.CTX_SUFF(pDevIns));
78 AssertMsg(i <= 255 && i >= 0, ("i=%d\n", i));
79 if (i >= 0)
80 {
81 pdmUnlock(pVM);
82 *pu8Interrupt = (uint8_t)i;
83 return VINF_SUCCESS;
84 }
85 }
86
87 /** @todo Figure out exactly why we can get here without anything being set. (REM) */
88
89 pdmUnlock(pVM);
90 return VERR_NO_DATA;
91}
92
93
94/**
95 * Sets the pending interrupt.
96 *
97 * @returns VBox status code.
98 * @param pVM VM handle.
99 * @param u8Irq The IRQ line.
100 * @param u8Level The new level.
101 */
102VMMDECL(int) PDMIsaSetIrq(PVM pVM, uint8_t u8Irq, uint8_t u8Level)
103{
104 pdmLock(pVM);
105
106 int rc = VERR_PDM_NO_PIC_INSTANCE;
107 if (pVM->pdm.s.Pic.CTX_SUFF(pDevIns))
108 {
109 Assert(pVM->pdm.s.Pic.CTX_SUFF(pfnSetIrq));
110 pVM->pdm.s.Pic.CTX_SUFF(pfnSetIrq)(pVM->pdm.s.Pic.CTX_SUFF(pDevIns), u8Irq, u8Level);
111 rc = VINF_SUCCESS;
112 }
113
114 if (pVM->pdm.s.IoApic.CTX_SUFF(pDevIns))
115 {
116 Assert(pVM->pdm.s.IoApic.CTX_SUFF(pfnSetIrq));
117 pVM->pdm.s.IoApic.CTX_SUFF(pfnSetIrq)(pVM->pdm.s.IoApic.CTX_SUFF(pDevIns), u8Irq, u8Level);
118 rc = VINF_SUCCESS;
119 }
120
121 pdmUnlock(pVM);
122 return rc;
123}
124
125
126/**
127 * Sets the pending I/O APIC interrupt.
128 *
129 * @returns VBox status code.
130 * @param pVM VM handle.
131 * @param u8Irq The IRQ line.
132 * @param u8Level The new level.
133 */
134VMMDECL(int) PDMIoApicSetIrq(PVM pVM, uint8_t u8Irq, uint8_t u8Level)
135{
136 if (pVM->pdm.s.IoApic.CTX_SUFF(pDevIns))
137 {
138 Assert(pVM->pdm.s.IoApic.CTX_SUFF(pfnSetIrq));
139 pdmLock(pVM);
140 pVM->pdm.s.IoApic.CTX_SUFF(pfnSetIrq)(pVM->pdm.s.IoApic.CTX_SUFF(pDevIns), u8Irq, u8Level);
141 pdmUnlock(pVM);
142 return VINF_SUCCESS;
143 }
144 return VERR_PDM_NO_PIC_INSTANCE;
145}
146
147
148/**
149 * Returns presence of an IO-APIC
150 *
151 * @returns VBox true if IO-APIC is present
152 * @param pVM VM handle.
153 */
154VMMDECL(bool) PDMHasIoApic(PVM pVM)
155{
156 return pVM->pdm.s.IoApic.CTX_SUFF(pDevIns) != NULL;
157}
158
159
160/**
161 * Set the APIC base.
162 *
163 * @returns VBox status code.
164 * @param pVM VM handle.
165 * @param u64Base The new base.
166 */
167VMMDECL(int) PDMApicSetBase(PVM pVM, uint64_t u64Base)
168{
169 if (pVM->pdm.s.Apic.CTX_SUFF(pDevIns))
170 {
171 Assert(pVM->pdm.s.Apic.CTX_SUFF(pfnSetBase));
172 pdmLock(pVM);
173 pVM->pdm.s.Apic.CTX_SUFF(pfnSetBase)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns), u64Base);
174 pdmUnlock(pVM);
175 return VINF_SUCCESS;
176 }
177 return VERR_PDM_NO_APIC_INSTANCE;
178}
179
180
181/**
182 * Get the APIC base.
183 *
184 * @returns VBox status code.
185 * @param pVM VM handle.
186 * @param pu64Base Where to store the APIC base.
187 */
188VMMDECL(int) PDMApicGetBase(PVM pVM, uint64_t *pu64Base)
189{
190 if (pVM->pdm.s.Apic.CTX_SUFF(pDevIns))
191 {
192 Assert(pVM->pdm.s.Apic.CTX_SUFF(pfnGetBase));
193 pdmLock(pVM);
194 *pu64Base = pVM->pdm.s.Apic.CTX_SUFF(pfnGetBase)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns));
195 pdmUnlock(pVM);
196 return VINF_SUCCESS;
197 }
198 *pu64Base = 0;
199 return VERR_PDM_NO_APIC_INSTANCE;
200}
201
202
203/**
204 * Check if the APIC has a pending interrupt/if a TPR change would active one.
205 *
206 * @returns VINF_SUCCESS or VERR_PDM_NO_APIC_INSTANCE.
207 * @param pDevIns Device instance of the APIC.
208 * @param pfPending Pending state (out).
209 */
210VMMDECL(int) PDMApicHasPendingIrq(PVM pVM, bool *pfPending)
211{
212 if (pVM->pdm.s.Apic.CTX_SUFF(pDevIns))
213 {
214 Assert(pVM->pdm.s.Apic.CTX_SUFF(pfnSetTPR));
215 pdmLock(pVM);
216 *pfPending = pVM->pdm.s.Apic.CTX_SUFF(pfnHasPendingIrq)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns));
217 pdmUnlock(pVM);
218 return VINF_SUCCESS;
219 }
220 return VERR_PDM_NO_APIC_INSTANCE;
221}
222
223
224/**
225 * Set the TPR (task priority register?).
226 *
227 * @returns VBox status code.
228 * @param pVM VM handle.
229 * @param u8TPR The new TPR.
230 */
231VMMDECL(int) PDMApicSetTPR(PVM pVM, uint8_t u8TPR)
232{
233 if (pVM->pdm.s.Apic.CTX_SUFF(pDevIns))
234 {
235 Assert(pVM->pdm.s.Apic.CTX_SUFF(pfnSetTPR));
236 pdmLock(pVM);
237 pVM->pdm.s.Apic.CTX_SUFF(pfnSetTPR)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns), u8TPR);
238 pdmUnlock(pVM);
239 return VINF_SUCCESS;
240 }
241 return VERR_PDM_NO_APIC_INSTANCE;
242}
243
244
245/**
246 * Get the TPR (task priority register).
247 *
248 * @returns The current TPR.
249 * @param pVM VM handle.
250 * @param pu8TPR Where to store the TRP.
251 * @param pfPending Pending interrupt state (out).
252*/
253VMMDECL(int) PDMApicGetTPR(PVM pVM, uint8_t *pu8TPR, bool *pfPending)
254{
255 if (pVM->pdm.s.Apic.CTX_SUFF(pDevIns))
256 {
257 Assert(pVM->pdm.s.Apic.CTX_SUFF(pfnGetTPR));
258 pdmLock(pVM);
259 *pu8TPR = pVM->pdm.s.Apic.CTX_SUFF(pfnGetTPR)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns));
260 if (pfPending)
261 *pfPending = pVM->pdm.s.Apic.CTX_SUFF(pfnHasPendingIrq)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns));
262 pdmUnlock(pVM);
263 return VINF_SUCCESS;
264 }
265 *pu8TPR = 0;
266 return VERR_PDM_NO_APIC_INSTANCE;
267}
268
269/**
270 * Write MSR in APIC range.
271 *
272 * @returns VBox status code.
273 * @param pVM VM handle.
274 * @param iCpu Target CPU.
275 * @param u32Reg MSR to write.
276 * @param u64Value Value to write.
277 */
278VMMDECL(int) PDMApicWriteMSR(PVM pVM, VMCPUID iCpu, uint32_t u32Reg, uint64_t u64Value)
279{
280 if (pVM->pdm.s.Apic.CTX_SUFF(pDevIns))
281 {
282 Assert(pVM->pdm.s.Apic.CTX_SUFF(pfnWriteMSR));
283 pdmLock(pVM);
284 pVM->pdm.s.Apic.CTX_SUFF(pfnWriteMSR)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns), iCpu, u32Reg, u64Value);
285 pdmUnlock(pVM);
286 return VINF_SUCCESS;
287 }
288 return VERR_PDM_NO_APIC_INSTANCE;
289}
290
291/**
292 * Read MSR in APIC range.
293 *
294 * @returns VBox status code.
295 * @param pVM VM handle.
296 * @param iCpu Target CPU.
297 * @param u32Reg MSR to read.
298 * @param pu64Value Value read.
299 */
300VMMDECL(int) PDMApicReadMSR(PVM pVM, VMCPUID iCpu, uint32_t u32Reg, uint64_t *pu64Value)
301{
302 if (pVM->pdm.s.Apic.CTX_SUFF(pDevIns))
303 {
304 Assert(pVM->pdm.s.Apic.CTX_SUFF(pfnReadMSR));
305 pdmLock(pVM);
306 pVM->pdm.s.Apic.CTX_SUFF(pfnReadMSR)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns), iCpu, u32Reg, pu64Value);
307 pdmUnlock(pVM);
308 return VINF_SUCCESS;
309 }
310 return VERR_PDM_NO_APIC_INSTANCE;
311}
312
313
314/**
315 * Locks PDM.
316 * This might call back to Ring-3 in order to deal with lock contention in GC and R3.
317 *
318 * @param pVM The VM handle.
319 */
320void pdmLock(PVM pVM)
321{
322#ifdef IN_RING3
323 int rc = PDMCritSectEnter(&pVM->pdm.s.CritSect, VERR_INTERNAL_ERROR);
324#else
325 int rc = PDMCritSectEnter(&pVM->pdm.s.CritSect, VERR_GENERAL_FAILURE);
326 if (rc == VERR_GENERAL_FAILURE)
327 {
328# ifdef IN_RC
329 rc = VMMGCCallHost(pVM, VMMCALLHOST_PDM_LOCK, 0);
330# else
331 rc = VMMR0CallHost(pVM, VMMCALLHOST_PDM_LOCK, 0);
332# endif
333 }
334#endif
335 AssertRC(rc);
336}
337
338
339/**
340 * Locks PDM but don't go to ring-3 if it's owned by someone.
341 *
342 * @returns VINF_SUCCESS on success.
343 * @returns rc if we're in GC or R0 and can't get the lock.
344 * @param pVM The VM handle.
345 * @param rc The RC to return in GC or R0 when we can't get the lock.
346 */
347int pdmLockEx(PVM pVM, int rc)
348{
349 return PDMCritSectEnter(&pVM->pdm.s.CritSect, rc);
350}
351
352
353/**
354 * Unlocks PDM.
355 *
356 * @param pVM The VM handle.
357 */
358void pdmUnlock(PVM pVM)
359{
360 PDMCritSectLeave(&pVM->pdm.s.CritSect);
361}
362
363
364/**
365 * Converts ring 3 VMM heap pointer to a guest physical address
366 *
367 * @returns VBox status code.
368 * @param pVM VM handle.
369 * @param pv Ring-3 pointer.
370 * @param pGCPhys GC phys address (out).
371 */
372VMMDECL(int) PDMVMMDevHeapR3ToGCPhys(PVM pVM, RTR3PTR pv, RTGCPHYS *pGCPhys)
373{
374 AssertReturn(pv >= pVM->pdm.s.pvVMMDevHeap && (RTR3UINTPTR)pv < (RTR3UINTPTR)pVM->pdm.s.pvVMMDevHeap + pVM->pdm.s.cbVMMDevHeap, VERR_INVALID_PARAMETER);
375
376 *pGCPhys = (pVM->pdm.s.GCPhysVMMDevHeap + ((RTR3UINTPTR)pv - (RTR3UINTPTR)pVM->pdm.s.pvVMMDevHeap));
377 return VINF_SUCCESS;
378}
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