VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/PDMAll.cpp@ 26278

Last change on this file since 26278 was 26143, checked in by vboxsync, 15 years ago

Introducing PDMVMMDevHeapIsEnabled
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1/* $Id: PDMAll.cpp 26143 2010-02-02 12:51:24Z vboxsync $ */
2/** @file
3 * PDM Critical Sections
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22
23/*******************************************************************************
24* Header Files *
25*******************************************************************************/
26#define LOG_GROUP LOG_GROUP_PDM
27#include "PDMInternal.h"
28#include <VBox/pdm.h>
29#include <VBox/mm.h>
30#include <VBox/vm.h>
31#include <VBox/err.h>
32
33#include <VBox/log.h>
34#include <iprt/asm.h>
35#include <iprt/assert.h>
36
37
38/**
39 * Gets the pending interrupt.
40 *
41 * @returns VBox status code.
42 * @param pVCpu VMCPU handle.
43 * @param pu8Interrupt Where to store the interrupt on success.
44 */
45VMMDECL(int) PDMGetInterrupt(PVMCPU pVCpu, uint8_t *pu8Interrupt)
46{
47 PVM pVM = pVCpu->CTX_SUFF(pVM);
48
49 pdmLock(pVM);
50
51 /*
52 * The local APIC has a higer priority than the PIC.
53 */
54 if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INTERRUPT_APIC))
55 {
56 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_APIC);
57 Assert(pVM->pdm.s.Apic.CTX_SUFF(pDevIns));
58 Assert(pVM->pdm.s.Apic.CTX_SUFF(pfnGetInterrupt));
59 int i = pVM->pdm.s.Apic.CTX_SUFF(pfnGetInterrupt)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns));
60 AssertMsg(i <= 255 && i >= 0, ("i=%d\n", i));
61 if (i >= 0)
62 {
63 pdmUnlock(pVM);
64 *pu8Interrupt = (uint8_t)i;
65 return VINF_SUCCESS;
66 }
67 }
68
69 /*
70 * Check the PIC.
71 */
72 if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INTERRUPT_PIC))
73 {
74 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_PIC);
75 Assert(pVM->pdm.s.Pic.CTX_SUFF(pDevIns));
76 Assert(pVM->pdm.s.Pic.CTX_SUFF(pfnGetInterrupt));
77 int i = pVM->pdm.s.Pic.CTX_SUFF(pfnGetInterrupt)(pVM->pdm.s.Pic.CTX_SUFF(pDevIns));
78 AssertMsg(i <= 255 && i >= 0, ("i=%d\n", i));
79 if (i >= 0)
80 {
81 pdmUnlock(pVM);
82 *pu8Interrupt = (uint8_t)i;
83 return VINF_SUCCESS;
84 }
85 }
86
87 /** @todo Figure out exactly why we can get here without anything being set. (REM) */
88
89 pdmUnlock(pVM);
90 return VERR_NO_DATA;
91}
92
93
94/**
95 * Sets the pending interrupt.
96 *
97 * @returns VBox status code.
98 * @param pVM VM handle.
99 * @param u8Irq The IRQ line.
100 * @param u8Level The new level.
101 */
102VMMDECL(int) PDMIsaSetIrq(PVM pVM, uint8_t u8Irq, uint8_t u8Level)
103{
104 pdmLock(pVM);
105
106 int rc = VERR_PDM_NO_PIC_INSTANCE;
107 if (pVM->pdm.s.Pic.CTX_SUFF(pDevIns))
108 {
109 Assert(pVM->pdm.s.Pic.CTX_SUFF(pfnSetIrq));
110 pVM->pdm.s.Pic.CTX_SUFF(pfnSetIrq)(pVM->pdm.s.Pic.CTX_SUFF(pDevIns), u8Irq, u8Level);
111 rc = VINF_SUCCESS;
112 }
113
114 if (pVM->pdm.s.IoApic.CTX_SUFF(pDevIns))
115 {
116 Assert(pVM->pdm.s.IoApic.CTX_SUFF(pfnSetIrq));
117 pVM->pdm.s.IoApic.CTX_SUFF(pfnSetIrq)(pVM->pdm.s.IoApic.CTX_SUFF(pDevIns), u8Irq, u8Level);
118 rc = VINF_SUCCESS;
119 }
120
121 pdmUnlock(pVM);
122 return rc;
123}
124
125
126/**
127 * Sets the pending I/O APIC interrupt.
128 *
129 * @returns VBox status code.
130 * @param pVM VM handle.
131 * @param u8Irq The IRQ line.
132 * @param u8Level The new level.
133 */
134VMMDECL(int) PDMIoApicSetIrq(PVM pVM, uint8_t u8Irq, uint8_t u8Level)
135{
136 if (pVM->pdm.s.IoApic.CTX_SUFF(pDevIns))
137 {
138 Assert(pVM->pdm.s.IoApic.CTX_SUFF(pfnSetIrq));
139 pdmLock(pVM);
140 pVM->pdm.s.IoApic.CTX_SUFF(pfnSetIrq)(pVM->pdm.s.IoApic.CTX_SUFF(pDevIns), u8Irq, u8Level);
141 pdmUnlock(pVM);
142 return VINF_SUCCESS;
143 }
144 return VERR_PDM_NO_PIC_INSTANCE;
145}
146
147
148/**
149 * Returns presence of an IO-APIC
150 *
151 * @returns VBox true if IO-APIC is present
152 * @param pVM VM handle.
153 */
154VMMDECL(bool) PDMHasIoApic(PVM pVM)
155{
156 return pVM->pdm.s.IoApic.CTX_SUFF(pDevIns) != NULL;
157}
158
159
160/**
161 * Set the APIC base.
162 *
163 * @returns VBox status code.
164 * @param pVM VM handle.
165 * @param u64Base The new base.
166 */
167VMMDECL(int) PDMApicSetBase(PVM pVM, uint64_t u64Base)
168{
169 if (pVM->pdm.s.Apic.CTX_SUFF(pDevIns))
170 {
171 Assert(pVM->pdm.s.Apic.CTX_SUFF(pfnSetBase));
172 pdmLock(pVM);
173 pVM->pdm.s.Apic.CTX_SUFF(pfnSetBase)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns), u64Base);
174 pdmUnlock(pVM);
175 return VINF_SUCCESS;
176 }
177 return VERR_PDM_NO_APIC_INSTANCE;
178}
179
180
181/**
182 * Get the APIC base.
183 *
184 * @returns VBox status code.
185 * @param pVM VM handle.
186 * @param pu64Base Where to store the APIC base.
187 */
188VMMDECL(int) PDMApicGetBase(PVM pVM, uint64_t *pu64Base)
189{
190 if (pVM->pdm.s.Apic.CTX_SUFF(pDevIns))
191 {
192 Assert(pVM->pdm.s.Apic.CTX_SUFF(pfnGetBase));
193 pdmLock(pVM);
194 *pu64Base = pVM->pdm.s.Apic.CTX_SUFF(pfnGetBase)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns));
195 pdmUnlock(pVM);
196 return VINF_SUCCESS;
197 }
198 *pu64Base = 0;
199 return VERR_PDM_NO_APIC_INSTANCE;
200}
201
202
203/**
204 * Check if the APIC has a pending interrupt/if a TPR change would active one.
205 *
206 * @returns VINF_SUCCESS or VERR_PDM_NO_APIC_INSTANCE.
207 * @param pDevIns Device instance of the APIC.
208 * @param pfPending Pending state (out).
209 */
210VMMDECL(int) PDMApicHasPendingIrq(PVM pVM, bool *pfPending)
211{
212 if (pVM->pdm.s.Apic.CTX_SUFF(pDevIns))
213 {
214 Assert(pVM->pdm.s.Apic.CTX_SUFF(pfnSetTPR));
215 pdmLock(pVM);
216 *pfPending = pVM->pdm.s.Apic.CTX_SUFF(pfnHasPendingIrq)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns));
217 pdmUnlock(pVM);
218 return VINF_SUCCESS;
219 }
220 return VERR_PDM_NO_APIC_INSTANCE;
221}
222
223
224/**
225 * Set the TPR (task priority register?).
226 *
227 * @returns VBox status code.
228 * @param pVCpu VMCPU handle.
229 * @param u8TPR The new TPR.
230 */
231VMMDECL(int) PDMApicSetTPR(PVMCPU pVCpu, uint8_t u8TPR)
232{
233 PVM pVM = pVCpu->CTX_SUFF(pVM);
234 if (pVM->pdm.s.Apic.CTX_SUFF(pDevIns))
235 {
236 Assert(pVM->pdm.s.Apic.CTX_SUFF(pfnSetTPR));
237 pdmLock(pVM);
238 pVM->pdm.s.Apic.CTX_SUFF(pfnSetTPR)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns), pVCpu->idCpu, u8TPR);
239 pdmUnlock(pVM);
240 return VINF_SUCCESS;
241 }
242 return VERR_PDM_NO_APIC_INSTANCE;
243}
244
245
246/**
247 * Get the TPR (task priority register).
248 *
249 * @returns The current TPR.
250 * @param pVCpu VMCPU handle.
251 * @param pu8TPR Where to store the TRP.
252 * @param pfPending Pending interrupt state (out).
253*/
254VMMDECL(int) PDMApicGetTPR(PVMCPU pVCpu, uint8_t *pu8TPR, bool *pfPending)
255{
256 PVM pVM = pVCpu->CTX_SUFF(pVM);
257 if (pVM->pdm.s.Apic.CTX_SUFF(pDevIns))
258 {
259 Assert(pVM->pdm.s.Apic.CTX_SUFF(pfnGetTPR));
260 /* We don't acquire the PDM lock here as we're just reading information. Doing so causes massive
261 * contention as this function is called very often by each and every VCPU.
262 */
263 *pu8TPR = pVM->pdm.s.Apic.CTX_SUFF(pfnGetTPR)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns), pVCpu->idCpu);
264 if (pfPending)
265 *pfPending = pVM->pdm.s.Apic.CTX_SUFF(pfnHasPendingIrq)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns));
266 return VINF_SUCCESS;
267 }
268 *pu8TPR = 0;
269 return VERR_PDM_NO_APIC_INSTANCE;
270}
271
272/**
273 * Write MSR in APIC range.
274 *
275 * @returns VBox status code.
276 * @param pVM VM handle.
277 * @param iCpu Target CPU.
278 * @param u32Reg MSR to write.
279 * @param u64Value Value to write.
280 */
281VMMDECL(int) PDMApicWriteMSR(PVM pVM, VMCPUID iCpu, uint32_t u32Reg, uint64_t u64Value)
282{
283 if (pVM->pdm.s.Apic.CTX_SUFF(pDevIns))
284 {
285 Assert(pVM->pdm.s.Apic.CTX_SUFF(pfnWriteMSR));
286 pdmLock(pVM);
287 pVM->pdm.s.Apic.CTX_SUFF(pfnWriteMSR)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns), iCpu, u32Reg, u64Value);
288 pdmUnlock(pVM);
289 return VINF_SUCCESS;
290 }
291 return VERR_PDM_NO_APIC_INSTANCE;
292}
293
294/**
295 * Read MSR in APIC range.
296 *
297 * @returns VBox status code.
298 * @param pVM VM handle.
299 * @param iCpu Target CPU.
300 * @param u32Reg MSR to read.
301 * @param pu64Value Value read.
302 */
303VMMDECL(int) PDMApicReadMSR(PVM pVM, VMCPUID iCpu, uint32_t u32Reg, uint64_t *pu64Value)
304{
305 if (pVM->pdm.s.Apic.CTX_SUFF(pDevIns))
306 {
307 Assert(pVM->pdm.s.Apic.CTX_SUFF(pfnReadMSR));
308 pdmLock(pVM);
309 pVM->pdm.s.Apic.CTX_SUFF(pfnReadMSR)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns), iCpu, u32Reg, pu64Value);
310 pdmUnlock(pVM);
311 return VINF_SUCCESS;
312 }
313 return VERR_PDM_NO_APIC_INSTANCE;
314}
315
316
317/**
318 * Locks PDM.
319 * This might call back to Ring-3 in order to deal with lock contention in GC and R3.
320 *
321 * @param pVM The VM handle.
322 */
323void pdmLock(PVM pVM)
324{
325#ifdef IN_RING3
326 int rc = PDMCritSectEnter(&pVM->pdm.s.CritSect, VERR_INTERNAL_ERROR);
327#else
328 int rc = PDMCritSectEnter(&pVM->pdm.s.CritSect, VERR_GENERAL_FAILURE);
329 if (rc == VERR_GENERAL_FAILURE)
330 rc = VMMRZCallRing3NoCpu(pVM, VMMCALLRING3_PDM_LOCK, 0);
331#endif
332 AssertRC(rc);
333}
334
335
336/**
337 * Locks PDM but don't go to ring-3 if it's owned by someone.
338 *
339 * @returns VINF_SUCCESS on success.
340 * @returns rc if we're in GC or R0 and can't get the lock.
341 * @param pVM The VM handle.
342 * @param rc The RC to return in GC or R0 when we can't get the lock.
343 */
344int pdmLockEx(PVM pVM, int rc)
345{
346 return PDMCritSectEnter(&pVM->pdm.s.CritSect, rc);
347}
348
349
350/**
351 * Unlocks PDM.
352 *
353 * @param pVM The VM handle.
354 */
355void pdmUnlock(PVM pVM)
356{
357 PDMCritSectLeave(&pVM->pdm.s.CritSect);
358}
359
360
361/**
362 * Converts ring 3 VMM heap pointer to a guest physical address
363 *
364 * @returns VBox status code.
365 * @param pVM VM handle.
366 * @param pv Ring-3 pointer.
367 * @param pGCPhys GC phys address (out).
368 */
369VMMDECL(int) PDMVMMDevHeapR3ToGCPhys(PVM pVM, RTR3PTR pv, RTGCPHYS *pGCPhys)
370{
371 /* Don't assert here as this is called before we can catch ring-0 assertions. */
372 if (RT_UNLIKELY((RTR3UINTPTR)pv - (RTR3UINTPTR)pVM->pdm.s.pvVMMDevHeap >= pVM->pdm.s.cbVMMDevHeap))
373 {
374 Log(("PDMVMMDevHeapR3ToGCPhys: pv=%p pvVMMDevHeap=%p cbVMMDevHeap=%#x\n",
375 pv, pVM->pdm.s.pvVMMDevHeap, pVM->pdm.s.cbVMMDevHeap));
376 return VERR_INTERNAL_ERROR_3;
377 }
378
379 *pGCPhys = (pVM->pdm.s.GCPhysVMMDevHeap + ((RTR3UINTPTR)pv - (RTR3UINTPTR)pVM->pdm.s.pvVMMDevHeap));
380 return VINF_SUCCESS;
381}
382
383/**
384 * Checks if the vmm device heap is enabled (== vmm device's pci region mapped)
385 *
386 * @returns dev heap enabled status (true/false)
387 * @param pVM VM handle.
388 */
389VMMDECL(bool) PDMVMMDevHeapIsEnabled(PVM pVM)
390{
391 return (pVM->pdm.s.pvVMMDevHeap != NULL);
392}
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