VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/PDMAll.cpp@ 74065

Last change on this file since 74065 was 73285, checked in by vboxsync, 6 years ago

APIC,PDM: Avoid a few more return-to-ring-3 statuses now that we've got LogRel. Updated related (mostly) docs here and there. bugref:9044
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1/* $Id: PDMAll.cpp 73285 2018-07-21 01:49:30Z vboxsync $ */
2/** @file
3 * PDM Critical Sections
4 */
5
6/*
7 * Copyright (C) 2006-2017 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_PDM
23#include "PDMInternal.h"
24#include <VBox/vmm/pdm.h>
25#include <VBox/vmm/mm.h>
26#include <VBox/vmm/vm.h>
27#include <VBox/err.h>
28#include <VBox/vmm/apic.h>
29
30#include <VBox/log.h>
31#include <iprt/asm.h>
32#include <iprt/assert.h>
33
34#include "PDMInline.h"
35#include "dtrace/VBoxVMM.h"
36
37
38
39/**
40 * Gets the pending interrupt.
41 *
42 * @returns VBox status code.
43 * @retval VINF_SUCCESS on success.
44 * @retval VERR_APIC_INTR_MASKED_BY_TPR when an APIC interrupt is pending but
45 * can't be delivered due to TPR priority.
46 * @retval VERR_NO_DATA if there is no interrupt to be delivered (either APIC
47 * has been software-disabled since it flagged something was pending,
48 * or other reasons).
49 *
50 * @param pVCpu The cross context virtual CPU structure.
51 * @param pu8Interrupt Where to store the interrupt.
52 */
53VMMDECL(int) PDMGetInterrupt(PVMCPU pVCpu, uint8_t *pu8Interrupt)
54{
55 PVM pVM = pVCpu->CTX_SUFF(pVM);
56
57 /*
58 * The local APIC has a higher priority than the PIC.
59 */
60 int rc = VERR_NO_DATA;
61 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC))
62 {
63 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_APIC);
64 uint32_t uTagSrc;
65 rc = APICGetInterrupt(pVCpu, pu8Interrupt, &uTagSrc);
66 if (RT_SUCCESS(rc))
67 {
68 if (rc == VINF_SUCCESS)
69 VBOXVMM_PDM_IRQ_GET(pVCpu, RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc), *pu8Interrupt);
70 return rc;
71 }
72 /* else if it's masked by TPR/PPR/whatever, go ahead checking the PIC. Such masked
73 interrupts shouldn't prevent ExtINT from being delivered. */
74 }
75
76 pdmLock(pVM);
77
78 /*
79 * Check the PIC.
80 */
81 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_PIC))
82 {
83 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_PIC);
84 Assert(pVM->pdm.s.Pic.CTX_SUFF(pDevIns));
85 Assert(pVM->pdm.s.Pic.CTX_SUFF(pfnGetInterrupt));
86 uint32_t uTagSrc;
87 int i = pVM->pdm.s.Pic.CTX_SUFF(pfnGetInterrupt)(pVM->pdm.s.Pic.CTX_SUFF(pDevIns), &uTagSrc);
88 AssertMsg(i <= 255 && i >= 0, ("i=%d\n", i));
89 if (i >= 0)
90 {
91 pdmUnlock(pVM);
92 *pu8Interrupt = (uint8_t)i;
93 VBOXVMM_PDM_IRQ_GET(pVCpu, RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc), i);
94 return VINF_SUCCESS;
95 }
96 }
97
98 /*
99 * One scenario where we may possibly get here is if the APIC signaled a pending interrupt,
100 * got an APIC MMIO/MSR VM-exit which disabled the APIC. We could, in theory, clear the APIC
101 * force-flag from all the places which disables the APIC but letting PDMGetInterrupt() fail
102 * without returning a valid interrupt still needs to be handled for the TPR masked case,
103 * so we shall just handle it here regardless if we choose to update the APIC code in the future.
104 */
105
106 pdmUnlock(pVM);
107 return rc;
108}
109
110
111/**
112 * Sets the pending interrupt coming from ISA source or HPET.
113 *
114 * @returns VBox status code.
115 * @param pVM The cross context VM structure.
116 * @param u8Irq The IRQ line.
117 * @param u8Level The new level.
118 * @param uTagSrc The IRQ tag and source tracer ID.
119 */
120VMMDECL(int) PDMIsaSetIrq(PVM pVM, uint8_t u8Irq, uint8_t u8Level, uint32_t uTagSrc)
121{
122 pdmLock(pVM);
123
124 /** @todo put the IRQ13 code elsewhere to avoid this unnecessary bloat. */
125 if (!uTagSrc && (u8Level & PDM_IRQ_LEVEL_HIGH)) /* FPU IRQ */
126 {
127 if (u8Level == PDM_IRQ_LEVEL_HIGH)
128 VBOXVMM_PDM_IRQ_HIGH(VMMGetCpu(pVM), 0, 0);
129 else
130 VBOXVMM_PDM_IRQ_HILO(VMMGetCpu(pVM), 0, 0);
131 }
132
133 int rc = VERR_PDM_NO_PIC_INSTANCE;
134 if (pVM->pdm.s.Pic.CTX_SUFF(pDevIns))
135 {
136 Assert(pVM->pdm.s.Pic.CTX_SUFF(pfnSetIrq));
137 pVM->pdm.s.Pic.CTX_SUFF(pfnSetIrq)(pVM->pdm.s.Pic.CTX_SUFF(pDevIns), u8Irq, u8Level, uTagSrc);
138 rc = VINF_SUCCESS;
139 }
140
141 if (pVM->pdm.s.IoApic.CTX_SUFF(pDevIns))
142 {
143 Assert(pVM->pdm.s.IoApic.CTX_SUFF(pfnSetIrq));
144
145 /*
146 * Apply Interrupt Source Override rules.
147 * See ACPI 4.0 specification 5.2.12.4 and 5.2.12.5 for details on
148 * interrupt source override.
149 * Shortly, ISA IRQ0 is electically connected to pin 2 on IO-APIC, and some OSes,
150 * notably recent OS X rely upon this configuration.
151 * If changing, also update override rules in MADT and MPS.
152 */
153 /* ISA IRQ0 routed to pin 2, all others ISA sources are identity mapped */
154 if (u8Irq == 0)
155 u8Irq = 2;
156
157 pVM->pdm.s.IoApic.CTX_SUFF(pfnSetIrq)(pVM->pdm.s.IoApic.CTX_SUFF(pDevIns), u8Irq, u8Level, uTagSrc);
158 rc = VINF_SUCCESS;
159 }
160
161 if (!uTagSrc && u8Level == PDM_IRQ_LEVEL_LOW)
162 VBOXVMM_PDM_IRQ_LOW(VMMGetCpu(pVM), 0, 0);
163 pdmUnlock(pVM);
164 return rc;
165}
166
167
168/**
169 * Sets the pending I/O APIC interrupt.
170 *
171 * @returns VBox status code.
172 * @param pVM The cross context VM structure.
173 * @param u8Irq The IRQ line.
174 * @param u8Level The new level.
175 * @param uTagSrc The IRQ tag and source tracer ID.
176 */
177VMM_INT_DECL(int) PDMIoApicSetIrq(PVM pVM, uint8_t u8Irq, uint8_t u8Level, uint32_t uTagSrc)
178{
179 if (pVM->pdm.s.IoApic.CTX_SUFF(pDevIns))
180 {
181 Assert(pVM->pdm.s.IoApic.CTX_SUFF(pfnSetIrq));
182 pVM->pdm.s.IoApic.CTX_SUFF(pfnSetIrq)(pVM->pdm.s.IoApic.CTX_SUFF(pDevIns), u8Irq, u8Level, uTagSrc);
183 return VINF_SUCCESS;
184 }
185 return VERR_PDM_NO_PIC_INSTANCE;
186}
187
188
189/**
190 * Broadcasts an EOI to the I/O APICs.
191 *
192 * @returns Strict VBox status code - only the following informational status codes:
193 * @retval VINF_IOM_R3_MMIO_WRITE if the I/O APIC lock is contenteded and we're in R0 or RC.
194 * @retval VINF_SUCCESS
195 *
196 * @param pVM The cross context VM structure.
197 * @param uVector The interrupt vector corresponding to the EOI.
198 */
199VMM_INT_DECL(int) PDMIoApicBroadcastEoi(PVM pVM, uint8_t uVector)
200{
201 /* At present, we support only a maximum of one I/O APIC per-VM. If we ever implement having
202 multiple I/O APICs per-VM, we'll have to broadcast this EOI to all of the I/O APICs. */
203 if (pVM->pdm.s.IoApic.CTX_SUFF(pDevIns))
204 {
205 Assert(pVM->pdm.s.IoApic.CTX_SUFF(pfnSetEoi));
206 return pVM->pdm.s.IoApic.CTX_SUFF(pfnSetEoi)(pVM->pdm.s.IoApic.CTX_SUFF(pDevIns), uVector);
207 }
208
209 /* We shouldn't return failure if no I/O APIC is present. */
210 return VINF_SUCCESS;
211}
212
213
214/**
215 * Send a MSI to an I/O APIC.
216 *
217 * @returns VBox status code.
218 * @param pVM The cross context VM structure.
219 * @param GCAddr Request address.
220 * @param uValue Request value.
221 * @param uTagSrc The IRQ tag and source tracer ID.
222 */
223VMM_INT_DECL(int) PDMIoApicSendMsi(PVM pVM, RTGCPHYS GCAddr, uint32_t uValue, uint32_t uTagSrc)
224{
225 if (pVM->pdm.s.IoApic.CTX_SUFF(pDevIns))
226 {
227 Assert(pVM->pdm.s.IoApic.CTX_SUFF(pfnSendMsi));
228 pVM->pdm.s.IoApic.CTX_SUFF(pfnSendMsi)(pVM->pdm.s.IoApic.CTX_SUFF(pDevIns), GCAddr, uValue, uTagSrc);
229 return VINF_SUCCESS;
230 }
231 return VERR_PDM_NO_PIC_INSTANCE;
232}
233
234
235
236/**
237 * Returns the presence of an IO-APIC.
238 *
239 * @returns true if an IO-APIC is present.
240 * @param pVM The cross context VM structure.
241 */
242VMM_INT_DECL(bool) PDMHasIoApic(PVM pVM)
243{
244 return pVM->pdm.s.IoApic.CTX_SUFF(pDevIns) != NULL;
245}
246
247
248/**
249 * Returns the presence of an APIC.
250 *
251 * @returns true if an APIC is present.
252 * @param pVM The cross context VM structure.
253 */
254VMM_INT_DECL(bool) PDMHasApic(PVM pVM)
255{
256 return pVM->pdm.s.Apic.CTX_SUFF(pDevIns) != NULL;
257}
258
259
260/**
261 * Locks PDM.
262 * This might call back to Ring-3 in order to deal with lock contention in GC and R3.
263 *
264 * @param pVM The cross context VM structure.
265 */
266void pdmLock(PVM pVM)
267{
268#ifdef IN_RING3
269 int rc = PDMCritSectEnter(&pVM->pdm.s.CritSect, VERR_IGNORED);
270#else
271 int rc = PDMCritSectEnter(&pVM->pdm.s.CritSect, VERR_GENERAL_FAILURE);
272 if (rc == VERR_GENERAL_FAILURE)
273 rc = VMMRZCallRing3NoCpu(pVM, VMMCALLRING3_PDM_LOCK, 0);
274#endif
275 AssertRC(rc);
276}
277
278
279/**
280 * Locks PDM but don't go to ring-3 if it's owned by someone.
281 *
282 * @returns VINF_SUCCESS on success.
283 * @returns rc if we're in GC or R0 and can't get the lock.
284 * @param pVM The cross context VM structure.
285 * @param rc The RC to return in GC or R0 when we can't get the lock.
286 */
287int pdmLockEx(PVM pVM, int rc)
288{
289 return PDMCritSectEnter(&pVM->pdm.s.CritSect, rc);
290}
291
292
293/**
294 * Unlocks PDM.
295 *
296 * @param pVM The cross context VM structure.
297 */
298void pdmUnlock(PVM pVM)
299{
300 PDMCritSectLeave(&pVM->pdm.s.CritSect);
301}
302
303
304/**
305 * Converts ring 3 VMM heap pointer to a guest physical address
306 *
307 * @returns VBox status code.
308 * @param pVM The cross context VM structure.
309 * @param pv Ring-3 pointer.
310 * @param pGCPhys GC phys address (out).
311 */
312VMM_INT_DECL(int) PDMVmmDevHeapR3ToGCPhys(PVM pVM, RTR3PTR pv, RTGCPHYS *pGCPhys)
313{
314 if (RT_LIKELY(pVM->pdm.s.GCPhysVMMDevHeap != NIL_RTGCPHYS))
315 {
316 RTR3UINTPTR const offHeap = (RTR3UINTPTR)pv - (RTR3UINTPTR)pVM->pdm.s.pvVMMDevHeap;
317 if (RT_LIKELY(offHeap < pVM->pdm.s.cbVMMDevHeap))
318 {
319 *pGCPhys = pVM->pdm.s.GCPhysVMMDevHeap + offHeap;
320 return VINF_SUCCESS;
321 }
322
323 /* Don't assert here as this is called before we can catch ring-0 assertions. */
324 Log(("PDMVmmDevHeapR3ToGCPhys: pv=%p pvVMMDevHeap=%p cbVMMDevHeap=%#x\n",
325 pv, pVM->pdm.s.pvVMMDevHeap, pVM->pdm.s.cbVMMDevHeap));
326 }
327 else
328 Log(("PDMVmmDevHeapR3ToGCPhys: GCPhysVMMDevHeap=%RGp (pv=%p)\n", pVM->pdm.s.GCPhysVMMDevHeap, pv));
329 return VERR_PDM_DEV_HEAP_R3_TO_GCPHYS;
330}
331
332
333/**
334 * Checks if the vmm device heap is enabled (== vmm device's pci region mapped)
335 *
336 * @returns dev heap enabled status (true/false)
337 * @param pVM The cross context VM structure.
338 */
339VMM_INT_DECL(bool) PDMVmmDevHeapIsEnabled(PVM pVM)
340{
341 return pVM->pdm.s.GCPhysVMMDevHeap != NIL_RTGCPHYS;
342}
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