VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/PDMAll.cpp@ 86667

Last change on this file since 86667 was 84826, checked in by vboxsync, 4 years ago

AMD IOMMU: bugref:9654 PDM interface changes for supplying bus:device:function for devices' initiating PCI interrupts and MSIs.
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1/* $Id: PDMAll.cpp 84826 2020-06-15 08:20:40Z vboxsync $ */
2/** @file
3 * PDM Critical Sections
4 */
5
6/*
7 * Copyright (C) 2006-2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_PDM
23#include "PDMInternal.h"
24#include <VBox/vmm/pdm.h>
25#include <VBox/vmm/mm.h>
26#include <VBox/vmm/vmcc.h>
27#include <VBox/err.h>
28#include <VBox/vmm/apic.h>
29
30#include <VBox/log.h>
31#include <iprt/asm.h>
32#include <iprt/assert.h>
33
34#include "PDMInline.h"
35#include "dtrace/VBoxVMM.h"
36
37
38
39/**
40 * Gets the pending interrupt.
41 *
42 * @returns VBox status code.
43 * @retval VINF_SUCCESS on success.
44 * @retval VERR_APIC_INTR_MASKED_BY_TPR when an APIC interrupt is pending but
45 * can't be delivered due to TPR priority.
46 * @retval VERR_NO_DATA if there is no interrupt to be delivered (either APIC
47 * has been software-disabled since it flagged something was pending,
48 * or other reasons).
49 *
50 * @param pVCpu The cross context virtual CPU structure.
51 * @param pu8Interrupt Where to store the interrupt.
52 */
53VMMDECL(int) PDMGetInterrupt(PVMCPUCC pVCpu, uint8_t *pu8Interrupt)
54{
55 /*
56 * The local APIC has a higher priority than the PIC.
57 */
58 int rc = VERR_NO_DATA;
59 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC))
60 {
61 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_APIC);
62 uint32_t uTagSrc;
63 rc = APICGetInterrupt(pVCpu, pu8Interrupt, &uTagSrc);
64 if (RT_SUCCESS(rc))
65 {
66 if (rc == VINF_SUCCESS)
67 VBOXVMM_PDM_IRQ_GET(pVCpu, RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc), *pu8Interrupt);
68 return rc;
69 }
70 /* else if it's masked by TPR/PPR/whatever, go ahead checking the PIC. Such masked
71 interrupts shouldn't prevent ExtINT from being delivered. */
72 }
73
74 PVMCC pVM = pVCpu->CTX_SUFF(pVM);
75 pdmLock(pVM);
76
77 /*
78 * Check the PIC.
79 */
80 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_PIC))
81 {
82 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_PIC);
83 Assert(pVM->pdm.s.Pic.CTX_SUFF(pDevIns));
84 Assert(pVM->pdm.s.Pic.CTX_SUFF(pfnGetInterrupt));
85 uint32_t uTagSrc;
86 int i = pVM->pdm.s.Pic.CTX_SUFF(pfnGetInterrupt)(pVM->pdm.s.Pic.CTX_SUFF(pDevIns), &uTagSrc);
87 AssertMsg(i <= 255 && i >= 0, ("i=%d\n", i));
88 if (i >= 0)
89 {
90 pdmUnlock(pVM);
91 *pu8Interrupt = (uint8_t)i;
92 VBOXVMM_PDM_IRQ_GET(pVCpu, RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc), i);
93 return VINF_SUCCESS;
94 }
95 }
96
97 /*
98 * One scenario where we may possibly get here is if the APIC signaled a pending interrupt,
99 * got an APIC MMIO/MSR VM-exit which disabled the APIC. We could, in theory, clear the APIC
100 * force-flag from all the places which disables the APIC but letting PDMGetInterrupt() fail
101 * without returning a valid interrupt still needs to be handled for the TPR masked case,
102 * so we shall just handle it here regardless if we choose to update the APIC code in the future.
103 */
104
105 pdmUnlock(pVM);
106 return rc;
107}
108
109
110/**
111 * Sets the pending interrupt coming from ISA source or HPET.
112 *
113 * @returns VBox status code.
114 * @param pVM The cross context VM structure.
115 * @param u8Irq The IRQ line.
116 * @param u8Level The new level.
117 * @param uTagSrc The IRQ tag and source tracer ID.
118 */
119VMMDECL(int) PDMIsaSetIrq(PVMCC pVM, uint8_t u8Irq, uint8_t u8Level, uint32_t uTagSrc)
120{
121 pdmLock(pVM);
122
123 /** @todo put the IRQ13 code elsewhere to avoid this unnecessary bloat. */
124 if (!uTagSrc && (u8Level & PDM_IRQ_LEVEL_HIGH)) /* FPU IRQ */
125 {
126 if (u8Level == PDM_IRQ_LEVEL_HIGH)
127 VBOXVMM_PDM_IRQ_HIGH(VMMGetCpu(pVM), 0, 0);
128 else
129 VBOXVMM_PDM_IRQ_HILO(VMMGetCpu(pVM), 0, 0);
130 }
131
132 int rc = VERR_PDM_NO_PIC_INSTANCE;
133/** @todo r=bird: This code is incorrect, as it ASSUMES the PIC and I/O APIC
134 * are always ring-0 enabled! */
135 if (pVM->pdm.s.Pic.CTX_SUFF(pDevIns))
136 {
137 Assert(pVM->pdm.s.Pic.CTX_SUFF(pfnSetIrq));
138 pVM->pdm.s.Pic.CTX_SUFF(pfnSetIrq)(pVM->pdm.s.Pic.CTX_SUFF(pDevIns), u8Irq, u8Level, uTagSrc);
139 rc = VINF_SUCCESS;
140 }
141
142 if (pVM->pdm.s.IoApic.CTX_SUFF(pDevIns))
143 {
144 Assert(pVM->pdm.s.IoApic.CTX_SUFF(pfnSetIrq));
145
146 /*
147 * Apply Interrupt Source Override rules.
148 * See ACPI 4.0 specification 5.2.12.4 and 5.2.12.5 for details on
149 * interrupt source override.
150 * Shortly, ISA IRQ0 is electically connected to pin 2 on IO-APIC, and some OSes,
151 * notably recent OS X rely upon this configuration.
152 * If changing, also update override rules in MADT and MPS.
153 */
154 /* ISA IRQ0 routed to pin 2, all others ISA sources are identity mapped */
155 if (u8Irq == 0)
156 u8Irq = 2;
157
158 pVM->pdm.s.IoApic.CTX_SUFF(pfnSetIrq)(pVM->pdm.s.IoApic.CTX_SUFF(pDevIns), NIL_PCIBDF, u8Irq, u8Level, uTagSrc);
159 rc = VINF_SUCCESS;
160 }
161
162 if (!uTagSrc && u8Level == PDM_IRQ_LEVEL_LOW)
163 VBOXVMM_PDM_IRQ_LOW(VMMGetCpu(pVM), 0, 0);
164 pdmUnlock(pVM);
165 return rc;
166}
167
168
169/**
170 * Sets the pending I/O APIC interrupt.
171 *
172 * @returns VBox status code.
173 * @param pVM The cross context VM structure.
174 * @param u8Irq The IRQ line.
175 * @param uBusDevFn The bus:device:function of the device initiating the IRQ.
176 * Pass NIL_PCIBDF when it's not a PCI device or interrupt.
177 * @param u8Level The new level.
178 * @param uTagSrc The IRQ tag and source tracer ID.
179 */
180VMM_INT_DECL(int) PDMIoApicSetIrq(PVM pVM, PCIBDF uBusDevFn, uint8_t u8Irq, uint8_t u8Level, uint32_t uTagSrc)
181{
182 if (pVM->pdm.s.IoApic.CTX_SUFF(pDevIns))
183 {
184 Assert(pVM->pdm.s.IoApic.CTX_SUFF(pfnSetIrq));
185 pVM->pdm.s.IoApic.CTX_SUFF(pfnSetIrq)(pVM->pdm.s.IoApic.CTX_SUFF(pDevIns), uBusDevFn, u8Irq, u8Level, uTagSrc);
186 return VINF_SUCCESS;
187 }
188 return VERR_PDM_NO_PIC_INSTANCE;
189}
190
191
192/**
193 * Broadcasts an EOI to the I/O APICs.
194 *
195 * @returns Strict VBox status code - only the following informational status codes:
196 * @retval VINF_IOM_R3_MMIO_WRITE if the I/O APIC lock is contenteded and we're in R0 or RC.
197 * @retval VINF_SUCCESS
198 *
199 * @param pVM The cross context VM structure.
200 * @param uVector The interrupt vector corresponding to the EOI.
201 */
202VMM_INT_DECL(VBOXSTRICTRC) PDMIoApicBroadcastEoi(PVM pVM, uint8_t uVector)
203{
204 /* At present, we support only a maximum of one I/O APIC per-VM. If we ever implement having
205 multiple I/O APICs per-VM, we'll have to broadcast this EOI to all of the I/O APICs. */
206 if (pVM->pdm.s.IoApic.CTX_SUFF(pDevIns))
207 {
208 Assert(pVM->pdm.s.IoApic.CTX_SUFF(pfnSetEoi));
209 return pVM->pdm.s.IoApic.CTX_SUFF(pfnSetEoi)(pVM->pdm.s.IoApic.CTX_SUFF(pDevIns), uVector);
210 }
211
212 /* We shouldn't return failure if no I/O APIC is present. */
213 return VINF_SUCCESS;
214}
215
216
217/**
218 * Send a MSI to an I/O APIC.
219 *
220 * @returns VBox status code.
221 * @param pVM The cross context VM structure.
222 * @param uBusDevFn The bus:device:function of the device initiating the MSI.
223 * Cannot be NIL_PCIBDF.
224 * @param pMsi The MSI to send.
225 * @param uTagSrc The IRQ tag and source tracer ID.
226 */
227VMM_INT_DECL(int) PDMIoApicSendMsi(PVM pVM, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc)
228{
229 Assert(PCIBDF_IS_VALID(uBusDevFn));
230 if (pVM->pdm.s.IoApic.CTX_SUFF(pDevIns))
231 {
232 Assert(pVM->pdm.s.IoApic.CTX_SUFF(pfnSendMsi));
233 pVM->pdm.s.IoApic.CTX_SUFF(pfnSendMsi)(pVM->pdm.s.IoApic.CTX_SUFF(pDevIns), uBusDevFn, pMsi, uTagSrc);
234 return VINF_SUCCESS;
235 }
236 return VERR_PDM_NO_PIC_INSTANCE;
237}
238
239
240
241/**
242 * Returns the presence of an IO-APIC.
243 *
244 * @returns true if an IO-APIC is present.
245 * @param pVM The cross context VM structure.
246 */
247VMM_INT_DECL(bool) PDMHasIoApic(PVM pVM)
248{
249 return pVM->pdm.s.IoApic.pDevInsR3 != NULL;
250}
251
252
253/**
254 * Returns the presence of an APIC.
255 *
256 * @returns true if an APIC is present.
257 * @param pVM The cross context VM structure.
258 */
259VMM_INT_DECL(bool) PDMHasApic(PVM pVM)
260{
261 return pVM->pdm.s.Apic.pDevInsR3 != NIL_RTR3PTR;
262}
263
264
265/**
266 * Locks PDM.
267 * This might call back to Ring-3 in order to deal with lock contention in GC and R3.
268 *
269 * @param pVM The cross context VM structure.
270 */
271void pdmLock(PVMCC pVM)
272{
273#ifdef IN_RING3
274 int rc = PDMCritSectEnter(&pVM->pdm.s.CritSect, VERR_IGNORED);
275#else
276 int rc = PDMCritSectEnter(&pVM->pdm.s.CritSect, VERR_GENERAL_FAILURE);
277 if (rc == VERR_GENERAL_FAILURE)
278 rc = VMMRZCallRing3NoCpu(pVM, VMMCALLRING3_PDM_LOCK, 0);
279#endif
280 AssertRC(rc);
281}
282
283
284/**
285 * Locks PDM but don't go to ring-3 if it's owned by someone.
286 *
287 * @returns VINF_SUCCESS on success.
288 * @returns rc if we're in GC or R0 and can't get the lock.
289 * @param pVM The cross context VM structure.
290 * @param rc The RC to return in GC or R0 when we can't get the lock.
291 */
292int pdmLockEx(PVMCC pVM, int rc)
293{
294 return PDMCritSectEnter(&pVM->pdm.s.CritSect, rc);
295}
296
297
298/**
299 * Unlocks PDM.
300 *
301 * @param pVM The cross context VM structure.
302 */
303void pdmUnlock(PVMCC pVM)
304{
305 PDMCritSectLeave(&pVM->pdm.s.CritSect);
306}
307
308
309/**
310 * Converts ring 3 VMM heap pointer to a guest physical address
311 *
312 * @returns VBox status code.
313 * @param pVM The cross context VM structure.
314 * @param pv Ring-3 pointer.
315 * @param pGCPhys GC phys address (out).
316 */
317VMM_INT_DECL(int) PDMVmmDevHeapR3ToGCPhys(PVM pVM, RTR3PTR pv, RTGCPHYS *pGCPhys)
318{
319 if (RT_LIKELY(pVM->pdm.s.GCPhysVMMDevHeap != NIL_RTGCPHYS))
320 {
321 RTR3UINTPTR const offHeap = (RTR3UINTPTR)pv - (RTR3UINTPTR)pVM->pdm.s.pvVMMDevHeap;
322 if (RT_LIKELY(offHeap < pVM->pdm.s.cbVMMDevHeap))
323 {
324 *pGCPhys = pVM->pdm.s.GCPhysVMMDevHeap + offHeap;
325 return VINF_SUCCESS;
326 }
327
328 /* Don't assert here as this is called before we can catch ring-0 assertions. */
329 Log(("PDMVmmDevHeapR3ToGCPhys: pv=%p pvVMMDevHeap=%p cbVMMDevHeap=%#x\n",
330 pv, pVM->pdm.s.pvVMMDevHeap, pVM->pdm.s.cbVMMDevHeap));
331 }
332 else
333 Log(("PDMVmmDevHeapR3ToGCPhys: GCPhysVMMDevHeap=%RGp (pv=%p)\n", pVM->pdm.s.GCPhysVMMDevHeap, pv));
334 return VERR_PDM_DEV_HEAP_R3_TO_GCPHYS;
335}
336
337
338/**
339 * Checks if the vmm device heap is enabled (== vmm device's pci region mapped)
340 *
341 * @returns dev heap enabled status (true/false)
342 * @param pVM The cross context VM structure.
343 */
344VMM_INT_DECL(bool) PDMVmmDevHeapIsEnabled(PVM pVM)
345{
346 return pVM->pdm.s.GCPhysVMMDevHeap != NIL_RTGCPHYS;
347}
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