VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/PDMAll.cpp@ 99299

Last change on this file since 99299 was 99051, checked in by vboxsync, 21 months ago

VMM: More ARMv8 x86/amd64 separation work, VBoxVMMArm compiles and links now, bugref:10385
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1/* $Id: PDMAll.cpp 99051 2023-03-19 16:40:06Z vboxsync $ */
2/** @file
3 * PDM Critical Sections
4 */
5
6/*
7 * Copyright (C) 2006-2023 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28
29/*********************************************************************************************************************************
30* Header Files *
31*********************************************************************************************************************************/
32#define LOG_GROUP LOG_GROUP_PDM
33#include "PDMInternal.h"
34#include <VBox/vmm/pdm.h>
35#include <VBox/vmm/mm.h>
36#include <VBox/vmm/vmcc.h>
37#include <VBox/err.h>
38#include <VBox/vmm/apic.h>
39
40#include <VBox/log.h>
41#include <iprt/asm.h>
42#include <iprt/assert.h>
43
44#include "PDMInline.h"
45#include "dtrace/VBoxVMM.h"
46
47
48
49/**
50 * Gets the pending interrupt.
51 *
52 * @returns VBox status code.
53 * @retval VINF_SUCCESS on success.
54 * @retval VERR_APIC_INTR_MASKED_BY_TPR when an APIC interrupt is pending but
55 * can't be delivered due to TPR priority.
56 * @retval VERR_NO_DATA if there is no interrupt to be delivered (either APIC
57 * has been software-disabled since it flagged something was pending,
58 * or other reasons).
59 *
60 * @param pVCpu The cross context virtual CPU structure.
61 * @param pu8Interrupt Where to store the interrupt.
62 */
63VMMDECL(int) PDMGetInterrupt(PVMCPUCC pVCpu, uint8_t *pu8Interrupt)
64{
65 /*
66 * The local APIC has a higher priority than the PIC.
67 */
68 int rc = VERR_NO_DATA;
69 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC))
70 {
71 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_APIC);
72#if defined(VBOX_VMM_TARGET_ARMV8)
73 AssertReleaseFailed();
74#else
75 uint32_t uTagSrc;
76 rc = APICGetInterrupt(pVCpu, pu8Interrupt, &uTagSrc);
77 if (RT_SUCCESS(rc))
78 {
79 VBOXVMM_PDM_IRQ_GET(pVCpu, RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc), *pu8Interrupt);
80 Log8(("PDMGetInterrupt: irq=%#x tag=%#x (apic)\n", *pu8Interrupt, uTagSrc));
81 return VINF_SUCCESS;
82 }
83 /* else if it's masked by TPR/PPR/whatever, go ahead checking the PIC. Such masked
84 interrupts shouldn't prevent ExtINT from being delivered. */
85#endif
86 }
87
88 PVMCC pVM = pVCpu->CTX_SUFF(pVM);
89 pdmLock(pVM);
90
91 /*
92 * Check the PIC.
93 */
94 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_PIC))
95 {
96 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_PIC);
97 Assert(pVM->pdm.s.Pic.CTX_SUFF(pDevIns));
98 Assert(pVM->pdm.s.Pic.CTX_SUFF(pfnGetInterrupt));
99 uint32_t uTagSrc;
100 int i = pVM->pdm.s.Pic.CTX_SUFF(pfnGetInterrupt)(pVM->pdm.s.Pic.CTX_SUFF(pDevIns), &uTagSrc);
101 AssertMsg(i <= 255 && i >= 0, ("i=%d\n", i));
102 if (i >= 0)
103 {
104 pdmUnlock(pVM);
105 *pu8Interrupt = (uint8_t)i;
106 VBOXVMM_PDM_IRQ_GET(pVCpu, RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc), i);
107 Log8(("PDMGetInterrupt: irq=%#x tag=%#x (pic)\n", i, uTagSrc));
108 return VINF_SUCCESS;
109 }
110 }
111
112 /*
113 * One scenario where we may possibly get here is if the APIC signaled a pending interrupt,
114 * got an APIC MMIO/MSR VM-exit which disabled the APIC. We could, in theory, clear the APIC
115 * force-flag from all the places which disables the APIC but letting PDMGetInterrupt() fail
116 * without returning a valid interrupt still needs to be handled for the TPR masked case,
117 * so we shall just handle it here regardless if we choose to update the APIC code in the future.
118 */
119
120 pdmUnlock(pVM);
121 return rc;
122}
123
124
125/**
126 * Sets the pending interrupt coming from ISA source or HPET.
127 *
128 * @returns VBox status code.
129 * @param pVM The cross context VM structure.
130 * @param u8Irq The IRQ line.
131 * @param u8Level The new level.
132 * @param uTagSrc The IRQ tag and source tracer ID.
133 */
134VMMDECL(int) PDMIsaSetIrq(PVMCC pVM, uint8_t u8Irq, uint8_t u8Level, uint32_t uTagSrc)
135{
136 pdmLock(pVM);
137
138 /** @todo put the IRQ13 code elsewhere to avoid this unnecessary bloat. */
139 if (!uTagSrc && (u8Level & PDM_IRQ_LEVEL_HIGH)) /* FPU IRQ */
140 {
141 if (u8Level == PDM_IRQ_LEVEL_HIGH)
142 VBOXVMM_PDM_IRQ_HIGH(VMMGetCpu(pVM), 0, 0);
143 else
144 VBOXVMM_PDM_IRQ_HILO(VMMGetCpu(pVM), 0, 0);
145 }
146 Log9(("PDMIsaSetIrq: irq=%#x lvl=%u tag=%#x\n", u8Irq, u8Level, uTagSrc));
147
148 int rc = VERR_PDM_NO_PIC_INSTANCE;
149/** @todo r=bird: This code is incorrect, as it ASSUMES the PIC and I/O APIC
150 * are always ring-0 enabled! */
151 if (pVM->pdm.s.Pic.CTX_SUFF(pDevIns))
152 {
153 Assert(pVM->pdm.s.Pic.CTX_SUFF(pfnSetIrq));
154 pVM->pdm.s.Pic.CTX_SUFF(pfnSetIrq)(pVM->pdm.s.Pic.CTX_SUFF(pDevIns), u8Irq, u8Level, uTagSrc);
155 rc = VINF_SUCCESS;
156 }
157
158 if (pVM->pdm.s.IoApic.CTX_SUFF(pDevIns))
159 {
160 Assert(pVM->pdm.s.IoApic.CTX_SUFF(pfnSetIrq));
161
162 /*
163 * Apply Interrupt Source Override rules.
164 * See ACPI 4.0 specification 5.2.12.4 and 5.2.12.5 for details on
165 * interrupt source override.
166 * Shortly, ISA IRQ0 is electically connected to pin 2 on IO-APIC, and some OSes,
167 * notably recent OS X rely upon this configuration.
168 * If changing, also update override rules in MADT and MPS.
169 */
170 /* ISA IRQ0 routed to pin 2, all others ISA sources are identity mapped */
171 if (u8Irq == 0)
172 u8Irq = 2;
173
174 pVM->pdm.s.IoApic.CTX_SUFF(pfnSetIrq)(pVM->pdm.s.IoApic.CTX_SUFF(pDevIns), NIL_PCIBDF, u8Irq, u8Level, uTagSrc);
175 rc = VINF_SUCCESS;
176 }
177
178 if (!uTagSrc && u8Level == PDM_IRQ_LEVEL_LOW)
179 VBOXVMM_PDM_IRQ_LOW(VMMGetCpu(pVM), 0, 0);
180 pdmUnlock(pVM);
181 return rc;
182}
183
184
185/**
186 * Sets the pending I/O APIC interrupt.
187 *
188 * @returns VBox status code.
189 * @param pVM The cross context VM structure.
190 * @param u8Irq The IRQ line.
191 * @param uBusDevFn The bus:device:function of the device initiating the IRQ.
192 * Pass NIL_PCIBDF when it's not a PCI device or interrupt.
193 * @param u8Level The new level.
194 * @param uTagSrc The IRQ tag and source tracer ID.
195 */
196VMM_INT_DECL(int) PDMIoApicSetIrq(PVM pVM, PCIBDF uBusDevFn, uint8_t u8Irq, uint8_t u8Level, uint32_t uTagSrc)
197{
198 Log9(("PDMIoApicSetIrq: irq=%#x lvl=%u tag=%#x src=%#x\n", u8Irq, u8Level, uTagSrc, uBusDevFn));
199 if (pVM->pdm.s.IoApic.CTX_SUFF(pDevIns))
200 {
201 Assert(pVM->pdm.s.IoApic.CTX_SUFF(pfnSetIrq));
202 pVM->pdm.s.IoApic.CTX_SUFF(pfnSetIrq)(pVM->pdm.s.IoApic.CTX_SUFF(pDevIns), uBusDevFn, u8Irq, u8Level, uTagSrc);
203 return VINF_SUCCESS;
204 }
205 return VERR_PDM_NO_PIC_INSTANCE;
206}
207
208
209/**
210 * Broadcasts an EOI to the I/O APIC(s).
211 *
212 * @param pVM The cross context VM structure.
213 * @param uVector The interrupt vector corresponding to the EOI.
214 */
215VMM_INT_DECL(void) PDMIoApicBroadcastEoi(PVMCC pVM, uint8_t uVector)
216{
217 /*
218 * At present, we support only a maximum of one I/O APIC per-VM. If we ever implement having
219 * multiple I/O APICs per-VM, we'll have to broadcast this EOI to all of the I/O APICs.
220 */
221 PCPDMIOAPIC pIoApic = &pVM->pdm.s.IoApic;
222#ifdef IN_RING0
223 if (pIoApic->pDevInsR0)
224 {
225 Assert(pIoApic->pfnSetEoiR0);
226 pIoApic->pfnSetEoiR0(pIoApic->pDevInsR0, uVector);
227 }
228 else if (pIoApic->pDevInsR3)
229 {
230 /* Queue for ring-3 execution. */
231 PPDMDEVHLPTASK pTask = (PPDMDEVHLPTASK)PDMQueueAlloc(pVM, pVM->pdm.s.hDevHlpQueue, pVM);
232 if (pTask)
233 {
234 pTask->enmOp = PDMDEVHLPTASKOP_IOAPIC_SET_EOI;
235 pTask->pDevInsR3 = NIL_RTR3PTR; /* not required */
236 pTask->u.IoApicSetEoi.uVector = uVector;
237 PDMQueueInsert(pVM, pVM->pdm.s.hDevHlpQueue, pVM, &pTask->Core);
238 }
239 else
240 AssertMsgFailed(("We're out of devhlp queue items!!!\n"));
241 }
242#else
243 if (pIoApic->pDevInsR3)
244 {
245 Assert(pIoApic->pfnSetEoiR3);
246 pIoApic->pfnSetEoiR3(pIoApic->pDevInsR3, uVector);
247 }
248#endif
249}
250
251
252/**
253 * Send a MSI to an I/O APIC.
254 *
255 * @param pVM The cross context VM structure.
256 * @param uBusDevFn The bus:device:function of the device initiating the MSI.
257 * @param pMsi The MSI to send.
258 * @param uTagSrc The IRQ tag and source tracer ID.
259 */
260VMM_INT_DECL(void) PDMIoApicSendMsi(PVMCC pVM, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc)
261{
262 Log9(("PDMIoApicSendMsi: addr=%#RX64 data=%#RX32 tag=%#x src=%#x\n", pMsi->Addr.u64, pMsi->Data.u32, uTagSrc, uBusDevFn));
263 PCPDMIOAPIC pIoApic = &pVM->pdm.s.IoApic;
264#ifdef IN_RING0
265 if (pIoApic->pDevInsR0)
266 pIoApic->pfnSendMsiR0(pIoApic->pDevInsR0, uBusDevFn, pMsi, uTagSrc);
267 else if (pIoApic->pDevInsR3)
268 {
269 /* Queue for ring-3 execution. */
270 PPDMDEVHLPTASK pTask = (PPDMDEVHLPTASK)PDMQueueAlloc(pVM, pVM->pdm.s.hDevHlpQueue, pVM);
271 if (pTask)
272 {
273 pTask->enmOp = PDMDEVHLPTASKOP_IOAPIC_SEND_MSI;
274 pTask->pDevInsR3 = NIL_RTR3PTR; /* not required */
275 pTask->u.IoApicSendMsi.uBusDevFn = uBusDevFn;
276 pTask->u.IoApicSendMsi.Msi = *pMsi;
277 pTask->u.IoApicSendMsi.uTagSrc = uTagSrc;
278 PDMQueueInsert(pVM, pVM->pdm.s.hDevHlpQueue, pVM, &pTask->Core);
279 }
280 else
281 AssertMsgFailed(("We're out of devhlp queue items!!!\n"));
282 }
283#else
284 if (pIoApic->pDevInsR3)
285 {
286 Assert(pIoApic->pfnSendMsiR3);
287 pIoApic->pfnSendMsiR3(pIoApic->pDevInsR3, uBusDevFn, pMsi, uTagSrc);
288 }
289#endif
290}
291
292
293
294/**
295 * Returns the presence of an IO-APIC.
296 *
297 * @returns true if an IO-APIC is present.
298 * @param pVM The cross context VM structure.
299 */
300VMM_INT_DECL(bool) PDMHasIoApic(PVM pVM)
301{
302 return pVM->pdm.s.IoApic.pDevInsR3 != NULL;
303}
304
305
306/**
307 * Returns the presence of an APIC.
308 *
309 * @returns true if an APIC is present.
310 * @param pVM The cross context VM structure.
311 */
312VMM_INT_DECL(bool) PDMHasApic(PVM pVM)
313{
314 return pVM->pdm.s.Apic.pDevInsR3 != NIL_RTR3PTR;
315}
316
317
318/**
319 * Translates a ring-0 device instance index to a pointer.
320 *
321 * This is used by PGM for device access handlers.
322 *
323 * @returns Device instance pointer if valid index, otherwise NULL (asserted).
324 * @param pVM The cross context VM structure.
325 * @param idxR0Device The ring-0 device instance index.
326 */
327VMM_INT_DECL(PPDMDEVINS) PDMDeviceRing0IdxToInstance(PVMCC pVM, uint64_t idxR0Device)
328{
329#ifdef IN_RING0
330 AssertMsgReturn(idxR0Device < RT_ELEMENTS(pVM->pdmr0.s.apDevInstances), ("%#RX64\n", idxR0Device), NULL);
331 PPDMDEVINS pDevIns = pVM->pdmr0.s.apDevInstances[idxR0Device];
332#elif defined(IN_RING3)
333 AssertMsgReturn(idxR0Device < RT_ELEMENTS(pVM->pdm.s.apDevRing0Instances), ("%#RX64\n", idxR0Device), NULL);
334 PPDMDEVINS pDevIns = pVM->pdm.s.apDevRing0Instances[idxR0Device];
335#else
336# error "Unsupported context"
337#endif
338 AssertMsg(pDevIns, ("%#RX64\n", idxR0Device));
339 return pDevIns;
340}
341
342
343/**
344 * Locks PDM.
345 *
346 * This might block.
347 *
348 * @param pVM The cross context VM structure.
349 */
350void pdmLock(PVMCC pVM)
351{
352 int rc = PDMCritSectEnter(pVM, &pVM->pdm.s.CritSect, VINF_SUCCESS);
353 PDM_CRITSECT_RELEASE_ASSERT_RC(pVM, &pVM->pdm.s.CritSect, rc);
354}
355
356
357/**
358 * Locks PDM but don't go to ring-3 if it's owned by someone.
359 *
360 * @returns VINF_SUCCESS on success.
361 * @returns rc if we're in GC or R0 and can't get the lock.
362 * @param pVM The cross context VM structure.
363 * @param rcBusy The RC to return in GC or R0 when we can't get the lock.
364 */
365int pdmLockEx(PVMCC pVM, int rcBusy)
366{
367 return PDMCritSectEnter(pVM, &pVM->pdm.s.CritSect, rcBusy);
368}
369
370
371/**
372 * Unlocks PDM.
373 *
374 * @param pVM The cross context VM structure.
375 */
376void pdmUnlock(PVMCC pVM)
377{
378 PDMCritSectLeave(pVM, &pVM->pdm.s.CritSect);
379}
380
381
382/**
383 * Checks if this thread is owning the PDM lock.
384 *
385 * @returns @c true if the lock is taken, @c false otherwise.
386 * @param pVM The cross context VM structure.
387 */
388bool pdmLockIsOwner(PVMCC pVM)
389{
390 return PDMCritSectIsOwner(pVM, &pVM->pdm.s.CritSect);
391}
392
393
394/**
395 * Converts ring 3 VMM heap pointer to a guest physical address
396 *
397 * @returns VBox status code.
398 * @param pVM The cross context VM structure.
399 * @param pv Ring-3 pointer.
400 * @param pGCPhys GC phys address (out).
401 */
402VMM_INT_DECL(int) PDMVmmDevHeapR3ToGCPhys(PVM pVM, RTR3PTR pv, RTGCPHYS *pGCPhys)
403{
404 if (RT_LIKELY(pVM->pdm.s.GCPhysVMMDevHeap != NIL_RTGCPHYS))
405 {
406 RTR3UINTPTR const offHeap = (RTR3UINTPTR)pv - (RTR3UINTPTR)pVM->pdm.s.pvVMMDevHeap;
407 if (RT_LIKELY(offHeap < pVM->pdm.s.cbVMMDevHeap))
408 {
409 *pGCPhys = pVM->pdm.s.GCPhysVMMDevHeap + offHeap;
410 return VINF_SUCCESS;
411 }
412
413 /* Don't assert here as this is called before we can catch ring-0 assertions. */
414 Log(("PDMVmmDevHeapR3ToGCPhys: pv=%p pvVMMDevHeap=%p cbVMMDevHeap=%#x\n",
415 pv, pVM->pdm.s.pvVMMDevHeap, pVM->pdm.s.cbVMMDevHeap));
416 }
417 else
418 Log(("PDMVmmDevHeapR3ToGCPhys: GCPhysVMMDevHeap=%RGp (pv=%p)\n", pVM->pdm.s.GCPhysVMMDevHeap, pv));
419 return VERR_PDM_DEV_HEAP_R3_TO_GCPHYS;
420}
421
422
423/**
424 * Checks if the vmm device heap is enabled (== vmm device's pci region mapped)
425 *
426 * @returns dev heap enabled status (true/false)
427 * @param pVM The cross context VM structure.
428 */
429VMM_INT_DECL(bool) PDMVmmDevHeapIsEnabled(PVM pVM)
430{
431 return pVM->pdm.s.GCPhysVMMDevHeap != NIL_RTGCPHYS;
432}
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