VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/PDMAll.cpp@ 99863

Last change on this file since 99863 was 99821, checked in by vboxsync, 19 months ago

VMM/GIC: Implement interrupt forwarding to the GIC from shared peripherals, bugref:10404
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1/* $Id: PDMAll.cpp 99821 2023-05-17 07:35:02Z vboxsync $ */
2/** @file
3 * PDM Critical Sections
4 */
5
6/*
7 * Copyright (C) 2006-2023 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28
29/*********************************************************************************************************************************
30* Header Files *
31*********************************************************************************************************************************/
32#define LOG_GROUP LOG_GROUP_PDM
33#include "PDMInternal.h"
34#include <VBox/vmm/pdm.h>
35#include <VBox/vmm/mm.h>
36#include <VBox/vmm/vmcc.h>
37#include <VBox/err.h>
38#ifdef VBOX_VMM_TARGET_ARMV8
39# include <VBox/vmm/gic.h>
40#else
41# include <VBox/vmm/apic.h>
42#endif
43
44#include <VBox/log.h>
45#include <iprt/asm.h>
46#include <iprt/assert.h>
47
48#include "PDMInline.h"
49#include "dtrace/VBoxVMM.h"
50
51
52#if !defined(VBOX_VMM_TARGET_ARMV8)
53/**
54 * Gets the pending interrupt.
55 *
56 * @returns VBox status code.
57 * @retval VINF_SUCCESS on success.
58 * @retval VERR_APIC_INTR_MASKED_BY_TPR when an APIC interrupt is pending but
59 * can't be delivered due to TPR priority.
60 * @retval VERR_NO_DATA if there is no interrupt to be delivered (either APIC
61 * has been software-disabled since it flagged something was pending,
62 * or other reasons).
63 *
64 * @param pVCpu The cross context virtual CPU structure.
65 * @param pu8Interrupt Where to store the interrupt.
66 */
67VMMDECL(int) PDMGetInterrupt(PVMCPUCC pVCpu, uint8_t *pu8Interrupt)
68{
69 /*
70 * The local APIC has a higher priority than the PIC.
71 */
72 int rc = VERR_NO_DATA;
73 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC))
74 {
75 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_APIC);
76
77 uint32_t uTagSrc;
78 rc = APICGetInterrupt(pVCpu, pu8Interrupt, &uTagSrc);
79 if (RT_SUCCESS(rc))
80 {
81 VBOXVMM_PDM_IRQ_GET(pVCpu, RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc), *pu8Interrupt);
82 Log8(("PDMGetInterrupt: irq=%#x tag=%#x (apic)\n", *pu8Interrupt, uTagSrc));
83 return VINF_SUCCESS;
84 }
85 /* else if it's masked by TPR/PPR/whatever, go ahead checking the PIC. Such masked
86 interrupts shouldn't prevent ExtINT from being delivered. */
87 }
88
89 PVMCC pVM = pVCpu->CTX_SUFF(pVM);
90 pdmLock(pVM);
91
92 /*
93 * Check the PIC.
94 */
95 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_PIC))
96 {
97 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_PIC);
98 Assert(pVM->pdm.s.Pic.CTX_SUFF(pDevIns));
99 Assert(pVM->pdm.s.Pic.CTX_SUFF(pfnGetInterrupt));
100 uint32_t uTagSrc;
101 int i = pVM->pdm.s.Pic.CTX_SUFF(pfnGetInterrupt)(pVM->pdm.s.Pic.CTX_SUFF(pDevIns), &uTagSrc);
102 AssertMsg(i <= 255 && i >= 0, ("i=%d\n", i));
103 if (i >= 0)
104 {
105 pdmUnlock(pVM);
106 *pu8Interrupt = (uint8_t)i;
107 VBOXVMM_PDM_IRQ_GET(pVCpu, RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc), i);
108 Log8(("PDMGetInterrupt: irq=%#x tag=%#x (pic)\n", i, uTagSrc));
109 return VINF_SUCCESS;
110 }
111 }
112
113 /*
114 * One scenario where we may possibly get here is if the APIC signaled a pending interrupt,
115 * got an APIC MMIO/MSR VM-exit which disabled the APIC. We could, in theory, clear the APIC
116 * force-flag from all the places which disables the APIC but letting PDMGetInterrupt() fail
117 * without returning a valid interrupt still needs to be handled for the TPR masked case,
118 * so we shall just handle it here regardless if we choose to update the APIC code in the future.
119 */
120
121 pdmUnlock(pVM);
122 return rc;
123}
124#endif
125
126
127/**
128 * Sets the pending interrupt coming from ISA source or HPET.
129 *
130 * @returns VBox status code.
131 * @param pVM The cross context VM structure.
132 * @param u8Irq The IRQ line.
133 * @param u8Level The new level.
134 * @param uTagSrc The IRQ tag and source tracer ID.
135 */
136VMMDECL(int) PDMIsaSetIrq(PVMCC pVM, uint8_t u8Irq, uint8_t u8Level, uint32_t uTagSrc)
137{
138 pdmLock(pVM);
139
140 /** @todo put the IRQ13 code elsewhere to avoid this unnecessary bloat. */
141 if (!uTagSrc && (u8Level & PDM_IRQ_LEVEL_HIGH)) /* FPU IRQ */
142 {
143 if (u8Level == PDM_IRQ_LEVEL_HIGH)
144 VBOXVMM_PDM_IRQ_HIGH(VMMGetCpu(pVM), 0, 0);
145 else
146 VBOXVMM_PDM_IRQ_HILO(VMMGetCpu(pVM), 0, 0);
147 }
148 Log9(("PDMIsaSetIrq: irq=%#x lvl=%u tag=%#x\n", u8Irq, u8Level, uTagSrc));
149
150#ifdef VBOX_VMM_TARGET_ARMV8
151 int rc = VINF_SUCCESS;
152 GICSpiSet(pVM, u8Level, u8Level == PDM_IRQ_LEVEL_HIGH ? true : false);
153#else
154 int rc = VERR_PDM_NO_PIC_INSTANCE;
155/** @todo r=bird: This code is incorrect, as it ASSUMES the PIC and I/O APIC
156 * are always ring-0 enabled! */
157 if (pVM->pdm.s.Pic.CTX_SUFF(pDevIns))
158 {
159 Assert(pVM->pdm.s.Pic.CTX_SUFF(pfnSetIrq));
160 pVM->pdm.s.Pic.CTX_SUFF(pfnSetIrq)(pVM->pdm.s.Pic.CTX_SUFF(pDevIns), u8Irq, u8Level, uTagSrc);
161 rc = VINF_SUCCESS;
162 }
163
164 if (pVM->pdm.s.IoApic.CTX_SUFF(pDevIns))
165 {
166 Assert(pVM->pdm.s.IoApic.CTX_SUFF(pfnSetIrq));
167
168 /*
169 * Apply Interrupt Source Override rules.
170 * See ACPI 4.0 specification 5.2.12.4 and 5.2.12.5 for details on
171 * interrupt source override.
172 * Shortly, ISA IRQ0 is electically connected to pin 2 on IO-APIC, and some OSes,
173 * notably recent OS X rely upon this configuration.
174 * If changing, also update override rules in MADT and MPS.
175 */
176 /* ISA IRQ0 routed to pin 2, all others ISA sources are identity mapped */
177 if (u8Irq == 0)
178 u8Irq = 2;
179
180 pVM->pdm.s.IoApic.CTX_SUFF(pfnSetIrq)(pVM->pdm.s.IoApic.CTX_SUFF(pDevIns), NIL_PCIBDF, u8Irq, u8Level, uTagSrc);
181 rc = VINF_SUCCESS;
182 }
183#endif
184
185 if (!uTagSrc && u8Level == PDM_IRQ_LEVEL_LOW)
186 VBOXVMM_PDM_IRQ_LOW(VMMGetCpu(pVM), 0, 0);
187 pdmUnlock(pVM);
188 return rc;
189}
190
191
192/**
193 * Sets the pending I/O APIC interrupt.
194 *
195 * @returns VBox status code.
196 * @param pVM The cross context VM structure.
197 * @param u8Irq The IRQ line.
198 * @param uBusDevFn The bus:device:function of the device initiating the IRQ.
199 * Pass NIL_PCIBDF when it's not a PCI device or interrupt.
200 * @param u8Level The new level.
201 * @param uTagSrc The IRQ tag and source tracer ID.
202 */
203VMM_INT_DECL(int) PDMIoApicSetIrq(PVM pVM, PCIBDF uBusDevFn, uint8_t u8Irq, uint8_t u8Level, uint32_t uTagSrc)
204{
205 Log9(("PDMIoApicSetIrq: irq=%#x lvl=%u tag=%#x src=%#x\n", u8Irq, u8Level, uTagSrc, uBusDevFn));
206
207#ifdef VBOX_VMM_TARGET_ARMV8
208 int rc = VINF_SUCCESS;
209 RT_NOREF(uBusDevFn, uTagSrc);
210 GICSpiSet(pVM, u8Irq, u8Level == PDM_IRQ_LEVEL_HIGH ? true : false);
211#else
212 if (pVM->pdm.s.IoApic.CTX_SUFF(pDevIns))
213 {
214 Assert(pVM->pdm.s.IoApic.CTX_SUFF(pfnSetIrq));
215 pVM->pdm.s.IoApic.CTX_SUFF(pfnSetIrq)(pVM->pdm.s.IoApic.CTX_SUFF(pDevIns), uBusDevFn, u8Irq, u8Level, uTagSrc);
216 return VINF_SUCCESS;
217 }
218 return VERR_PDM_NO_PIC_INSTANCE;
219#endif
220}
221
222
223/**
224 * Broadcasts an EOI to the I/O APIC(s).
225 *
226 * @param pVM The cross context VM structure.
227 * @param uVector The interrupt vector corresponding to the EOI.
228 */
229VMM_INT_DECL(void) PDMIoApicBroadcastEoi(PVMCC pVM, uint8_t uVector)
230{
231 /*
232 * At present, we support only a maximum of one I/O APIC per-VM. If we ever implement having
233 * multiple I/O APICs per-VM, we'll have to broadcast this EOI to all of the I/O APICs.
234 */
235 PCPDMIOAPIC pIoApic = &pVM->pdm.s.IoApic;
236#ifdef IN_RING0
237 if (pIoApic->pDevInsR0)
238 {
239 Assert(pIoApic->pfnSetEoiR0);
240 pIoApic->pfnSetEoiR0(pIoApic->pDevInsR0, uVector);
241 }
242 else if (pIoApic->pDevInsR3)
243 {
244 /* Queue for ring-3 execution. */
245 PPDMDEVHLPTASK pTask = (PPDMDEVHLPTASK)PDMQueueAlloc(pVM, pVM->pdm.s.hDevHlpQueue, pVM);
246 if (pTask)
247 {
248 pTask->enmOp = PDMDEVHLPTASKOP_IOAPIC_SET_EOI;
249 pTask->pDevInsR3 = NIL_RTR3PTR; /* not required */
250 pTask->u.IoApicSetEoi.uVector = uVector;
251 PDMQueueInsert(pVM, pVM->pdm.s.hDevHlpQueue, pVM, &pTask->Core);
252 }
253 else
254 AssertMsgFailed(("We're out of devhlp queue items!!!\n"));
255 }
256#else
257 if (pIoApic->pDevInsR3)
258 {
259 Assert(pIoApic->pfnSetEoiR3);
260 pIoApic->pfnSetEoiR3(pIoApic->pDevInsR3, uVector);
261 }
262#endif
263}
264
265
266/**
267 * Send a MSI to an I/O APIC.
268 *
269 * @param pVM The cross context VM structure.
270 * @param uBusDevFn The bus:device:function of the device initiating the MSI.
271 * @param pMsi The MSI to send.
272 * @param uTagSrc The IRQ tag and source tracer ID.
273 */
274VMM_INT_DECL(void) PDMIoApicSendMsi(PVMCC pVM, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc)
275{
276 Log9(("PDMIoApicSendMsi: addr=%#RX64 data=%#RX32 tag=%#x src=%#x\n", pMsi->Addr.u64, pMsi->Data.u32, uTagSrc, uBusDevFn));
277 PCPDMIOAPIC pIoApic = &pVM->pdm.s.IoApic;
278#ifdef IN_RING0
279 if (pIoApic->pDevInsR0)
280 pIoApic->pfnSendMsiR0(pIoApic->pDevInsR0, uBusDevFn, pMsi, uTagSrc);
281 else if (pIoApic->pDevInsR3)
282 {
283 /* Queue for ring-3 execution. */
284 PPDMDEVHLPTASK pTask = (PPDMDEVHLPTASK)PDMQueueAlloc(pVM, pVM->pdm.s.hDevHlpQueue, pVM);
285 if (pTask)
286 {
287 pTask->enmOp = PDMDEVHLPTASKOP_IOAPIC_SEND_MSI;
288 pTask->pDevInsR3 = NIL_RTR3PTR; /* not required */
289 pTask->u.IoApicSendMsi.uBusDevFn = uBusDevFn;
290 pTask->u.IoApicSendMsi.Msi = *pMsi;
291 pTask->u.IoApicSendMsi.uTagSrc = uTagSrc;
292 PDMQueueInsert(pVM, pVM->pdm.s.hDevHlpQueue, pVM, &pTask->Core);
293 }
294 else
295 AssertMsgFailed(("We're out of devhlp queue items!!!\n"));
296 }
297#else
298 if (pIoApic->pDevInsR3)
299 {
300 Assert(pIoApic->pfnSendMsiR3);
301 pIoApic->pfnSendMsiR3(pIoApic->pDevInsR3, uBusDevFn, pMsi, uTagSrc);
302 }
303#endif
304}
305
306
307
308/**
309 * Returns the presence of an IO-APIC.
310 *
311 * @returns true if an IO-APIC is present.
312 * @param pVM The cross context VM structure.
313 */
314VMM_INT_DECL(bool) PDMHasIoApic(PVM pVM)
315{
316 return pVM->pdm.s.IoApic.pDevInsR3 != NULL;
317}
318
319
320/**
321 * Returns the presence of an APIC.
322 *
323 * @returns true if an APIC is present.
324 * @param pVM The cross context VM structure.
325 */
326VMM_INT_DECL(bool) PDMHasApic(PVM pVM)
327{
328 return pVM->pdm.s.Apic.pDevInsR3 != NIL_RTR3PTR;
329}
330
331
332/**
333 * Translates a ring-0 device instance index to a pointer.
334 *
335 * This is used by PGM for device access handlers.
336 *
337 * @returns Device instance pointer if valid index, otherwise NULL (asserted).
338 * @param pVM The cross context VM structure.
339 * @param idxR0Device The ring-0 device instance index.
340 */
341VMM_INT_DECL(PPDMDEVINS) PDMDeviceRing0IdxToInstance(PVMCC pVM, uint64_t idxR0Device)
342{
343#ifdef IN_RING0
344 AssertMsgReturn(idxR0Device < RT_ELEMENTS(pVM->pdmr0.s.apDevInstances), ("%#RX64\n", idxR0Device), NULL);
345 PPDMDEVINS pDevIns = pVM->pdmr0.s.apDevInstances[idxR0Device];
346#elif defined(IN_RING3)
347 AssertMsgReturn(idxR0Device < RT_ELEMENTS(pVM->pdm.s.apDevRing0Instances), ("%#RX64\n", idxR0Device), NULL);
348 PPDMDEVINS pDevIns = pVM->pdm.s.apDevRing0Instances[idxR0Device];
349#else
350# error "Unsupported context"
351#endif
352 AssertMsg(pDevIns, ("%#RX64\n", idxR0Device));
353 return pDevIns;
354}
355
356
357/**
358 * Locks PDM.
359 *
360 * This might block.
361 *
362 * @param pVM The cross context VM structure.
363 */
364void pdmLock(PVMCC pVM)
365{
366 int rc = PDMCritSectEnter(pVM, &pVM->pdm.s.CritSect, VINF_SUCCESS);
367 PDM_CRITSECT_RELEASE_ASSERT_RC(pVM, &pVM->pdm.s.CritSect, rc);
368}
369
370
371/**
372 * Locks PDM but don't go to ring-3 if it's owned by someone.
373 *
374 * @returns VINF_SUCCESS on success.
375 * @returns rc if we're in GC or R0 and can't get the lock.
376 * @param pVM The cross context VM structure.
377 * @param rcBusy The RC to return in GC or R0 when we can't get the lock.
378 */
379int pdmLockEx(PVMCC pVM, int rcBusy)
380{
381 return PDMCritSectEnter(pVM, &pVM->pdm.s.CritSect, rcBusy);
382}
383
384
385/**
386 * Unlocks PDM.
387 *
388 * @param pVM The cross context VM structure.
389 */
390void pdmUnlock(PVMCC pVM)
391{
392 PDMCritSectLeave(pVM, &pVM->pdm.s.CritSect);
393}
394
395
396/**
397 * Checks if this thread is owning the PDM lock.
398 *
399 * @returns @c true if the lock is taken, @c false otherwise.
400 * @param pVM The cross context VM structure.
401 */
402bool pdmLockIsOwner(PVMCC pVM)
403{
404 return PDMCritSectIsOwner(pVM, &pVM->pdm.s.CritSect);
405}
406
407
408/**
409 * Converts ring 3 VMM heap pointer to a guest physical address
410 *
411 * @returns VBox status code.
412 * @param pVM The cross context VM structure.
413 * @param pv Ring-3 pointer.
414 * @param pGCPhys GC phys address (out).
415 */
416VMM_INT_DECL(int) PDMVmmDevHeapR3ToGCPhys(PVM pVM, RTR3PTR pv, RTGCPHYS *pGCPhys)
417{
418 if (RT_LIKELY(pVM->pdm.s.GCPhysVMMDevHeap != NIL_RTGCPHYS))
419 {
420 RTR3UINTPTR const offHeap = (RTR3UINTPTR)pv - (RTR3UINTPTR)pVM->pdm.s.pvVMMDevHeap;
421 if (RT_LIKELY(offHeap < pVM->pdm.s.cbVMMDevHeap))
422 {
423 *pGCPhys = pVM->pdm.s.GCPhysVMMDevHeap + offHeap;
424 return VINF_SUCCESS;
425 }
426
427 /* Don't assert here as this is called before we can catch ring-0 assertions. */
428 Log(("PDMVmmDevHeapR3ToGCPhys: pv=%p pvVMMDevHeap=%p cbVMMDevHeap=%#x\n",
429 pv, pVM->pdm.s.pvVMMDevHeap, pVM->pdm.s.cbVMMDevHeap));
430 }
431 else
432 Log(("PDMVmmDevHeapR3ToGCPhys: GCPhysVMMDevHeap=%RGp (pv=%p)\n", pVM->pdm.s.GCPhysVMMDevHeap, pv));
433 return VERR_PDM_DEV_HEAP_R3_TO_GCPHYS;
434}
435
436
437/**
438 * Checks if the vmm device heap is enabled (== vmm device's pci region mapped)
439 *
440 * @returns dev heap enabled status (true/false)
441 * @param pVM The cross context VM structure.
442 */
443VMM_INT_DECL(bool) PDMVmmDevHeapIsEnabled(PVM pVM)
444{
445 return pVM->pdm.s.GCPhysVMMDevHeap != NIL_RTGCPHYS;
446}
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