PGMAll.cpp@ 1507

Last change on this file since 1507 was 1310, checked in by vboxsync, 18 years ago
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1	/* $Id: PGMAll.cpp 1310 2007-03-07 20:06:16Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor - All context code.
4	*/
5
6	/*
7	* Copyright (C) 2006 InnoTek Systemberatung GmbH
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License as published by the Free Software Foundation,
13	* in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
14	* distribution. VirtualBox OSE is distributed in the hope that it will
15	* be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* If you received this file as part of a commercial VirtualBox
18	* distribution, then only the terms of your commercial VirtualBox
19	* license agreement apply instead of the previous paragraph.
20	*/
21
22	/*******************************************************************************
23	* Header Files *
24	*******************************************************************************/
25	#define LOG_GROUP LOG_GROUP_PGM
26	#include <VBox/pgm.h>
27	#include <VBox/cpum.h>
28	#include <VBox/selm.h>
29	#include <VBox/iom.h>
30	#include <VBox/sup.h>
31	#include <VBox/mm.h>
32	#include <VBox/stam.h>
33	#include <VBox/csam.h>
34	#include <VBox/trpm.h>
35	#include <VBox/rem.h>
36	#include <VBox/em.h>
37	#include "PGMInternal.h"
38	#include <VBox/vm.h>
39	#include <iprt/assert.h>
40	#include <iprt/asm.h>
41	#include <iprt/string.h>
42	#include <VBox/log.h>
43	#include <VBox/param.h>
44	#include <VBox/err.h>
45
46
47	/*******************************************************************************
48	* Structures and Typedefs *
49	*******************************************************************************/
50	/**
51	* Stated structure for PGM_GST_NAME(HandlerVirtualUpdate) that's
52	* passed to PGM_GST_NAME(VirtHandlerUpdateOne) during enumeration.
53	*/
54	typedef struct PGMHVUSTATE
55	{
56	/** The VM handle. */
57	PVM pVM;
58	/** The todo flags. */
59	RTUINT fTodo;
60	/** The CR4 register value. */
61	uint32_t cr4;
62	} PGMHVUSTATE, *PPGMHVUSTATE;
63
64
65	/*******************************************************************************
66	* Internal Functions *
67	*******************************************************************************/
68	/** @def DUMP_PDE_BIG
69	* Debug routine for dumping a big PDE.
70	*/
71	#ifdef DEBUG_Sander
72	/** Debug routine for dumping a big PDE. */
73	static void pgmDumpPDEBig(const char *pszPrefix, int iPD, VBOXPDE Pde)
74	{
75	Log(("%s: BIG %d u10PageNo=%08X P=%d W=%d U=%d CACHE=%d ACC=%d DIR=%d GBL=%d\n", pszPrefix, iPD, Pde.b.u10PageNo, Pde.b.u1Present, Pde.b.u1Write, Pde.b.u1User, Pde.b.u1CacheDisable, Pde.b.u1Accessed, Pde.b.u1Dirty, Pde.b.u1Global));
76	Log(("%s: BIG %d WRT=%d AVAIL=%X RSV=%X PAT=%d\n", pszPrefix, iPD, Pde.b.u1WriteThru, Pde.b.u3Available, Pde.b.u8PageNoHigh, Pde.b.u1PAT));
77	}
78	#define DUMP_PDE_BIG(a, b, c) pgmDumpPDEBig(a, b, c)
79	#else
80	#define DUMP_PDE_BIG(a, b, c) do { } while (0)
81	#endif
82
83
84
85	#if 1///@todo ndef __AMD64__
86	/*
87	* Shadow - 32-bit mode
88	*/
89	#define PGM_SHW_TYPE PGM_TYPE_32BIT
90	#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
91	#include "PGMAllShw.h"
92
93	/* Guest - real mode */
94	#define PGM_GST_TYPE PGM_TYPE_REAL
95	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
96	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
97	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
98	#include "PGMAllGst.h"
99	#include "PGMAllBth.h"
100	#undef BTH_PGMPOOLKIND_PT_FOR_PT
101	#undef PGM_BTH_NAME
102	#undef PGM_GST_TYPE
103	#undef PGM_GST_NAME
104
105	/* Guest - protected mode */
106	#define PGM_GST_TYPE PGM_TYPE_PROT
107	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
108	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
109	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
110	#include "PGMAllGst.h"
111	#include "PGMAllBth.h"
112	#undef BTH_PGMPOOLKIND_PT_FOR_PT
113	#undef PGM_BTH_NAME
114	#undef PGM_GST_TYPE
115	#undef PGM_GST_NAME
116
117	/* Guest - 32-bit mode */
118	#define PGM_GST_TYPE PGM_TYPE_32BIT
119	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
120	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
121	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
122	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
123	#include "PGMAllGst.h"
124	#include "PGMAllBth.h"
125	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
126	#undef BTH_PGMPOOLKIND_PT_FOR_PT
127	#undef PGM_BTH_NAME
128	#undef PGM_GST_TYPE
129	#undef PGM_GST_NAME
130
131	#undef PGM_SHW_TYPE
132	#undef PGM_SHW_NAME
133	#endif /* !__AMD64__ */
134
135
136	/*
137	* Shadow - PAE mode
138	*/
139	#define PGM_SHW_TYPE PGM_TYPE_PAE
140	#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
141	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
142	#include "PGMAllShw.h"
143
144	/* Guest - real mode */
145	#define PGM_GST_TYPE PGM_TYPE_REAL
146	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
147	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
148	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
149	#include "PGMAllBth.h"
150	#undef BTH_PGMPOOLKIND_PT_FOR_PT
151	#undef PGM_BTH_NAME
152	#undef PGM_GST_TYPE
153	#undef PGM_GST_NAME
154
155	/* Guest - protected mode */
156	#define PGM_GST_TYPE PGM_TYPE_PROT
157	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
158	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
159	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
160	#include "PGMAllBth.h"
161	#undef BTH_PGMPOOLKIND_PT_FOR_PT
162	#undef PGM_BTH_NAME
163	#undef PGM_GST_TYPE
164	#undef PGM_GST_NAME
165
166	/* Guest - 32-bit mode */
167	#define PGM_GST_TYPE PGM_TYPE_32BIT
168	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
169	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
170	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
171	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
172	#include "PGMAllBth.h"
173	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
174	#undef BTH_PGMPOOLKIND_PT_FOR_PT
175	#undef PGM_BTH_NAME
176	#undef PGM_GST_TYPE
177	#undef PGM_GST_NAME
178
179
180	/* Guest - PAE mode */
181	#define PGM_GST_TYPE PGM_TYPE_PAE
182	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
183	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
184	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
185	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
186	#include "PGMAllGst.h"
187	#include "PGMAllBth.h"
188	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
189	#undef BTH_PGMPOOLKIND_PT_FOR_PT
190	#undef PGM_BTH_NAME
191	#undef PGM_GST_TYPE
192	#undef PGM_GST_NAME
193
194	#undef PGM_SHW_TYPE
195	#undef PGM_SHW_NAME
196
197
198	/*
199	* Shadow - AMD64 mode
200	*/
201	#define PGM_SHW_TYPE PGM_TYPE_AMD64
202	#define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
203	#include "PGMAllShw.h"
204
205	/* Guest - real mode */
206	#define PGM_GST_TYPE PGM_TYPE_REAL
207	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
208	#define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_REAL(name)
209	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
210	#include "PGMAllBth.h"
211	#undef BTH_PGMPOOLKIND_PT_FOR_PT
212	#undef PGM_BTH_NAME
213	#undef PGM_GST_NAME
214	#undef PGM_GST_TYPE
215
216	/* Guest - protected mode */
217	#define PGM_GST_TYPE PGM_TYPE_PROT
218	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
219	#define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_PROT(name)
220	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
221	#include "PGMAllBth.h"
222	#undef BTH_PGMPOOLKIND_PT_FOR_PT
223	#undef PGM_BTH_NAME
224	#undef PGM_GST_TYPE
225	#undef PGM_GST_NAME
226
227	/* Guest - AMD64 mode */
228	#define PGM_GST_TYPE PGM_TYPE_AMD64
229	#define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
230	#define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
231	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
232	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
233	#include "PGMAllGst.h"
234	#include "PGMAllBth.h"
235	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
236	#undef BTH_PGMPOOLKIND_PT_FOR_PT
237	#undef PGM_BTH_NAME
238	#undef PGM_GST_TYPE
239	#undef PGM_GST_NAME
240
241	#undef PGM_SHW_TYPE
242	#undef PGM_SHW_NAME
243
244
245
246	/**
247	* #PF Handler.
248	*
249	* @returns VBox status code (appropriate for trap handling and GC return).
250	* @param pVM VM Handle.
251	* @param uErr The trap error code.
252	* @param pRegFrame Trap register frame.
253	* @param pvFault The fault address.
254	*/
255	PGMDECL(int) PGMTrap0eHandler(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
256	{
257	LogFlow(("PGMTrap0eHandler: uErr=%#x pvFault=%VGv eip=%VGv\n", uErr, pvFault, pRegFrame->eip));
258	STAM_PROFILE_START(&pVM->pgm.s.StatGCTrap0e, a);
259	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = NULL; } );
260
261
262	#ifdef VBOX_WITH_STATISTICS
263	/*
264	* Error code stats.
265	*/
266	if (uErr & X86_TRAP_PF_US)
267	{
268	if (!(uErr & X86_TRAP_PF_P))
269	{
270	if (uErr & X86_TRAP_PF_RW)
271	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eUSNotPresentWrite);
272	else
273	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eUSNotPresentRead);
274	}
275	else if (uErr & X86_TRAP_PF_RW)
276	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eUSWrite);
277	else if (uErr & X86_TRAP_PF_RSVD)
278	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eUSReserved);
279	else
280	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eUSRead);
281	}
282	else
283	{ //supervisor
284	if (!(uErr & X86_TRAP_PF_P))
285	{
286	if (uErr & X86_TRAP_PF_RW)
287	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eSVNotPresentWrite);
288	else
289	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eSVNotPresentRead);
290	}
291	else if (uErr & X86_TRAP_PF_RW)
292	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eSVWrite);
293	else if (uErr & X86_TRAP_PF_RSVD)
294	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eSVReserved);
295	}
296	#endif
297
298	/*
299	* Call the worker.
300	*/
301	int rc = PGM_BTH_PFN(Trap0eHandler, pVM)(pVM, uErr, pRegFrame, pvFault);
302	if (rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
303	rc = VINF_SUCCESS;
304	STAM_STATS({ if (!pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution))
305	pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eMisc; });
306	STAM_PROFILE_STOP_EX(&pVM->pgm.s.StatGCTrap0e, pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution), a);
307	return rc;
308	}
309
310
311	/**
312	* Prefetch a page
313	*
314	* Typically used to sync commonly used pages before entering raw mode
315	* after a CR3 reload.
316	*
317	* @returns VBox status code suitable for scheduling.
318	* @retval VINF_SUCCESS on success.
319	* @retval VINF_PGM_SYNC_CR3 if we're out of shadow pages or something like that.
320	* @param pVM VM handle.
321	* @param GCPtrPage Page to invalidate.
322	*/
323	PGMDECL(int) PGMPrefetchPage(PVM pVM, RTGCPTR GCPtrPage)
324	{
325	STAM_PROFILE_START(&pVM->pgm.s.StatHCPrefetch, a);
326	int rc = PGM_BTH_PFN(PrefetchPage, pVM)(pVM, (RTGCUINTPTR)GCPtrPage);
327	STAM_PROFILE_STOP(&pVM->pgm.s.StatHCPrefetch, a);
328	AssertMsg(rc == VINF_SUCCESS \|\| rc == VINF_PGM_SYNC_CR3 \|\| VBOX_FAILURE(rc), ("rc=%Vrc\n", rc));
329	return rc;
330	}
331
332
333	/**
334	* Gets the mapping corresponding to the specified address (if any).
335	*
336	* @returns Pointer to the mapping.
337	* @returns NULL if not
338	*
339	* @param pVM The virtual machine.
340	* @param GCPtr The guest context pointer.
341	*/
342	PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr)
343	{
344	PPGMMAPPING pMapping = CTXSUFF(pVM->pgm.s.pMappings);
345	while (pMapping)
346	{
347	if ((uintptr_t)GCPtr < (uintptr_t)pMapping->GCPtr)
348	break;
349	if ((uintptr_t)GCPtr - (uintptr_t)pMapping->GCPtr < pMapping->cb)
350	{
351	STAM_COUNTER_INC(&pVM->pgm.s.StatGCSyncPTConflict);
352	return pMapping;
353	}
354	pMapping = CTXSUFF(pMapping->pNext);
355	}
356	return NULL;
357	}
358
359
360	/**
361	* Verifies a range of pages for read or write access
362	*
363	* Only checks the guest's page tables
364	*
365	* @returns VBox status code.
366	* @param pVM VM handle.
367	* @param Addr Guest virtual address to check
368	* @param cbSize Access size
369	* @param fAccess Access type (r/w, user/supervisor (X86_PTE_*))
370	*/
371	PGMDECL(int) PGMIsValidAccess(PVM pVM, RTGCUINTPTR Addr, uint32_t cbSize, uint32_t fAccess)
372	{
373	/*
374	* Validate input.
375	*/
376	if (fAccess & ~(X86_PTE_US \| X86_PTE_RW))
377	{
378	AssertMsgFailed(("PGMIsValidAccess: invalid access type %08x\n", fAccess));
379	return VERR_INVALID_PARAMETER;
380	}
381
382	uint64_t fPage;
383	int rc = PGMGstGetPage(pVM, (RTGCPTR)Addr, &fPage, NULL);
384	if (VBOX_FAILURE(rc))
385	{
386	Log(("PGMIsValidAccess: access violation for %VGv rc=%d\n", Addr, rc));
387	return VINF_EM_RAW_GUEST_TRAP;
388	}
389
390	/*
391	* Check if the access would cause a page fault
392	*
393	* Note that hypervisor page directories are not present in the guest's tables, so this check
394	* is sufficient.
395	*/
396	bool fWrite = !!(fAccess & X86_PTE_RW);
397	bool fUser = !!(fAccess & X86_PTE_US);
398	if ( !(fPage & X86_PTE_P)
399	\|\| (fWrite && !(fPage & X86_PTE_RW))
400	\|\| (fUser && !(fPage & X86_PTE_US)) )
401	{
402	Log(("PGMIsValidAccess: access violation for %VGv attr %#llx vs %d:%d\n", Addr, fPage, fWrite, fUser));
403	return VINF_EM_RAW_GUEST_TRAP;
404	}
405	if ( VBOX_SUCCESS(rc)
406	&& PAGE_ADDRESS(Addr) != PAGE_ADDRESS(Addr + cbSize))
407	return PGMIsValidAccess(pVM, Addr + PAGE_SIZE, (cbSize > PAGE_SIZE) ? cbSize - PAGE_SIZE : 1, fAccess);
408	return rc;
409	}
410
411
412	/**
413	* Verifies a range of pages for read or write access
414	*
415	* Supports handling of pages marked for dirty bit tracking and CSAM
416	*
417	* @returns VBox status code.
418	* @param pVM VM handle.
419	* @param Addr Guest virtual address to check
420	* @param cbSize Access size
421	* @param fAccess Access type (r/w, user/supervisor (X86_PTE_*))
422	*/
423	PGMDECL(int) PGMVerifyAccess(PVM pVM, RTGCUINTPTR Addr, uint32_t cbSize, uint32_t fAccess)
424	{
425	/*
426	* Validate input.
427	*/
428	if (fAccess & ~(X86_PTE_US \| X86_PTE_RW))
429	{
430	AssertMsgFailed(("PGMVerifyAccess: invalid access type %08x\n", fAccess));
431	return VERR_INVALID_PARAMETER;
432	}
433
434	uint64_t fPageGst;
435	int rc = PGMGstGetPage(pVM, (RTGCPTR)Addr, &fPageGst, NULL);
436	if (VBOX_FAILURE(rc))
437	{
438	Log(("PGMVerifyAccess: access violation for %VGv rc=%d\n", Addr, rc));
439	return VINF_EM_RAW_GUEST_TRAP;
440	}
441
442	/*
443	* Check if the access would cause a page fault
444	*
445	* Note that hypervisor page directories are not present in the guest's tables, so this check
446	* is sufficient.
447	*/
448	const bool fWrite = !!(fAccess & X86_PTE_RW);
449	const bool fUser = !!(fAccess & X86_PTE_US);
450	if ( !(fPageGst & X86_PTE_P)
451	\|\| (fWrite && !(fPageGst & X86_PTE_RW))
452	\|\| (fUser && !(fPageGst & X86_PTE_US)) )
453	{
454	Log(("PGMVerifyAccess: access violation for %VGv attr %#llx vs %d:%d\n", Addr, fPageGst, fWrite, fUser));
455	return VINF_EM_RAW_GUEST_TRAP;
456	}
457
458	/*
459	* Next step is to verify if we protected this page for dirty bit tracking or for CSAM scanning
460	*/
461	rc = PGMShwGetPage(pVM, (RTGCPTR)Addr, NULL, NULL);
462	if (rc == VERR_PAGE_NOT_PRESENT)
463	{
464	/*
465	* Page is not present in our page tables.
466	* Try to sync it!
467	*/
468	Assert(X86_TRAP_PF_RW == X86_PTE_RW && X86_TRAP_PF_US == X86_PTE_US);
469	uint32_t uErr = fAccess & (X86_TRAP_PF_RW \| X86_TRAP_PF_US);
470	rc = PGM_BTH_PFN(VerifyAccessSyncPage, pVM)(pVM, Addr, fPageGst, uErr);
471	if (rc != VINF_SUCCESS)
472	return rc;
473	}
474	else if (rc == VERR_PAGE_TABLE_NOT_PRESENT)
475	{
476	/*
477	* Page table is not present; can't do much here (?)
478	* We could of course try sync the page table.... (?)
479	*/
480	return VINF_EM_RAW_EMULATE_INSTR;
481	}
482	else
483	AssertMsg(rc == VINF_SUCCESS, ("PGMShwGetPage %VGv failed with %Vrc\n", Addr, rc));
484
485	#if 0 /* def VBOX_STRICT; triggers too often now */
486	/*
487	* This check is a bit paranoid, but useful.
488	*/
489	/** @note this will assert when writing to monitored pages (a bit annoying actually) */
490	uint64_t fPageShw;
491	rc = PGMShwGetPage(pVM, (RTGCPTR)Addr, &fPageShw, NULL);
492	if ( (rc == VERR_PAGE_NOT_PRESENT \|\| VBOX_FAILURE(rc))
493	\|\| (fWrite && !(fPageShw & X86_PTE_RW))
494	\|\| (fUser && !(fPageShw & X86_PTE_US)) )
495	{
496	AssertMsgFailed(("Unexpected access violation for %VGv! rc=%Vrc write=%d user=%d\n",
497	Addr, rc, fWrite && !(fPageShw & X86_PTE_RW), fUser && !(fPageShw & X86_PTE_US)));
498	return VINF_EM_RAW_GUEST_TRAP;
499	}
500	#endif
501
502	if ( VBOX_SUCCESS(rc)
503	&& ( PAGE_ADDRESS(Addr) != PAGE_ADDRESS(Addr + cbSize - 1)
504	\|\| Addr + cbSize < Addr))
505	return PGMVerifyAccess(pVM, Addr + PAGE_SIZE, cbSize > PAGE_SIZE ? cbSize - PAGE_SIZE : 1, fAccess);
506	return rc;
507	}
508
509	#ifndef IN_GC
510	/**
511	* Emulation of the invlpg instruction (HC only actually).
512	*
513	* @returns VBox status code.
514	* @param pVM VM handle.
515	* @param GCPtrPage Page to invalidate.
516	* @remark ASSUMES the page table entry or page directory is
517	* valid. Fairly safe, but there could be edge cases!
518	* @todo Flush page or page directory only if necessary!
519	*/
520	PGMDECL(int) PGMInvalidatePage(PVM pVM, RTGCPTR GCPtrPage)
521	{
522	LogFlow(("PGMInvalidatePage: GCPtrPage=%VGv\n", GCPtrPage));
523
524	STAM_PROFILE_START(&CTXMID(pVM->pgm.s.Stat,InvalidatePage), a);
525	int rc = PGM_BTH_PFN(InvalidatePage, pVM)(pVM, GCPtrPage);
526	STAM_PROFILE_STOP(&CTXMID(pVM->pgm.s.Stat,InvalidatePage), a);
527
528	#ifndef IN_RING0
529	/*
530	* Check if we have a pending update of the CR3 monitoring.
531	*/
532	if ( VBOX_SUCCESS(rc)
533	&& (pVM->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3))
534	{
535	pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
536	Assert(!pVM->pgm.s.fMappingsFixed);
537	Assert(pVM->pgm.s.GCPhysCR3 == pVM->pgm.s.GCPhysGstCR3Monitored);
538	rc = PGM_GST_PFN(MonitorCR3, pVM)(pVM, pVM->pgm.s.GCPhysCR3);
539	}
540	#endif
541
542	#ifdef IN_RING3
543	/*
544	* Inform CSAM about the flush
545	*/
546	/** @note this is to check if monitored pages have been changed; when we implement callbacks for virtual handlers, this is no longer required. */
547	CSAMR3FlushPage(pVM, GCPtrPage);
548	#endif
549	return rc;
550	}
551	#endif
552
553
554	/**
555	* Executes an instruction using the interpreter.
556	*
557	* @returns VBox status code (appropriate for trap handling and GC return).
558	* @param pVM VM handle.
559	* @param pRegFrame Register frame.
560	* @param pvFault Fault address.
561	*/
562	PGMDECL(int) PGMInterpretInstruction(PVM pVM, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
563	{
564	#ifdef IN_RING0
565	/** @todo */
566	int rc = VINF_EM_RAW_EMULATE_INSTR;
567	#else
568	uint32_t cb;
569	int rc = EMInterpretInstruction(pVM, pRegFrame, pvFault, &cb);
570	if (rc == VERR_EM_INTERPRETER)
571	rc = VINF_EM_RAW_EMULATE_INSTR;
572	if (rc != VINF_SUCCESS)
573	Log(("PGMInterpretInstruction: returns %Rrc (pvFault=%VGv)\n", rc, pvFault));
574	#endif
575	return rc;
576	}
577
578
579	/**
580	* Gets effective page information (from the VMM page directory).
581	*
582	* @returns VBox status.
583	* @param pVM VM Handle.
584	* @param GCPtr Guest Context virtual address of the page.
585	* @param pfFlags Where to store the flags. These are X86_PTE_*.
586	* @param pHCPhys Where to store the HC physical address of the page.
587	* This is page aligned.
588	* @remark You should use PGMMapGetPage() for pages in a mapping.
589	*/
590	PGMDECL(int) PGMShwGetPage(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys)
591	{
592	return PGM_SHW_PFN(GetPage,pVM)(pVM, (RTGCUINTPTR)GCPtr, pfFlags, pHCPhys);
593	}
594
595
596	/**
597	* Sets (replaces) the page flags for a range of pages in the shadow context.
598	*
599	* @returns VBox status.
600	* @param pVM VM handle.
601	* @param GCPtr The address of the first page.
602	* @param cb The size of the range in bytes.
603	* @param fFlags Page flags X86_PTE_*, excluding the page mask of course.
604	* @remark You must use PGMMapSetPage() for pages in a mapping.
605	*/
606	PGMDECL(int) PGMShwSetPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags)
607	{
608	return PGMShwModifyPage(pVM, GCPtr, cb, fFlags, 0);
609	}
610
611
612	/**
613	* Modify page flags for a range of pages in the shadow context.
614	*
615	* The existing flags are ANDed with the fMask and ORed with the fFlags.
616	*
617	* @returns VBox status code.
618	* @param pVM VM handle.
619	* @param GCPtr Virtual address of the first page in the range.
620	* @param cb Size (in bytes) of the range to apply the modification to.
621	* @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
622	* @param fMask The AND mask - page flags X86_PTE_*.
623	* Be very CAREFUL when ~'ing constants which could be 32-bit!
624	* @remark You must use PGMMapModifyPage() for pages in a mapping.
625	*/
626	PGMDECL(int) PGMShwModifyPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
627	{
628	/*
629	* Validate input.
630	*/
631	if (fFlags & X86_PTE_PAE_PG_MASK)
632	{
633	AssertMsgFailed(("fFlags=%#llx\n", fFlags));
634	return VERR_INVALID_PARAMETER;
635	}
636	if (!cb)
637	{
638	AssertFailed();
639	return VERR_INVALID_PARAMETER;
640	}
641
642	/*
643	* Align the input.
644	*/
645	cb += (RTGCUINTPTR)GCPtr & PAGE_OFFSET_MASK;
646	cb = RT_ALIGN_Z(cb, PAGE_SIZE);
647	GCPtr = (RTGCPTR)((RTGCUINTPTR)GCPtr & PAGE_BASE_GC_MASK); /** @todo this ain't necessary, right... */
648
649	/*
650	* Call worker.
651	*/
652	return PGM_SHW_PFN(ModifyPage, pVM)(pVM, (RTGCUINTPTR)GCPtr, cb, fFlags, fMask);
653	}
654
655
656	/**
657	* Gets effective Guest OS page information.
658	*
659	* When GCPtr is in a big page, the function will return as if it was a normal
660	* 4KB page. If the need for distinguishing between big and normal page becomes
661	* necessary at a later point, a PGMGstGetPage() will be created for that
662	* purpose.
663	*
664	* @returns VBox status.
665	* @param pVM VM Handle.
666	* @param GCPtr Guest Context virtual address of the page.
667	* @param pfFlags Where to store the flags. These are X86_PTE_*, even for big pages.
668	* @param pGCPhys Where to store the GC physical address of the page.
669	* This is page aligned. The fact that the
670	*/
671	PGMDECL(int) PGMGstGetPage(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys)
672	{
673	return PGM_GST_PFN(GetPage,pVM)(pVM, (RTGCUINTPTR)GCPtr, pfFlags, pGCPhys);
674	}
675
676
677	/**
678	* Checks if the page is present.
679	*
680	* @returns true if the page is present.
681	* @returns false if the page is not present.
682	* @param pVM The VM handle.
683	* @param GCPtr Address within the page.
684	*/
685	PGMDECL(bool) PGMGstIsPagePresent(PVM pVM, RTGCPTR GCPtr)
686	{
687	int rc = PGMGstGetPage(pVM, GCPtr, NULL, NULL);
688	return VBOX_SUCCESS(rc);
689	}
690
691
692	/**
693	* Sets (replaces) the page flags for a range of pages in the guest's tables.
694	*
695	* @returns VBox status.
696	* @param pVM VM handle.
697	* @param GCPtr The address of the first page.
698	* @param cb The size of the range in bytes.
699	* @param fFlags Page flags X86_PTE_*, excluding the page mask of course.
700	*/
701	PGMDECL(int) PGMGstSetPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags)
702	{
703	return PGMGstModifyPage(pVM, GCPtr, cb, fFlags, 0);
704	}
705
706
707	/**
708	* Modify page flags for a range of pages in the guest's tables
709	*
710	* The existing flags are ANDed with the fMask and ORed with the fFlags.
711	*
712	* @returns VBox status code.
713	* @param pVM VM handle.
714	* @param GCPtr Virtual address of the first page in the range.
715	* @param cb Size (in bytes) of the range to apply the modification to.
716	* @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
717	* @param fMask The AND mask - page flags X86_PTE_*, excluding the page mask of course.
718	* Be very CAREFUL when ~'ing constants which could be 32-bit!
719	*/
720	PGMDECL(int) PGMGstModifyPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
721	{
722	STAM_PROFILE_START(&CTXMID(pVM->pgm.s.Stat,GstModifyPage), a);
723
724	/*
725	* Validate input.
726	*/
727	if (fFlags & X86_PTE_PAE_PG_MASK)
728	{
729	AssertMsgFailed(("fFlags=%#llx\n", fFlags));
730	STAM_PROFILE_STOP(&CTXMID(pVM->pgm.s.Stat,GstModifyPage), a);
731	return VERR_INVALID_PARAMETER;
732	}
733
734	if (!cb)
735	{
736	AssertFailed();
737	STAM_PROFILE_STOP(&CTXMID(pVM->pgm.s.Stat,GstModifyPage), a);
738	return VERR_INVALID_PARAMETER;
739	}
740
741	LogFlow(("PGMGstModifyPage %VGv %d bytes fFlags=%08llx fMask=%08llx\n", GCPtr, cb, fFlags, fMask));
742
743	/*
744	* Adjust input.
745	*/
746	cb += (RTGCUINTPTR)GCPtr & PAGE_OFFSET_MASK;
747	cb = RT_ALIGN_Z(cb, PAGE_SIZE);
748	GCPtr = (RTGCPTR)((RTGCUINTPTR)GCPtr & PAGE_BASE_GC_MASK);
749
750	/*
751	* Call worker.
752	*/
753	int rc = PGM_GST_PFN(ModifyPage, pVM)(pVM, (RTGCUINTPTR)GCPtr, cb, fFlags, fMask);
754
755	STAM_PROFILE_STOP(&CTXMID(pVM->pgm.s.Stat,GstModifyPage), a);
756	return rc;
757	}
758
759
760	/**
761	* Temporarily turns off the access monitoring of a page within a monitored
762	* physical write/all page access handler region.
763	*
764	* Use this when no further \#PFs are required for that page. Be aware that
765	* a page directory sync might reset the flags, and turn on access monitoring
766	* for the page.
767	*
768	* The caller must do required page table modifications.
769	*
770	* @returns VBox status code.
771	* @param pVM VM Handle
772	* @param GCPhys Start physical address earlier passed to PGMR3HandlerPhysicalRegister().
773	* @param GCPhysPage Physical address of the page to turn off access monitoring for.
774	*/
775	PGMDECL(int) PGMHandlerPhysicalPageTempOff(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage)
776	{
777	/*
778	* Validate the range.
779	*/
780	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)RTAvlroGCPhysGet(&pVM->pgm.s.CTXSUFF(pTrees)->PhysHandlers, GCPhys);
781	if (pCur)
782	{
783	if ( GCPhysPage >= pCur->Core.Key
784	&& GCPhysPage <= pCur->Core.KeyLast)
785	{
786	/*
787	* Ok, check that the type is right and then clear the flag.
788	*/
789	unsigned fFlag;
790	switch (pCur->enmType)
791	{
792	case PGMPHYSHANDLERTYPE_PHYSICAL_WRITE:
793	fFlag = MM_RAM_FLAGS_PHYSICAL_WRITE;
794	break;
795
796	case PGMPHYSHANDLERTYPE_PHYSICAL_ALL:
797	fFlag = MM_RAM_FLAGS_PHYSICAL_ALL;
798	break;
799
800	case PGMPHYSHANDLERTYPE_MMIO:
801	case PGMPHYSHANDLERTYPE_PHYSICAL:
802	AssertMsgFailed(("Cannot disable an MMIO or natural PHYSICAL access handler! enmType=%d\n", pCur->enmType));
803	return VERR_ACCESS_DENIED;
804
805	default:
806	AssertMsgFailed(("Invalid mapping type %d\n", pCur->enmType));
807	return VERR_INTERNAL_ERROR;
808	}
809
810	/** @todo add a function which does both clear and set! */
811	/* clear and set */
812	PPGMRAMRANGE pHint = NULL;
813	int rc = PGMRamFlagsClearByGCPhysWithHint(&pVM->pgm.s, GCPhysPage, fFlag, &pHint);
814	if (VBOX_SUCCESS(rc))
815	rc = PGMRamFlagsSetByGCPhysWithHint(&pVM->pgm.s, GCPhysPage, MM_RAM_FLAGS_PHYSICAL_TEMP_OFF, &pHint);
816	return rc;
817	}
818	AssertMsgFailed(("The page %#x is outside the range %#x-%#x\n",
819	GCPhysPage, pCur->Core.Key, pCur->Core.KeyLast));
820	return VERR_INVALID_PARAMETER;
821	}
822
823	AssertMsgFailed(("Specified physical handler start address %#x is invalid.\n", GCPhys));
824	return VERR_PGM_HANDLER_NOT_FOUND;
825	}
826
827
828	/**
829	* Turns access monitoring of a page within a monitored
830	* physical write/all page access handler regio back on.
831	*
832	* The caller must do required page table modifications.
833	*
834	* @returns VBox status code.
835	* @param pVM VM Handle
836	* @param GCPhys Start physical address earlier passed to PGMR3HandlerPhysicalRegister().
837	* @param GCPhysPage Physical address of the page to turn on access monitoring for.
838	*/
839	PGMDECL(int) PGMHandlerPhysicalPageReset(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage)
840	{
841	/*
842	* Validate the range.
843	*/
844	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)RTAvlroGCPhysGet(&pVM->pgm.s.CTXSUFF(pTrees)->PhysHandlers, GCPhys);
845	if (pCur)
846	{
847	if ( GCPhysPage >= pCur->Core.Key
848	&& GCPhysPage <= pCur->Core.KeyLast)
849	{
850	/*
851	* Ok, check that the type is right and then clear the flag.
852	*/
853	unsigned fFlag;
854	switch (pCur->enmType)
855	{
856	case PGMPHYSHANDLERTYPE_PHYSICAL_WRITE:
857	fFlag = MM_RAM_FLAGS_PHYSICAL_WRITE;
858	break;
859
860	case PGMPHYSHANDLERTYPE_PHYSICAL_ALL:
861	fFlag = MM_RAM_FLAGS_PHYSICAL_ALL;
862	break;
863
864	case PGMPHYSHANDLERTYPE_MMIO:
865	case PGMPHYSHANDLERTYPE_PHYSICAL:
866	AssertMsgFailed(("Cannot enable an MMIO or natural PHYSICAL access handler! enmType=%d\n", pCur->enmType));
867	return VERR_ACCESS_DENIED;
868
869	default:
870	AssertMsgFailed(("Invalid mapping type %d\n", pCur->enmType));
871	return VERR_INTERNAL_ERROR;
872	}
873
874	/** @todo add a function which does both clear and set! */
875	/* set and clear */
876	PPGMRAMRANGE pHint = NULL;
877	int rc = PGMRamFlagsSetByGCPhysWithHint(&pVM->pgm.s, GCPhysPage, fFlag, &pHint);
878	if (VBOX_SUCCESS(rc))
879	rc = PGMRamFlagsClearByGCPhysWithHint(&pVM->pgm.s, GCPhysPage, MM_RAM_FLAGS_PHYSICAL_TEMP_OFF, &pHint);
880	return rc;
881
882	}
883	AssertMsgFailed(("The page %#x is outside the range %#x-%#x\n",
884	GCPhysPage, pCur->Core.Key, pCur->Core.KeyLast));
885	return VERR_INVALID_PARAMETER;
886	}
887
888	AssertMsgFailed(("Specified physical handler start address %#x is invalid.\n", GCPhys));
889	return VERR_PGM_HANDLER_NOT_FOUND;
890	}
891
892
893	/**
894	* Checks if a physical range is handled
895	*
896	* @returns boolean
897	* @param pVM VM Handle
898	* @param GCPhys Start physical address earlier passed to PGMR3HandlerPhysicalRegister().
899	*/
900	PGMDECL(bool) PGMHandlerPhysicalIsRegistered(PVM pVM, RTGCPHYS GCPhys)
901	{
902	/*
903	* Find the handler.
904	*/
905	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)RTAvlroGCPhysGet(&pVM->pgm.s.CTXSUFF(pTrees)->PhysHandlers, GCPhys);
906	if (pCur)
907	{
908	if ( GCPhys >= pCur->Core.Key
909	&& GCPhys <= pCur->Core.KeyLast)
910	{
911	/*
912	* Validate type.
913	*/
914	switch (pCur->enmType)
915	{
916	case PGMPHYSHANDLERTYPE_PHYSICAL_WRITE:
917	case PGMPHYSHANDLERTYPE_PHYSICAL_ALL:
918	case PGMPHYSHANDLERTYPE_PHYSICAL:
919	case PGMPHYSHANDLERTYPE_MMIO:
920	return true;
921
922	default:
923	AssertMsgFailed(("Invalid type %d! Corruption!\n", pCur->enmType));
924	return false;
925	}
926	}
927	}
928
929	return false;
930	}
931
932
933	#ifdef VBOX_STRICT
934	DECLCALLBACK(int) pgmVirtHandlerDumpPhysRange(PAVLROGCPHYSNODECORE pNode, void *pvUser)
935	{
936	PPGMPHYS2VIRTHANDLER pCur = (PPGMPHYS2VIRTHANDLER)pNode;
937	PPGMVIRTHANDLER pVirt = (PPGMVIRTHANDLER)((uintptr_t)pCur + pCur->offVirtHandler);
938	Log(("PHYS2VIRT: Range %VGp-%VGp for virtual handler: %s\n", pCur->Core.Key, pCur->Core.KeyLast, pVirt->pszDesc));
939	return 0;
940	}
941
942
943	void pgmHandlerVirtualDumpPhysPages(PVM pVM)
944	{
945	RTAvlroGCPhysDoWithAll(CTXSUFF(&pVM->pgm.s.pTrees)->PhysToVirtHandlers, true, pgmVirtHandlerDumpPhysRange, 0);
946	}
947	#endif /* VBOX_STRICT */
948
949
950	/**
951	* Gets the current CR3 register value for the shadow memory context.
952	* @returns CR3 value.
953	* @param pVM The VM handle.
954	*/
955	PGMDECL(uint32_t) PGMGetHyperCR3(PVM pVM)
956	{
957	switch (pVM->pgm.s.enmShadowMode)
958	{
959	case PGMMODE_32_BIT:
960	return pVM->pgm.s.HCPhys32BitPD;
961
962	case PGMMODE_PAE:
963	case PGMMODE_PAE_NX:
964	return pVM->pgm.s.HCPhysPaePDPTR;
965
966	case PGMMODE_AMD64:
967	case PGMMODE_AMD64_NX:
968	return pVM->pgm.s.HCPhysPaePML4;
969
970	default:
971	AssertMsgFailed(("enmShadowMode=%d\n", pVM->pgm.s.enmShadowMode));
972	return ~0;
973	}
974	}
975
976
977	/**
978	* Gets the CR3 register value for the 32-Bit shadow memory context.
979	* @returns CR3 value.
980	* @param pVM The VM handle.
981	*/
982	PGMDECL(uint32_t) PGMGetHyper32BitCR3(PVM pVM)
983	{
984	return pVM->pgm.s.HCPhys32BitPD;
985	}
986
987
988	/**
989	* Gets the CR3 register value for the PAE shadow memory context.
990	* @returns CR3 value.
991	* @param pVM The VM handle.
992	*/
993	PGMDECL(uint32_t) PGMGetHyperPaeCR3(PVM pVM)
994	{
995	return pVM->pgm.s.HCPhysPaePDPTR;
996	}
997
998
999	/**
1000	* Gets the CR3 register value for the AMD64 shadow memory context.
1001	* @returns CR3 value.
1002	* @param pVM The VM handle.
1003	*/
1004	PGMDECL(uint32_t) PGMGetHyperAmd64CR3(PVM pVM)
1005	{
1006	return pVM->pgm.s.HCPhysPaePML4;
1007	}
1008
1009
1010	/**
1011	* Gets the current CR3 register value for the HC intermediate memory context.
1012	* @returns CR3 value.
1013	* @param pVM The VM handle.
1014	*/
1015	PGMDECL(uint32_t) PGMGetInterHCCR3(PVM pVM)
1016	{
1017	switch (pVM->pgm.s.enmHostMode)
1018	{
1019	case SUPPAGINGMODE_32_BIT:
1020	case SUPPAGINGMODE_32_BIT_GLOBAL:
1021	return pVM->pgm.s.HCPhysInterPD;
1022
1023	case SUPPAGINGMODE_PAE:
1024	case SUPPAGINGMODE_PAE_GLOBAL:
1025	case SUPPAGINGMODE_PAE_NX:
1026	case SUPPAGINGMODE_PAE_GLOBAL_NX:
1027	return pVM->pgm.s.HCPhysInterPaePDPTR;
1028
1029	case SUPPAGINGMODE_AMD64:
1030	case SUPPAGINGMODE_AMD64_GLOBAL:
1031	case SUPPAGINGMODE_AMD64_NX:
1032	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1033	return pVM->pgm.s.HCPhysInterPaePDPTR;
1034
1035	default:
1036	AssertMsgFailed(("enmHostMode=%d\n", pVM->pgm.s.enmHostMode));
1037	return ~0;
1038	}
1039	}
1040
1041
1042	/**
1043	* Gets the current CR3 register value for the GC intermediate memory context.
1044	* @returns CR3 value.
1045	* @param pVM The VM handle.
1046	*/
1047	PGMDECL(uint32_t) PGMGetInterGCCR3(PVM pVM)
1048	{
1049	switch (pVM->pgm.s.enmShadowMode)
1050	{
1051	case PGMMODE_32_BIT:
1052	return pVM->pgm.s.HCPhysInterPD;
1053
1054	case PGMMODE_PAE:
1055	case PGMMODE_PAE_NX:
1056	return pVM->pgm.s.HCPhysInterPaePDPTR;
1057
1058	case PGMMODE_AMD64:
1059	case PGMMODE_AMD64_NX:
1060	return pVM->pgm.s.HCPhysInterPaePML4;
1061
1062	default:
1063	AssertMsgFailed(("enmShadowMode=%d\n", pVM->pgm.s.enmShadowMode));
1064	return ~0;
1065	}
1066	}
1067
1068
1069	/**
1070	* Gets the CR3 register value for the 32-Bit intermediate memory context.
1071	* @returns CR3 value.
1072	* @param pVM The VM handle.
1073	*/
1074	PGMDECL(uint32_t) PGMGetInter32BitCR3(PVM pVM)
1075	{
1076	return pVM->pgm.s.HCPhysInterPD;
1077	}
1078
1079
1080	/**
1081	* Gets the CR3 register value for the PAE intermediate memory context.
1082	* @returns CR3 value.
1083	* @param pVM The VM handle.
1084	*/
1085	PGMDECL(uint32_t) PGMGetInterPaeCR3(PVM pVM)
1086	{
1087	return pVM->pgm.s.HCPhysInterPaePDPTR;
1088	}
1089
1090
1091	/**
1092	* Gets the CR3 register value for the AMD64 intermediate memory context.
1093	* @returns CR3 value.
1094	* @param pVM The VM handle.
1095	*/
1096	PGMDECL(uint32_t) PGMGetInterAmd64CR3(PVM pVM)
1097	{
1098	return pVM->pgm.s.HCPhysInterPaePML4;
1099	}
1100
1101
1102	/**
1103	* Performs and schedules necessary updates following a CR3 load or reload.
1104	*
1105	* This will normally involve mapping the guest PD or nPDPTR
1106	*
1107	* @returns VBox status code.
1108	* @retval VINF_PGM_SYNC_CR3 if monitoring requires a CR3 sync. This can
1109	* safely be ignored and overridden since the FF will be set too then.
1110	* @param pVM VM handle.
1111	* @param cr3 The new cr3.
1112	* @param fGlobal Indicates whether this is a global flush or not.
1113	*/
1114	PGMDECL(int) PGMFlushTLB(PVM pVM, uint32_t cr3, bool fGlobal)
1115	{
1116	/*
1117	* When in real or protected mode there is no TLB flushing, but
1118	* we may still be called because of REM not caring/knowing this.
1119	* REM is simple and we wish to keep it that way.
1120	*/
1121	if (pVM->pgm.s.enmGuestMode <= PGMMODE_PROTECTED)
1122	return VINF_SUCCESS;
1123	LogFlow(("PGMFlushTLB: cr3=%#x OldCr3=%#x fGlobal=%d\n", cr3, pVM->pgm.s.GCPhysCR3, fGlobal));
1124	STAM_PROFILE_START(&pVM->pgm.s.StatFlushTLB, a);
1125
1126	/*
1127	* Flag the necessary updates.
1128	*/
1129	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
1130	if (fGlobal)
1131	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
1132
1133	/*
1134	* Remap the CR3 content and adjust the monitoring if CR3 was actually changed.
1135	*/
1136	int rc = VINF_SUCCESS;
1137	RTGCPHYS GCPhysCR3;
1138	if ( pVM->pgm.s.enmGuestMode == PGMMODE_PAE
1139	\|\| pVM->pgm.s.enmGuestMode == PGMMODE_PAE_NX
1140	\|\| pVM->pgm.s.enmGuestMode == PGMMODE_AMD64
1141	\|\| pVM->pgm.s.enmGuestMode == PGMMODE_AMD64_NX)
1142	GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAE_PAGE_MASK);
1143	else
1144	GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAGE_MASK);
1145	if (pVM->pgm.s.GCPhysCR3 != GCPhysCR3)
1146	{
1147	pVM->pgm.s.GCPhysCR3 = GCPhysCR3;
1148	rc = PGM_GST_PFN(MapCR3, pVM)(pVM, GCPhysCR3);
1149	if (VBOX_SUCCESS(rc) && !pVM->pgm.s.fMappingsFixed)
1150	{
1151	pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
1152	rc = PGM_GST_PFN(MonitorCR3, pVM)(pVM, GCPhysCR3);
1153	}
1154	if (fGlobal)
1155	STAM_COUNTER_INC(&pVM->pgm.s.StatFlushTLBNewCR3Global);
1156	else
1157	STAM_COUNTER_INC(&pVM->pgm.s.StatFlushTLBNewCR3);
1158	}
1159	else
1160	{
1161	/*
1162	* Check if we have a pending update of the CR3 monitoring.
1163	*/
1164	if (pVM->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
1165	{
1166	pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
1167	Assert(!pVM->pgm.s.fMappingsFixed);
1168	rc = PGM_GST_PFN(MonitorCR3, pVM)(pVM, GCPhysCR3);
1169	}
1170	if (fGlobal)
1171	STAM_COUNTER_INC(&pVM->pgm.s.StatFlushTLBSameCR3Global);
1172	else
1173	STAM_COUNTER_INC(&pVM->pgm.s.StatFlushTLBSameCR3);
1174	}
1175
1176	STAM_PROFILE_STOP(&pVM->pgm.s.StatFlushTLB, a);
1177	return rc;
1178	}
1179
1180
1181	/**
1182	* Synchronize the paging structures.
1183	*
1184	* This function is called in response to the VM_FF_PGM_SYNC_CR3 and
1185	* VM_FF_PGM_SYNC_CR3_NONGLOBAL. Those two force action flags are set
1186	* in several places, most importantly whenever the CR3 is loaded.
1187	*
1188	* @returns VBox status code.
1189	* @param pVM The virtual machine.
1190	* @param cr0 Guest context CR0 register
1191	* @param cr3 Guest context CR3 register
1192	* @param cr4 Guest context CR4 register
1193	* @param fGlobal Including global page directories or not
1194	*/
1195	PGMDECL(int) PGMSyncCR3(PVM pVM, uint32_t cr0, uint32_t cr3, uint32_t cr4, bool fGlobal)
1196	{
1197	/*
1198	* We might be called when we shouldn't.
1199	*
1200	* The mode switching will ensure that the PD is resynced
1201	* after every mode switch. So, if we find ourselves here
1202	* when in protected or real mode we can safely disable the
1203	* FF and return immediately.
1204	*/
1205	if (pVM->pgm.s.enmGuestMode <= PGMMODE_PROTECTED)
1206	{
1207	Assert((cr0 & (X86_CR0_PG \| X86_CR0_PE)) != (X86_CR0_PG \| X86_CR0_PE));
1208	VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3);
1209	VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
1210	return VINF_SUCCESS;
1211	}
1212
1213	/* If global pages are not supported, then all flushes are global */
1214	if (!(cr4 & X86_CR4_PGE))
1215	fGlobal = true;
1216	LogFlow(("PGMSyncCR3: cr0=%08x cr3=%08x cr4=%08x fGlobal=%d[%d,%d]\n", cr0, cr3, cr4, fGlobal,
1217	VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3), VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL)));
1218
1219	/*
1220	* Let the 'Bth' function do the work and we'll just keep track of the flags.
1221	*/
1222	STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat,SyncCR3), a);
1223	int rc = PGM_BTH_PFN(SyncCR3, pVM)(pVM, cr0, cr3, cr4, fGlobal);
1224	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncCR3), a);
1225	AssertMsg(rc == VINF_SUCCESS \|\| rc == VINF_PGM_SYNC_CR3 \|\| VBOX_FAILURE(rc), ("rc=%VRc\n", rc));
1226	if (rc == VINF_SUCCESS)
1227	{
1228	if (!(pVM->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS))
1229	{
1230	VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3);
1231	VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
1232	}
1233
1234	/*
1235	* Check if we have a pending update of the CR3 monitoring.
1236	*/
1237	if (pVM->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
1238	{
1239	pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
1240	Assert(!pVM->pgm.s.fMappingsFixed);
1241	Assert(pVM->pgm.s.GCPhysCR3 == pVM->pgm.s.GCPhysGstCR3Monitored);
1242	rc = PGM_GST_PFN(MonitorCR3, pVM)(pVM, pVM->pgm.s.GCPhysCR3);
1243	}
1244	}
1245
1246	/*
1247	* Now flush the CR3 (guest context).
1248	*/
1249	if (rc == VINF_SUCCESS)
1250	PGM_INVL_GUEST_TLBS();
1251	return rc;
1252	}
1253
1254
1255	/**
1256	* Called whenever CR0 or CR4 in a way which may change
1257	* the paging mode.
1258	*
1259	* @returns VBox status code fit for scheduling in GC and R0.
1260	* @retval VINF_SUCCESS if the was no change, or it was successfully dealt with.
1261	* @retval VINF_PGM_CHANGE_MODE if we're in GC or R0 and the mode changes.
1262	* @param pVM VM handle.
1263	* @param cr0 The new cr0.
1264	* @param cr4 The new cr4.
1265	* @param efer The new extended feature enable register.
1266	*/
1267	PGMDECL(int) PGMChangeMode(PVM pVM, uint32_t cr0, uint32_t cr4, uint64_t efer)
1268	{
1269	PGMMODE enmGuestMode;
1270
1271	/*
1272	* Calc the new guest mode.
1273	*/
1274	if (!(cr0 & X86_CR0_PE))
1275	enmGuestMode = PGMMODE_REAL;
1276	else if (!(cr0 & X86_CR0_PG))
1277	enmGuestMode = PGMMODE_PROTECTED;
1278	else if (!(cr4 & X86_CR4_PAE))
1279	enmGuestMode = PGMMODE_32_BIT;
1280	else if (!(efer & MSR_K6_EFER_LME))
1281	{
1282	if (!(efer & MSR_K6_EFER_NXE))
1283	enmGuestMode = PGMMODE_PAE;
1284	else
1285	enmGuestMode = PGMMODE_PAE_NX;
1286	}
1287	else
1288	{
1289	if (!(efer & MSR_K6_EFER_NXE))
1290	enmGuestMode = PGMMODE_AMD64;
1291	else
1292	enmGuestMode = PGMMODE_AMD64_NX;
1293	}
1294
1295	/*
1296	* Did it change?
1297	*/
1298	if (pVM->pgm.s.enmGuestMode == enmGuestMode)
1299	return VINF_SUCCESS;
1300	#ifdef IN_RING3
1301	return pgmR3ChangeMode(pVM, enmGuestMode);
1302	#else
1303	Log(("PGMChangeMode: returns VINF_PGM_CHANGE_MODE.\n"));
1304	return VINF_PGM_CHANGE_MODE;
1305	#endif
1306	}
1307
1308
1309	/**
1310	* Gets the current guest paging mode.
1311	*
1312	* @returns The current paging mode.
1313	* @param pVM The VM handle.
1314	*/
1315	PGMDECL(PGMMODE) PGMGetGuestMode(PVM pVM)
1316	{
1317	return pVM->pgm.s.enmGuestMode;
1318	}
1319
1320
1321	/**
1322	* Gets the current shadow paging mode.
1323	*
1324	* @returns The current paging mode.
1325	* @param pVM The VM handle.
1326	*/
1327	PGMDECL(PGMMODE) PGMGetShadowMode(PVM pVM)
1328	{
1329	return pVM->pgm.s.enmShadowMode;
1330	}
1331
1332
1333	/**
1334	* Get mode name.
1335	*
1336	* @returns read-only name string.
1337	* @param enmMode The mode which name is desired.
1338	*/
1339	PGMDECL(const char *) PGMGetModeName(PGMMODE enmMode)
1340	{
1341	switch (enmMode)
1342	{
1343	case PGMMODE_REAL: return "real";
1344	case PGMMODE_PROTECTED: return "protected";
1345	case PGMMODE_32_BIT: return "32-bit";
1346	case PGMMODE_PAE: return "PAE";
1347	case PGMMODE_PAE_NX: return "PAE+NX";
1348	case PGMMODE_AMD64: return "AMD64";
1349	case PGMMODE_AMD64_NX: return "AMD64+NX";
1350	default: return "unknown mode value";
1351	}
1352	}
1353
1354
1355	/**
1356	* Acquire the PGM lock.
1357	*
1358	* @returns VBox status code
1359	* @param pVM The VM to operate on.
1360	*/
1361	int pgmLock(PVM pVM)
1362	{
1363	int rc = PDMCritSectEnter(&pVM->pgm.s.CritSect, VERR_SEM_BUSY);
1364	#ifdef IN_GC
1365	if (rc == VERR_SEM_BUSY)
1366	rc = VMMGCCallHost(pVM, VMMCALLHOST_PGM_LOCK, 0);
1367	#elif defined(IN_RING0)
1368	if (rc == VERR_SEM_BUSY)
1369	rc = VMMR0CallHost(pVM, VMMCALLHOST_PGM_LOCK, 0);
1370	#endif
1371	AssertRC(rc);
1372	return rc;
1373	}
1374
1375
1376	/**
1377	* Release the PGM lock.
1378	*
1379	* @returns VBox status code
1380	* @param pVM The VM to operate on.
1381	*/
1382	void pgmUnlock(PVM pVM)
1383	{
1384	PDMCritSectLeave(&pVM->pgm.s.CritSect);
1385	}
1386
1387
1388	#ifdef VBOX_STRICT
1389
1390	/**
1391	* State structure used by the PGMAssertHandlerAndFlagsInSync() function
1392	* and its AVL enumerators.
1393	*/
1394	typedef struct PGMAHAFIS
1395	{
1396	/** The VM handle. */
1397	PVM pVM;
1398	/** Number of errors. */
1399	unsigned cErrors;
1400	/** The flags we've found. */
1401	unsigned fFlagsFound;
1402	/** The flags we're matching up to.
1403	* This is also on the stack as a const, thus only valid during enumeration. */
1404	unsigned fFlags;
1405	/** The current physical address. */
1406	RTGCPHYS GCPhys;
1407	} PGMAHAFIS, *PPGMAHAFIS;
1408
1409	/**
1410	* Verify virtual handler by matching physical address.
1411	*
1412	* @returns 0
1413	* @param pNode Pointer to a PGMVIRTHANDLER.
1414	* @param pvUser Pointer to user parameter.
1415	*/
1416	static DECLCALLBACK(int) pgmVirtHandlerVerifyOneByPhysAddr(PAVLROGCPTRNODECORE pNode, void *pvUser)
1417	{
1418	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)pNode;
1419	PPGMAHAFIS pState = (PPGMAHAFIS)pvUser;
1420
1421	for (unsigned iPage = 0; iPage < pCur->cPages; iPage++)
1422	{
1423	if ((pCur->aPhysToVirt[iPage].Core.Key & X86_PTE_PAE_PG_MASK) == pState->GCPhys)
1424	{
1425	switch (pCur->enmType)
1426	{
1427	case PGMVIRTHANDLERTYPE_EIP:
1428	case PGMVIRTHANDLERTYPE_NORMAL: pState->fFlagsFound \|= MM_RAM_FLAGS_VIRTUAL_HANDLER; break;
1429	case PGMVIRTHANDLERTYPE_WRITE: pState->fFlagsFound \|= MM_RAM_FLAGS_VIRTUAL_HANDLER \| MM_RAM_FLAGS_VIRTUAL_WRITE; break;
1430	case PGMVIRTHANDLERTYPE_ALL: pState->fFlagsFound \|= MM_RAM_FLAGS_VIRTUAL_HANDLER \| MM_RAM_FLAGS_VIRTUAL_ALL; break;
1431	/* hypervisor handlers need no flags and wouldn't have nowhere to put them in any case. */
1432	case PGMVIRTHANDLERTYPE_HYPERVISOR:
1433	return 0;
1434	}
1435	if ( (pState->fFlags & (MM_RAM_FLAGS_VIRTUAL_HANDLER \| MM_RAM_FLAGS_VIRTUAL_WRITE \| MM_RAM_FLAGS_VIRTUAL_ALL))
1436	== pState->fFlagsFound)
1437	break;
1438	}
1439	}
1440	return 0;
1441	}
1442
1443
1444	/**
1445	* Verify a virtual handler.
1446	*
1447	* @returns 0
1448	* @param pNode Pointer to a PGMVIRTHANDLER.
1449	* @param pvUser Pointer to user parameter.
1450	*/
1451	static DECLCALLBACK(int) pgmVirtHandlerVerifyOne(PAVLROGCPTRNODECORE pNode, void *pvUser)
1452	{
1453	PPGMVIRTHANDLER pVirt = (PPGMVIRTHANDLER)pNode;
1454	PPGMAHAFIS pState = (PPGMAHAFIS)pvUser;
1455	PVM pVM = pState->pVM;
1456
1457	if ( pVirt->aPhysToVirt[0].Core.Key != NIL_RTGCPHYS
1458	&& (pVirt->aPhysToVirt[0].Core.Key & PAGE_OFFSET_MASK) != ((RTGCUINTPTR)pVirt->GCPtr & PAGE_OFFSET_MASK))
1459	{
1460	AssertMsgFailed(("virt handler phys out has incorrect key! %VGp %VGv %s\n",
1461	pVirt->aPhysToVirt[0].Core.Key, pVirt->GCPtr, HCSTRING(pVirt->pszDesc)));
1462	pState->cErrors++;
1463	}
1464
1465	/*
1466	* Calc flags.
1467	*/
1468	unsigned fFlags;
1469	switch (pVirt->enmType)
1470	{
1471	case PGMVIRTHANDLERTYPE_EIP:
1472	case PGMVIRTHANDLERTYPE_NORMAL: fFlags = MM_RAM_FLAGS_VIRTUAL_HANDLER; break;
1473	case PGMVIRTHANDLERTYPE_WRITE: fFlags = MM_RAM_FLAGS_VIRTUAL_HANDLER \| MM_RAM_FLAGS_VIRTUAL_WRITE; break;
1474	case PGMVIRTHANDLERTYPE_ALL: fFlags = MM_RAM_FLAGS_VIRTUAL_HANDLER \| MM_RAM_FLAGS_VIRTUAL_ALL; break;
1475	/* hypervisor handlers need no flags and wouldn't have nowhere to put them in any case. */
1476	case PGMVIRTHANDLERTYPE_HYPERVISOR:
1477	return 0;
1478	default:
1479	AssertMsgFailed(("unknown enmType=%d\n", pVirt->enmType));
1480	return 0;
1481	}
1482
1483	/*
1484	* Check pages against flags.
1485	*/
1486	RTGCUINTPTR GCPtr = (RTGCUINTPTR)pVirt->GCPtr;
1487	for (unsigned iPage = 0; iPage < pVirt->cPages; iPage++, GCPtr += PAGE_SIZE)
1488	{
1489	RTGCPHYS GCPhysGst;
1490	uint64_t fGst;
1491	int rc = PGMGstGetPage(pVM, (RTGCPTR)GCPtr, &fGst, &GCPhysGst);
1492	if (rc == VERR_PAGE_NOT_PRESENT)
1493	{
1494	if (pVirt->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
1495	{
1496	AssertMsgFailed(("virt handler phys out of sync. %VGp GCPhysNew=~0 iPage=%#x %VGv %s\n",
1497	pVirt->aPhysToVirt[iPage].Core.Key, iPage, GCPtr, HCSTRING(pVirt->pszDesc)));
1498	pState->cErrors++;
1499	}
1500	continue;
1501	}
1502
1503	AssertRCReturn(rc, 0);
1504	if ((pVirt->aPhysToVirt[iPage].Core.Key & X86_PTE_PAE_PG_MASK) != GCPhysGst)
1505	{
1506	AssertMsgFailed(("virt handler phys out of sync. %VGp GCPhysGst=%VGp iPage=%#x %VGv %s\n",
1507	pVirt->aPhysToVirt[iPage].Core.Key, GCPhysGst, iPage, GCPtr, HCSTRING(pVirt->pszDesc)));
1508	pState->cErrors++;
1509	continue;
1510	}
1511
1512	RTHCPHYS HCPhys;
1513	rc = PGMRamGCPhys2HCPhysWithFlags(&pVM->pgm.s, GCPhysGst, &HCPhys);
1514	if (VBOX_FAILURE(rc))
1515	{
1516	AssertMsgFailed(("virt handler getting ram flags rc=%Vrc. GCPhysGst=%VGp iPage=%#x %VGv %s\n",
1517	rc, GCPhysGst, iPage, GCPtr, HCSTRING(pVirt->pszDesc)));
1518	pState->cErrors++;
1519	continue;
1520	}
1521
1522	if ((HCPhys & fFlags) != fFlags)
1523	{
1524	AssertMsgFailed(("virt handler flags mismatch. HCPhys=%VHp fFlags=%#x GCPhysGst=%VGp iPage=%#x %VGv %s\n",
1525	HCPhys, fFlags, GCPhysGst, iPage, GCPtr, HCSTRING(pVirt->pszDesc)));
1526	pState->cErrors++;
1527	continue;
1528	}
1529	} /* for pages in virtual mapping. */
1530
1531	return 0;
1532	}
1533
1534
1535	/**
1536	* Asserts that the handlers+guest-page-tables == ramrange-flags and
1537	* that the physical addresses associated with virtual handlers are correct.
1538	*
1539	* @returns Number of mismatches.
1540	* @param pVM The VM handle.
1541	*/
1542	PGMDECL(unsigned) PGMAssertHandlerAndFlagsInSync(PVM pVM)
1543	{
1544	PPGM pPGM = &pVM->pgm.s;
1545	PGMAHAFIS State;
1546	State.cErrors = 0;
1547	State.pVM = pVM;
1548
1549	/*
1550	* Check the RAM flags against the handlers.
1551	*/
1552	for (PPGMRAMRANGE pRam = CTXSUFF(pPGM->pRamRanges); pRam; pRam = CTXSUFF(pRam->pNext))
1553	{
1554	const unsigned cPages = pRam->cb >> PAGE_SHIFT;
1555	for (unsigned iPage = 0; iPage < cPages; iPage++)
1556	{
1557	State.GCPhys = pRam->GCPhys + (iPage << PAGE_SHIFT);
1558	const unsigned fFlags = pRam->aHCPhys[iPage]
1559	& ( MM_RAM_FLAGS_VIRTUAL_HANDLER \| MM_RAM_FLAGS_VIRTUAL_WRITE \| MM_RAM_FLAGS_VIRTUAL_ALL
1560	\| MM_RAM_FLAGS_PHYSICAL_HANDLER \| MM_RAM_FLAGS_PHYSICAL_WRITE \| MM_RAM_FLAGS_PHYSICAL_ALL \| MM_RAM_FLAGS_PHYSICAL_TEMP_OFF);
1561	if (fFlags)
1562	{
1563	State.fFlagsFound = 0; /* build flags and compare. */
1564
1565	/* physical first. (simple because of page alignment) */
1566	if ( !(fFlags & MM_RAM_FLAGS_PHYSICAL_TEMP_OFF)
1567	&& (fFlags & (MM_RAM_FLAGS_PHYSICAL_HANDLER \| MM_RAM_FLAGS_PHYSICAL_WRITE \| MM_RAM_FLAGS_PHYSICAL_ALL)))
1568	{
1569	PPGMPHYSHANDLER pPhys = (PPGMPHYSHANDLER)RTAvlroGCPhysRangeGet(&pPGM->CTXSUFF(pTrees)->PhysHandlers, State.GCPhys);
1570	if (!pPhys)
1571	{
1572	pPhys = (PPGMPHYSHANDLER)RTAvlroGCPhysGetBestFit(&pPGM->CTXSUFF(pTrees)->PhysHandlers, State.GCPhys, true);
1573	if ( pPhys
1574	&& pPhys->Core.Key > (State.GCPhys + PAGE_SIZE - 1))
1575	pPhys = NULL;
1576	Assert(!pPhys \|\| pPhys->Core.Key >= State.GCPhys);
1577	}
1578	if (pPhys)
1579	{
1580	switch (pPhys->enmType)
1581	{
1582	case PGMPHYSHANDLERTYPE_PHYSICAL: State.fFlagsFound \|= MM_RAM_FLAGS_PHYSICAL_HANDLER; break;
1583	case PGMPHYSHANDLERTYPE_PHYSICAL_WRITE: State.fFlagsFound \|= MM_RAM_FLAGS_PHYSICAL_HANDLER \| MM_RAM_FLAGS_PHYSICAL_WRITE; break;
1584	case PGMPHYSHANDLERTYPE_MMIO:
1585	case PGMPHYSHANDLERTYPE_PHYSICAL_ALL: State.fFlagsFound \|= MM_RAM_FLAGS_PHYSICAL_HANDLER \| MM_RAM_FLAGS_PHYSICAL_ALL; break;
1586	default: AssertMsgFailed(("Invalid type phys type %d\n", pPhys->enmType)); State.cErrors++; break;
1587	}
1588	if ( (fFlags & (MM_RAM_FLAGS_PHYSICAL_HANDLER \| MM_RAM_FLAGS_PHYSICAL_WRITE \| MM_RAM_FLAGS_PHYSICAL_ALL))
1589	!= State.fFlagsFound)
1590	{
1591	AssertMsgFailed(("ram range vs phys handler flags mismatch. GCPhys=%#x fFlags=%#x fFlagsFound=%#x %s\n",
1592	State.GCPhys, fFlags, State.fFlagsFound, pPhys->pszDesc));
1593	State.cErrors++;
1594	}
1595
1596	#ifdef IN_RING3
1597	/* validate that REM is handling it. */
1598	if (!REMR3IsPageAccessHandled(pVM, State.GCPhys))
1599	{
1600	AssertMsgFailed(("ram range vs phys handler REM mismatch. GCPhys=%#x fFlags=%#x %s\n",
1601	State.GCPhys, fFlags, pPhys->pszDesc));
1602	State.cErrors++;
1603	}
1604	#endif
1605	}
1606	else
1607	{
1608	AssertMsgFailed(("ram range vs phys handler mismatch. no handler for GCPhys=%#x\n", State.GCPhys));
1609	State.cErrors++;
1610	}
1611	}
1612
1613	/* virtual flags. */
1614	if (fFlags & (MM_RAM_FLAGS_VIRTUAL_HANDLER \| MM_RAM_FLAGS_VIRTUAL_WRITE \| MM_RAM_FLAGS_VIRTUAL_ALL))
1615	{
1616	State.fFlags = fFlags;
1617	RTAvlroGCPtrDoWithAll(CTXSUFF(&pVM->pgm.s.pTrees)->VirtHandlers, true, pgmVirtHandlerVerifyOneByPhysAddr, &State);
1618	if ( (fFlags & (MM_RAM_FLAGS_VIRTUAL_HANDLER \| MM_RAM_FLAGS_VIRTUAL_WRITE \| MM_RAM_FLAGS_VIRTUAL_ALL))
1619	!= State.fFlagsFound)
1620	{
1621	AssertMsgFailed(("ram range vs virt handler flags mismatch. GCPhys=%#x fFlags=%#x fFlagsFound=%#x\n",
1622	State.GCPhys, fFlags, State.fFlagsFound));
1623	State.cErrors++;
1624	}
1625
1626	}
1627	}
1628	} /* foreach page in ram range. */
1629	} /* foreach ram range. */
1630
1631	/*
1632	* Check that the physical addresses of the virtual handlers matches up.
1633	*/
1634	RTAvlroGCPtrDoWithAll(CTXSUFF(&pVM->pgm.s.pTrees)->VirtHandlers, true, pgmVirtHandlerVerifyOne, &State);
1635
1636	return State.cErrors;
1637	}
1638
1639
1640	/**
1641	* Asserts that there are no mapping conflicts.
1642	*
1643	* @returns Number of conflicts.
1644	* @param pVM The VM Handle.
1645	*/
1646	PGMDECL(unsigned) PGMAssertNoMappingConflicts(PVM pVM)
1647	{
1648	unsigned cErrors = 0;
1649
1650	/*
1651	* Check for mapping conflicts.
1652	*/
1653	for (PPGMMAPPING pMapping = CTXSUFF(pVM->pgm.s.pMappings);
1654	pMapping;
1655	pMapping = CTXSUFF(pMapping->pNext))
1656	{
1657	/** @todo This is slow and should be optimized, but since it's just assertions I don't care now. */
1658	for (RTGCUINTPTR GCPtr = (RTGCUINTPTR)pMapping->GCPtr;
1659	GCPtr <= (RTGCUINTPTR)pMapping->GCPtrLast;
1660	GCPtr += PAGE_SIZE)
1661	{
1662	int rc = PGMGstGetPage(pVM, (RTGCPTR)GCPtr, NULL, NULL);
1663	if (rc != VERR_PAGE_TABLE_NOT_PRESENT)
1664	{
1665	AssertMsgFailed(("Conflict at %VGv with %s\n", GCPtr, HCSTRING(pMapping->pszDesc)));
1666	cErrors++;
1667	break;
1668	}
1669	}
1670	}
1671
1672	return cErrors;
1673	}
1674
1675
1676	/**
1677	* Asserts that everything related to the guest CR3 is correctly shadowed.
1678	*
1679	* This will call PGMAssertNoMappingConflicts() and PGMAssertHandlerAndFlagsInSync(),
1680	* and assert the correctness of the guest CR3 mapping before asserting that the
1681	* shadow page tables is in sync with the guest page tables.
1682	*
1683	* @returns Number of conflicts.
1684	* @param pVM The VM Handle.
1685	* @param cr3 The current guest CR3 register value.
1686	* @param cr4 The current guest CR4 register value.
1687	*/
1688	PGMDECL(unsigned) PGMAssertCR3(PVM pVM, uint32_t cr3, uint32_t cr4)
1689	{
1690	STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat,SyncCR3), a);
1691	unsigned cErrors = PGM_BTH_PFN(AssertCR3, pVM)(pVM, cr3, cr4, 0, ~(RTGCUINTPTR)0);
1692	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncCR3), a);
1693	return cErrors;
1694	}
1695
1696	#endif /* VBOX_STRICT */

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAll.cpp@ 1507

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