VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAll.cpp@ 17596

Last change on this file since 17596 was 17593, checked in by vboxsync, 16 years ago

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1/* $Id: PGMAll.cpp 17593 2009-03-09 17:11:35Z vboxsync $ */
2/** @file
3 * PGM - Page Manager and Monitor - All context code.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22/*******************************************************************************
23* Header Files *
24*******************************************************************************/
25#define LOG_GROUP LOG_GROUP_PGM
26#include <VBox/pgm.h>
27#include <VBox/cpum.h>
28#include <VBox/selm.h>
29#include <VBox/iom.h>
30#include <VBox/sup.h>
31#include <VBox/mm.h>
32#include <VBox/stam.h>
33#include <VBox/csam.h>
34#include <VBox/patm.h>
35#include <VBox/trpm.h>
36#include <VBox/rem.h>
37#include <VBox/em.h>
38#include <VBox/hwaccm.h>
39#include <VBox/hwacc_vmx.h>
40#include "PGMInternal.h"
41#include <VBox/vm.h>
42#include <iprt/assert.h>
43#include <iprt/asm.h>
44#include <iprt/string.h>
45#include <VBox/log.h>
46#include <VBox/param.h>
47#include <VBox/err.h>
48
49
50/*******************************************************************************
51* Structures and Typedefs *
52*******************************************************************************/
53/**
54 * Stated structure for PGM_GST_NAME(HandlerVirtualUpdate) that's
55 * passed to PGM_GST_NAME(VirtHandlerUpdateOne) during enumeration.
56 */
57typedef struct PGMHVUSTATE
58{
59 /** The VM handle. */
60 PVM pVM;
61 /** The todo flags. */
62 RTUINT fTodo;
63 /** The CR4 register value. */
64 uint32_t cr4;
65} PGMHVUSTATE, *PPGMHVUSTATE;
66
67
68/*******************************************************************************
69* Internal Functions *
70*******************************************************************************/
71DECLINLINE(int) pgmShwGetLongModePDPtr(PVM pVM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPT *ppPdpt, PX86PDPAE *ppPD);
72DECLINLINE(int) pgmShwGetPAEPDPtr(PVM pVM, RTGCPTR GCPtr, PX86PDPT *ppPdpt, PX86PDPAE *ppPD);
73DECLINLINE(int) pgmShwGetPaePoolPagePD(PPGM pPGM, RTGCPTR GCPtr, PPGMPOOLPAGE *ppShwPde);
74
75/*
76 * Shadow - 32-bit mode
77 */
78#define PGM_SHW_TYPE PGM_TYPE_32BIT
79#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
80#include "PGMAllShw.h"
81
82/* Guest - real mode */
83#define PGM_GST_TYPE PGM_TYPE_REAL
84#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
85#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
86#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
87#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
88#include "PGMGstDefs.h"
89#include "PGMAllGst.h"
90#include "PGMAllBth.h"
91#undef BTH_PGMPOOLKIND_PT_FOR_PT
92#undef BTH_PGMPOOLKIND_ROOT
93#undef PGM_BTH_NAME
94#undef PGM_GST_TYPE
95#undef PGM_GST_NAME
96
97/* Guest - protected mode */
98#define PGM_GST_TYPE PGM_TYPE_PROT
99#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
100#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
101#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
102#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
103#include "PGMGstDefs.h"
104#include "PGMAllGst.h"
105#include "PGMAllBth.h"
106#undef BTH_PGMPOOLKIND_PT_FOR_PT
107#undef BTH_PGMPOOLKIND_ROOT
108#undef PGM_BTH_NAME
109#undef PGM_GST_TYPE
110#undef PGM_GST_NAME
111
112/* Guest - 32-bit mode */
113#define PGM_GST_TYPE PGM_TYPE_32BIT
114#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
115#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
116#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
117#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
118#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD
119#include "PGMGstDefs.h"
120#include "PGMAllGst.h"
121#include "PGMAllBth.h"
122#undef BTH_PGMPOOLKIND_PT_FOR_BIG
123#undef BTH_PGMPOOLKIND_PT_FOR_PT
124#undef BTH_PGMPOOLKIND_ROOT
125#undef PGM_BTH_NAME
126#undef PGM_GST_TYPE
127#undef PGM_GST_NAME
128
129#undef PGM_SHW_TYPE
130#undef PGM_SHW_NAME
131
132
133/*
134 * Shadow - PAE mode
135 */
136#define PGM_SHW_TYPE PGM_TYPE_PAE
137#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
138#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
139#include "PGMAllShw.h"
140
141/* Guest - real mode */
142#define PGM_GST_TYPE PGM_TYPE_REAL
143#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
144#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
145#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
146#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
147#include "PGMGstDefs.h"
148#include "PGMAllBth.h"
149#undef BTH_PGMPOOLKIND_PT_FOR_PT
150#undef BTH_PGMPOOLKIND_ROOT
151#undef PGM_BTH_NAME
152#undef PGM_GST_TYPE
153#undef PGM_GST_NAME
154
155/* Guest - protected mode */
156#define PGM_GST_TYPE PGM_TYPE_PROT
157#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
158#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
159#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
160#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
161#include "PGMGstDefs.h"
162#include "PGMAllBth.h"
163#undef BTH_PGMPOOLKIND_PT_FOR_PT
164#undef BTH_PGMPOOLKIND_ROOT
165#undef PGM_BTH_NAME
166#undef PGM_GST_TYPE
167#undef PGM_GST_NAME
168
169/* Guest - 32-bit mode */
170#define PGM_GST_TYPE PGM_TYPE_32BIT
171#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
172#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
173#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
174#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
175#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_FOR_32BIT
176#include "PGMGstDefs.h"
177#include "PGMAllBth.h"
178#undef BTH_PGMPOOLKIND_PT_FOR_BIG
179#undef BTH_PGMPOOLKIND_PT_FOR_PT
180#undef BTH_PGMPOOLKIND_ROOT
181#undef PGM_BTH_NAME
182#undef PGM_GST_TYPE
183#undef PGM_GST_NAME
184
185
186/* Guest - PAE mode */
187#define PGM_GST_TYPE PGM_TYPE_PAE
188#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
189#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
190#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
191#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
192#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT
193#include "PGMGstDefs.h"
194#include "PGMAllGst.h"
195#include "PGMAllBth.h"
196#undef BTH_PGMPOOLKIND_PT_FOR_BIG
197#undef BTH_PGMPOOLKIND_PT_FOR_PT
198#undef BTH_PGMPOOLKIND_ROOT
199#undef PGM_BTH_NAME
200#undef PGM_GST_TYPE
201#undef PGM_GST_NAME
202
203#undef PGM_SHW_TYPE
204#undef PGM_SHW_NAME
205
206
207#ifndef IN_RC /* AMD64 implies VT-x/AMD-V */
208/*
209 * Shadow - AMD64 mode
210 */
211# define PGM_SHW_TYPE PGM_TYPE_AMD64
212# define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
213# include "PGMAllShw.h"
214
215/* Guest - protected mode (only used for AMD-V nested paging in 64 bits mode) */
216# define PGM_GST_TYPE PGM_TYPE_PROT
217# define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
218# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_PROT(name)
219# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
220# define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PD_PHYS
221# include "PGMGstDefs.h"
222# include "PGMAllBth.h"
223# undef BTH_PGMPOOLKIND_PT_FOR_PT
224# undef BTH_PGMPOOLKIND_ROOT
225# undef PGM_BTH_NAME
226# undef PGM_GST_TYPE
227# undef PGM_GST_NAME
228
229# ifdef VBOX_WITH_64_BITS_GUESTS
230/* Guest - AMD64 mode */
231# define PGM_GST_TYPE PGM_TYPE_AMD64
232# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
233# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
234# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
235# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
236# define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_64BIT_PML4
237# include "PGMGstDefs.h"
238# include "PGMAllGst.h"
239# include "PGMAllBth.h"
240# undef BTH_PGMPOOLKIND_PT_FOR_BIG
241# undef BTH_PGMPOOLKIND_PT_FOR_PT
242# undef BTH_PGMPOOLKIND_ROOT
243# undef PGM_BTH_NAME
244# undef PGM_GST_TYPE
245# undef PGM_GST_NAME
246# endif /* VBOX_WITH_64_BITS_GUESTS */
247
248# undef PGM_SHW_TYPE
249# undef PGM_SHW_NAME
250
251
252/*
253 * Shadow - Nested paging mode
254 */
255# define PGM_SHW_TYPE PGM_TYPE_NESTED
256# define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED(name)
257# include "PGMAllShw.h"
258
259/* Guest - real mode */
260# define PGM_GST_TYPE PGM_TYPE_REAL
261# define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
262# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_REAL(name)
263# include "PGMGstDefs.h"
264# include "PGMAllBth.h"
265# undef PGM_BTH_NAME
266# undef PGM_GST_TYPE
267# undef PGM_GST_NAME
268
269/* Guest - protected mode */
270# define PGM_GST_TYPE PGM_TYPE_PROT
271# define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
272# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PROT(name)
273# include "PGMGstDefs.h"
274# include "PGMAllBth.h"
275# undef PGM_BTH_NAME
276# undef PGM_GST_TYPE
277# undef PGM_GST_NAME
278
279/* Guest - 32-bit mode */
280# define PGM_GST_TYPE PGM_TYPE_32BIT
281# define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
282# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT(name)
283# include "PGMGstDefs.h"
284# include "PGMAllBth.h"
285# undef PGM_BTH_NAME
286# undef PGM_GST_TYPE
287# undef PGM_GST_NAME
288
289/* Guest - PAE mode */
290# define PGM_GST_TYPE PGM_TYPE_PAE
291# define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
292# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE(name)
293# include "PGMGstDefs.h"
294# include "PGMAllBth.h"
295# undef PGM_BTH_NAME
296# undef PGM_GST_TYPE
297# undef PGM_GST_NAME
298
299# ifdef VBOX_WITH_64_BITS_GUESTS
300/* Guest - AMD64 mode */
301# define PGM_GST_TYPE PGM_TYPE_AMD64
302# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
303# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64(name)
304# include "PGMGstDefs.h"
305# include "PGMAllBth.h"
306# undef PGM_BTH_NAME
307# undef PGM_GST_TYPE
308# undef PGM_GST_NAME
309# endif /* VBOX_WITH_64_BITS_GUESTS */
310
311# undef PGM_SHW_TYPE
312# undef PGM_SHW_NAME
313
314
315/*
316 * Shadow - EPT
317 */
318# define PGM_SHW_TYPE PGM_TYPE_EPT
319# define PGM_SHW_NAME(name) PGM_SHW_NAME_EPT(name)
320# include "PGMAllShw.h"
321
322/* Guest - real mode */
323# define PGM_GST_TYPE PGM_TYPE_REAL
324# define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
325# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_REAL(name)
326# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
327# include "PGMGstDefs.h"
328# include "PGMAllBth.h"
329# undef BTH_PGMPOOLKIND_PT_FOR_PT
330# undef PGM_BTH_NAME
331# undef PGM_GST_TYPE
332# undef PGM_GST_NAME
333
334/* Guest - protected mode */
335# define PGM_GST_TYPE PGM_TYPE_PROT
336# define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
337# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PROT(name)
338# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
339# include "PGMGstDefs.h"
340# include "PGMAllBth.h"
341# undef BTH_PGMPOOLKIND_PT_FOR_PT
342# undef PGM_BTH_NAME
343# undef PGM_GST_TYPE
344# undef PGM_GST_NAME
345
346/* Guest - 32-bit mode */
347# define PGM_GST_TYPE PGM_TYPE_32BIT
348# define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
349# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_32BIT(name)
350# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
351# include "PGMGstDefs.h"
352# include "PGMAllBth.h"
353# undef BTH_PGMPOOLKIND_PT_FOR_PT
354# undef PGM_BTH_NAME
355# undef PGM_GST_TYPE
356# undef PGM_GST_NAME
357
358/* Guest - PAE mode */
359# define PGM_GST_TYPE PGM_TYPE_PAE
360# define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
361# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PAE(name)
362# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
363# include "PGMGstDefs.h"
364# include "PGMAllBth.h"
365# undef BTH_PGMPOOLKIND_PT_FOR_PT
366# undef PGM_BTH_NAME
367# undef PGM_GST_TYPE
368# undef PGM_GST_NAME
369
370# ifdef VBOX_WITH_64_BITS_GUESTS
371/* Guest - AMD64 mode */
372# define PGM_GST_TYPE PGM_TYPE_AMD64
373# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
374# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_AMD64(name)
375# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
376# include "PGMGstDefs.h"
377# include "PGMAllBth.h"
378# undef BTH_PGMPOOLKIND_PT_FOR_PT
379# undef PGM_BTH_NAME
380# undef PGM_GST_TYPE
381# undef PGM_GST_NAME
382# endif /* VBOX_WITH_64_BITS_GUESTS */
383
384# undef PGM_SHW_TYPE
385# undef PGM_SHW_NAME
386
387#endif /* !IN_RC */
388
389
390#ifndef IN_RING3
391/**
392 * #PF Handler.
393 *
394 * @returns VBox status code (appropriate for trap handling and GC return).
395 * @param pVM VM Handle.
396 * @param uErr The trap error code.
397 * @param pRegFrame Trap register frame.
398 * @param pvFault The fault address.
399 */
400VMMDECL(int) PGMTrap0eHandler(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
401{
402 LogFlow(("PGMTrap0eHandler: uErr=%RGu pvFault=%RGv eip=%RGv\n", uErr, pvFault, (RTGCPTR)pRegFrame->rip));
403 STAM_PROFILE_START(&pVM->pgm.s.StatRZTrap0e, a);
404 STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = NULL; } );
405
406
407#ifdef VBOX_WITH_STATISTICS
408 /*
409 * Error code stats.
410 */
411 if (uErr & X86_TRAP_PF_US)
412 {
413 if (!(uErr & X86_TRAP_PF_P))
414 {
415 if (uErr & X86_TRAP_PF_RW)
416 STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eUSNotPresentWrite);
417 else
418 STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eUSNotPresentRead);
419 }
420 else if (uErr & X86_TRAP_PF_RW)
421 STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eUSWrite);
422 else if (uErr & X86_TRAP_PF_RSVD)
423 STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eUSReserved);
424 else if (uErr & X86_TRAP_PF_ID)
425 STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eUSNXE);
426 else
427 STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eUSRead);
428 }
429 else
430 { /* Supervisor */
431 if (!(uErr & X86_TRAP_PF_P))
432 {
433 if (uErr & X86_TRAP_PF_RW)
434 STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eSVNotPresentWrite);
435 else
436 STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eSVNotPresentRead);
437 }
438 else if (uErr & X86_TRAP_PF_RW)
439 STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eSVWrite);
440 else if (uErr & X86_TRAP_PF_ID)
441 STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eSNXE);
442 else if (uErr & X86_TRAP_PF_RSVD)
443 STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eSVReserved);
444 }
445#endif /* VBOX_WITH_STATISTICS */
446
447 /*
448 * Call the worker.
449 */
450 int rc = PGM_BTH_PFN(Trap0eHandler, pVM)(pVM, uErr, pRegFrame, pvFault);
451 if (rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
452 rc = VINF_SUCCESS;
453 STAM_STATS({ if (rc == VINF_EM_RAW_GUEST_TRAP) STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eGuestPF); });
454 STAM_STATS({ if (!pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution))
455 pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2Misc; });
456 STAM_PROFILE_STOP_EX(&pVM->pgm.s.StatRZTrap0e, pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution), a);
457 return rc;
458}
459#endif /* !IN_RING3 */
460
461
462/**
463 * Prefetch a page
464 *
465 * Typically used to sync commonly used pages before entering raw mode
466 * after a CR3 reload.
467 *
468 * @returns VBox status code suitable for scheduling.
469 * @retval VINF_SUCCESS on success.
470 * @retval VINF_PGM_SYNC_CR3 if we're out of shadow pages or something like that.
471 * @param pVM VM handle.
472 * @param GCPtrPage Page to invalidate.
473 */
474VMMDECL(int) PGMPrefetchPage(PVM pVM, RTGCPTR GCPtrPage)
475{
476 STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,Prefetch), a);
477 int rc = PGM_BTH_PFN(PrefetchPage, pVM)(pVM, GCPtrPage);
478 STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,Prefetch), a);
479 AssertMsg(rc == VINF_SUCCESS || rc == VINF_PGM_SYNC_CR3 || RT_FAILURE(rc), ("rc=%Rrc\n", rc));
480 return rc;
481}
482
483
484/**
485 * Gets the mapping corresponding to the specified address (if any).
486 *
487 * @returns Pointer to the mapping.
488 * @returns NULL if not
489 *
490 * @param pVM The virtual machine.
491 * @param GCPtr The guest context pointer.
492 */
493PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr)
494{
495 PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
496 while (pMapping)
497 {
498 if ((uintptr_t)GCPtr < (uintptr_t)pMapping->GCPtr)
499 break;
500 if ((uintptr_t)GCPtr - (uintptr_t)pMapping->GCPtr < pMapping->cb)
501 return pMapping;
502 pMapping = pMapping->CTX_SUFF(pNext);
503 }
504 return NULL;
505}
506
507
508/**
509 * Verifies a range of pages for read or write access
510 *
511 * Only checks the guest's page tables
512 *
513 * @returns VBox status code.
514 * @param pVM VM handle.
515 * @param Addr Guest virtual address to check
516 * @param cbSize Access size
517 * @param fAccess Access type (r/w, user/supervisor (X86_PTE_*))
518 * @remarks Current not in use.
519 */
520VMMDECL(int) PGMIsValidAccess(PVM pVM, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess)
521{
522 /*
523 * Validate input.
524 */
525 if (fAccess & ~(X86_PTE_US | X86_PTE_RW))
526 {
527 AssertMsgFailed(("PGMIsValidAccess: invalid access type %08x\n", fAccess));
528 return VERR_INVALID_PARAMETER;
529 }
530
531 uint64_t fPage;
532 int rc = PGMGstGetPage(pVM, (RTGCPTR)Addr, &fPage, NULL);
533 if (RT_FAILURE(rc))
534 {
535 Log(("PGMIsValidAccess: access violation for %RGv rc=%d\n", Addr, rc));
536 return VINF_EM_RAW_GUEST_TRAP;
537 }
538
539 /*
540 * Check if the access would cause a page fault
541 *
542 * Note that hypervisor page directories are not present in the guest's tables, so this check
543 * is sufficient.
544 */
545 bool fWrite = !!(fAccess & X86_PTE_RW);
546 bool fUser = !!(fAccess & X86_PTE_US);
547 if ( !(fPage & X86_PTE_P)
548 || (fWrite && !(fPage & X86_PTE_RW))
549 || (fUser && !(fPage & X86_PTE_US)) )
550 {
551 Log(("PGMIsValidAccess: access violation for %RGv attr %#llx vs %d:%d\n", Addr, fPage, fWrite, fUser));
552 return VINF_EM_RAW_GUEST_TRAP;
553 }
554 if ( RT_SUCCESS(rc)
555 && PAGE_ADDRESS(Addr) != PAGE_ADDRESS(Addr + cbSize))
556 return PGMIsValidAccess(pVM, Addr + PAGE_SIZE, (cbSize > PAGE_SIZE) ? cbSize - PAGE_SIZE : 1, fAccess);
557 return rc;
558}
559
560
561/**
562 * Verifies a range of pages for read or write access
563 *
564 * Supports handling of pages marked for dirty bit tracking and CSAM
565 *
566 * @returns VBox status code.
567 * @param pVM VM handle.
568 * @param Addr Guest virtual address to check
569 * @param cbSize Access size
570 * @param fAccess Access type (r/w, user/supervisor (X86_PTE_*))
571 */
572VMMDECL(int) PGMVerifyAccess(PVM pVM, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess)
573{
574 AssertMsg(!(fAccess & ~(X86_PTE_US | X86_PTE_RW)), ("PGMVerifyAccess: invalid access type %08x\n", fAccess));
575
576 /*
577 * Get going.
578 */
579 uint64_t fPageGst;
580 int rc = PGMGstGetPage(pVM, (RTGCPTR)Addr, &fPageGst, NULL);
581 if (RT_FAILURE(rc))
582 {
583 Log(("PGMVerifyAccess: access violation for %RGv rc=%d\n", Addr, rc));
584 return VINF_EM_RAW_GUEST_TRAP;
585 }
586
587 /*
588 * Check if the access would cause a page fault
589 *
590 * Note that hypervisor page directories are not present in the guest's tables, so this check
591 * is sufficient.
592 */
593 const bool fWrite = !!(fAccess & X86_PTE_RW);
594 const bool fUser = !!(fAccess & X86_PTE_US);
595 if ( !(fPageGst & X86_PTE_P)
596 || (fWrite && !(fPageGst & X86_PTE_RW))
597 || (fUser && !(fPageGst & X86_PTE_US)) )
598 {
599 Log(("PGMVerifyAccess: access violation for %RGv attr %#llx vs %d:%d\n", Addr, fPageGst, fWrite, fUser));
600 return VINF_EM_RAW_GUEST_TRAP;
601 }
602
603 if (!HWACCMIsNestedPagingActive(pVM))
604 {
605 /*
606 * Next step is to verify if we protected this page for dirty bit tracking or for CSAM scanning
607 */
608 rc = PGMShwGetPage(pVM, (RTGCPTR)Addr, NULL, NULL);
609 if ( rc == VERR_PAGE_NOT_PRESENT
610 || rc == VERR_PAGE_TABLE_NOT_PRESENT)
611 {
612 /*
613 * Page is not present in our page tables.
614 * Try to sync it!
615 */
616 Assert(X86_TRAP_PF_RW == X86_PTE_RW && X86_TRAP_PF_US == X86_PTE_US);
617 uint32_t uErr = fAccess & (X86_TRAP_PF_RW | X86_TRAP_PF_US);
618 rc = PGM_BTH_PFN(VerifyAccessSyncPage, pVM)(pVM, Addr, fPageGst, uErr);
619 if (rc != VINF_SUCCESS)
620 return rc;
621 }
622 else
623 AssertMsg(rc == VINF_SUCCESS, ("PGMShwGetPage %RGv failed with %Rrc\n", Addr, rc));
624 }
625
626#if 0 /* def VBOX_STRICT; triggers too often now */
627 /*
628 * This check is a bit paranoid, but useful.
629 */
630 /** @note this will assert when writing to monitored pages (a bit annoying actually) */
631 uint64_t fPageShw;
632 rc = PGMShwGetPage(pVM, (RTGCPTR)Addr, &fPageShw, NULL);
633 if ( (rc == VERR_PAGE_NOT_PRESENT || RT_FAILURE(rc))
634 || (fWrite && !(fPageShw & X86_PTE_RW))
635 || (fUser && !(fPageShw & X86_PTE_US)) )
636 {
637 AssertMsgFailed(("Unexpected access violation for %RGv! rc=%Rrc write=%d user=%d\n",
638 Addr, rc, fWrite && !(fPageShw & X86_PTE_RW), fUser && !(fPageShw & X86_PTE_US)));
639 return VINF_EM_RAW_GUEST_TRAP;
640 }
641#endif
642
643 if ( RT_SUCCESS(rc)
644 && ( PAGE_ADDRESS(Addr) != PAGE_ADDRESS(Addr + cbSize - 1)
645 || Addr + cbSize < Addr))
646 {
647 /* Don't recursively call PGMVerifyAccess as we might run out of stack. */
648 for (;;)
649 {
650 Addr += PAGE_SIZE;
651 if (cbSize > PAGE_SIZE)
652 cbSize -= PAGE_SIZE;
653 else
654 cbSize = 1;
655 rc = PGMVerifyAccess(pVM, Addr, 1, fAccess);
656 if (rc != VINF_SUCCESS)
657 break;
658 if (PAGE_ADDRESS(Addr) == PAGE_ADDRESS(Addr + cbSize - 1))
659 break;
660 }
661 }
662 return rc;
663}
664
665
666/**
667 * Emulation of the invlpg instruction (HC only actually).
668 *
669 * @returns VBox status code, special care required.
670 * @retval VINF_PGM_SYNC_CR3 - handled.
671 * @retval VINF_EM_RAW_EMULATE_INSTR - not handled (RC only).
672 * @retval VERR_REM_FLUSHED_PAGES_OVERFLOW - not handled.
673 *
674 * @param pVM VM handle.
675 * @param GCPtrPage Page to invalidate.
676 *
677 * @remark ASSUMES the page table entry or page directory is valid. Fairly
678 * safe, but there could be edge cases!
679 *
680 * @todo Flush page or page directory only if necessary!
681 */
682VMMDECL(int) PGMInvalidatePage(PVM pVM, RTGCPTR GCPtrPage)
683{
684 int rc;
685 Log3(("PGMInvalidatePage: GCPtrPage=%RGv\n", GCPtrPage));
686
687#ifndef IN_RING3
688 /*
689 * Notify the recompiler so it can record this instruction.
690 * Failure happens when it's out of space. We'll return to HC in that case.
691 */
692 rc = REMNotifyInvalidatePage(pVM, GCPtrPage);
693 if (rc != VINF_SUCCESS)
694 return rc;
695#endif /* !IN_RING3 */
696
697
698#ifdef IN_RC
699 /*
700 * Check for conflicts and pending CR3 monitoring updates.
701 */
702 if (!pVM->pgm.s.fMappingsFixed)
703 {
704 if ( pgmGetMapping(pVM, GCPtrPage)
705 && PGMGstGetPage(pVM, GCPtrPage, NULL, NULL) != VERR_PAGE_TABLE_NOT_PRESENT)
706 {
707 LogFlow(("PGMGCInvalidatePage: Conflict!\n"));
708 VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
709 STAM_COUNTER_INC(&pVM->pgm.s.StatRCInvlPgConflict);
710 return VINF_PGM_SYNC_CR3;
711 }
712
713 if (pVM->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
714 {
715 LogFlow(("PGMGCInvalidatePage: PGM_SYNC_MONITOR_CR3 -> reinterpret instruction in R3\n"));
716 STAM_COUNTER_INC(&pVM->pgm.s.StatRCInvlPgSyncMonCR3);
717 return VINF_EM_RAW_EMULATE_INSTR;
718 }
719 }
720#endif /* IN_RC */
721
722 /*
723 * Call paging mode specific worker.
724 */
725 STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePage), a);
726 rc = PGM_BTH_PFN(InvalidatePage, pVM)(pVM, GCPtrPage);
727 STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePage), a);
728
729#ifdef IN_RING3
730 /*
731 * Check if we have a pending update of the CR3 monitoring.
732 */
733 if ( RT_SUCCESS(rc)
734 && (pVM->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3))
735 {
736 pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
737 Assert(!pVM->pgm.s.fMappingsFixed);
738 }
739
740 /*
741 * Inform CSAM about the flush
742 *
743 * Note: This is to check if monitored pages have been changed; when we implement
744 * callbacks for virtual handlers, this is no longer required.
745 */
746 CSAMR3FlushPage(pVM, GCPtrPage);
747#endif /* IN_RING3 */
748 return rc;
749}
750
751
752/**
753 * Executes an instruction using the interpreter.
754 *
755 * @returns VBox status code (appropriate for trap handling and GC return).
756 * @param pVM VM handle.
757 * @param pRegFrame Register frame.
758 * @param pvFault Fault address.
759 */
760VMMDECL(int) PGMInterpretInstruction(PVM pVM, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
761{
762 uint32_t cb;
763 int rc = EMInterpretInstruction(pVM, pRegFrame, pvFault, &cb);
764 if (rc == VERR_EM_INTERPRETER)
765 rc = VINF_EM_RAW_EMULATE_INSTR;
766 if (rc != VINF_SUCCESS)
767 Log(("PGMInterpretInstruction: returns %Rrc (pvFault=%RGv)\n", rc, pvFault));
768 return rc;
769}
770
771
772/**
773 * Gets effective page information (from the VMM page directory).
774 *
775 * @returns VBox status.
776 * @param pVM VM Handle.
777 * @param GCPtr Guest Context virtual address of the page.
778 * @param pfFlags Where to store the flags. These are X86_PTE_*.
779 * @param pHCPhys Where to store the HC physical address of the page.
780 * This is page aligned.
781 * @remark You should use PGMMapGetPage() for pages in a mapping.
782 */
783VMMDECL(int) PGMShwGetPage(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys)
784{
785 return PGM_SHW_PFN(GetPage,pVM)(pVM, GCPtr, pfFlags, pHCPhys);
786}
787
788
789/**
790 * Sets (replaces) the page flags for a range of pages in the shadow context.
791 *
792 * @returns VBox status.
793 * @param pVM VM handle.
794 * @param GCPtr The address of the first page.
795 * @param cb The size of the range in bytes.
796 * @param fFlags Page flags X86_PTE_*, excluding the page mask of course.
797 * @remark You must use PGMMapSetPage() for pages in a mapping.
798 */
799VMMDECL(int) PGMShwSetPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags)
800{
801 return PGMShwModifyPage(pVM, GCPtr, cb, fFlags, 0);
802}
803
804
805/**
806 * Modify page flags for a range of pages in the shadow context.
807 *
808 * The existing flags are ANDed with the fMask and ORed with the fFlags.
809 *
810 * @returns VBox status code.
811 * @param pVM VM handle.
812 * @param GCPtr Virtual address of the first page in the range.
813 * @param cb Size (in bytes) of the range to apply the modification to.
814 * @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
815 * @param fMask The AND mask - page flags X86_PTE_*.
816 * Be very CAREFUL when ~'ing constants which could be 32-bit!
817 * @remark You must use PGMMapModifyPage() for pages in a mapping.
818 */
819VMMDECL(int) PGMShwModifyPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
820{
821 AssertMsg(!(fFlags & X86_PTE_PAE_PG_MASK), ("fFlags=%#llx\n", fFlags));
822 Assert(cb);
823
824 /*
825 * Align the input.
826 */
827 cb += GCPtr & PAGE_OFFSET_MASK;
828 cb = RT_ALIGN_Z(cb, PAGE_SIZE);
829 GCPtr = (GCPtr & PAGE_BASE_GC_MASK); /** @todo this ain't necessary, right... */
830
831 /*
832 * Call worker.
833 */
834 return PGM_SHW_PFN(ModifyPage, pVM)(pVM, GCPtr, cb, fFlags, fMask);
835}
836
837
838/**
839 * Gets the SHADOW page directory pointer for the specified address.
840 *
841 * @returns VBox status.
842 * @param pVM VM handle.
843 * @param GCPtr The address.
844 * @param ppPdpt Receives address of pdpt
845 * @param ppPD Receives address of page directory
846 * @remarks Unused.
847 */
848DECLINLINE(int) pgmShwGetPAEPDPtr(PVM pVM, RTGCPTR GCPtr, PX86PDPT *ppPdpt, PX86PDPAE *ppPD)
849{
850 PPGM pPGM = &pVM->pgm.s;
851 PPGMPOOL pPool = pPGM->CTX_SUFF(pPool);
852 PPGMPOOLPAGE pShwPage;
853
854 Assert(!HWACCMIsNestedPagingActive(pVM));
855
856 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
857 PX86PDPT pPdpt = pgmShwGetPaePDPTPtr(&pVM->pgm.s);
858 PX86PDPE pPdpe = &pPdpt->a[iPdPt];
859
860 *ppPdpt = pPdpt;
861 if (!pPdpe->n.u1Present)
862 return VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT;
863
864 Assert(pPdpe->u & X86_PDPE_PG_MASK);
865 pShwPage = pgmPoolGetPage(pPool, pPdpe->u & X86_PDPE_PG_MASK);
866 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
867
868 *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
869 return VINF_SUCCESS;
870}
871
872/**
873 * Gets the shadow page directory for the specified address, PAE.
874 *
875 * @returns Pointer to the shadow PD.
876 * @param pVM VM handle.
877 * @param GCPtr The address.
878 * @param pGstPdpe Guest PDPT entry
879 * @param ppPD Receives address of page directory
880 */
881int pgmShwSyncPaePDPtr(PVM pVM, RTGCPTR GCPtr, PX86PDPE pGstPdpe, PX86PDPAE *ppPD)
882{
883 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
884 PX86PDPT pPdpt = pgmShwGetPaePDPTPtr(&pVM->pgm.s);
885 PX86PDPE pPdpe = &pPdpt->a[iPdPt];
886 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
887 PPGMPOOLPAGE pShwPage;
888 int rc;
889
890 /* Allocate page directory if not present. */
891 if ( !pPdpe->n.u1Present
892 && !(pPdpe->u & X86_PDPE_PG_MASK))
893 {
894 bool fNestedPaging = HWACCMIsNestedPagingActive(pVM);
895 bool fPaging = !!(CPUMGetGuestCR0(pVM) & X86_CR0_PG);
896 RTGCPTR64 GCPdPt;
897 PGMPOOLKIND enmKind;
898
899# if defined(IN_RC)
900 /* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
901 PGMDynLockHCPage(pVM, (uint8_t *)pPdpe);
902# endif
903
904 if (fNestedPaging || !fPaging)
905 {
906 /* AMD-V nested paging or real/protected mode without paging */
907 GCPdPt = (RTGCPTR64)iPdPt << X86_PDPT_SHIFT;
908 enmKind = PGMPOOLKIND_PAE_PD_PHYS;
909 }
910 else
911 {
912 Assert(pGstPdpe);
913
914 if (CPUMGetGuestCR4(pVM) & X86_CR4_PAE)
915 {
916 if (!pGstPdpe->n.u1Present)
917 {
918 /* PD not present; guest must reload CR3 to change it.
919 * No need to monitor anything in this case.
920 */
921 Assert(!HWACCMIsEnabled(pVM));
922
923 GCPdPt = pGstPdpe->u & X86_PDPE_PG_MASK;
924 enmKind = PGMPOOLKIND_PAE_PD_PHYS;
925 pGstPdpe->n.u1Present = 1;
926 }
927 else
928 {
929 GCPdPt = pGstPdpe->u & X86_PDPE_PG_MASK;
930 enmKind = PGMPOOLKIND_PAE_PD_FOR_PAE_PD;
931 }
932 }
933 else
934 {
935 GCPdPt = CPUMGetGuestCR3(pVM);
936 enmKind = (PGMPOOLKIND)(PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD + iPdPt);
937 }
938 }
939
940 /* Create a reference back to the PDPT by using the index in its shadow page. */
941 rc = pgmPoolAlloc(pVM, GCPdPt, enmKind, pVM->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPdPt, &pShwPage);
942 if (rc == VERR_PGM_POOL_FLUSHED)
943 {
944 Log(("pgmShwSyncPaePDPtr: PGM pool flushed -> signal sync cr3\n"));
945 Assert(pVM->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL);
946 VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
947# if defined(IN_RC)
948 PGMDynUnlockHCPage(pVM, (uint8_t *)pPdpe);
949# endif
950 return VINF_PGM_SYNC_CR3;
951 }
952 AssertRCReturn(rc, rc);
953
954 /* The PD was cached or created; hook it up now. */
955 pPdpe->u |= pShwPage->Core.Key
956 | (pGstPdpe->u & ~(X86_PDPE_PG_MASK | X86_PDPE_AVL_MASK | X86_PDPE_PCD | X86_PDPE_PWT));
957
958# if defined(IN_RC)
959 /* In 32 bits PAE mode we *must* invalidate the TLB when changing a PDPT entry; the CPU fetches them only during cr3 load, so any
960 * non-present PDPT will continue to cause page faults.
961 */
962 ASMReloadCR3();
963 PGMDynUnlockHCPage(pVM, (uint8_t *)pPdpe);
964# endif
965 }
966 else
967 {
968 pShwPage = pgmPoolGetPage(pPool, pPdpe->u & X86_PDPE_PG_MASK);
969 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
970
971 Assert((pPdpe->u & X86_PDPE_PG_MASK) == pShwPage->Core.Key);
972 }
973 *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
974 return VINF_SUCCESS;
975}
976
977
978/**
979 * Gets the pointer to the shadow page directory entry for an address, PAE.
980 *
981 * @returns Pointer to the PDE.
982 * @param pPGM Pointer to the PGM instance data.
983 * @param GCPtr The address.
984 * @param ppShwPde Receives the address of the pgm pool page for the shadow page directory
985 */
986DECLINLINE(int) pgmShwGetPaePoolPagePD(PPGM pPGM, RTGCPTR GCPtr, PPGMPOOLPAGE *ppShwPde)
987{
988 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
989 PX86PDPT pPdpt = pgmShwGetPaePDPTPtr(pPGM);
990 AssertReturn(pPdpt, VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT); /* can't happen */
991 if (!pPdpt->a[iPdPt].n.u1Present)
992 {
993 LogFlow(("pgmShwGetPaePoolPagePD: PD %d not present (%RX64)\n", iPdPt, pPdpt->a[iPdPt].u));
994 return VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT;
995 }
996 AssertMsg(pPdpt->a[iPdPt].u & X86_PDPE_PG_MASK, ("GCPtr=%RGv\n", GCPtr));
997
998 /* Fetch the pgm pool shadow descriptor. */
999 PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(PGM2VM(pPGM), pPdpt->a[iPdPt].u & X86_PDPE_PG_MASK);
1000 AssertReturn(pShwPde, VERR_INTERNAL_ERROR);
1001
1002 *ppShwPde = pShwPde;
1003 return VINF_SUCCESS;
1004}
1005
1006#ifndef IN_RC
1007
1008/**
1009 * Syncs the SHADOW page directory pointer for the specified address.
1010 *
1011 * Allocates backing pages in case the PDPT or PML4 entry is missing.
1012 *
1013 * The caller is responsible for making sure the guest has a valid PD before
1014 * calling this function.
1015 *
1016 * @returns VBox status.
1017 * @param pVM VM handle.
1018 * @param GCPtr The address.
1019 * @param pGstPml4e Guest PML4 entry
1020 * @param pGstPdpe Guest PDPT entry
1021 * @param ppPD Receives address of page directory
1022 */
1023int pgmShwSyncLongModePDPtr(PVM pVM, RTGCPTR64 GCPtr, PX86PML4E pGstPml4e, PX86PDPE pGstPdpe, PX86PDPAE *ppPD)
1024{
1025 PPGM pPGM = &pVM->pgm.s;
1026 PPGMPOOL pPool = pPGM->CTX_SUFF(pPool);
1027 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
1028 PX86PML4E pPml4e = pgmShwGetLongModePML4EPtr(pPGM, iPml4);
1029 bool fNestedPaging = HWACCMIsNestedPagingActive(pVM);
1030 bool fPaging = !!(CPUMGetGuestCR0(pVM) & X86_CR0_PG);
1031 PPGMPOOLPAGE pShwPage;
1032 int rc;
1033
1034 /* Allocate page directory pointer table if not present. */
1035 if ( !pPml4e->n.u1Present
1036 && !(pPml4e->u & X86_PML4E_PG_MASK))
1037 {
1038 RTGCPTR64 GCPml4;
1039 PGMPOOLKIND enmKind;
1040
1041 Assert(pVM->pgm.s.CTX_SUFF(pShwPageCR3));
1042
1043 if (fNestedPaging || !fPaging)
1044 {
1045 /* AMD-V nested paging or real/protected mode without paging */
1046 GCPml4 = (RTGCPTR64)iPml4 << X86_PML4_SHIFT;
1047 enmKind = PGMPOOLKIND_64BIT_PDPT_FOR_PHYS;
1048 }
1049 else
1050 {
1051 Assert(pGstPml4e && pGstPdpe);
1052
1053 GCPml4 = pGstPml4e->u & X86_PML4E_PG_MASK;
1054 enmKind = PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT;
1055 }
1056
1057 /* Create a reference back to the PDPT by using the index in its shadow page. */
1058 rc = pgmPoolAlloc(pVM, GCPml4, enmKind, pVM->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPml4, &pShwPage);
1059 if (rc == VERR_PGM_POOL_FLUSHED)
1060 {
1061 Log(("PGMShwSyncLongModePDPtr: PGM pool flushed (1) -> signal sync cr3\n"));
1062 Assert(pVM->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL);
1063 VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
1064 return VINF_PGM_SYNC_CR3;
1065 }
1066 AssertRCReturn(rc, rc);
1067 }
1068 else
1069 {
1070 pShwPage = pgmPoolGetPage(pPool, pPml4e->u & X86_PML4E_PG_MASK);
1071 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1072 }
1073 /* The PDPT was cached or created; hook it up now. */
1074 pPml4e->u |= pShwPage->Core.Key
1075 | (pGstPml4e->u & ~(X86_PML4E_PG_MASK | X86_PML4E_AVL_MASK | X86_PML4E_PCD | X86_PML4E_PWT));
1076
1077 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1078 PX86PDPT pPdpt = (PX86PDPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1079 PX86PDPE pPdpe = &pPdpt->a[iPdPt];
1080
1081 /* Allocate page directory if not present. */
1082 if ( !pPdpe->n.u1Present
1083 && !(pPdpe->u & X86_PDPE_PG_MASK))
1084 {
1085 RTGCPTR64 GCPdPt;
1086 PGMPOOLKIND enmKind;
1087
1088 if (fNestedPaging || !fPaging)
1089 {
1090 /* AMD-V nested paging or real/protected mode without paging */
1091 GCPdPt = (RTGCPTR64)iPdPt << X86_PDPT_SHIFT;
1092 enmKind = PGMPOOLKIND_64BIT_PD_FOR_PHYS;
1093 }
1094 else
1095 {
1096 Assert(pGstPdpe);
1097
1098 GCPdPt = pGstPdpe->u & X86_PDPE_PG_MASK;
1099 enmKind = PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD;
1100 }
1101
1102 /* Create a reference back to the PDPT by using the index in its shadow page. */
1103 rc = pgmPoolAlloc(pVM, GCPdPt, enmKind, pShwPage->idx, iPdPt, &pShwPage);
1104 if (rc == VERR_PGM_POOL_FLUSHED)
1105 {
1106 Log(("PGMShwSyncLongModePDPtr: PGM pool flushed (2) -> signal sync cr3\n"));
1107 Assert(pVM->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL);
1108 VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
1109 return VINF_PGM_SYNC_CR3;
1110 }
1111 AssertRCReturn(rc, rc);
1112 }
1113 else
1114 {
1115 pShwPage = pgmPoolGetPage(pPool, pPdpe->u & X86_PDPE_PG_MASK);
1116 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1117 }
1118 /* The PD was cached or created; hook it up now. */
1119 pPdpe->u |= pShwPage->Core.Key
1120 | (pGstPdpe->u & ~(X86_PDPE_PG_MASK | X86_PDPE_AVL_MASK | X86_PDPE_PCD | X86_PDPE_PWT));
1121
1122 *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1123 return VINF_SUCCESS;
1124}
1125
1126
1127/**
1128 * Gets the SHADOW page directory pointer for the specified address (long mode).
1129 *
1130 * @returns VBox status.
1131 * @param pVM VM handle.
1132 * @param GCPtr The address.
1133 * @param ppPdpt Receives address of pdpt
1134 * @param ppPD Receives address of page directory
1135 */
1136DECLINLINE(int) pgmShwGetLongModePDPtr(PVM pVM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPT *ppPdpt, PX86PDPAE *ppPD)
1137{
1138 PPGM pPGM = &pVM->pgm.s;
1139 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
1140 PCX86PML4E pPml4e = pgmShwGetLongModePML4EPtr(pPGM, iPml4);
1141 AssertReturn(pPml4e, VERR_INTERNAL_ERROR);
1142 if (ppPml4e)
1143 *ppPml4e = (PX86PML4E)pPml4e;
1144 if (!pPml4e->n.u1Present)
1145 return VERR_PAGE_MAP_LEVEL4_NOT_PRESENT;
1146
1147 PPGMPOOL pPool = pPGM->CTX_SUFF(pPool);
1148 PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPml4e->u & X86_PML4E_PG_MASK);
1149 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1150
1151 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1152 PCX86PDPT pPdpt = *ppPdpt = (PX86PDPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1153 if (!pPdpt->a[iPdPt].n.u1Present)
1154 return VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT;
1155
1156 pShwPage = pgmPoolGetPage(pPool, pPdpt->a[iPdPt].u & X86_PDPE_PG_MASK);
1157 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1158
1159 *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1160 return VINF_SUCCESS;
1161}
1162
1163
1164/**
1165 * Syncs the SHADOW EPT page directory pointer for the specified address. Allocates
1166 * backing pages in case the PDPT or PML4 entry is missing.
1167 *
1168 * @returns VBox status.
1169 * @param pVM VM handle.
1170 * @param GCPtr The address.
1171 * @param ppPdpt Receives address of pdpt
1172 * @param ppPD Receives address of page directory
1173 */
1174int pgmShwGetEPTPDPtr(PVM pVM, RTGCPTR64 GCPtr, PEPTPDPT *ppPdpt, PEPTPD *ppPD)
1175{
1176 PPGM pPGM = &pVM->pgm.s;
1177 const unsigned iPml4 = (GCPtr >> EPT_PML4_SHIFT) & EPT_PML4_MASK;
1178 PPGMPOOL pPool = pPGM->CTX_SUFF(pPool);
1179 PEPTPML4 pPml4;
1180 PEPTPML4E pPml4e;
1181 PPGMPOOLPAGE pShwPage;
1182 int rc;
1183
1184 Assert(HWACCMIsNestedPagingActive(pVM));
1185
1186 pPml4 = (PEPTPML4)PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
1187 Assert(pPml4);
1188
1189 /* Allocate page directory pointer table if not present. */
1190 pPml4e = &pPml4->a[iPml4];
1191 if ( !pPml4e->n.u1Present
1192 && !(pPml4e->u & EPT_PML4E_PG_MASK))
1193 {
1194 Assert(!(pPml4e->u & EPT_PML4E_PG_MASK));
1195 RTGCPTR64 GCPml4 = (RTGCPTR64)iPml4 << EPT_PML4_SHIFT;
1196
1197 rc = pgmPoolAlloc(pVM, GCPml4, PGMPOOLKIND_EPT_PDPT_FOR_PHYS, PGMPOOL_IDX_NESTED_ROOT, iPml4, &pShwPage);
1198 if (rc == VERR_PGM_POOL_FLUSHED)
1199 {
1200 Log(("PGMShwSyncEPTPDPtr: PGM pool flushed (1) -> signal sync cr3\n"));
1201 Assert(pVM->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL);
1202 VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
1203 return VINF_PGM_SYNC_CR3;
1204 }
1205 AssertRCReturn(rc, rc);
1206 }
1207 else
1208 {
1209 pShwPage = pgmPoolGetPage(pPool, pPml4e->u & EPT_PML4E_PG_MASK);
1210 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1211 }
1212 /* The PDPT was cached or created; hook it up now and fill with the default value. */
1213 pPml4e->u = pShwPage->Core.Key;
1214 pPml4e->n.u1Present = 1;
1215 pPml4e->n.u1Write = 1;
1216 pPml4e->n.u1Execute = 1;
1217
1218 const unsigned iPdPt = (GCPtr >> EPT_PDPT_SHIFT) & EPT_PDPT_MASK;
1219 PEPTPDPT pPdpt = (PEPTPDPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1220 PEPTPDPTE pPdpe = &pPdpt->a[iPdPt];
1221
1222 if (ppPdpt)
1223 *ppPdpt = pPdpt;
1224
1225 /* Allocate page directory if not present. */
1226 if ( !pPdpe->n.u1Present
1227 && !(pPdpe->u & EPT_PDPTE_PG_MASK))
1228 {
1229 RTGCPTR64 GCPdPt = (RTGCPTR64)iPdPt << EPT_PDPT_SHIFT;
1230
1231 rc = pgmPoolAlloc(pVM, GCPdPt, PGMPOOLKIND_64BIT_PD_FOR_PHYS, pShwPage->idx, iPdPt, &pShwPage);
1232 if (rc == VERR_PGM_POOL_FLUSHED)
1233 {
1234 Log(("PGMShwSyncEPTPDPtr: PGM pool flushed (2) -> signal sync cr3\n"));
1235 Assert(pVM->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL);
1236 VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
1237 return VINF_PGM_SYNC_CR3;
1238 }
1239 AssertRCReturn(rc, rc);
1240 }
1241 else
1242 {
1243 pShwPage = pgmPoolGetPage(pPool, pPdpe->u & EPT_PDPTE_PG_MASK);
1244 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1245 }
1246 /* The PD was cached or created; hook it up now and fill with the default value. */
1247 pPdpe->u = pShwPage->Core.Key;
1248 pPdpe->n.u1Present = 1;
1249 pPdpe->n.u1Write = 1;
1250 pPdpe->n.u1Execute = 1;
1251
1252 *ppPD = (PEPTPD)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1253 return VINF_SUCCESS;
1254}
1255
1256#endif /* IN_RC */
1257
1258/**
1259 * Gets effective Guest OS page information.
1260 *
1261 * When GCPtr is in a big page, the function will return as if it was a normal
1262 * 4KB page. If the need for distinguishing between big and normal page becomes
1263 * necessary at a later point, a PGMGstGetPage() will be created for that
1264 * purpose.
1265 *
1266 * @returns VBox status.
1267 * @param pVM VM Handle.
1268 * @param GCPtr Guest Context virtual address of the page.
1269 * @param pfFlags Where to store the flags. These are X86_PTE_*, even for big pages.
1270 * @param pGCPhys Where to store the GC physical address of the page.
1271 * This is page aligned. The fact that the
1272 */
1273VMMDECL(int) PGMGstGetPage(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys)
1274{
1275 return PGM_GST_PFN(GetPage,pVM)(pVM, GCPtr, pfFlags, pGCPhys);
1276}
1277
1278
1279/**
1280 * Checks if the page is present.
1281 *
1282 * @returns true if the page is present.
1283 * @returns false if the page is not present.
1284 * @param pVM The VM handle.
1285 * @param GCPtr Address within the page.
1286 */
1287VMMDECL(bool) PGMGstIsPagePresent(PVM pVM, RTGCPTR GCPtr)
1288{
1289 int rc = PGMGstGetPage(pVM, GCPtr, NULL, NULL);
1290 return RT_SUCCESS(rc);
1291}
1292
1293
1294/**
1295 * Sets (replaces) the page flags for a range of pages in the guest's tables.
1296 *
1297 * @returns VBox status.
1298 * @param pVM VM handle.
1299 * @param GCPtr The address of the first page.
1300 * @param cb The size of the range in bytes.
1301 * @param fFlags Page flags X86_PTE_*, excluding the page mask of course.
1302 */
1303VMMDECL(int) PGMGstSetPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags)
1304{
1305 return PGMGstModifyPage(pVM, GCPtr, cb, fFlags, 0);
1306}
1307
1308
1309/**
1310 * Modify page flags for a range of pages in the guest's tables
1311 *
1312 * The existing flags are ANDed with the fMask and ORed with the fFlags.
1313 *
1314 * @returns VBox status code.
1315 * @param pVM VM handle.
1316 * @param GCPtr Virtual address of the first page in the range.
1317 * @param cb Size (in bytes) of the range to apply the modification to.
1318 * @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
1319 * @param fMask The AND mask - page flags X86_PTE_*, excluding the page mask of course.
1320 * Be very CAREFUL when ~'ing constants which could be 32-bit!
1321 */
1322VMMDECL(int) PGMGstModifyPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
1323{
1324 STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,GstModifyPage), a);
1325
1326 /*
1327 * Validate input.
1328 */
1329 AssertMsg(!(fFlags & X86_PTE_PAE_PG_MASK), ("fFlags=%#llx\n", fFlags));
1330 Assert(cb);
1331
1332 LogFlow(("PGMGstModifyPage %RGv %d bytes fFlags=%08llx fMask=%08llx\n", GCPtr, cb, fFlags, fMask));
1333
1334 /*
1335 * Adjust input.
1336 */
1337 cb += GCPtr & PAGE_OFFSET_MASK;
1338 cb = RT_ALIGN_Z(cb, PAGE_SIZE);
1339 GCPtr = (GCPtr & PAGE_BASE_GC_MASK);
1340
1341 /*
1342 * Call worker.
1343 */
1344 int rc = PGM_GST_PFN(ModifyPage, pVM)(pVM, GCPtr, cb, fFlags, fMask);
1345
1346 STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,GstModifyPage), a);
1347 return rc;
1348}
1349
1350
1351/**
1352 * Gets the specified page directory pointer table entry.
1353 *
1354 * @returns PDP entry
1355 * @param pPGM Pointer to the PGM instance data.
1356 * @param iPdpt PDPT index
1357 */
1358VMMDECL(X86PDPE) PGMGstGetPaePDPtr(PVM pVM, unsigned iPdpt)
1359{
1360 Assert(iPdpt <= 3);
1361 return pgmGstGetPaePDPTPtr(&pVM->pgm.s)->a[iPdpt & 3];
1362}
1363
1364
1365/**
1366 * Gets the current CR3 register value for the shadow memory context.
1367 * @returns CR3 value.
1368 * @param pVM The VM handle.
1369 */
1370VMMDECL(RTHCPHYS) PGMGetHyperCR3(PVM pVM)
1371{
1372 Assert(pVM->pgm.s.CTX_SUFF(pShwPageCR3));
1373 return pVM->pgm.s.CTX_SUFF(pShwPageCR3)->Core.Key;
1374}
1375
1376
1377/**
1378 * Gets the current CR3 register value for the nested memory context.
1379 * @returns CR3 value.
1380 * @param pVM The VM handle.
1381 */
1382VMMDECL(RTHCPHYS) PGMGetNestedCR3(PVM pVM, PGMMODE enmShadowMode)
1383{
1384 Assert(pVM->pgm.s.CTX_SUFF(pShwPageCR3));
1385 return pVM->pgm.s.CTX_SUFF(pShwPageCR3)->Core.Key;
1386}
1387
1388
1389/**
1390 * Gets the CR3 register value for the 32-Bit shadow memory context.
1391 * @returns CR3 value.
1392 * @param pVM The VM handle.
1393 */
1394VMMDECL(RTHCPHYS) PGMGetHyper32BitCR3(PVM pVM)
1395{
1396 Assert(pVM->pgm.s.CTX_SUFF(pShwPageCR3));
1397 return pVM->pgm.s.CTX_SUFF(pShwPageCR3)->Core.Key;
1398}
1399
1400
1401/**
1402 * Gets the CR3 register value for the PAE shadow memory context.
1403 * @returns CR3 value.
1404 * @param pVM The VM handle.
1405 */
1406VMMDECL(RTHCPHYS) PGMGetHyperPaeCR3(PVM pVM)
1407{
1408 Assert(pVM->pgm.s.CTX_SUFF(pShwPageCR3));
1409 return pVM->pgm.s.CTX_SUFF(pShwPageCR3)->Core.Key;
1410}
1411
1412
1413/**
1414 * Gets the CR3 register value for the AMD64 shadow memory context.
1415 * @returns CR3 value.
1416 * @param pVM The VM handle.
1417 */
1418VMMDECL(RTHCPHYS) PGMGetHyperAmd64CR3(PVM pVM)
1419{
1420 Assert(pVM->pgm.s.CTX_SUFF(pShwPageCR3));
1421 return pVM->pgm.s.CTX_SUFF(pShwPageCR3)->Core.Key;
1422}
1423
1424
1425/**
1426 * Gets the current CR3 register value for the HC intermediate memory context.
1427 * @returns CR3 value.
1428 * @param pVM The VM handle.
1429 */
1430VMMDECL(RTHCPHYS) PGMGetInterHCCR3(PVM pVM)
1431{
1432 switch (pVM->pgm.s.enmHostMode)
1433 {
1434 case SUPPAGINGMODE_32_BIT:
1435 case SUPPAGINGMODE_32_BIT_GLOBAL:
1436 return pVM->pgm.s.HCPhysInterPD;
1437
1438 case SUPPAGINGMODE_PAE:
1439 case SUPPAGINGMODE_PAE_GLOBAL:
1440 case SUPPAGINGMODE_PAE_NX:
1441 case SUPPAGINGMODE_PAE_GLOBAL_NX:
1442 return pVM->pgm.s.HCPhysInterPaePDPT;
1443
1444 case SUPPAGINGMODE_AMD64:
1445 case SUPPAGINGMODE_AMD64_GLOBAL:
1446 case SUPPAGINGMODE_AMD64_NX:
1447 case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1448 return pVM->pgm.s.HCPhysInterPaePDPT;
1449
1450 default:
1451 AssertMsgFailed(("enmHostMode=%d\n", pVM->pgm.s.enmHostMode));
1452 return ~0;
1453 }
1454}
1455
1456
1457/**
1458 * Gets the current CR3 register value for the RC intermediate memory context.
1459 * @returns CR3 value.
1460 * @param pVM The VM handle.
1461 */
1462VMMDECL(RTHCPHYS) PGMGetInterRCCR3(PVM pVM)
1463{
1464 switch (pVM->pgm.s.enmShadowMode)
1465 {
1466 case PGMMODE_32_BIT:
1467 return pVM->pgm.s.HCPhysInterPD;
1468
1469 case PGMMODE_PAE:
1470 case PGMMODE_PAE_NX:
1471 return pVM->pgm.s.HCPhysInterPaePDPT;
1472
1473 case PGMMODE_AMD64:
1474 case PGMMODE_AMD64_NX:
1475 return pVM->pgm.s.HCPhysInterPaePML4;
1476
1477 case PGMMODE_EPT:
1478 case PGMMODE_NESTED:
1479 return 0; /* not relevant */
1480
1481 default:
1482 AssertMsgFailed(("enmShadowMode=%d\n", pVM->pgm.s.enmShadowMode));
1483 return ~0;
1484 }
1485}
1486
1487
1488/**
1489 * Gets the CR3 register value for the 32-Bit intermediate memory context.
1490 * @returns CR3 value.
1491 * @param pVM The VM handle.
1492 */
1493VMMDECL(RTHCPHYS) PGMGetInter32BitCR3(PVM pVM)
1494{
1495 return pVM->pgm.s.HCPhysInterPD;
1496}
1497
1498
1499/**
1500 * Gets the CR3 register value for the PAE intermediate memory context.
1501 * @returns CR3 value.
1502 * @param pVM The VM handle.
1503 */
1504VMMDECL(RTHCPHYS) PGMGetInterPaeCR3(PVM pVM)
1505{
1506 return pVM->pgm.s.HCPhysInterPaePDPT;
1507}
1508
1509
1510/**
1511 * Gets the CR3 register value for the AMD64 intermediate memory context.
1512 * @returns CR3 value.
1513 * @param pVM The VM handle.
1514 */
1515VMMDECL(RTHCPHYS) PGMGetInterAmd64CR3(PVM pVM)
1516{
1517 return pVM->pgm.s.HCPhysInterPaePML4;
1518}
1519
1520
1521/**
1522 * Performs and schedules necessary updates following a CR3 load or reload.
1523 *
1524 * This will normally involve mapping the guest PD or nPDPT
1525 *
1526 * @returns VBox status code.
1527 * @retval VINF_PGM_SYNC_CR3 if monitoring requires a CR3 sync. This can
1528 * safely be ignored and overridden since the FF will be set too then.
1529 * @param pVM VM handle.
1530 * @param cr3 The new cr3.
1531 * @param fGlobal Indicates whether this is a global flush or not.
1532 */
1533VMMDECL(int) PGMFlushTLB(PVM pVM, uint64_t cr3, bool fGlobal)
1534{
1535 STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,FlushTLB), a);
1536
1537 /*
1538 * Always flag the necessary updates; necessary for hardware acceleration
1539 */
1540 /** @todo optimize this, it shouldn't always be necessary. */
1541 VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
1542 if (fGlobal)
1543 VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
1544 LogFlow(("PGMFlushTLB: cr3=%RX64 OldCr3=%RX64 fGlobal=%d\n", cr3, pVM->pgm.s.GCPhysCR3, fGlobal));
1545
1546 /*
1547 * Remap the CR3 content and adjust the monitoring if CR3 was actually changed.
1548 */
1549 int rc = VINF_SUCCESS;
1550 RTGCPHYS GCPhysCR3;
1551 switch (pVM->pgm.s.enmGuestMode)
1552 {
1553 case PGMMODE_PAE:
1554 case PGMMODE_PAE_NX:
1555 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAE_PAGE_MASK);
1556 break;
1557 case PGMMODE_AMD64:
1558 case PGMMODE_AMD64_NX:
1559 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_AMD64_PAGE_MASK);
1560 break;
1561 default:
1562 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAGE_MASK);
1563 break;
1564 }
1565
1566 if (pVM->pgm.s.GCPhysCR3 != GCPhysCR3)
1567 {
1568 RTGCPHYS GCPhysOldCR3 = pVM->pgm.s.GCPhysCR3;
1569 pVM->pgm.s.GCPhysCR3 = GCPhysCR3;
1570 rc = PGM_BTH_PFN(MapCR3, pVM)(pVM, GCPhysCR3);
1571 if (RT_LIKELY(rc == VINF_SUCCESS))
1572 {
1573 if (!pVM->pgm.s.fMappingsFixed)
1574 {
1575 pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
1576 }
1577 }
1578 else
1579 {
1580 AssertMsg(rc == VINF_PGM_SYNC_CR3, ("%Rrc\n", rc));
1581 Assert(VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL | VM_FF_PGM_SYNC_CR3));
1582 pVM->pgm.s.GCPhysCR3 = GCPhysOldCR3;
1583 pVM->pgm.s.fSyncFlags |= PGM_SYNC_MAP_CR3;
1584 if (!pVM->pgm.s.fMappingsFixed)
1585 pVM->pgm.s.fSyncFlags |= PGM_SYNC_MONITOR_CR3;
1586 }
1587
1588 if (fGlobal)
1589 STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,FlushTLBNewCR3Global));
1590 else
1591 STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,FlushTLBNewCR3));
1592 }
1593 else
1594 {
1595 /*
1596 * Check if we have a pending update of the CR3 monitoring.
1597 */
1598 if (pVM->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
1599 {
1600 pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
1601 Assert(!pVM->pgm.s.fMappingsFixed);
1602 }
1603 if (fGlobal)
1604 STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,FlushTLBSameCR3Global));
1605 else
1606 STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,FlushTLBSameCR3));
1607 }
1608
1609 STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,FlushTLB), a);
1610 return rc;
1611}
1612
1613
1614/**
1615 * Performs and schedules necessary updates following a CR3 load or reload when
1616 * using nested or extended paging.
1617 *
1618 * This API is an alterantive to PDMFlushTLB that avoids actually flushing the
1619 * TLB and triggering a SyncCR3.
1620 *
1621 * This will normally involve mapping the guest PD or nPDPT
1622 *
1623 * @returns VBox status code.
1624 * @retval VINF_SUCCESS.
1625 * @retval (If applied when not in nested mode: VINF_PGM_SYNC_CR3 if monitoring
1626 * requires a CR3 sync. This can safely be ignored and overridden since
1627 * the FF will be set too then.)
1628 * @param pVM VM handle.
1629 * @param cr3 The new cr3.
1630 */
1631VMMDECL(int) PGMUpdateCR3(PVM pVM, uint64_t cr3)
1632{
1633 LogFlow(("PGMUpdateCR3: cr3=%RX64 OldCr3=%RX64\n", cr3, pVM->pgm.s.GCPhysCR3));
1634
1635 /* We assume we're only called in nested paging mode. */
1636 Assert(pVM->pgm.s.fMappingsFixed);
1637 Assert(!(pVM->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3));
1638 Assert(pVM->pgm.s.enmShadowMode == PGMMODE_NESTED || pVM->pgm.s.enmShadowMode == PGMMODE_EPT);
1639
1640 /*
1641 * Remap the CR3 content and adjust the monitoring if CR3 was actually changed.
1642 */
1643 int rc = VINF_SUCCESS;
1644 RTGCPHYS GCPhysCR3;
1645 switch (pVM->pgm.s.enmGuestMode)
1646 {
1647 case PGMMODE_PAE:
1648 case PGMMODE_PAE_NX:
1649 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAE_PAGE_MASK);
1650 break;
1651 case PGMMODE_AMD64:
1652 case PGMMODE_AMD64_NX:
1653 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_AMD64_PAGE_MASK);
1654 break;
1655 default:
1656 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAGE_MASK);
1657 break;
1658 }
1659 if (pVM->pgm.s.GCPhysCR3 != GCPhysCR3)
1660 {
1661 pVM->pgm.s.GCPhysCR3 = GCPhysCR3;
1662 rc = PGM_BTH_PFN(MapCR3, pVM)(pVM, GCPhysCR3);
1663 AssertRCSuccess(rc); /* Assumes VINF_PGM_SYNC_CR3 doesn't apply to nested paging. */ /** @todo this isn't true for the mac, but we need hw to test/fix this. */
1664 }
1665 return rc;
1666}
1667
1668
1669/**
1670 * Synchronize the paging structures.
1671 *
1672 * This function is called in response to the VM_FF_PGM_SYNC_CR3 and
1673 * VM_FF_PGM_SYNC_CR3_NONGLOBAL. Those two force action flags are set
1674 * in several places, most importantly whenever the CR3 is loaded.
1675 *
1676 * @returns VBox status code.
1677 * @param pVM The virtual machine.
1678 * @param cr0 Guest context CR0 register
1679 * @param cr3 Guest context CR3 register
1680 * @param cr4 Guest context CR4 register
1681 * @param fGlobal Including global page directories or not
1682 */
1683VMMDECL(int) PGMSyncCR3(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
1684{
1685 int rc;
1686
1687 /*
1688 * We might be called when we shouldn't.
1689 *
1690 * The mode switching will ensure that the PD is resynced
1691 * after every mode switch. So, if we find ourselves here
1692 * when in protected or real mode we can safely disable the
1693 * FF and return immediately.
1694 */
1695 if (pVM->pgm.s.enmGuestMode <= PGMMODE_PROTECTED)
1696 {
1697 Assert((cr0 & (X86_CR0_PG | X86_CR0_PE)) != (X86_CR0_PG | X86_CR0_PE));
1698 VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3);
1699 VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
1700 return VINF_SUCCESS;
1701 }
1702
1703 /* If global pages are not supported, then all flushes are global. */
1704 if (!(cr4 & X86_CR4_PGE))
1705 fGlobal = true;
1706 LogFlow(("PGMSyncCR3: cr0=%RX64 cr3=%RX64 cr4=%RX64 fGlobal=%d[%d,%d]\n", cr0, cr3, cr4, fGlobal,
1707 VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3), VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL)));
1708
1709#ifdef PGMPOOL_WITH_MONITORING
1710 /*
1711 * The pool may have pending stuff and even require a return to ring-3 to
1712 * clear the whole thing.
1713 */
1714 rc = pgmPoolSyncCR3(pVM);
1715 if (rc != VINF_SUCCESS)
1716 return rc;
1717#endif
1718
1719 /*
1720 * Check if we need to finish an aborted MapCR3 call (see PGMFlushTLB).
1721 * This should be done before SyncCR3.
1722 */
1723 if (pVM->pgm.s.fSyncFlags & PGM_SYNC_MAP_CR3)
1724 {
1725 pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_MAP_CR3;
1726
1727 RTGCPHYS GCPhysCR3Old = pVM->pgm.s.GCPhysCR3;
1728 RTGCPHYS GCPhysCR3;
1729 switch (pVM->pgm.s.enmGuestMode)
1730 {
1731 case PGMMODE_PAE:
1732 case PGMMODE_PAE_NX:
1733 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAE_PAGE_MASK);
1734 break;
1735 case PGMMODE_AMD64:
1736 case PGMMODE_AMD64_NX:
1737 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_AMD64_PAGE_MASK);
1738 break;
1739 default:
1740 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAGE_MASK);
1741 break;
1742 }
1743
1744 if (pVM->pgm.s.GCPhysCR3 != GCPhysCR3)
1745 {
1746 pVM->pgm.s.GCPhysCR3 = GCPhysCR3;
1747 rc = PGM_BTH_PFN(MapCR3, pVM)(pVM, GCPhysCR3);
1748 }
1749#ifdef IN_RING3
1750 if (rc == VINF_PGM_SYNC_CR3)
1751 rc = pgmPoolSyncCR3(pVM);
1752#else
1753 if (rc == VINF_PGM_SYNC_CR3)
1754 {
1755 pVM->pgm.s.GCPhysCR3 = GCPhysCR3Old;
1756 return rc;
1757 }
1758#endif
1759 AssertRCReturn(rc, rc);
1760 AssertRCSuccessReturn(rc, VERR_INTERNAL_ERROR);
1761 }
1762
1763 /*
1764 * Let the 'Bth' function do the work and we'll just keep track of the flags.
1765 */
1766 STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3), a);
1767 rc = PGM_BTH_PFN(SyncCR3, pVM)(pVM, cr0, cr3, cr4, fGlobal);
1768 STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3), a);
1769 AssertMsg(rc == VINF_SUCCESS || rc == VINF_PGM_SYNC_CR3 || RT_FAILURE(rc), ("rc=%Rrc\n", rc));
1770 if (rc == VINF_SUCCESS)
1771 {
1772 if (!(pVM->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS))
1773 {
1774 VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3);
1775 VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
1776 }
1777
1778 /*
1779 * Check if we have a pending update of the CR3 monitoring.
1780 */
1781 if (pVM->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
1782 {
1783 pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
1784 Assert(!pVM->pgm.s.fMappingsFixed);
1785 }
1786 }
1787
1788 /*
1789 * Now flush the CR3 (guest context).
1790 */
1791 if (rc == VINF_SUCCESS)
1792 PGM_INVL_GUEST_TLBS();
1793 return rc;
1794}
1795
1796
1797/**
1798 * Called whenever CR0 or CR4 in a way which may change
1799 * the paging mode.
1800 *
1801 * @returns VBox status code fit for scheduling in GC and R0.
1802 * @retval VINF_SUCCESS if the was no change, or it was successfully dealt with.
1803 * @retval VINF_PGM_CHANGE_MODE if we're in GC or R0 and the mode changes.
1804 * @param pVM VM handle.
1805 * @param cr0 The new cr0.
1806 * @param cr4 The new cr4.
1807 * @param efer The new extended feature enable register.
1808 */
1809VMMDECL(int) PGMChangeMode(PVM pVM, uint64_t cr0, uint64_t cr4, uint64_t efer)
1810{
1811 PGMMODE enmGuestMode;
1812
1813 /*
1814 * Calc the new guest mode.
1815 */
1816 if (!(cr0 & X86_CR0_PE))
1817 enmGuestMode = PGMMODE_REAL;
1818 else if (!(cr0 & X86_CR0_PG))
1819 enmGuestMode = PGMMODE_PROTECTED;
1820 else if (!(cr4 & X86_CR4_PAE))
1821 enmGuestMode = PGMMODE_32_BIT;
1822 else if (!(efer & MSR_K6_EFER_LME))
1823 {
1824 if (!(efer & MSR_K6_EFER_NXE))
1825 enmGuestMode = PGMMODE_PAE;
1826 else
1827 enmGuestMode = PGMMODE_PAE_NX;
1828 }
1829 else
1830 {
1831 if (!(efer & MSR_K6_EFER_NXE))
1832 enmGuestMode = PGMMODE_AMD64;
1833 else
1834 enmGuestMode = PGMMODE_AMD64_NX;
1835 }
1836
1837 /*
1838 * Did it change?
1839 */
1840 if (pVM->pgm.s.enmGuestMode == enmGuestMode)
1841 return VINF_SUCCESS;
1842
1843 /* Flush the TLB */
1844 PGM_INVL_GUEST_TLBS();
1845
1846#ifdef IN_RING3
1847 return PGMR3ChangeMode(pVM, enmGuestMode);
1848#else
1849 LogFlow(("PGMChangeMode: returns VINF_PGM_CHANGE_MODE.\n"));
1850 return VINF_PGM_CHANGE_MODE;
1851#endif
1852}
1853
1854
1855/**
1856 * Gets the current guest paging mode.
1857 *
1858 * If you just need the CPU mode (real/protected/long), use CPUMGetGuestMode().
1859 *
1860 * @returns The current paging mode.
1861 * @param pVM The VM handle.
1862 */
1863VMMDECL(PGMMODE) PGMGetGuestMode(PVM pVM)
1864{
1865 return pVM->pgm.s.enmGuestMode;
1866}
1867
1868
1869/**
1870 * Gets the current shadow paging mode.
1871 *
1872 * @returns The current paging mode.
1873 * @param pVM The VM handle.
1874 */
1875VMMDECL(PGMMODE) PGMGetShadowMode(PVM pVM)
1876{
1877 return pVM->pgm.s.enmShadowMode;
1878}
1879
1880/**
1881 * Gets the current host paging mode.
1882 *
1883 * @returns The current paging mode.
1884 * @param pVM The VM handle.
1885 */
1886VMMDECL(PGMMODE) PGMGetHostMode(PVM pVM)
1887{
1888 switch (pVM->pgm.s.enmHostMode)
1889 {
1890 case SUPPAGINGMODE_32_BIT:
1891 case SUPPAGINGMODE_32_BIT_GLOBAL:
1892 return PGMMODE_32_BIT;
1893
1894 case SUPPAGINGMODE_PAE:
1895 case SUPPAGINGMODE_PAE_GLOBAL:
1896 return PGMMODE_PAE;
1897
1898 case SUPPAGINGMODE_PAE_NX:
1899 case SUPPAGINGMODE_PAE_GLOBAL_NX:
1900 return PGMMODE_PAE_NX;
1901
1902 case SUPPAGINGMODE_AMD64:
1903 case SUPPAGINGMODE_AMD64_GLOBAL:
1904 return PGMMODE_AMD64;
1905
1906 case SUPPAGINGMODE_AMD64_NX:
1907 case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1908 return PGMMODE_AMD64_NX;
1909
1910 default: AssertMsgFailed(("enmHostMode=%d\n", pVM->pgm.s.enmHostMode)); break;
1911 }
1912
1913 return PGMMODE_INVALID;
1914}
1915
1916
1917/**
1918 * Get mode name.
1919 *
1920 * @returns read-only name string.
1921 * @param enmMode The mode which name is desired.
1922 */
1923VMMDECL(const char *) PGMGetModeName(PGMMODE enmMode)
1924{
1925 switch (enmMode)
1926 {
1927 case PGMMODE_REAL: return "Real";
1928 case PGMMODE_PROTECTED: return "Protected";
1929 case PGMMODE_32_BIT: return "32-bit";
1930 case PGMMODE_PAE: return "PAE";
1931 case PGMMODE_PAE_NX: return "PAE+NX";
1932 case PGMMODE_AMD64: return "AMD64";
1933 case PGMMODE_AMD64_NX: return "AMD64+NX";
1934 case PGMMODE_NESTED: return "Nested";
1935 case PGMMODE_EPT: return "EPT";
1936 default: return "unknown mode value";
1937 }
1938}
1939
1940
1941/**
1942 * Acquire the PGM lock.
1943 *
1944 * @returns VBox status code
1945 * @param pVM The VM to operate on.
1946 */
1947int pgmLock(PVM pVM)
1948{
1949 int rc = PDMCritSectEnter(&pVM->pgm.s.CritSect, VERR_SEM_BUSY);
1950#ifdef IN_RC
1951 if (rc == VERR_SEM_BUSY)
1952 rc = VMMGCCallHost(pVM, VMMCALLHOST_PGM_LOCK, 0);
1953#elif defined(IN_RING0)
1954 if (rc == VERR_SEM_BUSY)
1955 rc = VMMR0CallHost(pVM, VMMCALLHOST_PGM_LOCK, 0);
1956#endif
1957 AssertMsg(rc == VINF_SUCCESS, ("%Rrc\n", rc));
1958 return rc;
1959}
1960
1961
1962/**
1963 * Release the PGM lock.
1964 *
1965 * @returns VBox status code
1966 * @param pVM The VM to operate on.
1967 */
1968void pgmUnlock(PVM pVM)
1969{
1970 PDMCritSectLeave(&pVM->pgm.s.CritSect);
1971}
1972
1973#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1974
1975/**
1976 * Temporarily maps one guest page specified by GC physical address.
1977 * These pages must have a physical mapping in HC, i.e. they cannot be MMIO pages.
1978 *
1979 * Be WARNED that the dynamic page mapping area is small, 8 pages, thus the space is
1980 * reused after 8 mappings (or perhaps a few more if you score with the cache).
1981 *
1982 * @returns VBox status.
1983 * @param pVM VM handle.
1984 * @param GCPhys GC Physical address of the page.
1985 * @param ppv Where to store the address of the mapping.
1986 */
1987VMMDECL(int) PGMDynMapGCPage(PVM pVM, RTGCPHYS GCPhys, void **ppv)
1988{
1989 AssertMsg(!(GCPhys & PAGE_OFFSET_MASK), ("GCPhys=%RGp\n", GCPhys));
1990
1991 /*
1992 * Get the ram range.
1993 */
1994 PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
1995 while (pRam && GCPhys - pRam->GCPhys >= pRam->cb)
1996 pRam = pRam->CTX_SUFF(pNext);
1997 if (!pRam)
1998 {
1999 AssertMsgFailed(("Invalid physical address %RGp!\n", GCPhys));
2000 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2001 }
2002
2003 /*
2004 * Pass it on to PGMDynMapHCPage.
2005 */
2006 RTHCPHYS HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT]);
2007 //Log(("PGMDynMapGCPage: GCPhys=%RGp HCPhys=%RHp\n", GCPhys, HCPhys));
2008#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2009 pgmR0DynMapHCPageInlined(&pVM->pgm.s, HCPhys, ppv);
2010#else
2011 PGMDynMapHCPage(pVM, HCPhys, ppv);
2012#endif
2013 return VINF_SUCCESS;
2014}
2015
2016
2017/**
2018 * Temporarily maps one guest page specified by unaligned GC physical address.
2019 * These pages must have a physical mapping in HC, i.e. they cannot be MMIO pages.
2020 *
2021 * Be WARNED that the dynamic page mapping area is small, 8 pages, thus the space is
2022 * reused after 8 mappings (or perhaps a few more if you score with the cache).
2023 *
2024 * The caller is aware that only the speicifed page is mapped and that really bad things
2025 * will happen if writing beyond the page!
2026 *
2027 * @returns VBox status.
2028 * @param pVM VM handle.
2029 * @param GCPhys GC Physical address within the page to be mapped.
2030 * @param ppv Where to store the address of the mapping address corresponding to GCPhys.
2031 */
2032VMMDECL(int) PGMDynMapGCPageOff(PVM pVM, RTGCPHYS GCPhys, void **ppv)
2033{
2034 /*
2035 * Get the ram range.
2036 */
2037 PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
2038 while (pRam && GCPhys - pRam->GCPhys >= pRam->cb)
2039 pRam = pRam->CTX_SUFF(pNext);
2040 if (!pRam)
2041 {
2042 AssertMsgFailed(("Invalid physical address %RGp!\n", GCPhys));
2043 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2044 }
2045
2046 /*
2047 * Pass it on to PGMDynMapHCPage.
2048 */
2049 RTHCPHYS HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT]);
2050#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2051 pgmR0DynMapHCPageInlined(&pVM->pgm.s, HCPhys, ppv);
2052#else
2053 PGMDynMapHCPage(pVM, HCPhys, ppv);
2054#endif
2055 *ppv = (void *)((uintptr_t)*ppv | (GCPhys & PAGE_OFFSET_MASK));
2056 return VINF_SUCCESS;
2057}
2058
2059# ifdef IN_RC
2060
2061/**
2062 * Temporarily maps one host page specified by HC physical address.
2063 *
2064 * Be WARNED that the dynamic page mapping area is small, 16 pages, thus the space is
2065 * reused after 16 mappings (or perhaps a few more if you score with the cache).
2066 *
2067 * @returns VINF_SUCCESS, will bail out to ring-3 on failure.
2068 * @param pVM VM handle.
2069 * @param HCPhys HC Physical address of the page.
2070 * @param ppv Where to store the address of the mapping. This is the
2071 * address of the PAGE not the exact address corresponding
2072 * to HCPhys. Use PGMDynMapHCPageOff if you care for the
2073 * page offset.
2074 */
2075VMMDECL(int) PGMDynMapHCPage(PVM pVM, RTHCPHYS HCPhys, void **ppv)
2076{
2077 AssertMsg(!(HCPhys & PAGE_OFFSET_MASK), ("HCPhys=%RHp\n", HCPhys));
2078
2079 /*
2080 * Check the cache.
2081 */
2082 register unsigned iCache;
2083 for (iCache = 0;iCache < RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache);iCache++)
2084 {
2085 static const uint8_t au8Trans[MM_HYPER_DYNAMIC_SIZE >> PAGE_SHIFT][RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache)] =
2086 {
2087 { 0, 9, 10, 11, 12, 13, 14, 15},
2088 { 0, 1, 10, 11, 12, 13, 14, 15},
2089 { 0, 1, 2, 11, 12, 13, 14, 15},
2090 { 0, 1, 2, 3, 12, 13, 14, 15},
2091 { 0, 1, 2, 3, 4, 13, 14, 15},
2092 { 0, 1, 2, 3, 4, 5, 14, 15},
2093 { 0, 1, 2, 3, 4, 5, 6, 15},
2094 { 0, 1, 2, 3, 4, 5, 6, 7},
2095 { 8, 1, 2, 3, 4, 5, 6, 7},
2096 { 8, 9, 2, 3, 4, 5, 6, 7},
2097 { 8, 9, 10, 3, 4, 5, 6, 7},
2098 { 8, 9, 10, 11, 4, 5, 6, 7},
2099 { 8, 9, 10, 11, 12, 5, 6, 7},
2100 { 8, 9, 10, 11, 12, 13, 6, 7},
2101 { 8, 9, 10, 11, 12, 13, 14, 7},
2102 { 8, 9, 10, 11, 12, 13, 14, 15},
2103 };
2104 AssertCompile(RT_ELEMENTS(au8Trans) == 16);
2105 AssertCompile(RT_ELEMENTS(au8Trans[0]) == 8);
2106
2107 if (pVM->pgm.s.aHCPhysDynPageMapCache[iCache] == HCPhys)
2108 {
2109 int iPage = au8Trans[pVM->pgm.s.iDynPageMapLast][iCache];
2110
2111 /* The cache can get out of sync with locked entries. (10 locked, 2 overwrites its cache position, last = 11, lookup 2 -> page 10 instead of 2) */
2112 if ((pVM->pgm.s.paDynPageMap32BitPTEsGC[iPage].u & X86_PTE_PG_MASK) == HCPhys)
2113 {
2114 void *pv = pVM->pgm.s.pbDynPageMapBaseGC + (iPage << PAGE_SHIFT);
2115 *ppv = pv;
2116 STAM_COUNTER_INC(&pVM->pgm.s.StatRCDynMapCacheHits);
2117 Log4(("PGMGCDynMapHCPage: HCPhys=%RHp pv=%p iPage=%d iCache=%d\n", HCPhys, pv, iPage, iCache));
2118 return VINF_SUCCESS;
2119 }
2120 else
2121 LogFlow(("Out of sync entry %d\n", iPage));
2122 }
2123 }
2124 AssertCompile(RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache) == 8);
2125 AssertCompile((MM_HYPER_DYNAMIC_SIZE >> PAGE_SHIFT) == 16);
2126 STAM_COUNTER_INC(&pVM->pgm.s.StatRCDynMapCacheMisses);
2127
2128 /*
2129 * Update the page tables.
2130 */
2131 register unsigned iPage = pVM->pgm.s.iDynPageMapLast;
2132 unsigned i;
2133 for (i=0;i<(MM_HYPER_DYNAMIC_SIZE >> PAGE_SHIFT);i++)
2134 {
2135 pVM->pgm.s.iDynPageMapLast = iPage = (iPage + 1) & ((MM_HYPER_DYNAMIC_SIZE >> PAGE_SHIFT) - 1);
2136 if (!pVM->pgm.s.aLockedDynPageMapCache[iPage])
2137 break;
2138 iPage++;
2139 }
2140 AssertRelease(i != (MM_HYPER_DYNAMIC_SIZE >> PAGE_SHIFT));
2141
2142 pVM->pgm.s.aHCPhysDynPageMapCache[iPage & (RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache) - 1)] = HCPhys;
2143 pVM->pgm.s.paDynPageMap32BitPTEsGC[iPage].u = (uint32_t)HCPhys | X86_PTE_P | X86_PTE_A | X86_PTE_D;
2144 pVM->pgm.s.paDynPageMapPaePTEsGC[iPage].u = HCPhys | X86_PTE_P | X86_PTE_A | X86_PTE_D;
2145 pVM->pgm.s.aLockedDynPageMapCache[iPage] = 0;
2146
2147 void *pv = pVM->pgm.s.pbDynPageMapBaseGC + (iPage << PAGE_SHIFT);
2148 *ppv = pv;
2149 ASMInvalidatePage(pv);
2150 Log4(("PGMGCDynMapHCPage: HCPhys=%RHp pv=%p iPage=%d\n", HCPhys, pv, iPage));
2151 return VINF_SUCCESS;
2152}
2153
2154
2155/**
2156 * Temporarily lock a dynamic page to prevent it from being reused.
2157 *
2158 * @param pVM VM handle.
2159 * @param GCPage GC address of page
2160 */
2161VMMDECL(void) PGMDynLockHCPage(PVM pVM, RCPTRTYPE(uint8_t *) GCPage)
2162{
2163 unsigned iPage;
2164
2165 Assert(GCPage >= pVM->pgm.s.pbDynPageMapBaseGC && GCPage < (pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE));
2166 iPage = ((uintptr_t)(GCPage - pVM->pgm.s.pbDynPageMapBaseGC)) >> PAGE_SHIFT;
2167 ASMAtomicIncU32(&pVM->pgm.s.aLockedDynPageMapCache[iPage]);
2168 Log4(("PGMDynLockHCPage %RRv iPage=%d\n", GCPage, iPage));
2169}
2170
2171
2172/**
2173 * Unlock a dynamic page
2174 *
2175 * @param pVM VM handle.
2176 * @param GCPage GC address of page
2177 */
2178VMMDECL(void) PGMDynUnlockHCPage(PVM pVM, RCPTRTYPE(uint8_t *) GCPage)
2179{
2180 unsigned iPage;
2181
2182 AssertCompile(RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache) == RT_ELEMENTS(pVM->pgm.s.aLockedDynPageMapCache));
2183
2184 Assert(GCPage >= pVM->pgm.s.pbDynPageMapBaseGC && GCPage < (pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE));
2185 iPage = ((uintptr_t)(GCPage - pVM->pgm.s.pbDynPageMapBaseGC)) >> PAGE_SHIFT;
2186 Assert(pVM->pgm.s.aLockedDynPageMapCache[iPage]);
2187 ASMAtomicDecU32(&pVM->pgm.s.aLockedDynPageMapCache[iPage]);
2188 Log4(("PGMDynUnlockHCPage %RRv iPage=%d\n", GCPage, iPage));
2189}
2190
2191
2192# ifdef VBOX_STRICT
2193/**
2194 * Check for lock leaks.
2195 *
2196 * @param pVM VM handle.
2197 */
2198VMMDECL(void) PGMDynCheckLocks(PVM pVM)
2199{
2200 for (unsigned i=0;i<RT_ELEMENTS(pVM->pgm.s.aLockedDynPageMapCache);i++)
2201 Assert(!pVM->pgm.s.aLockedDynPageMapCache[i]);
2202}
2203# endif /* VBOX_STRICT */
2204
2205# endif /* IN_RC */
2206#endif /* IN_RC || VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
2207
2208#if !defined(IN_R0) || defined(LOG_ENABLED)
2209
2210/** Format handler for PGMPAGE.
2211 * @copydoc FNRTSTRFORMATTYPE */
2212static DECLCALLBACK(size_t) pgmFormatTypeHandlerPage(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
2213 const char *pszType, void const *pvValue,
2214 int cchWidth, int cchPrecision, unsigned fFlags,
2215 void *pvUser)
2216{
2217 size_t cch;
2218 PCPGMPAGE pPage = (PCPGMPAGE)pvValue;
2219 if (VALID_PTR(pPage))
2220 {
2221 char szTmp[64+80];
2222
2223 cch = 0;
2224
2225 /* The single char state stuff. */
2226 static const char s_achPageStates[4] = { 'Z', 'A', 'W', 'S' };
2227 szTmp[cch++] = s_achPageStates[PGM_PAGE_GET_STATE(pPage)];
2228
2229#define IS_PART_INCLUDED(lvl) ( !(fFlags & RTSTR_F_PRECISION) || cchPrecision == (lvl) || cchPrecision >= (lvl)+10 )
2230 if (IS_PART_INCLUDED(5))
2231 {
2232 static const char s_achHandlerStates[4] = { '-', 't', 'w', 'a' };
2233 szTmp[cch++] = s_achHandlerStates[PGM_PAGE_GET_HNDL_PHYS_STATE(pPage)];
2234 szTmp[cch++] = s_achHandlerStates[PGM_PAGE_GET_HNDL_VIRT_STATE(pPage)];
2235 }
2236
2237 /* The type. */
2238 if (IS_PART_INCLUDED(4))
2239 {
2240 szTmp[cch++] = ':';
2241 static const char s_achPageTypes[8][4] = { "INV", "RAM", "MI2", "M2A", "SHA", "ROM", "MIO", "BAD" };
2242 szTmp[cch++] = s_achPageTypes[PGM_PAGE_GET_TYPE(pPage)][0];
2243 szTmp[cch++] = s_achPageTypes[PGM_PAGE_GET_TYPE(pPage)][1];
2244 szTmp[cch++] = s_achPageTypes[PGM_PAGE_GET_TYPE(pPage)][2];
2245 }
2246
2247 /* The numbers. */
2248 if (IS_PART_INCLUDED(3))
2249 {
2250 szTmp[cch++] = ':';
2251 cch += RTStrFormatNumber(&szTmp[cch], PGM_PAGE_GET_HCPHYS(pPage), 16, 12, 0, RTSTR_F_ZEROPAD | RTSTR_F_64BIT);
2252 }
2253
2254 if (IS_PART_INCLUDED(2))
2255 {
2256 szTmp[cch++] = ':';
2257 cch += RTStrFormatNumber(&szTmp[cch], PGM_PAGE_GET_PAGEID(pPage), 16, 7, 0, RTSTR_F_ZEROPAD | RTSTR_F_32BIT);
2258 }
2259
2260 if (IS_PART_INCLUDED(6))
2261 {
2262 szTmp[cch++] = ':';
2263 static const char s_achRefs[4] = { '-', 'U', '!', 'L' };
2264 szTmp[cch++] = s_achRefs[PGM_PAGE_GET_TD_CREFS(pPage)];
2265 cch += RTStrFormatNumber(&szTmp[cch], PGM_PAGE_GET_TD_IDX(pPage), 16, 4, 0, RTSTR_F_ZEROPAD | RTSTR_F_16BIT);
2266 }
2267#undef IS_PART_INCLUDED
2268
2269 cch = pfnOutput(pvArgOutput, szTmp, cch);
2270 }
2271 else
2272 cch = pfnOutput(pvArgOutput, "<bad-pgmpage-ptr>", sizeof("<bad-pgmpage-ptr>") - 1);
2273 return cch;
2274}
2275
2276
2277/** Format handler for PGMRAMRANGE.
2278 * @copydoc FNRTSTRFORMATTYPE */
2279static DECLCALLBACK(size_t) pgmFormatTypeHandlerRamRange(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
2280 const char *pszType, void const *pvValue,
2281 int cchWidth, int cchPrecision, unsigned fFlags,
2282 void *pvUser)
2283{
2284 size_t cch;
2285 PGMRAMRANGE const *pRam = (PGMRAMRANGE const *)pvValue;
2286 if (VALID_PTR(pRam))
2287 {
2288 char szTmp[80];
2289 cch = RTStrPrintf(szTmp, sizeof(szTmp), "%RGp-%RGp", pRam->GCPhys, pRam->GCPhysLast);
2290 cch = pfnOutput(pvArgOutput, szTmp, cch);
2291 }
2292 else
2293 cch = pfnOutput(pvArgOutput, "<bad-pgmramrange-ptr>", sizeof("<bad-pgmramrange-ptr>") - 1);
2294 return cch;
2295}
2296
2297/** Format type andlers to be registered/deregistered. */
2298static const struct
2299{
2300 char szType[24];
2301 PFNRTSTRFORMATTYPE pfnHandler;
2302} g_aPgmFormatTypes[] =
2303{
2304 { "pgmpage", pgmFormatTypeHandlerPage },
2305 { "pgmramrange", pgmFormatTypeHandlerRamRange }
2306};
2307
2308#endif /* !IN_R0 || LOG_ENABLED */
2309
2310
2311/**
2312 * Registers the global string format types.
2313 *
2314 * This should be called at module load time or in some other manner that ensure
2315 * that it's called exactly one time.
2316 *
2317 * @returns IPRT status code on RTStrFormatTypeRegister failure.
2318 */
2319VMMDECL(int) PGMRegisterStringFormatTypes(void)
2320{
2321#if !defined(IN_R0) || defined(LOG_ENABLED)
2322 int rc = VINF_SUCCESS;
2323 unsigned i;
2324 for (i = 0; RT_SUCCESS(rc) && i < RT_ELEMENTS(g_aPgmFormatTypes); i++)
2325 {
2326 rc = RTStrFormatTypeRegister(g_aPgmFormatTypes[i].szType, g_aPgmFormatTypes[i].pfnHandler, NULL);
2327# ifdef IN_RING0
2328 if (rc == VERR_ALREADY_EXISTS)
2329 {
2330 /* in case of cleanup failure in ring-0 */
2331 RTStrFormatTypeDeregister(g_aPgmFormatTypes[i].szType);
2332 rc = RTStrFormatTypeRegister(g_aPgmFormatTypes[i].szType, g_aPgmFormatTypes[i].pfnHandler, NULL);
2333 }
2334# endif
2335 }
2336 if (RT_FAILURE(rc))
2337 while (i-- > 0)
2338 RTStrFormatTypeDeregister(g_aPgmFormatTypes[i].szType);
2339
2340 return rc;
2341#else
2342 return VINF_SUCCESS;
2343#endif
2344}
2345
2346
2347/**
2348 * Deregisters the global string format types.
2349 *
2350 * This should be called at module unload time or in some other manner that
2351 * ensure that it's called exactly one time.
2352 */
2353VMMDECL(void) PGMDeregisterStringFormatTypes(void)
2354{
2355#if !defined(IN_R0) || defined(LOG_ENABLED)
2356 for (unsigned i = 0; i < RT_ELEMENTS(g_aPgmFormatTypes); i++)
2357 RTStrFormatTypeDeregister(g_aPgmFormatTypes[i].szType);
2358#endif
2359}
2360
2361#ifdef VBOX_STRICT
2362
2363/**
2364 * Asserts that there are no mapping conflicts.
2365 *
2366 * @returns Number of conflicts.
2367 * @param pVM The VM Handle.
2368 */
2369VMMDECL(unsigned) PGMAssertNoMappingConflicts(PVM pVM)
2370{
2371 unsigned cErrors = 0;
2372
2373 /*
2374 * Check for mapping conflicts.
2375 */
2376 for (PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
2377 pMapping;
2378 pMapping = pMapping->CTX_SUFF(pNext))
2379 {
2380 /** @todo This is slow and should be optimized, but since it's just assertions I don't care now. */
2381 for (RTGCPTR GCPtr = pMapping->GCPtr;
2382 GCPtr <= pMapping->GCPtrLast;
2383 GCPtr += PAGE_SIZE)
2384 {
2385 int rc = PGMGstGetPage(pVM, (RTGCPTR)GCPtr, NULL, NULL);
2386 if (rc != VERR_PAGE_TABLE_NOT_PRESENT)
2387 {
2388 AssertMsgFailed(("Conflict at %RGv with %s\n", GCPtr, R3STRING(pMapping->pszDesc)));
2389 cErrors++;
2390 break;
2391 }
2392 }
2393 }
2394
2395 return cErrors;
2396}
2397
2398
2399/**
2400 * Asserts that everything related to the guest CR3 is correctly shadowed.
2401 *
2402 * This will call PGMAssertNoMappingConflicts() and PGMAssertHandlerAndFlagsInSync(),
2403 * and assert the correctness of the guest CR3 mapping before asserting that the
2404 * shadow page tables is in sync with the guest page tables.
2405 *
2406 * @returns Number of conflicts.
2407 * @param pVM The VM Handle.
2408 * @param cr3 The current guest CR3 register value.
2409 * @param cr4 The current guest CR4 register value.
2410 */
2411VMMDECL(unsigned) PGMAssertCR3(PVM pVM, uint64_t cr3, uint64_t cr4)
2412{
2413 STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3), a);
2414 unsigned cErrors = PGM_BTH_PFN(AssertCR3, pVM)(pVM, cr3, cr4, 0, ~(RTGCPTR)0);
2415 STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3), a);
2416 return cErrors;
2417}
2418
2419#endif /* VBOX_STRICT */
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