VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAll.cpp@ 18976

Last change on this file since 18976 was 18958, checked in by vboxsync, 16 years ago

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1/* $Id: PGMAll.cpp 18958 2009-04-16 17:06:00Z vboxsync $ */
2/** @file
3 * PGM - Page Manager and Monitor - All context code.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22/*******************************************************************************
23* Header Files *
24*******************************************************************************/
25#define LOG_GROUP LOG_GROUP_PGM
26#include <VBox/pgm.h>
27#include <VBox/cpum.h>
28#include <VBox/selm.h>
29#include <VBox/iom.h>
30#include <VBox/sup.h>
31#include <VBox/mm.h>
32#include <VBox/stam.h>
33#include <VBox/csam.h>
34#include <VBox/patm.h>
35#include <VBox/trpm.h>
36#include <VBox/rem.h>
37#include <VBox/em.h>
38#include <VBox/hwaccm.h>
39#include <VBox/hwacc_vmx.h>
40#include "PGMInternal.h"
41#include <VBox/vm.h>
42#include <iprt/assert.h>
43#include <iprt/asm.h>
44#include <iprt/string.h>
45#include <VBox/log.h>
46#include <VBox/param.h>
47#include <VBox/err.h>
48
49
50/*******************************************************************************
51* Structures and Typedefs *
52*******************************************************************************/
53/**
54 * Stated structure for PGM_GST_NAME(HandlerVirtualUpdate) that's
55 * passed to PGM_GST_NAME(VirtHandlerUpdateOne) during enumeration.
56 */
57typedef struct PGMHVUSTATE
58{
59 /** The VM handle. */
60 PVM pVM;
61 /** The VMCPU handle. */
62 PVMCPU pVCpu;
63 /** The todo flags. */
64 RTUINT fTodo;
65 /** The CR4 register value. */
66 uint32_t cr4;
67} PGMHVUSTATE, *PPGMHVUSTATE;
68
69
70/*******************************************************************************
71* Internal Functions *
72*******************************************************************************/
73DECLINLINE(int) pgmShwGetLongModePDPtr(PVM pVM, PVMCPU pVCpu, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPT *ppPdpt, PX86PDPAE *ppPD);
74DECLINLINE(int) pgmShwGetPAEPDPtr(PVM pVM, RTGCPTR GCPtr, PX86PDPT *ppPdpt, PX86PDPAE *ppPD);
75DECLINLINE(int) pgmShwGetPaePoolPagePD(PPGMCPU pPGM, RTGCPTR GCPtr, PPGMPOOLPAGE *ppShwPde);
76
77/*
78 * Shadow - 32-bit mode
79 */
80#define PGM_SHW_TYPE PGM_TYPE_32BIT
81#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
82#include "PGMAllShw.h"
83
84/* Guest - real mode */
85#define PGM_GST_TYPE PGM_TYPE_REAL
86#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
87#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
88#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
89#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
90#include "PGMGstDefs.h"
91#include "PGMAllGst.h"
92#include "PGMAllBth.h"
93#undef BTH_PGMPOOLKIND_PT_FOR_PT
94#undef BTH_PGMPOOLKIND_ROOT
95#undef PGM_BTH_NAME
96#undef PGM_GST_TYPE
97#undef PGM_GST_NAME
98
99/* Guest - protected mode */
100#define PGM_GST_TYPE PGM_TYPE_PROT
101#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
102#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
103#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
104#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
105#include "PGMGstDefs.h"
106#include "PGMAllGst.h"
107#include "PGMAllBth.h"
108#undef BTH_PGMPOOLKIND_PT_FOR_PT
109#undef BTH_PGMPOOLKIND_ROOT
110#undef PGM_BTH_NAME
111#undef PGM_GST_TYPE
112#undef PGM_GST_NAME
113
114/* Guest - 32-bit mode */
115#define PGM_GST_TYPE PGM_TYPE_32BIT
116#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
117#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
118#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
119#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
120#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD
121#include "PGMGstDefs.h"
122#include "PGMAllGst.h"
123#include "PGMAllBth.h"
124#undef BTH_PGMPOOLKIND_PT_FOR_BIG
125#undef BTH_PGMPOOLKIND_PT_FOR_PT
126#undef BTH_PGMPOOLKIND_ROOT
127#undef PGM_BTH_NAME
128#undef PGM_GST_TYPE
129#undef PGM_GST_NAME
130
131#undef PGM_SHW_TYPE
132#undef PGM_SHW_NAME
133
134
135/*
136 * Shadow - PAE mode
137 */
138#define PGM_SHW_TYPE PGM_TYPE_PAE
139#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
140#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
141#include "PGMAllShw.h"
142
143/* Guest - real mode */
144#define PGM_GST_TYPE PGM_TYPE_REAL
145#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
146#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
147#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
148#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
149#include "PGMGstDefs.h"
150#include "PGMAllBth.h"
151#undef BTH_PGMPOOLKIND_PT_FOR_PT
152#undef BTH_PGMPOOLKIND_ROOT
153#undef PGM_BTH_NAME
154#undef PGM_GST_TYPE
155#undef PGM_GST_NAME
156
157/* Guest - protected mode */
158#define PGM_GST_TYPE PGM_TYPE_PROT
159#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
160#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
161#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
162#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
163#include "PGMGstDefs.h"
164#include "PGMAllBth.h"
165#undef BTH_PGMPOOLKIND_PT_FOR_PT
166#undef BTH_PGMPOOLKIND_ROOT
167#undef PGM_BTH_NAME
168#undef PGM_GST_TYPE
169#undef PGM_GST_NAME
170
171/* Guest - 32-bit mode */
172#define PGM_GST_TYPE PGM_TYPE_32BIT
173#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
174#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
175#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
176#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
177#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_FOR_32BIT
178#include "PGMGstDefs.h"
179#include "PGMAllBth.h"
180#undef BTH_PGMPOOLKIND_PT_FOR_BIG
181#undef BTH_PGMPOOLKIND_PT_FOR_PT
182#undef BTH_PGMPOOLKIND_ROOT
183#undef PGM_BTH_NAME
184#undef PGM_GST_TYPE
185#undef PGM_GST_NAME
186
187
188/* Guest - PAE mode */
189#define PGM_GST_TYPE PGM_TYPE_PAE
190#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
191#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
192#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
193#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
194#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT
195#include "PGMGstDefs.h"
196#include "PGMAllGst.h"
197#include "PGMAllBth.h"
198#undef BTH_PGMPOOLKIND_PT_FOR_BIG
199#undef BTH_PGMPOOLKIND_PT_FOR_PT
200#undef BTH_PGMPOOLKIND_ROOT
201#undef PGM_BTH_NAME
202#undef PGM_GST_TYPE
203#undef PGM_GST_NAME
204
205#undef PGM_SHW_TYPE
206#undef PGM_SHW_NAME
207
208
209#ifndef IN_RC /* AMD64 implies VT-x/AMD-V */
210/*
211 * Shadow - AMD64 mode
212 */
213# define PGM_SHW_TYPE PGM_TYPE_AMD64
214# define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
215# include "PGMAllShw.h"
216
217/* Guest - protected mode (only used for AMD-V nested paging in 64 bits mode) */
218# define PGM_GST_TYPE PGM_TYPE_PROT
219# define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
220# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_PROT(name)
221# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
222# define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PD_PHYS
223# include "PGMGstDefs.h"
224# include "PGMAllBth.h"
225# undef BTH_PGMPOOLKIND_PT_FOR_PT
226# undef BTH_PGMPOOLKIND_ROOT
227# undef PGM_BTH_NAME
228# undef PGM_GST_TYPE
229# undef PGM_GST_NAME
230
231# ifdef VBOX_WITH_64_BITS_GUESTS
232/* Guest - AMD64 mode */
233# define PGM_GST_TYPE PGM_TYPE_AMD64
234# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
235# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
236# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
237# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
238# define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_64BIT_PML4
239# include "PGMGstDefs.h"
240# include "PGMAllGst.h"
241# include "PGMAllBth.h"
242# undef BTH_PGMPOOLKIND_PT_FOR_BIG
243# undef BTH_PGMPOOLKIND_PT_FOR_PT
244# undef BTH_PGMPOOLKIND_ROOT
245# undef PGM_BTH_NAME
246# undef PGM_GST_TYPE
247# undef PGM_GST_NAME
248# endif /* VBOX_WITH_64_BITS_GUESTS */
249
250# undef PGM_SHW_TYPE
251# undef PGM_SHW_NAME
252
253
254/*
255 * Shadow - Nested paging mode
256 */
257# define PGM_SHW_TYPE PGM_TYPE_NESTED
258# define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED(name)
259# include "PGMAllShw.h"
260
261/* Guest - real mode */
262# define PGM_GST_TYPE PGM_TYPE_REAL
263# define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
264# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_REAL(name)
265# include "PGMGstDefs.h"
266# include "PGMAllBth.h"
267# undef PGM_BTH_NAME
268# undef PGM_GST_TYPE
269# undef PGM_GST_NAME
270
271/* Guest - protected mode */
272# define PGM_GST_TYPE PGM_TYPE_PROT
273# define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
274# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PROT(name)
275# include "PGMGstDefs.h"
276# include "PGMAllBth.h"
277# undef PGM_BTH_NAME
278# undef PGM_GST_TYPE
279# undef PGM_GST_NAME
280
281/* Guest - 32-bit mode */
282# define PGM_GST_TYPE PGM_TYPE_32BIT
283# define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
284# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT(name)
285# include "PGMGstDefs.h"
286# include "PGMAllBth.h"
287# undef PGM_BTH_NAME
288# undef PGM_GST_TYPE
289# undef PGM_GST_NAME
290
291/* Guest - PAE mode */
292# define PGM_GST_TYPE PGM_TYPE_PAE
293# define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
294# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE(name)
295# include "PGMGstDefs.h"
296# include "PGMAllBth.h"
297# undef PGM_BTH_NAME
298# undef PGM_GST_TYPE
299# undef PGM_GST_NAME
300
301# ifdef VBOX_WITH_64_BITS_GUESTS
302/* Guest - AMD64 mode */
303# define PGM_GST_TYPE PGM_TYPE_AMD64
304# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
305# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64(name)
306# include "PGMGstDefs.h"
307# include "PGMAllBth.h"
308# undef PGM_BTH_NAME
309# undef PGM_GST_TYPE
310# undef PGM_GST_NAME
311# endif /* VBOX_WITH_64_BITS_GUESTS */
312
313# undef PGM_SHW_TYPE
314# undef PGM_SHW_NAME
315
316
317/*
318 * Shadow - EPT
319 */
320# define PGM_SHW_TYPE PGM_TYPE_EPT
321# define PGM_SHW_NAME(name) PGM_SHW_NAME_EPT(name)
322# include "PGMAllShw.h"
323
324/* Guest - real mode */
325# define PGM_GST_TYPE PGM_TYPE_REAL
326# define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
327# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_REAL(name)
328# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
329# include "PGMGstDefs.h"
330# include "PGMAllBth.h"
331# undef BTH_PGMPOOLKIND_PT_FOR_PT
332# undef PGM_BTH_NAME
333# undef PGM_GST_TYPE
334# undef PGM_GST_NAME
335
336/* Guest - protected mode */
337# define PGM_GST_TYPE PGM_TYPE_PROT
338# define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
339# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PROT(name)
340# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
341# include "PGMGstDefs.h"
342# include "PGMAllBth.h"
343# undef BTH_PGMPOOLKIND_PT_FOR_PT
344# undef PGM_BTH_NAME
345# undef PGM_GST_TYPE
346# undef PGM_GST_NAME
347
348/* Guest - 32-bit mode */
349# define PGM_GST_TYPE PGM_TYPE_32BIT
350# define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
351# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_32BIT(name)
352# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
353# include "PGMGstDefs.h"
354# include "PGMAllBth.h"
355# undef BTH_PGMPOOLKIND_PT_FOR_PT
356# undef PGM_BTH_NAME
357# undef PGM_GST_TYPE
358# undef PGM_GST_NAME
359
360/* Guest - PAE mode */
361# define PGM_GST_TYPE PGM_TYPE_PAE
362# define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
363# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PAE(name)
364# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
365# include "PGMGstDefs.h"
366# include "PGMAllBth.h"
367# undef BTH_PGMPOOLKIND_PT_FOR_PT
368# undef PGM_BTH_NAME
369# undef PGM_GST_TYPE
370# undef PGM_GST_NAME
371
372# ifdef VBOX_WITH_64_BITS_GUESTS
373/* Guest - AMD64 mode */
374# define PGM_GST_TYPE PGM_TYPE_AMD64
375# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
376# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_AMD64(name)
377# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
378# include "PGMGstDefs.h"
379# include "PGMAllBth.h"
380# undef BTH_PGMPOOLKIND_PT_FOR_PT
381# undef PGM_BTH_NAME
382# undef PGM_GST_TYPE
383# undef PGM_GST_NAME
384# endif /* VBOX_WITH_64_BITS_GUESTS */
385
386# undef PGM_SHW_TYPE
387# undef PGM_SHW_NAME
388
389#endif /* !IN_RC */
390
391
392#ifndef IN_RING3
393/**
394 * #PF Handler.
395 *
396 * @returns VBox status code (appropriate for trap handling and GC return).
397 * @param pVM VM Handle.
398 * @param pVCpu VMCPU handle.
399 * @param uErr The trap error code.
400 * @param pRegFrame Trap register frame.
401 * @param pvFault The fault address.
402 */
403VMMDECL(int) PGMTrap0eHandler(PVM pVM, PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
404{
405 LogFlow(("PGMTrap0eHandler: uErr=%RGu pvFault=%RGv eip=%04x:%RGv\n", uErr, pvFault, pRegFrame->cs, (RTGCPTR)pRegFrame->rip));
406 STAM_PROFILE_START(&pVCpu->pgm.s.StatRZTrap0e, a);
407 STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = NULL; } );
408
409
410#ifdef VBOX_WITH_STATISTICS
411 /*
412 * Error code stats.
413 */
414 if (uErr & X86_TRAP_PF_US)
415 {
416 if (!(uErr & X86_TRAP_PF_P))
417 {
418 if (uErr & X86_TRAP_PF_RW)
419 STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eUSNotPresentWrite);
420 else
421 STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eUSNotPresentRead);
422 }
423 else if (uErr & X86_TRAP_PF_RW)
424 STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eUSWrite);
425 else if (uErr & X86_TRAP_PF_RSVD)
426 STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eUSReserved);
427 else if (uErr & X86_TRAP_PF_ID)
428 STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eUSNXE);
429 else
430 STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eUSRead);
431 }
432 else
433 { /* Supervisor */
434 if (!(uErr & X86_TRAP_PF_P))
435 {
436 if (uErr & X86_TRAP_PF_RW)
437 STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eSVNotPresentWrite);
438 else
439 STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eSVNotPresentRead);
440 }
441 else if (uErr & X86_TRAP_PF_RW)
442 STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eSVWrite);
443 else if (uErr & X86_TRAP_PF_ID)
444 STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eSNXE);
445 else if (uErr & X86_TRAP_PF_RSVD)
446 STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eSVReserved);
447 }
448#endif /* VBOX_WITH_STATISTICS */
449
450 /*
451 * Call the worker.
452 */
453 int rc = PGM_BTH_PFN(Trap0eHandler, pVM)(pVM, pVCpu, uErr, pRegFrame, pvFault);
454 if (rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
455 rc = VINF_SUCCESS;
456 STAM_STATS({ if (rc == VINF_EM_RAW_GUEST_TRAP) STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eGuestPF); });
457 STAM_STATS({ if (!pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution))
458 pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2Misc; });
459 STAM_PROFILE_STOP_EX(&pVCpu->pgm.s.StatRZTrap0e, pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution), a);
460 return rc;
461}
462#endif /* !IN_RING3 */
463
464
465/**
466 * Prefetch a page
467 *
468 * Typically used to sync commonly used pages before entering raw mode
469 * after a CR3 reload.
470 *
471 * @returns VBox status code suitable for scheduling.
472 * @retval VINF_SUCCESS on success.
473 * @retval VINF_PGM_SYNC_CR3 if we're out of shadow pages or something like that.
474 * @param pVM VM handle.
475 * @param pVCpu VMCPU handle.
476 * @param GCPtrPage Page to invalidate.
477 */
478VMMDECL(int) PGMPrefetchPage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCPtrPage)
479{
480 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_MID_Z(Stat,Prefetch), a);
481 int rc = PGM_BTH_PFN(PrefetchPage, pVM)(pVM, pVCpu, GCPtrPage);
482 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,Prefetch), a);
483 AssertMsg(rc == VINF_SUCCESS || rc == VINF_PGM_SYNC_CR3 || RT_FAILURE(rc), ("rc=%Rrc\n", rc));
484 return rc;
485}
486
487
488/**
489 * Gets the mapping corresponding to the specified address (if any).
490 *
491 * @returns Pointer to the mapping.
492 * @returns NULL if not
493 *
494 * @param pVM The virtual machine.
495 * @param GCPtr The guest context pointer.
496 */
497PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr)
498{
499 PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
500 while (pMapping)
501 {
502 if ((uintptr_t)GCPtr < (uintptr_t)pMapping->GCPtr)
503 break;
504 if ((uintptr_t)GCPtr - (uintptr_t)pMapping->GCPtr < pMapping->cb)
505 return pMapping;
506 pMapping = pMapping->CTX_SUFF(pNext);
507 }
508 return NULL;
509}
510
511
512/**
513 * Verifies a range of pages for read or write access
514 *
515 * Only checks the guest's page tables
516 *
517 * @returns VBox status code.
518 * @param pVM VM handle.
519 * @param pVCpu VMCPU handle.
520 * @param Addr Guest virtual address to check
521 * @param cbSize Access size
522 * @param fAccess Access type (r/w, user/supervisor (X86_PTE_*))
523 * @remarks Current not in use.
524 */
525VMMDECL(int) PGMIsValidAccess(PVM pVM, PVMCPU pVCpu, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess)
526{
527 /*
528 * Validate input.
529 */
530 if (fAccess & ~(X86_PTE_US | X86_PTE_RW))
531 {
532 AssertMsgFailed(("PGMIsValidAccess: invalid access type %08x\n", fAccess));
533 return VERR_INVALID_PARAMETER;
534 }
535
536 uint64_t fPage;
537 int rc = PGMGstGetPage(pVM, pVCpu, (RTGCPTR)Addr, &fPage, NULL);
538 if (RT_FAILURE(rc))
539 {
540 Log(("PGMIsValidAccess: access violation for %RGv rc=%d\n", Addr, rc));
541 return VINF_EM_RAW_GUEST_TRAP;
542 }
543
544 /*
545 * Check if the access would cause a page fault
546 *
547 * Note that hypervisor page directories are not present in the guest's tables, so this check
548 * is sufficient.
549 */
550 bool fWrite = !!(fAccess & X86_PTE_RW);
551 bool fUser = !!(fAccess & X86_PTE_US);
552 if ( !(fPage & X86_PTE_P)
553 || (fWrite && !(fPage & X86_PTE_RW))
554 || (fUser && !(fPage & X86_PTE_US)) )
555 {
556 Log(("PGMIsValidAccess: access violation for %RGv attr %#llx vs %d:%d\n", Addr, fPage, fWrite, fUser));
557 return VINF_EM_RAW_GUEST_TRAP;
558 }
559 if ( RT_SUCCESS(rc)
560 && PAGE_ADDRESS(Addr) != PAGE_ADDRESS(Addr + cbSize))
561 return PGMIsValidAccess(pVM, pVCpu, Addr + PAGE_SIZE, (cbSize > PAGE_SIZE) ? cbSize - PAGE_SIZE : 1, fAccess);
562 return rc;
563}
564
565
566/**
567 * Verifies a range of pages for read or write access
568 *
569 * Supports handling of pages marked for dirty bit tracking and CSAM
570 *
571 * @returns VBox status code.
572 * @param pVM VM handle.
573 * @param pVCpu VMCPU handle.
574 * @param Addr Guest virtual address to check
575 * @param cbSize Access size
576 * @param fAccess Access type (r/w, user/supervisor (X86_PTE_*))
577 */
578VMMDECL(int) PGMVerifyAccess(PVM pVM, PVMCPU pVCpu, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess)
579{
580 AssertMsg(!(fAccess & ~(X86_PTE_US | X86_PTE_RW)), ("PGMVerifyAccess: invalid access type %08x\n", fAccess));
581
582 /*
583 * Get going.
584 */
585 uint64_t fPageGst;
586 int rc = PGMGstGetPage(pVM, pVCpu, (RTGCPTR)Addr, &fPageGst, NULL);
587 if (RT_FAILURE(rc))
588 {
589 Log(("PGMVerifyAccess: access violation for %RGv rc=%d\n", Addr, rc));
590 return VINF_EM_RAW_GUEST_TRAP;
591 }
592
593 /*
594 * Check if the access would cause a page fault
595 *
596 * Note that hypervisor page directories are not present in the guest's tables, so this check
597 * is sufficient.
598 */
599 const bool fWrite = !!(fAccess & X86_PTE_RW);
600 const bool fUser = !!(fAccess & X86_PTE_US);
601 if ( !(fPageGst & X86_PTE_P)
602 || (fWrite && !(fPageGst & X86_PTE_RW))
603 || (fUser && !(fPageGst & X86_PTE_US)) )
604 {
605 Log(("PGMVerifyAccess: access violation for %RGv attr %#llx vs %d:%d\n", Addr, fPageGst, fWrite, fUser));
606 return VINF_EM_RAW_GUEST_TRAP;
607 }
608
609 if (!HWACCMIsNestedPagingActive(pVM))
610 {
611 /*
612 * Next step is to verify if we protected this page for dirty bit tracking or for CSAM scanning
613 */
614 rc = PGMShwGetPage(pVM, pVCpu, (RTGCPTR)Addr, NULL, NULL);
615 if ( rc == VERR_PAGE_NOT_PRESENT
616 || rc == VERR_PAGE_TABLE_NOT_PRESENT)
617 {
618 /*
619 * Page is not present in our page tables.
620 * Try to sync it!
621 */
622 Assert(X86_TRAP_PF_RW == X86_PTE_RW && X86_TRAP_PF_US == X86_PTE_US);
623 uint32_t uErr = fAccess & (X86_TRAP_PF_RW | X86_TRAP_PF_US);
624 rc = PGM_BTH_PFN(VerifyAccessSyncPage, pVM)(pVM, pVCpu, Addr, fPageGst, uErr);
625 if (rc != VINF_SUCCESS)
626 return rc;
627 }
628 else
629 AssertMsg(rc == VINF_SUCCESS, ("PGMShwGetPage %RGv failed with %Rrc\n", Addr, rc));
630 }
631
632#if 0 /* def VBOX_STRICT; triggers too often now */
633 /*
634 * This check is a bit paranoid, but useful.
635 */
636 /** @note this will assert when writing to monitored pages (a bit annoying actually) */
637 uint64_t fPageShw;
638 rc = PGMShwGetPage(pVM, pVCpu, (RTGCPTR)Addr, &fPageShw, NULL);
639 if ( (rc == VERR_PAGE_NOT_PRESENT || RT_FAILURE(rc))
640 || (fWrite && !(fPageShw & X86_PTE_RW))
641 || (fUser && !(fPageShw & X86_PTE_US)) )
642 {
643 AssertMsgFailed(("Unexpected access violation for %RGv! rc=%Rrc write=%d user=%d\n",
644 Addr, rc, fWrite && !(fPageShw & X86_PTE_RW), fUser && !(fPageShw & X86_PTE_US)));
645 return VINF_EM_RAW_GUEST_TRAP;
646 }
647#endif
648
649 if ( RT_SUCCESS(rc)
650 && ( PAGE_ADDRESS(Addr) != PAGE_ADDRESS(Addr + cbSize - 1)
651 || Addr + cbSize < Addr))
652 {
653 /* Don't recursively call PGMVerifyAccess as we might run out of stack. */
654 for (;;)
655 {
656 Addr += PAGE_SIZE;
657 if (cbSize > PAGE_SIZE)
658 cbSize -= PAGE_SIZE;
659 else
660 cbSize = 1;
661 rc = PGMVerifyAccess(pVM, pVCpu, Addr, 1, fAccess);
662 if (rc != VINF_SUCCESS)
663 break;
664 if (PAGE_ADDRESS(Addr) == PAGE_ADDRESS(Addr + cbSize - 1))
665 break;
666 }
667 }
668 return rc;
669}
670
671
672/**
673 * Emulation of the invlpg instruction (HC only actually).
674 *
675 * @returns VBox status code, special care required.
676 * @retval VINF_PGM_SYNC_CR3 - handled.
677 * @retval VINF_EM_RAW_EMULATE_INSTR - not handled (RC only).
678 * @retval VERR_REM_FLUSHED_PAGES_OVERFLOW - not handled.
679 *
680 * @param pVM VM handle.
681 * @param pVCpu VMCPU handle.
682 * @param GCPtrPage Page to invalidate.
683 *
684 * @remark ASSUMES the page table entry or page directory is valid. Fairly
685 * safe, but there could be edge cases!
686 *
687 * @todo Flush page or page directory only if necessary!
688 */
689VMMDECL(int) PGMInvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCPtrPage)
690{
691 int rc;
692 Log3(("PGMInvalidatePage: GCPtrPage=%RGv\n", GCPtrPage));
693
694#ifndef IN_RING3
695 /*
696 * Notify the recompiler so it can record this instruction.
697 * Failure happens when it's out of space. We'll return to HC in that case.
698 */
699 rc = REMNotifyInvalidatePage(pVM, GCPtrPage);
700 if (rc != VINF_SUCCESS)
701 return rc;
702#endif /* !IN_RING3 */
703
704
705#ifdef IN_RC
706 /*
707 * Check for conflicts and pending CR3 monitoring updates.
708 */
709 if (!pVM->pgm.s.fMappingsFixed)
710 {
711 if ( pgmGetMapping(pVM, GCPtrPage)
712 && PGMGstGetPage(pVM, pVCpu, GCPtrPage, NULL, NULL) != VERR_PAGE_TABLE_NOT_PRESENT)
713 {
714 LogFlow(("PGMGCInvalidatePage: Conflict!\n"));
715 VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
716 STAM_COUNTER_INC(&pVM->pgm.s.StatRCInvlPgConflict);
717 return VINF_PGM_SYNC_CR3;
718 }
719
720 if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
721 {
722 LogFlow(("PGMGCInvalidatePage: PGM_SYNC_MONITOR_CR3 -> reinterpret instruction in R3\n"));
723 STAM_COUNTER_INC(&pVM->pgm.s.StatRCInvlPgSyncMonCR3);
724 return VINF_EM_RAW_EMULATE_INSTR;
725 }
726 }
727#endif /* IN_RC */
728
729 /*
730 * Call paging mode specific worker.
731 */
732 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePage), a);
733 rc = PGM_BTH_PFN(InvalidatePage, pVM)(pVM, pVCpu, GCPtrPage);
734 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePage), a);
735
736#ifdef IN_RING3
737 /*
738 * Check if we have a pending update of the CR3 monitoring.
739 */
740 if ( RT_SUCCESS(rc)
741 && (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3))
742 {
743 pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
744 Assert(!pVM->pgm.s.fMappingsFixed);
745 }
746
747 /*
748 * Inform CSAM about the flush
749 *
750 * Note: This is to check if monitored pages have been changed; when we implement
751 * callbacks for virtual handlers, this is no longer required.
752 */
753 CSAMR3FlushPage(pVM, GCPtrPage);
754#endif /* IN_RING3 */
755 return rc;
756}
757
758
759/**
760 * Executes an instruction using the interpreter.
761 *
762 * @returns VBox status code (appropriate for trap handling and GC return).
763 * @param pVM VM handle.
764 * @param pVCpu VMCPU handle.
765 * @param pRegFrame Register frame.
766 * @param pvFault Fault address.
767 */
768VMMDECL(int) PGMInterpretInstruction(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
769{
770 uint32_t cb;
771 int rc = EMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault, &cb);
772 if (rc == VERR_EM_INTERPRETER)
773 rc = VINF_EM_RAW_EMULATE_INSTR;
774 if (rc != VINF_SUCCESS)
775 Log(("PGMInterpretInstruction: returns %Rrc (pvFault=%RGv)\n", rc, pvFault));
776 return rc;
777}
778
779
780/**
781 * Gets effective page information (from the VMM page directory).
782 *
783 * @returns VBox status.
784 * @param pVM VM Handle.
785 * @param pVCpu VMCPU handle.
786 * @param GCPtr Guest Context virtual address of the page.
787 * @param pfFlags Where to store the flags. These are X86_PTE_*.
788 * @param pHCPhys Where to store the HC physical address of the page.
789 * This is page aligned.
790 * @remark You should use PGMMapGetPage() for pages in a mapping.
791 */
792VMMDECL(int) PGMShwGetPage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys)
793{
794 return PGM_SHW_PFN(GetPage,pVM)(pVM, pVCpu, GCPtr, pfFlags, pHCPhys);
795}
796
797
798/**
799 * Sets (replaces) the page flags for a range of pages in the shadow context.
800 *
801 * @returns VBox status.
802 * @param pVM VM handle.
803 * @param pVCpu VMCPU handle.
804 * @param GCPtr The address of the first page.
805 * @param cb The size of the range in bytes.
806 * @param fFlags Page flags X86_PTE_*, excluding the page mask of course.
807 * @remark You must use PGMMapSetPage() for pages in a mapping.
808 */
809VMMDECL(int) PGMShwSetPage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags)
810{
811 return PGMShwModifyPage(pVM, pVCpu, GCPtr, cb, fFlags, 0);
812}
813
814
815/**
816 * Modify page flags for a range of pages in the shadow context.
817 *
818 * The existing flags are ANDed with the fMask and ORed with the fFlags.
819 *
820 * @returns VBox status code.
821 * @param pVM VM handle.
822 * @param pVCpu VMCPU handle.
823 * @param GCPtr Virtual address of the first page in the range.
824 * @param cb Size (in bytes) of the range to apply the modification to.
825 * @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
826 * @param fMask The AND mask - page flags X86_PTE_*.
827 * Be very CAREFUL when ~'ing constants which could be 32-bit!
828 * @remark You must use PGMMapModifyPage() for pages in a mapping.
829 */
830VMMDECL(int) PGMShwModifyPage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
831{
832 AssertMsg(!(fFlags & X86_PTE_PAE_PG_MASK), ("fFlags=%#llx\n", fFlags));
833 Assert(cb);
834
835 /*
836 * Align the input.
837 */
838 cb += GCPtr & PAGE_OFFSET_MASK;
839 cb = RT_ALIGN_Z(cb, PAGE_SIZE);
840 GCPtr = (GCPtr & PAGE_BASE_GC_MASK); /** @todo this ain't necessary, right... */
841
842 /*
843 * Call worker.
844 */
845 return PGM_SHW_PFN(ModifyPage, pVM)(pVM, pVCpu, GCPtr, cb, fFlags, fMask);
846}
847
848
849#if 0 /* obsolete */
850/**
851 * Gets the SHADOW page directory pointer for the specified address.
852 *
853 * @returns VBox status.
854 * @param pVM VM handle.
855 * @param pVCpu VMCPU handle.
856 * @param GCPtr The address.
857 * @param ppPdpt Receives address of pdpt
858 * @param ppPD Receives address of page directory
859 * @remarks Unused.
860 */
861DECLINLINE(int) pgmShwGetPAEPDPtr(PVM pVM, RTGCPTR GCPtr, PX86PDPT *ppPdpt, PX86PDPAE *ppPD)
862{
863 PPGM pPGM = &pVM->pgm.s;
864 PPGMPOOL pPool = pPGM->CTX_SUFF(pPool);
865 PPGMPOOLPAGE pShwPage;
866
867 Assert(!HWACCMIsNestedPagingActive(pVM));
868
869 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
870 PX86PDPT pPdpt = pgmShwGetPaePDPTPtr(&pVM->pgm.s);
871 PX86PDPE pPdpe = &pPdpt->a[iPdPt];
872
873 *ppPdpt = pPdpt;
874 if (!pPdpe->n.u1Present)
875 return VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT;
876
877 Assert(pPdpe->u & X86_PDPE_PG_MASK);
878 pShwPage = pgmPoolGetPage(pPool, pPdpe->u & X86_PDPE_PG_MASK);
879 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
880
881 *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
882 return VINF_SUCCESS;
883}
884#endif
885
886/**
887 * Gets the shadow page directory for the specified address, PAE.
888 *
889 * @returns Pointer to the shadow PD.
890 * @param pVM VM handle.
891 * @param pVCpu The VMCPU handle.
892 * @param GCPtr The address.
893 * @param pGstPdpe Guest PDPT entry
894 * @param ppPD Receives address of page directory
895 */
896int pgmShwSyncPaePDPtr(PVM pVM, PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDPE pGstPdpe, PX86PDPAE *ppPD)
897{
898 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
899 PX86PDPT pPdpt = pgmShwGetPaePDPTPtr(&pVCpu->pgm.s);
900 PX86PDPE pPdpe = &pPdpt->a[iPdPt];
901 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
902 PPGMPOOLPAGE pShwPage;
903 int rc;
904
905 /* Allocate page directory if not present. */
906 if ( !pPdpe->n.u1Present
907 && !(pPdpe->u & X86_PDPE_PG_MASK))
908 {
909 bool fNestedPaging = HWACCMIsNestedPagingActive(pVM);
910 bool fPaging = !!(CPUMGetGuestCR0(pVCpu) & X86_CR0_PG);
911 RTGCPTR64 GCPdPt;
912 PGMPOOLKIND enmKind;
913
914# if defined(IN_RC)
915 /* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
916 PGMDynLockHCPage(pVM, (uint8_t *)pPdpe);
917# endif
918
919 if (fNestedPaging || !fPaging)
920 {
921 /* AMD-V nested paging or real/protected mode without paging */
922 GCPdPt = (RTGCPTR64)iPdPt << X86_PDPT_SHIFT;
923 enmKind = PGMPOOLKIND_PAE_PD_PHYS;
924 }
925 else
926 {
927 Assert(pGstPdpe);
928
929 if (CPUMGetGuestCR4(pVCpu) & X86_CR4_PAE)
930 {
931 if (!pGstPdpe->n.u1Present)
932 {
933 /* PD not present; guest must reload CR3 to change it.
934 * No need to monitor anything in this case.
935 */
936 Assert(!HWACCMIsEnabled(pVM));
937
938 GCPdPt = pGstPdpe->u & X86_PDPE_PG_MASK;
939 enmKind = PGMPOOLKIND_PAE_PD_PHYS;
940 pGstPdpe->n.u1Present = 1;
941 }
942 else
943 {
944 GCPdPt = pGstPdpe->u & X86_PDPE_PG_MASK;
945 enmKind = PGMPOOLKIND_PAE_PD_FOR_PAE_PD;
946 }
947 }
948 else
949 {
950 GCPdPt = CPUMGetGuestCR3(pVCpu);
951 enmKind = (PGMPOOLKIND)(PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD + iPdPt);
952 }
953 }
954
955 /* Create a reference back to the PDPT by using the index in its shadow page. */
956 rc = pgmPoolAlloc(pVM, GCPdPt, enmKind, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPdPt, &pShwPage);
957 AssertRCReturn(rc, rc);
958
959 /* The PD was cached or created; hook it up now. */
960 pPdpe->u |= pShwPage->Core.Key
961 | (pGstPdpe->u & ~(X86_PDPE_PG_MASK | X86_PDPE_AVL_MASK | X86_PDPE_PCD | X86_PDPE_PWT));
962
963# if defined(IN_RC)
964 /* In 32 bits PAE mode we *must* invalidate the TLB when changing a PDPT entry; the CPU fetches them only during cr3 load, so any
965 * non-present PDPT will continue to cause page faults.
966 */
967 ASMReloadCR3();
968 PGMDynUnlockHCPage(pVM, (uint8_t *)pPdpe);
969# endif
970 }
971 else
972 {
973 pShwPage = pgmPoolGetPage(pPool, pPdpe->u & X86_PDPE_PG_MASK);
974 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
975 Assert((pPdpe->u & X86_PDPE_PG_MASK) == pShwPage->Core.Key);
976
977 pgmPoolCacheUsed(pPool, pShwPage);
978 }
979 *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
980 return VINF_SUCCESS;
981}
982
983
984/**
985 * Gets the pointer to the shadow page directory entry for an address, PAE.
986 *
987 * @returns Pointer to the PDE.
988 * @param pPGM Pointer to the PGMCPU instance data.
989 * @param GCPtr The address.
990 * @param ppShwPde Receives the address of the pgm pool page for the shadow page directory
991 */
992DECLINLINE(int) pgmShwGetPaePoolPagePD(PPGMCPU pPGM, RTGCPTR GCPtr, PPGMPOOLPAGE *ppShwPde)
993{
994 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
995 PX86PDPT pPdpt = pgmShwGetPaePDPTPtr(pPGM);
996 AssertReturn(pPdpt, VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT); /* can't happen */
997 if (!pPdpt->a[iPdPt].n.u1Present)
998 {
999 LogFlow(("pgmShwGetPaePoolPagePD: PD %d not present (%RX64)\n", iPdPt, pPdpt->a[iPdPt].u));
1000 return VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT;
1001 }
1002 AssertMsg(pPdpt->a[iPdPt].u & X86_PDPE_PG_MASK, ("GCPtr=%RGv\n", GCPtr));
1003
1004 /* Fetch the pgm pool shadow descriptor. */
1005 PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(PGMCPU2VM(pPGM), pPdpt->a[iPdPt].u & X86_PDPE_PG_MASK);
1006 AssertReturn(pShwPde, VERR_INTERNAL_ERROR);
1007
1008 *ppShwPde = pShwPde;
1009 return VINF_SUCCESS;
1010}
1011
1012#ifndef IN_RC
1013
1014/**
1015 * Syncs the SHADOW page directory pointer for the specified address.
1016 *
1017 * Allocates backing pages in case the PDPT or PML4 entry is missing.
1018 *
1019 * The caller is responsible for making sure the guest has a valid PD before
1020 * calling this function.
1021 *
1022 * @returns VBox status.
1023 * @param pVM VM handle.
1024 * @param pVCpu VMCPU handle.
1025 * @param GCPtr The address.
1026 * @param pGstPml4e Guest PML4 entry
1027 * @param pGstPdpe Guest PDPT entry
1028 * @param ppPD Receives address of page directory
1029 */
1030int pgmShwSyncLongModePDPtr(PVM pVM, PVMCPU pVCpu, RTGCPTR64 GCPtr, PX86PML4E pGstPml4e, PX86PDPE pGstPdpe, PX86PDPAE *ppPD)
1031{
1032 PPGMCPU pPGM = &pVCpu->pgm.s;
1033 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1034 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
1035 PX86PML4E pPml4e = pgmShwGetLongModePML4EPtr(pPGM, iPml4);
1036 bool fNestedPaging = HWACCMIsNestedPagingActive(pVM);
1037 bool fPaging = !!(CPUMGetGuestCR0(pVCpu) & X86_CR0_PG);
1038 PPGMPOOLPAGE pShwPage;
1039 int rc;
1040
1041 /* Allocate page directory pointer table if not present. */
1042 if ( !pPml4e->n.u1Present
1043 && !(pPml4e->u & X86_PML4E_PG_MASK))
1044 {
1045 RTGCPTR64 GCPml4;
1046 PGMPOOLKIND enmKind;
1047
1048 Assert(pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
1049
1050 if (fNestedPaging || !fPaging)
1051 {
1052 /* AMD-V nested paging or real/protected mode without paging */
1053 GCPml4 = (RTGCPTR64)iPml4 << X86_PML4_SHIFT;
1054 enmKind = PGMPOOLKIND_64BIT_PDPT_FOR_PHYS;
1055 }
1056 else
1057 {
1058 Assert(pGstPml4e && pGstPdpe);
1059
1060 GCPml4 = pGstPml4e->u & X86_PML4E_PG_MASK;
1061 enmKind = PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT;
1062 }
1063
1064 /* Create a reference back to the PDPT by using the index in its shadow page. */
1065 rc = pgmPoolAlloc(pVM, GCPml4, enmKind, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPml4, &pShwPage);
1066 AssertRCReturn(rc, rc);
1067 }
1068 else
1069 {
1070 pShwPage = pgmPoolGetPage(pPool, pPml4e->u & X86_PML4E_PG_MASK);
1071 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1072
1073 pgmPoolCacheUsed(pPool, pShwPage);
1074 }
1075 /* The PDPT was cached or created; hook it up now. */
1076 pPml4e->u |= pShwPage->Core.Key
1077 | (pGstPml4e->u & ~(X86_PML4E_PG_MASK | X86_PML4E_AVL_MASK | X86_PML4E_PCD | X86_PML4E_PWT));
1078
1079 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1080 PX86PDPT pPdpt = (PX86PDPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1081 PX86PDPE pPdpe = &pPdpt->a[iPdPt];
1082
1083 /* Allocate page directory if not present. */
1084 if ( !pPdpe->n.u1Present
1085 && !(pPdpe->u & X86_PDPE_PG_MASK))
1086 {
1087 RTGCPTR64 GCPdPt;
1088 PGMPOOLKIND enmKind;
1089
1090 if (fNestedPaging || !fPaging)
1091 {
1092 /* AMD-V nested paging or real/protected mode without paging */
1093 GCPdPt = (RTGCPTR64)iPdPt << X86_PDPT_SHIFT;
1094 enmKind = PGMPOOLKIND_64BIT_PD_FOR_PHYS;
1095 }
1096 else
1097 {
1098 Assert(pGstPdpe);
1099
1100 GCPdPt = pGstPdpe->u & X86_PDPE_PG_MASK;
1101 enmKind = PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD;
1102 }
1103
1104 /* Create a reference back to the PDPT by using the index in its shadow page. */
1105 rc = pgmPoolAlloc(pVM, GCPdPt, enmKind, pShwPage->idx, iPdPt, &pShwPage);
1106 AssertRCReturn(rc, rc);
1107 }
1108 else
1109 {
1110 pShwPage = pgmPoolGetPage(pPool, pPdpe->u & X86_PDPE_PG_MASK);
1111 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1112
1113 pgmPoolCacheUsed(pPool, pShwPage);
1114 }
1115 /* The PD was cached or created; hook it up now. */
1116 pPdpe->u |= pShwPage->Core.Key
1117 | (pGstPdpe->u & ~(X86_PDPE_PG_MASK | X86_PDPE_AVL_MASK | X86_PDPE_PCD | X86_PDPE_PWT));
1118
1119 *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1120 return VINF_SUCCESS;
1121}
1122
1123
1124/**
1125 * Gets the SHADOW page directory pointer for the specified address (long mode).
1126 *
1127 * @returns VBox status.
1128 * @param pVM VM handle.
1129 * @param pVCpu VMCPU handle.
1130 * @param GCPtr The address.
1131 * @param ppPdpt Receives address of pdpt
1132 * @param ppPD Receives address of page directory
1133 */
1134DECLINLINE(int) pgmShwGetLongModePDPtr(PVM pVM, PVMCPU pVCpu, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPT *ppPdpt, PX86PDPAE *ppPD)
1135{
1136 PPGMCPU pPGM = &pVCpu->pgm.s;
1137 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
1138 PCX86PML4E pPml4e = pgmShwGetLongModePML4EPtr(pPGM, iPml4);
1139 AssertReturn(pPml4e, VERR_INTERNAL_ERROR);
1140 if (ppPml4e)
1141 *ppPml4e = (PX86PML4E)pPml4e;
1142
1143 Log4(("pgmShwGetLongModePDPtr %VGv (%VHv) %RX64\n", GCPtr, pPml4e, pPml4e->u));
1144
1145 if (!pPml4e->n.u1Present)
1146 return VERR_PAGE_MAP_LEVEL4_NOT_PRESENT;
1147
1148 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1149 PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPml4e->u & X86_PML4E_PG_MASK);
1150 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1151
1152 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1153 PCX86PDPT pPdpt = *ppPdpt = (PX86PDPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1154 if (!pPdpt->a[iPdPt].n.u1Present)
1155 return VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT;
1156
1157 pShwPage = pgmPoolGetPage(pPool, pPdpt->a[iPdPt].u & X86_PDPE_PG_MASK);
1158 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1159
1160 *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1161 return VINF_SUCCESS;
1162}
1163
1164
1165/**
1166 * Syncs the SHADOW EPT page directory pointer for the specified address. Allocates
1167 * backing pages in case the PDPT or PML4 entry is missing.
1168 *
1169 * @returns VBox status.
1170 * @param pVM VM handle.
1171 * @param pVCpu VMCPU handle.
1172 * @param GCPtr The address.
1173 * @param ppPdpt Receives address of pdpt
1174 * @param ppPD Receives address of page directory
1175 */
1176int pgmShwGetEPTPDPtr(PVM pVM, PVMCPU pVCpu, RTGCPTR64 GCPtr, PEPTPDPT *ppPdpt, PEPTPD *ppPD)
1177{
1178 PPGMCPU pPGM = &pVCpu->pgm.s;
1179 const unsigned iPml4 = (GCPtr >> EPT_PML4_SHIFT) & EPT_PML4_MASK;
1180 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1181 PEPTPML4 pPml4;
1182 PEPTPML4E pPml4e;
1183 PPGMPOOLPAGE pShwPage;
1184 int rc;
1185
1186 Assert(HWACCMIsNestedPagingActive(pVM));
1187
1188 pPml4 = (PEPTPML4)PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
1189 Assert(pPml4);
1190
1191 /* Allocate page directory pointer table if not present. */
1192 pPml4e = &pPml4->a[iPml4];
1193 if ( !pPml4e->n.u1Present
1194 && !(pPml4e->u & EPT_PML4E_PG_MASK))
1195 {
1196 Assert(!(pPml4e->u & EPT_PML4E_PG_MASK));
1197 RTGCPTR64 GCPml4 = (RTGCPTR64)iPml4 << EPT_PML4_SHIFT;
1198
1199 rc = pgmPoolAlloc(pVM, GCPml4, PGMPOOLKIND_EPT_PDPT_FOR_PHYS, PGMPOOL_IDX_NESTED_ROOT, iPml4, &pShwPage);
1200 AssertRCReturn(rc, rc);
1201 }
1202 else
1203 {
1204 pShwPage = pgmPoolGetPage(pPool, pPml4e->u & EPT_PML4E_PG_MASK);
1205 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1206
1207 pgmPoolCacheUsed(pPool, pShwPage);
1208 }
1209 /* The PDPT was cached or created; hook it up now and fill with the default value. */
1210 pPml4e->u = pShwPage->Core.Key;
1211 pPml4e->n.u1Present = 1;
1212 pPml4e->n.u1Write = 1;
1213 pPml4e->n.u1Execute = 1;
1214
1215 const unsigned iPdPt = (GCPtr >> EPT_PDPT_SHIFT) & EPT_PDPT_MASK;
1216 PEPTPDPT pPdpt = (PEPTPDPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1217 PEPTPDPTE pPdpe = &pPdpt->a[iPdPt];
1218
1219 if (ppPdpt)
1220 *ppPdpt = pPdpt;
1221
1222 /* Allocate page directory if not present. */
1223 if ( !pPdpe->n.u1Present
1224 && !(pPdpe->u & EPT_PDPTE_PG_MASK))
1225 {
1226 RTGCPTR64 GCPdPt = (RTGCPTR64)iPdPt << EPT_PDPT_SHIFT;
1227
1228 rc = pgmPoolAlloc(pVM, GCPdPt, PGMPOOLKIND_64BIT_PD_FOR_PHYS, pShwPage->idx, iPdPt, &pShwPage);
1229 AssertRCReturn(rc, rc);
1230 }
1231 else
1232 {
1233 pShwPage = pgmPoolGetPage(pPool, pPdpe->u & EPT_PDPTE_PG_MASK);
1234 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1235
1236 pgmPoolCacheUsed(pPool, pShwPage);
1237 }
1238 /* The PD was cached or created; hook it up now and fill with the default value. */
1239 pPdpe->u = pShwPage->Core.Key;
1240 pPdpe->n.u1Present = 1;
1241 pPdpe->n.u1Write = 1;
1242 pPdpe->n.u1Execute = 1;
1243
1244 *ppPD = (PEPTPD)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1245 return VINF_SUCCESS;
1246}
1247
1248#endif /* IN_RC */
1249
1250/**
1251 * Gets effective Guest OS page information.
1252 *
1253 * When GCPtr is in a big page, the function will return as if it was a normal
1254 * 4KB page. If the need for distinguishing between big and normal page becomes
1255 * necessary at a later point, a PGMGstGetPage() will be created for that
1256 * purpose.
1257 *
1258 * @returns VBox status.
1259 * @param pVM VM Handle.
1260 * @param pVCpu VMCPU handle.
1261 * @param GCPtr Guest Context virtual address of the page.
1262 * @param pfFlags Where to store the flags. These are X86_PTE_*, even for big pages.
1263 * @param pGCPhys Where to store the GC physical address of the page.
1264 * This is page aligned. The fact that the
1265 */
1266VMMDECL(int) PGMGstGetPage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys)
1267{
1268 return PGM_GST_PFN(GetPage,pVM)(pVM, pVCpu, GCPtr, pfFlags, pGCPhys);
1269}
1270
1271
1272/**
1273 * Checks if the page is present.
1274 *
1275 * @returns true if the page is present.
1276 * @returns false if the page is not present.
1277 * @param pVM The VM handle.
1278 * @param pVCpu VMCPU handle.
1279 * @param GCPtr Address within the page.
1280 */
1281VMMDECL(bool) PGMGstIsPagePresent(PVM pVM, PVMCPU pVCpu, RTGCPTR GCPtr)
1282{
1283 int rc = PGMGstGetPage(pVM, pVCpu, GCPtr, NULL, NULL);
1284 return RT_SUCCESS(rc);
1285}
1286
1287
1288/**
1289 * Sets (replaces) the page flags for a range of pages in the guest's tables.
1290 *
1291 * @returns VBox status.
1292 * @param pVM VM handle.
1293 * @param pVCpu VMCPU handle.
1294 * @param GCPtr The address of the first page.
1295 * @param cb The size of the range in bytes.
1296 * @param fFlags Page flags X86_PTE_*, excluding the page mask of course.
1297 */
1298VMMDECL(int) PGMGstSetPage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags)
1299{
1300 return PGMGstModifyPage(pVM, pVCpu, GCPtr, cb, fFlags, 0);
1301}
1302
1303
1304/**
1305 * Modify page flags for a range of pages in the guest's tables
1306 *
1307 * The existing flags are ANDed with the fMask and ORed with the fFlags.
1308 *
1309 * @returns VBox status code.
1310 * @param pVM VM handle.
1311 * @param pVCpu VMCPU handle.
1312 * @param GCPtr Virtual address of the first page in the range.
1313 * @param cb Size (in bytes) of the range to apply the modification to.
1314 * @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
1315 * @param fMask The AND mask - page flags X86_PTE_*, excluding the page mask of course.
1316 * Be very CAREFUL when ~'ing constants which could be 32-bit!
1317 */
1318VMMDECL(int) PGMGstModifyPage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
1319{
1320 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_MID_Z(Stat,GstModifyPage), a);
1321
1322 /*
1323 * Validate input.
1324 */
1325 AssertMsg(!(fFlags & X86_PTE_PAE_PG_MASK), ("fFlags=%#llx\n", fFlags));
1326 Assert(cb);
1327
1328 LogFlow(("PGMGstModifyPage %RGv %d bytes fFlags=%08llx fMask=%08llx\n", GCPtr, cb, fFlags, fMask));
1329
1330 /*
1331 * Adjust input.
1332 */
1333 cb += GCPtr & PAGE_OFFSET_MASK;
1334 cb = RT_ALIGN_Z(cb, PAGE_SIZE);
1335 GCPtr = (GCPtr & PAGE_BASE_GC_MASK);
1336
1337 /*
1338 * Call worker.
1339 */
1340 int rc = PGM_GST_PFN(ModifyPage, pVM)(pVM, pVCpu, GCPtr, cb, fFlags, fMask);
1341
1342 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,GstModifyPage), a);
1343 return rc;
1344}
1345
1346#ifdef IN_RING3
1347
1348/**
1349 * Performs the lazy mapping of the 32-bit guest PD.
1350 *
1351 * @returns Pointer to the mapping.
1352 * @param pPGM The PGM instance data.
1353 */
1354PX86PD pgmGstLazyMap32BitPD(PPGMCPU pPGM)
1355{
1356 Assert(!pPGM->CTX_SUFF(pGst32BitPd));
1357 PVM pVM = PGMCPU2VM(pPGM);
1358 pgmLock(pVM);
1359
1360 PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, pPGM->GCPhysCR3);
1361 AssertReturn(pPage, NULL);
1362
1363 RTHCPTR HCPtrGuestCR3;
1364 int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, pPGM->GCPhysCR3 & X86_CR3_PAGE_MASK, (void **)&HCPtrGuestCR3);
1365 AssertRCReturn(rc, NULL);
1366
1367 pPGM->pGst32BitPdR3 = (R3PTRTYPE(PX86PD))HCPtrGuestCR3;
1368# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1369 pPGM->pGst32BitPdR0 = (R0PTRTYPE(PX86PD))HCPtrGuestCR3;
1370# endif
1371
1372 pgmUnlock(pVM);
1373 return pPGM->CTX_SUFF(pGst32BitPd);
1374}
1375
1376
1377/**
1378 * Performs the lazy mapping of the PAE guest PDPT.
1379 *
1380 * @returns Pointer to the mapping.
1381 * @param pPGM The PGM instance data.
1382 */
1383PX86PDPT pgmGstLazyMapPaePDPT(PPGMCPU pPGM)
1384{
1385 Assert(!pPGM->CTX_SUFF(pGstPaePdpt));
1386 PVM pVM = PGMCPU2VM(pPGM);
1387 pgmLock(pVM);
1388
1389 PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, pPGM->GCPhysCR3);
1390 AssertReturn(pPage, NULL);
1391
1392 RTHCPTR HCPtrGuestCR3;
1393 int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, pPGM->GCPhysCR3 & X86_CR3_PAE_PAGE_MASK, (void **)&HCPtrGuestCR3);
1394 AssertRCReturn(rc, NULL);
1395
1396 pPGM->pGstPaePdptR3 = (R3PTRTYPE(PX86PDPT))HCPtrGuestCR3;
1397# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1398 pPGM->pGstPaePdptR0 = (R0PTRTYPE(PX86PDPT))HCPtrGuestCR3;
1399# endif
1400
1401 pgmUnlock(pVM);
1402 return pPGM->CTX_SUFF(pGstPaePdpt);
1403}
1404
1405#endif /* IN_RING3 */
1406
1407#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
1408/**
1409 * Performs the lazy mapping / updating of a PAE guest PD.
1410 *
1411 * @returns Pointer to the mapping.
1412 * @param pPGM The PGM instance data.
1413 * @param iPdpt Which PD entry to map (0..3).
1414 */
1415PX86PDPAE pgmGstLazyMapPaePD(PPGMCPU pPGM, uint32_t iPdpt)
1416{
1417 PVM pVM = PGMCPU2VM(pPGM);
1418 pgmLock(pVM);
1419
1420 PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
1421 Assert(pGuestPDPT);
1422 Assert(pGuestPDPT->a[iPdpt].n.u1Present);
1423 RTGCPHYS GCPhys = pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK;
1424 bool const fChanged = pPGM->aGCPhysGstPaePDs[iPdpt] != GCPhys;
1425
1426 PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, GCPhys);
1427 if (RT_LIKELY(pPage))
1428 {
1429 int rc = VINF_SUCCESS;
1430 RTRCPTR RCPtr = NIL_RTRCPTR;
1431 RTHCPTR HCPtr = NIL_RTHCPTR;
1432#if !defined(IN_RC) && !defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1433 rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, &HCPtr);
1434 AssertRC(rc);
1435#endif
1436 if (RT_SUCCESS(rc) && fChanged)
1437 {
1438 RCPtr = (RTRCPTR)(RTRCUINTPTR)(pVM->pgm.s.GCPtrCR3Mapping + (1 + iPdpt) * PAGE_SIZE);
1439 rc = PGMMap(pVM, (RTRCUINTPTR)RCPtr, PGM_PAGE_GET_HCPHYS(pPage), PAGE_SIZE, 0);
1440 }
1441 if (RT_SUCCESS(rc))
1442 {
1443 pPGM->apGstPaePDsR3[iPdpt] = (R3PTRTYPE(PX86PDPAE))HCPtr;
1444# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1445 pPGM->apGstPaePDsR0[iPdpt] = (R0PTRTYPE(PX86PDPAE))HCPtr;
1446# endif
1447 if (fChanged)
1448 {
1449 pPGM->aGCPhysGstPaePDs[iPdpt] = GCPhys;
1450 pPGM->apGstPaePDsRC[iPdpt] = (RCPTRTYPE(PX86PDPAE))RCPtr;
1451 }
1452
1453 pgmUnlock(pVM);
1454 return pPGM->CTX_SUFF(apGstPaePDs)[iPdpt];
1455 }
1456 }
1457
1458 /* Invalid page or some failure, invalidate the entry. */
1459 pPGM->aGCPhysGstPaePDs[iPdpt] = NIL_RTGCPHYS;
1460 pPGM->apGstPaePDsR3[iPdpt] = 0;
1461# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1462 pPGM->apGstPaePDsR0[iPdpt] = 0;
1463# endif
1464 pPGM->apGstPaePDsRC[iPdpt] = 0;
1465
1466 pgmUnlock(pVM);
1467 return NULL;
1468}
1469#endif /* !VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
1470
1471
1472#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R3
1473/**
1474 * Performs the lazy mapping of the 32-bit guest PD.
1475 *
1476 * @returns Pointer to the mapping.
1477 * @param pPGM The PGM instance data.
1478 */
1479PX86PML4 pgmGstLazyMapPml4(PPGMCPU pPGM)
1480{
1481 Assert(!pPGM->CTX_SUFF(pGstAmd64Pml4));
1482 PVM pVM = PGMCPU2VM(pPGM);
1483 pgmLock(pVM);
1484
1485 PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, pPGM->GCPhysCR3);
1486 AssertReturn(pPage, NULL);
1487
1488 RTHCPTR HCPtrGuestCR3;
1489 int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, pPGM->GCPhysCR3 & X86_CR3_AMD64_PAGE_MASK, (void **)&HCPtrGuestCR3);
1490 AssertRCReturn(rc, NULL);
1491
1492 pPGM->pGstAmd64Pml4R3 = (R3PTRTYPE(PX86PML4))HCPtrGuestCR3;
1493# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1494 pPGM->pGstAmd64Pml4R0 = (R0PTRTYPE(PX86PML4))HCPtrGuestCR3;
1495# endif
1496
1497 pgmUnlock(pVM);
1498 return pPGM->CTX_SUFF(pGstAmd64Pml4);
1499}
1500#endif /* VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R3 */
1501
1502
1503/**
1504 * Gets the specified page directory pointer table entry.
1505 *
1506 * @returns PDP entry
1507 * @param pVCpu VMCPU handle.
1508 * @param iPdpt PDPT index
1509 */
1510VMMDECL(X86PDPE) PGMGstGetPaePDPtr(PVMCPU pVCpu, unsigned iPdpt)
1511{
1512 Assert(iPdpt <= 3);
1513 return pgmGstGetPaePDPTPtr(&pVCpu->pgm.s)->a[iPdpt & 3];
1514}
1515
1516
1517/**
1518 * Gets the current CR3 register value for the shadow memory context.
1519 * @returns CR3 value.
1520 * @param pVCpu VMCPU handle.
1521 */
1522VMMDECL(RTHCPHYS) PGMGetHyperCR3(PVMCPU pVCpu)
1523{
1524 PPGMPOOLPAGE pPoolPage = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
1525 AssertPtrReturn(pPoolPage, 0);
1526 return pPoolPage->Core.Key;
1527}
1528
1529
1530/**
1531 * Gets the current CR3 register value for the nested memory context.
1532 * @returns CR3 value.
1533 * @param pVCpu VMCPU handle.
1534 */
1535VMMDECL(RTHCPHYS) PGMGetNestedCR3(PVMCPU pVCpu, PGMMODE enmShadowMode)
1536{
1537 Assert(pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
1538 return pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->Core.Key;
1539}
1540
1541
1542/**
1543 * Gets the current CR3 register value for the HC intermediate memory context.
1544 * @returns CR3 value.
1545 * @param pVM The VM handle.
1546 */
1547VMMDECL(RTHCPHYS) PGMGetInterHCCR3(PVM pVM)
1548{
1549 switch (pVM->pgm.s.enmHostMode)
1550 {
1551 case SUPPAGINGMODE_32_BIT:
1552 case SUPPAGINGMODE_32_BIT_GLOBAL:
1553 return pVM->pgm.s.HCPhysInterPD;
1554
1555 case SUPPAGINGMODE_PAE:
1556 case SUPPAGINGMODE_PAE_GLOBAL:
1557 case SUPPAGINGMODE_PAE_NX:
1558 case SUPPAGINGMODE_PAE_GLOBAL_NX:
1559 return pVM->pgm.s.HCPhysInterPaePDPT;
1560
1561 case SUPPAGINGMODE_AMD64:
1562 case SUPPAGINGMODE_AMD64_GLOBAL:
1563 case SUPPAGINGMODE_AMD64_NX:
1564 case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1565 return pVM->pgm.s.HCPhysInterPaePDPT;
1566
1567 default:
1568 AssertMsgFailed(("enmHostMode=%d\n", pVM->pgm.s.enmHostMode));
1569 return ~0;
1570 }
1571}
1572
1573
1574/**
1575 * Gets the current CR3 register value for the RC intermediate memory context.
1576 * @returns CR3 value.
1577 * @param pVM The VM handle.
1578 * @param pVCpu VMCPU handle.
1579 */
1580VMMDECL(RTHCPHYS) PGMGetInterRCCR3(PVM pVM, PVMCPU pVCpu)
1581{
1582 switch (pVCpu->pgm.s.enmShadowMode)
1583 {
1584 case PGMMODE_32_BIT:
1585 return pVM->pgm.s.HCPhysInterPD;
1586
1587 case PGMMODE_PAE:
1588 case PGMMODE_PAE_NX:
1589 return pVM->pgm.s.HCPhysInterPaePDPT;
1590
1591 case PGMMODE_AMD64:
1592 case PGMMODE_AMD64_NX:
1593 return pVM->pgm.s.HCPhysInterPaePML4;
1594
1595 case PGMMODE_EPT:
1596 case PGMMODE_NESTED:
1597 return 0; /* not relevant */
1598
1599 default:
1600 AssertMsgFailed(("enmShadowMode=%d\n", pVCpu->pgm.s.enmShadowMode));
1601 return ~0;
1602 }
1603}
1604
1605
1606/**
1607 * Gets the CR3 register value for the 32-Bit intermediate memory context.
1608 * @returns CR3 value.
1609 * @param pVM The VM handle.
1610 */
1611VMMDECL(RTHCPHYS) PGMGetInter32BitCR3(PVM pVM)
1612{
1613 return pVM->pgm.s.HCPhysInterPD;
1614}
1615
1616
1617/**
1618 * Gets the CR3 register value for the PAE intermediate memory context.
1619 * @returns CR3 value.
1620 * @param pVM The VM handle.
1621 */
1622VMMDECL(RTHCPHYS) PGMGetInterPaeCR3(PVM pVM)
1623{
1624 return pVM->pgm.s.HCPhysInterPaePDPT;
1625}
1626
1627
1628/**
1629 * Gets the CR3 register value for the AMD64 intermediate memory context.
1630 * @returns CR3 value.
1631 * @param pVM The VM handle.
1632 */
1633VMMDECL(RTHCPHYS) PGMGetInterAmd64CR3(PVM pVM)
1634{
1635 return pVM->pgm.s.HCPhysInterPaePML4;
1636}
1637
1638
1639/**
1640 * Performs and schedules necessary updates following a CR3 load or reload.
1641 *
1642 * This will normally involve mapping the guest PD or nPDPT
1643 *
1644 * @returns VBox status code.
1645 * @retval VINF_PGM_SYNC_CR3 if monitoring requires a CR3 sync. This can
1646 * safely be ignored and overridden since the FF will be set too then.
1647 * @param pVM VM handle.
1648 * @param pVCpu VMCPU handle.
1649 * @param cr3 The new cr3.
1650 * @param fGlobal Indicates whether this is a global flush or not.
1651 */
1652VMMDECL(int) PGMFlushTLB(PVM pVM, PVMCPU pVCpu, uint64_t cr3, bool fGlobal)
1653{
1654 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_MID_Z(Stat,FlushTLB), a);
1655
1656 /*
1657 * Always flag the necessary updates; necessary for hardware acceleration
1658 */
1659 /** @todo optimize this, it shouldn't always be necessary. */
1660 VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
1661 if (fGlobal)
1662 VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
1663 LogFlow(("PGMFlushTLB: cr3=%RX64 OldCr3=%RX64 fGlobal=%d\n", cr3, pVCpu->pgm.s.GCPhysCR3, fGlobal));
1664
1665 /*
1666 * Remap the CR3 content and adjust the monitoring if CR3 was actually changed.
1667 */
1668 int rc = VINF_SUCCESS;
1669 RTGCPHYS GCPhysCR3;
1670 switch (pVCpu->pgm.s.enmGuestMode)
1671 {
1672 case PGMMODE_PAE:
1673 case PGMMODE_PAE_NX:
1674 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAE_PAGE_MASK);
1675 break;
1676 case PGMMODE_AMD64:
1677 case PGMMODE_AMD64_NX:
1678 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_AMD64_PAGE_MASK);
1679 break;
1680 default:
1681 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAGE_MASK);
1682 break;
1683 }
1684
1685 if (pVCpu->pgm.s.GCPhysCR3 != GCPhysCR3)
1686 {
1687 RTGCPHYS GCPhysOldCR3 = pVCpu->pgm.s.GCPhysCR3;
1688 pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3;
1689 rc = PGM_BTH_PFN(MapCR3, pVM)(pVM, pVCpu, GCPhysCR3);
1690 if (RT_LIKELY(rc == VINF_SUCCESS))
1691 {
1692 if (!pVM->pgm.s.fMappingsFixed)
1693 {
1694 pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
1695 }
1696 }
1697 else
1698 {
1699 AssertMsg(rc == VINF_PGM_SYNC_CR3, ("%Rrc\n", rc));
1700 Assert(VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL | VM_FF_PGM_SYNC_CR3));
1701 pVCpu->pgm.s.GCPhysCR3 = GCPhysOldCR3;
1702 pVCpu->pgm.s.fSyncFlags |= PGM_SYNC_MAP_CR3;
1703 if (!pVM->pgm.s.fMappingsFixed)
1704 pVCpu->pgm.s.fSyncFlags |= PGM_SYNC_MONITOR_CR3;
1705 }
1706
1707 if (fGlobal)
1708 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,FlushTLBNewCR3Global));
1709 else
1710 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,FlushTLBNewCR3));
1711 }
1712 else
1713 {
1714 /*
1715 * Check if we have a pending update of the CR3 monitoring.
1716 */
1717 if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
1718 {
1719 pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
1720 Assert(!pVM->pgm.s.fMappingsFixed);
1721 }
1722 if (fGlobal)
1723 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,FlushTLBSameCR3Global));
1724 else
1725 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,FlushTLBSameCR3));
1726 }
1727
1728 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,FlushTLB), a);
1729 return rc;
1730}
1731
1732
1733/**
1734 * Performs and schedules necessary updates following a CR3 load or reload when
1735 * using nested or extended paging.
1736 *
1737 * This API is an alterantive to PDMFlushTLB that avoids actually flushing the
1738 * TLB and triggering a SyncCR3.
1739 *
1740 * This will normally involve mapping the guest PD or nPDPT
1741 *
1742 * @returns VBox status code.
1743 * @retval VINF_SUCCESS.
1744 * @retval (If applied when not in nested mode: VINF_PGM_SYNC_CR3 if monitoring
1745 * requires a CR3 sync. This can safely be ignored and overridden since
1746 * the FF will be set too then.)
1747 * @param pVM VM handle.
1748 * @param pVCpu VMCPU handle.
1749 * @param cr3 The new cr3.
1750 */
1751VMMDECL(int) PGMUpdateCR3(PVM pVM, PVMCPU pVCpu, uint64_t cr3)
1752{
1753 LogFlow(("PGMUpdateCR3: cr3=%RX64 OldCr3=%RX64\n", cr3, pVCpu->pgm.s.GCPhysCR3));
1754
1755 /* We assume we're only called in nested paging mode. */
1756 Assert(pVM->pgm.s.fMappingsFixed);
1757 Assert(!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3));
1758 Assert(HWACCMIsNestedPagingActive(pVM) || pVCpu->pgm.s.enmShadowMode == PGMMODE_EPT);
1759
1760 /*
1761 * Remap the CR3 content and adjust the monitoring if CR3 was actually changed.
1762 */
1763 int rc = VINF_SUCCESS;
1764 RTGCPHYS GCPhysCR3;
1765 switch (pVCpu->pgm.s.enmGuestMode)
1766 {
1767 case PGMMODE_PAE:
1768 case PGMMODE_PAE_NX:
1769 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAE_PAGE_MASK);
1770 break;
1771 case PGMMODE_AMD64:
1772 case PGMMODE_AMD64_NX:
1773 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_AMD64_PAGE_MASK);
1774 break;
1775 default:
1776 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAGE_MASK);
1777 break;
1778 }
1779 if (pVCpu->pgm.s.GCPhysCR3 != GCPhysCR3)
1780 {
1781 pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3;
1782 rc = PGM_BTH_PFN(MapCR3, pVM)(pVM, pVCpu, GCPhysCR3);
1783 AssertRCSuccess(rc); /* Assumes VINF_PGM_SYNC_CR3 doesn't apply to nested paging. */ /** @todo this isn't true for the mac, but we need hw to test/fix this. */
1784 }
1785 return rc;
1786}
1787
1788
1789/**
1790 * Synchronize the paging structures.
1791 *
1792 * This function is called in response to the VM_FF_PGM_SYNC_CR3 and
1793 * VM_FF_PGM_SYNC_CR3_NONGLOBAL. Those two force action flags are set
1794 * in several places, most importantly whenever the CR3 is loaded.
1795 *
1796 * @returns VBox status code.
1797 * @param pVM The virtual machine.
1798 * @param pVCpu VMCPU handle.
1799 * @param cr0 Guest context CR0 register
1800 * @param cr3 Guest context CR3 register
1801 * @param cr4 Guest context CR4 register
1802 * @param fGlobal Including global page directories or not
1803 */
1804VMMDECL(int) PGMSyncCR3(PVM pVM, PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
1805{
1806 int rc;
1807
1808 /*
1809 * We might be called when we shouldn't.
1810 *
1811 * The mode switching will ensure that the PD is resynced
1812 * after every mode switch. So, if we find ourselves here
1813 * when in protected or real mode we can safely disable the
1814 * FF and return immediately.
1815 */
1816 if (pVCpu->pgm.s.enmGuestMode <= PGMMODE_PROTECTED)
1817 {
1818 Assert((cr0 & (X86_CR0_PG | X86_CR0_PE)) != (X86_CR0_PG | X86_CR0_PE));
1819 VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3);
1820 VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
1821 return VINF_SUCCESS;
1822 }
1823
1824 /* If global pages are not supported, then all flushes are global. */
1825 if (!(cr4 & X86_CR4_PGE))
1826 fGlobal = true;
1827 LogFlow(("PGMSyncCR3: cr0=%RX64 cr3=%RX64 cr4=%RX64 fGlobal=%d[%d,%d]\n", cr0, cr3, cr4, fGlobal,
1828 VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3), VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL)));
1829
1830#ifdef PGMPOOL_WITH_MONITORING
1831 /*
1832 * The pool may have pending stuff and even require a return to ring-3 to
1833 * clear the whole thing.
1834 */
1835 rc = pgmPoolSyncCR3(pVM);
1836 if (rc != VINF_SUCCESS)
1837 return rc;
1838#endif
1839
1840 /*
1841 * Check if we need to finish an aborted MapCR3 call (see PGMFlushTLB).
1842 * This should be done before SyncCR3.
1843 */
1844 if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MAP_CR3)
1845 {
1846 pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MAP_CR3;
1847
1848 RTGCPHYS GCPhysCR3Old = pVCpu->pgm.s.GCPhysCR3;
1849 RTGCPHYS GCPhysCR3;
1850 switch (pVCpu->pgm.s.enmGuestMode)
1851 {
1852 case PGMMODE_PAE:
1853 case PGMMODE_PAE_NX:
1854 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAE_PAGE_MASK);
1855 break;
1856 case PGMMODE_AMD64:
1857 case PGMMODE_AMD64_NX:
1858 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_AMD64_PAGE_MASK);
1859 break;
1860 default:
1861 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAGE_MASK);
1862 break;
1863 }
1864
1865 if (pVCpu->pgm.s.GCPhysCR3 != GCPhysCR3)
1866 {
1867 pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3;
1868 rc = PGM_BTH_PFN(MapCR3, pVM)(pVM, pVCpu, GCPhysCR3);
1869 }
1870#ifdef IN_RING3
1871 if (rc == VINF_PGM_SYNC_CR3)
1872 rc = pgmPoolSyncCR3(pVM);
1873#else
1874 if (rc == VINF_PGM_SYNC_CR3)
1875 {
1876 pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3Old;
1877 return rc;
1878 }
1879#endif
1880 AssertRCReturn(rc, rc);
1881 AssertRCSuccessReturn(rc, VERR_INTERNAL_ERROR);
1882 }
1883
1884 /*
1885 * Let the 'Bth' function do the work and we'll just keep track of the flags.
1886 */
1887 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncCR3), a);
1888 rc = PGM_BTH_PFN(SyncCR3, pVM)(pVM, pVCpu, cr0, cr3, cr4, fGlobal);
1889 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncCR3), a);
1890 AssertMsg(rc == VINF_SUCCESS || rc == VINF_PGM_SYNC_CR3 || RT_FAILURE(rc), ("rc=%Rrc\n", rc));
1891 if (rc == VINF_SUCCESS)
1892 {
1893 if (!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS))
1894 {
1895 VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3);
1896 VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
1897 }
1898
1899 /*
1900 * Check if we have a pending update of the CR3 monitoring.
1901 */
1902 if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
1903 {
1904 pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
1905 Assert(!pVM->pgm.s.fMappingsFixed);
1906 }
1907 }
1908
1909 /*
1910 * Now flush the CR3 (guest context).
1911 */
1912 if (rc == VINF_SUCCESS)
1913 PGM_INVL_GUEST_TLBS();
1914 return rc;
1915}
1916
1917
1918/**
1919 * Called whenever CR0 or CR4 in a way which may change
1920 * the paging mode.
1921 *
1922 * @returns VBox status code, with the following informational code for
1923 * VM scheduling.
1924 * @retval VINF_SUCCESS if the was no change, or it was successfully dealt with.
1925 * @retval VINF_PGM_CHANGE_MODE if we're in RC or R0 and the mode changes.
1926 * (I.e. not in R3.)
1927 * @retval VINF_EM_SUSPEND or VINF_EM_OFF on a fatal runtime error. (R3 only)
1928 *
1929 * @param pVM VM handle.
1930 * @param pVCpu VMCPU handle.
1931 * @param cr0 The new cr0.
1932 * @param cr4 The new cr4.
1933 * @param efer The new extended feature enable register.
1934 */
1935VMMDECL(int) PGMChangeMode(PVM pVM, PVMCPU pVCpu, uint64_t cr0, uint64_t cr4, uint64_t efer)
1936{
1937 PGMMODE enmGuestMode;
1938
1939 /*
1940 * Calc the new guest mode.
1941 */
1942 if (!(cr0 & X86_CR0_PE))
1943 enmGuestMode = PGMMODE_REAL;
1944 else if (!(cr0 & X86_CR0_PG))
1945 enmGuestMode = PGMMODE_PROTECTED;
1946 else if (!(cr4 & X86_CR4_PAE))
1947 enmGuestMode = PGMMODE_32_BIT;
1948 else if (!(efer & MSR_K6_EFER_LME))
1949 {
1950 if (!(efer & MSR_K6_EFER_NXE))
1951 enmGuestMode = PGMMODE_PAE;
1952 else
1953 enmGuestMode = PGMMODE_PAE_NX;
1954 }
1955 else
1956 {
1957 if (!(efer & MSR_K6_EFER_NXE))
1958 enmGuestMode = PGMMODE_AMD64;
1959 else
1960 enmGuestMode = PGMMODE_AMD64_NX;
1961 }
1962
1963 /*
1964 * Did it change?
1965 */
1966 if (pVCpu->pgm.s.enmGuestMode == enmGuestMode)
1967 return VINF_SUCCESS;
1968
1969 /* Flush the TLB */
1970 PGM_INVL_GUEST_TLBS();
1971
1972#ifdef IN_RING3
1973 return PGMR3ChangeMode(pVM, pVCpu, enmGuestMode);
1974#else
1975 LogFlow(("PGMChangeMode: returns VINF_PGM_CHANGE_MODE.\n"));
1976 return VINF_PGM_CHANGE_MODE;
1977#endif
1978}
1979
1980
1981/**
1982 * Gets the current guest paging mode.
1983 *
1984 * If you just need the CPU mode (real/protected/long), use CPUMGetGuestMode().
1985 *
1986 * @returns The current paging mode.
1987 * @param pVCpu VMCPU handle.
1988 */
1989VMMDECL(PGMMODE) PGMGetGuestMode(PVMCPU pVCpu)
1990{
1991 return pVCpu->pgm.s.enmGuestMode;
1992}
1993
1994
1995/**
1996 * Gets the current shadow paging mode.
1997 *
1998 * @returns The current paging mode.
1999 * @param pVCpu VMCPU handle.
2000 */
2001VMMDECL(PGMMODE) PGMGetShadowMode(PVMCPU pVCpu)
2002{
2003 return pVCpu->pgm.s.enmShadowMode;
2004}
2005
2006/**
2007 * Gets the current host paging mode.
2008 *
2009 * @returns The current paging mode.
2010 * @param pVM The VM handle.
2011 */
2012VMMDECL(PGMMODE) PGMGetHostMode(PVM pVM)
2013{
2014 switch (pVM->pgm.s.enmHostMode)
2015 {
2016 case SUPPAGINGMODE_32_BIT:
2017 case SUPPAGINGMODE_32_BIT_GLOBAL:
2018 return PGMMODE_32_BIT;
2019
2020 case SUPPAGINGMODE_PAE:
2021 case SUPPAGINGMODE_PAE_GLOBAL:
2022 return PGMMODE_PAE;
2023
2024 case SUPPAGINGMODE_PAE_NX:
2025 case SUPPAGINGMODE_PAE_GLOBAL_NX:
2026 return PGMMODE_PAE_NX;
2027
2028 case SUPPAGINGMODE_AMD64:
2029 case SUPPAGINGMODE_AMD64_GLOBAL:
2030 return PGMMODE_AMD64;
2031
2032 case SUPPAGINGMODE_AMD64_NX:
2033 case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2034 return PGMMODE_AMD64_NX;
2035
2036 default: AssertMsgFailed(("enmHostMode=%d\n", pVM->pgm.s.enmHostMode)); break;
2037 }
2038
2039 return PGMMODE_INVALID;
2040}
2041
2042
2043/**
2044 * Get mode name.
2045 *
2046 * @returns read-only name string.
2047 * @param enmMode The mode which name is desired.
2048 */
2049VMMDECL(const char *) PGMGetModeName(PGMMODE enmMode)
2050{
2051 switch (enmMode)
2052 {
2053 case PGMMODE_REAL: return "Real";
2054 case PGMMODE_PROTECTED: return "Protected";
2055 case PGMMODE_32_BIT: return "32-bit";
2056 case PGMMODE_PAE: return "PAE";
2057 case PGMMODE_PAE_NX: return "PAE+NX";
2058 case PGMMODE_AMD64: return "AMD64";
2059 case PGMMODE_AMD64_NX: return "AMD64+NX";
2060 case PGMMODE_NESTED: return "Nested";
2061 case PGMMODE_EPT: return "EPT";
2062 default: return "unknown mode value";
2063 }
2064}
2065
2066
2067/**
2068 * Acquire the PGM lock.
2069 *
2070 * @returns VBox status code
2071 * @param pVM The VM to operate on.
2072 */
2073int pgmLock(PVM pVM)
2074{
2075 int rc = PDMCritSectEnter(&pVM->pgm.s.CritSect, VERR_SEM_BUSY);
2076#ifdef IN_RC
2077 if (rc == VERR_SEM_BUSY)
2078 rc = VMMGCCallHost(pVM, VMMCALLHOST_PGM_LOCK, 0);
2079#elif defined(IN_RING0)
2080 if (rc == VERR_SEM_BUSY)
2081 rc = VMMR0CallHost(pVM, VMMCALLHOST_PGM_LOCK, 0);
2082#endif
2083 AssertMsg(rc == VINF_SUCCESS, ("%Rrc\n", rc));
2084 return rc;
2085}
2086
2087
2088/**
2089 * Release the PGM lock.
2090 *
2091 * @returns VBox status code
2092 * @param pVM The VM to operate on.
2093 */
2094void pgmUnlock(PVM pVM)
2095{
2096 PDMCritSectLeave(&pVM->pgm.s.CritSect);
2097}
2098
2099#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2100
2101/**
2102 * Temporarily maps one guest page specified by GC physical address.
2103 * These pages must have a physical mapping in HC, i.e. they cannot be MMIO pages.
2104 *
2105 * Be WARNED that the dynamic page mapping area is small, 8 pages, thus the space is
2106 * reused after 8 mappings (or perhaps a few more if you score with the cache).
2107 *
2108 * @returns VBox status.
2109 * @param pVM VM handle.
2110 * @param GCPhys GC Physical address of the page.
2111 * @param ppv Where to store the address of the mapping.
2112 */
2113VMMDECL(int) PGMDynMapGCPage(PVM pVM, RTGCPHYS GCPhys, void **ppv)
2114{
2115 AssertMsg(!(GCPhys & PAGE_OFFSET_MASK), ("GCPhys=%RGp\n", GCPhys));
2116
2117 /*
2118 * Get the ram range.
2119 */
2120 PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
2121 while (pRam && GCPhys - pRam->GCPhys >= pRam->cb)
2122 pRam = pRam->CTX_SUFF(pNext);
2123 if (!pRam)
2124 {
2125 AssertMsgFailed(("Invalid physical address %RGp!\n", GCPhys));
2126 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2127 }
2128
2129 /*
2130 * Pass it on to PGMDynMapHCPage.
2131 */
2132 RTHCPHYS HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT]);
2133 //Log(("PGMDynMapGCPage: GCPhys=%RGp HCPhys=%RHp\n", GCPhys, HCPhys));
2134#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2135 pgmR0DynMapHCPageInlined(&pVM->pgm.s, HCPhys, ppv);
2136#else
2137 PGMDynMapHCPage(pVM, HCPhys, ppv);
2138#endif
2139 return VINF_SUCCESS;
2140}
2141
2142
2143/**
2144 * Temporarily maps one guest page specified by unaligned GC physical address.
2145 * These pages must have a physical mapping in HC, i.e. they cannot be MMIO pages.
2146 *
2147 * Be WARNED that the dynamic page mapping area is small, 8 pages, thus the space is
2148 * reused after 8 mappings (or perhaps a few more if you score with the cache).
2149 *
2150 * The caller is aware that only the speicifed page is mapped and that really bad things
2151 * will happen if writing beyond the page!
2152 *
2153 * @returns VBox status.
2154 * @param pVM VM handle.
2155 * @param GCPhys GC Physical address within the page to be mapped.
2156 * @param ppv Where to store the address of the mapping address corresponding to GCPhys.
2157 */
2158VMMDECL(int) PGMDynMapGCPageOff(PVM pVM, RTGCPHYS GCPhys, void **ppv)
2159{
2160 /*
2161 * Get the ram range.
2162 */
2163 PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
2164 while (pRam && GCPhys - pRam->GCPhys >= pRam->cb)
2165 pRam = pRam->CTX_SUFF(pNext);
2166 if (!pRam)
2167 {
2168 AssertMsgFailed(("Invalid physical address %RGp!\n", GCPhys));
2169 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2170 }
2171
2172 /*
2173 * Pass it on to PGMDynMapHCPage.
2174 */
2175 RTHCPHYS HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT]);
2176#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2177 pgmR0DynMapHCPageInlined(&pVM->pgm.s, HCPhys, ppv);
2178#else
2179 PGMDynMapHCPage(pVM, HCPhys, ppv);
2180#endif
2181 *ppv = (void *)((uintptr_t)*ppv | (GCPhys & PAGE_OFFSET_MASK));
2182 return VINF_SUCCESS;
2183}
2184
2185# ifdef IN_RC
2186
2187/**
2188 * Temporarily maps one host page specified by HC physical address.
2189 *
2190 * Be WARNED that the dynamic page mapping area is small, 16 pages, thus the space is
2191 * reused after 16 mappings (or perhaps a few more if you score with the cache).
2192 *
2193 * @returns VINF_SUCCESS, will bail out to ring-3 on failure.
2194 * @param pVM VM handle.
2195 * @param HCPhys HC Physical address of the page.
2196 * @param ppv Where to store the address of the mapping. This is the
2197 * address of the PAGE not the exact address corresponding
2198 * to HCPhys. Use PGMDynMapHCPageOff if you care for the
2199 * page offset.
2200 */
2201VMMDECL(int) PGMDynMapHCPage(PVM pVM, RTHCPHYS HCPhys, void **ppv)
2202{
2203 AssertMsg(!(HCPhys & PAGE_OFFSET_MASK), ("HCPhys=%RHp\n", HCPhys));
2204
2205 /*
2206 * Check the cache.
2207 */
2208 register unsigned iCache;
2209 for (iCache = 0;iCache < RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache);iCache++)
2210 {
2211 static const uint8_t au8Trans[MM_HYPER_DYNAMIC_SIZE >> PAGE_SHIFT][RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache)] =
2212 {
2213 { 0, 9, 10, 11, 12, 13, 14, 15},
2214 { 0, 1, 10, 11, 12, 13, 14, 15},
2215 { 0, 1, 2, 11, 12, 13, 14, 15},
2216 { 0, 1, 2, 3, 12, 13, 14, 15},
2217 { 0, 1, 2, 3, 4, 13, 14, 15},
2218 { 0, 1, 2, 3, 4, 5, 14, 15},
2219 { 0, 1, 2, 3, 4, 5, 6, 15},
2220 { 0, 1, 2, 3, 4, 5, 6, 7},
2221 { 8, 1, 2, 3, 4, 5, 6, 7},
2222 { 8, 9, 2, 3, 4, 5, 6, 7},
2223 { 8, 9, 10, 3, 4, 5, 6, 7},
2224 { 8, 9, 10, 11, 4, 5, 6, 7},
2225 { 8, 9, 10, 11, 12, 5, 6, 7},
2226 { 8, 9, 10, 11, 12, 13, 6, 7},
2227 { 8, 9, 10, 11, 12, 13, 14, 7},
2228 { 8, 9, 10, 11, 12, 13, 14, 15},
2229 };
2230 AssertCompile(RT_ELEMENTS(au8Trans) == 16);
2231 AssertCompile(RT_ELEMENTS(au8Trans[0]) == 8);
2232
2233 if (pVM->pgm.s.aHCPhysDynPageMapCache[iCache] == HCPhys)
2234 {
2235 int iPage = au8Trans[pVM->pgm.s.iDynPageMapLast][iCache];
2236
2237 /* The cache can get out of sync with locked entries. (10 locked, 2 overwrites its cache position, last = 11, lookup 2 -> page 10 instead of 2) */
2238 if ((pVM->pgm.s.paDynPageMap32BitPTEsGC[iPage].u & X86_PTE_PG_MASK) == HCPhys)
2239 {
2240 void *pv = pVM->pgm.s.pbDynPageMapBaseGC + (iPage << PAGE_SHIFT);
2241 *ppv = pv;
2242 STAM_COUNTER_INC(&pVM->pgm.s.StatRCDynMapCacheHits);
2243 Log4(("PGMGCDynMapHCPage: HCPhys=%RHp pv=%p iPage=%d iCache=%d\n", HCPhys, pv, iPage, iCache));
2244 return VINF_SUCCESS;
2245 }
2246 else
2247 LogFlow(("Out of sync entry %d\n", iPage));
2248 }
2249 }
2250 AssertCompile(RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache) == 8);
2251 AssertCompile((MM_HYPER_DYNAMIC_SIZE >> PAGE_SHIFT) == 16);
2252 STAM_COUNTER_INC(&pVM->pgm.s.StatRCDynMapCacheMisses);
2253
2254 /*
2255 * Update the page tables.
2256 */
2257 register unsigned iPage = pVM->pgm.s.iDynPageMapLast;
2258 unsigned i;
2259 for (i=0;i<(MM_HYPER_DYNAMIC_SIZE >> PAGE_SHIFT);i++)
2260 {
2261 pVM->pgm.s.iDynPageMapLast = iPage = (iPage + 1) & ((MM_HYPER_DYNAMIC_SIZE >> PAGE_SHIFT) - 1);
2262 if (!pVM->pgm.s.aLockedDynPageMapCache[iPage])
2263 break;
2264 iPage++;
2265 }
2266 AssertRelease(i != (MM_HYPER_DYNAMIC_SIZE >> PAGE_SHIFT));
2267
2268 pVM->pgm.s.aHCPhysDynPageMapCache[iPage & (RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache) - 1)] = HCPhys;
2269 pVM->pgm.s.paDynPageMap32BitPTEsGC[iPage].u = (uint32_t)HCPhys | X86_PTE_P | X86_PTE_A | X86_PTE_D;
2270 pVM->pgm.s.paDynPageMapPaePTEsGC[iPage].u = HCPhys | X86_PTE_P | X86_PTE_A | X86_PTE_D;
2271 pVM->pgm.s.aLockedDynPageMapCache[iPage] = 0;
2272
2273 void *pv = pVM->pgm.s.pbDynPageMapBaseGC + (iPage << PAGE_SHIFT);
2274 *ppv = pv;
2275 ASMInvalidatePage(pv);
2276 Log4(("PGMGCDynMapHCPage: HCPhys=%RHp pv=%p iPage=%d\n", HCPhys, pv, iPage));
2277 return VINF_SUCCESS;
2278}
2279
2280
2281/**
2282 * Temporarily lock a dynamic page to prevent it from being reused.
2283 *
2284 * @param pVM VM handle.
2285 * @param GCPage GC address of page
2286 */
2287VMMDECL(void) PGMDynLockHCPage(PVM pVM, RCPTRTYPE(uint8_t *) GCPage)
2288{
2289 unsigned iPage;
2290
2291 Assert(GCPage >= pVM->pgm.s.pbDynPageMapBaseGC && GCPage < (pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE));
2292 iPage = ((uintptr_t)(GCPage - pVM->pgm.s.pbDynPageMapBaseGC)) >> PAGE_SHIFT;
2293 ASMAtomicIncU32(&pVM->pgm.s.aLockedDynPageMapCache[iPage]);
2294 Log4(("PGMDynLockHCPage %RRv iPage=%d\n", GCPage, iPage));
2295}
2296
2297
2298/**
2299 * Unlock a dynamic page
2300 *
2301 * @param pVM VM handle.
2302 * @param GCPage GC address of page
2303 */
2304VMMDECL(void) PGMDynUnlockHCPage(PVM pVM, RCPTRTYPE(uint8_t *) GCPage)
2305{
2306 unsigned iPage;
2307
2308 AssertCompile(RT_ELEMENTS(pVM->pgm.s.aLockedDynPageMapCache) == 2* RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache));
2309 AssertCompileMemberSize(VM, pgm.s.aLockedDynPageMapCache, sizeof(uint32_t) * (MM_HYPER_DYNAMIC_SIZE >> (PAGE_SHIFT)));
2310
2311 Assert(GCPage >= pVM->pgm.s.pbDynPageMapBaseGC && GCPage < (pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE));
2312 iPage = ((uintptr_t)(GCPage - pVM->pgm.s.pbDynPageMapBaseGC)) >> PAGE_SHIFT;
2313 Assert(pVM->pgm.s.aLockedDynPageMapCache[iPage]);
2314 ASMAtomicDecU32(&pVM->pgm.s.aLockedDynPageMapCache[iPage]);
2315 Log4(("PGMDynUnlockHCPage %RRv iPage=%d\n", GCPage, iPage));
2316}
2317
2318
2319# ifdef VBOX_STRICT
2320/**
2321 * Check for lock leaks.
2322 *
2323 * @param pVM VM handle.
2324 */
2325VMMDECL(void) PGMDynCheckLocks(PVM pVM)
2326{
2327 for (unsigned i=0;i<RT_ELEMENTS(pVM->pgm.s.aLockedDynPageMapCache);i++)
2328 Assert(!pVM->pgm.s.aLockedDynPageMapCache[i]);
2329}
2330# endif /* VBOX_STRICT */
2331
2332# endif /* IN_RC */
2333#endif /* IN_RC || VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
2334
2335#if !defined(IN_R0) || defined(LOG_ENABLED)
2336
2337/** Format handler for PGMPAGE.
2338 * @copydoc FNRTSTRFORMATTYPE */
2339static DECLCALLBACK(size_t) pgmFormatTypeHandlerPage(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
2340 const char *pszType, void const *pvValue,
2341 int cchWidth, int cchPrecision, unsigned fFlags,
2342 void *pvUser)
2343{
2344 size_t cch;
2345 PCPGMPAGE pPage = (PCPGMPAGE)pvValue;
2346 if (VALID_PTR(pPage))
2347 {
2348 char szTmp[64+80];
2349
2350 cch = 0;
2351
2352 /* The single char state stuff. */
2353 static const char s_achPageStates[4] = { 'Z', 'A', 'W', 'S' };
2354 szTmp[cch++] = s_achPageStates[PGM_PAGE_GET_STATE(pPage)];
2355
2356#define IS_PART_INCLUDED(lvl) ( !(fFlags & RTSTR_F_PRECISION) || cchPrecision == (lvl) || cchPrecision >= (lvl)+10 )
2357 if (IS_PART_INCLUDED(5))
2358 {
2359 static const char s_achHandlerStates[4] = { '-', 't', 'w', 'a' };
2360 szTmp[cch++] = s_achHandlerStates[PGM_PAGE_GET_HNDL_PHYS_STATE(pPage)];
2361 szTmp[cch++] = s_achHandlerStates[PGM_PAGE_GET_HNDL_VIRT_STATE(pPage)];
2362 }
2363
2364 /* The type. */
2365 if (IS_PART_INCLUDED(4))
2366 {
2367 szTmp[cch++] = ':';
2368 static const char s_achPageTypes[8][4] = { "INV", "RAM", "MI2", "M2A", "SHA", "ROM", "MIO", "BAD" };
2369 szTmp[cch++] = s_achPageTypes[PGM_PAGE_GET_TYPE(pPage)][0];
2370 szTmp[cch++] = s_achPageTypes[PGM_PAGE_GET_TYPE(pPage)][1];
2371 szTmp[cch++] = s_achPageTypes[PGM_PAGE_GET_TYPE(pPage)][2];
2372 }
2373
2374 /* The numbers. */
2375 if (IS_PART_INCLUDED(3))
2376 {
2377 szTmp[cch++] = ':';
2378 cch += RTStrFormatNumber(&szTmp[cch], PGM_PAGE_GET_HCPHYS(pPage), 16, 12, 0, RTSTR_F_ZEROPAD | RTSTR_F_64BIT);
2379 }
2380
2381 if (IS_PART_INCLUDED(2))
2382 {
2383 szTmp[cch++] = ':';
2384 cch += RTStrFormatNumber(&szTmp[cch], PGM_PAGE_GET_PAGEID(pPage), 16, 7, 0, RTSTR_F_ZEROPAD | RTSTR_F_32BIT);
2385 }
2386
2387 if (IS_PART_INCLUDED(6))
2388 {
2389 szTmp[cch++] = ':';
2390 static const char s_achRefs[4] = { '-', 'U', '!', 'L' };
2391 szTmp[cch++] = s_achRefs[PGM_PAGE_GET_TD_CREFS(pPage)];
2392 cch += RTStrFormatNumber(&szTmp[cch], PGM_PAGE_GET_TD_IDX(pPage), 16, 4, 0, RTSTR_F_ZEROPAD | RTSTR_F_16BIT);
2393 }
2394#undef IS_PART_INCLUDED
2395
2396 cch = pfnOutput(pvArgOutput, szTmp, cch);
2397 }
2398 else
2399 cch = pfnOutput(pvArgOutput, "<bad-pgmpage-ptr>", sizeof("<bad-pgmpage-ptr>") - 1);
2400 return cch;
2401}
2402
2403
2404/** Format handler for PGMRAMRANGE.
2405 * @copydoc FNRTSTRFORMATTYPE */
2406static DECLCALLBACK(size_t) pgmFormatTypeHandlerRamRange(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
2407 const char *pszType, void const *pvValue,
2408 int cchWidth, int cchPrecision, unsigned fFlags,
2409 void *pvUser)
2410{
2411 size_t cch;
2412 PGMRAMRANGE const *pRam = (PGMRAMRANGE const *)pvValue;
2413 if (VALID_PTR(pRam))
2414 {
2415 char szTmp[80];
2416 cch = RTStrPrintf(szTmp, sizeof(szTmp), "%RGp-%RGp", pRam->GCPhys, pRam->GCPhysLast);
2417 cch = pfnOutput(pvArgOutput, szTmp, cch);
2418 }
2419 else
2420 cch = pfnOutput(pvArgOutput, "<bad-pgmramrange-ptr>", sizeof("<bad-pgmramrange-ptr>") - 1);
2421 return cch;
2422}
2423
2424/** Format type andlers to be registered/deregistered. */
2425static const struct
2426{
2427 char szType[24];
2428 PFNRTSTRFORMATTYPE pfnHandler;
2429} g_aPgmFormatTypes[] =
2430{
2431 { "pgmpage", pgmFormatTypeHandlerPage },
2432 { "pgmramrange", pgmFormatTypeHandlerRamRange }
2433};
2434
2435#endif /* !IN_R0 || LOG_ENABLED */
2436
2437
2438/**
2439 * Registers the global string format types.
2440 *
2441 * This should be called at module load time or in some other manner that ensure
2442 * that it's called exactly one time.
2443 *
2444 * @returns IPRT status code on RTStrFormatTypeRegister failure.
2445 */
2446VMMDECL(int) PGMRegisterStringFormatTypes(void)
2447{
2448#if !defined(IN_R0) || defined(LOG_ENABLED)
2449 int rc = VINF_SUCCESS;
2450 unsigned i;
2451 for (i = 0; RT_SUCCESS(rc) && i < RT_ELEMENTS(g_aPgmFormatTypes); i++)
2452 {
2453 rc = RTStrFormatTypeRegister(g_aPgmFormatTypes[i].szType, g_aPgmFormatTypes[i].pfnHandler, NULL);
2454# ifdef IN_RING0
2455 if (rc == VERR_ALREADY_EXISTS)
2456 {
2457 /* in case of cleanup failure in ring-0 */
2458 RTStrFormatTypeDeregister(g_aPgmFormatTypes[i].szType);
2459 rc = RTStrFormatTypeRegister(g_aPgmFormatTypes[i].szType, g_aPgmFormatTypes[i].pfnHandler, NULL);
2460 }
2461# endif
2462 }
2463 if (RT_FAILURE(rc))
2464 while (i-- > 0)
2465 RTStrFormatTypeDeregister(g_aPgmFormatTypes[i].szType);
2466
2467 return rc;
2468#else
2469 return VINF_SUCCESS;
2470#endif
2471}
2472
2473
2474/**
2475 * Deregisters the global string format types.
2476 *
2477 * This should be called at module unload time or in some other manner that
2478 * ensure that it's called exactly one time.
2479 */
2480VMMDECL(void) PGMDeregisterStringFormatTypes(void)
2481{
2482#if !defined(IN_R0) || defined(LOG_ENABLED)
2483 for (unsigned i = 0; i < RT_ELEMENTS(g_aPgmFormatTypes); i++)
2484 RTStrFormatTypeDeregister(g_aPgmFormatTypes[i].szType);
2485#endif
2486}
2487
2488#ifdef VBOX_STRICT
2489
2490/**
2491 * Asserts that there are no mapping conflicts.
2492 *
2493 * @returns Number of conflicts.
2494 * @param pVM The VM Handle.
2495 */
2496VMMDECL(unsigned) PGMAssertNoMappingConflicts(PVM pVM)
2497{
2498 unsigned cErrors = 0;
2499
2500 /* Only applies to raw mode -> 1 VPCU */
2501 Assert(pVM->cCPUs == 1);
2502 PVMCPU pVCpu = &pVM->aCpus[0];
2503
2504 /*
2505 * Check for mapping conflicts.
2506 */
2507 for (PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
2508 pMapping;
2509 pMapping = pMapping->CTX_SUFF(pNext))
2510 {
2511 /** @todo This is slow and should be optimized, but since it's just assertions I don't care now. */
2512 for (RTGCPTR GCPtr = pMapping->GCPtr;
2513 GCPtr <= pMapping->GCPtrLast;
2514 GCPtr += PAGE_SIZE)
2515 {
2516 int rc = PGMGstGetPage(pVM, pVCpu, (RTGCPTR)GCPtr, NULL, NULL);
2517 if (rc != VERR_PAGE_TABLE_NOT_PRESENT)
2518 {
2519 AssertMsgFailed(("Conflict at %RGv with %s\n", GCPtr, R3STRING(pMapping->pszDesc)));
2520 cErrors++;
2521 break;
2522 }
2523 }
2524 }
2525
2526 return cErrors;
2527}
2528
2529
2530/**
2531 * Asserts that everything related to the guest CR3 is correctly shadowed.
2532 *
2533 * This will call PGMAssertNoMappingConflicts() and PGMAssertHandlerAndFlagsInSync(),
2534 * and assert the correctness of the guest CR3 mapping before asserting that the
2535 * shadow page tables is in sync with the guest page tables.
2536 *
2537 * @returns Number of conflicts.
2538 * @param pVM The VM Handle.
2539 * @param pVCpu VMCPU handle.
2540 * @param cr3 The current guest CR3 register value.
2541 * @param cr4 The current guest CR4 register value.
2542 */
2543VMMDECL(unsigned) PGMAssertCR3(PVM pVM, PVMCPU pVCpu, uint64_t cr3, uint64_t cr4)
2544{
2545 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncCR3), a);
2546 unsigned cErrors = PGM_BTH_PFN(AssertCR3, pVM)(pVM, pVCpu, cr3, cr4, 0, ~(RTGCPTR)0);
2547 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncCR3), a);
2548 return cErrors;
2549}
2550
2551#endif /* VBOX_STRICT */
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