VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAll.cpp@ 45870

Last change on this file since 45870 was 45826, checked in by vboxsync, 12 years ago

PGM: Extended the WP0+RO+US hack to include big pages and adjusted some assertions to handle the hack.
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  • Property svn:keywords set to Id Revision
File size: 90.8 KB
Line 
1/* $Id: PGMAll.cpp 45826 2013-04-30 00:14:47Z vboxsync $ */
2/** @file
3 * PGM - Page Manager and Monitor - All context code.
4 */
5
6/*
7 * Copyright (C) 2006-2012 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/*******************************************************************************
19* Header Files *
20*******************************************************************************/
21#define LOG_GROUP LOG_GROUP_PGM
22#include <VBox/vmm/pgm.h>
23#include <VBox/vmm/cpum.h>
24#include <VBox/vmm/selm.h>
25#include <VBox/vmm/iom.h>
26#include <VBox/sup.h>
27#include <VBox/vmm/mm.h>
28#include <VBox/vmm/stam.h>
29#include <VBox/vmm/csam.h>
30#include <VBox/vmm/patm.h>
31#include <VBox/vmm/trpm.h>
32#ifdef VBOX_WITH_REM
33# include <VBox/vmm/rem.h>
34#endif
35#include <VBox/vmm/em.h>
36#include <VBox/vmm/hm.h>
37#include <VBox/vmm/hm_vmx.h>
38#include "PGMInternal.h"
39#include <VBox/vmm/vm.h>
40#include "PGMInline.h"
41#include <iprt/assert.h>
42#include <iprt/asm-amd64-x86.h>
43#include <iprt/string.h>
44#include <VBox/log.h>
45#include <VBox/param.h>
46#include <VBox/err.h>
47
48
49/*******************************************************************************
50* Structures and Typedefs *
51*******************************************************************************/
52/**
53 * Stated structure for PGM_GST_NAME(HandlerVirtualUpdate) that's
54 * passed to PGM_GST_NAME(VirtHandlerUpdateOne) during enumeration.
55 */
56typedef struct PGMHVUSTATE
57{
58 /** Pointer to the VM. */
59 PVM pVM;
60 /** Pointer to the VMCPU. */
61 PVMCPU pVCpu;
62 /** The todo flags. */
63 RTUINT fTodo;
64 /** The CR4 register value. */
65 uint32_t cr4;
66} PGMHVUSTATE, *PPGMHVUSTATE;
67
68
69/*******************************************************************************
70* Internal Functions *
71*******************************************************************************/
72DECLINLINE(int) pgmShwGetLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPT *ppPdpt, PX86PDPAE *ppPD);
73DECLINLINE(int) pgmShwGetPaePoolPagePD(PVMCPU pVCpu, RTGCPTR GCPtr, PPGMPOOLPAGE *ppShwPde);
74#ifndef IN_RC
75static int pgmShwSyncLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, X86PGPAEUINT uGstPml4e, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD);
76static int pgmShwGetEPTPDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PEPTPDPT *ppPdpt, PEPTPD *ppPD);
77#endif
78
79
80/*
81 * Shadow - 32-bit mode
82 */
83#define PGM_SHW_TYPE PGM_TYPE_32BIT
84#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
85#include "PGMAllShw.h"
86
87/* Guest - real mode */
88#define PGM_GST_TYPE PGM_TYPE_REAL
89#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
90#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
91#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
92#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
93#include "PGMGstDefs.h"
94#include "PGMAllGst.h"
95#include "PGMAllBth.h"
96#undef BTH_PGMPOOLKIND_PT_FOR_PT
97#undef BTH_PGMPOOLKIND_ROOT
98#undef PGM_BTH_NAME
99#undef PGM_GST_TYPE
100#undef PGM_GST_NAME
101
102/* Guest - protected mode */
103#define PGM_GST_TYPE PGM_TYPE_PROT
104#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
105#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
106#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
107#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
108#include "PGMGstDefs.h"
109#include "PGMAllGst.h"
110#include "PGMAllBth.h"
111#undef BTH_PGMPOOLKIND_PT_FOR_PT
112#undef BTH_PGMPOOLKIND_ROOT
113#undef PGM_BTH_NAME
114#undef PGM_GST_TYPE
115#undef PGM_GST_NAME
116
117/* Guest - 32-bit mode */
118#define PGM_GST_TYPE PGM_TYPE_32BIT
119#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
120#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
121#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
122#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
123#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD
124#include "PGMGstDefs.h"
125#include "PGMAllGst.h"
126#include "PGMAllBth.h"
127#undef BTH_PGMPOOLKIND_PT_FOR_BIG
128#undef BTH_PGMPOOLKIND_PT_FOR_PT
129#undef BTH_PGMPOOLKIND_ROOT
130#undef PGM_BTH_NAME
131#undef PGM_GST_TYPE
132#undef PGM_GST_NAME
133
134#undef PGM_SHW_TYPE
135#undef PGM_SHW_NAME
136
137
138/*
139 * Shadow - PAE mode
140 */
141#define PGM_SHW_TYPE PGM_TYPE_PAE
142#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
143#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
144#include "PGMAllShw.h"
145
146/* Guest - real mode */
147#define PGM_GST_TYPE PGM_TYPE_REAL
148#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
149#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
150#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
151#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
152#include "PGMGstDefs.h"
153#include "PGMAllBth.h"
154#undef BTH_PGMPOOLKIND_PT_FOR_PT
155#undef BTH_PGMPOOLKIND_ROOT
156#undef PGM_BTH_NAME
157#undef PGM_GST_TYPE
158#undef PGM_GST_NAME
159
160/* Guest - protected mode */
161#define PGM_GST_TYPE PGM_TYPE_PROT
162#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
163#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
164#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
165#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
166#include "PGMGstDefs.h"
167#include "PGMAllBth.h"
168#undef BTH_PGMPOOLKIND_PT_FOR_PT
169#undef BTH_PGMPOOLKIND_ROOT
170#undef PGM_BTH_NAME
171#undef PGM_GST_TYPE
172#undef PGM_GST_NAME
173
174/* Guest - 32-bit mode */
175#define PGM_GST_TYPE PGM_TYPE_32BIT
176#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
177#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
178#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
179#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
180#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_FOR_32BIT
181#include "PGMGstDefs.h"
182#include "PGMAllBth.h"
183#undef BTH_PGMPOOLKIND_PT_FOR_BIG
184#undef BTH_PGMPOOLKIND_PT_FOR_PT
185#undef BTH_PGMPOOLKIND_ROOT
186#undef PGM_BTH_NAME
187#undef PGM_GST_TYPE
188#undef PGM_GST_NAME
189
190
191/* Guest - PAE mode */
192#define PGM_GST_TYPE PGM_TYPE_PAE
193#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
194#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
195#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
196#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
197#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT
198#include "PGMGstDefs.h"
199#include "PGMAllGst.h"
200#include "PGMAllBth.h"
201#undef BTH_PGMPOOLKIND_PT_FOR_BIG
202#undef BTH_PGMPOOLKIND_PT_FOR_PT
203#undef BTH_PGMPOOLKIND_ROOT
204#undef PGM_BTH_NAME
205#undef PGM_GST_TYPE
206#undef PGM_GST_NAME
207
208#undef PGM_SHW_TYPE
209#undef PGM_SHW_NAME
210
211
212#ifndef IN_RC /* AMD64 implies VT-x/AMD-V */
213/*
214 * Shadow - AMD64 mode
215 */
216# define PGM_SHW_TYPE PGM_TYPE_AMD64
217# define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
218# include "PGMAllShw.h"
219
220/* Guest - protected mode (only used for AMD-V nested paging in 64 bits mode) */
221# define PGM_GST_TYPE PGM_TYPE_PROT
222# define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
223# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_PROT(name)
224# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
225# define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PD_PHYS
226# include "PGMGstDefs.h"
227# include "PGMAllBth.h"
228# undef BTH_PGMPOOLKIND_PT_FOR_PT
229# undef BTH_PGMPOOLKIND_ROOT
230# undef PGM_BTH_NAME
231# undef PGM_GST_TYPE
232# undef PGM_GST_NAME
233
234# ifdef VBOX_WITH_64_BITS_GUESTS
235/* Guest - AMD64 mode */
236# define PGM_GST_TYPE PGM_TYPE_AMD64
237# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
238# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
239# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
240# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
241# define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_64BIT_PML4
242# include "PGMGstDefs.h"
243# include "PGMAllGst.h"
244# include "PGMAllBth.h"
245# undef BTH_PGMPOOLKIND_PT_FOR_BIG
246# undef BTH_PGMPOOLKIND_PT_FOR_PT
247# undef BTH_PGMPOOLKIND_ROOT
248# undef PGM_BTH_NAME
249# undef PGM_GST_TYPE
250# undef PGM_GST_NAME
251# endif /* VBOX_WITH_64_BITS_GUESTS */
252
253# undef PGM_SHW_TYPE
254# undef PGM_SHW_NAME
255
256
257/*
258 * Shadow - Nested paging mode
259 */
260# define PGM_SHW_TYPE PGM_TYPE_NESTED
261# define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED(name)
262# include "PGMAllShw.h"
263
264/* Guest - real mode */
265# define PGM_GST_TYPE PGM_TYPE_REAL
266# define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
267# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_REAL(name)
268# include "PGMGstDefs.h"
269# include "PGMAllBth.h"
270# undef PGM_BTH_NAME
271# undef PGM_GST_TYPE
272# undef PGM_GST_NAME
273
274/* Guest - protected mode */
275# define PGM_GST_TYPE PGM_TYPE_PROT
276# define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
277# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PROT(name)
278# include "PGMGstDefs.h"
279# include "PGMAllBth.h"
280# undef PGM_BTH_NAME
281# undef PGM_GST_TYPE
282# undef PGM_GST_NAME
283
284/* Guest - 32-bit mode */
285# define PGM_GST_TYPE PGM_TYPE_32BIT
286# define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
287# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT(name)
288# include "PGMGstDefs.h"
289# include "PGMAllBth.h"
290# undef PGM_BTH_NAME
291# undef PGM_GST_TYPE
292# undef PGM_GST_NAME
293
294/* Guest - PAE mode */
295# define PGM_GST_TYPE PGM_TYPE_PAE
296# define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
297# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE(name)
298# include "PGMGstDefs.h"
299# include "PGMAllBth.h"
300# undef PGM_BTH_NAME
301# undef PGM_GST_TYPE
302# undef PGM_GST_NAME
303
304# ifdef VBOX_WITH_64_BITS_GUESTS
305/* Guest - AMD64 mode */
306# define PGM_GST_TYPE PGM_TYPE_AMD64
307# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
308# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64(name)
309# include "PGMGstDefs.h"
310# include "PGMAllBth.h"
311# undef PGM_BTH_NAME
312# undef PGM_GST_TYPE
313# undef PGM_GST_NAME
314# endif /* VBOX_WITH_64_BITS_GUESTS */
315
316# undef PGM_SHW_TYPE
317# undef PGM_SHW_NAME
318
319
320/*
321 * Shadow - EPT
322 */
323# define PGM_SHW_TYPE PGM_TYPE_EPT
324# define PGM_SHW_NAME(name) PGM_SHW_NAME_EPT(name)
325# include "PGMAllShw.h"
326
327/* Guest - real mode */
328# define PGM_GST_TYPE PGM_TYPE_REAL
329# define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
330# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_REAL(name)
331# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
332# include "PGMGstDefs.h"
333# include "PGMAllBth.h"
334# undef BTH_PGMPOOLKIND_PT_FOR_PT
335# undef PGM_BTH_NAME
336# undef PGM_GST_TYPE
337# undef PGM_GST_NAME
338
339/* Guest - protected mode */
340# define PGM_GST_TYPE PGM_TYPE_PROT
341# define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
342# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PROT(name)
343# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
344# include "PGMGstDefs.h"
345# include "PGMAllBth.h"
346# undef BTH_PGMPOOLKIND_PT_FOR_PT
347# undef PGM_BTH_NAME
348# undef PGM_GST_TYPE
349# undef PGM_GST_NAME
350
351/* Guest - 32-bit mode */
352# define PGM_GST_TYPE PGM_TYPE_32BIT
353# define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
354# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_32BIT(name)
355# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
356# include "PGMGstDefs.h"
357# include "PGMAllBth.h"
358# undef BTH_PGMPOOLKIND_PT_FOR_PT
359# undef PGM_BTH_NAME
360# undef PGM_GST_TYPE
361# undef PGM_GST_NAME
362
363/* Guest - PAE mode */
364# define PGM_GST_TYPE PGM_TYPE_PAE
365# define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
366# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PAE(name)
367# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
368# include "PGMGstDefs.h"
369# include "PGMAllBth.h"
370# undef BTH_PGMPOOLKIND_PT_FOR_PT
371# undef PGM_BTH_NAME
372# undef PGM_GST_TYPE
373# undef PGM_GST_NAME
374
375# ifdef VBOX_WITH_64_BITS_GUESTS
376/* Guest - AMD64 mode */
377# define PGM_GST_TYPE PGM_TYPE_AMD64
378# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
379# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_AMD64(name)
380# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
381# include "PGMGstDefs.h"
382# include "PGMAllBth.h"
383# undef BTH_PGMPOOLKIND_PT_FOR_PT
384# undef PGM_BTH_NAME
385# undef PGM_GST_TYPE
386# undef PGM_GST_NAME
387# endif /* VBOX_WITH_64_BITS_GUESTS */
388
389# undef PGM_SHW_TYPE
390# undef PGM_SHW_NAME
391
392#endif /* !IN_RC */
393
394
395#ifndef IN_RING3
396/**
397 * #PF Handler.
398 *
399 * @returns VBox status code (appropriate for trap handling and GC return).
400 * @param pVCpu Pointer to the VMCPU.
401 * @param uErr The trap error code.
402 * @param pRegFrame Trap register frame.
403 * @param pvFault The fault address.
404 */
405VMMDECL(int) PGMTrap0eHandler(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
406{
407 PVM pVM = pVCpu->CTX_SUFF(pVM);
408
409 Log(("PGMTrap0eHandler: uErr=%RGx pvFault=%RGv eip=%04x:%RGv cr3=%RGp\n", uErr, pvFault, pRegFrame->cs.Sel, (RTGCPTR)pRegFrame->rip, (RTGCPHYS)CPUMGetGuestCR3(pVCpu)));
410 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0e, a);
411 STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = NULL; } );
412
413
414#ifdef VBOX_WITH_STATISTICS
415 /*
416 * Error code stats.
417 */
418 if (uErr & X86_TRAP_PF_US)
419 {
420 if (!(uErr & X86_TRAP_PF_P))
421 {
422 if (uErr & X86_TRAP_PF_RW)
423 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eUSNotPresentWrite);
424 else
425 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eUSNotPresentRead);
426 }
427 else if (uErr & X86_TRAP_PF_RW)
428 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eUSWrite);
429 else if (uErr & X86_TRAP_PF_RSVD)
430 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eUSReserved);
431 else if (uErr & X86_TRAP_PF_ID)
432 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eUSNXE);
433 else
434 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eUSRead);
435 }
436 else
437 { /* Supervisor */
438 if (!(uErr & X86_TRAP_PF_P))
439 {
440 if (uErr & X86_TRAP_PF_RW)
441 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eSVNotPresentWrite);
442 else
443 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eSVNotPresentRead);
444 }
445 else if (uErr & X86_TRAP_PF_RW)
446 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eSVWrite);
447 else if (uErr & X86_TRAP_PF_ID)
448 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eSNXE);
449 else if (uErr & X86_TRAP_PF_RSVD)
450 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eSVReserved);
451 }
452#endif /* VBOX_WITH_STATISTICS */
453
454 /*
455 * Call the worker.
456 */
457 bool fLockTaken = false;
458 int rc = PGM_BTH_PFN(Trap0eHandler, pVCpu)(pVCpu, uErr, pRegFrame, pvFault, &fLockTaken);
459 if (fLockTaken)
460 {
461 PGM_LOCK_ASSERT_OWNER(pVM);
462 pgmUnlock(pVM);
463 }
464 LogFlow(("PGMTrap0eHandler: uErr=%RGx pvFault=%RGv rc=%Rrc\n", uErr, pvFault, rc));
465
466 /*
467 * Return code tweaks.
468 */
469 if (rc != VINF_SUCCESS)
470 {
471 if (rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
472 rc = VINF_SUCCESS;
473
474# ifdef IN_RING0
475 /* Note: hack alert for difficult to reproduce problem. */
476 if ( rc == VERR_PAGE_NOT_PRESENT /* SMP only ; disassembly might fail. */
477 || rc == VERR_PAGE_TABLE_NOT_PRESENT /* seen with UNI & SMP */
478 || rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT /* seen with SMP */
479 || rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT) /* precaution */
480 {
481 Log(("WARNING: Unexpected VERR_PAGE_TABLE_NOT_PRESENT (%d) for page fault at %RGv error code %x (rip=%RGv)\n", rc, pvFault, uErr, pRegFrame->rip));
482 /* Some kind of inconsistency in the SMP case; it's safe to just execute the instruction again; not sure about single VCPU VMs though. */
483 rc = VINF_SUCCESS;
484 }
485# endif
486 }
487
488 STAM_STATS({ if (rc == VINF_EM_RAW_GUEST_TRAP) STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eGuestPF); });
489 STAM_STATS({ if (!pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution))
490 pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Misc; });
491 STAM_PROFILE_STOP_EX(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0e, pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution), a);
492 return rc;
493}
494#endif /* !IN_RING3 */
495
496
497/**
498 * Prefetch a page
499 *
500 * Typically used to sync commonly used pages before entering raw mode
501 * after a CR3 reload.
502 *
503 * @returns VBox status code suitable for scheduling.
504 * @retval VINF_SUCCESS on success.
505 * @retval VINF_PGM_SYNC_CR3 if we're out of shadow pages or something like that.
506 * @param pVCpu Pointer to the VMCPU.
507 * @param GCPtrPage Page to invalidate.
508 */
509VMMDECL(int) PGMPrefetchPage(PVMCPU pVCpu, RTGCPTR GCPtrPage)
510{
511 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Prefetch), a);
512 int rc = PGM_BTH_PFN(PrefetchPage, pVCpu)(pVCpu, GCPtrPage);
513 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Prefetch), a);
514 AssertMsg(rc == VINF_SUCCESS || rc == VINF_PGM_SYNC_CR3 || RT_FAILURE(rc), ("rc=%Rrc\n", rc));
515 return rc;
516}
517
518
519/**
520 * Gets the mapping corresponding to the specified address (if any).
521 *
522 * @returns Pointer to the mapping.
523 * @returns NULL if not
524 *
525 * @param pVM Pointer to the VM.
526 * @param GCPtr The guest context pointer.
527 */
528PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr)
529{
530 PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
531 while (pMapping)
532 {
533 if ((uintptr_t)GCPtr < (uintptr_t)pMapping->GCPtr)
534 break;
535 if ((uintptr_t)GCPtr - (uintptr_t)pMapping->GCPtr < pMapping->cb)
536 return pMapping;
537 pMapping = pMapping->CTX_SUFF(pNext);
538 }
539 return NULL;
540}
541
542
543/**
544 * Verifies a range of pages for read or write access
545 *
546 * Only checks the guest's page tables
547 *
548 * @returns VBox status code.
549 * @param pVCpu Pointer to the VMCPU.
550 * @param Addr Guest virtual address to check
551 * @param cbSize Access size
552 * @param fAccess Access type (r/w, user/supervisor (X86_PTE_*))
553 * @remarks Current not in use.
554 */
555VMMDECL(int) PGMIsValidAccess(PVMCPU pVCpu, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess)
556{
557 /*
558 * Validate input.
559 */
560 if (fAccess & ~(X86_PTE_US | X86_PTE_RW))
561 {
562 AssertMsgFailed(("PGMIsValidAccess: invalid access type %08x\n", fAccess));
563 return VERR_INVALID_PARAMETER;
564 }
565
566 uint64_t fPage;
567 int rc = PGMGstGetPage(pVCpu, (RTGCPTR)Addr, &fPage, NULL);
568 if (RT_FAILURE(rc))
569 {
570 Log(("PGMIsValidAccess: access violation for %RGv rc=%d\n", Addr, rc));
571 return VINF_EM_RAW_GUEST_TRAP;
572 }
573
574 /*
575 * Check if the access would cause a page fault
576 *
577 * Note that hypervisor page directories are not present in the guest's tables, so this check
578 * is sufficient.
579 */
580 bool fWrite = !!(fAccess & X86_PTE_RW);
581 bool fUser = !!(fAccess & X86_PTE_US);
582 if ( !(fPage & X86_PTE_P)
583 || (fWrite && !(fPage & X86_PTE_RW))
584 || (fUser && !(fPage & X86_PTE_US)) )
585 {
586 Log(("PGMIsValidAccess: access violation for %RGv attr %#llx vs %d:%d\n", Addr, fPage, fWrite, fUser));
587 return VINF_EM_RAW_GUEST_TRAP;
588 }
589 if ( RT_SUCCESS(rc)
590 && PAGE_ADDRESS(Addr) != PAGE_ADDRESS(Addr + cbSize))
591 return PGMIsValidAccess(pVCpu, Addr + PAGE_SIZE, (cbSize > PAGE_SIZE) ? cbSize - PAGE_SIZE : 1, fAccess);
592 return rc;
593}
594
595
596/**
597 * Verifies a range of pages for read or write access
598 *
599 * Supports handling of pages marked for dirty bit tracking and CSAM
600 *
601 * @returns VBox status code.
602 * @param pVCpu Pointer to the VMCPU.
603 * @param Addr Guest virtual address to check
604 * @param cbSize Access size
605 * @param fAccess Access type (r/w, user/supervisor (X86_PTE_*))
606 */
607VMMDECL(int) PGMVerifyAccess(PVMCPU pVCpu, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess)
608{
609 PVM pVM = pVCpu->CTX_SUFF(pVM);
610
611 AssertMsg(!(fAccess & ~(X86_PTE_US | X86_PTE_RW)), ("PGMVerifyAccess: invalid access type %08x\n", fAccess));
612
613 /*
614 * Get going.
615 */
616 uint64_t fPageGst;
617 int rc = PGMGstGetPage(pVCpu, (RTGCPTR)Addr, &fPageGst, NULL);
618 if (RT_FAILURE(rc))
619 {
620 Log(("PGMVerifyAccess: access violation for %RGv rc=%d\n", Addr, rc));
621 return VINF_EM_RAW_GUEST_TRAP;
622 }
623
624 /*
625 * Check if the access would cause a page fault
626 *
627 * Note that hypervisor page directories are not present in the guest's tables, so this check
628 * is sufficient.
629 */
630 const bool fWrite = !!(fAccess & X86_PTE_RW);
631 const bool fUser = !!(fAccess & X86_PTE_US);
632 if ( !(fPageGst & X86_PTE_P)
633 || (fWrite && !(fPageGst & X86_PTE_RW))
634 || (fUser && !(fPageGst & X86_PTE_US)) )
635 {
636 Log(("PGMVerifyAccess: access violation for %RGv attr %#llx vs %d:%d\n", Addr, fPageGst, fWrite, fUser));
637 return VINF_EM_RAW_GUEST_TRAP;
638 }
639
640 if (!pVM->pgm.s.fNestedPaging)
641 {
642 /*
643 * Next step is to verify if we protected this page for dirty bit tracking or for CSAM scanning
644 */
645 rc = PGMShwGetPage(pVCpu, (RTGCPTR)Addr, NULL, NULL);
646 if ( rc == VERR_PAGE_NOT_PRESENT
647 || rc == VERR_PAGE_TABLE_NOT_PRESENT)
648 {
649 /*
650 * Page is not present in our page tables.
651 * Try to sync it!
652 */
653 Assert(X86_TRAP_PF_RW == X86_PTE_RW && X86_TRAP_PF_US == X86_PTE_US);
654 uint32_t uErr = fAccess & (X86_TRAP_PF_RW | X86_TRAP_PF_US);
655 rc = PGM_BTH_PFN(VerifyAccessSyncPage, pVCpu)(pVCpu, Addr, fPageGst, uErr);
656 if (rc != VINF_SUCCESS)
657 return rc;
658 }
659 else
660 AssertMsg(rc == VINF_SUCCESS, ("PGMShwGetPage %RGv failed with %Rrc\n", Addr, rc));
661 }
662
663#if 0 /* def VBOX_STRICT; triggers too often now */
664 /*
665 * This check is a bit paranoid, but useful.
666 */
667 /* Note! This will assert when writing to monitored pages (a bit annoying actually). */
668 uint64_t fPageShw;
669 rc = PGMShwGetPage(pVCpu, (RTGCPTR)Addr, &fPageShw, NULL);
670 if ( (rc == VERR_PAGE_NOT_PRESENT || RT_FAILURE(rc))
671 || (fWrite && !(fPageShw & X86_PTE_RW))
672 || (fUser && !(fPageShw & X86_PTE_US)) )
673 {
674 AssertMsgFailed(("Unexpected access violation for %RGv! rc=%Rrc write=%d user=%d\n",
675 Addr, rc, fWrite && !(fPageShw & X86_PTE_RW), fUser && !(fPageShw & X86_PTE_US)));
676 return VINF_EM_RAW_GUEST_TRAP;
677 }
678#endif
679
680 if ( RT_SUCCESS(rc)
681 && ( PAGE_ADDRESS(Addr) != PAGE_ADDRESS(Addr + cbSize - 1)
682 || Addr + cbSize < Addr))
683 {
684 /* Don't recursively call PGMVerifyAccess as we might run out of stack. */
685 for (;;)
686 {
687 Addr += PAGE_SIZE;
688 if (cbSize > PAGE_SIZE)
689 cbSize -= PAGE_SIZE;
690 else
691 cbSize = 1;
692 rc = PGMVerifyAccess(pVCpu, Addr, 1, fAccess);
693 if (rc != VINF_SUCCESS)
694 break;
695 if (PAGE_ADDRESS(Addr) == PAGE_ADDRESS(Addr + cbSize - 1))
696 break;
697 }
698 }
699 return rc;
700}
701
702
703/**
704 * Emulation of the invlpg instruction (HC only actually).
705 *
706 * @returns Strict VBox status code, special care required.
707 * @retval VINF_PGM_SYNC_CR3 - handled.
708 * @retval VINF_EM_RAW_EMULATE_INSTR - not handled (RC only).
709 * @retval VERR_REM_FLUSHED_PAGES_OVERFLOW - not handled.
710 *
711 * @param pVCpu Pointer to the VMCPU.
712 * @param GCPtrPage Page to invalidate.
713 *
714 * @remark ASSUMES the page table entry or page directory is valid. Fairly
715 * safe, but there could be edge cases!
716 *
717 * @todo Flush page or page directory only if necessary!
718 * @todo VBOXSTRICTRC
719 */
720VMMDECL(int) PGMInvalidatePage(PVMCPU pVCpu, RTGCPTR GCPtrPage)
721{
722 PVM pVM = pVCpu->CTX_SUFF(pVM);
723 int rc;
724 Log3(("PGMInvalidatePage: GCPtrPage=%RGv\n", GCPtrPage));
725
726#if !defined(IN_RING3) && defined(VBOX_WITH_REM)
727 /*
728 * Notify the recompiler so it can record this instruction.
729 */
730 REMNotifyInvalidatePage(pVM, GCPtrPage);
731#endif /* !IN_RING3 */
732
733
734#ifdef IN_RC
735 /*
736 * Check for conflicts and pending CR3 monitoring updates.
737 */
738 if (pgmMapAreMappingsFloating(pVM))
739 {
740 if ( pgmGetMapping(pVM, GCPtrPage)
741 && PGMGstGetPage(pVCpu, GCPtrPage, NULL, NULL) != VERR_PAGE_TABLE_NOT_PRESENT)
742 {
743 LogFlow(("PGMGCInvalidatePage: Conflict!\n"));
744 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
745 STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatRCInvlPgConflict);
746 return VINF_PGM_SYNC_CR3;
747 }
748
749 if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
750 {
751 LogFlow(("PGMGCInvalidatePage: PGM_SYNC_MONITOR_CR3 -> reinterpret instruction in R3\n"));
752 STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatRCInvlPgSyncMonCR3);
753 return VINF_EM_RAW_EMULATE_INSTR;
754 }
755 }
756#endif /* IN_RC */
757
758 /*
759 * Call paging mode specific worker.
760 */
761 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePage), a);
762 pgmLock(pVM);
763 rc = PGM_BTH_PFN(InvalidatePage, pVCpu)(pVCpu, GCPtrPage);
764 pgmUnlock(pVM);
765 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePage), a);
766
767#ifdef IN_RING3
768 /*
769 * Check if we have a pending update of the CR3 monitoring.
770 */
771 if ( RT_SUCCESS(rc)
772 && (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3))
773 {
774 pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
775 Assert(!pVM->pgm.s.fMappingsFixed); Assert(pgmMapAreMappingsEnabled(pVM));
776 }
777
778# ifdef VBOX_WITH_RAW_MODE
779 /*
780 * Inform CSAM about the flush
781 *
782 * Note: This is to check if monitored pages have been changed; when we implement
783 * callbacks for virtual handlers, this is no longer required.
784 */
785 CSAMR3FlushPage(pVM, GCPtrPage);
786# endif
787#endif /* IN_RING3 */
788
789 /* Ignore all irrelevant error codes. */
790 if ( rc == VERR_PAGE_NOT_PRESENT
791 || rc == VERR_PAGE_TABLE_NOT_PRESENT
792 || rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT
793 || rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT)
794 rc = VINF_SUCCESS;
795
796 return rc;
797}
798
799
800/**
801 * Executes an instruction using the interpreter.
802 *
803 * @returns VBox status code (appropriate for trap handling and GC return).
804 * @param pVM Pointer to the VM.
805 * @param pVCpu Pointer to the VMCPU.
806 * @param pRegFrame Register frame.
807 * @param pvFault Fault address.
808 */
809VMMDECL(VBOXSTRICTRC) PGMInterpretInstruction(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
810{
811 VBOXSTRICTRC rc = EMInterpretInstruction(pVCpu, pRegFrame, pvFault);
812 if (rc == VERR_EM_INTERPRETER)
813 rc = VINF_EM_RAW_EMULATE_INSTR;
814 if (rc != VINF_SUCCESS)
815 Log(("PGMInterpretInstruction: returns %Rrc (pvFault=%RGv)\n", VBOXSTRICTRC_VAL(rc), pvFault));
816 return rc;
817}
818
819
820/**
821 * Gets effective page information (from the VMM page directory).
822 *
823 * @returns VBox status.
824 * @param pVCpu Pointer to the VMCPU.
825 * @param GCPtr Guest Context virtual address of the page.
826 * @param pfFlags Where to store the flags. These are X86_PTE_*.
827 * @param pHCPhys Where to store the HC physical address of the page.
828 * This is page aligned.
829 * @remark You should use PGMMapGetPage() for pages in a mapping.
830 */
831VMMDECL(int) PGMShwGetPage(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys)
832{
833 pgmLock(pVCpu->CTX_SUFF(pVM));
834 int rc = PGM_SHW_PFN(GetPage, pVCpu)(pVCpu, GCPtr, pfFlags, pHCPhys);
835 pgmUnlock(pVCpu->CTX_SUFF(pVM));
836 return rc;
837}
838
839
840/**
841 * Modify page flags for a range of pages in the shadow context.
842 *
843 * The existing flags are ANDed with the fMask and ORed with the fFlags.
844 *
845 * @returns VBox status code.
846 * @param pVCpu Pointer to the VMCPU.
847 * @param GCPtr Virtual address of the first page in the range.
848 * @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
849 * @param fMask The AND mask - page flags X86_PTE_*.
850 * Be very CAREFUL when ~'ing constants which could be 32-bit!
851 * @param fOpFlags A combination of the PGM_MK_PK_XXX flags.
852 * @remark You must use PGMMapModifyPage() for pages in a mapping.
853 */
854DECLINLINE(int) pdmShwModifyPage(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags)
855{
856 AssertMsg(!(fFlags & X86_PTE_PAE_PG_MASK), ("fFlags=%#llx\n", fFlags));
857 Assert(!(fOpFlags & ~(PGM_MK_PG_IS_MMIO2 | PGM_MK_PG_IS_WRITE_FAULT)));
858
859 GCPtr &= PAGE_BASE_GC_MASK; /** @todo this ain't necessary, right... */
860
861 PVM pVM = pVCpu->CTX_SUFF(pVM);
862 pgmLock(pVM);
863 int rc = PGM_SHW_PFN(ModifyPage, pVCpu)(pVCpu, GCPtr, PAGE_SIZE, fFlags, fMask, fOpFlags);
864 pgmUnlock(pVM);
865 return rc;
866}
867
868
869/**
870 * Changing the page flags for a single page in the shadow page tables so as to
871 * make it read-only.
872 *
873 * @returns VBox status code.
874 * @param pVCpu Pointer to the VMCPU.
875 * @param GCPtr Virtual address of the first page in the range.
876 * @param fOpFlags A combination of the PGM_MK_PK_XXX flags.
877 */
878VMMDECL(int) PGMShwMakePageReadonly(PVMCPU pVCpu, RTGCPTR GCPtr, uint32_t fOpFlags)
879{
880 return pdmShwModifyPage(pVCpu, GCPtr, 0, ~(uint64_t)X86_PTE_RW, fOpFlags);
881}
882
883
884/**
885 * Changing the page flags for a single page in the shadow page tables so as to
886 * make it writable.
887 *
888 * The call must know with 101% certainty that the guest page tables maps this
889 * as writable too. This function will deal shared, zero and write monitored
890 * pages.
891 *
892 * @returns VBox status code.
893 * @param pVCpu Pointer to the VMCPU.
894 * @param GCPtr Virtual address of the first page in the range.
895 * @param fMmio2 Set if it is an MMIO2 page.
896 * @param fOpFlags A combination of the PGM_MK_PK_XXX flags.
897 */
898VMMDECL(int) PGMShwMakePageWritable(PVMCPU pVCpu, RTGCPTR GCPtr, uint32_t fOpFlags)
899{
900 return pdmShwModifyPage(pVCpu, GCPtr, X86_PTE_RW, ~(uint64_t)0, fOpFlags);
901}
902
903
904/**
905 * Changing the page flags for a single page in the shadow page tables so as to
906 * make it not present.
907 *
908 * @returns VBox status code.
909 * @param pVCpu Pointer to the VMCPU.
910 * @param GCPtr Virtual address of the first page in the range.
911 * @param fOpFlags A combination of the PGM_MK_PG_XXX flags.
912 */
913VMMDECL(int) PGMShwMakePageNotPresent(PVMCPU pVCpu, RTGCPTR GCPtr, uint32_t fOpFlags)
914{
915 return pdmShwModifyPage(pVCpu, GCPtr, 0, 0, fOpFlags);
916}
917
918
919/**
920 * Changing the page flags for a single page in the shadow page tables so as to
921 * make it supervisor and writable.
922 *
923 * This if for dealing with CR0.WP=0 and readonly user pages.
924 *
925 * @returns VBox status code.
926 * @param pVCpu Pointer to the VMCPU.
927 * @param GCPtr Virtual address of the first page in the range.
928 * @param fBigPage Whether or not this is a big page. If it is, we have to
929 * change the shadow PDE as well. If it isn't, the caller
930 * has checked that the shadow PDE doesn't need changing.
931 * We ASSUME 4KB pages backing the big page here!
932 * @param fOpFlags A combination of the PGM_MK_PG_XXX flags.
933 */
934int pgmShwMakePageSupervisorAndWritable(PVMCPU pVCpu, RTGCPTR GCPtr, bool fBigPage, uint32_t fOpFlags)
935{
936 int rc = pdmShwModifyPage(pVCpu, GCPtr, X86_PTE_RW, ~(uint64_t)X86_PTE_US, fOpFlags);
937 if (rc == VINF_SUCCESS && fBigPage)
938 {
939 /* this is a bit ugly... */
940 switch (pVCpu->pgm.s.enmShadowMode)
941 {
942 case PGMMODE_32_BIT:
943 {
944 PX86PDE pPde = pgmShwGet32BitPDEPtr(pVCpu, GCPtr);
945 AssertReturn(pPde, VERR_INTERNAL_ERROR_3);
946 Log(("pgmShwMakePageSupervisorAndWritable: PDE=%#llx", pPde->u));
947 pPde->n.u1Write = 1;
948 Log(("-> PDE=%#llx (32)\n", pPde->u));
949 break;
950 }
951 case PGMMODE_PAE:
952 case PGMMODE_PAE_NX:
953 {
954 PX86PDEPAE pPde = pgmShwGetPaePDEPtr(pVCpu, GCPtr);
955 AssertReturn(pPde, VERR_INTERNAL_ERROR_3);
956 Log(("pgmShwMakePageSupervisorAndWritable: PDE=%#llx", pPde->u));
957 pPde->n.u1Write = 1;
958 Log(("-> PDE=%#llx (PAE)\n", pPde->u));
959 break;
960 }
961 default:
962 AssertFailedReturn(VERR_INTERNAL_ERROR_4);
963 }
964 }
965 return rc;
966}
967
968
969/**
970 * Gets the shadow page directory for the specified address, PAE.
971 *
972 * @returns Pointer to the shadow PD.
973 * @param pVCpu Pointer to the VMCPU.
974 * @param GCPtr The address.
975 * @param uGstPdpe Guest PDPT entry. Valid.
976 * @param ppPD Receives address of page directory
977 */
978int pgmShwSyncPaePDPtr(PVMCPU pVCpu, RTGCPTR GCPtr, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD)
979{
980 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
981 PX86PDPT pPdpt = pgmShwGetPaePDPTPtr(pVCpu);
982 PX86PDPE pPdpe = &pPdpt->a[iPdPt];
983 PVM pVM = pVCpu->CTX_SUFF(pVM);
984 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
985 PPGMPOOLPAGE pShwPage;
986 int rc;
987
988 PGM_LOCK_ASSERT_OWNER(pVM);
989
990 /* Allocate page directory if not present. */
991 if ( !pPdpe->n.u1Present
992 && !(pPdpe->u & X86_PDPE_PG_MASK))
993 {
994 RTGCPTR64 GCPdPt;
995 PGMPOOLKIND enmKind;
996
997 if (pVM->pgm.s.fNestedPaging || !CPUMIsGuestPagingEnabled(pVCpu))
998 {
999 /* AMD-V nested paging or real/protected mode without paging. */
1000 GCPdPt = (RTGCPTR64)iPdPt << X86_PDPT_SHIFT;
1001 enmKind = PGMPOOLKIND_PAE_PD_PHYS;
1002 }
1003 else
1004 {
1005 if (CPUMGetGuestCR4(pVCpu) & X86_CR4_PAE)
1006 {
1007 if (!(uGstPdpe & X86_PDPE_P))
1008 {
1009 /* PD not present; guest must reload CR3 to change it.
1010 * No need to monitor anything in this case.
1011 */
1012 Assert(!HMIsEnabled(pVM));
1013
1014 GCPdPt = uGstPdpe & X86_PDPE_PG_MASK;
1015 enmKind = PGMPOOLKIND_PAE_PD_PHYS;
1016 uGstPdpe |= X86_PDPE_P;
1017 }
1018 else
1019 {
1020 GCPdPt = uGstPdpe & X86_PDPE_PG_MASK;
1021 enmKind = PGMPOOLKIND_PAE_PD_FOR_PAE_PD;
1022 }
1023 }
1024 else
1025 {
1026 GCPdPt = CPUMGetGuestCR3(pVCpu);
1027 enmKind = (PGMPOOLKIND)(PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD + iPdPt);
1028 }
1029 }
1030
1031 /* Create a reference back to the PDPT by using the index in its shadow page. */
1032 rc = pgmPoolAlloc(pVM, GCPdPt, enmKind, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
1033 pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPdPt, false /*fLockPage*/,
1034 &pShwPage);
1035 AssertRCReturn(rc, rc);
1036
1037 /* The PD was cached or created; hook it up now. */
1038 pPdpe->u |= pShwPage->Core.Key | (uGstPdpe & (X86_PDPE_P | X86_PDPE_A));
1039
1040# if defined(IN_RC)
1041 /*
1042 * In 32 bits PAE mode we *must* invalidate the TLB when changing a
1043 * PDPT entry; the CPU fetches them only during cr3 load, so any
1044 * non-present PDPT will continue to cause page faults.
1045 */
1046 ASMReloadCR3();
1047# endif
1048 PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdpe);
1049 }
1050 else
1051 {
1052 pShwPage = pgmPoolGetPage(pPool, pPdpe->u & X86_PDPE_PG_MASK);
1053 AssertReturn(pShwPage, VERR_PGM_POOL_GET_PAGE_FAILED);
1054 Assert((pPdpe->u & X86_PDPE_PG_MASK) == pShwPage->Core.Key);
1055
1056 pgmPoolCacheUsed(pPool, pShwPage);
1057 }
1058 *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1059 return VINF_SUCCESS;
1060}
1061
1062
1063/**
1064 * Gets the pointer to the shadow page directory entry for an address, PAE.
1065 *
1066 * @returns Pointer to the PDE.
1067 * @param pVCpu The current CPU.
1068 * @param GCPtr The address.
1069 * @param ppShwPde Receives the address of the pgm pool page for the shadow page directory
1070 */
1071DECLINLINE(int) pgmShwGetPaePoolPagePD(PVMCPU pVCpu, RTGCPTR GCPtr, PPGMPOOLPAGE *ppShwPde)
1072{
1073 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
1074 PX86PDPT pPdpt = pgmShwGetPaePDPTPtr(pVCpu);
1075 PVM pVM = pVCpu->CTX_SUFF(pVM);
1076
1077 PGM_LOCK_ASSERT_OWNER(pVM);
1078
1079 AssertReturn(pPdpt, VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT); /* can't happen */
1080 if (!pPdpt->a[iPdPt].n.u1Present)
1081 {
1082 LogFlow(("pgmShwGetPaePoolPagePD: PD %d not present (%RX64)\n", iPdPt, pPdpt->a[iPdPt].u));
1083 return VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT;
1084 }
1085 AssertMsg(pPdpt->a[iPdPt].u & X86_PDPE_PG_MASK, ("GCPtr=%RGv\n", GCPtr));
1086
1087 /* Fetch the pgm pool shadow descriptor. */
1088 PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pVM->pgm.s.CTX_SUFF(pPool), pPdpt->a[iPdPt].u & X86_PDPE_PG_MASK);
1089 AssertReturn(pShwPde, VERR_PGM_POOL_GET_PAGE_FAILED);
1090
1091 *ppShwPde = pShwPde;
1092 return VINF_SUCCESS;
1093}
1094
1095#ifndef IN_RC
1096
1097/**
1098 * Syncs the SHADOW page directory pointer for the specified address.
1099 *
1100 * Allocates backing pages in case the PDPT or PML4 entry is missing.
1101 *
1102 * The caller is responsible for making sure the guest has a valid PD before
1103 * calling this function.
1104 *
1105 * @returns VBox status.
1106 * @param pVCpu Pointer to the VMCPU.
1107 * @param GCPtr The address.
1108 * @param uGstPml4e Guest PML4 entry (valid).
1109 * @param uGstPdpe Guest PDPT entry (valid).
1110 * @param ppPD Receives address of page directory
1111 */
1112static int pgmShwSyncLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, X86PGPAEUINT uGstPml4e, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD)
1113{
1114 PVM pVM = pVCpu->CTX_SUFF(pVM);
1115 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1116 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
1117 PX86PML4E pPml4e = pgmShwGetLongModePML4EPtr(pVCpu, iPml4);
1118 bool fNestedPagingOrNoGstPaging = pVM->pgm.s.fNestedPaging || !CPUMIsGuestPagingEnabled(pVCpu);
1119 PPGMPOOLPAGE pShwPage;
1120 int rc;
1121
1122 PGM_LOCK_ASSERT_OWNER(pVM);
1123
1124 /* Allocate page directory pointer table if not present. */
1125 if ( !pPml4e->n.u1Present
1126 && !(pPml4e->u & X86_PML4E_PG_MASK))
1127 {
1128 RTGCPTR64 GCPml4;
1129 PGMPOOLKIND enmKind;
1130
1131 Assert(pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
1132
1133 if (fNestedPagingOrNoGstPaging)
1134 {
1135 /* AMD-V nested paging or real/protected mode without paging */
1136 GCPml4 = (RTGCPTR64)iPml4 << X86_PML4_SHIFT;
1137 enmKind = PGMPOOLKIND_64BIT_PDPT_FOR_PHYS;
1138 }
1139 else
1140 {
1141 GCPml4 = uGstPml4e & X86_PML4E_PG_MASK;
1142 enmKind = PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT;
1143 }
1144
1145 /* Create a reference back to the PDPT by using the index in its shadow page. */
1146 rc = pgmPoolAlloc(pVM, GCPml4, enmKind, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
1147 pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPml4, false /*fLockPage*/,
1148 &pShwPage);
1149 AssertRCReturn(rc, rc);
1150 }
1151 else
1152 {
1153 pShwPage = pgmPoolGetPage(pPool, pPml4e->u & X86_PML4E_PG_MASK);
1154 AssertReturn(pShwPage, VERR_PGM_POOL_GET_PAGE_FAILED);
1155
1156 pgmPoolCacheUsed(pPool, pShwPage);
1157 }
1158 /* The PDPT was cached or created; hook it up now. */
1159 pPml4e->u |= pShwPage->Core.Key | (uGstPml4e & pVCpu->pgm.s.fGstAmd64ShadowedPml4eMask);
1160
1161 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1162 PX86PDPT pPdpt = (PX86PDPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1163 PX86PDPE pPdpe = &pPdpt->a[iPdPt];
1164
1165 /* Allocate page directory if not present. */
1166 if ( !pPdpe->n.u1Present
1167 && !(pPdpe->u & X86_PDPE_PG_MASK))
1168 {
1169 RTGCPTR64 GCPdPt;
1170 PGMPOOLKIND enmKind;
1171
1172 if (fNestedPagingOrNoGstPaging)
1173 {
1174 /* AMD-V nested paging or real/protected mode without paging */
1175 GCPdPt = (RTGCPTR64)iPdPt << X86_PDPT_SHIFT;
1176 enmKind = PGMPOOLKIND_64BIT_PD_FOR_PHYS;
1177 }
1178 else
1179 {
1180 GCPdPt = uGstPdpe & X86_PDPE_PG_MASK;
1181 enmKind = PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD;
1182 }
1183
1184 /* Create a reference back to the PDPT by using the index in its shadow page. */
1185 rc = pgmPoolAlloc(pVM, GCPdPt, enmKind, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
1186 pShwPage->idx, iPdPt, false /*fLockPage*/,
1187 &pShwPage);
1188 AssertRCReturn(rc, rc);
1189 }
1190 else
1191 {
1192 pShwPage = pgmPoolGetPage(pPool, pPdpe->u & X86_PDPE_PG_MASK);
1193 AssertReturn(pShwPage, VERR_PGM_POOL_GET_PAGE_FAILED);
1194
1195 pgmPoolCacheUsed(pPool, pShwPage);
1196 }
1197 /* The PD was cached or created; hook it up now. */
1198 pPdpe->u |= pShwPage->Core.Key | (uGstPdpe & pVCpu->pgm.s.fGstAmd64ShadowedPdpeMask);
1199
1200 *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1201 return VINF_SUCCESS;
1202}
1203
1204
1205/**
1206 * Gets the SHADOW page directory pointer for the specified address (long mode).
1207 *
1208 * @returns VBox status.
1209 * @param pVCpu Pointer to the VMCPU.
1210 * @param GCPtr The address.
1211 * @param ppPdpt Receives address of pdpt
1212 * @param ppPD Receives address of page directory
1213 */
1214DECLINLINE(int) pgmShwGetLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPT *ppPdpt, PX86PDPAE *ppPD)
1215{
1216 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
1217 PCX86PML4E pPml4e = pgmShwGetLongModePML4EPtr(pVCpu, iPml4);
1218
1219 PGM_LOCK_ASSERT_OWNER(pVCpu->CTX_SUFF(pVM));
1220
1221 AssertReturn(pPml4e, VERR_PGM_PML4_MAPPING);
1222 if (ppPml4e)
1223 *ppPml4e = (PX86PML4E)pPml4e;
1224
1225 Log4(("pgmShwGetLongModePDPtr %RGv (%RHv) %RX64\n", GCPtr, pPml4e, pPml4e->u));
1226
1227 if (!pPml4e->n.u1Present)
1228 return VERR_PAGE_MAP_LEVEL4_NOT_PRESENT;
1229
1230 PVM pVM = pVCpu->CTX_SUFF(pVM);
1231 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1232 PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPml4e->u & X86_PML4E_PG_MASK);
1233 AssertReturn(pShwPage, VERR_PGM_POOL_GET_PAGE_FAILED);
1234
1235 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1236 PCX86PDPT pPdpt = *ppPdpt = (PX86PDPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1237 if (!pPdpt->a[iPdPt].n.u1Present)
1238 return VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT;
1239
1240 pShwPage = pgmPoolGetPage(pPool, pPdpt->a[iPdPt].u & X86_PDPE_PG_MASK);
1241 AssertReturn(pShwPage, VERR_PGM_POOL_GET_PAGE_FAILED);
1242
1243 *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1244 Log4(("pgmShwGetLongModePDPtr %RGv -> *ppPD=%p PDE=%p/%RX64\n", GCPtr, *ppPD, &(*ppPD)->a[(GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK], (*ppPD)->a[(GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK].u));
1245 return VINF_SUCCESS;
1246}
1247
1248
1249/**
1250 * Syncs the SHADOW EPT page directory pointer for the specified address. Allocates
1251 * backing pages in case the PDPT or PML4 entry is missing.
1252 *
1253 * @returns VBox status.
1254 * @param pVCpu Pointer to the VMCPU.
1255 * @param GCPtr The address.
1256 * @param ppPdpt Receives address of pdpt
1257 * @param ppPD Receives address of page directory
1258 */
1259static int pgmShwGetEPTPDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PEPTPDPT *ppPdpt, PEPTPD *ppPD)
1260{
1261 PVM pVM = pVCpu->CTX_SUFF(pVM);
1262 const unsigned iPml4 = (GCPtr >> EPT_PML4_SHIFT) & EPT_PML4_MASK;
1263 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1264 PEPTPML4 pPml4;
1265 PEPTPML4E pPml4e;
1266 PPGMPOOLPAGE pShwPage;
1267 int rc;
1268
1269 Assert(pVM->pgm.s.fNestedPaging);
1270 PGM_LOCK_ASSERT_OWNER(pVM);
1271
1272 pPml4 = (PEPTPML4)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
1273 Assert(pPml4);
1274
1275 /* Allocate page directory pointer table if not present. */
1276 pPml4e = &pPml4->a[iPml4];
1277 if ( !pPml4e->n.u1Present
1278 && !(pPml4e->u & EPT_PML4E_PG_MASK))
1279 {
1280 Assert(!(pPml4e->u & EPT_PML4E_PG_MASK));
1281 RTGCPTR64 GCPml4 = (RTGCPTR64)iPml4 << EPT_PML4_SHIFT;
1282
1283 rc = pgmPoolAlloc(pVM, GCPml4, PGMPOOLKIND_EPT_PDPT_FOR_PHYS, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
1284 pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPml4, false /*fLockPage*/,
1285 &pShwPage);
1286 AssertRCReturn(rc, rc);
1287 }
1288 else
1289 {
1290 pShwPage = pgmPoolGetPage(pPool, pPml4e->u & EPT_PML4E_PG_MASK);
1291 AssertReturn(pShwPage, VERR_PGM_POOL_GET_PAGE_FAILED);
1292
1293 pgmPoolCacheUsed(pPool, pShwPage);
1294 }
1295 /* The PDPT was cached or created; hook it up now and fill with the default value. */
1296 pPml4e->u = pShwPage->Core.Key;
1297 pPml4e->n.u1Present = 1;
1298 pPml4e->n.u1Write = 1;
1299 pPml4e->n.u1Execute = 1;
1300
1301 const unsigned iPdPt = (GCPtr >> EPT_PDPT_SHIFT) & EPT_PDPT_MASK;
1302 PEPTPDPT pPdpt = (PEPTPDPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1303 PEPTPDPTE pPdpe = &pPdpt->a[iPdPt];
1304
1305 if (ppPdpt)
1306 *ppPdpt = pPdpt;
1307
1308 /* Allocate page directory if not present. */
1309 if ( !pPdpe->n.u1Present
1310 && !(pPdpe->u & EPT_PDPTE_PG_MASK))
1311 {
1312 RTGCPTR64 GCPdPt = (RTGCPTR64)iPdPt << EPT_PDPT_SHIFT;
1313 rc = pgmPoolAlloc(pVM, GCPdPt, PGMPOOLKIND_EPT_PD_FOR_PHYS, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
1314 pShwPage->idx, iPdPt, false /*fLockPage*/,
1315 &pShwPage);
1316 AssertRCReturn(rc, rc);
1317 }
1318 else
1319 {
1320 pShwPage = pgmPoolGetPage(pPool, pPdpe->u & EPT_PDPTE_PG_MASK);
1321 AssertReturn(pShwPage, VERR_PGM_POOL_GET_PAGE_FAILED);
1322
1323 pgmPoolCacheUsed(pPool, pShwPage);
1324 }
1325 /* The PD was cached or created; hook it up now and fill with the default value. */
1326 pPdpe->u = pShwPage->Core.Key;
1327 pPdpe->n.u1Present = 1;
1328 pPdpe->n.u1Write = 1;
1329 pPdpe->n.u1Execute = 1;
1330
1331 *ppPD = (PEPTPD)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1332 return VINF_SUCCESS;
1333}
1334
1335#endif /* IN_RC */
1336
1337#ifdef IN_RING0
1338/**
1339 * Synchronizes a range of nested page table entries.
1340 *
1341 * The caller must own the PGM lock.
1342 *
1343 * @param pVCpu The current CPU.
1344 * @param GCPhys Where to start.
1345 * @param cPages How many pages which entries should be synced.
1346 * @param enmShwPagingMode The shadow paging mode (PGMMODE_EPT for VT-x,
1347 * host paging mode for AMD-V).
1348 */
1349int pgmShwSyncNestedPageLocked(PVMCPU pVCpu, RTGCPHYS GCPhysFault, uint32_t cPages, PGMMODE enmShwPagingMode)
1350{
1351 PGM_LOCK_ASSERT_OWNER(pVCpu->CTX_SUFF(pVM));
1352
1353 int rc;
1354 switch (enmShwPagingMode)
1355 {
1356 case PGMMODE_32_BIT:
1357 {
1358 X86PDE PdeDummy = { X86_PDE_P | X86_PDE_US | X86_PDE_RW | X86_PDE_A };
1359 rc = PGM_BTH_NAME_32BIT_PROT(SyncPage)(pVCpu, PdeDummy, GCPhysFault, cPages, ~0U /*uErr*/);
1360 break;
1361 }
1362
1363 case PGMMODE_PAE:
1364 case PGMMODE_PAE_NX:
1365 {
1366 X86PDEPAE PdeDummy = { X86_PDE_P | X86_PDE_US | X86_PDE_RW | X86_PDE_A };
1367 rc = PGM_BTH_NAME_PAE_PROT(SyncPage)(pVCpu, PdeDummy, GCPhysFault, cPages, ~0U /*uErr*/);
1368 break;
1369 }
1370
1371 case PGMMODE_AMD64:
1372 case PGMMODE_AMD64_NX:
1373 {
1374 X86PDEPAE PdeDummy = { X86_PDE_P | X86_PDE_US | X86_PDE_RW | X86_PDE_A };
1375 rc = PGM_BTH_NAME_AMD64_PROT(SyncPage)(pVCpu, PdeDummy, GCPhysFault, cPages, ~0U /*uErr*/);
1376 break;
1377 }
1378
1379 case PGMMODE_EPT:
1380 {
1381 X86PDEPAE PdeDummy = { X86_PDE_P | X86_PDE_US | X86_PDE_RW | X86_PDE_A };
1382 rc = PGM_BTH_NAME_EPT_PROT(SyncPage)(pVCpu, PdeDummy, GCPhysFault, cPages, ~0U /*uErr*/);
1383 break;
1384 }
1385
1386 default:
1387 AssertMsgFailedReturn(("%d\n", enmShwPagingMode), VERR_IPE_NOT_REACHED_DEFAULT_CASE);
1388 }
1389 return rc;
1390}
1391#endif /* IN_RING0 */
1392
1393
1394/**
1395 * Gets effective Guest OS page information.
1396 *
1397 * When GCPtr is in a big page, the function will return as if it was a normal
1398 * 4KB page. If the need for distinguishing between big and normal page becomes
1399 * necessary at a later point, a PGMGstGetPage() will be created for that
1400 * purpose.
1401 *
1402 * @returns VBox status.
1403 * @param pVCpu The current CPU.
1404 * @param GCPtr Guest Context virtual address of the page.
1405 * @param pfFlags Where to store the flags. These are X86_PTE_*, even for big pages.
1406 * @param pGCPhys Where to store the GC physical address of the page.
1407 * This is page aligned. The fact that the
1408 */
1409VMMDECL(int) PGMGstGetPage(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys)
1410{
1411 VMCPU_ASSERT_EMT(pVCpu);
1412 return PGM_GST_PFN(GetPage, pVCpu)(pVCpu, GCPtr, pfFlags, pGCPhys);
1413}
1414
1415
1416/**
1417 * Checks if the page is present.
1418 *
1419 * @returns true if the page is present.
1420 * @returns false if the page is not present.
1421 * @param pVCpu Pointer to the VMCPU.
1422 * @param GCPtr Address within the page.
1423 */
1424VMMDECL(bool) PGMGstIsPagePresent(PVMCPU pVCpu, RTGCPTR GCPtr)
1425{
1426 VMCPU_ASSERT_EMT(pVCpu);
1427 int rc = PGMGstGetPage(pVCpu, GCPtr, NULL, NULL);
1428 return RT_SUCCESS(rc);
1429}
1430
1431
1432/**
1433 * Sets (replaces) the page flags for a range of pages in the guest's tables.
1434 *
1435 * @returns VBox status.
1436 * @param pVCpu Pointer to the VMCPU.
1437 * @param GCPtr The address of the first page.
1438 * @param cb The size of the range in bytes.
1439 * @param fFlags Page flags X86_PTE_*, excluding the page mask of course.
1440 */
1441VMMDECL(int) PGMGstSetPage(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags)
1442{
1443 VMCPU_ASSERT_EMT(pVCpu);
1444 return PGMGstModifyPage(pVCpu, GCPtr, cb, fFlags, 0);
1445}
1446
1447
1448/**
1449 * Modify page flags for a range of pages in the guest's tables
1450 *
1451 * The existing flags are ANDed with the fMask and ORed with the fFlags.
1452 *
1453 * @returns VBox status code.
1454 * @param pVCpu Pointer to the VMCPU.
1455 * @param GCPtr Virtual address of the first page in the range.
1456 * @param cb Size (in bytes) of the range to apply the modification to.
1457 * @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
1458 * @param fMask The AND mask - page flags X86_PTE_*, excluding the page mask of course.
1459 * Be very CAREFUL when ~'ing constants which could be 32-bit!
1460 */
1461VMMDECL(int) PGMGstModifyPage(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
1462{
1463 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,GstModifyPage), a);
1464 VMCPU_ASSERT_EMT(pVCpu);
1465
1466 /*
1467 * Validate input.
1468 */
1469 AssertMsg(!(fFlags & X86_PTE_PAE_PG_MASK), ("fFlags=%#llx\n", fFlags));
1470 Assert(cb);
1471
1472 LogFlow(("PGMGstModifyPage %RGv %d bytes fFlags=%08llx fMask=%08llx\n", GCPtr, cb, fFlags, fMask));
1473
1474 /*
1475 * Adjust input.
1476 */
1477 cb += GCPtr & PAGE_OFFSET_MASK;
1478 cb = RT_ALIGN_Z(cb, PAGE_SIZE);
1479 GCPtr = (GCPtr & PAGE_BASE_GC_MASK);
1480
1481 /*
1482 * Call worker.
1483 */
1484 int rc = PGM_GST_PFN(ModifyPage, pVCpu)(pVCpu, GCPtr, cb, fFlags, fMask);
1485
1486 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,GstModifyPage), a);
1487 return rc;
1488}
1489
1490
1491#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
1492
1493/**
1494 * Performs the lazy mapping of the 32-bit guest PD.
1495 *
1496 * @returns VBox status code.
1497 * @param pVCpu The current CPU.
1498 * @param ppPd Where to return the pointer to the mapping. This is
1499 * always set.
1500 */
1501int pgmGstLazyMap32BitPD(PVMCPU pVCpu, PX86PD *ppPd)
1502{
1503 PVM pVM = pVCpu->CTX_SUFF(pVM);
1504 pgmLock(pVM);
1505
1506 Assert(!pVCpu->pgm.s.CTX_SUFF(pGst32BitPd));
1507
1508 RTGCPHYS GCPhysCR3 = pVCpu->pgm.s.GCPhysCR3 & X86_CR3_PAGE_MASK;
1509 PPGMPAGE pPage;
1510 int rc = pgmPhysGetPageEx(pVM, GCPhysCR3, &pPage);
1511 if (RT_SUCCESS(rc))
1512 {
1513 RTHCPTR HCPtrGuestCR3;
1514 rc = pgmPhysGCPhys2CCPtrInternalDepr(pVM, pPage, GCPhysCR3, (void **)&HCPtrGuestCR3);
1515 if (RT_SUCCESS(rc))
1516 {
1517 pVCpu->pgm.s.pGst32BitPdR3 = (R3PTRTYPE(PX86PD))HCPtrGuestCR3;
1518# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1519 pVCpu->pgm.s.pGst32BitPdR0 = (R0PTRTYPE(PX86PD))HCPtrGuestCR3;
1520# endif
1521 *ppPd = (PX86PD)HCPtrGuestCR3;
1522
1523 pgmUnlock(pVM);
1524 return VINF_SUCCESS;
1525 }
1526
1527 AssertRC(rc);
1528 }
1529 pgmUnlock(pVM);
1530
1531 *ppPd = NULL;
1532 return rc;
1533}
1534
1535
1536/**
1537 * Performs the lazy mapping of the PAE guest PDPT.
1538 *
1539 * @returns VBox status code.
1540 * @param pVCpu The current CPU.
1541 * @param ppPdpt Where to return the pointer to the mapping. This is
1542 * always set.
1543 */
1544int pgmGstLazyMapPaePDPT(PVMCPU pVCpu, PX86PDPT *ppPdpt)
1545{
1546 Assert(!pVCpu->pgm.s.CTX_SUFF(pGstPaePdpt));
1547 PVM pVM = pVCpu->CTX_SUFF(pVM);
1548 pgmLock(pVM);
1549
1550 RTGCPHYS GCPhysCR3 = pVCpu->pgm.s.GCPhysCR3 & X86_CR3_PAE_PAGE_MASK;
1551 PPGMPAGE pPage;
1552 int rc = pgmPhysGetPageEx(pVM, GCPhysCR3, &pPage);
1553 if (RT_SUCCESS(rc))
1554 {
1555 RTHCPTR HCPtrGuestCR3;
1556 rc = pgmPhysGCPhys2CCPtrInternalDepr(pVM, pPage, GCPhysCR3, (void **)&HCPtrGuestCR3);
1557 if (RT_SUCCESS(rc))
1558 {
1559 pVCpu->pgm.s.pGstPaePdptR3 = (R3PTRTYPE(PX86PDPT))HCPtrGuestCR3;
1560# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1561 pVCpu->pgm.s.pGstPaePdptR0 = (R0PTRTYPE(PX86PDPT))HCPtrGuestCR3;
1562# endif
1563 *ppPdpt = (PX86PDPT)HCPtrGuestCR3;
1564
1565 pgmUnlock(pVM);
1566 return VINF_SUCCESS;
1567 }
1568
1569 AssertRC(rc);
1570 }
1571
1572 pgmUnlock(pVM);
1573 *ppPdpt = NULL;
1574 return rc;
1575}
1576
1577
1578/**
1579 * Performs the lazy mapping / updating of a PAE guest PD.
1580 *
1581 * @returns Pointer to the mapping.
1582 * @returns VBox status code.
1583 * @param pVCpu The current CPU.
1584 * @param iPdpt Which PD entry to map (0..3).
1585 * @param ppPd Where to return the pointer to the mapping. This is
1586 * always set.
1587 */
1588int pgmGstLazyMapPaePD(PVMCPU pVCpu, uint32_t iPdpt, PX86PDPAE *ppPd)
1589{
1590 PVM pVM = pVCpu->CTX_SUFF(pVM);
1591 pgmLock(pVM);
1592
1593 PX86PDPT pGuestPDPT = pVCpu->pgm.s.CTX_SUFF(pGstPaePdpt);
1594 Assert(pGuestPDPT);
1595 Assert(pGuestPDPT->a[iPdpt].n.u1Present);
1596 RTGCPHYS GCPhys = pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK;
1597 bool const fChanged = pVCpu->pgm.s.aGCPhysGstPaePDs[iPdpt] != GCPhys;
1598
1599 PPGMPAGE pPage;
1600 int rc = pgmPhysGetPageEx(pVM, GCPhys, &pPage);
1601 if (RT_SUCCESS(rc))
1602 {
1603 RTRCPTR RCPtr = NIL_RTRCPTR;
1604 RTHCPTR HCPtr = NIL_RTHCPTR;
1605#if !defined(IN_RC) && !defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1606 rc = pgmPhysGCPhys2CCPtrInternalDepr(pVM, pPage, GCPhys, &HCPtr);
1607 AssertRC(rc);
1608#endif
1609 if (RT_SUCCESS(rc) && fChanged)
1610 {
1611 RCPtr = (RTRCPTR)(RTRCUINTPTR)(pVM->pgm.s.GCPtrCR3Mapping + (1 + iPdpt) * PAGE_SIZE);
1612 rc = PGMMap(pVM, (RTRCUINTPTR)RCPtr, PGM_PAGE_GET_HCPHYS(pPage), PAGE_SIZE, 0);
1613 }
1614 if (RT_SUCCESS(rc))
1615 {
1616 pVCpu->pgm.s.apGstPaePDsR3[iPdpt] = (R3PTRTYPE(PX86PDPAE))HCPtr;
1617# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1618 pVCpu->pgm.s.apGstPaePDsR0[iPdpt] = (R0PTRTYPE(PX86PDPAE))HCPtr;
1619# endif
1620 if (fChanged)
1621 {
1622 pVCpu->pgm.s.aGCPhysGstPaePDs[iPdpt] = GCPhys;
1623 pVCpu->pgm.s.apGstPaePDsRC[iPdpt] = (RCPTRTYPE(PX86PDPAE))RCPtr;
1624 }
1625
1626 *ppPd = pVCpu->pgm.s.CTX_SUFF(apGstPaePDs)[iPdpt];
1627 pgmUnlock(pVM);
1628 return VINF_SUCCESS;
1629 }
1630 }
1631
1632 /* Invalid page or some failure, invalidate the entry. */
1633 pVCpu->pgm.s.aGCPhysGstPaePDs[iPdpt] = NIL_RTGCPHYS;
1634 pVCpu->pgm.s.apGstPaePDsR3[iPdpt] = 0;
1635# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1636 pVCpu->pgm.s.apGstPaePDsR0[iPdpt] = 0;
1637# endif
1638 pVCpu->pgm.s.apGstPaePDsRC[iPdpt] = 0;
1639
1640 pgmUnlock(pVM);
1641 return rc;
1642}
1643
1644#endif /* !VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
1645#if !defined(IN_RC) && !defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1646/**
1647 * Performs the lazy mapping of the 32-bit guest PD.
1648 *
1649 * @returns VBox status code.
1650 * @param pVCpu The current CPU.
1651 * @param ppPml4 Where to return the pointer to the mapping. This will
1652 * always be set.
1653 */
1654int pgmGstLazyMapPml4(PVMCPU pVCpu, PX86PML4 *ppPml4)
1655{
1656 Assert(!pVCpu->pgm.s.CTX_SUFF(pGstAmd64Pml4));
1657 PVM pVM = pVCpu->CTX_SUFF(pVM);
1658 pgmLock(pVM);
1659
1660 RTGCPHYS GCPhysCR3 = pVCpu->pgm.s.GCPhysCR3 & X86_CR3_AMD64_PAGE_MASK;
1661 PPGMPAGE pPage;
1662 int rc = pgmPhysGetPageEx(pVM, GCPhysCR3, &pPage);
1663 if (RT_SUCCESS(rc))
1664 {
1665 RTHCPTR HCPtrGuestCR3;
1666 rc = pgmPhysGCPhys2CCPtrInternalDepr(pVM, pPage, GCPhysCR3, (void **)&HCPtrGuestCR3);
1667 if (RT_SUCCESS(rc))
1668 {
1669 pVCpu->pgm.s.pGstAmd64Pml4R3 = (R3PTRTYPE(PX86PML4))HCPtrGuestCR3;
1670# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1671 pVCpu->pgm.s.pGstAmd64Pml4R0 = (R0PTRTYPE(PX86PML4))HCPtrGuestCR3;
1672# endif
1673 *ppPml4 = (PX86PML4)HCPtrGuestCR3;
1674
1675 pgmUnlock(pVM);
1676 return VINF_SUCCESS;
1677 }
1678 }
1679
1680 pgmUnlock(pVM);
1681 *ppPml4 = NULL;
1682 return rc;
1683}
1684#endif
1685
1686
1687/**
1688 * Gets the PAE PDPEs values cached by the CPU.
1689 *
1690 * @returns VBox status code.
1691 * @param pVCpu Pointer to the VMCPU.
1692 * @param paPdpes Where to return the four PDPEs. The array
1693 * pointed to must have 4 entries.
1694 */
1695VMM_INT_DECL(int) PGMGstGetPaePdpes(PVMCPU pVCpu, PX86PDPE paPdpes)
1696{
1697 Assert(pVCpu->pgm.s.enmShadowMode == PGMMODE_EPT);
1698
1699 paPdpes[0] = pVCpu->pgm.s.aGstPaePdpeRegs[0];
1700 paPdpes[1] = pVCpu->pgm.s.aGstPaePdpeRegs[1];
1701 paPdpes[2] = pVCpu->pgm.s.aGstPaePdpeRegs[2];
1702 paPdpes[3] = pVCpu->pgm.s.aGstPaePdpeRegs[3];
1703 return VINF_SUCCESS;
1704}
1705
1706
1707/**
1708 * Sets the PAE PDPEs values cached by the CPU.
1709 *
1710 * @remarks This must be called *AFTER* PGMUpdateCR3.
1711 *
1712 * @returns VBox status code.
1713 * @param pVCpu Pointer to the VMCPU.
1714 * @param paPdpes The four PDPE values. The array pointed to must
1715 * have exactly 4 entries.
1716 *
1717 * @remarks No-long-jump zone!!!
1718 */
1719VMM_INT_DECL(int) PGMGstUpdatePaePdpes(PVMCPU pVCpu, PCX86PDPE paPdpes)
1720{
1721 Assert(pVCpu->pgm.s.enmShadowMode == PGMMODE_EPT);
1722
1723 for (unsigned i = 0; i < RT_ELEMENTS(pVCpu->pgm.s.aGstPaePdpeRegs); i++)
1724 {
1725 if (pVCpu->pgm.s.aGstPaePdpeRegs[i].u != paPdpes[i].u)
1726 {
1727 pVCpu->pgm.s.aGstPaePdpeRegs[i] = paPdpes[i];
1728
1729 /* Force lazy remapping if it changed in any way. */
1730 pVCpu->pgm.s.apGstPaePDsR3[i] = 0;
1731# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1732 pVCpu->pgm.s.apGstPaePDsR0[i] = 0;
1733# endif
1734 pVCpu->pgm.s.apGstPaePDsRC[i] = 0;
1735 pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
1736 }
1737 }
1738
1739 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES);
1740 return VINF_SUCCESS;
1741}
1742
1743
1744/**
1745 * Gets the current CR3 register value for the shadow memory context.
1746 * @returns CR3 value.
1747 * @param pVCpu Pointer to the VMCPU.
1748 */
1749VMMDECL(RTHCPHYS) PGMGetHyperCR3(PVMCPU pVCpu)
1750{
1751 PPGMPOOLPAGE pPoolPage = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
1752 AssertPtrReturn(pPoolPage, 0);
1753 return pPoolPage->Core.Key;
1754}
1755
1756
1757/**
1758 * Gets the current CR3 register value for the nested memory context.
1759 * @returns CR3 value.
1760 * @param pVCpu Pointer to the VMCPU.
1761 */
1762VMMDECL(RTHCPHYS) PGMGetNestedCR3(PVMCPU pVCpu, PGMMODE enmShadowMode)
1763{
1764 NOREF(enmShadowMode);
1765 Assert(pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
1766 return pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->Core.Key;
1767}
1768
1769
1770/**
1771 * Gets the current CR3 register value for the HC intermediate memory context.
1772 * @returns CR3 value.
1773 * @param pVM Pointer to the VM.
1774 */
1775VMMDECL(RTHCPHYS) PGMGetInterHCCR3(PVM pVM)
1776{
1777 switch (pVM->pgm.s.enmHostMode)
1778 {
1779 case SUPPAGINGMODE_32_BIT:
1780 case SUPPAGINGMODE_32_BIT_GLOBAL:
1781 return pVM->pgm.s.HCPhysInterPD;
1782
1783 case SUPPAGINGMODE_PAE:
1784 case SUPPAGINGMODE_PAE_GLOBAL:
1785 case SUPPAGINGMODE_PAE_NX:
1786 case SUPPAGINGMODE_PAE_GLOBAL_NX:
1787 return pVM->pgm.s.HCPhysInterPaePDPT;
1788
1789 case SUPPAGINGMODE_AMD64:
1790 case SUPPAGINGMODE_AMD64_GLOBAL:
1791 case SUPPAGINGMODE_AMD64_NX:
1792 case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1793 return pVM->pgm.s.HCPhysInterPaePDPT;
1794
1795 default:
1796 AssertMsgFailed(("enmHostMode=%d\n", pVM->pgm.s.enmHostMode));
1797 return NIL_RTHCPHYS;
1798 }
1799}
1800
1801
1802/**
1803 * Gets the current CR3 register value for the RC intermediate memory context.
1804 * @returns CR3 value.
1805 * @param pVM Pointer to the VM.
1806 * @param pVCpu Pointer to the VMCPU.
1807 */
1808VMMDECL(RTHCPHYS) PGMGetInterRCCR3(PVM pVM, PVMCPU pVCpu)
1809{
1810 switch (pVCpu->pgm.s.enmShadowMode)
1811 {
1812 case PGMMODE_32_BIT:
1813 return pVM->pgm.s.HCPhysInterPD;
1814
1815 case PGMMODE_PAE:
1816 case PGMMODE_PAE_NX:
1817 return pVM->pgm.s.HCPhysInterPaePDPT;
1818
1819 case PGMMODE_AMD64:
1820 case PGMMODE_AMD64_NX:
1821 return pVM->pgm.s.HCPhysInterPaePML4;
1822
1823 case PGMMODE_EPT:
1824 case PGMMODE_NESTED:
1825 return 0; /* not relevant */
1826
1827 default:
1828 AssertMsgFailed(("enmShadowMode=%d\n", pVCpu->pgm.s.enmShadowMode));
1829 return NIL_RTHCPHYS;
1830 }
1831}
1832
1833
1834/**
1835 * Gets the CR3 register value for the 32-Bit intermediate memory context.
1836 * @returns CR3 value.
1837 * @param pVM Pointer to the VM.
1838 */
1839VMMDECL(RTHCPHYS) PGMGetInter32BitCR3(PVM pVM)
1840{
1841 return pVM->pgm.s.HCPhysInterPD;
1842}
1843
1844
1845/**
1846 * Gets the CR3 register value for the PAE intermediate memory context.
1847 * @returns CR3 value.
1848 * @param pVM Pointer to the VM.
1849 */
1850VMMDECL(RTHCPHYS) PGMGetInterPaeCR3(PVM pVM)
1851{
1852 return pVM->pgm.s.HCPhysInterPaePDPT;
1853}
1854
1855
1856/**
1857 * Gets the CR3 register value for the AMD64 intermediate memory context.
1858 * @returns CR3 value.
1859 * @param pVM Pointer to the VM.
1860 */
1861VMMDECL(RTHCPHYS) PGMGetInterAmd64CR3(PVM pVM)
1862{
1863 return pVM->pgm.s.HCPhysInterPaePML4;
1864}
1865
1866
1867/**
1868 * Performs and schedules necessary updates following a CR3 load or reload.
1869 *
1870 * This will normally involve mapping the guest PD or nPDPT
1871 *
1872 * @returns VBox status code.
1873 * @retval VINF_PGM_SYNC_CR3 if monitoring requires a CR3 sync. This can
1874 * safely be ignored and overridden since the FF will be set too then.
1875 * @param pVCpu Pointer to the VMCPU.
1876 * @param cr3 The new cr3.
1877 * @param fGlobal Indicates whether this is a global flush or not.
1878 */
1879VMMDECL(int) PGMFlushTLB(PVMCPU pVCpu, uint64_t cr3, bool fGlobal)
1880{
1881 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FlushTLB), a);
1882 PVM pVM = pVCpu->CTX_SUFF(pVM);
1883
1884 VMCPU_ASSERT_EMT(pVCpu);
1885
1886 /*
1887 * Always flag the necessary updates; necessary for hardware acceleration
1888 */
1889 /** @todo optimize this, it shouldn't always be necessary. */
1890 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
1891 if (fGlobal)
1892 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
1893 LogFlow(("PGMFlushTLB: cr3=%RX64 OldCr3=%RX64 fGlobal=%d\n", cr3, pVCpu->pgm.s.GCPhysCR3, fGlobal));
1894
1895 /*
1896 * Remap the CR3 content and adjust the monitoring if CR3 was actually changed.
1897 */
1898 int rc = VINF_SUCCESS;
1899 RTGCPHYS GCPhysCR3;
1900 switch (pVCpu->pgm.s.enmGuestMode)
1901 {
1902 case PGMMODE_PAE:
1903 case PGMMODE_PAE_NX:
1904 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAE_PAGE_MASK);
1905 break;
1906 case PGMMODE_AMD64:
1907 case PGMMODE_AMD64_NX:
1908 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_AMD64_PAGE_MASK);
1909 break;
1910 default:
1911 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAGE_MASK);
1912 break;
1913 }
1914 PGM_A20_APPLY_TO_VAR(pVCpu, GCPhysCR3);
1915
1916 if (pVCpu->pgm.s.GCPhysCR3 != GCPhysCR3)
1917 {
1918 RTGCPHYS GCPhysOldCR3 = pVCpu->pgm.s.GCPhysCR3;
1919 pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3;
1920 rc = PGM_BTH_PFN(MapCR3, pVCpu)(pVCpu, GCPhysCR3);
1921 if (RT_LIKELY(rc == VINF_SUCCESS))
1922 {
1923 if (pgmMapAreMappingsFloating(pVM))
1924 pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
1925 }
1926 else
1927 {
1928 AssertMsg(rc == VINF_PGM_SYNC_CR3, ("%Rrc\n", rc));
1929 Assert(VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL | VMCPU_FF_PGM_SYNC_CR3));
1930 pVCpu->pgm.s.GCPhysCR3 = GCPhysOldCR3;
1931 pVCpu->pgm.s.fSyncFlags |= PGM_SYNC_MAP_CR3;
1932 if (pgmMapAreMappingsFloating(pVM))
1933 pVCpu->pgm.s.fSyncFlags |= PGM_SYNC_MONITOR_CR3;
1934 }
1935
1936 if (fGlobal)
1937 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FlushTLBNewCR3Global));
1938 else
1939 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FlushTLBNewCR3));
1940 }
1941 else
1942 {
1943# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
1944 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1945 if (pPool->cDirtyPages)
1946 {
1947 pgmLock(pVM);
1948 pgmPoolResetDirtyPages(pVM);
1949 pgmUnlock(pVM);
1950 }
1951# endif
1952 /*
1953 * Check if we have a pending update of the CR3 monitoring.
1954 */
1955 if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
1956 {
1957 pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
1958 Assert(!pVM->pgm.s.fMappingsFixed); Assert(pgmMapAreMappingsEnabled(pVM));
1959 }
1960 if (fGlobal)
1961 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FlushTLBSameCR3Global));
1962 else
1963 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FlushTLBSameCR3));
1964 }
1965
1966 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FlushTLB), a);
1967 return rc;
1968}
1969
1970
1971/**
1972 * Performs and schedules necessary updates following a CR3 load or reload when
1973 * using nested or extended paging.
1974 *
1975 * This API is an alternative to PDMFlushTLB that avoids actually flushing the
1976 * TLB and triggering a SyncCR3.
1977 *
1978 * This will normally involve mapping the guest PD or nPDPT
1979 *
1980 * @returns VBox status code.
1981 * @retval VINF_SUCCESS.
1982 * @retval (If applied when not in nested mode: VINF_PGM_SYNC_CR3 if monitoring
1983 * requires a CR3 sync. This can safely be ignored and overridden since
1984 * the FF will be set too then.)
1985 * @param pVCpu Pointer to the VMCPU.
1986 * @param cr3 The new cr3.
1987 */
1988VMMDECL(int) PGMUpdateCR3(PVMCPU pVCpu, uint64_t cr3)
1989{
1990 VMCPU_ASSERT_EMT(pVCpu);
1991 LogFlow(("PGMUpdateCR3: cr3=%RX64 OldCr3=%RX64\n", cr3, pVCpu->pgm.s.GCPhysCR3));
1992
1993 /* We assume we're only called in nested paging mode. */
1994 Assert(pVCpu->CTX_SUFF(pVM)->pgm.s.fNestedPaging || pVCpu->pgm.s.enmShadowMode == PGMMODE_EPT);
1995 Assert(!pgmMapAreMappingsEnabled(pVCpu->CTX_SUFF(pVM)));
1996 Assert(!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3));
1997
1998 /*
1999 * Remap the CR3 content and adjust the monitoring if CR3 was actually changed.
2000 */
2001 int rc = VINF_SUCCESS;
2002 RTGCPHYS GCPhysCR3;
2003 switch (pVCpu->pgm.s.enmGuestMode)
2004 {
2005 case PGMMODE_PAE:
2006 case PGMMODE_PAE_NX:
2007 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAE_PAGE_MASK);
2008 break;
2009 case PGMMODE_AMD64:
2010 case PGMMODE_AMD64_NX:
2011 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_AMD64_PAGE_MASK);
2012 break;
2013 default:
2014 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAGE_MASK);
2015 break;
2016 }
2017 PGM_A20_APPLY_TO_VAR(pVCpu, GCPhysCR3);
2018
2019 if (pVCpu->pgm.s.GCPhysCR3 != GCPhysCR3)
2020 {
2021 pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3;
2022 rc = PGM_BTH_PFN(MapCR3, pVCpu)(pVCpu, GCPhysCR3);
2023 AssertRCSuccess(rc); /* Assumes VINF_PGM_SYNC_CR3 doesn't apply to nested paging. */ /** @todo this isn't true for the mac, but we need hw to test/fix this. */
2024 }
2025
2026 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_HM_UPDATE_CR3);
2027 return rc;
2028}
2029
2030
2031/**
2032 * Synchronize the paging structures.
2033 *
2034 * This function is called in response to the VM_FF_PGM_SYNC_CR3 and
2035 * VM_FF_PGM_SYNC_CR3_NONGLOBAL. Those two force action flags are set
2036 * in several places, most importantly whenever the CR3 is loaded.
2037 *
2038 * @returns VBox status code.
2039 * @param pVCpu Pointer to the VMCPU.
2040 * @param cr0 Guest context CR0 register
2041 * @param cr3 Guest context CR3 register
2042 * @param cr4 Guest context CR4 register
2043 * @param fGlobal Including global page directories or not
2044 */
2045VMMDECL(int) PGMSyncCR3(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
2046{
2047 int rc;
2048
2049 VMCPU_ASSERT_EMT(pVCpu);
2050
2051 /*
2052 * The pool may have pending stuff and even require a return to ring-3 to
2053 * clear the whole thing.
2054 */
2055 rc = pgmPoolSyncCR3(pVCpu);
2056 if (rc != VINF_SUCCESS)
2057 return rc;
2058
2059 /*
2060 * We might be called when we shouldn't.
2061 *
2062 * The mode switching will ensure that the PD is resynced after every mode
2063 * switch. So, if we find ourselves here when in protected or real mode
2064 * we can safely clear the FF and return immediately.
2065 */
2066 if (pVCpu->pgm.s.enmGuestMode <= PGMMODE_PROTECTED)
2067 {
2068 Assert((cr0 & (X86_CR0_PG | X86_CR0_PE)) != (X86_CR0_PG | X86_CR0_PE));
2069 Assert(!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL));
2070 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2071 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
2072 return VINF_SUCCESS;
2073 }
2074
2075 /* If global pages are not supported, then all flushes are global. */
2076 if (!(cr4 & X86_CR4_PGE))
2077 fGlobal = true;
2078 LogFlow(("PGMSyncCR3: cr0=%RX64 cr3=%RX64 cr4=%RX64 fGlobal=%d[%d,%d]\n", cr0, cr3, cr4, fGlobal,
2079 VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3), VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)));
2080
2081 /*
2082 * Check if we need to finish an aborted MapCR3 call (see PGMFlushTLB).
2083 * This should be done before SyncCR3.
2084 */
2085 if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MAP_CR3)
2086 {
2087 pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MAP_CR3;
2088
2089 RTGCPHYS GCPhysCR3Old = pVCpu->pgm.s.GCPhysCR3; NOREF(GCPhysCR3Old);
2090 RTGCPHYS GCPhysCR3;
2091 switch (pVCpu->pgm.s.enmGuestMode)
2092 {
2093 case PGMMODE_PAE:
2094 case PGMMODE_PAE_NX:
2095 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAE_PAGE_MASK);
2096 break;
2097 case PGMMODE_AMD64:
2098 case PGMMODE_AMD64_NX:
2099 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_AMD64_PAGE_MASK);
2100 break;
2101 default:
2102 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAGE_MASK);
2103 break;
2104 }
2105 PGM_A20_APPLY_TO_VAR(pVCpu, GCPhysCR3);
2106
2107 if (pVCpu->pgm.s.GCPhysCR3 != GCPhysCR3)
2108 {
2109 pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3;
2110 rc = PGM_BTH_PFN(MapCR3, pVCpu)(pVCpu, GCPhysCR3);
2111 }
2112
2113 /* Make sure we check for pending pgm pool syncs as we clear VMCPU_FF_PGM_SYNC_CR3 later on! */
2114 if ( rc == VINF_PGM_SYNC_CR3
2115 || (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL))
2116 {
2117 Log(("PGMSyncCR3: pending pgm pool sync after MapCR3!\n"));
2118#ifdef IN_RING3
2119 rc = pgmPoolSyncCR3(pVCpu);
2120#else
2121 if (rc == VINF_PGM_SYNC_CR3)
2122 pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3Old;
2123 return VINF_PGM_SYNC_CR3;
2124#endif
2125 }
2126 AssertRCReturn(rc, rc);
2127 AssertRCSuccessReturn(rc, VERR_IPE_UNEXPECTED_INFO_STATUS);
2128 }
2129
2130 /*
2131 * Let the 'Bth' function do the work and we'll just keep track of the flags.
2132 */
2133 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3), a);
2134 rc = PGM_BTH_PFN(SyncCR3, pVCpu)(pVCpu, cr0, cr3, cr4, fGlobal);
2135 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3), a);
2136 AssertMsg(rc == VINF_SUCCESS || rc == VINF_PGM_SYNC_CR3 || RT_FAILURE(rc), ("rc=%Rrc\n", rc));
2137 if (rc == VINF_SUCCESS)
2138 {
2139 if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL)
2140 {
2141 /* Go back to ring 3 if a pgm pool sync is again pending. */
2142 return VINF_PGM_SYNC_CR3;
2143 }
2144
2145 if (!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS))
2146 {
2147 Assert(!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL));
2148 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2149 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
2150 }
2151
2152 /*
2153 * Check if we have a pending update of the CR3 monitoring.
2154 */
2155 if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
2156 {
2157 pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
2158 Assert(!pVCpu->CTX_SUFF(pVM)->pgm.s.fMappingsFixed);
2159 Assert(pgmMapAreMappingsEnabled(pVCpu->CTX_SUFF(pVM)));
2160 }
2161 }
2162
2163 /*
2164 * Now flush the CR3 (guest context).
2165 */
2166 if (rc == VINF_SUCCESS)
2167 PGM_INVL_VCPU_TLBS(pVCpu);
2168 return rc;
2169}
2170
2171
2172/**
2173 * Called whenever CR0 or CR4 in a way which may affect the paging mode.
2174 *
2175 * @returns VBox status code, with the following informational code for
2176 * VM scheduling.
2177 * @retval VINF_SUCCESS if the was no change, or it was successfully dealt with.
2178 * @retval VINF_PGM_CHANGE_MODE if we're in RC or R0 and the mode changes.
2179 * (I.e. not in R3.)
2180 * @retval VINF_EM_SUSPEND or VINF_EM_OFF on a fatal runtime error. (R3 only)
2181 *
2182 * @param pVCpu Pointer to the VMCPU.
2183 * @param cr0 The new cr0.
2184 * @param cr4 The new cr4.
2185 * @param efer The new extended feature enable register.
2186 */
2187VMMDECL(int) PGMChangeMode(PVMCPU pVCpu, uint64_t cr0, uint64_t cr4, uint64_t efer)
2188{
2189 PGMMODE enmGuestMode;
2190
2191 VMCPU_ASSERT_EMT(pVCpu);
2192
2193 /*
2194 * Calc the new guest mode.
2195 */
2196 if (!(cr0 & X86_CR0_PE))
2197 enmGuestMode = PGMMODE_REAL;
2198 else if (!(cr0 & X86_CR0_PG))
2199 enmGuestMode = PGMMODE_PROTECTED;
2200 else if (!(cr4 & X86_CR4_PAE))
2201 {
2202 bool const fPse = !!(cr4 & X86_CR4_PSE);
2203 if (pVCpu->pgm.s.fGst32BitPageSizeExtension != fPse)
2204 Log(("PGMChangeMode: CR4.PSE %d -> %d\n", pVCpu->pgm.s.fGst32BitPageSizeExtension, fPse));
2205 pVCpu->pgm.s.fGst32BitPageSizeExtension = fPse;
2206 enmGuestMode = PGMMODE_32_BIT;
2207 }
2208 else if (!(efer & MSR_K6_EFER_LME))
2209 {
2210 if (!(efer & MSR_K6_EFER_NXE))
2211 enmGuestMode = PGMMODE_PAE;
2212 else
2213 enmGuestMode = PGMMODE_PAE_NX;
2214 }
2215 else
2216 {
2217 if (!(efer & MSR_K6_EFER_NXE))
2218 enmGuestMode = PGMMODE_AMD64;
2219 else
2220 enmGuestMode = PGMMODE_AMD64_NX;
2221 }
2222
2223 /*
2224 * Did it change?
2225 */
2226 if (pVCpu->pgm.s.enmGuestMode == enmGuestMode)
2227 return VINF_SUCCESS;
2228
2229 /* Flush the TLB */
2230 PGM_INVL_VCPU_TLBS(pVCpu);
2231
2232#ifdef IN_RING3
2233 return PGMR3ChangeMode(pVCpu->CTX_SUFF(pVM), pVCpu, enmGuestMode);
2234#else
2235 LogFlow(("PGMChangeMode: returns VINF_PGM_CHANGE_MODE.\n"));
2236 return VINF_PGM_CHANGE_MODE;
2237#endif
2238}
2239
2240
2241/**
2242 * Called by CPUM or REM when CR0.WP changes to 1.
2243 *
2244 * @param pVCpu The cross context virtual CPU structure of the caller.
2245 * @thread EMT
2246 */
2247VMMDECL(void) PGMCr0WpEnabled(PVMCPU pVCpu)
2248{
2249 /*
2250 * Netware WP0+RO+US hack cleanup when WP0 -> WP1.
2251 *
2252 * Use the counter to judge whether there might be pool pages with active
2253 * hacks in them. If there are, we will be running the risk of messing up
2254 * the guest by allowing it to write to read-only pages. Thus, we have to
2255 * clear the page pool ASAP if there is the slightest chance.
2256 */
2257 if (pVCpu->pgm.s.cNetwareWp0Hacks > 0)
2258 {
2259 Assert(pVCpu->CTX_SUFF(pVM)->cCpus == 1);
2260
2261 Log(("PGMCr0WpEnabled: %llu WP0 hacks active - clearing page pool\n", pVCpu->pgm.s.cNetwareWp0Hacks));
2262 pVCpu->pgm.s.cNetwareWp0Hacks = 0;
2263 pVCpu->pgm.s.fSyncFlags |= PGM_SYNC_CLEAR_PGM_POOL;
2264 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2265 }
2266}
2267
2268
2269/**
2270 * Gets the current guest paging mode.
2271 *
2272 * If you just need the CPU mode (real/protected/long), use CPUMGetGuestMode().
2273 *
2274 * @returns The current paging mode.
2275 * @param pVCpu Pointer to the VMCPU.
2276 */
2277VMMDECL(PGMMODE) PGMGetGuestMode(PVMCPU pVCpu)
2278{
2279 return pVCpu->pgm.s.enmGuestMode;
2280}
2281
2282
2283/**
2284 * Gets the current shadow paging mode.
2285 *
2286 * @returns The current paging mode.
2287 * @param pVCpu Pointer to the VMCPU.
2288 */
2289VMMDECL(PGMMODE) PGMGetShadowMode(PVMCPU pVCpu)
2290{
2291 return pVCpu->pgm.s.enmShadowMode;
2292}
2293
2294
2295/**
2296 * Gets the current host paging mode.
2297 *
2298 * @returns The current paging mode.
2299 * @param pVM Pointer to the VM.
2300 */
2301VMMDECL(PGMMODE) PGMGetHostMode(PVM pVM)
2302{
2303 switch (pVM->pgm.s.enmHostMode)
2304 {
2305 case SUPPAGINGMODE_32_BIT:
2306 case SUPPAGINGMODE_32_BIT_GLOBAL:
2307 return PGMMODE_32_BIT;
2308
2309 case SUPPAGINGMODE_PAE:
2310 case SUPPAGINGMODE_PAE_GLOBAL:
2311 return PGMMODE_PAE;
2312
2313 case SUPPAGINGMODE_PAE_NX:
2314 case SUPPAGINGMODE_PAE_GLOBAL_NX:
2315 return PGMMODE_PAE_NX;
2316
2317 case SUPPAGINGMODE_AMD64:
2318 case SUPPAGINGMODE_AMD64_GLOBAL:
2319 return PGMMODE_AMD64;
2320
2321 case SUPPAGINGMODE_AMD64_NX:
2322 case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2323 return PGMMODE_AMD64_NX;
2324
2325 default: AssertMsgFailed(("enmHostMode=%d\n", pVM->pgm.s.enmHostMode)); break;
2326 }
2327
2328 return PGMMODE_INVALID;
2329}
2330
2331
2332/**
2333 * Get mode name.
2334 *
2335 * @returns read-only name string.
2336 * @param enmMode The mode which name is desired.
2337 */
2338VMMDECL(const char *) PGMGetModeName(PGMMODE enmMode)
2339{
2340 switch (enmMode)
2341 {
2342 case PGMMODE_REAL: return "Real";
2343 case PGMMODE_PROTECTED: return "Protected";
2344 case PGMMODE_32_BIT: return "32-bit";
2345 case PGMMODE_PAE: return "PAE";
2346 case PGMMODE_PAE_NX: return "PAE+NX";
2347 case PGMMODE_AMD64: return "AMD64";
2348 case PGMMODE_AMD64_NX: return "AMD64+NX";
2349 case PGMMODE_NESTED: return "Nested";
2350 case PGMMODE_EPT: return "EPT";
2351 default: return "unknown mode value";
2352 }
2353}
2354
2355
2356
2357/**
2358 * Notification from CPUM that the EFER.NXE bit has changed.
2359 *
2360 * @param pVCpu The virtual CPU for which EFER changed.
2361 * @param fNxe The new NXE state.
2362 */
2363VMM_INT_DECL(void) PGMNotifyNxeChanged(PVMCPU pVCpu, bool fNxe)
2364{
2365/** @todo VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu); */
2366 Log(("PGMNotifyNxeChanged: fNxe=%RTbool\n", fNxe));
2367
2368 pVCpu->pgm.s.fNoExecuteEnabled = fNxe;
2369 if (fNxe)
2370 {
2371 /*pVCpu->pgm.s.fGst32BitMbzBigPdeMask - N/A */
2372 pVCpu->pgm.s.fGstPaeMbzPteMask &= ~X86_PTE_PAE_NX;
2373 pVCpu->pgm.s.fGstPaeMbzPdeMask &= ~X86_PDE_PAE_NX;
2374 pVCpu->pgm.s.fGstPaeMbzBigPdeMask &= ~X86_PDE2M_PAE_NX;
2375 /*pVCpu->pgm.s.fGstPaeMbzPdpeMask - N/A */
2376 pVCpu->pgm.s.fGstAmd64MbzPteMask &= ~X86_PTE_PAE_NX;
2377 pVCpu->pgm.s.fGstAmd64MbzPdeMask &= ~X86_PDE_PAE_NX;
2378 pVCpu->pgm.s.fGstAmd64MbzBigPdeMask &= ~X86_PDE2M_PAE_NX;
2379 pVCpu->pgm.s.fGstAmd64MbzPdpeMask &= ~X86_PDPE_LM_NX;
2380 pVCpu->pgm.s.fGstAmd64MbzBigPdpeMask &= ~X86_PDPE_LM_NX;
2381 pVCpu->pgm.s.fGstAmd64MbzPml4eMask &= ~X86_PML4E_NX;
2382
2383 pVCpu->pgm.s.fGst64ShadowedPteMask |= X86_PTE_PAE_NX;
2384 pVCpu->pgm.s.fGst64ShadowedPdeMask |= X86_PDE_PAE_NX;
2385 pVCpu->pgm.s.fGst64ShadowedBigPdeMask |= X86_PDE2M_PAE_NX;
2386 pVCpu->pgm.s.fGst64ShadowedBigPde4PteMask |= X86_PDE2M_PAE_NX;
2387 pVCpu->pgm.s.fGstAmd64ShadowedPdpeMask |= X86_PDPE_LM_NX;
2388 pVCpu->pgm.s.fGstAmd64ShadowedPml4eMask |= X86_PML4E_NX;
2389 }
2390 else
2391 {
2392 /*pVCpu->pgm.s.fGst32BitMbzBigPdeMask - N/A */
2393 pVCpu->pgm.s.fGstPaeMbzPteMask |= X86_PTE_PAE_NX;
2394 pVCpu->pgm.s.fGstPaeMbzPdeMask |= X86_PDE_PAE_NX;
2395 pVCpu->pgm.s.fGstPaeMbzBigPdeMask |= X86_PDE2M_PAE_NX;
2396 /*pVCpu->pgm.s.fGstPaeMbzPdpeMask -N/A */
2397 pVCpu->pgm.s.fGstAmd64MbzPteMask |= X86_PTE_PAE_NX;
2398 pVCpu->pgm.s.fGstAmd64MbzPdeMask |= X86_PDE_PAE_NX;
2399 pVCpu->pgm.s.fGstAmd64MbzBigPdeMask |= X86_PDE2M_PAE_NX;
2400 pVCpu->pgm.s.fGstAmd64MbzPdpeMask |= X86_PDPE_LM_NX;
2401 pVCpu->pgm.s.fGstAmd64MbzBigPdpeMask |= X86_PDPE_LM_NX;
2402 pVCpu->pgm.s.fGstAmd64MbzPml4eMask |= X86_PML4E_NX;
2403
2404 pVCpu->pgm.s.fGst64ShadowedPteMask &= ~X86_PTE_PAE_NX;
2405 pVCpu->pgm.s.fGst64ShadowedPdeMask &= ~X86_PDE_PAE_NX;
2406 pVCpu->pgm.s.fGst64ShadowedBigPdeMask &= ~X86_PDE2M_PAE_NX;
2407 pVCpu->pgm.s.fGst64ShadowedBigPde4PteMask &= ~X86_PDE2M_PAE_NX;
2408 pVCpu->pgm.s.fGstAmd64ShadowedPdpeMask &= ~X86_PDPE_LM_NX;
2409 pVCpu->pgm.s.fGstAmd64ShadowedPml4eMask &= ~X86_PML4E_NX;
2410 }
2411}
2412
2413
2414/**
2415 * Check if any pgm pool pages are marked dirty (not monitored)
2416 *
2417 * @returns bool locked/not locked
2418 * @param pVM Pointer to the VM.
2419 */
2420VMMDECL(bool) PGMHasDirtyPages(PVM pVM)
2421{
2422 return pVM->pgm.s.CTX_SUFF(pPool)->cDirtyPages != 0;
2423}
2424
2425
2426/**
2427 * Check if this VCPU currently owns the PGM lock.
2428 *
2429 * @returns bool owner/not owner
2430 * @param pVM Pointer to the VM.
2431 */
2432VMMDECL(bool) PGMIsLockOwner(PVM pVM)
2433{
2434 return PDMCritSectIsOwner(&pVM->pgm.s.CritSectX);
2435}
2436
2437
2438/**
2439 * Enable or disable large page usage
2440 *
2441 * @returns VBox status code.
2442 * @param pVM Pointer to the VM.
2443 * @param fUseLargePages Use/not use large pages
2444 */
2445VMMDECL(int) PGMSetLargePageUsage(PVM pVM, bool fUseLargePages)
2446{
2447 VM_ASSERT_VALID_EXT_RETURN(pVM, VERR_INVALID_VM_HANDLE);
2448
2449 pVM->fUseLargePages = fUseLargePages;
2450 return VINF_SUCCESS;
2451}
2452
2453
2454/**
2455 * Acquire the PGM lock.
2456 *
2457 * @returns VBox status code
2458 * @param pVM Pointer to the VM.
2459 */
2460#if defined(VBOX_STRICT) && defined(IN_RING3)
2461int pgmLockDebug(PVM pVM, RT_SRC_POS_DECL)
2462#else
2463int pgmLock(PVM pVM)
2464#endif
2465{
2466#if defined(VBOX_STRICT) && defined(IN_RING3)
2467 int rc = PDMCritSectEnterDebug(&pVM->pgm.s.CritSectX, VERR_SEM_BUSY, (uintptr_t)ASMReturnAddress(), RT_SRC_POS_ARGS);
2468#else
2469 int rc = PDMCritSectEnter(&pVM->pgm.s.CritSectX, VERR_SEM_BUSY);
2470#endif
2471#if defined(IN_RC) || defined(IN_RING0)
2472 if (rc == VERR_SEM_BUSY)
2473 rc = VMMRZCallRing3NoCpu(pVM, VMMCALLRING3_PGM_LOCK, 0);
2474#endif
2475 AssertMsg(rc == VINF_SUCCESS, ("%Rrc\n", rc));
2476 return rc;
2477}
2478
2479
2480/**
2481 * Release the PGM lock.
2482 *
2483 * @returns VBox status code
2484 * @param pVM Pointer to the VM.
2485 */
2486void pgmUnlock(PVM pVM)
2487{
2488 uint32_t cDeprecatedPageLocks = pVM->pgm.s.cDeprecatedPageLocks;
2489 pVM->pgm.s.cDeprecatedPageLocks = 0;
2490 int rc = PDMCritSectLeave(&pVM->pgm.s.CritSectX);
2491 if (rc == VINF_SEM_NESTED)
2492 pVM->pgm.s.cDeprecatedPageLocks = cDeprecatedPageLocks;
2493}
2494
2495#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2496
2497/**
2498 * Common worker for pgmRZDynMapGCPageOffInlined and pgmRZDynMapGCPageV2Inlined.
2499 *
2500 * @returns VBox status code.
2501 * @param pVM Pointer to the VM.
2502 * @param pVCpu The current CPU.
2503 * @param GCPhys The guest physical address of the page to map. The
2504 * offset bits are not ignored.
2505 * @param ppv Where to return the address corresponding to @a GCPhys.
2506 */
2507int pgmRZDynMapGCPageCommon(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void **ppv RTLOG_COMMA_SRC_POS_DECL)
2508{
2509 pgmLock(pVM);
2510
2511 /*
2512 * Convert it to a writable page and it on to the dynamic mapper.
2513 */
2514 int rc;
2515 PPGMPAGE pPage = pgmPhysGetPage(pVM, GCPhys);
2516 if (RT_LIKELY(pPage))
2517 {
2518 rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
2519 if (RT_SUCCESS(rc))
2520 {
2521 void *pv;
2522 rc = pgmRZDynMapHCPageInlined(pVCpu, PGM_PAGE_GET_HCPHYS(pPage), &pv RTLOG_COMMA_SRC_POS_ARGS);
2523 if (RT_SUCCESS(rc))
2524 *ppv = (void *)((uintptr_t)pv | ((uintptr_t)GCPhys & PAGE_OFFSET_MASK));
2525 }
2526 else
2527 AssertRC(rc);
2528 }
2529 else
2530 {
2531 AssertMsgFailed(("Invalid physical address %RGp!\n", GCPhys));
2532 rc = VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2533 }
2534
2535 pgmUnlock(pVM);
2536 return rc;
2537}
2538
2539#endif /* IN_RC || VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
2540#if !defined(IN_R0) || defined(LOG_ENABLED)
2541
2542/** Format handler for PGMPAGE.
2543 * @copydoc FNRTSTRFORMATTYPE */
2544static DECLCALLBACK(size_t) pgmFormatTypeHandlerPage(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
2545 const char *pszType, void const *pvValue,
2546 int cchWidth, int cchPrecision, unsigned fFlags,
2547 void *pvUser)
2548{
2549 size_t cch;
2550 PCPGMPAGE pPage = (PCPGMPAGE)pvValue;
2551 if (RT_VALID_PTR(pPage))
2552 {
2553 char szTmp[64+80];
2554
2555 cch = 0;
2556
2557 /* The single char state stuff. */
2558 static const char s_achPageStates[4] = { 'Z', 'A', 'W', 'S' };
2559 szTmp[cch++] = s_achPageStates[PGM_PAGE_GET_STATE_NA(pPage)];
2560
2561#define IS_PART_INCLUDED(lvl) ( !(fFlags & RTSTR_F_PRECISION) || cchPrecision == (lvl) || cchPrecision >= (lvl)+10 )
2562 if (IS_PART_INCLUDED(5))
2563 {
2564 static const char s_achHandlerStates[4] = { '-', 't', 'w', 'a' };
2565 szTmp[cch++] = s_achHandlerStates[PGM_PAGE_GET_HNDL_PHYS_STATE(pPage)];
2566 szTmp[cch++] = s_achHandlerStates[PGM_PAGE_GET_HNDL_VIRT_STATE(pPage)];
2567 }
2568
2569 /* The type. */
2570 if (IS_PART_INCLUDED(4))
2571 {
2572 szTmp[cch++] = ':';
2573 static const char s_achPageTypes[8][4] = { "INV", "RAM", "MI2", "M2A", "SHA", "ROM", "MIO", "BAD" };
2574 szTmp[cch++] = s_achPageTypes[PGM_PAGE_GET_TYPE_NA(pPage)][0];
2575 szTmp[cch++] = s_achPageTypes[PGM_PAGE_GET_TYPE_NA(pPage)][1];
2576 szTmp[cch++] = s_achPageTypes[PGM_PAGE_GET_TYPE_NA(pPage)][2];
2577 }
2578
2579 /* The numbers. */
2580 if (IS_PART_INCLUDED(3))
2581 {
2582 szTmp[cch++] = ':';
2583 cch += RTStrFormatNumber(&szTmp[cch], PGM_PAGE_GET_HCPHYS_NA(pPage), 16, 12, 0, RTSTR_F_ZEROPAD | RTSTR_F_64BIT);
2584 }
2585
2586 if (IS_PART_INCLUDED(2))
2587 {
2588 szTmp[cch++] = ':';
2589 cch += RTStrFormatNumber(&szTmp[cch], PGM_PAGE_GET_PAGEID(pPage), 16, 7, 0, RTSTR_F_ZEROPAD | RTSTR_F_32BIT);
2590 }
2591
2592 if (IS_PART_INCLUDED(6))
2593 {
2594 szTmp[cch++] = ':';
2595 static const char s_achRefs[4] = { '-', 'U', '!', 'L' };
2596 szTmp[cch++] = s_achRefs[PGM_PAGE_GET_TD_CREFS_NA(pPage)];
2597 cch += RTStrFormatNumber(&szTmp[cch], PGM_PAGE_GET_TD_IDX_NA(pPage), 16, 4, 0, RTSTR_F_ZEROPAD | RTSTR_F_16BIT);
2598 }
2599#undef IS_PART_INCLUDED
2600
2601 cch = pfnOutput(pvArgOutput, szTmp, cch);
2602 }
2603 else
2604 cch = pfnOutput(pvArgOutput, "<bad-pgmpage-ptr>", sizeof("<bad-pgmpage-ptr>") - 1);
2605 NOREF(pszType); NOREF(cchWidth); NOREF(pvUser);
2606 return cch;
2607}
2608
2609
2610/** Format handler for PGMRAMRANGE.
2611 * @copydoc FNRTSTRFORMATTYPE */
2612static DECLCALLBACK(size_t) pgmFormatTypeHandlerRamRange(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
2613 const char *pszType, void const *pvValue,
2614 int cchWidth, int cchPrecision, unsigned fFlags,
2615 void *pvUser)
2616{
2617 size_t cch;
2618 PGMRAMRANGE const *pRam = (PGMRAMRANGE const *)pvValue;
2619 if (VALID_PTR(pRam))
2620 {
2621 char szTmp[80];
2622 cch = RTStrPrintf(szTmp, sizeof(szTmp), "%RGp-%RGp", pRam->GCPhys, pRam->GCPhysLast);
2623 cch = pfnOutput(pvArgOutput, szTmp, cch);
2624 }
2625 else
2626 cch = pfnOutput(pvArgOutput, "<bad-pgmramrange-ptr>", sizeof("<bad-pgmramrange-ptr>") - 1);
2627 NOREF(pszType); NOREF(cchWidth); NOREF(cchPrecision); NOREF(pvUser); NOREF(fFlags);
2628 return cch;
2629}
2630
2631/** Format type andlers to be registered/deregistered. */
2632static const struct
2633{
2634 char szType[24];
2635 PFNRTSTRFORMATTYPE pfnHandler;
2636} g_aPgmFormatTypes[] =
2637{
2638 { "pgmpage", pgmFormatTypeHandlerPage },
2639 { "pgmramrange", pgmFormatTypeHandlerRamRange }
2640};
2641
2642#endif /* !IN_R0 || LOG_ENABLED */
2643
2644/**
2645 * Registers the global string format types.
2646 *
2647 * This should be called at module load time or in some other manner that ensure
2648 * that it's called exactly one time.
2649 *
2650 * @returns IPRT status code on RTStrFormatTypeRegister failure.
2651 */
2652VMMDECL(int) PGMRegisterStringFormatTypes(void)
2653{
2654#if !defined(IN_R0) || defined(LOG_ENABLED)
2655 int rc = VINF_SUCCESS;
2656 unsigned i;
2657 for (i = 0; RT_SUCCESS(rc) && i < RT_ELEMENTS(g_aPgmFormatTypes); i++)
2658 {
2659 rc = RTStrFormatTypeRegister(g_aPgmFormatTypes[i].szType, g_aPgmFormatTypes[i].pfnHandler, NULL);
2660# ifdef IN_RING0
2661 if (rc == VERR_ALREADY_EXISTS)
2662 {
2663 /* in case of cleanup failure in ring-0 */
2664 RTStrFormatTypeDeregister(g_aPgmFormatTypes[i].szType);
2665 rc = RTStrFormatTypeRegister(g_aPgmFormatTypes[i].szType, g_aPgmFormatTypes[i].pfnHandler, NULL);
2666 }
2667# endif
2668 }
2669 if (RT_FAILURE(rc))
2670 while (i-- > 0)
2671 RTStrFormatTypeDeregister(g_aPgmFormatTypes[i].szType);
2672
2673 return rc;
2674#else
2675 return VINF_SUCCESS;
2676#endif
2677}
2678
2679
2680/**
2681 * Deregisters the global string format types.
2682 *
2683 * This should be called at module unload time or in some other manner that
2684 * ensure that it's called exactly one time.
2685 */
2686VMMDECL(void) PGMDeregisterStringFormatTypes(void)
2687{
2688#if !defined(IN_R0) || defined(LOG_ENABLED)
2689 for (unsigned i = 0; i < RT_ELEMENTS(g_aPgmFormatTypes); i++)
2690 RTStrFormatTypeDeregister(g_aPgmFormatTypes[i].szType);
2691#endif
2692}
2693
2694#ifdef VBOX_STRICT
2695
2696/**
2697 * Asserts that there are no mapping conflicts.
2698 *
2699 * @returns Number of conflicts.
2700 * @param pVM Pointer to the VM.
2701 */
2702VMMDECL(unsigned) PGMAssertNoMappingConflicts(PVM pVM)
2703{
2704 unsigned cErrors = 0;
2705
2706 /* Only applies to raw mode -> 1 VPCU */
2707 Assert(pVM->cCpus == 1);
2708 PVMCPU pVCpu = &pVM->aCpus[0];
2709
2710 /*
2711 * Check for mapping conflicts.
2712 */
2713 for (PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
2714 pMapping;
2715 pMapping = pMapping->CTX_SUFF(pNext))
2716 {
2717 /** @todo This is slow and should be optimized, but since it's just assertions I don't care now. */
2718 for (RTGCPTR GCPtr = pMapping->GCPtr;
2719 GCPtr <= pMapping->GCPtrLast;
2720 GCPtr += PAGE_SIZE)
2721 {
2722 int rc = PGMGstGetPage(pVCpu, (RTGCPTR)GCPtr, NULL, NULL);
2723 if (rc != VERR_PAGE_TABLE_NOT_PRESENT)
2724 {
2725 AssertMsgFailed(("Conflict at %RGv with %s\n", GCPtr, R3STRING(pMapping->pszDesc)));
2726 cErrors++;
2727 break;
2728 }
2729 }
2730 }
2731
2732 return cErrors;
2733}
2734
2735
2736/**
2737 * Asserts that everything related to the guest CR3 is correctly shadowed.
2738 *
2739 * This will call PGMAssertNoMappingConflicts() and PGMAssertHandlerAndFlagsInSync(),
2740 * and assert the correctness of the guest CR3 mapping before asserting that the
2741 * shadow page tables is in sync with the guest page tables.
2742 *
2743 * @returns Number of conflicts.
2744 * @param pVM Pointer to the VM.
2745 * @param pVCpu Pointer to the VMCPU.
2746 * @param cr3 The current guest CR3 register value.
2747 * @param cr4 The current guest CR4 register value.
2748 */
2749VMMDECL(unsigned) PGMAssertCR3(PVM pVM, PVMCPU pVCpu, uint64_t cr3, uint64_t cr4)
2750{
2751 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3), a);
2752 pgmLock(pVM);
2753 unsigned cErrors = PGM_BTH_PFN(AssertCR3, pVCpu)(pVCpu, cr3, cr4, 0, ~(RTGCPTR)0);
2754 pgmUnlock(pVM);
2755 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3), a);
2756 return cErrors;
2757}
2758
2759#endif /* VBOX_STRICT */
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