VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAll.cpp@ 10700

Last change on this file since 10700 was 10340, checked in by vboxsync, 16 years ago

Pool flush handling updates
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File size: 51.8 KB
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1/* $Id: PGMAll.cpp 10340 2008-07-07 16:58:59Z vboxsync $ */
2/** @file
3 * PGM - Page Manager and Monitor - All context code.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22/*******************************************************************************
23* Header Files *
24*******************************************************************************/
25#define LOG_GROUP LOG_GROUP_PGM
26#include <VBox/pgm.h>
27#include <VBox/cpum.h>
28#include <VBox/selm.h>
29#include <VBox/iom.h>
30#include <VBox/sup.h>
31#include <VBox/mm.h>
32#include <VBox/stam.h>
33#include <VBox/csam.h>
34#include <VBox/patm.h>
35#include <VBox/trpm.h>
36#include <VBox/rem.h>
37#include <VBox/em.h>
38#include <VBox/hwaccm.h>
39#include "PGMInternal.h"
40#include <VBox/vm.h>
41#include <iprt/assert.h>
42#include <iprt/asm.h>
43#include <iprt/string.h>
44#include <VBox/log.h>
45#include <VBox/param.h>
46#include <VBox/err.h>
47
48
49/*******************************************************************************
50* Structures and Typedefs *
51*******************************************************************************/
52/**
53 * Stated structure for PGM_GST_NAME(HandlerVirtualUpdate) that's
54 * passed to PGM_GST_NAME(VirtHandlerUpdateOne) during enumeration.
55 */
56typedef struct PGMHVUSTATE
57{
58 /** The VM handle. */
59 PVM pVM;
60 /** The todo flags. */
61 RTUINT fTodo;
62 /** The CR4 register value. */
63 uint32_t cr4;
64} PGMHVUSTATE, *PPGMHVUSTATE;
65
66
67/*******************************************************************************
68* Internal Functions *
69*******************************************************************************/
70
71/*
72 * Shadow - 32-bit mode
73 */
74#define PGM_SHW_TYPE PGM_TYPE_32BIT
75#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
76#include "PGMAllShw.h"
77
78/* Guest - real mode */
79#define PGM_GST_TYPE PGM_TYPE_REAL
80#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
81#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
82#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
83#include "PGMAllGst.h"
84#include "PGMAllBth.h"
85#undef BTH_PGMPOOLKIND_PT_FOR_PT
86#undef PGM_BTH_NAME
87#undef PGM_GST_TYPE
88#undef PGM_GST_NAME
89
90/* Guest - protected mode */
91#define PGM_GST_TYPE PGM_TYPE_PROT
92#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
93#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
94#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
95#include "PGMAllGst.h"
96#include "PGMAllBth.h"
97#undef BTH_PGMPOOLKIND_PT_FOR_PT
98#undef PGM_BTH_NAME
99#undef PGM_GST_TYPE
100#undef PGM_GST_NAME
101
102/* Guest - 32-bit mode */
103#define PGM_GST_TYPE PGM_TYPE_32BIT
104#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
105#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
106#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
107#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
108#include "PGMAllGst.h"
109#include "PGMAllBth.h"
110#undef BTH_PGMPOOLKIND_PT_FOR_BIG
111#undef BTH_PGMPOOLKIND_PT_FOR_PT
112#undef PGM_BTH_NAME
113#undef PGM_GST_TYPE
114#undef PGM_GST_NAME
115
116#undef PGM_SHW_TYPE
117#undef PGM_SHW_NAME
118
119
120/*
121 * Shadow - PAE mode
122 */
123#define PGM_SHW_TYPE PGM_TYPE_PAE
124#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
125#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
126#include "PGMAllShw.h"
127
128/* Guest - real mode */
129#define PGM_GST_TYPE PGM_TYPE_REAL
130#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
131#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
132#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
133#include "PGMAllBth.h"
134#undef BTH_PGMPOOLKIND_PT_FOR_PT
135#undef PGM_BTH_NAME
136#undef PGM_GST_TYPE
137#undef PGM_GST_NAME
138
139/* Guest - protected mode */
140#define PGM_GST_TYPE PGM_TYPE_PROT
141#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
142#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
143#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
144#include "PGMAllBth.h"
145#undef BTH_PGMPOOLKIND_PT_FOR_PT
146#undef PGM_BTH_NAME
147#undef PGM_GST_TYPE
148#undef PGM_GST_NAME
149
150/* Guest - 32-bit mode */
151#define PGM_GST_TYPE PGM_TYPE_32BIT
152#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
153#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
154#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
155#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
156#include "PGMAllBth.h"
157#undef BTH_PGMPOOLKIND_PT_FOR_BIG
158#undef BTH_PGMPOOLKIND_PT_FOR_PT
159#undef PGM_BTH_NAME
160#undef PGM_GST_TYPE
161#undef PGM_GST_NAME
162
163
164/* Guest - PAE mode */
165#define PGM_GST_TYPE PGM_TYPE_PAE
166#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
167#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
168#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
169#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
170#include "PGMAllGst.h"
171#include "PGMAllBth.h"
172#undef BTH_PGMPOOLKIND_PT_FOR_BIG
173#undef BTH_PGMPOOLKIND_PT_FOR_PT
174#undef PGM_BTH_NAME
175#undef PGM_GST_TYPE
176#undef PGM_GST_NAME
177
178#undef PGM_SHW_TYPE
179#undef PGM_SHW_NAME
180
181
182#ifndef IN_GC /* AMD64 implies VT-x/AMD-V */
183/*
184 * Shadow - AMD64 mode
185 */
186#define PGM_SHW_TYPE PGM_TYPE_AMD64
187#define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
188#include "PGMAllShw.h"
189
190/* Guest - protected mode */
191#define PGM_GST_TYPE PGM_TYPE_PROT
192#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
193#define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_PROT(name)
194#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
195#include "PGMAllBth.h"
196#undef BTH_PGMPOOLKIND_PT_FOR_PT
197#undef PGM_BTH_NAME
198#undef PGM_GST_TYPE
199#undef PGM_GST_NAME
200
201/* Guest - AMD64 mode */
202#define PGM_GST_TYPE PGM_TYPE_AMD64
203#define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
204#define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
205#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
206#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
207#include "PGMAllGst.h"
208#include "PGMAllBth.h"
209#undef BTH_PGMPOOLKIND_PT_FOR_BIG
210#undef BTH_PGMPOOLKIND_PT_FOR_PT
211#undef PGM_BTH_NAME
212#undef PGM_GST_TYPE
213#undef PGM_GST_NAME
214
215#undef PGM_SHW_TYPE
216#undef PGM_SHW_NAME
217
218/*
219 * Shadow - Nested paging mode
220 */
221#define PGM_SHW_TYPE PGM_TYPE_NESTED
222#define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED(name)
223#include "PGMAllShw.h"
224
225/* Guest - real mode */
226#define PGM_GST_TYPE PGM_TYPE_REAL
227#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
228#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_REAL(name)
229#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
230#include "PGMAllBth.h"
231#undef BTH_PGMPOOLKIND_PT_FOR_PT
232#undef PGM_BTH_NAME
233#undef PGM_GST_TYPE
234#undef PGM_GST_NAME
235
236/* Guest - protected mode */
237#define PGM_GST_TYPE PGM_TYPE_PROT
238#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
239#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PROT(name)
240#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
241#include "PGMAllBth.h"
242#undef BTH_PGMPOOLKIND_PT_FOR_PT
243#undef PGM_BTH_NAME
244#undef PGM_GST_TYPE
245#undef PGM_GST_NAME
246
247/* Guest - 32-bit mode */
248#define PGM_GST_TYPE PGM_TYPE_32BIT
249#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
250#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT(name)
251#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
252#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
253#include "PGMAllBth.h"
254#undef BTH_PGMPOOLKIND_PT_FOR_BIG
255#undef BTH_PGMPOOLKIND_PT_FOR_PT
256#undef PGM_BTH_NAME
257#undef PGM_GST_TYPE
258#undef PGM_GST_NAME
259
260/* Guest - PAE mode */
261#define PGM_GST_TYPE PGM_TYPE_PAE
262#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
263#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE(name)
264#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
265#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
266#include "PGMAllBth.h"
267#undef BTH_PGMPOOLKIND_PT_FOR_BIG
268#undef BTH_PGMPOOLKIND_PT_FOR_PT
269#undef PGM_BTH_NAME
270#undef PGM_GST_TYPE
271#undef PGM_GST_NAME
272
273/* Guest - AMD64 mode */
274#define PGM_GST_TYPE PGM_TYPE_AMD64
275#define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
276#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64(name)
277#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
278#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
279#include "PGMAllBth.h"
280#undef BTH_PGMPOOLKIND_PT_FOR_BIG
281#undef BTH_PGMPOOLKIND_PT_FOR_PT
282#undef PGM_BTH_NAME
283#undef PGM_GST_TYPE
284#undef PGM_GST_NAME
285
286#undef PGM_SHW_TYPE
287#undef PGM_SHW_NAME
288#endif
289
290/**
291 * #PF Handler.
292 *
293 * @returns VBox status code (appropriate for trap handling and GC return).
294 * @param pVM VM Handle.
295 * @param uErr The trap error code.
296 * @param pRegFrame Trap register frame.
297 * @param pvFault The fault address.
298 */
299PGMDECL(int) PGMTrap0eHandler(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
300{
301 LogFlow(("PGMTrap0eHandler: uErr=%#x pvFault=%VGv eip=%VGv\n", (uint32_t)uErr, pvFault, pRegFrame->rip));
302 STAM_PROFILE_START(&pVM->pgm.s.StatGCTrap0e, a);
303 STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = NULL; } );
304
305
306#ifdef VBOX_WITH_STATISTICS
307 /*
308 * Error code stats.
309 */
310 if (uErr & X86_TRAP_PF_US)
311 {
312 if (!(uErr & X86_TRAP_PF_P))
313 {
314 if (uErr & X86_TRAP_PF_RW)
315 STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eUSNotPresentWrite);
316 else
317 STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eUSNotPresentRead);
318 }
319 else if (uErr & X86_TRAP_PF_RW)
320 STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eUSWrite);
321 else if (uErr & X86_TRAP_PF_RSVD)
322 STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eUSReserved);
323 else if (uErr & X86_TRAP_PF_ID)
324 STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eUSNXE);
325 else
326 STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eUSRead);
327 }
328 else
329 { /* Supervisor */
330 if (!(uErr & X86_TRAP_PF_P))
331 {
332 if (uErr & X86_TRAP_PF_RW)
333 STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eSVNotPresentWrite);
334 else
335 STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eSVNotPresentRead);
336 }
337 else if (uErr & X86_TRAP_PF_RW)
338 STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eSVWrite);
339 else if (uErr & X86_TRAP_PF_ID)
340 STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eSNXE);
341 else if (uErr & X86_TRAP_PF_RSVD)
342 STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eSVReserved);
343 }
344#endif
345
346 /*
347 * Call the worker.
348 */
349 int rc = PGM_BTH_PFN(Trap0eHandler, pVM)(pVM, uErr, pRegFrame, pvFault);
350 if (rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
351 rc = VINF_SUCCESS;
352 STAM_STATS({ if (!pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution))
353 pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eMisc; });
354 STAM_PROFILE_STOP_EX(&pVM->pgm.s.StatGCTrap0e, pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution), a);
355 return rc;
356}
357
358/**
359 * Prefetch a page
360 *
361 * Typically used to sync commonly used pages before entering raw mode
362 * after a CR3 reload.
363 *
364 * @returns VBox status code suitable for scheduling.
365 * @retval VINF_SUCCESS on success.
366 * @retval VINF_PGM_SYNC_CR3 if we're out of shadow pages or something like that.
367 * @param pVM VM handle.
368 * @param GCPtrPage Page to invalidate.
369 */
370PGMDECL(int) PGMPrefetchPage(PVM pVM, RTGCPTR GCPtrPage)
371{
372 STAM_PROFILE_START(&pVM->pgm.s.StatHCPrefetch, a);
373 int rc = PGM_BTH_PFN(PrefetchPage, pVM)(pVM, (RTGCUINTPTR)GCPtrPage);
374 STAM_PROFILE_STOP(&pVM->pgm.s.StatHCPrefetch, a);
375 AssertMsg(rc == VINF_SUCCESS || rc == VINF_PGM_SYNC_CR3 || VBOX_FAILURE(rc), ("rc=%Vrc\n", rc));
376 return rc;
377}
378
379
380/**
381 * Gets the mapping corresponding to the specified address (if any).
382 *
383 * @returns Pointer to the mapping.
384 * @returns NULL if not
385 *
386 * @param pVM The virtual machine.
387 * @param GCPtr The guest context pointer.
388 */
389PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr)
390{
391 PPGMMAPPING pMapping = CTXALLSUFF(pVM->pgm.s.pMappings);
392 while (pMapping)
393 {
394 if ((uintptr_t)GCPtr < (uintptr_t)pMapping->GCPtr)
395 break;
396 if ((uintptr_t)GCPtr - (uintptr_t)pMapping->GCPtr < pMapping->cb)
397 {
398 STAM_COUNTER_INC(&pVM->pgm.s.StatGCSyncPTConflict);
399 return pMapping;
400 }
401 pMapping = CTXALLSUFF(pMapping->pNext);
402 }
403 return NULL;
404}
405
406
407/**
408 * Verifies a range of pages for read or write access
409 *
410 * Only checks the guest's page tables
411 *
412 * @returns VBox status code.
413 * @param pVM VM handle.
414 * @param Addr Guest virtual address to check
415 * @param cbSize Access size
416 * @param fAccess Access type (r/w, user/supervisor (X86_PTE_*))
417 */
418PGMDECL(int) PGMIsValidAccess(PVM pVM, RTGCUINTPTR Addr, uint32_t cbSize, uint32_t fAccess)
419{
420 /*
421 * Validate input.
422 */
423 if (fAccess & ~(X86_PTE_US | X86_PTE_RW))
424 {
425 AssertMsgFailed(("PGMIsValidAccess: invalid access type %08x\n", fAccess));
426 return VERR_INVALID_PARAMETER;
427 }
428
429 uint64_t fPage;
430 int rc = PGMGstGetPage(pVM, (RTGCPTR)Addr, &fPage, NULL);
431 if (VBOX_FAILURE(rc))
432 {
433 Log(("PGMIsValidAccess: access violation for %VGv rc=%d\n", Addr, rc));
434 return VINF_EM_RAW_GUEST_TRAP;
435 }
436
437 /*
438 * Check if the access would cause a page fault
439 *
440 * Note that hypervisor page directories are not present in the guest's tables, so this check
441 * is sufficient.
442 */
443 bool fWrite = !!(fAccess & X86_PTE_RW);
444 bool fUser = !!(fAccess & X86_PTE_US);
445 if ( !(fPage & X86_PTE_P)
446 || (fWrite && !(fPage & X86_PTE_RW))
447 || (fUser && !(fPage & X86_PTE_US)) )
448 {
449 Log(("PGMIsValidAccess: access violation for %VGv attr %#llx vs %d:%d\n", Addr, fPage, fWrite, fUser));
450 return VINF_EM_RAW_GUEST_TRAP;
451 }
452 if ( VBOX_SUCCESS(rc)
453 && PAGE_ADDRESS(Addr) != PAGE_ADDRESS(Addr + cbSize))
454 return PGMIsValidAccess(pVM, Addr + PAGE_SIZE, (cbSize > PAGE_SIZE) ? cbSize - PAGE_SIZE : 1, fAccess);
455 return rc;
456}
457
458
459/**
460 * Verifies a range of pages for read or write access
461 *
462 * Supports handling of pages marked for dirty bit tracking and CSAM
463 *
464 * @returns VBox status code.
465 * @param pVM VM handle.
466 * @param Addr Guest virtual address to check
467 * @param cbSize Access size
468 * @param fAccess Access type (r/w, user/supervisor (X86_PTE_*))
469 */
470PGMDECL(int) PGMVerifyAccess(PVM pVM, RTGCUINTPTR Addr, uint32_t cbSize, uint32_t fAccess)
471{
472 /*
473 * Validate input.
474 */
475 if (fAccess & ~(X86_PTE_US | X86_PTE_RW))
476 {
477 AssertMsgFailed(("PGMVerifyAccess: invalid access type %08x\n", fAccess));
478 return VERR_INVALID_PARAMETER;
479 }
480
481 uint64_t fPageGst;
482 int rc = PGMGstGetPage(pVM, (RTGCPTR)Addr, &fPageGst, NULL);
483 if (VBOX_FAILURE(rc))
484 {
485 Log(("PGMVerifyAccess: access violation for %VGv rc=%d\n", Addr, rc));
486 return VINF_EM_RAW_GUEST_TRAP;
487 }
488
489 /*
490 * Check if the access would cause a page fault
491 *
492 * Note that hypervisor page directories are not present in the guest's tables, so this check
493 * is sufficient.
494 */
495 const bool fWrite = !!(fAccess & X86_PTE_RW);
496 const bool fUser = !!(fAccess & X86_PTE_US);
497 if ( !(fPageGst & X86_PTE_P)
498 || (fWrite && !(fPageGst & X86_PTE_RW))
499 || (fUser && !(fPageGst & X86_PTE_US)) )
500 {
501 Log(("PGMVerifyAccess: access violation for %VGv attr %#llx vs %d:%d\n", Addr, fPageGst, fWrite, fUser));
502 return VINF_EM_RAW_GUEST_TRAP;
503 }
504
505 if (!HWACCMIsNestedPagingActive(pVM))
506 {
507 /*
508 * Next step is to verify if we protected this page for dirty bit tracking or for CSAM scanning
509 */
510 rc = PGMShwGetPage(pVM, (RTGCPTR)Addr, NULL, NULL);
511 if ( rc == VERR_PAGE_NOT_PRESENT
512 || rc == VERR_PAGE_TABLE_NOT_PRESENT)
513 {
514 /*
515 * Page is not present in our page tables.
516 * Try to sync it!
517 */
518 Assert(X86_TRAP_PF_RW == X86_PTE_RW && X86_TRAP_PF_US == X86_PTE_US);
519 uint32_t uErr = fAccess & (X86_TRAP_PF_RW | X86_TRAP_PF_US);
520 rc = PGM_BTH_PFN(VerifyAccessSyncPage, pVM)(pVM, Addr, fPageGst, uErr);
521 if (rc != VINF_SUCCESS)
522 return rc;
523 }
524 else
525 AssertMsg(rc == VINF_SUCCESS, ("PGMShwGetPage %VGv failed with %Vrc\n", Addr, rc));
526 }
527
528#if 0 /* def VBOX_STRICT; triggers too often now */
529 /*
530 * This check is a bit paranoid, but useful.
531 */
532 /** @note this will assert when writing to monitored pages (a bit annoying actually) */
533 uint64_t fPageShw;
534 rc = PGMShwGetPage(pVM, (RTGCPTR)Addr, &fPageShw, NULL);
535 if ( (rc == VERR_PAGE_NOT_PRESENT || VBOX_FAILURE(rc))
536 || (fWrite && !(fPageShw & X86_PTE_RW))
537 || (fUser && !(fPageShw & X86_PTE_US)) )
538 {
539 AssertMsgFailed(("Unexpected access violation for %VGv! rc=%Vrc write=%d user=%d\n",
540 Addr, rc, fWrite && !(fPageShw & X86_PTE_RW), fUser && !(fPageShw & X86_PTE_US)));
541 return VINF_EM_RAW_GUEST_TRAP;
542 }
543#endif
544
545 if ( VBOX_SUCCESS(rc)
546 && ( PAGE_ADDRESS(Addr) != PAGE_ADDRESS(Addr + cbSize - 1)
547 || Addr + cbSize < Addr))
548 {
549 /* Don't recursively call PGMVerifyAccess as we might run out of stack. */
550 for (;;)
551 {
552 Addr += PAGE_SIZE;
553 if (cbSize > PAGE_SIZE)
554 cbSize -= PAGE_SIZE;
555 else
556 cbSize = 1;
557 rc = PGMVerifyAccess(pVM, Addr, 1, fAccess);
558 if (rc != VINF_SUCCESS)
559 break;
560 if (PAGE_ADDRESS(Addr) == PAGE_ADDRESS(Addr + cbSize - 1))
561 break;
562 }
563 }
564 return rc;
565}
566
567
568#ifndef IN_GC
569/**
570 * Emulation of the invlpg instruction (HC only actually).
571 *
572 * @returns VBox status code.
573 * @param pVM VM handle.
574 * @param GCPtrPage Page to invalidate.
575 * @remark ASSUMES the page table entry or page directory is
576 * valid. Fairly safe, but there could be edge cases!
577 * @todo Flush page or page directory only if necessary!
578 */
579PGMDECL(int) PGMInvalidatePage(PVM pVM, RTGCPTR GCPtrPage)
580{
581 int rc;
582
583 Log3(("PGMInvalidatePage: GCPtrPage=%VGv\n", GCPtrPage));
584
585 /** @todo merge PGMGCInvalidatePage with this one */
586
587#ifndef IN_RING3
588 /*
589 * Notify the recompiler so it can record this instruction.
590 * Failure happens when it's out of space. We'll return to HC in that case.
591 */
592 rc = REMNotifyInvalidatePage(pVM, GCPtrPage);
593 if (VBOX_FAILURE(rc))
594 return rc;
595#endif
596
597 STAM_PROFILE_START(&CTXMID(pVM->pgm.s.Stat,InvalidatePage), a);
598 rc = PGM_BTH_PFN(InvalidatePage, pVM)(pVM, GCPtrPage);
599 STAM_PROFILE_STOP(&CTXMID(pVM->pgm.s.Stat,InvalidatePage), a);
600
601#ifndef IN_RING0
602 /*
603 * Check if we have a pending update of the CR3 monitoring.
604 */
605 if ( VBOX_SUCCESS(rc)
606 && (pVM->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3))
607 {
608 pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
609 Assert(!pVM->pgm.s.fMappingsFixed);
610 Assert(pVM->pgm.s.GCPhysCR3 == pVM->pgm.s.GCPhysGstCR3Monitored);
611 rc = PGM_GST_PFN(MonitorCR3, pVM)(pVM, pVM->pgm.s.GCPhysCR3);
612 }
613#endif
614
615#ifdef IN_RING3
616 /*
617 * Inform CSAM about the flush
618 */
619 /** @note this is to check if monitored pages have been changed; when we implement callbacks for virtual handlers, this is no longer required. */
620 CSAMR3FlushPage(pVM, GCPtrPage);
621#endif
622 return rc;
623}
624#endif
625
626
627/**
628 * Executes an instruction using the interpreter.
629 *
630 * @returns VBox status code (appropriate for trap handling and GC return).
631 * @param pVM VM handle.
632 * @param pRegFrame Register frame.
633 * @param pvFault Fault address.
634 */
635PGMDECL(int) PGMInterpretInstruction(PVM pVM, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
636{
637 uint32_t cb;
638 int rc = EMInterpretInstruction(pVM, pRegFrame, pvFault, &cb);
639 if (rc == VERR_EM_INTERPRETER)
640 rc = VINF_EM_RAW_EMULATE_INSTR;
641 if (rc != VINF_SUCCESS)
642 Log(("PGMInterpretInstruction: returns %Rrc (pvFault=%VGv)\n", rc, pvFault));
643 return rc;
644}
645
646
647/**
648 * Gets effective page information (from the VMM page directory).
649 *
650 * @returns VBox status.
651 * @param pVM VM Handle.
652 * @param GCPtr Guest Context virtual address of the page.
653 * @param pfFlags Where to store the flags. These are X86_PTE_*.
654 * @param pHCPhys Where to store the HC physical address of the page.
655 * This is page aligned.
656 * @remark You should use PGMMapGetPage() for pages in a mapping.
657 */
658PGMDECL(int) PGMShwGetPage(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys)
659{
660 return PGM_SHW_PFN(GetPage,pVM)(pVM, (RTGCUINTPTR)GCPtr, pfFlags, pHCPhys);
661}
662
663
664/**
665 * Sets (replaces) the page flags for a range of pages in the shadow context.
666 *
667 * @returns VBox status.
668 * @param pVM VM handle.
669 * @param GCPtr The address of the first page.
670 * @param cb The size of the range in bytes.
671 * @param fFlags Page flags X86_PTE_*, excluding the page mask of course.
672 * @remark You must use PGMMapSetPage() for pages in a mapping.
673 */
674PGMDECL(int) PGMShwSetPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags)
675{
676 return PGMShwModifyPage(pVM, GCPtr, cb, fFlags, 0);
677}
678
679
680/**
681 * Modify page flags for a range of pages in the shadow context.
682 *
683 * The existing flags are ANDed with the fMask and ORed with the fFlags.
684 *
685 * @returns VBox status code.
686 * @param pVM VM handle.
687 * @param GCPtr Virtual address of the first page in the range.
688 * @param cb Size (in bytes) of the range to apply the modification to.
689 * @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
690 * @param fMask The AND mask - page flags X86_PTE_*.
691 * Be very CAREFUL when ~'ing constants which could be 32-bit!
692 * @remark You must use PGMMapModifyPage() for pages in a mapping.
693 */
694PGMDECL(int) PGMShwModifyPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
695{
696 /*
697 * Validate input.
698 */
699 if (fFlags & X86_PTE_PAE_PG_MASK)
700 {
701 AssertMsgFailed(("fFlags=%#llx\n", fFlags));
702 return VERR_INVALID_PARAMETER;
703 }
704 if (!cb)
705 {
706 AssertFailed();
707 return VERR_INVALID_PARAMETER;
708 }
709
710 /*
711 * Align the input.
712 */
713 cb += (RTGCUINTPTR)GCPtr & PAGE_OFFSET_MASK;
714 cb = RT_ALIGN_Z(cb, PAGE_SIZE);
715 GCPtr = (RTGCPTR)((RTGCUINTPTR)GCPtr & PAGE_BASE_GC_MASK); /** @todo this ain't necessary, right... */
716
717 /*
718 * Call worker.
719 */
720 return PGM_SHW_PFN(ModifyPage, pVM)(pVM, (RTGCUINTPTR)GCPtr, cb, fFlags, fMask);
721}
722
723/**
724 * Syncs the SHADOW page directory pointer for the specified address. Allocates
725 * backing pages in case the PDPT entry is missing.
726 *
727 * @returns VBox status.
728 * @param pVM VM handle.
729 * @param GCPtr The address.
730 * @param pGstPdpe Guest PDPT entry
731 * @param ppPD Receives address of page directory
732 */
733PGMDECL(int) PGMShwSyncPAEPDPtr(PVM pVM, RTGCUINTPTR GCPtr, PX86PDPE pGstPdpe, PX86PDPAE *ppPD)
734{
735 PPGM pPGM = &pVM->pgm.s;
736 PPGMPOOL pPool = pPGM->CTXSUFF(pPool);
737 PPGMPOOLPAGE pShwPage;
738 int rc;
739
740 Assert(!HWACCMIsNestedPagingActive(pVM));
741
742 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
743 PX86PDPT pPdpt = pVM->pgm.s.CTXMID(p,PaePDPT);
744 PX86PDPE pPdpe = &pPdpt->a[iPdPt];
745
746 /* Allocate page directory if not present. */
747 if ( !pPdpe->n.u1Present
748 && !(pPdpe->u & X86_PDPE_PG_MASK))
749 {
750 PX86PDPE pPdptGst = &CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt];
751
752 Assert(!(pPdpe->u & X86_PDPE_PG_MASK));
753 /* Create a reference back to the PDPT by using the index in its shadow page. */
754 rc = pgmPoolAlloc(pVM, pPdptGst->u & X86_PDPE_PG_MASK, PGMPOOLKIND_PAE_PD_FOR_PAE_PD, PGMPOOL_IDX_PDPT, iPdPt, &pShwPage);
755 if (rc == VERR_PGM_POOL_FLUSHED)
756 {
757 Assert(pVM->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL);
758 VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
759 return VINF_PGM_SYNC_CR3;
760 }
761 AssertRCReturn(rc, rc);
762 }
763 else
764 {
765 pShwPage = pgmPoolGetPage(pPool, pPdpe->u & X86_PDPE_PG_MASK);
766 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
767 }
768 /* The PD was cached or created; hook it up now. */
769 pPdpe->u |= pShwPage->Core.Key
770 | (pGstPdpe->u & ~(X86_PDPE_PG_MASK | X86_PDPE_AVL_MASK | X86_PDPE_PCD | X86_PDPE_PWT));
771
772 *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
773 return VINF_SUCCESS;
774}
775
776/**
777 * Gets the SHADOW page directory pointer for the specified address.
778 *
779 * @returns VBox status.
780 * @param pVM VM handle.
781 * @param GCPtr The address.
782 * @param ppPdpt Receives address of pdpt
783 * @param ppPD Receives address of page directory
784 */
785PGMDECL(int) PGMShwGetPAEPDPtr(PVM pVM, RTGCUINTPTR GCPtr, PX86PDPT *ppPdpt, PX86PDPAE *ppPD)
786{
787 PPGM pPGM = &pVM->pgm.s;
788 PPGMPOOL pPool = pPGM->CTXSUFF(pPool);
789 PPGMPOOLPAGE pShwPage;
790
791 Assert(!HWACCMIsNestedPagingActive(pVM));
792
793 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
794 PX86PDPT pPdpt = pVM->pgm.s.CTXMID(p,PaePDPT);
795 PX86PDPE pPdpe = &pPdpt->a[iPdPt];
796
797 *ppPdpt = pPdpt;
798 if (!pPdpe->n.u1Present)
799 return VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT;
800
801 pShwPage = pgmPoolGetPage(pPool, pPdpe->u & X86_PDPE_PG_MASK);
802 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
803
804 *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
805 return VINF_SUCCESS;
806}
807
808#ifndef IN_GC
809/**
810 * Syncs the SHADOW page directory pointer for the specified address. Allocates
811 * backing pages in case the PDPT or PML4 entry is missing.
812 *
813 * @returns VBox status.
814 * @param pVM VM handle.
815 * @param GCPtr The address.
816 * @param pGstPml4e Guest PML4 entry
817 * @param pGstPdpe Guest PDPT entry
818 * @param ppPD Receives address of page directory
819 */
820PGMDECL(int) PGMShwSyncLongModePDPtr(PVM pVM, RTGCUINTPTR64 GCPtr, PX86PML4E pGstPml4e, PX86PDPE pGstPdpe, PX86PDPAE *ppPD)
821{
822 PPGM pPGM = &pVM->pgm.s;
823 const unsigned iPml4e = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
824 PPGMPOOL pPool = pPGM->CTXSUFF(pPool);
825 PX86PML4E pPml4e;
826 PPGMPOOLPAGE pShwPage;
827 int rc;
828 bool fNestedPaging = HWACCMIsNestedPagingActive(pVM);
829
830 Assert(pVM->pgm.s.pHCPaePML4);
831
832 /* Allocate page directory pointer table if not present. */
833 pPml4e = &pPGM->pHCPaePML4->a[iPml4e];
834 if ( !pPml4e->n.u1Present
835 && !(pPml4e->u & X86_PML4E_PG_MASK))
836 {
837 Assert(!(pPml4e->u & X86_PML4E_PG_MASK));
838
839 if (!fNestedPaging)
840 {
841 Assert(pVM->pgm.s.pHCShwAmd64CR3);
842 Assert(pPGM->pGstPaePML4HC);
843
844 PX86PML4E pPml4eGst = &pPGM->pGstPaePML4HC->a[iPml4e];
845
846 rc = pgmPoolAlloc(pVM, pPml4eGst->u & X86_PML4E_PG_MASK, PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT, pVM->pgm.s.pHCShwAmd64CR3->idx, iPml4e, &pShwPage);
847 }
848 else
849 rc = pgmPoolAlloc(pVM, GCPtr + RT_BIT_64(63) /* hack: make the address unique */, PGMPOOLKIND_64BIT_PDPT_FOR_PHYS, PGMPOOL_IDX_NESTED_ROOT, iPml4e, &pShwPage);
850
851 if (rc == VERR_PGM_POOL_FLUSHED)
852 {
853 Assert(pVM->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL);
854 VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
855 return VINF_PGM_SYNC_CR3;
856 }
857 AssertRCReturn(rc, rc);
858 }
859 else
860 {
861 pShwPage = pgmPoolGetPage(pPool, pPml4e->u & X86_PML4E_PG_MASK);
862 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
863 }
864 /* The PDPT was cached or created; hook it up now. */
865 pPml4e->u |= pShwPage->Core.Key
866 | (pGstPml4e->u & ~(X86_PML4E_PG_MASK | X86_PML4E_AVL_MASK | X86_PML4E_PCD | X86_PML4E_PWT));
867
868 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
869 PX86PDPT pPdpt = (PX86PDPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
870 PX86PDPE pPdpe = &pPdpt->a[iPdPt];
871
872 /* Allocate page directory if not present. */
873 if ( !pPdpe->n.u1Present
874 && !(pPdpe->u & X86_PDPE_PG_MASK))
875 {
876 if (!fNestedPaging)
877 {
878 Assert(pPGM->pGstPaePML4HC);
879
880 PX86PML4E pPml4eGst = &pPGM->pGstPaePML4HC->a[iPml4e];
881 PX86PDPT pPdptGst;
882 rc = PGM_GCPHYS_2_PTR(pVM, pPml4eGst->u & X86_PML4E_PG_MASK, &pPdptGst);
883 AssertRCReturn(rc, rc);
884
885 Assert(!(pPdpe->u & X86_PDPE_PG_MASK));
886 /* Create a reference back to the PDPT by using the index in its shadow page. */
887 rc = pgmPoolAlloc(pVM, pPdptGst->a[iPdPt].u & X86_PDPE_PG_MASK, PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD, pShwPage->idx, iPdPt, &pShwPage);
888 }
889 else
890 rc = pgmPoolAlloc(pVM, GCPtr + RT_BIT_64(62) /* hack: make the address unique */, PGMPOOLKIND_64BIT_PD_FOR_PHYS, pShwPage->idx, iPdPt, &pShwPage);
891
892 if (rc == VERR_PGM_POOL_FLUSHED)
893 {
894 Assert(pVM->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL);
895 VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
896 return VINF_PGM_SYNC_CR3;
897 }
898 AssertRCReturn(rc, rc);
899 }
900 else
901 {
902 pShwPage = pgmPoolGetPage(pPool, pPdpe->u & X86_PDPE_PG_MASK);
903 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
904 }
905 /* The PD was cached or created; hook it up now. */
906 pPdpe->u |= pShwPage->Core.Key
907 | (pGstPdpe->u & ~(X86_PDPE_PG_MASK | X86_PDPE_AVL_MASK | X86_PDPE_PCD | X86_PDPE_PWT));
908
909 *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
910 return VINF_SUCCESS;
911}
912
913/**
914 * Gets the SHADOW page directory pointer for the specified address.
915 *
916 * @returns VBox status.
917 * @param pVM VM handle.
918 * @param GCPtr The address.
919 * @param ppPdpt Receives address of pdpt
920 * @param ppPD Receives address of page directory
921 */
922PGMDECL(int) PGMShwGetLongModePDPtr(PVM pVM, RTGCUINTPTR64 GCPtr, PX86PDPT *ppPdpt, PX86PDPAE *ppPD)
923{
924 PPGM pPGM = &pVM->pgm.s;
925 const unsigned iPml4e = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
926 PPGMPOOL pPool = pPGM->CTXSUFF(pPool);
927 PX86PML4E pPml4e;
928 PPGMPOOLPAGE pShwPage;
929
930 AssertReturn(pVM->pgm.s.pHCPaePML4, VERR_INTERNAL_ERROR);
931
932 pPml4e = &pPGM->pHCPaePML4->a[iPml4e];
933 if (!pPml4e->n.u1Present)
934 return VERR_PAGE_MAP_LEVEL4_NOT_PRESENT;
935
936 pShwPage = pgmPoolGetPage(pPool, pPml4e->u & X86_PML4E_PG_MASK);
937 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
938
939 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
940 PX86PDPT pPdpt = (PX86PDPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
941 PX86PDPE pPdpe = &pPdpt->a[iPdPt];
942
943 *ppPdpt = pPdpt;
944 if (!pPdpe->n.u1Present)
945 return VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT;
946
947 pShwPage = pgmPoolGetPage(pPool, pPdpe->u & X86_PDPE_PG_MASK);
948 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
949
950 *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
951 return VINF_SUCCESS;
952}
953#endif
954
955/**
956 * Gets effective Guest OS page information.
957 *
958 * When GCPtr is in a big page, the function will return as if it was a normal
959 * 4KB page. If the need for distinguishing between big and normal page becomes
960 * necessary at a later point, a PGMGstGetPage() will be created for that
961 * purpose.
962 *
963 * @returns VBox status.
964 * @param pVM VM Handle.
965 * @param GCPtr Guest Context virtual address of the page.
966 * @param pfFlags Where to store the flags. These are X86_PTE_*, even for big pages.
967 * @param pGCPhys Where to store the GC physical address of the page.
968 * This is page aligned. The fact that the
969 */
970PGMDECL(int) PGMGstGetPage(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys)
971{
972 return PGM_GST_PFN(GetPage,pVM)(pVM, (RTGCUINTPTR)GCPtr, pfFlags, pGCPhys);
973}
974
975
976/**
977 * Checks if the page is present.
978 *
979 * @returns true if the page is present.
980 * @returns false if the page is not present.
981 * @param pVM The VM handle.
982 * @param GCPtr Address within the page.
983 */
984PGMDECL(bool) PGMGstIsPagePresent(PVM pVM, RTGCPTR GCPtr)
985{
986 int rc = PGMGstGetPage(pVM, GCPtr, NULL, NULL);
987 return VBOX_SUCCESS(rc);
988}
989
990
991/**
992 * Sets (replaces) the page flags for a range of pages in the guest's tables.
993 *
994 * @returns VBox status.
995 * @param pVM VM handle.
996 * @param GCPtr The address of the first page.
997 * @param cb The size of the range in bytes.
998 * @param fFlags Page flags X86_PTE_*, excluding the page mask of course.
999 */
1000PGMDECL(int) PGMGstSetPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags)
1001{
1002 return PGMGstModifyPage(pVM, GCPtr, cb, fFlags, 0);
1003}
1004
1005
1006/**
1007 * Modify page flags for a range of pages in the guest's tables
1008 *
1009 * The existing flags are ANDed with the fMask and ORed with the fFlags.
1010 *
1011 * @returns VBox status code.
1012 * @param pVM VM handle.
1013 * @param GCPtr Virtual address of the first page in the range.
1014 * @param cb Size (in bytes) of the range to apply the modification to.
1015 * @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
1016 * @param fMask The AND mask - page flags X86_PTE_*, excluding the page mask of course.
1017 * Be very CAREFUL when ~'ing constants which could be 32-bit!
1018 */
1019PGMDECL(int) PGMGstModifyPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
1020{
1021 STAM_PROFILE_START(&CTXMID(pVM->pgm.s.Stat,GstModifyPage), a);
1022
1023 /*
1024 * Validate input.
1025 */
1026 if (fFlags & X86_PTE_PAE_PG_MASK)
1027 {
1028 AssertMsgFailed(("fFlags=%#llx\n", fFlags));
1029 STAM_PROFILE_STOP(&CTXMID(pVM->pgm.s.Stat,GstModifyPage), a);
1030 return VERR_INVALID_PARAMETER;
1031 }
1032
1033 if (!cb)
1034 {
1035 AssertFailed();
1036 STAM_PROFILE_STOP(&CTXMID(pVM->pgm.s.Stat,GstModifyPage), a);
1037 return VERR_INVALID_PARAMETER;
1038 }
1039
1040 LogFlow(("PGMGstModifyPage %VGv %d bytes fFlags=%08llx fMask=%08llx\n", GCPtr, cb, fFlags, fMask));
1041
1042 /*
1043 * Adjust input.
1044 */
1045 cb += (RTGCUINTPTR)GCPtr & PAGE_OFFSET_MASK;
1046 cb = RT_ALIGN_Z(cb, PAGE_SIZE);
1047 GCPtr = (RTGCPTR)((RTGCUINTPTR)GCPtr & PAGE_BASE_GC_MASK);
1048
1049 /*
1050 * Call worker.
1051 */
1052 int rc = PGM_GST_PFN(ModifyPage, pVM)(pVM, (RTGCUINTPTR)GCPtr, cb, fFlags, fMask);
1053
1054 STAM_PROFILE_STOP(&CTXMID(pVM->pgm.s.Stat,GstModifyPage), a);
1055 return rc;
1056}
1057
1058
1059/**
1060 * Gets the current CR3 register value for the shadow memory context.
1061 * @returns CR3 value.
1062 * @param pVM The VM handle.
1063 */
1064PGMDECL(RTHCPHYS) PGMGetHyperCR3(PVM pVM)
1065{
1066 PGMMODE enmShadowMode = pVM->pgm.s.enmShadowMode;
1067 switch (enmShadowMode)
1068 {
1069 case PGMMODE_32_BIT:
1070 return pVM->pgm.s.HCPhys32BitPD;
1071
1072 case PGMMODE_PAE:
1073 case PGMMODE_PAE_NX:
1074 return pVM->pgm.s.HCPhysPaePDPT;
1075
1076 case PGMMODE_AMD64:
1077 case PGMMODE_AMD64_NX:
1078 return pVM->pgm.s.HCPhysPaePML4;
1079
1080 case PGMMODE_NESTED:
1081 return PGMGetNestedCR3(pVM, PGMGetHostMode(pVM));
1082
1083 default:
1084 AssertMsgFailed(("enmShadowMode=%d\n", enmShadowMode));
1085 return ~0;
1086 }
1087}
1088
1089/**
1090 * Gets the current CR3 register value for the nested memory context.
1091 * @returns CR3 value.
1092 * @param pVM The VM handle.
1093 */
1094PGMDECL(RTHCPHYS) PGMGetNestedCR3(PVM pVM, PGMMODE enmShadowMode)
1095{
1096 switch (enmShadowMode)
1097 {
1098 case PGMMODE_32_BIT:
1099 return pVM->pgm.s.HCPhys32BitPD;
1100
1101 case PGMMODE_PAE:
1102 case PGMMODE_PAE_NX:
1103 return pVM->pgm.s.HCPhysPaePDPT;
1104
1105 case PGMMODE_AMD64:
1106 case PGMMODE_AMD64_NX:
1107 return pVM->pgm.s.HCPhysPaePML4;
1108
1109 default:
1110 AssertMsgFailed(("enmShadowMode=%d\n", enmShadowMode));
1111 return ~0;
1112 }
1113}
1114
1115
1116/**
1117 * Gets the CR3 register value for the 32-Bit shadow memory context.
1118 * @returns CR3 value.
1119 * @param pVM The VM handle.
1120 */
1121PGMDECL(RTHCPHYS) PGMGetHyper32BitCR3(PVM pVM)
1122{
1123 return pVM->pgm.s.HCPhys32BitPD;
1124}
1125
1126
1127/**
1128 * Gets the CR3 register value for the PAE shadow memory context.
1129 * @returns CR3 value.
1130 * @param pVM The VM handle.
1131 */
1132PGMDECL(RTHCPHYS) PGMGetHyperPaeCR3(PVM pVM)
1133{
1134 return pVM->pgm.s.HCPhysPaePDPT;
1135}
1136
1137
1138/**
1139 * Gets the CR3 register value for the AMD64 shadow memory context.
1140 * @returns CR3 value.
1141 * @param pVM The VM handle.
1142 */
1143PGMDECL(RTHCPHYS) PGMGetHyperAmd64CR3(PVM pVM)
1144{
1145 return pVM->pgm.s.HCPhysPaePML4;
1146}
1147
1148
1149/**
1150 * Gets the current CR3 register value for the HC intermediate memory context.
1151 * @returns CR3 value.
1152 * @param pVM The VM handle.
1153 */
1154PGMDECL(RTHCPHYS) PGMGetInterHCCR3(PVM pVM)
1155{
1156 switch (pVM->pgm.s.enmHostMode)
1157 {
1158 case SUPPAGINGMODE_32_BIT:
1159 case SUPPAGINGMODE_32_BIT_GLOBAL:
1160 return pVM->pgm.s.HCPhysInterPD;
1161
1162 case SUPPAGINGMODE_PAE:
1163 case SUPPAGINGMODE_PAE_GLOBAL:
1164 case SUPPAGINGMODE_PAE_NX:
1165 case SUPPAGINGMODE_PAE_GLOBAL_NX:
1166 return pVM->pgm.s.HCPhysInterPaePDPT;
1167
1168 case SUPPAGINGMODE_AMD64:
1169 case SUPPAGINGMODE_AMD64_GLOBAL:
1170 case SUPPAGINGMODE_AMD64_NX:
1171 case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1172 return pVM->pgm.s.HCPhysInterPaePDPT;
1173
1174 default:
1175 AssertMsgFailed(("enmHostMode=%d\n", pVM->pgm.s.enmHostMode));
1176 return ~0;
1177 }
1178}
1179
1180
1181/**
1182 * Gets the current CR3 register value for the GC intermediate memory context.
1183 * @returns CR3 value.
1184 * @param pVM The VM handle.
1185 */
1186PGMDECL(RTHCPHYS) PGMGetInterGCCR3(PVM pVM)
1187{
1188 switch (pVM->pgm.s.enmShadowMode)
1189 {
1190 case PGMMODE_32_BIT:
1191 return pVM->pgm.s.HCPhysInterPD;
1192
1193 case PGMMODE_PAE:
1194 case PGMMODE_PAE_NX:
1195 return pVM->pgm.s.HCPhysInterPaePDPT;
1196
1197 case PGMMODE_AMD64:
1198 case PGMMODE_AMD64_NX:
1199 return pVM->pgm.s.HCPhysInterPaePML4;
1200
1201 case PGMMODE_NESTED:
1202 return 0; /* not relevant */
1203
1204 default:
1205 AssertMsgFailed(("enmShadowMode=%d\n", pVM->pgm.s.enmShadowMode));
1206 return ~0;
1207 }
1208}
1209
1210
1211/**
1212 * Gets the CR3 register value for the 32-Bit intermediate memory context.
1213 * @returns CR3 value.
1214 * @param pVM The VM handle.
1215 */
1216PGMDECL(RTHCPHYS) PGMGetInter32BitCR3(PVM pVM)
1217{
1218 return pVM->pgm.s.HCPhysInterPD;
1219}
1220
1221
1222/**
1223 * Gets the CR3 register value for the PAE intermediate memory context.
1224 * @returns CR3 value.
1225 * @param pVM The VM handle.
1226 */
1227PGMDECL(RTHCPHYS) PGMGetInterPaeCR3(PVM pVM)
1228{
1229 return pVM->pgm.s.HCPhysInterPaePDPT;
1230}
1231
1232
1233/**
1234 * Gets the CR3 register value for the AMD64 intermediate memory context.
1235 * @returns CR3 value.
1236 * @param pVM The VM handle.
1237 */
1238PGMDECL(RTHCPHYS) PGMGetInterAmd64CR3(PVM pVM)
1239{
1240 return pVM->pgm.s.HCPhysInterPaePML4;
1241}
1242
1243
1244/**
1245 * Performs and schedules necessary updates following a CR3 load or reload.
1246 *
1247 * This will normally involve mapping the guest PD or nPDPT
1248 *
1249 * @returns VBox status code.
1250 * @retval VINF_PGM_SYNC_CR3 if monitoring requires a CR3 sync. This can
1251 * safely be ignored and overridden since the FF will be set too then.
1252 * @param pVM VM handle.
1253 * @param cr3 The new cr3.
1254 * @param fGlobal Indicates whether this is a global flush or not.
1255 */
1256PGMDECL(int) PGMFlushTLB(PVM pVM, uint64_t cr3, bool fGlobal)
1257{
1258 STAM_PROFILE_START(&pVM->pgm.s.StatFlushTLB, a);
1259
1260 /*
1261 * Always flag the necessary updates; necessary for hardware acceleration
1262 */
1263 VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
1264 if (fGlobal)
1265 VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
1266 LogFlow(("PGMFlushTLB: cr3=%VX64 OldCr3=%VX64 fGlobal=%d\n", cr3, pVM->pgm.s.GCPhysCR3, fGlobal));
1267
1268 /*
1269 * Remap the CR3 content and adjust the monitoring if CR3 was actually changed.
1270 */
1271 int rc = VINF_SUCCESS;
1272 RTGCPHYS GCPhysCR3;
1273 if ( pVM->pgm.s.enmGuestMode == PGMMODE_PAE
1274 || pVM->pgm.s.enmGuestMode == PGMMODE_PAE_NX
1275 || pVM->pgm.s.enmGuestMode == PGMMODE_AMD64
1276 || pVM->pgm.s.enmGuestMode == PGMMODE_AMD64_NX)
1277 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAE_PAGE_MASK);
1278 else
1279 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAGE_MASK);
1280 if (pVM->pgm.s.GCPhysCR3 != GCPhysCR3)
1281 {
1282 pVM->pgm.s.GCPhysCR3 = GCPhysCR3;
1283 rc = PGM_GST_PFN(MapCR3, pVM)(pVM, GCPhysCR3);
1284 if (VBOX_SUCCESS(rc) && !pVM->pgm.s.fMappingsFixed)
1285 {
1286 pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
1287 rc = PGM_GST_PFN(MonitorCR3, pVM)(pVM, GCPhysCR3);
1288 }
1289 if (fGlobal)
1290 STAM_COUNTER_INC(&pVM->pgm.s.StatFlushTLBNewCR3Global);
1291 else
1292 STAM_COUNTER_INC(&pVM->pgm.s.StatFlushTLBNewCR3);
1293 }
1294 else
1295 {
1296 /*
1297 * Check if we have a pending update of the CR3 monitoring.
1298 */
1299 if (pVM->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
1300 {
1301 pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
1302 Assert(!pVM->pgm.s.fMappingsFixed);
1303 rc = PGM_GST_PFN(MonitorCR3, pVM)(pVM, GCPhysCR3);
1304 }
1305 if (fGlobal)
1306 STAM_COUNTER_INC(&pVM->pgm.s.StatFlushTLBSameCR3Global);
1307 else
1308 STAM_COUNTER_INC(&pVM->pgm.s.StatFlushTLBSameCR3);
1309 }
1310
1311 STAM_PROFILE_STOP(&pVM->pgm.s.StatFlushTLB, a);
1312 return rc;
1313}
1314
1315/**
1316 * Performs and schedules necessary updates following a CR3 load or reload,
1317 * without actually flushing the TLB as with PGMFlushTLB.
1318 *
1319 * This will normally involve mapping the guest PD or nPDPT
1320 *
1321 * @returns VBox status code.
1322 * @retval VINF_PGM_SYNC_CR3 if monitoring requires a CR3 sync. This can
1323 * safely be ignored and overridden since the FF will be set too then.
1324 * @param pVM VM handle.
1325 * @param cr3 The new cr3.
1326 */
1327PGMDECL(int) PGMUpdateCR3(PVM pVM, uint64_t cr3)
1328{
1329 LogFlow(("PGMUpdateCR3: cr3=%VX64 OldCr3=%VX64\n", cr3, pVM->pgm.s.GCPhysCR3));
1330
1331 /* We assume we're only called in nested paging mode. */
1332 Assert(pVM->pgm.s.fMappingsFixed);
1333 Assert(!(pVM->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3));
1334 Assert(pVM->pgm.s.enmShadowMode == PGMMODE_NESTED);
1335
1336 /*
1337 * Remap the CR3 content and adjust the monitoring if CR3 was actually changed.
1338 */
1339 int rc = VINF_SUCCESS;
1340 RTGCPHYS GCPhysCR3;
1341 if ( pVM->pgm.s.enmGuestMode == PGMMODE_PAE
1342 || pVM->pgm.s.enmGuestMode == PGMMODE_PAE_NX
1343 || pVM->pgm.s.enmGuestMode == PGMMODE_AMD64
1344 || pVM->pgm.s.enmGuestMode == PGMMODE_AMD64_NX)
1345 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAE_PAGE_MASK);
1346 else
1347 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAGE_MASK);
1348 if (pVM->pgm.s.GCPhysCR3 != GCPhysCR3)
1349 {
1350 pVM->pgm.s.GCPhysCR3 = GCPhysCR3;
1351 rc = PGM_GST_PFN(MapCR3, pVM)(pVM, GCPhysCR3);
1352 }
1353 AssertRC(rc);
1354 return rc;
1355}
1356
1357/**
1358 * Synchronize the paging structures.
1359 *
1360 * This function is called in response to the VM_FF_PGM_SYNC_CR3 and
1361 * VM_FF_PGM_SYNC_CR3_NONGLOBAL. Those two force action flags are set
1362 * in several places, most importantly whenever the CR3 is loaded.
1363 *
1364 * @returns VBox status code.
1365 * @param pVM The virtual machine.
1366 * @param cr0 Guest context CR0 register
1367 * @param cr3 Guest context CR3 register
1368 * @param cr4 Guest context CR4 register
1369 * @param fGlobal Including global page directories or not
1370 */
1371PGMDECL(int) PGMSyncCR3(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
1372{
1373 /*
1374 * We might be called when we shouldn't.
1375 *
1376 * The mode switching will ensure that the PD is resynced
1377 * after every mode switch. So, if we find ourselves here
1378 * when in protected or real mode we can safely disable the
1379 * FF and return immediately.
1380 */
1381 if (pVM->pgm.s.enmGuestMode <= PGMMODE_PROTECTED)
1382 {
1383 Assert((cr0 & (X86_CR0_PG | X86_CR0_PE)) != (X86_CR0_PG | X86_CR0_PE));
1384 VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3);
1385 VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
1386 return VINF_SUCCESS;
1387 }
1388
1389 /* If global pages are not supported, then all flushes are global */
1390 if (!(cr4 & X86_CR4_PGE))
1391 fGlobal = true;
1392 LogFlow(("PGMSyncCR3: cr0=%VX64 cr3=%VX64 cr4=%VX64 fGlobal=%d[%d,%d]\n", cr0, cr3, cr4, fGlobal,
1393 VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3), VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL)));
1394
1395 /*
1396 * Let the 'Bth' function do the work and we'll just keep track of the flags.
1397 */
1398 STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat,SyncCR3), a);
1399 int rc = PGM_BTH_PFN(SyncCR3, pVM)(pVM, cr0, cr3, cr4, fGlobal);
1400 STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncCR3), a);
1401 AssertMsg(rc == VINF_SUCCESS || rc == VINF_PGM_SYNC_CR3 || VBOX_FAILURE(rc), ("rc=%VRc\n", rc));
1402 if (rc == VINF_SUCCESS)
1403 {
1404 if (!(pVM->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS))
1405 {
1406 VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3);
1407 VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
1408 }
1409
1410 /*
1411 * Check if we have a pending update of the CR3 monitoring.
1412 */
1413 if (pVM->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
1414 {
1415 pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
1416 Assert(!pVM->pgm.s.fMappingsFixed);
1417 Assert(pVM->pgm.s.GCPhysCR3 == pVM->pgm.s.GCPhysGstCR3Monitored);
1418 rc = PGM_GST_PFN(MonitorCR3, pVM)(pVM, pVM->pgm.s.GCPhysCR3);
1419 }
1420 }
1421
1422 /*
1423 * Now flush the CR3 (guest context).
1424 */
1425 if (rc == VINF_SUCCESS)
1426 PGM_INVL_GUEST_TLBS();
1427 return rc;
1428}
1429
1430
1431/**
1432 * Called whenever CR0 or CR4 in a way which may change
1433 * the paging mode.
1434 *
1435 * @returns VBox status code fit for scheduling in GC and R0.
1436 * @retval VINF_SUCCESS if the was no change, or it was successfully dealt with.
1437 * @retval VINF_PGM_CHANGE_MODE if we're in GC or R0 and the mode changes.
1438 * @param pVM VM handle.
1439 * @param cr0 The new cr0.
1440 * @param cr4 The new cr4.
1441 * @param efer The new extended feature enable register.
1442 */
1443PGMDECL(int) PGMChangeMode(PVM pVM, uint64_t cr0, uint64_t cr4, uint64_t efer)
1444{
1445 PGMMODE enmGuestMode;
1446
1447 /*
1448 * Calc the new guest mode.
1449 */
1450 if (!(cr0 & X86_CR0_PE))
1451 enmGuestMode = PGMMODE_REAL;
1452 else if (!(cr0 & X86_CR0_PG))
1453 enmGuestMode = PGMMODE_PROTECTED;
1454 else if (!(cr4 & X86_CR4_PAE))
1455 enmGuestMode = PGMMODE_32_BIT;
1456 else if (!(efer & MSR_K6_EFER_LME))
1457 {
1458 if (!(efer & MSR_K6_EFER_NXE))
1459 enmGuestMode = PGMMODE_PAE;
1460 else
1461 enmGuestMode = PGMMODE_PAE_NX;
1462 }
1463 else
1464 {
1465 if (!(efer & MSR_K6_EFER_NXE))
1466 enmGuestMode = PGMMODE_AMD64;
1467 else
1468 enmGuestMode = PGMMODE_AMD64_NX;
1469 }
1470
1471 /*
1472 * Did it change?
1473 */
1474 if (pVM->pgm.s.enmGuestMode == enmGuestMode)
1475 return VINF_SUCCESS;
1476
1477 /* Flush the TLB */
1478 PGM_INVL_GUEST_TLBS();
1479
1480#ifdef IN_RING3
1481 return PGMR3ChangeMode(pVM, enmGuestMode);
1482#else
1483 Log(("PGMChangeMode: returns VINF_PGM_CHANGE_MODE.\n"));
1484 return VINF_PGM_CHANGE_MODE;
1485#endif
1486}
1487
1488
1489/**
1490 * Gets the current guest paging mode.
1491 *
1492 * If you just need the CPU mode (real/protected/long), use CPUMGetGuestMode().
1493 *
1494 * @returns The current paging mode.
1495 * @param pVM The VM handle.
1496 */
1497PGMDECL(PGMMODE) PGMGetGuestMode(PVM pVM)
1498{
1499 return pVM->pgm.s.enmGuestMode;
1500}
1501
1502
1503/**
1504 * Gets the current shadow paging mode.
1505 *
1506 * @returns The current paging mode.
1507 * @param pVM The VM handle.
1508 */
1509PGMDECL(PGMMODE) PGMGetShadowMode(PVM pVM)
1510{
1511 return pVM->pgm.s.enmShadowMode;
1512}
1513
1514/**
1515 * Gets the current host paging mode.
1516 *
1517 * @returns The current paging mode.
1518 * @param pVM The VM handle.
1519 */
1520PGMDECL(PGMMODE) PGMGetHostMode(PVM pVM)
1521{
1522 switch (pVM->pgm.s.enmHostMode)
1523 {
1524 case SUPPAGINGMODE_32_BIT:
1525 case SUPPAGINGMODE_32_BIT_GLOBAL:
1526 return PGMMODE_32_BIT;
1527
1528 case SUPPAGINGMODE_PAE:
1529 case SUPPAGINGMODE_PAE_GLOBAL:
1530 return PGMMODE_PAE;
1531
1532 case SUPPAGINGMODE_PAE_NX:
1533 case SUPPAGINGMODE_PAE_GLOBAL_NX:
1534 return PGMMODE_PAE_NX;
1535
1536 case SUPPAGINGMODE_AMD64:
1537 case SUPPAGINGMODE_AMD64_GLOBAL:
1538 return PGMMODE_AMD64;
1539
1540 case SUPPAGINGMODE_AMD64_NX:
1541 case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1542 return PGMMODE_AMD64_NX;
1543
1544 default: AssertMsgFailed(("enmHostMode=%d\n", pVM->pgm.s.enmHostMode)); break;
1545 }
1546
1547 return PGMMODE_INVALID;
1548}
1549
1550
1551/**
1552 * Get mode name.
1553 *
1554 * @returns read-only name string.
1555 * @param enmMode The mode which name is desired.
1556 */
1557PGMDECL(const char *) PGMGetModeName(PGMMODE enmMode)
1558{
1559 switch (enmMode)
1560 {
1561 case PGMMODE_REAL: return "real";
1562 case PGMMODE_PROTECTED: return "protected";
1563 case PGMMODE_32_BIT: return "32-bit";
1564 case PGMMODE_PAE: return "PAE";
1565 case PGMMODE_PAE_NX: return "PAE+NX";
1566 case PGMMODE_AMD64: return "AMD64";
1567 case PGMMODE_AMD64_NX: return "AMD64+NX";
1568 default: return "unknown mode value";
1569 }
1570}
1571
1572
1573/**
1574 * Acquire the PGM lock.
1575 *
1576 * @returns VBox status code
1577 * @param pVM The VM to operate on.
1578 */
1579int pgmLock(PVM pVM)
1580{
1581 int rc = PDMCritSectEnter(&pVM->pgm.s.CritSect, VERR_SEM_BUSY);
1582#ifdef IN_GC
1583 if (rc == VERR_SEM_BUSY)
1584 rc = VMMGCCallHost(pVM, VMMCALLHOST_PGM_LOCK, 0);
1585#elif defined(IN_RING0)
1586 if (rc == VERR_SEM_BUSY)
1587 rc = VMMR0CallHost(pVM, VMMCALLHOST_PGM_LOCK, 0);
1588#endif
1589 AssertRC(rc);
1590 return rc;
1591}
1592
1593
1594/**
1595 * Release the PGM lock.
1596 *
1597 * @returns VBox status code
1598 * @param pVM The VM to operate on.
1599 */
1600void pgmUnlock(PVM pVM)
1601{
1602 PDMCritSectLeave(&pVM->pgm.s.CritSect);
1603}
1604
1605
1606#ifdef VBOX_STRICT
1607
1608/**
1609 * Asserts that there are no mapping conflicts.
1610 *
1611 * @returns Number of conflicts.
1612 * @param pVM The VM Handle.
1613 */
1614PGMDECL(unsigned) PGMAssertNoMappingConflicts(PVM pVM)
1615{
1616 unsigned cErrors = 0;
1617
1618 /*
1619 * Check for mapping conflicts.
1620 */
1621 for (PPGMMAPPING pMapping = CTXALLSUFF(pVM->pgm.s.pMappings);
1622 pMapping;
1623 pMapping = CTXALLSUFF(pMapping->pNext))
1624 {
1625 /** @todo This is slow and should be optimized, but since it's just assertions I don't care now. */
1626 for (RTGCUINTPTR GCPtr = (RTGCUINTPTR)pMapping->GCPtr;
1627 GCPtr <= (RTGCUINTPTR)pMapping->GCPtrLast;
1628 GCPtr += PAGE_SIZE)
1629 {
1630 int rc = PGMGstGetPage(pVM, (RTGCPTR)GCPtr, NULL, NULL);
1631 if (rc != VERR_PAGE_TABLE_NOT_PRESENT)
1632 {
1633 AssertMsgFailed(("Conflict at %VGv with %s\n", GCPtr, HCSTRING(pMapping->pszDesc)));
1634 cErrors++;
1635 break;
1636 }
1637 }
1638 }
1639
1640 return cErrors;
1641}
1642
1643
1644/**
1645 * Asserts that everything related to the guest CR3 is correctly shadowed.
1646 *
1647 * This will call PGMAssertNoMappingConflicts() and PGMAssertHandlerAndFlagsInSync(),
1648 * and assert the correctness of the guest CR3 mapping before asserting that the
1649 * shadow page tables is in sync with the guest page tables.
1650 *
1651 * @returns Number of conflicts.
1652 * @param pVM The VM Handle.
1653 * @param cr3 The current guest CR3 register value.
1654 * @param cr4 The current guest CR4 register value.
1655 */
1656PGMDECL(unsigned) PGMAssertCR3(PVM pVM, uint64_t cr3, uint64_t cr4)
1657{
1658 STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat,SyncCR3), a);
1659 unsigned cErrors = PGM_BTH_PFN(AssertCR3, pVM)(pVM, cr3, cr4, 0, ~(RTGCUINTPTR)0);
1660 STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncCR3), a);
1661 return cErrors;
1662 return 0;
1663}
1664
1665#endif /* VBOX_STRICT */
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