VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAll.cpp@ 12998

Last change on this file since 12998 was 12998, checked in by vboxsync, 16 years ago

More logging
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id
File size: 56.5 KB
Line 
1/* $Id: PGMAll.cpp 12998 2008-10-06 09:38:43Z vboxsync $ */
2/** @file
3 * PGM - Page Manager and Monitor - All context code.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22/*******************************************************************************
23* Header Files *
24*******************************************************************************/
25#define LOG_GROUP LOG_GROUP_PGM
26#include <VBox/pgm.h>
27#include <VBox/cpum.h>
28#include <VBox/selm.h>
29#include <VBox/iom.h>
30#include <VBox/sup.h>
31#include <VBox/mm.h>
32#include <VBox/stam.h>
33#include <VBox/csam.h>
34#include <VBox/patm.h>
35#include <VBox/trpm.h>
36#include <VBox/rem.h>
37#include <VBox/em.h>
38#include <VBox/hwaccm.h>
39#include <VBox/hwacc_vmx.h>
40#include "PGMInternal.h"
41#include <VBox/vm.h>
42#include <iprt/assert.h>
43#include <iprt/asm.h>
44#include <iprt/string.h>
45#include <VBox/log.h>
46#include <VBox/param.h>
47#include <VBox/err.h>
48
49
50/*******************************************************************************
51* Structures and Typedefs *
52*******************************************************************************/
53/**
54 * Stated structure for PGM_GST_NAME(HandlerVirtualUpdate) that's
55 * passed to PGM_GST_NAME(VirtHandlerUpdateOne) during enumeration.
56 */
57typedef struct PGMHVUSTATE
58{
59 /** The VM handle. */
60 PVM pVM;
61 /** The todo flags. */
62 RTUINT fTodo;
63 /** The CR4 register value. */
64 uint32_t cr4;
65} PGMHVUSTATE, *PPGMHVUSTATE;
66
67
68/*******************************************************************************
69* Internal Functions *
70*******************************************************************************/
71
72/*
73 * Shadow - 32-bit mode
74 */
75#define PGM_SHW_TYPE PGM_TYPE_32BIT
76#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
77#include "PGMAllShw.h"
78
79/* Guest - real mode */
80#define PGM_GST_TYPE PGM_TYPE_REAL
81#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
82#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
83#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
84#include "PGMAllGst.h"
85#include "PGMAllBth.h"
86#undef BTH_PGMPOOLKIND_PT_FOR_PT
87#undef PGM_BTH_NAME
88#undef PGM_GST_TYPE
89#undef PGM_GST_NAME
90
91/* Guest - protected mode */
92#define PGM_GST_TYPE PGM_TYPE_PROT
93#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
94#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
95#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
96#include "PGMAllGst.h"
97#include "PGMAllBth.h"
98#undef BTH_PGMPOOLKIND_PT_FOR_PT
99#undef PGM_BTH_NAME
100#undef PGM_GST_TYPE
101#undef PGM_GST_NAME
102
103/* Guest - 32-bit mode */
104#define PGM_GST_TYPE PGM_TYPE_32BIT
105#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
106#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
107#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
108#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
109#include "PGMAllGst.h"
110#include "PGMAllBth.h"
111#undef BTH_PGMPOOLKIND_PT_FOR_BIG
112#undef BTH_PGMPOOLKIND_PT_FOR_PT
113#undef PGM_BTH_NAME
114#undef PGM_GST_TYPE
115#undef PGM_GST_NAME
116
117#undef PGM_SHW_TYPE
118#undef PGM_SHW_NAME
119
120
121/*
122 * Shadow - PAE mode
123 */
124#define PGM_SHW_TYPE PGM_TYPE_PAE
125#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
126#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
127#include "PGMAllShw.h"
128
129/* Guest - real mode */
130#define PGM_GST_TYPE PGM_TYPE_REAL
131#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
132#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
133#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
134#include "PGMAllBth.h"
135#undef BTH_PGMPOOLKIND_PT_FOR_PT
136#undef PGM_BTH_NAME
137#undef PGM_GST_TYPE
138#undef PGM_GST_NAME
139
140/* Guest - protected mode */
141#define PGM_GST_TYPE PGM_TYPE_PROT
142#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
143#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
144#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
145#include "PGMAllBth.h"
146#undef BTH_PGMPOOLKIND_PT_FOR_PT
147#undef PGM_BTH_NAME
148#undef PGM_GST_TYPE
149#undef PGM_GST_NAME
150
151/* Guest - 32-bit mode */
152#define PGM_GST_TYPE PGM_TYPE_32BIT
153#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
154#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
155#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
156#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
157#include "PGMAllBth.h"
158#undef BTH_PGMPOOLKIND_PT_FOR_BIG
159#undef BTH_PGMPOOLKIND_PT_FOR_PT
160#undef PGM_BTH_NAME
161#undef PGM_GST_TYPE
162#undef PGM_GST_NAME
163
164
165/* Guest - PAE mode */
166#define PGM_GST_TYPE PGM_TYPE_PAE
167#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
168#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
169#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
170#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
171#include "PGMAllGst.h"
172#include "PGMAllBth.h"
173#undef BTH_PGMPOOLKIND_PT_FOR_BIG
174#undef BTH_PGMPOOLKIND_PT_FOR_PT
175#undef PGM_BTH_NAME
176#undef PGM_GST_TYPE
177#undef PGM_GST_NAME
178
179#undef PGM_SHW_TYPE
180#undef PGM_SHW_NAME
181
182
183#ifndef IN_GC /* AMD64 implies VT-x/AMD-V */
184/*
185 * Shadow - AMD64 mode
186 */
187#define PGM_SHW_TYPE PGM_TYPE_AMD64
188#define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
189#include "PGMAllShw.h"
190
191/* Guest - protected mode */
192#define PGM_GST_TYPE PGM_TYPE_PROT
193#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
194#define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_PROT(name)
195#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
196#include "PGMAllBth.h"
197#undef BTH_PGMPOOLKIND_PT_FOR_PT
198#undef PGM_BTH_NAME
199#undef PGM_GST_TYPE
200#undef PGM_GST_NAME
201
202/* Guest - AMD64 mode */
203#define PGM_GST_TYPE PGM_TYPE_AMD64
204#define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
205#define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
206#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
207#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
208#include "PGMAllGst.h"
209#include "PGMAllBth.h"
210#undef BTH_PGMPOOLKIND_PT_FOR_BIG
211#undef BTH_PGMPOOLKIND_PT_FOR_PT
212#undef PGM_BTH_NAME
213#undef PGM_GST_TYPE
214#undef PGM_GST_NAME
215
216#undef PGM_SHW_TYPE
217#undef PGM_SHW_NAME
218
219/*
220 * Shadow - Nested paging mode
221 */
222#define PGM_SHW_TYPE PGM_TYPE_NESTED
223#define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED(name)
224#include "PGMAllShw.h"
225
226/* Guest - real mode */
227#define PGM_GST_TYPE PGM_TYPE_REAL
228#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
229#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_REAL(name)
230#include "PGMAllBth.h"
231#undef PGM_BTH_NAME
232#undef PGM_GST_TYPE
233#undef PGM_GST_NAME
234
235/* Guest - protected mode */
236#define PGM_GST_TYPE PGM_TYPE_PROT
237#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
238#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PROT(name)
239#include "PGMAllBth.h"
240#undef PGM_BTH_NAME
241#undef PGM_GST_TYPE
242#undef PGM_GST_NAME
243
244/* Guest - 32-bit mode */
245#define PGM_GST_TYPE PGM_TYPE_32BIT
246#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
247#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT(name)
248#include "PGMAllBth.h"
249#undef PGM_BTH_NAME
250#undef PGM_GST_TYPE
251#undef PGM_GST_NAME
252
253/* Guest - PAE mode */
254#define PGM_GST_TYPE PGM_TYPE_PAE
255#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
256#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE(name)
257#include "PGMAllBth.h"
258#undef PGM_BTH_NAME
259#undef PGM_GST_TYPE
260#undef PGM_GST_NAME
261
262/* Guest - AMD64 mode */
263#define PGM_GST_TYPE PGM_TYPE_AMD64
264#define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
265#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64(name)
266#include "PGMAllBth.h"
267#undef PGM_BTH_NAME
268#undef PGM_GST_TYPE
269#undef PGM_GST_NAME
270
271#undef PGM_SHW_TYPE
272#undef PGM_SHW_NAME
273
274/*
275 * Shadow - EPT
276 */
277#define PGM_SHW_TYPE PGM_TYPE_EPT
278#define PGM_SHW_NAME(name) PGM_SHW_NAME_EPT(name)
279#include "PGMAllShw.h"
280
281/* Guest - real mode */
282#define PGM_GST_TYPE PGM_TYPE_REAL
283#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
284#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_REAL(name)
285#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
286#include "PGMAllBth.h"
287#undef BTH_PGMPOOLKIND_PT_FOR_PT
288#undef PGM_BTH_NAME
289#undef PGM_GST_TYPE
290#undef PGM_GST_NAME
291
292/* Guest - protected mode */
293#define PGM_GST_TYPE PGM_TYPE_PROT
294#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
295#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PROT(name)
296#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
297#include "PGMAllBth.h"
298#undef BTH_PGMPOOLKIND_PT_FOR_PT
299#undef PGM_BTH_NAME
300#undef PGM_GST_TYPE
301#undef PGM_GST_NAME
302
303/* Guest - 32-bit mode */
304#define PGM_GST_TYPE PGM_TYPE_32BIT
305#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
306#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_32BIT(name)
307#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
308#include "PGMAllBth.h"
309#undef BTH_PGMPOOLKIND_PT_FOR_PT
310#undef PGM_BTH_NAME
311#undef PGM_GST_TYPE
312#undef PGM_GST_NAME
313
314/* Guest - PAE mode */
315#define PGM_GST_TYPE PGM_TYPE_PAE
316#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
317#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PAE(name)
318#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
319#include "PGMAllBth.h"
320#undef BTH_PGMPOOLKIND_PT_FOR_PT
321#undef PGM_BTH_NAME
322#undef PGM_GST_TYPE
323#undef PGM_GST_NAME
324
325/* Guest - AMD64 mode */
326#define PGM_GST_TYPE PGM_TYPE_AMD64
327#define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
328#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_AMD64(name)
329#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
330#include "PGMAllBth.h"
331#undef BTH_PGMPOOLKIND_PT_FOR_PT
332#undef PGM_BTH_NAME
333#undef PGM_GST_TYPE
334#undef PGM_GST_NAME
335
336#undef PGM_SHW_TYPE
337#undef PGM_SHW_NAME
338
339#endif
340
341/**
342 * #PF Handler.
343 *
344 * @returns VBox status code (appropriate for trap handling and GC return).
345 * @param pVM VM Handle.
346 * @param uErr The trap error code.
347 * @param pRegFrame Trap register frame.
348 * @param pvFault The fault address.
349 */
350VMMDECL(int) PGMTrap0eHandler(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
351{
352 LogFlow(("PGMTrap0eHandler: uErr=%RGu pvFault=%VGv eip=%VGv\n", uErr, pvFault, pRegFrame->rip));
353 STAM_PROFILE_START(&pVM->pgm.s.StatGCTrap0e, a);
354 STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = NULL; } );
355
356
357#ifdef VBOX_WITH_STATISTICS
358 /*
359 * Error code stats.
360 */
361 if (uErr & X86_TRAP_PF_US)
362 {
363 if (!(uErr & X86_TRAP_PF_P))
364 {
365 if (uErr & X86_TRAP_PF_RW)
366 STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eUSNotPresentWrite);
367 else
368 STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eUSNotPresentRead);
369 }
370 else if (uErr & X86_TRAP_PF_RW)
371 STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eUSWrite);
372 else if (uErr & X86_TRAP_PF_RSVD)
373 STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eUSReserved);
374 else if (uErr & X86_TRAP_PF_ID)
375 STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eUSNXE);
376 else
377 STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eUSRead);
378 }
379 else
380 { /* Supervisor */
381 if (!(uErr & X86_TRAP_PF_P))
382 {
383 if (uErr & X86_TRAP_PF_RW)
384 STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eSVNotPresentWrite);
385 else
386 STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eSVNotPresentRead);
387 }
388 else if (uErr & X86_TRAP_PF_RW)
389 STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eSVWrite);
390 else if (uErr & X86_TRAP_PF_ID)
391 STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eSNXE);
392 else if (uErr & X86_TRAP_PF_RSVD)
393 STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eSVReserved);
394 }
395#endif
396
397 /*
398 * Call the worker.
399 */
400 int rc = PGM_BTH_PFN(Trap0eHandler, pVM)(pVM, uErr, pRegFrame, pvFault);
401 if (rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
402 rc = VINF_SUCCESS;
403 STAM_STATS({ if (!pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution))
404 pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eMisc; });
405 STAM_PROFILE_STOP_EX(&pVM->pgm.s.StatGCTrap0e, pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution), a);
406 return rc;
407}
408
409/**
410 * Prefetch a page
411 *
412 * Typically used to sync commonly used pages before entering raw mode
413 * after a CR3 reload.
414 *
415 * @returns VBox status code suitable for scheduling.
416 * @retval VINF_SUCCESS on success.
417 * @retval VINF_PGM_SYNC_CR3 if we're out of shadow pages or something like that.
418 * @param pVM VM handle.
419 * @param GCPtrPage Page to invalidate.
420 */
421VMMDECL(int) PGMPrefetchPage(PVM pVM, RTGCPTR GCPtrPage)
422{
423 STAM_PROFILE_START(&pVM->pgm.s.StatHCPrefetch, a);
424 int rc = PGM_BTH_PFN(PrefetchPage, pVM)(pVM, (RTGCUINTPTR)GCPtrPage);
425 STAM_PROFILE_STOP(&pVM->pgm.s.StatHCPrefetch, a);
426 AssertMsg(rc == VINF_SUCCESS || rc == VINF_PGM_SYNC_CR3 || VBOX_FAILURE(rc), ("rc=%Vrc\n", rc));
427 return rc;
428}
429
430
431/**
432 * Gets the mapping corresponding to the specified address (if any).
433 *
434 * @returns Pointer to the mapping.
435 * @returns NULL if not
436 *
437 * @param pVM The virtual machine.
438 * @param GCPtr The guest context pointer.
439 */
440PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr)
441{
442 PPGMMAPPING pMapping = CTXALLSUFF(pVM->pgm.s.pMappings);
443 while (pMapping)
444 {
445 if ((uintptr_t)GCPtr < (uintptr_t)pMapping->GCPtr)
446 break;
447 if ((uintptr_t)GCPtr - (uintptr_t)pMapping->GCPtr < pMapping->cb)
448 {
449 STAM_COUNTER_INC(&pVM->pgm.s.StatGCSyncPTConflict);
450 return pMapping;
451 }
452 pMapping = CTXALLSUFF(pMapping->pNext);
453 }
454 return NULL;
455}
456
457
458/**
459 * Verifies a range of pages for read or write access
460 *
461 * Only checks the guest's page tables
462 *
463 * @returns VBox status code.
464 * @param pVM VM handle.
465 * @param Addr Guest virtual address to check
466 * @param cbSize Access size
467 * @param fAccess Access type (r/w, user/supervisor (X86_PTE_*))
468 */
469VMMDECL(int) PGMIsValidAccess(PVM pVM, RTGCUINTPTR Addr, uint32_t cbSize, uint32_t fAccess)
470{
471 /*
472 * Validate input.
473 */
474 if (fAccess & ~(X86_PTE_US | X86_PTE_RW))
475 {
476 AssertMsgFailed(("PGMIsValidAccess: invalid access type %08x\n", fAccess));
477 return VERR_INVALID_PARAMETER;
478 }
479
480 uint64_t fPage;
481 int rc = PGMGstGetPage(pVM, (RTGCPTR)Addr, &fPage, NULL);
482 if (VBOX_FAILURE(rc))
483 {
484 Log(("PGMIsValidAccess: access violation for %VGv rc=%d\n", Addr, rc));
485 return VINF_EM_RAW_GUEST_TRAP;
486 }
487
488 /*
489 * Check if the access would cause a page fault
490 *
491 * Note that hypervisor page directories are not present in the guest's tables, so this check
492 * is sufficient.
493 */
494 bool fWrite = !!(fAccess & X86_PTE_RW);
495 bool fUser = !!(fAccess & X86_PTE_US);
496 if ( !(fPage & X86_PTE_P)
497 || (fWrite && !(fPage & X86_PTE_RW))
498 || (fUser && !(fPage & X86_PTE_US)) )
499 {
500 Log(("PGMIsValidAccess: access violation for %VGv attr %#llx vs %d:%d\n", Addr, fPage, fWrite, fUser));
501 return VINF_EM_RAW_GUEST_TRAP;
502 }
503 if ( VBOX_SUCCESS(rc)
504 && PAGE_ADDRESS(Addr) != PAGE_ADDRESS(Addr + cbSize))
505 return PGMIsValidAccess(pVM, Addr + PAGE_SIZE, (cbSize > PAGE_SIZE) ? cbSize - PAGE_SIZE : 1, fAccess);
506 return rc;
507}
508
509
510/**
511 * Verifies a range of pages for read or write access
512 *
513 * Supports handling of pages marked for dirty bit tracking and CSAM
514 *
515 * @returns VBox status code.
516 * @param pVM VM handle.
517 * @param Addr Guest virtual address to check
518 * @param cbSize Access size
519 * @param fAccess Access type (r/w, user/supervisor (X86_PTE_*))
520 */
521VMMDECL(int) PGMVerifyAccess(PVM pVM, RTGCUINTPTR Addr, uint32_t cbSize, uint32_t fAccess)
522{
523 /*
524 * Validate input.
525 */
526 if (fAccess & ~(X86_PTE_US | X86_PTE_RW))
527 {
528 AssertMsgFailed(("PGMVerifyAccess: invalid access type %08x\n", fAccess));
529 return VERR_INVALID_PARAMETER;
530 }
531
532 uint64_t fPageGst;
533 int rc = PGMGstGetPage(pVM, (RTGCPTR)Addr, &fPageGst, NULL);
534 if (VBOX_FAILURE(rc))
535 {
536 Log(("PGMVerifyAccess: access violation for %VGv rc=%d\n", Addr, rc));
537 return VINF_EM_RAW_GUEST_TRAP;
538 }
539
540 /*
541 * Check if the access would cause a page fault
542 *
543 * Note that hypervisor page directories are not present in the guest's tables, so this check
544 * is sufficient.
545 */
546 const bool fWrite = !!(fAccess & X86_PTE_RW);
547 const bool fUser = !!(fAccess & X86_PTE_US);
548 if ( !(fPageGst & X86_PTE_P)
549 || (fWrite && !(fPageGst & X86_PTE_RW))
550 || (fUser && !(fPageGst & X86_PTE_US)) )
551 {
552 Log(("PGMVerifyAccess: access violation for %VGv attr %#llx vs %d:%d\n", Addr, fPageGst, fWrite, fUser));
553 return VINF_EM_RAW_GUEST_TRAP;
554 }
555
556 if (!HWACCMIsNestedPagingActive(pVM))
557 {
558 /*
559 * Next step is to verify if we protected this page for dirty bit tracking or for CSAM scanning
560 */
561 rc = PGMShwGetPage(pVM, (RTGCPTR)Addr, NULL, NULL);
562 if ( rc == VERR_PAGE_NOT_PRESENT
563 || rc == VERR_PAGE_TABLE_NOT_PRESENT)
564 {
565 /*
566 * Page is not present in our page tables.
567 * Try to sync it!
568 */
569 Assert(X86_TRAP_PF_RW == X86_PTE_RW && X86_TRAP_PF_US == X86_PTE_US);
570 uint32_t uErr = fAccess & (X86_TRAP_PF_RW | X86_TRAP_PF_US);
571 rc = PGM_BTH_PFN(VerifyAccessSyncPage, pVM)(pVM, Addr, fPageGst, uErr);
572 if (rc != VINF_SUCCESS)
573 return rc;
574 }
575 else
576 AssertMsg(rc == VINF_SUCCESS, ("PGMShwGetPage %VGv failed with %Vrc\n", Addr, rc));
577 }
578
579#if 0 /* def VBOX_STRICT; triggers too often now */
580 /*
581 * This check is a bit paranoid, but useful.
582 */
583 /** @note this will assert when writing to monitored pages (a bit annoying actually) */
584 uint64_t fPageShw;
585 rc = PGMShwGetPage(pVM, (RTGCPTR)Addr, &fPageShw, NULL);
586 if ( (rc == VERR_PAGE_NOT_PRESENT || VBOX_FAILURE(rc))
587 || (fWrite && !(fPageShw & X86_PTE_RW))
588 || (fUser && !(fPageShw & X86_PTE_US)) )
589 {
590 AssertMsgFailed(("Unexpected access violation for %VGv! rc=%Vrc write=%d user=%d\n",
591 Addr, rc, fWrite && !(fPageShw & X86_PTE_RW), fUser && !(fPageShw & X86_PTE_US)));
592 return VINF_EM_RAW_GUEST_TRAP;
593 }
594#endif
595
596 if ( VBOX_SUCCESS(rc)
597 && ( PAGE_ADDRESS(Addr) != PAGE_ADDRESS(Addr + cbSize - 1)
598 || Addr + cbSize < Addr))
599 {
600 /* Don't recursively call PGMVerifyAccess as we might run out of stack. */
601 for (;;)
602 {
603 Addr += PAGE_SIZE;
604 if (cbSize > PAGE_SIZE)
605 cbSize -= PAGE_SIZE;
606 else
607 cbSize = 1;
608 rc = PGMVerifyAccess(pVM, Addr, 1, fAccess);
609 if (rc != VINF_SUCCESS)
610 break;
611 if (PAGE_ADDRESS(Addr) == PAGE_ADDRESS(Addr + cbSize - 1))
612 break;
613 }
614 }
615 return rc;
616}
617
618
619#ifndef IN_GC
620/**
621 * Emulation of the invlpg instruction (HC only actually).
622 *
623 * @returns VBox status code.
624 * @param pVM VM handle.
625 * @param GCPtrPage Page to invalidate.
626 * @remark ASSUMES the page table entry or page directory is
627 * valid. Fairly safe, but there could be edge cases!
628 * @todo Flush page or page directory only if necessary!
629 */
630VMMDECL(int) PGMInvalidatePage(PVM pVM, RTGCPTR GCPtrPage)
631{
632 int rc;
633
634 Log3(("PGMInvalidatePage: GCPtrPage=%VGv\n", GCPtrPage));
635
636 /** @todo merge PGMGCInvalidatePage with this one */
637
638#ifndef IN_RING3
639 /*
640 * Notify the recompiler so it can record this instruction.
641 * Failure happens when it's out of space. We'll return to HC in that case.
642 */
643 rc = REMNotifyInvalidatePage(pVM, GCPtrPage);
644 if (VBOX_FAILURE(rc))
645 return rc;
646#endif
647
648 STAM_PROFILE_START(&CTXMID(pVM->pgm.s.Stat,InvalidatePage), a);
649 rc = PGM_BTH_PFN(InvalidatePage, pVM)(pVM, GCPtrPage);
650 STAM_PROFILE_STOP(&CTXMID(pVM->pgm.s.Stat,InvalidatePage), a);
651
652#ifndef IN_RING0
653 /*
654 * Check if we have a pending update of the CR3 monitoring.
655 */
656 if ( VBOX_SUCCESS(rc)
657 && (pVM->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3))
658 {
659 pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
660 Assert(!pVM->pgm.s.fMappingsFixed);
661 Assert(pVM->pgm.s.GCPhysCR3 == pVM->pgm.s.GCPhysGstCR3Monitored);
662 rc = PGM_GST_PFN(MonitorCR3, pVM)(pVM, pVM->pgm.s.GCPhysCR3);
663 }
664#endif
665
666#ifdef IN_RING3
667 /*
668 * Inform CSAM about the flush
669 */
670 /** @note this is to check if monitored pages have been changed; when we implement callbacks for virtual handlers, this is no longer required. */
671 CSAMR3FlushPage(pVM, GCPtrPage);
672#endif
673 return rc;
674}
675#endif
676
677
678/**
679 * Executes an instruction using the interpreter.
680 *
681 * @returns VBox status code (appropriate for trap handling and GC return).
682 * @param pVM VM handle.
683 * @param pRegFrame Register frame.
684 * @param pvFault Fault address.
685 */
686VMMDECL(int) PGMInterpretInstruction(PVM pVM, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
687{
688 uint32_t cb;
689 int rc = EMInterpretInstruction(pVM, pRegFrame, pvFault, &cb);
690 if (rc == VERR_EM_INTERPRETER)
691 rc = VINF_EM_RAW_EMULATE_INSTR;
692 if (rc != VINF_SUCCESS)
693 Log(("PGMInterpretInstruction: returns %Rrc (pvFault=%VGv)\n", rc, pvFault));
694 return rc;
695}
696
697
698/**
699 * Gets effective page information (from the VMM page directory).
700 *
701 * @returns VBox status.
702 * @param pVM VM Handle.
703 * @param GCPtr Guest Context virtual address of the page.
704 * @param pfFlags Where to store the flags. These are X86_PTE_*.
705 * @param pHCPhys Where to store the HC physical address of the page.
706 * This is page aligned.
707 * @remark You should use PGMMapGetPage() for pages in a mapping.
708 */
709VMMDECL(int) PGMShwGetPage(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys)
710{
711 return PGM_SHW_PFN(GetPage,pVM)(pVM, (RTGCUINTPTR)GCPtr, pfFlags, pHCPhys);
712}
713
714
715/**
716 * Sets (replaces) the page flags for a range of pages in the shadow context.
717 *
718 * @returns VBox status.
719 * @param pVM VM handle.
720 * @param GCPtr The address of the first page.
721 * @param cb The size of the range in bytes.
722 * @param fFlags Page flags X86_PTE_*, excluding the page mask of course.
723 * @remark You must use PGMMapSetPage() for pages in a mapping.
724 */
725VMMDECL(int) PGMShwSetPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags)
726{
727 return PGMShwModifyPage(pVM, GCPtr, cb, fFlags, 0);
728}
729
730
731/**
732 * Modify page flags for a range of pages in the shadow context.
733 *
734 * The existing flags are ANDed with the fMask and ORed with the fFlags.
735 *
736 * @returns VBox status code.
737 * @param pVM VM handle.
738 * @param GCPtr Virtual address of the first page in the range.
739 * @param cb Size (in bytes) of the range to apply the modification to.
740 * @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
741 * @param fMask The AND mask - page flags X86_PTE_*.
742 * Be very CAREFUL when ~'ing constants which could be 32-bit!
743 * @remark You must use PGMMapModifyPage() for pages in a mapping.
744 */
745VMMDECL(int) PGMShwModifyPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
746{
747 /*
748 * Validate input.
749 */
750 if (fFlags & X86_PTE_PAE_PG_MASK)
751 {
752 AssertMsgFailed(("fFlags=%#llx\n", fFlags));
753 return VERR_INVALID_PARAMETER;
754 }
755 if (!cb)
756 {
757 AssertFailed();
758 return VERR_INVALID_PARAMETER;
759 }
760
761 /*
762 * Align the input.
763 */
764 cb += (RTGCUINTPTR)GCPtr & PAGE_OFFSET_MASK;
765 cb = RT_ALIGN_Z(cb, PAGE_SIZE);
766 GCPtr = (RTGCPTR)((RTGCUINTPTR)GCPtr & PAGE_BASE_GC_MASK); /** @todo this ain't necessary, right... */
767
768 /*
769 * Call worker.
770 */
771 return PGM_SHW_PFN(ModifyPage, pVM)(pVM, (RTGCUINTPTR)GCPtr, cb, fFlags, fMask);
772}
773
774/**
775 * Syncs the SHADOW page directory pointer for the specified address. Allocates
776 * backing pages in case the PDPT entry is missing.
777 *
778 * @returns VBox status.
779 * @param pVM VM handle.
780 * @param GCPtr The address.
781 * @param pGstPdpe Guest PDPT entry
782 * @param ppPD Receives address of page directory
783 */
784VMMDECL(int) PGMShwSyncPAEPDPtr(PVM pVM, RTGCUINTPTR GCPtr, PX86PDPE pGstPdpe, PX86PDPAE *ppPD)
785{
786 PPGM pPGM = &pVM->pgm.s;
787 PPGMPOOL pPool = pPGM->CTXSUFF(pPool);
788 PPGMPOOLPAGE pShwPage;
789 int rc;
790
791 Assert(!HWACCMIsNestedPagingActive(pVM));
792
793 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
794 PX86PDPT pPdpt = pVM->pgm.s.CTXMID(p,PaePDPT);
795 PX86PDPE pPdpe = &pPdpt->a[iPdPt];
796
797 /* Allocate page directory if not present. */
798 if ( !pPdpe->n.u1Present
799 && !(pPdpe->u & X86_PDPE_PG_MASK))
800 {
801 PX86PDPE pPdptGst = &CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt];
802
803 Assert(!(pPdpe->u & X86_PDPE_PG_MASK));
804 /* Create a reference back to the PDPT by using the index in its shadow page. */
805 rc = pgmPoolAlloc(pVM, pPdptGst->u & X86_PDPE_PG_MASK, PGMPOOLKIND_PAE_PD_FOR_PAE_PD, PGMPOOL_IDX_PDPT, iPdPt, &pShwPage);
806 if (rc == VERR_PGM_POOL_FLUSHED)
807 {
808 Assert(pVM->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL);
809 VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
810 return VINF_PGM_SYNC_CR3;
811 }
812 AssertRCReturn(rc, rc);
813 }
814 else
815 {
816 pShwPage = pgmPoolGetPage(pPool, pPdpe->u & X86_PDPE_PG_MASK);
817 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
818 }
819 /* The PD was cached or created; hook it up now. */
820 pPdpe->u |= pShwPage->Core.Key
821 | (pGstPdpe->u & ~(X86_PDPE_PG_MASK | X86_PDPE_AVL_MASK | X86_PDPE_PCD | X86_PDPE_PWT));
822
823 *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
824 return VINF_SUCCESS;
825}
826
827/**
828 * Gets the SHADOW page directory pointer for the specified address.
829 *
830 * @returns VBox status.
831 * @param pVM VM handle.
832 * @param GCPtr The address.
833 * @param ppPdpt Receives address of pdpt
834 * @param ppPD Receives address of page directory
835 */
836VMMDECL(int) PGMShwGetPAEPDPtr(PVM pVM, RTGCUINTPTR GCPtr, PX86PDPT *ppPdpt, PX86PDPAE *ppPD)
837{
838 PPGM pPGM = &pVM->pgm.s;
839 PPGMPOOL pPool = pPGM->CTXSUFF(pPool);
840 PPGMPOOLPAGE pShwPage;
841
842 Assert(!HWACCMIsNestedPagingActive(pVM));
843
844 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
845 PX86PDPT pPdpt = pVM->pgm.s.CTXMID(p,PaePDPT);
846 PX86PDPE pPdpe = &pPdpt->a[iPdPt];
847
848 *ppPdpt = pPdpt;
849 if (!pPdpe->n.u1Present)
850 return VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT;
851
852 pShwPage = pgmPoolGetPage(pPool, pPdpe->u & X86_PDPE_PG_MASK);
853 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
854
855 *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
856 return VINF_SUCCESS;
857}
858
859#ifndef IN_GC
860/**
861 * Syncs the SHADOW page directory pointer for the specified address. Allocates
862 * backing pages in case the PDPT or PML4 entry is missing.
863 *
864 * @returns VBox status.
865 * @param pVM VM handle.
866 * @param GCPtr The address.
867 * @param pGstPml4e Guest PML4 entry
868 * @param pGstPdpe Guest PDPT entry
869 * @param ppPD Receives address of page directory
870 */
871VMMDECL(int) PGMShwSyncLongModePDPtr(PVM pVM, RTGCUINTPTR64 GCPtr, PX86PML4E pGstPml4e, PX86PDPE pGstPdpe, PX86PDPAE *ppPD)
872{
873 PPGM pPGM = &pVM->pgm.s;
874 const unsigned iPml4e = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
875 PPGMPOOL pPool = pPGM->CTXSUFF(pPool);
876 PX86PML4E pPml4e;
877 PPGMPOOLPAGE pShwPage;
878 int rc;
879 bool fNestedPaging = HWACCMIsNestedPagingActive(pVM);
880
881 Assert(pVM->pgm.s.pHCPaePML4);
882
883 /* Allocate page directory pointer table if not present. */
884 pPml4e = &pPGM->pHCPaePML4->a[iPml4e];
885 if ( !pPml4e->n.u1Present
886 && !(pPml4e->u & X86_PML4E_PG_MASK))
887 {
888 Assert(!(pPml4e->u & X86_PML4E_PG_MASK));
889
890 if (!fNestedPaging)
891 {
892 Assert(pVM->pgm.s.pHCShwAmd64CR3);
893 Assert(pPGM->pGstPaePML4HC);
894
895 PX86PML4E pPml4eGst = &pPGM->pGstPaePML4HC->a[iPml4e];
896
897 rc = pgmPoolAlloc(pVM, pPml4eGst->u & X86_PML4E_PG_MASK, PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT, pVM->pgm.s.pHCShwAmd64CR3->idx, iPml4e, &pShwPage);
898 }
899 else
900 rc = pgmPoolAlloc(pVM, GCPtr + RT_BIT_64(63) /* hack: make the address unique */, PGMPOOLKIND_64BIT_PDPT_FOR_PHYS, PGMPOOL_IDX_NESTED_ROOT, iPml4e, &pShwPage);
901
902 if (rc == VERR_PGM_POOL_FLUSHED)
903 {
904 Log(("PGMShwSyncLongModePDPtr: PGM pool flushed (1) -> signal sync cr3\n"));
905 Assert(pVM->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL);
906 VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
907 return VINF_PGM_SYNC_CR3;
908 }
909 AssertRCReturn(rc, rc);
910 }
911 else
912 {
913 pShwPage = pgmPoolGetPage(pPool, pPml4e->u & X86_PML4E_PG_MASK);
914 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
915 }
916 /* The PDPT was cached or created; hook it up now. */
917 pPml4e->u |= pShwPage->Core.Key
918 | (pGstPml4e->u & ~(X86_PML4E_PG_MASK | X86_PML4E_AVL_MASK | X86_PML4E_PCD | X86_PML4E_PWT));
919
920 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
921 PX86PDPT pPdpt = (PX86PDPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
922 PX86PDPE pPdpe = &pPdpt->a[iPdPt];
923
924 /* Allocate page directory if not present. */
925 if ( !pPdpe->n.u1Present
926 && !(pPdpe->u & X86_PDPE_PG_MASK))
927 {
928 if (!fNestedPaging)
929 {
930 Assert(pPGM->pGstPaePML4HC);
931
932 PX86PML4E pPml4eGst = &pPGM->pGstPaePML4HC->a[iPml4e];
933 PX86PDPT pPdptGst;
934 rc = PGM_GCPHYS_2_PTR(pVM, pPml4eGst->u & X86_PML4E_PG_MASK, &pPdptGst);
935 AssertRCReturn(rc, rc);
936
937 Assert(!(pPdpe->u & X86_PDPE_PG_MASK));
938 /* Create a reference back to the PDPT by using the index in its shadow page. */
939 rc = pgmPoolAlloc(pVM, pPdptGst->a[iPdPt].u & X86_PDPE_PG_MASK, PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD, pShwPage->idx, iPdPt, &pShwPage);
940 }
941 else
942 rc = pgmPoolAlloc(pVM, GCPtr + RT_BIT_64(62) /* hack: make the address unique */, PGMPOOLKIND_64BIT_PD_FOR_PHYS, pShwPage->idx, iPdPt, &pShwPage);
943
944 if (rc == VERR_PGM_POOL_FLUSHED)
945 {
946 Log(("PGMShwSyncLongModePDPtr: PGM pool flushed (2) -> signal sync cr3\n"));
947 Assert(pVM->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL);
948 VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
949 return VINF_PGM_SYNC_CR3;
950 }
951 AssertRCReturn(rc, rc);
952 }
953 else
954 {
955 pShwPage = pgmPoolGetPage(pPool, pPdpe->u & X86_PDPE_PG_MASK);
956 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
957 }
958 /* The PD was cached or created; hook it up now. */
959 pPdpe->u |= pShwPage->Core.Key
960 | (pGstPdpe->u & ~(X86_PDPE_PG_MASK | X86_PDPE_AVL_MASK | X86_PDPE_PCD | X86_PDPE_PWT));
961
962 *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
963 return VINF_SUCCESS;
964}
965
966/**
967 * Gets the SHADOW page directory pointer for the specified address.
968 *
969 * @returns VBox status.
970 * @param pVM VM handle.
971 * @param GCPtr The address.
972 * @param ppPdpt Receives address of pdpt
973 * @param ppPD Receives address of page directory
974 */
975VMMDECL(int) PGMShwGetLongModePDPtr(PVM pVM, RTGCUINTPTR64 GCPtr, PX86PDPT *ppPdpt, PX86PDPAE *ppPD)
976{
977 PPGM pPGM = &pVM->pgm.s;
978 const unsigned iPml4e = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
979 PPGMPOOL pPool = pPGM->CTXSUFF(pPool);
980 PX86PML4E pPml4e;
981 PPGMPOOLPAGE pShwPage;
982
983 AssertReturn(pVM->pgm.s.pHCPaePML4, VERR_INTERNAL_ERROR);
984
985 pPml4e = &pPGM->pHCPaePML4->a[iPml4e];
986 if (!pPml4e->n.u1Present)
987 return VERR_PAGE_MAP_LEVEL4_NOT_PRESENT;
988
989 pShwPage = pgmPoolGetPage(pPool, pPml4e->u & X86_PML4E_PG_MASK);
990 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
991
992 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
993 PX86PDPT pPdpt = (PX86PDPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
994 PX86PDPE pPdpe = &pPdpt->a[iPdPt];
995
996 *ppPdpt = pPdpt;
997 if (!pPdpe->n.u1Present)
998 return VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT;
999
1000 pShwPage = pgmPoolGetPage(pPool, pPdpe->u & X86_PDPE_PG_MASK);
1001 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1002
1003 *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1004 return VINF_SUCCESS;
1005}
1006
1007/**
1008 * Syncs the SHADOW EPT page directory pointer for the specified address. Allocates
1009 * backing pages in case the PDPT or PML4 entry is missing.
1010 *
1011 * @returns VBox status.
1012 * @param pVM VM handle.
1013 * @param GCPtr The address.
1014 * @param ppPdpt Receives address of pdpt
1015 * @param ppPD Receives address of page directory
1016 */
1017VMMDECL(int) PGMShwGetEPTPDPtr(PVM pVM, RTGCUINTPTR64 GCPtr, PEPTPDPT *ppPdpt, PEPTPD *ppPD)
1018{
1019 PPGM pPGM = &pVM->pgm.s;
1020 const unsigned iPml4e = (GCPtr >> EPT_PML4_SHIFT) & EPT_PML4_MASK;
1021 PPGMPOOL pPool = pPGM->CTXSUFF(pPool);
1022 PEPTPML4 pPml4 = (PEPTPML4)pPGM->pHCNestedRoot;
1023 PEPTPML4E pPml4e;
1024 PPGMPOOLPAGE pShwPage;
1025 int rc;
1026
1027 Assert(HWACCMIsNestedPagingActive(pVM));
1028 Assert(pPml4);
1029
1030 /* Allocate page directory pointer table if not present. */
1031 pPml4e = &pPml4->a[iPml4e];
1032 if ( !pPml4e->n.u1Present
1033 && !(pPml4e->u & EPT_PML4E_PG_MASK))
1034 {
1035 Assert(!(pPml4e->u & EPT_PML4E_PG_MASK));
1036
1037 rc = pgmPoolAlloc(pVM, (GCPtr & EPT_PML4E_PG_MASK) + RT_BIT_64(63) /* hack: make the address unique */, PGMPOOLKIND_EPT_PDPT_FOR_PHYS, PGMPOOL_IDX_NESTED_ROOT, iPml4e, &pShwPage);
1038 if (rc == VERR_PGM_POOL_FLUSHED)
1039 {
1040 Assert(pVM->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL);
1041 VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
1042 return VINF_PGM_SYNC_CR3;
1043 }
1044 AssertRCReturn(rc, rc);
1045 }
1046 else
1047 {
1048 pShwPage = pgmPoolGetPage(pPool, pPml4e->u & EPT_PML4E_PG_MASK);
1049 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1050 }
1051 /* The PDPT was cached or created; hook it up now and fill with the default value. */
1052 pPml4e->u = pShwPage->Core.Key;
1053 pPml4e->n.u1Present = 1;
1054 pPml4e->n.u1Write = 1;
1055 pPml4e->n.u1Execute = 1;
1056
1057 const unsigned iPdPt = (GCPtr >> EPT_PDPT_SHIFT) & EPT_PDPT_MASK;
1058 PEPTPDPT pPdpt = (PEPTPDPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1059 PEPTPDPTE pPdpe = &pPdpt->a[iPdPt];
1060
1061 if (ppPdpt)
1062 *ppPdpt = pPdpt;
1063
1064 /* Allocate page directory if not present. */
1065 if ( !pPdpe->n.u1Present
1066 && !(pPdpe->u & EPT_PDPTE_PG_MASK))
1067 {
1068 rc = pgmPoolAlloc(pVM, (GCPtr & EPT_PDPTE_PG_MASK) + RT_BIT_64(62) /* hack: make the address unique */, PGMPOOLKIND_64BIT_PD_FOR_PHYS, pShwPage->idx, iPdPt, &pShwPage);
1069 if (rc == VERR_PGM_POOL_FLUSHED)
1070 {
1071 Assert(pVM->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL);
1072 VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
1073 return VINF_PGM_SYNC_CR3;
1074 }
1075 AssertRCReturn(rc, rc);
1076 }
1077 else
1078 {
1079 pShwPage = pgmPoolGetPage(pPool, pPdpe->u & X86_PDPE_PG_MASK);
1080 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1081 }
1082 /* The PD was cached or created; hook it up now and fill with the default value. */
1083 pPdpe->u = pShwPage->Core.Key;
1084 pPdpe->n.u1Present = 1;
1085 pPdpe->n.u1Write = 1;
1086 pPdpe->n.u1Execute = 1;
1087
1088 *ppPD = (PEPTPD)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1089 return VINF_SUCCESS;
1090}
1091
1092#endif
1093
1094/**
1095 * Gets effective Guest OS page information.
1096 *
1097 * When GCPtr is in a big page, the function will return as if it was a normal
1098 * 4KB page. If the need for distinguishing between big and normal page becomes
1099 * necessary at a later point, a PGMGstGetPage() will be created for that
1100 * purpose.
1101 *
1102 * @returns VBox status.
1103 * @param pVM VM Handle.
1104 * @param GCPtr Guest Context virtual address of the page.
1105 * @param pfFlags Where to store the flags. These are X86_PTE_*, even for big pages.
1106 * @param pGCPhys Where to store the GC physical address of the page.
1107 * This is page aligned. The fact that the
1108 */
1109VMMDECL(int) PGMGstGetPage(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys)
1110{
1111 return PGM_GST_PFN(GetPage,pVM)(pVM, (RTGCUINTPTR)GCPtr, pfFlags, pGCPhys);
1112}
1113
1114
1115/**
1116 * Checks if the page is present.
1117 *
1118 * @returns true if the page is present.
1119 * @returns false if the page is not present.
1120 * @param pVM The VM handle.
1121 * @param GCPtr Address within the page.
1122 */
1123VMMDECL(bool) PGMGstIsPagePresent(PVM pVM, RTGCPTR GCPtr)
1124{
1125 int rc = PGMGstGetPage(pVM, GCPtr, NULL, NULL);
1126 return VBOX_SUCCESS(rc);
1127}
1128
1129
1130/**
1131 * Sets (replaces) the page flags for a range of pages in the guest's tables.
1132 *
1133 * @returns VBox status.
1134 * @param pVM VM handle.
1135 * @param GCPtr The address of the first page.
1136 * @param cb The size of the range in bytes.
1137 * @param fFlags Page flags X86_PTE_*, excluding the page mask of course.
1138 */
1139VMMDECL(int) PGMGstSetPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags)
1140{
1141 return PGMGstModifyPage(pVM, GCPtr, cb, fFlags, 0);
1142}
1143
1144
1145/**
1146 * Modify page flags for a range of pages in the guest's tables
1147 *
1148 * The existing flags are ANDed with the fMask and ORed with the fFlags.
1149 *
1150 * @returns VBox status code.
1151 * @param pVM VM handle.
1152 * @param GCPtr Virtual address of the first page in the range.
1153 * @param cb Size (in bytes) of the range to apply the modification to.
1154 * @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
1155 * @param fMask The AND mask - page flags X86_PTE_*, excluding the page mask of course.
1156 * Be very CAREFUL when ~'ing constants which could be 32-bit!
1157 */
1158VMMDECL(int) PGMGstModifyPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
1159{
1160 STAM_PROFILE_START(&CTXMID(pVM->pgm.s.Stat,GstModifyPage), a);
1161
1162 /*
1163 * Validate input.
1164 */
1165 if (fFlags & X86_PTE_PAE_PG_MASK)
1166 {
1167 AssertMsgFailed(("fFlags=%#llx\n", fFlags));
1168 STAM_PROFILE_STOP(&CTXMID(pVM->pgm.s.Stat,GstModifyPage), a);
1169 return VERR_INVALID_PARAMETER;
1170 }
1171
1172 if (!cb)
1173 {
1174 AssertFailed();
1175 STAM_PROFILE_STOP(&CTXMID(pVM->pgm.s.Stat,GstModifyPage), a);
1176 return VERR_INVALID_PARAMETER;
1177 }
1178
1179 LogFlow(("PGMGstModifyPage %VGv %d bytes fFlags=%08llx fMask=%08llx\n", GCPtr, cb, fFlags, fMask));
1180
1181 /*
1182 * Adjust input.
1183 */
1184 cb += (RTGCUINTPTR)GCPtr & PAGE_OFFSET_MASK;
1185 cb = RT_ALIGN_Z(cb, PAGE_SIZE);
1186 GCPtr = (RTGCPTR)((RTGCUINTPTR)GCPtr & PAGE_BASE_GC_MASK);
1187
1188 /*
1189 * Call worker.
1190 */
1191 int rc = PGM_GST_PFN(ModifyPage, pVM)(pVM, (RTGCUINTPTR)GCPtr, cb, fFlags, fMask);
1192
1193 STAM_PROFILE_STOP(&CTXMID(pVM->pgm.s.Stat,GstModifyPage), a);
1194 return rc;
1195}
1196
1197
1198/**
1199 * Gets the current CR3 register value for the shadow memory context.
1200 * @returns CR3 value.
1201 * @param pVM The VM handle.
1202 */
1203VMMDECL(RTHCPHYS) PGMGetHyperCR3(PVM pVM)
1204{
1205 PGMMODE enmShadowMode = pVM->pgm.s.enmShadowMode;
1206 switch (enmShadowMode)
1207 {
1208 case PGMMODE_32_BIT:
1209 return pVM->pgm.s.HCPhys32BitPD;
1210
1211 case PGMMODE_PAE:
1212 case PGMMODE_PAE_NX:
1213 return pVM->pgm.s.HCPhysPaePDPT;
1214
1215 case PGMMODE_AMD64:
1216 case PGMMODE_AMD64_NX:
1217 return pVM->pgm.s.HCPhysPaePML4;
1218
1219 case PGMMODE_EPT:
1220 return pVM->pgm.s.HCPhysNestedRoot;
1221
1222 case PGMMODE_NESTED:
1223 return PGMGetNestedCR3(pVM, PGMGetHostMode(pVM));
1224
1225 default:
1226 AssertMsgFailed(("enmShadowMode=%d\n", enmShadowMode));
1227 return ~0;
1228 }
1229}
1230
1231/**
1232 * Gets the current CR3 register value for the nested memory context.
1233 * @returns CR3 value.
1234 * @param pVM The VM handle.
1235 */
1236VMMDECL(RTHCPHYS) PGMGetNestedCR3(PVM pVM, PGMMODE enmShadowMode)
1237{
1238 switch (enmShadowMode)
1239 {
1240 case PGMMODE_32_BIT:
1241 return pVM->pgm.s.HCPhys32BitPD;
1242
1243 case PGMMODE_PAE:
1244 case PGMMODE_PAE_NX:
1245 return pVM->pgm.s.HCPhysPaePDPT;
1246
1247 case PGMMODE_AMD64:
1248 case PGMMODE_AMD64_NX:
1249 return pVM->pgm.s.HCPhysPaePML4;
1250
1251 default:
1252 AssertMsgFailed(("enmShadowMode=%d\n", enmShadowMode));
1253 return ~0;
1254 }
1255}
1256
1257
1258/**
1259 * Gets the CR3 register value for the 32-Bit shadow memory context.
1260 * @returns CR3 value.
1261 * @param pVM The VM handle.
1262 */
1263VMMDECL(RTHCPHYS) PGMGetHyper32BitCR3(PVM pVM)
1264{
1265 return pVM->pgm.s.HCPhys32BitPD;
1266}
1267
1268
1269/**
1270 * Gets the CR3 register value for the PAE shadow memory context.
1271 * @returns CR3 value.
1272 * @param pVM The VM handle.
1273 */
1274VMMDECL(RTHCPHYS) PGMGetHyperPaeCR3(PVM pVM)
1275{
1276 return pVM->pgm.s.HCPhysPaePDPT;
1277}
1278
1279
1280/**
1281 * Gets the CR3 register value for the AMD64 shadow memory context.
1282 * @returns CR3 value.
1283 * @param pVM The VM handle.
1284 */
1285VMMDECL(RTHCPHYS) PGMGetHyperAmd64CR3(PVM pVM)
1286{
1287 return pVM->pgm.s.HCPhysPaePML4;
1288}
1289
1290
1291/**
1292 * Gets the current CR3 register value for the HC intermediate memory context.
1293 * @returns CR3 value.
1294 * @param pVM The VM handle.
1295 */
1296VMMDECL(RTHCPHYS) PGMGetInterHCCR3(PVM pVM)
1297{
1298 switch (pVM->pgm.s.enmHostMode)
1299 {
1300 case SUPPAGINGMODE_32_BIT:
1301 case SUPPAGINGMODE_32_BIT_GLOBAL:
1302 return pVM->pgm.s.HCPhysInterPD;
1303
1304 case SUPPAGINGMODE_PAE:
1305 case SUPPAGINGMODE_PAE_GLOBAL:
1306 case SUPPAGINGMODE_PAE_NX:
1307 case SUPPAGINGMODE_PAE_GLOBAL_NX:
1308 return pVM->pgm.s.HCPhysInterPaePDPT;
1309
1310 case SUPPAGINGMODE_AMD64:
1311 case SUPPAGINGMODE_AMD64_GLOBAL:
1312 case SUPPAGINGMODE_AMD64_NX:
1313 case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1314 return pVM->pgm.s.HCPhysInterPaePDPT;
1315
1316 default:
1317 AssertMsgFailed(("enmHostMode=%d\n", pVM->pgm.s.enmHostMode));
1318 return ~0;
1319 }
1320}
1321
1322
1323/**
1324 * Gets the current CR3 register value for the GC intermediate memory context.
1325 * @returns CR3 value.
1326 * @param pVM The VM handle.
1327 */
1328VMMDECL(RTHCPHYS) PGMGetInterGCCR3(PVM pVM)
1329{
1330 switch (pVM->pgm.s.enmShadowMode)
1331 {
1332 case PGMMODE_32_BIT:
1333 return pVM->pgm.s.HCPhysInterPD;
1334
1335 case PGMMODE_PAE:
1336 case PGMMODE_PAE_NX:
1337 return pVM->pgm.s.HCPhysInterPaePDPT;
1338
1339 case PGMMODE_AMD64:
1340 case PGMMODE_AMD64_NX:
1341 return pVM->pgm.s.HCPhysInterPaePML4;
1342
1343 case PGMMODE_EPT:
1344 case PGMMODE_NESTED:
1345 return 0; /* not relevant */
1346
1347 default:
1348 AssertMsgFailed(("enmShadowMode=%d\n", pVM->pgm.s.enmShadowMode));
1349 return ~0;
1350 }
1351}
1352
1353
1354/**
1355 * Gets the CR3 register value for the 32-Bit intermediate memory context.
1356 * @returns CR3 value.
1357 * @param pVM The VM handle.
1358 */
1359VMMDECL(RTHCPHYS) PGMGetInter32BitCR3(PVM pVM)
1360{
1361 return pVM->pgm.s.HCPhysInterPD;
1362}
1363
1364
1365/**
1366 * Gets the CR3 register value for the PAE intermediate memory context.
1367 * @returns CR3 value.
1368 * @param pVM The VM handle.
1369 */
1370VMMDECL(RTHCPHYS) PGMGetInterPaeCR3(PVM pVM)
1371{
1372 return pVM->pgm.s.HCPhysInterPaePDPT;
1373}
1374
1375
1376/**
1377 * Gets the CR3 register value for the AMD64 intermediate memory context.
1378 * @returns CR3 value.
1379 * @param pVM The VM handle.
1380 */
1381VMMDECL(RTHCPHYS) PGMGetInterAmd64CR3(PVM pVM)
1382{
1383 return pVM->pgm.s.HCPhysInterPaePML4;
1384}
1385
1386
1387/**
1388 * Performs and schedules necessary updates following a CR3 load or reload.
1389 *
1390 * This will normally involve mapping the guest PD or nPDPT
1391 *
1392 * @returns VBox status code.
1393 * @retval VINF_PGM_SYNC_CR3 if monitoring requires a CR3 sync. This can
1394 * safely be ignored and overridden since the FF will be set too then.
1395 * @param pVM VM handle.
1396 * @param cr3 The new cr3.
1397 * @param fGlobal Indicates whether this is a global flush or not.
1398 */
1399VMMDECL(int) PGMFlushTLB(PVM pVM, uint64_t cr3, bool fGlobal)
1400{
1401 STAM_PROFILE_START(&pVM->pgm.s.StatFlushTLB, a);
1402
1403 /*
1404 * Always flag the necessary updates; necessary for hardware acceleration
1405 */
1406 VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
1407 if (fGlobal)
1408 VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
1409 LogFlow(("PGMFlushTLB: cr3=%VX64 OldCr3=%VX64 fGlobal=%d\n", cr3, pVM->pgm.s.GCPhysCR3, fGlobal));
1410
1411 /*
1412 * Remap the CR3 content and adjust the monitoring if CR3 was actually changed.
1413 */
1414 int rc = VINF_SUCCESS;
1415 RTGCPHYS GCPhysCR3;
1416 if ( pVM->pgm.s.enmGuestMode == PGMMODE_PAE
1417 || pVM->pgm.s.enmGuestMode == PGMMODE_PAE_NX
1418 || pVM->pgm.s.enmGuestMode == PGMMODE_AMD64
1419 || pVM->pgm.s.enmGuestMode == PGMMODE_AMD64_NX)
1420 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAE_PAGE_MASK);
1421 else
1422 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAGE_MASK);
1423 if (pVM->pgm.s.GCPhysCR3 != GCPhysCR3)
1424 {
1425 pVM->pgm.s.GCPhysCR3 = GCPhysCR3;
1426 rc = PGM_GST_PFN(MapCR3, pVM)(pVM, GCPhysCR3);
1427 if (VBOX_SUCCESS(rc) && !pVM->pgm.s.fMappingsFixed)
1428 {
1429 pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
1430 rc = PGM_GST_PFN(MonitorCR3, pVM)(pVM, GCPhysCR3);
1431 }
1432 if (fGlobal)
1433 STAM_COUNTER_INC(&pVM->pgm.s.StatFlushTLBNewCR3Global);
1434 else
1435 STAM_COUNTER_INC(&pVM->pgm.s.StatFlushTLBNewCR3);
1436 }
1437 else
1438 {
1439 /*
1440 * Check if we have a pending update of the CR3 monitoring.
1441 */
1442 if (pVM->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
1443 {
1444 pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
1445 Assert(!pVM->pgm.s.fMappingsFixed);
1446 rc = PGM_GST_PFN(MonitorCR3, pVM)(pVM, GCPhysCR3);
1447 }
1448 if (fGlobal)
1449 STAM_COUNTER_INC(&pVM->pgm.s.StatFlushTLBSameCR3Global);
1450 else
1451 STAM_COUNTER_INC(&pVM->pgm.s.StatFlushTLBSameCR3);
1452 }
1453
1454 STAM_PROFILE_STOP(&pVM->pgm.s.StatFlushTLB, a);
1455 return rc;
1456}
1457
1458/**
1459 * Performs and schedules necessary updates following a CR3 load or reload,
1460 * without actually flushing the TLB as with PGMFlushTLB.
1461 *
1462 * This will normally involve mapping the guest PD or nPDPT
1463 *
1464 * @returns VBox status code.
1465 * @retval VINF_PGM_SYNC_CR3 if monitoring requires a CR3 sync. This can
1466 * safely be ignored and overridden since the FF will be set too then.
1467 * @param pVM VM handle.
1468 * @param cr3 The new cr3.
1469 */
1470VMMDECL(int) PGMUpdateCR3(PVM pVM, uint64_t cr3)
1471{
1472 LogFlow(("PGMUpdateCR3: cr3=%VX64 OldCr3=%VX64\n", cr3, pVM->pgm.s.GCPhysCR3));
1473
1474 /* We assume we're only called in nested paging mode. */
1475 Assert(pVM->pgm.s.fMappingsFixed);
1476 Assert(!(pVM->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3));
1477 Assert(pVM->pgm.s.enmShadowMode == PGMMODE_NESTED || pVM->pgm.s.enmShadowMode == PGMMODE_EPT);
1478
1479 /*
1480 * Remap the CR3 content and adjust the monitoring if CR3 was actually changed.
1481 */
1482 int rc = VINF_SUCCESS;
1483 RTGCPHYS GCPhysCR3;
1484 if ( pVM->pgm.s.enmGuestMode == PGMMODE_PAE
1485 || pVM->pgm.s.enmGuestMode == PGMMODE_PAE_NX
1486 || pVM->pgm.s.enmGuestMode == PGMMODE_AMD64
1487 || pVM->pgm.s.enmGuestMode == PGMMODE_AMD64_NX)
1488 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAE_PAGE_MASK);
1489 else
1490 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAGE_MASK);
1491 if (pVM->pgm.s.GCPhysCR3 != GCPhysCR3)
1492 {
1493 pVM->pgm.s.GCPhysCR3 = GCPhysCR3;
1494 rc = PGM_GST_PFN(MapCR3, pVM)(pVM, GCPhysCR3);
1495 }
1496 AssertRC(rc);
1497 return rc;
1498}
1499
1500/**
1501 * Synchronize the paging structures.
1502 *
1503 * This function is called in response to the VM_FF_PGM_SYNC_CR3 and
1504 * VM_FF_PGM_SYNC_CR3_NONGLOBAL. Those two force action flags are set
1505 * in several places, most importantly whenever the CR3 is loaded.
1506 *
1507 * @returns VBox status code.
1508 * @param pVM The virtual machine.
1509 * @param cr0 Guest context CR0 register
1510 * @param cr3 Guest context CR3 register
1511 * @param cr4 Guest context CR4 register
1512 * @param fGlobal Including global page directories or not
1513 */
1514VMMDECL(int) PGMSyncCR3(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
1515{
1516 /*
1517 * We might be called when we shouldn't.
1518 *
1519 * The mode switching will ensure that the PD is resynced
1520 * after every mode switch. So, if we find ourselves here
1521 * when in protected or real mode we can safely disable the
1522 * FF and return immediately.
1523 */
1524 if (pVM->pgm.s.enmGuestMode <= PGMMODE_PROTECTED)
1525 {
1526 Assert((cr0 & (X86_CR0_PG | X86_CR0_PE)) != (X86_CR0_PG | X86_CR0_PE));
1527 VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3);
1528 VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
1529 return VINF_SUCCESS;
1530 }
1531
1532 /* If global pages are not supported, then all flushes are global */
1533 if (!(cr4 & X86_CR4_PGE))
1534 fGlobal = true;
1535 LogFlow(("PGMSyncCR3: cr0=%VX64 cr3=%VX64 cr4=%VX64 fGlobal=%d[%d,%d]\n", cr0, cr3, cr4, fGlobal,
1536 VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3), VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL)));
1537
1538 /*
1539 * Let the 'Bth' function do the work and we'll just keep track of the flags.
1540 */
1541 STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat,SyncCR3), a);
1542 int rc = PGM_BTH_PFN(SyncCR3, pVM)(pVM, cr0, cr3, cr4, fGlobal);
1543 STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncCR3), a);
1544 AssertMsg(rc == VINF_SUCCESS || rc == VINF_PGM_SYNC_CR3 || VBOX_FAILURE(rc), ("rc=%VRc\n", rc));
1545 if (rc == VINF_SUCCESS)
1546 {
1547 if (!(pVM->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS))
1548 {
1549 VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3);
1550 VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
1551 }
1552
1553 /*
1554 * Check if we have a pending update of the CR3 monitoring.
1555 */
1556 if (pVM->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
1557 {
1558 pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
1559 Assert(!pVM->pgm.s.fMappingsFixed);
1560 Assert(pVM->pgm.s.GCPhysCR3 == pVM->pgm.s.GCPhysGstCR3Monitored);
1561 rc = PGM_GST_PFN(MonitorCR3, pVM)(pVM, pVM->pgm.s.GCPhysCR3);
1562 }
1563 }
1564
1565 /*
1566 * Now flush the CR3 (guest context).
1567 */
1568 if (rc == VINF_SUCCESS)
1569 PGM_INVL_GUEST_TLBS();
1570 return rc;
1571}
1572
1573
1574/**
1575 * Called whenever CR0 or CR4 in a way which may change
1576 * the paging mode.
1577 *
1578 * @returns VBox status code fit for scheduling in GC and R0.
1579 * @retval VINF_SUCCESS if the was no change, or it was successfully dealt with.
1580 * @retval VINF_PGM_CHANGE_MODE if we're in GC or R0 and the mode changes.
1581 * @param pVM VM handle.
1582 * @param cr0 The new cr0.
1583 * @param cr4 The new cr4.
1584 * @param efer The new extended feature enable register.
1585 */
1586VMMDECL(int) PGMChangeMode(PVM pVM, uint64_t cr0, uint64_t cr4, uint64_t efer)
1587{
1588 PGMMODE enmGuestMode;
1589
1590 /*
1591 * Calc the new guest mode.
1592 */
1593 if (!(cr0 & X86_CR0_PE))
1594 enmGuestMode = PGMMODE_REAL;
1595 else if (!(cr0 & X86_CR0_PG))
1596 enmGuestMode = PGMMODE_PROTECTED;
1597 else if (!(cr4 & X86_CR4_PAE))
1598 enmGuestMode = PGMMODE_32_BIT;
1599 else if (!(efer & MSR_K6_EFER_LME))
1600 {
1601 if (!(efer & MSR_K6_EFER_NXE))
1602 enmGuestMode = PGMMODE_PAE;
1603 else
1604 enmGuestMode = PGMMODE_PAE_NX;
1605 }
1606 else
1607 {
1608 if (!(efer & MSR_K6_EFER_NXE))
1609 enmGuestMode = PGMMODE_AMD64;
1610 else
1611 enmGuestMode = PGMMODE_AMD64_NX;
1612 }
1613
1614 /*
1615 * Did it change?
1616 */
1617 if (pVM->pgm.s.enmGuestMode == enmGuestMode)
1618 return VINF_SUCCESS;
1619
1620 /* Flush the TLB */
1621 PGM_INVL_GUEST_TLBS();
1622
1623#ifdef IN_RING3
1624 return PGMR3ChangeMode(pVM, enmGuestMode);
1625#else
1626 Log(("PGMChangeMode: returns VINF_PGM_CHANGE_MODE.\n"));
1627 return VINF_PGM_CHANGE_MODE;
1628#endif
1629}
1630
1631
1632/**
1633 * Gets the current guest paging mode.
1634 *
1635 * If you just need the CPU mode (real/protected/long), use CPUMGetGuestMode().
1636 *
1637 * @returns The current paging mode.
1638 * @param pVM The VM handle.
1639 */
1640VMMDECL(PGMMODE) PGMGetGuestMode(PVM pVM)
1641{
1642 return pVM->pgm.s.enmGuestMode;
1643}
1644
1645
1646/**
1647 * Gets the current shadow paging mode.
1648 *
1649 * @returns The current paging mode.
1650 * @param pVM The VM handle.
1651 */
1652VMMDECL(PGMMODE) PGMGetShadowMode(PVM pVM)
1653{
1654 return pVM->pgm.s.enmShadowMode;
1655}
1656
1657/**
1658 * Gets the current host paging mode.
1659 *
1660 * @returns The current paging mode.
1661 * @param pVM The VM handle.
1662 */
1663VMMDECL(PGMMODE) PGMGetHostMode(PVM pVM)
1664{
1665 switch (pVM->pgm.s.enmHostMode)
1666 {
1667 case SUPPAGINGMODE_32_BIT:
1668 case SUPPAGINGMODE_32_BIT_GLOBAL:
1669 return PGMMODE_32_BIT;
1670
1671 case SUPPAGINGMODE_PAE:
1672 case SUPPAGINGMODE_PAE_GLOBAL:
1673 return PGMMODE_PAE;
1674
1675 case SUPPAGINGMODE_PAE_NX:
1676 case SUPPAGINGMODE_PAE_GLOBAL_NX:
1677 return PGMMODE_PAE_NX;
1678
1679 case SUPPAGINGMODE_AMD64:
1680 case SUPPAGINGMODE_AMD64_GLOBAL:
1681 return PGMMODE_AMD64;
1682
1683 case SUPPAGINGMODE_AMD64_NX:
1684 case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1685 return PGMMODE_AMD64_NX;
1686
1687 default: AssertMsgFailed(("enmHostMode=%d\n", pVM->pgm.s.enmHostMode)); break;
1688 }
1689
1690 return PGMMODE_INVALID;
1691}
1692
1693
1694/**
1695 * Get mode name.
1696 *
1697 * @returns read-only name string.
1698 * @param enmMode The mode which name is desired.
1699 */
1700VMMDECL(const char *) PGMGetModeName(PGMMODE enmMode)
1701{
1702 switch (enmMode)
1703 {
1704 case PGMMODE_REAL: return "Real";
1705 case PGMMODE_PROTECTED: return "Protected";
1706 case PGMMODE_32_BIT: return "32-bit";
1707 case PGMMODE_PAE: return "PAE";
1708 case PGMMODE_PAE_NX: return "PAE+NX";
1709 case PGMMODE_AMD64: return "AMD64";
1710 case PGMMODE_AMD64_NX: return "AMD64+NX";
1711 case PGMMODE_NESTED: return "Nested";
1712 case PGMMODE_EPT: return "EPT";
1713 default: return "unknown mode value";
1714 }
1715}
1716
1717
1718/**
1719 * Acquire the PGM lock.
1720 *
1721 * @returns VBox status code
1722 * @param pVM The VM to operate on.
1723 */
1724int pgmLock(PVM pVM)
1725{
1726 int rc = PDMCritSectEnter(&pVM->pgm.s.CritSect, VERR_SEM_BUSY);
1727#ifdef IN_GC
1728 if (rc == VERR_SEM_BUSY)
1729 rc = VMMGCCallHost(pVM, VMMCALLHOST_PGM_LOCK, 0);
1730#elif defined(IN_RING0)
1731 if (rc == VERR_SEM_BUSY)
1732 rc = VMMR0CallHost(pVM, VMMCALLHOST_PGM_LOCK, 0);
1733#endif
1734 AssertRC(rc);
1735 return rc;
1736}
1737
1738
1739/**
1740 * Release the PGM lock.
1741 *
1742 * @returns VBox status code
1743 * @param pVM The VM to operate on.
1744 */
1745void pgmUnlock(PVM pVM)
1746{
1747 PDMCritSectLeave(&pVM->pgm.s.CritSect);
1748}
1749
1750
1751#ifdef VBOX_STRICT
1752
1753/**
1754 * Asserts that there are no mapping conflicts.
1755 *
1756 * @returns Number of conflicts.
1757 * @param pVM The VM Handle.
1758 */
1759VMMDECL(unsigned) PGMAssertNoMappingConflicts(PVM pVM)
1760{
1761 unsigned cErrors = 0;
1762
1763 /*
1764 * Check for mapping conflicts.
1765 */
1766 for (PPGMMAPPING pMapping = CTXALLSUFF(pVM->pgm.s.pMappings);
1767 pMapping;
1768 pMapping = CTXALLSUFF(pMapping->pNext))
1769 {
1770 /** @todo This is slow and should be optimized, but since it's just assertions I don't care now. */
1771 for (RTGCUINTPTR GCPtr = (RTGCUINTPTR)pMapping->GCPtr;
1772 GCPtr <= (RTGCUINTPTR)pMapping->GCPtrLast;
1773 GCPtr += PAGE_SIZE)
1774 {
1775 int rc = PGMGstGetPage(pVM, (RTGCPTR)GCPtr, NULL, NULL);
1776 if (rc != VERR_PAGE_TABLE_NOT_PRESENT)
1777 {
1778 AssertMsgFailed(("Conflict at %VGv with %s\n", GCPtr, R3STRING(pMapping->pszDesc)));
1779 cErrors++;
1780 break;
1781 }
1782 }
1783 }
1784
1785 return cErrors;
1786}
1787
1788
1789/**
1790 * Asserts that everything related to the guest CR3 is correctly shadowed.
1791 *
1792 * This will call PGMAssertNoMappingConflicts() and PGMAssertHandlerAndFlagsInSync(),
1793 * and assert the correctness of the guest CR3 mapping before asserting that the
1794 * shadow page tables is in sync with the guest page tables.
1795 *
1796 * @returns Number of conflicts.
1797 * @param pVM The VM Handle.
1798 * @param cr3 The current guest CR3 register value.
1799 * @param cr4 The current guest CR4 register value.
1800 */
1801VMMDECL(unsigned) PGMAssertCR3(PVM pVM, uint64_t cr3, uint64_t cr4)
1802{
1803 STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat,SyncCR3), a);
1804 unsigned cErrors = PGM_BTH_PFN(AssertCR3, pVM)(pVM, cr3, cr4, 0, ~(RTGCUINTPTR)0);
1805 STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncCR3), a);
1806 return cErrors;
1807 return 0;
1808}
1809
1810#endif /* VBOX_STRICT */
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette