VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAll.cpp@ 13193

Last change on this file since 13193 was 13188, checked in by vboxsync, 16 years ago

PGM: polish.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id
File size: 63.9 KB
Line 
1/* $Id: PGMAll.cpp 13188 2008-10-11 01:58:30Z vboxsync $ */
2/** @file
3 * PGM - Page Manager and Monitor - All context code.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22/*******************************************************************************
23* Header Files *
24*******************************************************************************/
25#define LOG_GROUP LOG_GROUP_PGM
26#include <VBox/pgm.h>
27#include <VBox/cpum.h>
28#include <VBox/selm.h>
29#include <VBox/iom.h>
30#include <VBox/sup.h>
31#include <VBox/mm.h>
32#include <VBox/stam.h>
33#include <VBox/csam.h>
34#include <VBox/patm.h>
35#include <VBox/trpm.h>
36#include <VBox/rem.h>
37#include <VBox/em.h>
38#include <VBox/hwaccm.h>
39#include <VBox/hwacc_vmx.h>
40#include "PGMInternal.h"
41#include <VBox/vm.h>
42#include <iprt/assert.h>
43#include <iprt/asm.h>
44#include <iprt/string.h>
45#include <VBox/log.h>
46#include <VBox/param.h>
47#include <VBox/err.h>
48
49
50/*******************************************************************************
51* Structures and Typedefs *
52*******************************************************************************/
53/**
54 * Stated structure for PGM_GST_NAME(HandlerVirtualUpdate) that's
55 * passed to PGM_GST_NAME(VirtHandlerUpdateOne) during enumeration.
56 */
57typedef struct PGMHVUSTATE
58{
59 /** The VM handle. */
60 PVM pVM;
61 /** The todo flags. */
62 RTUINT fTodo;
63 /** The CR4 register value. */
64 uint32_t cr4;
65} PGMHVUSTATE, *PPGMHVUSTATE;
66
67
68/*******************************************************************************
69* Internal Functions *
70*******************************************************************************/
71
72/*
73 * Shadow - 32-bit mode
74 */
75#define PGM_SHW_TYPE PGM_TYPE_32BIT
76#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
77#include "PGMAllShw.h"
78
79/* Guest - real mode */
80#define PGM_GST_TYPE PGM_TYPE_REAL
81#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
82#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
83#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
84#include "PGMAllGst.h"
85#include "PGMAllBth.h"
86#undef BTH_PGMPOOLKIND_PT_FOR_PT
87#undef PGM_BTH_NAME
88#undef PGM_GST_TYPE
89#undef PGM_GST_NAME
90
91/* Guest - protected mode */
92#define PGM_GST_TYPE PGM_TYPE_PROT
93#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
94#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
95#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
96#include "PGMAllGst.h"
97#include "PGMAllBth.h"
98#undef BTH_PGMPOOLKIND_PT_FOR_PT
99#undef PGM_BTH_NAME
100#undef PGM_GST_TYPE
101#undef PGM_GST_NAME
102
103/* Guest - 32-bit mode */
104#define PGM_GST_TYPE PGM_TYPE_32BIT
105#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
106#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
107#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
108#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
109#include "PGMAllGst.h"
110#include "PGMAllBth.h"
111#undef BTH_PGMPOOLKIND_PT_FOR_BIG
112#undef BTH_PGMPOOLKIND_PT_FOR_PT
113#undef PGM_BTH_NAME
114#undef PGM_GST_TYPE
115#undef PGM_GST_NAME
116
117#undef PGM_SHW_TYPE
118#undef PGM_SHW_NAME
119
120
121/*
122 * Shadow - PAE mode
123 */
124#define PGM_SHW_TYPE PGM_TYPE_PAE
125#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
126#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
127#include "PGMAllShw.h"
128
129/* Guest - real mode */
130#define PGM_GST_TYPE PGM_TYPE_REAL
131#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
132#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
133#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
134#include "PGMAllBth.h"
135#undef BTH_PGMPOOLKIND_PT_FOR_PT
136#undef PGM_BTH_NAME
137#undef PGM_GST_TYPE
138#undef PGM_GST_NAME
139
140/* Guest - protected mode */
141#define PGM_GST_TYPE PGM_TYPE_PROT
142#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
143#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
144#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
145#include "PGMAllBth.h"
146#undef BTH_PGMPOOLKIND_PT_FOR_PT
147#undef PGM_BTH_NAME
148#undef PGM_GST_TYPE
149#undef PGM_GST_NAME
150
151/* Guest - 32-bit mode */
152#define PGM_GST_TYPE PGM_TYPE_32BIT
153#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
154#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
155#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
156#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
157#include "PGMAllBth.h"
158#undef BTH_PGMPOOLKIND_PT_FOR_BIG
159#undef BTH_PGMPOOLKIND_PT_FOR_PT
160#undef PGM_BTH_NAME
161#undef PGM_GST_TYPE
162#undef PGM_GST_NAME
163
164
165/* Guest - PAE mode */
166#define PGM_GST_TYPE PGM_TYPE_PAE
167#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
168#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
169#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
170#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
171#include "PGMAllGst.h"
172#include "PGMAllBth.h"
173#undef BTH_PGMPOOLKIND_PT_FOR_BIG
174#undef BTH_PGMPOOLKIND_PT_FOR_PT
175#undef PGM_BTH_NAME
176#undef PGM_GST_TYPE
177#undef PGM_GST_NAME
178
179#undef PGM_SHW_TYPE
180#undef PGM_SHW_NAME
181
182
183#ifndef IN_GC /* AMD64 implies VT-x/AMD-V */
184/*
185 * Shadow - AMD64 mode
186 */
187# define PGM_SHW_TYPE PGM_TYPE_AMD64
188# define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
189# include "PGMAllShw.h"
190
191/* Guest - protected mode */
192# define PGM_GST_TYPE PGM_TYPE_PROT
193# define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
194# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_PROT(name)
195# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
196# include "PGMAllBth.h"
197# undef BTH_PGMPOOLKIND_PT_FOR_PT
198# undef PGM_BTH_NAME
199# undef PGM_GST_TYPE
200# undef PGM_GST_NAME
201
202# ifdef VBOX_WITH_64_BITS_GUESTS
203/* Guest - AMD64 mode */
204# define PGM_GST_TYPE PGM_TYPE_AMD64
205# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
206# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
207# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
208# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
209# include "PGMAllGst.h"
210# include "PGMAllBth.h"
211# undef BTH_PGMPOOLKIND_PT_FOR_BIG
212# undef BTH_PGMPOOLKIND_PT_FOR_PT
213# undef PGM_BTH_NAME
214# undef PGM_GST_TYPE
215# undef PGM_GST_NAME
216# endif /* VBOX_WITH_64_BITS_GUESTS */
217
218# undef PGM_SHW_TYPE
219# undef PGM_SHW_NAME
220
221
222/*
223 * Shadow - Nested paging mode
224 */
225# define PGM_SHW_TYPE PGM_TYPE_NESTED
226# define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED(name)
227# include "PGMAllShw.h"
228
229/* Guest - real mode */
230# define PGM_GST_TYPE PGM_TYPE_REAL
231# define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
232# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_REAL(name)
233# include "PGMAllBth.h"
234# undef PGM_BTH_NAME
235# undef PGM_GST_TYPE
236# undef PGM_GST_NAME
237
238/* Guest - protected mode */
239# define PGM_GST_TYPE PGM_TYPE_PROT
240# define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
241# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PROT(name)
242# include "PGMAllBth.h"
243# undef PGM_BTH_NAME
244# undef PGM_GST_TYPE
245# undef PGM_GST_NAME
246
247/* Guest - 32-bit mode */
248# define PGM_GST_TYPE PGM_TYPE_32BIT
249# define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
250# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT(name)
251# include "PGMAllBth.h"
252# undef PGM_BTH_NAME
253# undef PGM_GST_TYPE
254# undef PGM_GST_NAME
255
256/* Guest - PAE mode */
257# define PGM_GST_TYPE PGM_TYPE_PAE
258# define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
259# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE(name)
260# include "PGMAllBth.h"
261# undef PGM_BTH_NAME
262# undef PGM_GST_TYPE
263# undef PGM_GST_NAME
264
265# ifdef VBOX_WITH_64_BITS_GUESTS
266/* Guest - AMD64 mode */
267# define PGM_GST_TYPE PGM_TYPE_AMD64
268# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
269# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64(name)
270# include "PGMAllBth.h"
271# undef PGM_BTH_NAME
272# undef PGM_GST_TYPE
273# undef PGM_GST_NAME
274# endif /* VBOX_WITH_64_BITS_GUESTS */
275
276# undef PGM_SHW_TYPE
277# undef PGM_SHW_NAME
278
279
280/*
281 * Shadow - EPT
282 */
283# define PGM_SHW_TYPE PGM_TYPE_EPT
284# define PGM_SHW_NAME(name) PGM_SHW_NAME_EPT(name)
285# include "PGMAllShw.h"
286
287/* Guest - real mode */
288# define PGM_GST_TYPE PGM_TYPE_REAL
289# define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
290# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_REAL(name)
291# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
292# include "PGMAllBth.h"
293# undef BTH_PGMPOOLKIND_PT_FOR_PT
294# undef PGM_BTH_NAME
295# undef PGM_GST_TYPE
296# undef PGM_GST_NAME
297
298/* Guest - protected mode */
299# define PGM_GST_TYPE PGM_TYPE_PROT
300# define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
301# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PROT(name)
302# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
303# include "PGMAllBth.h"
304# undef BTH_PGMPOOLKIND_PT_FOR_PT
305# undef PGM_BTH_NAME
306# undef PGM_GST_TYPE
307# undef PGM_GST_NAME
308
309/* Guest - 32-bit mode */
310# define PGM_GST_TYPE PGM_TYPE_32BIT
311# define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
312# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_32BIT(name)
313# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
314# include "PGMAllBth.h"
315# undef BTH_PGMPOOLKIND_PT_FOR_PT
316# undef PGM_BTH_NAME
317# undef PGM_GST_TYPE
318# undef PGM_GST_NAME
319
320/* Guest - PAE mode */
321# define PGM_GST_TYPE PGM_TYPE_PAE
322# define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
323# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PAE(name)
324# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
325# include "PGMAllBth.h"
326# undef BTH_PGMPOOLKIND_PT_FOR_PT
327# undef PGM_BTH_NAME
328# undef PGM_GST_TYPE
329# undef PGM_GST_NAME
330
331# ifdef VBOX_WITH_64_BITS_GUESTS
332/* Guest - AMD64 mode */
333# define PGM_GST_TYPE PGM_TYPE_AMD64
334# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
335# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_AMD64(name)
336# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
337# include "PGMAllBth.h"
338# undef BTH_PGMPOOLKIND_PT_FOR_PT
339# undef PGM_BTH_NAME
340# undef PGM_GST_TYPE
341# undef PGM_GST_NAME
342# endif /* VBOX_WITH_64_BITS_GUESTS */
343
344# undef PGM_SHW_TYPE
345# undef PGM_SHW_NAME
346
347#endif /* !IN_GC */
348
349
350#ifndef IN_RING3
351/**
352 * #PF Handler.
353 *
354 * @returns VBox status code (appropriate for trap handling and GC return).
355 * @param pVM VM Handle.
356 * @param uErr The trap error code.
357 * @param pRegFrame Trap register frame.
358 * @param pvFault The fault address.
359 */
360VMMDECL(int) PGMTrap0eHandler(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
361{
362 LogFlow(("PGMTrap0eHandler: uErr=%RGu pvFault=%VGv eip=%VGv\n", uErr, pvFault, pRegFrame->rip));
363 STAM_PROFILE_START(&pVM->pgm.s.StatRZTrap0e, a);
364 STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = NULL; } );
365
366
367#ifdef VBOX_WITH_STATISTICS
368 /*
369 * Error code stats.
370 */
371 if (uErr & X86_TRAP_PF_US)
372 {
373 if (!(uErr & X86_TRAP_PF_P))
374 {
375 if (uErr & X86_TRAP_PF_RW)
376 STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eUSNotPresentWrite);
377 else
378 STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eUSNotPresentRead);
379 }
380 else if (uErr & X86_TRAP_PF_RW)
381 STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eUSWrite);
382 else if (uErr & X86_TRAP_PF_RSVD)
383 STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eUSReserved);
384 else if (uErr & X86_TRAP_PF_ID)
385 STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eUSNXE);
386 else
387 STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eUSRead);
388 }
389 else
390 { /* Supervisor */
391 if (!(uErr & X86_TRAP_PF_P))
392 {
393 if (uErr & X86_TRAP_PF_RW)
394 STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eSVNotPresentWrite);
395 else
396 STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eSVNotPresentRead);
397 }
398 else if (uErr & X86_TRAP_PF_RW)
399 STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eSVWrite);
400 else if (uErr & X86_TRAP_PF_ID)
401 STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eSNXE);
402 else if (uErr & X86_TRAP_PF_RSVD)
403 STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eSVReserved);
404 }
405#endif
406
407 /*
408 * Call the worker.
409 */
410 int rc = PGM_BTH_PFN(Trap0eHandler, pVM)(pVM, uErr, pRegFrame, pvFault);
411 if (rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
412 rc = VINF_SUCCESS;
413 STAM_STATS({ if (rc == VINF_EM_RAW_GUEST_TRAP) STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eGuestPF); });
414 STAM_STATS({ if (!pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution))
415 pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2Misc; });
416 STAM_PROFILE_STOP_EX(&pVM->pgm.s.StatRZTrap0e, pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution), a);
417 return rc;
418}
419#endif /* !IN_RING3 */
420
421
422/**
423 * Prefetch a page
424 *
425 * Typically used to sync commonly used pages before entering raw mode
426 * after a CR3 reload.
427 *
428 * @returns VBox status code suitable for scheduling.
429 * @retval VINF_SUCCESS on success.
430 * @retval VINF_PGM_SYNC_CR3 if we're out of shadow pages or something like that.
431 * @param pVM VM handle.
432 * @param GCPtrPage Page to invalidate.
433 */
434VMMDECL(int) PGMPrefetchPage(PVM pVM, RTGCPTR GCPtrPage)
435{
436 STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,Prefetch), a);
437 int rc = PGM_BTH_PFN(PrefetchPage, pVM)(pVM, (RTGCUINTPTR)GCPtrPage);
438 STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,Prefetch), a);
439 AssertMsg(rc == VINF_SUCCESS || rc == VINF_PGM_SYNC_CR3 || VBOX_FAILURE(rc), ("rc=%Vrc\n", rc));
440 return rc;
441}
442
443
444/**
445 * Gets the mapping corresponding to the specified address (if any).
446 *
447 * @returns Pointer to the mapping.
448 * @returns NULL if not
449 *
450 * @param pVM The virtual machine.
451 * @param GCPtr The guest context pointer.
452 */
453PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr)
454{
455 PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
456 while (pMapping)
457 {
458 if ((uintptr_t)GCPtr < (uintptr_t)pMapping->GCPtr)
459 break;
460 if ((uintptr_t)GCPtr - (uintptr_t)pMapping->GCPtr < pMapping->cb)
461 return pMapping;
462 pMapping = pMapping->CTX_SUFF(pNext);
463 }
464 return NULL;
465}
466
467
468/**
469 * Verifies a range of pages for read or write access
470 *
471 * Only checks the guest's page tables
472 *
473 * @returns VBox status code.
474 * @param pVM VM handle.
475 * @param Addr Guest virtual address to check
476 * @param cbSize Access size
477 * @param fAccess Access type (r/w, user/supervisor (X86_PTE_*))
478 */
479VMMDECL(int) PGMIsValidAccess(PVM pVM, RTGCUINTPTR Addr, uint32_t cbSize, uint32_t fAccess)
480{
481 /*
482 * Validate input.
483 */
484 if (fAccess & ~(X86_PTE_US | X86_PTE_RW))
485 {
486 AssertMsgFailed(("PGMIsValidAccess: invalid access type %08x\n", fAccess));
487 return VERR_INVALID_PARAMETER;
488 }
489
490 uint64_t fPage;
491 int rc = PGMGstGetPage(pVM, (RTGCPTR)Addr, &fPage, NULL);
492 if (VBOX_FAILURE(rc))
493 {
494 Log(("PGMIsValidAccess: access violation for %VGv rc=%d\n", Addr, rc));
495 return VINF_EM_RAW_GUEST_TRAP;
496 }
497
498 /*
499 * Check if the access would cause a page fault
500 *
501 * Note that hypervisor page directories are not present in the guest's tables, so this check
502 * is sufficient.
503 */
504 bool fWrite = !!(fAccess & X86_PTE_RW);
505 bool fUser = !!(fAccess & X86_PTE_US);
506 if ( !(fPage & X86_PTE_P)
507 || (fWrite && !(fPage & X86_PTE_RW))
508 || (fUser && !(fPage & X86_PTE_US)) )
509 {
510 Log(("PGMIsValidAccess: access violation for %VGv attr %#llx vs %d:%d\n", Addr, fPage, fWrite, fUser));
511 return VINF_EM_RAW_GUEST_TRAP;
512 }
513 if ( VBOX_SUCCESS(rc)
514 && PAGE_ADDRESS(Addr) != PAGE_ADDRESS(Addr + cbSize))
515 return PGMIsValidAccess(pVM, Addr + PAGE_SIZE, (cbSize > PAGE_SIZE) ? cbSize - PAGE_SIZE : 1, fAccess);
516 return rc;
517}
518
519
520/**
521 * Verifies a range of pages for read or write access
522 *
523 * Supports handling of pages marked for dirty bit tracking and CSAM
524 *
525 * @returns VBox status code.
526 * @param pVM VM handle.
527 * @param Addr Guest virtual address to check
528 * @param cbSize Access size
529 * @param fAccess Access type (r/w, user/supervisor (X86_PTE_*))
530 */
531VMMDECL(int) PGMVerifyAccess(PVM pVM, RTGCUINTPTR Addr, uint32_t cbSize, uint32_t fAccess)
532{
533 /*
534 * Validate input.
535 */
536 if (fAccess & ~(X86_PTE_US | X86_PTE_RW))
537 {
538 AssertMsgFailed(("PGMVerifyAccess: invalid access type %08x\n", fAccess));
539 return VERR_INVALID_PARAMETER;
540 }
541
542 uint64_t fPageGst;
543 int rc = PGMGstGetPage(pVM, (RTGCPTR)Addr, &fPageGst, NULL);
544 if (VBOX_FAILURE(rc))
545 {
546 Log(("PGMVerifyAccess: access violation for %VGv rc=%d\n", Addr, rc));
547 return VINF_EM_RAW_GUEST_TRAP;
548 }
549
550 /*
551 * Check if the access would cause a page fault
552 *
553 * Note that hypervisor page directories are not present in the guest's tables, so this check
554 * is sufficient.
555 */
556 const bool fWrite = !!(fAccess & X86_PTE_RW);
557 const bool fUser = !!(fAccess & X86_PTE_US);
558 if ( !(fPageGst & X86_PTE_P)
559 || (fWrite && !(fPageGst & X86_PTE_RW))
560 || (fUser && !(fPageGst & X86_PTE_US)) )
561 {
562 Log(("PGMVerifyAccess: access violation for %VGv attr %#llx vs %d:%d\n", Addr, fPageGst, fWrite, fUser));
563 return VINF_EM_RAW_GUEST_TRAP;
564 }
565
566 if (!HWACCMIsNestedPagingActive(pVM))
567 {
568 /*
569 * Next step is to verify if we protected this page for dirty bit tracking or for CSAM scanning
570 */
571 rc = PGMShwGetPage(pVM, (RTGCPTR)Addr, NULL, NULL);
572 if ( rc == VERR_PAGE_NOT_PRESENT
573 || rc == VERR_PAGE_TABLE_NOT_PRESENT)
574 {
575 /*
576 * Page is not present in our page tables.
577 * Try to sync it!
578 */
579 Assert(X86_TRAP_PF_RW == X86_PTE_RW && X86_TRAP_PF_US == X86_PTE_US);
580 uint32_t uErr = fAccess & (X86_TRAP_PF_RW | X86_TRAP_PF_US);
581 rc = PGM_BTH_PFN(VerifyAccessSyncPage, pVM)(pVM, Addr, fPageGst, uErr);
582 if (rc != VINF_SUCCESS)
583 return rc;
584 }
585 else
586 AssertMsg(rc == VINF_SUCCESS, ("PGMShwGetPage %VGv failed with %Vrc\n", Addr, rc));
587 }
588
589#if 0 /* def VBOX_STRICT; triggers too often now */
590 /*
591 * This check is a bit paranoid, but useful.
592 */
593 /** @note this will assert when writing to monitored pages (a bit annoying actually) */
594 uint64_t fPageShw;
595 rc = PGMShwGetPage(pVM, (RTGCPTR)Addr, &fPageShw, NULL);
596 if ( (rc == VERR_PAGE_NOT_PRESENT || VBOX_FAILURE(rc))
597 || (fWrite && !(fPageShw & X86_PTE_RW))
598 || (fUser && !(fPageShw & X86_PTE_US)) )
599 {
600 AssertMsgFailed(("Unexpected access violation for %VGv! rc=%Vrc write=%d user=%d\n",
601 Addr, rc, fWrite && !(fPageShw & X86_PTE_RW), fUser && !(fPageShw & X86_PTE_US)));
602 return VINF_EM_RAW_GUEST_TRAP;
603 }
604#endif
605
606 if ( VBOX_SUCCESS(rc)
607 && ( PAGE_ADDRESS(Addr) != PAGE_ADDRESS(Addr + cbSize - 1)
608 || Addr + cbSize < Addr))
609 {
610 /* Don't recursively call PGMVerifyAccess as we might run out of stack. */
611 for (;;)
612 {
613 Addr += PAGE_SIZE;
614 if (cbSize > PAGE_SIZE)
615 cbSize -= PAGE_SIZE;
616 else
617 cbSize = 1;
618 rc = PGMVerifyAccess(pVM, Addr, 1, fAccess);
619 if (rc != VINF_SUCCESS)
620 break;
621 if (PAGE_ADDRESS(Addr) == PAGE_ADDRESS(Addr + cbSize - 1))
622 break;
623 }
624 }
625 return rc;
626}
627
628
629#ifndef IN_GC
630/**
631 * Emulation of the invlpg instruction (HC only actually).
632 *
633 * @returns VBox status code.
634 * @param pVM VM handle.
635 * @param GCPtrPage Page to invalidate.
636 * @remark ASSUMES the page table entry or page directory is
637 * valid. Fairly safe, but there could be edge cases!
638 * @todo Flush page or page directory only if necessary!
639 */
640VMMDECL(int) PGMInvalidatePage(PVM pVM, RTGCPTR GCPtrPage)
641{
642 int rc;
643
644 Log3(("PGMInvalidatePage: GCPtrPage=%VGv\n", GCPtrPage));
645
646 /** @todo merge PGMGCInvalidatePage with this one */
647
648# ifndef IN_RING3
649 /*
650 * Notify the recompiler so it can record this instruction.
651 * Failure happens when it's out of space. We'll return to HC in that case.
652 */
653 rc = REMNotifyInvalidatePage(pVM, GCPtrPage);
654 if (VBOX_FAILURE(rc))
655 return rc;
656# endif
657
658 STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePage), a);
659 rc = PGM_BTH_PFN(InvalidatePage, pVM)(pVM, GCPtrPage);
660 STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePage), a);
661
662# ifndef IN_RING0
663 /*
664 * Check if we have a pending update of the CR3 monitoring.
665 */
666 if ( VBOX_SUCCESS(rc)
667 && (pVM->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3))
668 {
669 pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
670 Assert(!pVM->pgm.s.fMappingsFixed);
671 Assert(pVM->pgm.s.GCPhysCR3 == pVM->pgm.s.GCPhysGstCR3Monitored);
672 rc = PGM_GST_PFN(MonitorCR3, pVM)(pVM, pVM->pgm.s.GCPhysCR3);
673 }
674# endif
675
676# ifdef IN_RING3
677 /*
678 * Inform CSAM about the flush
679 */
680 /** @note this is to check if monitored pages have been changed; when we implement callbacks for virtual handlers, this is no longer required. */
681 CSAMR3FlushPage(pVM, GCPtrPage);
682# endif
683 return rc;
684}
685#endif /* !IN_GC */
686
687
688/**
689 * Executes an instruction using the interpreter.
690 *
691 * @returns VBox status code (appropriate for trap handling and GC return).
692 * @param pVM VM handle.
693 * @param pRegFrame Register frame.
694 * @param pvFault Fault address.
695 */
696VMMDECL(int) PGMInterpretInstruction(PVM pVM, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
697{
698 uint32_t cb;
699 int rc = EMInterpretInstruction(pVM, pRegFrame, pvFault, &cb);
700 if (rc == VERR_EM_INTERPRETER)
701 rc = VINF_EM_RAW_EMULATE_INSTR;
702 if (rc != VINF_SUCCESS)
703 Log(("PGMInterpretInstruction: returns %Rrc (pvFault=%VGv)\n", rc, pvFault));
704 return rc;
705}
706
707
708/**
709 * Gets effective page information (from the VMM page directory).
710 *
711 * @returns VBox status.
712 * @param pVM VM Handle.
713 * @param GCPtr Guest Context virtual address of the page.
714 * @param pfFlags Where to store the flags. These are X86_PTE_*.
715 * @param pHCPhys Where to store the HC physical address of the page.
716 * This is page aligned.
717 * @remark You should use PGMMapGetPage() for pages in a mapping.
718 */
719VMMDECL(int) PGMShwGetPage(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys)
720{
721 return PGM_SHW_PFN(GetPage,pVM)(pVM, (RTGCUINTPTR)GCPtr, pfFlags, pHCPhys);
722}
723
724
725/**
726 * Sets (replaces) the page flags for a range of pages in the shadow context.
727 *
728 * @returns VBox status.
729 * @param pVM VM handle.
730 * @param GCPtr The address of the first page.
731 * @param cb The size of the range in bytes.
732 * @param fFlags Page flags X86_PTE_*, excluding the page mask of course.
733 * @remark You must use PGMMapSetPage() for pages in a mapping.
734 */
735VMMDECL(int) PGMShwSetPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags)
736{
737 return PGMShwModifyPage(pVM, GCPtr, cb, fFlags, 0);
738}
739
740
741/**
742 * Modify page flags for a range of pages in the shadow context.
743 *
744 * The existing flags are ANDed with the fMask and ORed with the fFlags.
745 *
746 * @returns VBox status code.
747 * @param pVM VM handle.
748 * @param GCPtr Virtual address of the first page in the range.
749 * @param cb Size (in bytes) of the range to apply the modification to.
750 * @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
751 * @param fMask The AND mask - page flags X86_PTE_*.
752 * Be very CAREFUL when ~'ing constants which could be 32-bit!
753 * @remark You must use PGMMapModifyPage() for pages in a mapping.
754 */
755VMMDECL(int) PGMShwModifyPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
756{
757 /*
758 * Validate input.
759 */
760 if (fFlags & X86_PTE_PAE_PG_MASK)
761 {
762 AssertMsgFailed(("fFlags=%#llx\n", fFlags));
763 return VERR_INVALID_PARAMETER;
764 }
765 if (!cb)
766 {
767 AssertFailed();
768 return VERR_INVALID_PARAMETER;
769 }
770
771 /*
772 * Align the input.
773 */
774 cb += (RTGCUINTPTR)GCPtr & PAGE_OFFSET_MASK;
775 cb = RT_ALIGN_Z(cb, PAGE_SIZE);
776 GCPtr = (RTGCPTR)((RTGCUINTPTR)GCPtr & PAGE_BASE_GC_MASK); /** @todo this ain't necessary, right... */
777
778 /*
779 * Call worker.
780 */
781 return PGM_SHW_PFN(ModifyPage, pVM)(pVM, (RTGCUINTPTR)GCPtr, cb, fFlags, fMask);
782}
783
784
785/**
786 * Syncs the SHADOW page directory pointer for the specified address.
787 *
788 * Allocates backing pages in case the PDPT entry is missing.
789 *
790 * @returns VBox status.
791 * @param pVM VM handle.
792 * @param GCPtr The address.
793 * @param pGstPdpe Guest PDPT entry
794 * @param ppPD Receives address of page directory
795 */
796VMMDECL(int) PGMShwSyncPAEPDPtr(PVM pVM, RTGCUINTPTR GCPtr, PX86PDPE pGstPdpe, PX86PDPAE *ppPD)
797{
798 PPGM pPGM = &pVM->pgm.s;
799 PPGMPOOL pPool = pPGM->CTX_SUFF(pPool);
800 PPGMPOOLPAGE pShwPage;
801 int rc;
802
803 Assert(!HWACCMIsNestedPagingActive(pVM));
804
805 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
806 PX86PDPT pPdpt = pVM->pgm.s.CTXMID(p,PaePDPT);
807 PX86PDPE pPdpe = &pPdpt->a[iPdPt];
808
809 /* Allocate page directory if not present. */
810 if ( !pPdpe->n.u1Present
811 && !(pPdpe->u & X86_PDPE_PG_MASK))
812 {
813 PX86PDPE pPdptGst = &CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt];
814
815 Assert(!(pPdpe->u & X86_PDPE_PG_MASK));
816 /* Create a reference back to the PDPT by using the index in its shadow page. */
817 rc = pgmPoolAlloc(pVM, pPdptGst->u & X86_PDPE_PG_MASK, PGMPOOLKIND_PAE_PD_FOR_PAE_PD, PGMPOOL_IDX_PDPT, iPdPt, &pShwPage);
818 if (rc == VERR_PGM_POOL_FLUSHED)
819 {
820 Assert(pVM->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL);
821 VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
822 return VINF_PGM_SYNC_CR3;
823 }
824 AssertRCReturn(rc, rc);
825 }
826 else
827 {
828 pShwPage = pgmPoolGetPage(pPool, pPdpe->u & X86_PDPE_PG_MASK);
829 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
830 }
831 /* The PD was cached or created; hook it up now. */
832 pPdpe->u |= pShwPage->Core.Key
833 | (pGstPdpe->u & ~(X86_PDPE_PG_MASK | X86_PDPE_AVL_MASK | X86_PDPE_PCD | X86_PDPE_PWT));
834
835 *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
836 return VINF_SUCCESS;
837}
838
839
840/**
841 * Gets the SHADOW page directory pointer for the specified address.
842 *
843 * @returns VBox status.
844 * @param pVM VM handle.
845 * @param GCPtr The address.
846 * @param ppPdpt Receives address of pdpt
847 * @param ppPD Receives address of page directory
848 */
849VMMDECL(int) PGMShwGetPAEPDPtr(PVM pVM, RTGCUINTPTR GCPtr, PX86PDPT *ppPdpt, PX86PDPAE *ppPD)
850{
851 PPGM pPGM = &pVM->pgm.s;
852 PPGMPOOL pPool = pPGM->CTX_SUFF(pPool);
853 PPGMPOOLPAGE pShwPage;
854
855 Assert(!HWACCMIsNestedPagingActive(pVM));
856
857 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
858 PX86PDPT pPdpt = pVM->pgm.s.CTXMID(p,PaePDPT);
859 PX86PDPE pPdpe = &pPdpt->a[iPdPt];
860
861 *ppPdpt = pPdpt;
862 if (!pPdpe->n.u1Present)
863 return VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT;
864
865 pShwPage = pgmPoolGetPage(pPool, pPdpe->u & X86_PDPE_PG_MASK);
866 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
867
868 *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
869 return VINF_SUCCESS;
870}
871
872
873#ifndef IN_GC
874/**
875 * Syncs the SHADOW page directory pointer for the specified address. Allocates
876 * backing pages in case the PDPT or PML4 entry is missing.
877 *
878 * @returns VBox status.
879 * @param pVM VM handle.
880 * @param GCPtr The address.
881 * @param pGstPml4e Guest PML4 entry
882 * @param pGstPdpe Guest PDPT entry
883 * @param ppPD Receives address of page directory
884 */
885VMMDECL(int) PGMShwSyncLongModePDPtr(PVM pVM, RTGCUINTPTR64 GCPtr, PX86PML4E pGstPml4e, PX86PDPE pGstPdpe, PX86PDPAE *ppPD)
886{
887 PPGM pPGM = &pVM->pgm.s;
888 const unsigned iPml4e = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
889 PPGMPOOL pPool = pPGM->CTX_SUFF(pPool);
890 PX86PML4E pPml4e;
891 PPGMPOOLPAGE pShwPage;
892 int rc;
893 bool fNestedPaging = HWACCMIsNestedPagingActive(pVM);
894
895 Assert(pVM->pgm.s.pHCPaePML4);
896
897 /* Allocate page directory pointer table if not present. */
898 pPml4e = &pPGM->pHCPaePML4->a[iPml4e];
899 if ( !pPml4e->n.u1Present
900 && !(pPml4e->u & X86_PML4E_PG_MASK))
901 {
902 Assert(!(pPml4e->u & X86_PML4E_PG_MASK));
903
904 if (!fNestedPaging)
905 {
906 Assert(pVM->pgm.s.pHCShwAmd64CR3);
907 Assert(pPGM->pGstPaePML4HC);
908
909 PX86PML4E pPml4eGst = &pPGM->pGstPaePML4HC->a[iPml4e];
910
911 rc = pgmPoolAlloc(pVM, pPml4eGst->u & X86_PML4E_PG_MASK, PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT, pVM->pgm.s.pHCShwAmd64CR3->idx, iPml4e, &pShwPage);
912 }
913 else
914 rc = pgmPoolAlloc(pVM, GCPtr + RT_BIT_64(63) /* hack: make the address unique */, PGMPOOLKIND_64BIT_PDPT_FOR_PHYS, PGMPOOL_IDX_NESTED_ROOT, iPml4e, &pShwPage);
915
916 if (rc == VERR_PGM_POOL_FLUSHED)
917 {
918 Log(("PGMShwSyncLongModePDPtr: PGM pool flushed (1) -> signal sync cr3\n"));
919 Assert(pVM->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL);
920 VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
921 return VINF_PGM_SYNC_CR3;
922 }
923 AssertRCReturn(rc, rc);
924 }
925 else
926 {
927 pShwPage = pgmPoolGetPage(pPool, pPml4e->u & X86_PML4E_PG_MASK);
928 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
929 }
930 /* The PDPT was cached or created; hook it up now. */
931 pPml4e->u |= pShwPage->Core.Key
932 | (pGstPml4e->u & ~(X86_PML4E_PG_MASK | X86_PML4E_AVL_MASK | X86_PML4E_PCD | X86_PML4E_PWT));
933
934 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
935 PX86PDPT pPdpt = (PX86PDPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
936 PX86PDPE pPdpe = &pPdpt->a[iPdPt];
937
938 /* Allocate page directory if not present. */
939 if ( !pPdpe->n.u1Present
940 && !(pPdpe->u & X86_PDPE_PG_MASK))
941 {
942 if (!fNestedPaging)
943 {
944 Assert(pPGM->pGstPaePML4HC);
945
946 PX86PML4E pPml4eGst = &pPGM->pGstPaePML4HC->a[iPml4e];
947 PX86PDPT pPdptGst;
948 rc = PGM_GCPHYS_2_PTR(pVM, pPml4eGst->u & X86_PML4E_PG_MASK, &pPdptGst);
949 AssertRCReturn(rc, rc);
950
951 Assert(!(pPdpe->u & X86_PDPE_PG_MASK));
952 /* Create a reference back to the PDPT by using the index in its shadow page. */
953 rc = pgmPoolAlloc(pVM, pPdptGst->a[iPdPt].u & X86_PDPE_PG_MASK, PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD, pShwPage->idx, iPdPt, &pShwPage);
954 }
955 else
956 rc = pgmPoolAlloc(pVM, GCPtr + RT_BIT_64(62) /* hack: make the address unique */, PGMPOOLKIND_64BIT_PD_FOR_PHYS, pShwPage->idx, iPdPt, &pShwPage);
957
958 if (rc == VERR_PGM_POOL_FLUSHED)
959 {
960 Log(("PGMShwSyncLongModePDPtr: PGM pool flushed (2) -> signal sync cr3\n"));
961 Assert(pVM->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL);
962 VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
963 return VINF_PGM_SYNC_CR3;
964 }
965 AssertRCReturn(rc, rc);
966 }
967 else
968 {
969 pShwPage = pgmPoolGetPage(pPool, pPdpe->u & X86_PDPE_PG_MASK);
970 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
971 }
972 /* The PD was cached or created; hook it up now. */
973 pPdpe->u |= pShwPage->Core.Key
974 | (pGstPdpe->u & ~(X86_PDPE_PG_MASK | X86_PDPE_AVL_MASK | X86_PDPE_PCD | X86_PDPE_PWT));
975
976 *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
977 return VINF_SUCCESS;
978}
979
980/**
981 * Gets the SHADOW page directory pointer for the specified address.
982 *
983 * @returns VBox status.
984 * @param pVM VM handle.
985 * @param GCPtr The address.
986 * @param ppPdpt Receives address of pdpt
987 * @param ppPD Receives address of page directory
988 */
989VMMDECL(int) PGMShwGetLongModePDPtr(PVM pVM, RTGCUINTPTR64 GCPtr, PX86PDPT *ppPdpt, PX86PDPAE *ppPD)
990{
991 PPGM pPGM = &pVM->pgm.s;
992 const unsigned iPml4e = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
993 PPGMPOOL pPool = pPGM->CTX_SUFF(pPool);
994 PX86PML4E pPml4e;
995 PPGMPOOLPAGE pShwPage;
996
997 AssertReturn(pVM->pgm.s.pHCPaePML4, VERR_INTERNAL_ERROR);
998
999 pPml4e = &pPGM->pHCPaePML4->a[iPml4e];
1000 if (!pPml4e->n.u1Present)
1001 return VERR_PAGE_MAP_LEVEL4_NOT_PRESENT;
1002
1003 pShwPage = pgmPoolGetPage(pPool, pPml4e->u & X86_PML4E_PG_MASK);
1004 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1005
1006 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1007 PX86PDPT pPdpt = (PX86PDPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1008 PX86PDPE pPdpe = &pPdpt->a[iPdPt];
1009
1010 *ppPdpt = pPdpt;
1011 if (!pPdpe->n.u1Present)
1012 return VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT;
1013
1014 pShwPage = pgmPoolGetPage(pPool, pPdpe->u & X86_PDPE_PG_MASK);
1015 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1016
1017 *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1018 return VINF_SUCCESS;
1019}
1020
1021/**
1022 * Syncs the SHADOW EPT page directory pointer for the specified address. Allocates
1023 * backing pages in case the PDPT or PML4 entry is missing.
1024 *
1025 * @returns VBox status.
1026 * @param pVM VM handle.
1027 * @param GCPtr The address.
1028 * @param ppPdpt Receives address of pdpt
1029 * @param ppPD Receives address of page directory
1030 */
1031VMMDECL(int) PGMShwGetEPTPDPtr(PVM pVM, RTGCUINTPTR64 GCPtr, PEPTPDPT *ppPdpt, PEPTPD *ppPD)
1032{
1033 PPGM pPGM = &pVM->pgm.s;
1034 const unsigned iPml4e = (GCPtr >> EPT_PML4_SHIFT) & EPT_PML4_MASK;
1035 PPGMPOOL pPool = pPGM->CTX_SUFF(pPool);
1036 PEPTPML4 pPml4 = (PEPTPML4)pPGM->pHCNestedRoot;
1037 PEPTPML4E pPml4e;
1038 PPGMPOOLPAGE pShwPage;
1039 int rc;
1040
1041 Assert(HWACCMIsNestedPagingActive(pVM));
1042 Assert(pPml4);
1043
1044 /* Allocate page directory pointer table if not present. */
1045 pPml4e = &pPml4->a[iPml4e];
1046 if ( !pPml4e->n.u1Present
1047 && !(pPml4e->u & EPT_PML4E_PG_MASK))
1048 {
1049 Assert(!(pPml4e->u & EPT_PML4E_PG_MASK));
1050
1051 rc = pgmPoolAlloc(pVM, (GCPtr & EPT_PML4E_PG_MASK) + RT_BIT_64(63) /* hack: make the address unique */, PGMPOOLKIND_EPT_PDPT_FOR_PHYS, PGMPOOL_IDX_NESTED_ROOT, iPml4e, &pShwPage);
1052 if (rc == VERR_PGM_POOL_FLUSHED)
1053 {
1054 Log(("PGMShwSyncEPTPDPtr: PGM pool flushed (1) -> signal sync cr3\n"));
1055 Assert(pVM->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL);
1056 VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
1057 return VINF_PGM_SYNC_CR3;
1058 }
1059 AssertRCReturn(rc, rc);
1060 }
1061 else
1062 {
1063 pShwPage = pgmPoolGetPage(pPool, pPml4e->u & EPT_PML4E_PG_MASK);
1064 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1065 }
1066 /* The PDPT was cached or created; hook it up now and fill with the default value. */
1067 pPml4e->u = pShwPage->Core.Key;
1068 pPml4e->n.u1Present = 1;
1069 pPml4e->n.u1Write = 1;
1070 pPml4e->n.u1Execute = 1;
1071
1072 const unsigned iPdPt = (GCPtr >> EPT_PDPT_SHIFT) & EPT_PDPT_MASK;
1073 PEPTPDPT pPdpt = (PEPTPDPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1074 PEPTPDPTE pPdpe = &pPdpt->a[iPdPt];
1075
1076 if (ppPdpt)
1077 *ppPdpt = pPdpt;
1078
1079 /* Allocate page directory if not present. */
1080 if ( !pPdpe->n.u1Present
1081 && !(pPdpe->u & EPT_PDPTE_PG_MASK))
1082 {
1083 rc = pgmPoolAlloc(pVM, (GCPtr & EPT_PDPTE_PG_MASK) + RT_BIT_64(62) /* hack: make the address unique */, PGMPOOLKIND_64BIT_PD_FOR_PHYS, pShwPage->idx, iPdPt, &pShwPage);
1084 if (rc == VERR_PGM_POOL_FLUSHED)
1085 {
1086 Log(("PGMShwSyncEPTPDPtr: PGM pool flushed (2) -> signal sync cr3\n"));
1087 Assert(pVM->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL);
1088 VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
1089 return VINF_PGM_SYNC_CR3;
1090 }
1091 AssertRCReturn(rc, rc);
1092 }
1093 else
1094 {
1095 pShwPage = pgmPoolGetPage(pPool, pPdpe->u & EPT_PDPTE_PG_MASK);
1096 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1097 }
1098 /* The PD was cached or created; hook it up now and fill with the default value. */
1099 pPdpe->u = pShwPage->Core.Key;
1100 pPdpe->n.u1Present = 1;
1101 pPdpe->n.u1Write = 1;
1102 pPdpe->n.u1Execute = 1;
1103
1104 *ppPD = (PEPTPD)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1105 return VINF_SUCCESS;
1106}
1107
1108#endif
1109
1110/**
1111 * Gets effective Guest OS page information.
1112 *
1113 * When GCPtr is in a big page, the function will return as if it was a normal
1114 * 4KB page. If the need for distinguishing between big and normal page becomes
1115 * necessary at a later point, a PGMGstGetPage() will be created for that
1116 * purpose.
1117 *
1118 * @returns VBox status.
1119 * @param pVM VM Handle.
1120 * @param GCPtr Guest Context virtual address of the page.
1121 * @param pfFlags Where to store the flags. These are X86_PTE_*, even for big pages.
1122 * @param pGCPhys Where to store the GC physical address of the page.
1123 * This is page aligned. The fact that the
1124 */
1125VMMDECL(int) PGMGstGetPage(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys)
1126{
1127 return PGM_GST_PFN(GetPage,pVM)(pVM, (RTGCUINTPTR)GCPtr, pfFlags, pGCPhys);
1128}
1129
1130
1131/**
1132 * Checks if the page is present.
1133 *
1134 * @returns true if the page is present.
1135 * @returns false if the page is not present.
1136 * @param pVM The VM handle.
1137 * @param GCPtr Address within the page.
1138 */
1139VMMDECL(bool) PGMGstIsPagePresent(PVM pVM, RTGCPTR GCPtr)
1140{
1141 int rc = PGMGstGetPage(pVM, GCPtr, NULL, NULL);
1142 return VBOX_SUCCESS(rc);
1143}
1144
1145
1146/**
1147 * Sets (replaces) the page flags for a range of pages in the guest's tables.
1148 *
1149 * @returns VBox status.
1150 * @param pVM VM handle.
1151 * @param GCPtr The address of the first page.
1152 * @param cb The size of the range in bytes.
1153 * @param fFlags Page flags X86_PTE_*, excluding the page mask of course.
1154 */
1155VMMDECL(int) PGMGstSetPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags)
1156{
1157 return PGMGstModifyPage(pVM, GCPtr, cb, fFlags, 0);
1158}
1159
1160
1161/**
1162 * Modify page flags for a range of pages in the guest's tables
1163 *
1164 * The existing flags are ANDed with the fMask and ORed with the fFlags.
1165 *
1166 * @returns VBox status code.
1167 * @param pVM VM handle.
1168 * @param GCPtr Virtual address of the first page in the range.
1169 * @param cb Size (in bytes) of the range to apply the modification to.
1170 * @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
1171 * @param fMask The AND mask - page flags X86_PTE_*, excluding the page mask of course.
1172 * Be very CAREFUL when ~'ing constants which could be 32-bit!
1173 */
1174VMMDECL(int) PGMGstModifyPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
1175{
1176 STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,GstModifyPage), a);
1177
1178 /*
1179 * Validate input.
1180 */
1181 if (fFlags & X86_PTE_PAE_PG_MASK)
1182 {
1183 AssertMsgFailed(("fFlags=%#llx\n", fFlags));
1184 STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,GstModifyPage), a);
1185 return VERR_INVALID_PARAMETER;
1186 }
1187
1188 if (!cb)
1189 {
1190 AssertFailed();
1191 STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,GstModifyPage), a);
1192 return VERR_INVALID_PARAMETER;
1193 }
1194
1195 LogFlow(("PGMGstModifyPage %VGv %d bytes fFlags=%08llx fMask=%08llx\n", GCPtr, cb, fFlags, fMask));
1196
1197 /*
1198 * Adjust input.
1199 */
1200 cb += (RTGCUINTPTR)GCPtr & PAGE_OFFSET_MASK;
1201 cb = RT_ALIGN_Z(cb, PAGE_SIZE);
1202 GCPtr = (RTGCPTR)((RTGCUINTPTR)GCPtr & PAGE_BASE_GC_MASK);
1203
1204 /*
1205 * Call worker.
1206 */
1207 int rc = PGM_GST_PFN(ModifyPage, pVM)(pVM, (RTGCUINTPTR)GCPtr, cb, fFlags, fMask);
1208
1209 STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,GstModifyPage), a);
1210 return rc;
1211}
1212
1213
1214/**
1215 * Gets the current CR3 register value for the shadow memory context.
1216 * @returns CR3 value.
1217 * @param pVM The VM handle.
1218 */
1219VMMDECL(RTHCPHYS) PGMGetHyperCR3(PVM pVM)
1220{
1221 PGMMODE enmShadowMode = pVM->pgm.s.enmShadowMode;
1222 switch (enmShadowMode)
1223 {
1224 case PGMMODE_32_BIT:
1225 return pVM->pgm.s.HCPhys32BitPD;
1226
1227 case PGMMODE_PAE:
1228 case PGMMODE_PAE_NX:
1229 return pVM->pgm.s.HCPhysPaePDPT;
1230
1231 case PGMMODE_AMD64:
1232 case PGMMODE_AMD64_NX:
1233 return pVM->pgm.s.HCPhysPaePML4;
1234
1235 case PGMMODE_EPT:
1236 return pVM->pgm.s.HCPhysNestedRoot;
1237
1238 case PGMMODE_NESTED:
1239 return PGMGetNestedCR3(pVM, PGMGetHostMode(pVM));
1240
1241 default:
1242 AssertMsgFailed(("enmShadowMode=%d\n", enmShadowMode));
1243 return ~0;
1244 }
1245}
1246
1247/**
1248 * Gets the current CR3 register value for the nested memory context.
1249 * @returns CR3 value.
1250 * @param pVM The VM handle.
1251 */
1252VMMDECL(RTHCPHYS) PGMGetNestedCR3(PVM pVM, PGMMODE enmShadowMode)
1253{
1254 switch (enmShadowMode)
1255 {
1256 case PGMMODE_32_BIT:
1257 return pVM->pgm.s.HCPhys32BitPD;
1258
1259 case PGMMODE_PAE:
1260 case PGMMODE_PAE_NX:
1261 return pVM->pgm.s.HCPhysPaePDPT;
1262
1263 case PGMMODE_AMD64:
1264 case PGMMODE_AMD64_NX:
1265 return pVM->pgm.s.HCPhysPaePML4;
1266
1267 default:
1268 AssertMsgFailed(("enmShadowMode=%d\n", enmShadowMode));
1269 return ~0;
1270 }
1271}
1272
1273/**
1274 * Gets the current CR3 register value for the EPT paging memory context.
1275 * @returns CR3 value.
1276 * @param pVM The VM handle.
1277 */
1278VMMDECL(RTHCPHYS) PGMGetEPTCR3(PVM pVM)
1279{
1280 return pVM->pgm.s.HCPhysNestedRoot;
1281}
1282
1283/**
1284 * Gets the CR3 register value for the 32-Bit shadow memory context.
1285 * @returns CR3 value.
1286 * @param pVM The VM handle.
1287 */
1288VMMDECL(RTHCPHYS) PGMGetHyper32BitCR3(PVM pVM)
1289{
1290 return pVM->pgm.s.HCPhys32BitPD;
1291}
1292
1293
1294/**
1295 * Gets the CR3 register value for the PAE shadow memory context.
1296 * @returns CR3 value.
1297 * @param pVM The VM handle.
1298 */
1299VMMDECL(RTHCPHYS) PGMGetHyperPaeCR3(PVM pVM)
1300{
1301 return pVM->pgm.s.HCPhysPaePDPT;
1302}
1303
1304
1305/**
1306 * Gets the CR3 register value for the AMD64 shadow memory context.
1307 * @returns CR3 value.
1308 * @param pVM The VM handle.
1309 */
1310VMMDECL(RTHCPHYS) PGMGetHyperAmd64CR3(PVM pVM)
1311{
1312 return pVM->pgm.s.HCPhysPaePML4;
1313}
1314
1315
1316/**
1317 * Gets the current CR3 register value for the HC intermediate memory context.
1318 * @returns CR3 value.
1319 * @param pVM The VM handle.
1320 */
1321VMMDECL(RTHCPHYS) PGMGetInterHCCR3(PVM pVM)
1322{
1323 switch (pVM->pgm.s.enmHostMode)
1324 {
1325 case SUPPAGINGMODE_32_BIT:
1326 case SUPPAGINGMODE_32_BIT_GLOBAL:
1327 return pVM->pgm.s.HCPhysInterPD;
1328
1329 case SUPPAGINGMODE_PAE:
1330 case SUPPAGINGMODE_PAE_GLOBAL:
1331 case SUPPAGINGMODE_PAE_NX:
1332 case SUPPAGINGMODE_PAE_GLOBAL_NX:
1333 return pVM->pgm.s.HCPhysInterPaePDPT;
1334
1335 case SUPPAGINGMODE_AMD64:
1336 case SUPPAGINGMODE_AMD64_GLOBAL:
1337 case SUPPAGINGMODE_AMD64_NX:
1338 case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1339 return pVM->pgm.s.HCPhysInterPaePDPT;
1340
1341 default:
1342 AssertMsgFailed(("enmHostMode=%d\n", pVM->pgm.s.enmHostMode));
1343 return ~0;
1344 }
1345}
1346
1347
1348/**
1349 * Gets the current CR3 register value for the GC intermediate memory context.
1350 * @returns CR3 value.
1351 * @param pVM The VM handle.
1352 */
1353VMMDECL(RTHCPHYS) PGMGetInterGCCR3(PVM pVM)
1354{
1355 switch (pVM->pgm.s.enmShadowMode)
1356 {
1357 case PGMMODE_32_BIT:
1358 return pVM->pgm.s.HCPhysInterPD;
1359
1360 case PGMMODE_PAE:
1361 case PGMMODE_PAE_NX:
1362 return pVM->pgm.s.HCPhysInterPaePDPT;
1363
1364 case PGMMODE_AMD64:
1365 case PGMMODE_AMD64_NX:
1366 return pVM->pgm.s.HCPhysInterPaePML4;
1367
1368 case PGMMODE_EPT:
1369 case PGMMODE_NESTED:
1370 return 0; /* not relevant */
1371
1372 default:
1373 AssertMsgFailed(("enmShadowMode=%d\n", pVM->pgm.s.enmShadowMode));
1374 return ~0;
1375 }
1376}
1377
1378
1379/**
1380 * Gets the CR3 register value for the 32-Bit intermediate memory context.
1381 * @returns CR3 value.
1382 * @param pVM The VM handle.
1383 */
1384VMMDECL(RTHCPHYS) PGMGetInter32BitCR3(PVM pVM)
1385{
1386 return pVM->pgm.s.HCPhysInterPD;
1387}
1388
1389
1390/**
1391 * Gets the CR3 register value for the PAE intermediate memory context.
1392 * @returns CR3 value.
1393 * @param pVM The VM handle.
1394 */
1395VMMDECL(RTHCPHYS) PGMGetInterPaeCR3(PVM pVM)
1396{
1397 return pVM->pgm.s.HCPhysInterPaePDPT;
1398}
1399
1400
1401/**
1402 * Gets the CR3 register value for the AMD64 intermediate memory context.
1403 * @returns CR3 value.
1404 * @param pVM The VM handle.
1405 */
1406VMMDECL(RTHCPHYS) PGMGetInterAmd64CR3(PVM pVM)
1407{
1408 return pVM->pgm.s.HCPhysInterPaePML4;
1409}
1410
1411
1412/**
1413 * Performs and schedules necessary updates following a CR3 load or reload.
1414 *
1415 * This will normally involve mapping the guest PD or nPDPT
1416 *
1417 * @returns VBox status code.
1418 * @retval VINF_PGM_SYNC_CR3 if monitoring requires a CR3 sync. This can
1419 * safely be ignored and overridden since the FF will be set too then.
1420 * @param pVM VM handle.
1421 * @param cr3 The new cr3.
1422 * @param fGlobal Indicates whether this is a global flush or not.
1423 */
1424VMMDECL(int) PGMFlushTLB(PVM pVM, uint64_t cr3, bool fGlobal)
1425{
1426 STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,FlushTLB), a);
1427
1428 /*
1429 * Always flag the necessary updates; necessary for hardware acceleration
1430 */
1431 VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
1432 if (fGlobal)
1433 VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
1434 LogFlow(("PGMFlushTLB: cr3=%VX64 OldCr3=%VX64 fGlobal=%d\n", cr3, pVM->pgm.s.GCPhysCR3, fGlobal));
1435
1436 /*
1437 * Remap the CR3 content and adjust the monitoring if CR3 was actually changed.
1438 */
1439 int rc = VINF_SUCCESS;
1440 RTGCPHYS GCPhysCR3;
1441 if ( pVM->pgm.s.enmGuestMode == PGMMODE_PAE
1442 || pVM->pgm.s.enmGuestMode == PGMMODE_PAE_NX
1443 || pVM->pgm.s.enmGuestMode == PGMMODE_AMD64
1444 || pVM->pgm.s.enmGuestMode == PGMMODE_AMD64_NX)
1445 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAE_PAGE_MASK);
1446 else
1447 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAGE_MASK);
1448 if (pVM->pgm.s.GCPhysCR3 != GCPhysCR3)
1449 {
1450 pVM->pgm.s.GCPhysCR3 = GCPhysCR3;
1451 rc = PGM_GST_PFN(MapCR3, pVM)(pVM, GCPhysCR3);
1452 if (VBOX_SUCCESS(rc) && !pVM->pgm.s.fMappingsFixed)
1453 {
1454 pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
1455 rc = PGM_GST_PFN(MonitorCR3, pVM)(pVM, GCPhysCR3);
1456 }
1457 if (fGlobal)
1458 STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,FlushTLBNewCR3Global));
1459 else
1460 STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,FlushTLBNewCR3));
1461 }
1462 else
1463 {
1464 /*
1465 * Check if we have a pending update of the CR3 monitoring.
1466 */
1467 if (pVM->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
1468 {
1469 pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
1470 Assert(!pVM->pgm.s.fMappingsFixed);
1471 rc = PGM_GST_PFN(MonitorCR3, pVM)(pVM, GCPhysCR3);
1472 }
1473 if (fGlobal)
1474 STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,FlushTLBSameCR3Global));
1475 else
1476 STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,FlushTLBSameCR3));
1477 }
1478
1479 STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,FlushTLB), a);
1480 return rc;
1481}
1482
1483/**
1484 * Performs and schedules necessary updates following a CR3 load or reload,
1485 * without actually flushing the TLB as with PGMFlushTLB.
1486 *
1487 * This will normally involve mapping the guest PD or nPDPT
1488 *
1489 * @returns VBox status code.
1490 * @retval VINF_PGM_SYNC_CR3 if monitoring requires a CR3 sync. This can
1491 * safely be ignored and overridden since the FF will be set too then.
1492 * @param pVM VM handle.
1493 * @param cr3 The new cr3.
1494 */
1495VMMDECL(int) PGMUpdateCR3(PVM pVM, uint64_t cr3)
1496{
1497 LogFlow(("PGMUpdateCR3: cr3=%VX64 OldCr3=%VX64\n", cr3, pVM->pgm.s.GCPhysCR3));
1498
1499 /* We assume we're only called in nested paging mode. */
1500 Assert(pVM->pgm.s.fMappingsFixed);
1501 Assert(!(pVM->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3));
1502 Assert(pVM->pgm.s.enmShadowMode == PGMMODE_NESTED || pVM->pgm.s.enmShadowMode == PGMMODE_EPT);
1503
1504 /*
1505 * Remap the CR3 content and adjust the monitoring if CR3 was actually changed.
1506 */
1507 int rc = VINF_SUCCESS;
1508 RTGCPHYS GCPhysCR3;
1509 if ( pVM->pgm.s.enmGuestMode == PGMMODE_PAE
1510 || pVM->pgm.s.enmGuestMode == PGMMODE_PAE_NX
1511 || pVM->pgm.s.enmGuestMode == PGMMODE_AMD64
1512 || pVM->pgm.s.enmGuestMode == PGMMODE_AMD64_NX)
1513 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAE_PAGE_MASK);
1514 else
1515 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAGE_MASK);
1516 if (pVM->pgm.s.GCPhysCR3 != GCPhysCR3)
1517 {
1518 pVM->pgm.s.GCPhysCR3 = GCPhysCR3;
1519 rc = PGM_GST_PFN(MapCR3, pVM)(pVM, GCPhysCR3);
1520 }
1521 AssertRC(rc);
1522 return rc;
1523}
1524
1525/**
1526 * Synchronize the paging structures.
1527 *
1528 * This function is called in response to the VM_FF_PGM_SYNC_CR3 and
1529 * VM_FF_PGM_SYNC_CR3_NONGLOBAL. Those two force action flags are set
1530 * in several places, most importantly whenever the CR3 is loaded.
1531 *
1532 * @returns VBox status code.
1533 * @param pVM The virtual machine.
1534 * @param cr0 Guest context CR0 register
1535 * @param cr3 Guest context CR3 register
1536 * @param cr4 Guest context CR4 register
1537 * @param fGlobal Including global page directories or not
1538 */
1539VMMDECL(int) PGMSyncCR3(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
1540{
1541 /*
1542 * We might be called when we shouldn't.
1543 *
1544 * The mode switching will ensure that the PD is resynced
1545 * after every mode switch. So, if we find ourselves here
1546 * when in protected or real mode we can safely disable the
1547 * FF and return immediately.
1548 */
1549 if (pVM->pgm.s.enmGuestMode <= PGMMODE_PROTECTED)
1550 {
1551 Assert((cr0 & (X86_CR0_PG | X86_CR0_PE)) != (X86_CR0_PG | X86_CR0_PE));
1552 VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3);
1553 VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
1554 return VINF_SUCCESS;
1555 }
1556
1557 /* If global pages are not supported, then all flushes are global */
1558 if (!(cr4 & X86_CR4_PGE))
1559 fGlobal = true;
1560 LogFlow(("PGMSyncCR3: cr0=%VX64 cr3=%VX64 cr4=%VX64 fGlobal=%d[%d,%d]\n", cr0, cr3, cr4, fGlobal,
1561 VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3), VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL)));
1562
1563 /*
1564 * Let the 'Bth' function do the work and we'll just keep track of the flags.
1565 */
1566 STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3), a);
1567 int rc = PGM_BTH_PFN(SyncCR3, pVM)(pVM, cr0, cr3, cr4, fGlobal);
1568 STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3), a);
1569 AssertMsg(rc == VINF_SUCCESS || rc == VINF_PGM_SYNC_CR3 || VBOX_FAILURE(rc), ("rc=%VRc\n", rc));
1570 if (rc == VINF_SUCCESS)
1571 {
1572 if (!(pVM->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS))
1573 {
1574 VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3);
1575 VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
1576 }
1577
1578 /*
1579 * Check if we have a pending update of the CR3 monitoring.
1580 */
1581 if (pVM->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
1582 {
1583 pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
1584 Assert(!pVM->pgm.s.fMappingsFixed);
1585 Assert(pVM->pgm.s.GCPhysCR3 == pVM->pgm.s.GCPhysGstCR3Monitored);
1586 rc = PGM_GST_PFN(MonitorCR3, pVM)(pVM, pVM->pgm.s.GCPhysCR3);
1587 }
1588 }
1589
1590 /*
1591 * Now flush the CR3 (guest context).
1592 */
1593 if (rc == VINF_SUCCESS)
1594 PGM_INVL_GUEST_TLBS();
1595 return rc;
1596}
1597
1598
1599/**
1600 * Called whenever CR0 or CR4 in a way which may change
1601 * the paging mode.
1602 *
1603 * @returns VBox status code fit for scheduling in GC and R0.
1604 * @retval VINF_SUCCESS if the was no change, or it was successfully dealt with.
1605 * @retval VINF_PGM_CHANGE_MODE if we're in GC or R0 and the mode changes.
1606 * @param pVM VM handle.
1607 * @param cr0 The new cr0.
1608 * @param cr4 The new cr4.
1609 * @param efer The new extended feature enable register.
1610 */
1611VMMDECL(int) PGMChangeMode(PVM pVM, uint64_t cr0, uint64_t cr4, uint64_t efer)
1612{
1613 PGMMODE enmGuestMode;
1614
1615 /*
1616 * Calc the new guest mode.
1617 */
1618 if (!(cr0 & X86_CR0_PE))
1619 enmGuestMode = PGMMODE_REAL;
1620 else if (!(cr0 & X86_CR0_PG))
1621 enmGuestMode = PGMMODE_PROTECTED;
1622 else if (!(cr4 & X86_CR4_PAE))
1623 enmGuestMode = PGMMODE_32_BIT;
1624 else if (!(efer & MSR_K6_EFER_LME))
1625 {
1626 if (!(efer & MSR_K6_EFER_NXE))
1627 enmGuestMode = PGMMODE_PAE;
1628 else
1629 enmGuestMode = PGMMODE_PAE_NX;
1630 }
1631 else
1632 {
1633 if (!(efer & MSR_K6_EFER_NXE))
1634 enmGuestMode = PGMMODE_AMD64;
1635 else
1636 enmGuestMode = PGMMODE_AMD64_NX;
1637 }
1638
1639 /*
1640 * Did it change?
1641 */
1642 if (pVM->pgm.s.enmGuestMode == enmGuestMode)
1643 return VINF_SUCCESS;
1644
1645 /* Flush the TLB */
1646 PGM_INVL_GUEST_TLBS();
1647
1648#ifdef IN_RING3
1649 return PGMR3ChangeMode(pVM, enmGuestMode);
1650#else
1651 Log(("PGMChangeMode: returns VINF_PGM_CHANGE_MODE.\n"));
1652 return VINF_PGM_CHANGE_MODE;
1653#endif
1654}
1655
1656
1657/**
1658 * Gets the current guest paging mode.
1659 *
1660 * If you just need the CPU mode (real/protected/long), use CPUMGetGuestMode().
1661 *
1662 * @returns The current paging mode.
1663 * @param pVM The VM handle.
1664 */
1665VMMDECL(PGMMODE) PGMGetGuestMode(PVM pVM)
1666{
1667 return pVM->pgm.s.enmGuestMode;
1668}
1669
1670
1671/**
1672 * Gets the current shadow paging mode.
1673 *
1674 * @returns The current paging mode.
1675 * @param pVM The VM handle.
1676 */
1677VMMDECL(PGMMODE) PGMGetShadowMode(PVM pVM)
1678{
1679 return pVM->pgm.s.enmShadowMode;
1680}
1681
1682/**
1683 * Gets the current host paging mode.
1684 *
1685 * @returns The current paging mode.
1686 * @param pVM The VM handle.
1687 */
1688VMMDECL(PGMMODE) PGMGetHostMode(PVM pVM)
1689{
1690 switch (pVM->pgm.s.enmHostMode)
1691 {
1692 case SUPPAGINGMODE_32_BIT:
1693 case SUPPAGINGMODE_32_BIT_GLOBAL:
1694 return PGMMODE_32_BIT;
1695
1696 case SUPPAGINGMODE_PAE:
1697 case SUPPAGINGMODE_PAE_GLOBAL:
1698 return PGMMODE_PAE;
1699
1700 case SUPPAGINGMODE_PAE_NX:
1701 case SUPPAGINGMODE_PAE_GLOBAL_NX:
1702 return PGMMODE_PAE_NX;
1703
1704 case SUPPAGINGMODE_AMD64:
1705 case SUPPAGINGMODE_AMD64_GLOBAL:
1706 return PGMMODE_AMD64;
1707
1708 case SUPPAGINGMODE_AMD64_NX:
1709 case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1710 return PGMMODE_AMD64_NX;
1711
1712 default: AssertMsgFailed(("enmHostMode=%d\n", pVM->pgm.s.enmHostMode)); break;
1713 }
1714
1715 return PGMMODE_INVALID;
1716}
1717
1718
1719/**
1720 * Get mode name.
1721 *
1722 * @returns read-only name string.
1723 * @param enmMode The mode which name is desired.
1724 */
1725VMMDECL(const char *) PGMGetModeName(PGMMODE enmMode)
1726{
1727 switch (enmMode)
1728 {
1729 case PGMMODE_REAL: return "Real";
1730 case PGMMODE_PROTECTED: return "Protected";
1731 case PGMMODE_32_BIT: return "32-bit";
1732 case PGMMODE_PAE: return "PAE";
1733 case PGMMODE_PAE_NX: return "PAE+NX";
1734 case PGMMODE_AMD64: return "AMD64";
1735 case PGMMODE_AMD64_NX: return "AMD64+NX";
1736 case PGMMODE_NESTED: return "Nested";
1737 case PGMMODE_EPT: return "EPT";
1738 default: return "unknown mode value";
1739 }
1740}
1741
1742
1743/**
1744 * Acquire the PGM lock.
1745 *
1746 * @returns VBox status code
1747 * @param pVM The VM to operate on.
1748 */
1749int pgmLock(PVM pVM)
1750{
1751 int rc = PDMCritSectEnter(&pVM->pgm.s.CritSect, VERR_SEM_BUSY);
1752#ifdef IN_GC
1753 if (rc == VERR_SEM_BUSY)
1754 rc = VMMGCCallHost(pVM, VMMCALLHOST_PGM_LOCK, 0);
1755#elif defined(IN_RING0)
1756 if (rc == VERR_SEM_BUSY)
1757 rc = VMMR0CallHost(pVM, VMMCALLHOST_PGM_LOCK, 0);
1758#endif
1759 AssertRC(rc);
1760 return rc;
1761}
1762
1763
1764/**
1765 * Release the PGM lock.
1766 *
1767 * @returns VBox status code
1768 * @param pVM The VM to operate on.
1769 */
1770void pgmUnlock(PVM pVM)
1771{
1772 PDMCritSectLeave(&pVM->pgm.s.CritSect);
1773}
1774
1775#if defined(IN_GC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1776
1777/**
1778 * Temporarily maps one guest page specified by GC physical address.
1779 * These pages must have a physical mapping in HC, i.e. they cannot be MMIO pages.
1780 *
1781 * Be WARNED that the dynamic page mapping area is small, 8 pages, thus the space is
1782 * reused after 8 mappings (or perhaps a few more if you score with the cache).
1783 *
1784 * @returns VBox status.
1785 * @param pVM VM handle.
1786 * @param GCPhys GC Physical address of the page.
1787 * @param ppv Where to store the address of the mapping.
1788 */
1789VMMDECL(int) PGMDynMapGCPage(PVM pVM, RTGCPHYS GCPhys, void **ppv)
1790{
1791 AssertMsg(!(GCPhys & PAGE_OFFSET_MASK), ("GCPhys=%RGp\n", GCPhys));
1792
1793 /*
1794 * Get the ram range.
1795 */
1796 PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
1797 while (pRam && GCPhys - pRam->GCPhys >= pRam->cb)
1798 pRam = pRam->CTX_SUFF(pNext);
1799 if (!pRam)
1800 {
1801 AssertMsgFailed(("Invalid physical address %RGp!\n", GCPhys));
1802 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
1803 }
1804
1805 /*
1806 * Pass it on to PGMDynMapHCPage.
1807 */
1808 RTHCPHYS HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT]);
1809 //Log(("PGMDynMapGCPage: GCPhys=%VGp HCPhys=%VHp\n", GCPhys, HCPhys));
1810 return PGMDynMapHCPage(pVM, HCPhys, ppv);
1811}
1812
1813
1814/**
1815 * Temporarily maps one guest page specified by unaligned GC physical address.
1816 * These pages must have a physical mapping in HC, i.e. they cannot be MMIO pages.
1817 *
1818 * Be WARNED that the dynamic page mapping area is small, 8 pages, thus the space is
1819 * reused after 8 mappings (or perhaps a few more if you score with the cache).
1820 *
1821 * The caller is aware that only the speicifed page is mapped and that really bad things
1822 * will happen if writing beyond the page!
1823 *
1824 * @returns VBox status.
1825 * @param pVM VM handle.
1826 * @param GCPhys GC Physical address within the page to be mapped.
1827 * @param ppv Where to store the address of the mapping address corresponding to GCPhys.
1828 */
1829VMMDECL(int) PGMDynMapGCPageOff(PVM pVM, RTGCPHYS GCPhys, void **ppv)
1830{
1831 /*
1832 * Get the ram range.
1833 */
1834 PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
1835 while (pRam && GCPhys - pRam->GCPhys >= pRam->cb)
1836 pRam = pRam->CTX_SUFF(pNext);
1837 if (!pRam)
1838 {
1839 AssertMsgFailed(("Invalid physical address %VGp!\n", GCPhys));
1840 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
1841 }
1842
1843 /*
1844 * Pass it on to PGMDynMapHCPage.
1845 */
1846 RTHCPHYS HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT]);
1847 int rc = PGMDynMapHCPage(pVM, HCPhys, ppv);
1848 if (RT_SUCCESS(rc))
1849 *ppv = (void *)((uintptr_t)*ppv | (GCPhys & PAGE_OFFSET_MASK));
1850 return rc;
1851}
1852
1853
1854/**
1855 * Temporarily maps one host page specified by HC physical address.
1856 *
1857 * Be WARNED that the dynamic page mapping area is small, 8 pages, thus the space is
1858 * reused after 8 mappings (or perhaps a few more if you score with the cache).
1859 *
1860 * @returns VBox status.
1861 * @param pVM VM handle.
1862 * @param HCPhys HC Physical address of the page.
1863 * @param ppv Where to store the address of the mapping. This is the
1864 * address of the PAGE not the exact address corresponding
1865 * to HCPhys. Use PGMDynMapHCPageOff if you care for the
1866 * page offset.
1867 */
1868VMMDECL(int) PGMDynMapHCPage(PVM pVM, RTHCPHYS HCPhys, void **ppv)
1869{
1870 AssertMsg(!(HCPhys & PAGE_OFFSET_MASK), ("HCPhys=%RHp\n", HCPhys));
1871# ifdef IN_GC
1872
1873 /*
1874 * Check the cache.
1875 */
1876 register unsigned iCache;
1877 if ( pVM->pgm.s.aHCPhysDynPageMapCache[iCache = 0] == HCPhys
1878 || pVM->pgm.s.aHCPhysDynPageMapCache[iCache = 1] == HCPhys
1879 || pVM->pgm.s.aHCPhysDynPageMapCache[iCache = 2] == HCPhys
1880 || pVM->pgm.s.aHCPhysDynPageMapCache[iCache = 3] == HCPhys)
1881 {
1882 static const uint8_t au8Trans[MM_HYPER_DYNAMIC_SIZE >> PAGE_SHIFT][RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache)] =
1883 {
1884 { 0, 5, 6, 7 },
1885 { 0, 1, 6, 7 },
1886 { 0, 1, 2, 7 },
1887 { 0, 1, 2, 3 },
1888 { 4, 1, 2, 3 },
1889 { 4, 5, 2, 3 },
1890 { 4, 5, 6, 3 },
1891 { 4, 5, 6, 7 },
1892 };
1893 Assert(RT_ELEMENTS(au8Trans) == 8);
1894 Assert(RT_ELEMENTS(au8Trans[0]) == 4);
1895 int iPage = au8Trans[pVM->pgm.s.iDynPageMapLast][iCache];
1896 void *pv = pVM->pgm.s.pbDynPageMapBaseGC + (iPage << PAGE_SHIFT);
1897 *ppv = pv;
1898 STAM_COUNTER_INC(&pVM->pgm.s.StatRCDynMapCacheHits);
1899 //Log(("PGMGCDynMapHCPage: HCPhys=%VHp pv=%VGv iPage=%d iCache=%d\n", HCPhys, pv, iPage, iCache));
1900 return VINF_SUCCESS;
1901 }
1902 Assert(RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache) == 4);
1903 STAM_COUNTER_INC(&pVM->pgm.s.StatRCDynMapCacheMisses);
1904
1905 /*
1906 * Update the page tables.
1907 */
1908 register unsigned iPage = pVM->pgm.s.iDynPageMapLast;
1909 pVM->pgm.s.iDynPageMapLast = iPage = (iPage + 1) & ((MM_HYPER_DYNAMIC_SIZE >> PAGE_SHIFT) - 1);
1910 Assert((MM_HYPER_DYNAMIC_SIZE >> PAGE_SHIFT) == 8);
1911
1912 pVM->pgm.s.aHCPhysDynPageMapCache[iPage & (RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache) - 1)] = HCPhys;
1913 pVM->pgm.s.paDynPageMap32BitPTEsGC[iPage].u = (uint32_t)HCPhys | X86_PTE_P | X86_PTE_A | X86_PTE_D;
1914 pVM->pgm.s.paDynPageMapPaePTEsGC[iPage].u = HCPhys | X86_PTE_P | X86_PTE_A | X86_PTE_D;
1915
1916 void *pv = pVM->pgm.s.pbDynPageMapBaseGC + (iPage << PAGE_SHIFT);
1917 *ppv = pv;
1918 ASMInvalidatePage(pv);
1919 Log4(("PGMGCDynMapHCPage: HCPhys=%VHp pv=%VGv iPage=%d\n", HCPhys, pv, iPage));
1920 return VINF_SUCCESS;
1921
1922#else /* VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
1923 AssertFailed();
1924 return VERR_NOT_IMPLEMENTED;
1925#endif /* VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
1926}
1927
1928
1929/**
1930 * Temporarily maps one host page specified by HC physical address, returning
1931 * pointer within the page.
1932 *
1933 * Be WARNED that the dynamic page mapping area is small, 8 pages, thus the space is
1934 * reused after 8 mappings (or perhaps a few more if you score with the cache).
1935 *
1936 * @returns VBox status.
1937 * @param pVM VM handle.
1938 * @param HCPhys HC Physical address of the page.
1939 * @param ppv Where to store the address corresponding to HCPhys.
1940 */
1941VMMDECL(int) PGMDynMapHCPageOff(PVM pVM, RTHCPHYS HCPhys, void **ppv)
1942{
1943 int rc = PGMDynMapHCPage(pVM, HCPhys & ~(RTHCPHYS)PAGE_OFFSET_MASK, ppv);
1944 if (RT_SUCCESS(rc))
1945 *ppv = (void *)((uintptr_t)*ppv | (HCPhys & PAGE_OFFSET_MASK));
1946 return rc;
1947}
1948
1949#endif /* IN_GC || VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
1950
1951#ifdef VBOX_STRICT
1952
1953/**
1954 * Asserts that there are no mapping conflicts.
1955 *
1956 * @returns Number of conflicts.
1957 * @param pVM The VM Handle.
1958 */
1959VMMDECL(unsigned) PGMAssertNoMappingConflicts(PVM pVM)
1960{
1961 unsigned cErrors = 0;
1962
1963 /*
1964 * Check for mapping conflicts.
1965 */
1966 for (PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
1967 pMapping;
1968 pMapping = pMapping->CTX_SUFF(pNext))
1969 {
1970 /** @todo This is slow and should be optimized, but since it's just assertions I don't care now. */
1971 for (RTGCUINTPTR GCPtr = (RTGCUINTPTR)pMapping->GCPtr;
1972 GCPtr <= (RTGCUINTPTR)pMapping->GCPtrLast;
1973 GCPtr += PAGE_SIZE)
1974 {
1975 int rc = PGMGstGetPage(pVM, (RTGCPTR)GCPtr, NULL, NULL);
1976 if (rc != VERR_PAGE_TABLE_NOT_PRESENT)
1977 {
1978 AssertMsgFailed(("Conflict at %VGv with %s\n", GCPtr, R3STRING(pMapping->pszDesc)));
1979 cErrors++;
1980 break;
1981 }
1982 }
1983 }
1984
1985 return cErrors;
1986}
1987
1988
1989/**
1990 * Asserts that everything related to the guest CR3 is correctly shadowed.
1991 *
1992 * This will call PGMAssertNoMappingConflicts() and PGMAssertHandlerAndFlagsInSync(),
1993 * and assert the correctness of the guest CR3 mapping before asserting that the
1994 * shadow page tables is in sync with the guest page tables.
1995 *
1996 * @returns Number of conflicts.
1997 * @param pVM The VM Handle.
1998 * @param cr3 The current guest CR3 register value.
1999 * @param cr4 The current guest CR4 register value.
2000 */
2001VMMDECL(unsigned) PGMAssertCR3(PVM pVM, uint64_t cr3, uint64_t cr4)
2002{
2003 STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3), a);
2004 unsigned cErrors = PGM_BTH_PFN(AssertCR3, pVM)(pVM, cr3, cr4, 0, ~(RTGCUINTPTR)0);
2005 STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3), a);
2006 return cErrors;
2007 return 0;
2008}
2009
2010#endif /* VBOX_STRICT */
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