VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAll.cpp@ 13972

Last change on this file since 13972 was 13969, checked in by vboxsync, 16 years ago

PGM: RTGCUINTPTR64 -> RTGCPTR64 (forgot this one yesterday)
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id
File size: 65.4 KB
Line 
1/* $Id: PGMAll.cpp 13969 2008-11-07 16:06:39Z vboxsync $ */
2/** @file
3 * PGM - Page Manager and Monitor - All context code.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22/*******************************************************************************
23* Header Files *
24*******************************************************************************/
25#define LOG_GROUP LOG_GROUP_PGM
26#include <VBox/pgm.h>
27#include <VBox/cpum.h>
28#include <VBox/selm.h>
29#include <VBox/iom.h>
30#include <VBox/sup.h>
31#include <VBox/mm.h>
32#include <VBox/stam.h>
33#include <VBox/csam.h>
34#include <VBox/patm.h>
35#include <VBox/trpm.h>
36#include <VBox/rem.h>
37#include <VBox/em.h>
38#include <VBox/hwaccm.h>
39#include <VBox/hwacc_vmx.h>
40#include "PGMInternal.h"
41#include <VBox/vm.h>
42#include <iprt/assert.h>
43#include <iprt/asm.h>
44#include <iprt/string.h>
45#include <VBox/log.h>
46#include <VBox/param.h>
47#include <VBox/err.h>
48
49
50/*******************************************************************************
51* Structures and Typedefs *
52*******************************************************************************/
53/**
54 * Stated structure for PGM_GST_NAME(HandlerVirtualUpdate) that's
55 * passed to PGM_GST_NAME(VirtHandlerUpdateOne) during enumeration.
56 */
57typedef struct PGMHVUSTATE
58{
59 /** The VM handle. */
60 PVM pVM;
61 /** The todo flags. */
62 RTUINT fTodo;
63 /** The CR4 register value. */
64 uint32_t cr4;
65} PGMHVUSTATE, *PPGMHVUSTATE;
66
67
68/*******************************************************************************
69* Internal Functions *
70*******************************************************************************/
71
72/*
73 * Shadow - 32-bit mode
74 */
75#define PGM_SHW_TYPE PGM_TYPE_32BIT
76#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
77#include "PGMAllShw.h"
78
79/* Guest - real mode */
80#define PGM_GST_TYPE PGM_TYPE_REAL
81#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
82#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
83#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
84#include "PGMAllGst.h"
85#include "PGMAllBth.h"
86#undef BTH_PGMPOOLKIND_PT_FOR_PT
87#undef PGM_BTH_NAME
88#undef PGM_GST_TYPE
89#undef PGM_GST_NAME
90
91/* Guest - protected mode */
92#define PGM_GST_TYPE PGM_TYPE_PROT
93#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
94#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
95#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
96#include "PGMAllGst.h"
97#include "PGMAllBth.h"
98#undef BTH_PGMPOOLKIND_PT_FOR_PT
99#undef PGM_BTH_NAME
100#undef PGM_GST_TYPE
101#undef PGM_GST_NAME
102
103/* Guest - 32-bit mode */
104#define PGM_GST_TYPE PGM_TYPE_32BIT
105#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
106#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
107#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
108#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
109#include "PGMAllGst.h"
110#include "PGMAllBth.h"
111#undef BTH_PGMPOOLKIND_PT_FOR_BIG
112#undef BTH_PGMPOOLKIND_PT_FOR_PT
113#undef PGM_BTH_NAME
114#undef PGM_GST_TYPE
115#undef PGM_GST_NAME
116
117#undef PGM_SHW_TYPE
118#undef PGM_SHW_NAME
119
120
121/*
122 * Shadow - PAE mode
123 */
124#define PGM_SHW_TYPE PGM_TYPE_PAE
125#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
126#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
127#include "PGMAllShw.h"
128
129/* Guest - real mode */
130#define PGM_GST_TYPE PGM_TYPE_REAL
131#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
132#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
133#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
134#include "PGMAllBth.h"
135#undef BTH_PGMPOOLKIND_PT_FOR_PT
136#undef PGM_BTH_NAME
137#undef PGM_GST_TYPE
138#undef PGM_GST_NAME
139
140/* Guest - protected mode */
141#define PGM_GST_TYPE PGM_TYPE_PROT
142#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
143#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
144#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
145#include "PGMAllBth.h"
146#undef BTH_PGMPOOLKIND_PT_FOR_PT
147#undef PGM_BTH_NAME
148#undef PGM_GST_TYPE
149#undef PGM_GST_NAME
150
151/* Guest - 32-bit mode */
152#define PGM_GST_TYPE PGM_TYPE_32BIT
153#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
154#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
155#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
156#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
157#include "PGMAllBth.h"
158#undef BTH_PGMPOOLKIND_PT_FOR_BIG
159#undef BTH_PGMPOOLKIND_PT_FOR_PT
160#undef PGM_BTH_NAME
161#undef PGM_GST_TYPE
162#undef PGM_GST_NAME
163
164
165/* Guest - PAE mode */
166#define PGM_GST_TYPE PGM_TYPE_PAE
167#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
168#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
169#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
170#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
171#include "PGMAllGst.h"
172#include "PGMAllBth.h"
173#undef BTH_PGMPOOLKIND_PT_FOR_BIG
174#undef BTH_PGMPOOLKIND_PT_FOR_PT
175#undef PGM_BTH_NAME
176#undef PGM_GST_TYPE
177#undef PGM_GST_NAME
178
179#undef PGM_SHW_TYPE
180#undef PGM_SHW_NAME
181
182
183#ifndef IN_RC /* AMD64 implies VT-x/AMD-V */
184/*
185 * Shadow - AMD64 mode
186 */
187# define PGM_SHW_TYPE PGM_TYPE_AMD64
188# define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
189# include "PGMAllShw.h"
190
191/* Guest - protected mode */
192# define PGM_GST_TYPE PGM_TYPE_PROT
193# define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
194# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_PROT(name)
195# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
196# include "PGMAllBth.h"
197# undef BTH_PGMPOOLKIND_PT_FOR_PT
198# undef PGM_BTH_NAME
199# undef PGM_GST_TYPE
200# undef PGM_GST_NAME
201
202# ifdef VBOX_WITH_64_BITS_GUESTS
203/* Guest - AMD64 mode */
204# define PGM_GST_TYPE PGM_TYPE_AMD64
205# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
206# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
207# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
208# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
209# include "PGMAllGst.h"
210# include "PGMAllBth.h"
211# undef BTH_PGMPOOLKIND_PT_FOR_BIG
212# undef BTH_PGMPOOLKIND_PT_FOR_PT
213# undef PGM_BTH_NAME
214# undef PGM_GST_TYPE
215# undef PGM_GST_NAME
216# endif /* VBOX_WITH_64_BITS_GUESTS */
217
218# undef PGM_SHW_TYPE
219# undef PGM_SHW_NAME
220
221
222/*
223 * Shadow - Nested paging mode
224 */
225# define PGM_SHW_TYPE PGM_TYPE_NESTED
226# define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED(name)
227# include "PGMAllShw.h"
228
229/* Guest - real mode */
230# define PGM_GST_TYPE PGM_TYPE_REAL
231# define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
232# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_REAL(name)
233# include "PGMAllBth.h"
234# undef PGM_BTH_NAME
235# undef PGM_GST_TYPE
236# undef PGM_GST_NAME
237
238/* Guest - protected mode */
239# define PGM_GST_TYPE PGM_TYPE_PROT
240# define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
241# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PROT(name)
242# include "PGMAllBth.h"
243# undef PGM_BTH_NAME
244# undef PGM_GST_TYPE
245# undef PGM_GST_NAME
246
247/* Guest - 32-bit mode */
248# define PGM_GST_TYPE PGM_TYPE_32BIT
249# define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
250# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT(name)
251# include "PGMAllBth.h"
252# undef PGM_BTH_NAME
253# undef PGM_GST_TYPE
254# undef PGM_GST_NAME
255
256/* Guest - PAE mode */
257# define PGM_GST_TYPE PGM_TYPE_PAE
258# define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
259# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE(name)
260# include "PGMAllBth.h"
261# undef PGM_BTH_NAME
262# undef PGM_GST_TYPE
263# undef PGM_GST_NAME
264
265# ifdef VBOX_WITH_64_BITS_GUESTS
266/* Guest - AMD64 mode */
267# define PGM_GST_TYPE PGM_TYPE_AMD64
268# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
269# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64(name)
270# include "PGMAllBth.h"
271# undef PGM_BTH_NAME
272# undef PGM_GST_TYPE
273# undef PGM_GST_NAME
274# endif /* VBOX_WITH_64_BITS_GUESTS */
275
276# undef PGM_SHW_TYPE
277# undef PGM_SHW_NAME
278
279
280/*
281 * Shadow - EPT
282 */
283# define PGM_SHW_TYPE PGM_TYPE_EPT
284# define PGM_SHW_NAME(name) PGM_SHW_NAME_EPT(name)
285# include "PGMAllShw.h"
286
287/* Guest - real mode */
288# define PGM_GST_TYPE PGM_TYPE_REAL
289# define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
290# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_REAL(name)
291# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
292# include "PGMAllBth.h"
293# undef BTH_PGMPOOLKIND_PT_FOR_PT
294# undef PGM_BTH_NAME
295# undef PGM_GST_TYPE
296# undef PGM_GST_NAME
297
298/* Guest - protected mode */
299# define PGM_GST_TYPE PGM_TYPE_PROT
300# define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
301# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PROT(name)
302# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
303# include "PGMAllBth.h"
304# undef BTH_PGMPOOLKIND_PT_FOR_PT
305# undef PGM_BTH_NAME
306# undef PGM_GST_TYPE
307# undef PGM_GST_NAME
308
309/* Guest - 32-bit mode */
310# define PGM_GST_TYPE PGM_TYPE_32BIT
311# define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
312# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_32BIT(name)
313# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
314# include "PGMAllBth.h"
315# undef BTH_PGMPOOLKIND_PT_FOR_PT
316# undef PGM_BTH_NAME
317# undef PGM_GST_TYPE
318# undef PGM_GST_NAME
319
320/* Guest - PAE mode */
321# define PGM_GST_TYPE PGM_TYPE_PAE
322# define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
323# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PAE(name)
324# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
325# include "PGMAllBth.h"
326# undef BTH_PGMPOOLKIND_PT_FOR_PT
327# undef PGM_BTH_NAME
328# undef PGM_GST_TYPE
329# undef PGM_GST_NAME
330
331# ifdef VBOX_WITH_64_BITS_GUESTS
332/* Guest - AMD64 mode */
333# define PGM_GST_TYPE PGM_TYPE_AMD64
334# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
335# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_AMD64(name)
336# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
337# include "PGMAllBth.h"
338# undef BTH_PGMPOOLKIND_PT_FOR_PT
339# undef PGM_BTH_NAME
340# undef PGM_GST_TYPE
341# undef PGM_GST_NAME
342# endif /* VBOX_WITH_64_BITS_GUESTS */
343
344# undef PGM_SHW_TYPE
345# undef PGM_SHW_NAME
346
347#endif /* !IN_RC */
348
349
350#ifndef IN_RING3
351/**
352 * #PF Handler.
353 *
354 * @returns VBox status code (appropriate for trap handling and GC return).
355 * @param pVM VM Handle.
356 * @param uErr The trap error code.
357 * @param pRegFrame Trap register frame.
358 * @param pvFault The fault address.
359 */
360VMMDECL(int) PGMTrap0eHandler(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
361{
362 LogFlow(("PGMTrap0eHandler: uErr=%RGu pvFault=%RGv eip=%RGv\n", uErr, pvFault, (RTGCPTR)pRegFrame->rip));
363 STAM_PROFILE_START(&pVM->pgm.s.StatRZTrap0e, a);
364 STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = NULL; } );
365
366
367#ifdef VBOX_WITH_STATISTICS
368 /*
369 * Error code stats.
370 */
371 if (uErr & X86_TRAP_PF_US)
372 {
373 if (!(uErr & X86_TRAP_PF_P))
374 {
375 if (uErr & X86_TRAP_PF_RW)
376 STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eUSNotPresentWrite);
377 else
378 STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eUSNotPresentRead);
379 }
380 else if (uErr & X86_TRAP_PF_RW)
381 STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eUSWrite);
382 else if (uErr & X86_TRAP_PF_RSVD)
383 STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eUSReserved);
384 else if (uErr & X86_TRAP_PF_ID)
385 STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eUSNXE);
386 else
387 STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eUSRead);
388 }
389 else
390 { /* Supervisor */
391 if (!(uErr & X86_TRAP_PF_P))
392 {
393 if (uErr & X86_TRAP_PF_RW)
394 STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eSVNotPresentWrite);
395 else
396 STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eSVNotPresentRead);
397 }
398 else if (uErr & X86_TRAP_PF_RW)
399 STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eSVWrite);
400 else if (uErr & X86_TRAP_PF_ID)
401 STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eSNXE);
402 else if (uErr & X86_TRAP_PF_RSVD)
403 STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eSVReserved);
404 }
405#endif /* VBOX_WITH_STATISTICS */
406
407 /*
408 * Call the worker.
409 */
410 int rc = PGM_BTH_PFN(Trap0eHandler, pVM)(pVM, uErr, pRegFrame, pvFault);
411 if (rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
412 rc = VINF_SUCCESS;
413 STAM_STATS({ if (rc == VINF_EM_RAW_GUEST_TRAP) STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eGuestPF); });
414 STAM_STATS({ if (!pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution))
415 pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2Misc; });
416 STAM_PROFILE_STOP_EX(&pVM->pgm.s.StatRZTrap0e, pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution), a);
417 return rc;
418}
419#endif /* !IN_RING3 */
420
421
422/**
423 * Prefetch a page
424 *
425 * Typically used to sync commonly used pages before entering raw mode
426 * after a CR3 reload.
427 *
428 * @returns VBox status code suitable for scheduling.
429 * @retval VINF_SUCCESS on success.
430 * @retval VINF_PGM_SYNC_CR3 if we're out of shadow pages or something like that.
431 * @param pVM VM handle.
432 * @param GCPtrPage Page to invalidate.
433 */
434VMMDECL(int) PGMPrefetchPage(PVM pVM, RTGCPTR GCPtrPage)
435{
436 STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,Prefetch), a);
437 int rc = PGM_BTH_PFN(PrefetchPage, pVM)(pVM, GCPtrPage);
438 STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,Prefetch), a);
439 AssertMsg(rc == VINF_SUCCESS || rc == VINF_PGM_SYNC_CR3 || RT_FAILURE(rc), ("rc=%Rrc\n", rc));
440 return rc;
441}
442
443
444/**
445 * Gets the mapping corresponding to the specified address (if any).
446 *
447 * @returns Pointer to the mapping.
448 * @returns NULL if not
449 *
450 * @param pVM The virtual machine.
451 * @param GCPtr The guest context pointer.
452 */
453PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr)
454{
455 PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
456 while (pMapping)
457 {
458 if ((uintptr_t)GCPtr < (uintptr_t)pMapping->GCPtr)
459 break;
460 if ((uintptr_t)GCPtr - (uintptr_t)pMapping->GCPtr < pMapping->cb)
461 return pMapping;
462 pMapping = pMapping->CTX_SUFF(pNext);
463 }
464 return NULL;
465}
466
467
468/**
469 * Verifies a range of pages for read or write access
470 *
471 * Only checks the guest's page tables
472 *
473 * @returns VBox status code.
474 * @param pVM VM handle.
475 * @param Addr Guest virtual address to check
476 * @param cbSize Access size
477 * @param fAccess Access type (r/w, user/supervisor (X86_PTE_*))
478 * @remarks Current not in use.
479 */
480VMMDECL(int) PGMIsValidAccess(PVM pVM, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess)
481{
482 /*
483 * Validate input.
484 */
485 if (fAccess & ~(X86_PTE_US | X86_PTE_RW))
486 {
487 AssertMsgFailed(("PGMIsValidAccess: invalid access type %08x\n", fAccess));
488 return VERR_INVALID_PARAMETER;
489 }
490
491 uint64_t fPage;
492 int rc = PGMGstGetPage(pVM, (RTGCPTR)Addr, &fPage, NULL);
493 if (RT_FAILURE(rc))
494 {
495 Log(("PGMIsValidAccess: access violation for %RGv rc=%d\n", Addr, rc));
496 return VINF_EM_RAW_GUEST_TRAP;
497 }
498
499 /*
500 * Check if the access would cause a page fault
501 *
502 * Note that hypervisor page directories are not present in the guest's tables, so this check
503 * is sufficient.
504 */
505 bool fWrite = !!(fAccess & X86_PTE_RW);
506 bool fUser = !!(fAccess & X86_PTE_US);
507 if ( !(fPage & X86_PTE_P)
508 || (fWrite && !(fPage & X86_PTE_RW))
509 || (fUser && !(fPage & X86_PTE_US)) )
510 {
511 Log(("PGMIsValidAccess: access violation for %RGv attr %#llx vs %d:%d\n", Addr, fPage, fWrite, fUser));
512 return VINF_EM_RAW_GUEST_TRAP;
513 }
514 if ( RT_SUCCESS(rc)
515 && PAGE_ADDRESS(Addr) != PAGE_ADDRESS(Addr + cbSize))
516 return PGMIsValidAccess(pVM, Addr + PAGE_SIZE, (cbSize > PAGE_SIZE) ? cbSize - PAGE_SIZE : 1, fAccess);
517 return rc;
518}
519
520
521/**
522 * Verifies a range of pages for read or write access
523 *
524 * Supports handling of pages marked for dirty bit tracking and CSAM
525 *
526 * @returns VBox status code.
527 * @param pVM VM handle.
528 * @param Addr Guest virtual address to check
529 * @param cbSize Access size
530 * @param fAccess Access type (r/w, user/supervisor (X86_PTE_*))
531 */
532VMMDECL(int) PGMVerifyAccess(PVM pVM, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess)
533{
534 AssertMsg(!(fAccess & ~(X86_PTE_US | X86_PTE_RW)), ("PGMVerifyAccess: invalid access type %08x\n", fAccess));
535
536 /*
537 * Get going.
538 */
539 uint64_t fPageGst;
540 int rc = PGMGstGetPage(pVM, (RTGCPTR)Addr, &fPageGst, NULL);
541 if (RT_FAILURE(rc))
542 {
543 Log(("PGMVerifyAccess: access violation for %RGv rc=%d\n", Addr, rc));
544 return VINF_EM_RAW_GUEST_TRAP;
545 }
546
547 /*
548 * Check if the access would cause a page fault
549 *
550 * Note that hypervisor page directories are not present in the guest's tables, so this check
551 * is sufficient.
552 */
553 const bool fWrite = !!(fAccess & X86_PTE_RW);
554 const bool fUser = !!(fAccess & X86_PTE_US);
555 if ( !(fPageGst & X86_PTE_P)
556 || (fWrite && !(fPageGst & X86_PTE_RW))
557 || (fUser && !(fPageGst & X86_PTE_US)) )
558 {
559 Log(("PGMVerifyAccess: access violation for %RGv attr %#llx vs %d:%d\n", Addr, fPageGst, fWrite, fUser));
560 return VINF_EM_RAW_GUEST_TRAP;
561 }
562
563 if (!HWACCMIsNestedPagingActive(pVM))
564 {
565 /*
566 * Next step is to verify if we protected this page for dirty bit tracking or for CSAM scanning
567 */
568 rc = PGMShwGetPage(pVM, (RTGCPTR)Addr, NULL, NULL);
569 if ( rc == VERR_PAGE_NOT_PRESENT
570 || rc == VERR_PAGE_TABLE_NOT_PRESENT)
571 {
572 /*
573 * Page is not present in our page tables.
574 * Try to sync it!
575 */
576 Assert(X86_TRAP_PF_RW == X86_PTE_RW && X86_TRAP_PF_US == X86_PTE_US);
577 uint32_t uErr = fAccess & (X86_TRAP_PF_RW | X86_TRAP_PF_US);
578 rc = PGM_BTH_PFN(VerifyAccessSyncPage, pVM)(pVM, Addr, fPageGst, uErr);
579 if (rc != VINF_SUCCESS)
580 return rc;
581 }
582 else
583 AssertMsg(rc == VINF_SUCCESS, ("PGMShwGetPage %RGv failed with %Rrc\n", Addr, rc));
584 }
585
586#if 0 /* def VBOX_STRICT; triggers too often now */
587 /*
588 * This check is a bit paranoid, but useful.
589 */
590 /** @note this will assert when writing to monitored pages (a bit annoying actually) */
591 uint64_t fPageShw;
592 rc = PGMShwGetPage(pVM, (RTGCPTR)Addr, &fPageShw, NULL);
593 if ( (rc == VERR_PAGE_NOT_PRESENT || RT_FAILURE(rc))
594 || (fWrite && !(fPageShw & X86_PTE_RW))
595 || (fUser && !(fPageShw & X86_PTE_US)) )
596 {
597 AssertMsgFailed(("Unexpected access violation for %RGv! rc=%Rrc write=%d user=%d\n",
598 Addr, rc, fWrite && !(fPageShw & X86_PTE_RW), fUser && !(fPageShw & X86_PTE_US)));
599 return VINF_EM_RAW_GUEST_TRAP;
600 }
601#endif
602
603 if ( RT_SUCCESS(rc)
604 && ( PAGE_ADDRESS(Addr) != PAGE_ADDRESS(Addr + cbSize - 1)
605 || Addr + cbSize < Addr))
606 {
607 /* Don't recursively call PGMVerifyAccess as we might run out of stack. */
608 for (;;)
609 {
610 Addr += PAGE_SIZE;
611 if (cbSize > PAGE_SIZE)
612 cbSize -= PAGE_SIZE;
613 else
614 cbSize = 1;
615 rc = PGMVerifyAccess(pVM, Addr, 1, fAccess);
616 if (rc != VINF_SUCCESS)
617 break;
618 if (PAGE_ADDRESS(Addr) == PAGE_ADDRESS(Addr + cbSize - 1))
619 break;
620 }
621 }
622 return rc;
623}
624
625
626/**
627 * Emulation of the invlpg instruction (HC only actually).
628 *
629 * @returns VBox status code, special care required.
630 * @retval VINF_PGM_SYNC_CR3 - handled.
631 * @retval VINF_EM_RAW_EMULATE_INSTR - not handled (RC only).
632 * @retval VERR_REM_FLUSHED_PAGES_OVERFLOW - not handled.
633 *
634 * @param pVM VM handle.
635 * @param GCPtrPage Page to invalidate.
636 *
637 * @remark ASSUMES the page table entry or page directory is valid. Fairly
638 * safe, but there could be edge cases!
639 *
640 * @todo Flush page or page directory only if necessary!
641 */
642VMMDECL(int) PGMInvalidatePage(PVM pVM, RTGCPTR GCPtrPage)
643{
644 int rc;
645 Log3(("PGMInvalidatePage: GCPtrPage=%RGv\n", GCPtrPage));
646
647#ifndef IN_RING3
648 /*
649 * Notify the recompiler so it can record this instruction.
650 * Failure happens when it's out of space. We'll return to HC in that case.
651 */
652 rc = REMNotifyInvalidatePage(pVM, GCPtrPage);
653 if (rc != VINF_SUCCESS)
654 return rc;
655#endif /* !IN_RING3 */
656
657
658#ifdef IN_RC
659 /*
660 * Check for conflicts and pending CR3 monitoring updates.
661 */
662 if (!pVM->pgm.s.fMappingsFixed)
663 {
664 if ( pgmGetMapping(pVM, GCPtrPage)
665 && PGMGstGetPage(pVM, GCPtrPage, NULL, NULL) != VERR_PAGE_TABLE_NOT_PRESENT)
666 {
667 LogFlow(("PGMGCInvalidatePage: Conflict!\n"));
668 VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
669 STAM_COUNTER_INC(&pVM->pgm.s.StatRCInvlPgConflict);
670 return VINF_PGM_SYNC_CR3;
671 }
672
673 if (pVM->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
674 {
675 LogFlow(("PGMGCInvalidatePage: PGM_SYNC_MONITOR_CR3 -> reinterpret instruction in R3\n"));
676 STAM_COUNTER_INC(&pVM->pgm.s.StatRCInvlPgSyncMonCR3);
677 return VINF_EM_RAW_EMULATE_INSTR;
678 }
679 }
680#endif /* IN_RC */
681
682 /*
683 * Call paging mode specific worker.
684 */
685 STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePage), a);
686 rc = PGM_BTH_PFN(InvalidatePage, pVM)(pVM, GCPtrPage);
687 STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePage), a);
688
689#ifdef IN_RING3
690 /*
691 * Check if we have a pending update of the CR3 monitoring.
692 */
693 if ( RT_SUCCESS(rc)
694 && (pVM->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3))
695 {
696 pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
697 Assert(!pVM->pgm.s.fMappingsFixed);
698 Assert(pVM->pgm.s.GCPhysCR3 == pVM->pgm.s.GCPhysGstCR3Monitored);
699 rc = PGM_GST_PFN(MonitorCR3, pVM)(pVM, pVM->pgm.s.GCPhysCR3);
700 }
701
702 /*
703 * Inform CSAM about the flush
704 *
705 * Note: This is to check if monitored pages have been changed; when we implement
706 * callbacks for virtual handlers, this is no longer required.
707 */
708 CSAMR3FlushPage(pVM, GCPtrPage);
709#endif /* IN_RING3 */
710 return rc;
711}
712
713
714/**
715 * Executes an instruction using the interpreter.
716 *
717 * @returns VBox status code (appropriate for trap handling and GC return).
718 * @param pVM VM handle.
719 * @param pRegFrame Register frame.
720 * @param pvFault Fault address.
721 */
722VMMDECL(int) PGMInterpretInstruction(PVM pVM, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
723{
724 uint32_t cb;
725 int rc = EMInterpretInstruction(pVM, pRegFrame, pvFault, &cb);
726 if (rc == VERR_EM_INTERPRETER)
727 rc = VINF_EM_RAW_EMULATE_INSTR;
728 if (rc != VINF_SUCCESS)
729 Log(("PGMInterpretInstruction: returns %Rrc (pvFault=%RGv)\n", rc, pvFault));
730 return rc;
731}
732
733
734/**
735 * Gets effective page information (from the VMM page directory).
736 *
737 * @returns VBox status.
738 * @param pVM VM Handle.
739 * @param GCPtr Guest Context virtual address of the page.
740 * @param pfFlags Where to store the flags. These are X86_PTE_*.
741 * @param pHCPhys Where to store the HC physical address of the page.
742 * This is page aligned.
743 * @remark You should use PGMMapGetPage() for pages in a mapping.
744 */
745VMMDECL(int) PGMShwGetPage(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys)
746{
747 return PGM_SHW_PFN(GetPage,pVM)(pVM, GCPtr, pfFlags, pHCPhys);
748}
749
750
751/**
752 * Sets (replaces) the page flags for a range of pages in the shadow context.
753 *
754 * @returns VBox status.
755 * @param pVM VM handle.
756 * @param GCPtr The address of the first page.
757 * @param cb The size of the range in bytes.
758 * @param fFlags Page flags X86_PTE_*, excluding the page mask of course.
759 * @remark You must use PGMMapSetPage() for pages in a mapping.
760 */
761VMMDECL(int) PGMShwSetPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags)
762{
763 return PGMShwModifyPage(pVM, GCPtr, cb, fFlags, 0);
764}
765
766
767/**
768 * Modify page flags for a range of pages in the shadow context.
769 *
770 * The existing flags are ANDed with the fMask and ORed with the fFlags.
771 *
772 * @returns VBox status code.
773 * @param pVM VM handle.
774 * @param GCPtr Virtual address of the first page in the range.
775 * @param cb Size (in bytes) of the range to apply the modification to.
776 * @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
777 * @param fMask The AND mask - page flags X86_PTE_*.
778 * Be very CAREFUL when ~'ing constants which could be 32-bit!
779 * @remark You must use PGMMapModifyPage() for pages in a mapping.
780 */
781VMMDECL(int) PGMShwModifyPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
782{
783 AssertMsg(!(fFlags & X86_PTE_PAE_PG_MASK), ("fFlags=%#llx\n", fFlags));
784 Assert(cb);
785
786 /*
787 * Align the input.
788 */
789 cb += GCPtr & PAGE_OFFSET_MASK;
790 cb = RT_ALIGN_Z(cb, PAGE_SIZE);
791 GCPtr = (GCPtr & PAGE_BASE_GC_MASK); /** @todo this ain't necessary, right... */
792
793 /*
794 * Call worker.
795 */
796 return PGM_SHW_PFN(ModifyPage, pVM)(pVM, GCPtr, cb, fFlags, fMask);
797}
798
799
800/**
801 * Syncs the SHADOW page directory pointer for the specified address.
802 *
803 * Allocates backing pages in case the PDPT entry is missing.
804 *
805 * @returns VBox status.
806 * @param pVM VM handle.
807 * @param GCPtr The address.
808 * @param pGstPdpe Guest PDPT entry
809 * @param ppPD Receives address of page directory
810 */
811VMMDECL(int) PGMShwSyncPAEPDPtr(PVM pVM, RTGCPTR GCPtr, PX86PDPE pGstPdpe, PX86PDPAE *ppPD)
812{
813 PPGM pPGM = &pVM->pgm.s;
814 PPGMPOOL pPool = pPGM->CTX_SUFF(pPool);
815 PPGMPOOLPAGE pShwPage;
816 int rc;
817
818 Assert(!HWACCMIsNestedPagingActive(pVM));
819
820 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
821 PX86PDPT pPdpt = pVM->pgm.s.CTXMID(p,PaePDPT);
822 PX86PDPE pPdpe = &pPdpt->a[iPdPt];
823
824 /* Allocate page directory if not present. */
825 if ( !pPdpe->n.u1Present
826 && !(pPdpe->u & X86_PDPE_PG_MASK))
827 {
828 PX86PDPE pPdptGst = pgmGstGetPaePDPEPtr(pPGM, GCPtr);
829
830 Assert(!(pPdpe->u & X86_PDPE_PG_MASK));
831 /* Create a reference back to the PDPT by using the index in its shadow page. */
832 rc = pgmPoolAlloc(pVM, pPdptGst->u & X86_PDPE_PG_MASK, PGMPOOLKIND_PAE_PD_FOR_PAE_PD, PGMPOOL_IDX_PDPT, iPdPt, &pShwPage);
833 if (rc == VERR_PGM_POOL_FLUSHED)
834 {
835 Assert(pVM->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL);
836 VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
837 return VINF_PGM_SYNC_CR3;
838 }
839 AssertRCReturn(rc, rc);
840 }
841 else
842 {
843 pShwPage = pgmPoolGetPage(pPool, pPdpe->u & X86_PDPE_PG_MASK);
844 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
845 }
846 /* The PD was cached or created; hook it up now. */
847 pPdpe->u |= pShwPage->Core.Key
848 | (pGstPdpe->u & ~(X86_PDPE_PG_MASK | X86_PDPE_AVL_MASK | X86_PDPE_PCD | X86_PDPE_PWT));
849
850 *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
851 return VINF_SUCCESS;
852}
853
854
855/**
856 * Gets the SHADOW page directory pointer for the specified address.
857 *
858 * @returns VBox status.
859 * @param pVM VM handle.
860 * @param GCPtr The address.
861 * @param ppPdpt Receives address of pdpt
862 * @param ppPD Receives address of page directory
863 */
864VMMDECL(int) PGMShwGetPAEPDPtr(PVM pVM, RTGCPTR GCPtr, PX86PDPT *ppPdpt, PX86PDPAE *ppPD)
865{
866 PPGM pPGM = &pVM->pgm.s;
867 PPGMPOOL pPool = pPGM->CTX_SUFF(pPool);
868 PPGMPOOLPAGE pShwPage;
869
870 Assert(!HWACCMIsNestedPagingActive(pVM));
871
872 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
873 PX86PDPT pPdpt = pVM->pgm.s.CTXMID(p,PaePDPT);
874 PX86PDPE pPdpe = &pPdpt->a[iPdPt];
875
876 *ppPdpt = pPdpt;
877 if (!pPdpe->n.u1Present)
878 return VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT;
879
880 pShwPage = pgmPoolGetPage(pPool, pPdpe->u & X86_PDPE_PG_MASK);
881 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
882
883 *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
884 return VINF_SUCCESS;
885}
886
887#ifndef IN_RC
888
889/**
890 * Syncs the SHADOW page directory pointer for the specified address.
891 *
892 * Allocates backing pages in case the PDPT or PML4 entry is missing.
893 *
894 * The caller is responsible for making sure the guest has a valid PD before
895 * calling this function.
896 *
897 * @returns VBox status.
898 * @param pVM VM handle.
899 * @param GCPtr The address.
900 * @param pGstPml4e Guest PML4 entry
901 * @param pGstPdpe Guest PDPT entry
902 * @param ppPD Receives address of page directory
903 */
904VMMDECL(int) PGMShwSyncLongModePDPtr(PVM pVM, RTGCPTR64 GCPtr, PX86PML4E pGstPml4e, PX86PDPE pGstPdpe, PX86PDPAE *ppPD)
905{
906 PPGM pPGM = &pVM->pgm.s;
907 const unsigned iPml4e = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
908 PPGMPOOL pPool = pPGM->CTX_SUFF(pPool);
909 PX86PML4E pPml4e;
910 PPGMPOOLPAGE pShwPage;
911 X86PML4E Pml4eGst;
912 int rc;
913 bool fNestedPaging = HWACCMIsNestedPagingActive(pVM);
914
915 Assert(pVM->pgm.s.pHCPaePML4);
916
917 /* Allocate page directory pointer table if not present. */
918 pPml4e = &pPGM->pHCPaePML4->a[iPml4e];
919 if ( !pPml4e->n.u1Present
920 && !(pPml4e->u & X86_PML4E_PG_MASK))
921 {
922 Assert(!(pPml4e->u & X86_PML4E_PG_MASK));
923
924 if (!fNestedPaging)
925 {
926 /** @todo why are we looking up the guest PML4E here? Isn't pGstPml4e
927 * trustworthy? (Remove pgmGstGetLongModePML4E if pGstPml4e and pGstPdpe
928 * are fine.) */
929 Assert(pVM->pgm.s.pHCShwAmd64CR3);
930 Pml4eGst.u = pgmGstGetLongModePML4E(&pVM->pgm.s, iPml4e);
931
932 rc = pgmPoolAlloc(pVM, Pml4eGst.u & X86_PML4E_PG_MASK,
933 PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT, pVM->pgm.s.pHCShwAmd64CR3->idx, iPml4e, &pShwPage);
934 }
935 else
936 rc = pgmPoolAlloc(pVM, GCPtr + RT_BIT_64(63) /* hack: make the address unique */,
937 PGMPOOLKIND_64BIT_PDPT_FOR_PHYS, PGMPOOL_IDX_NESTED_ROOT, iPml4e, &pShwPage);
938
939 if (rc == VERR_PGM_POOL_FLUSHED)
940 {
941 Log(("PGMShwSyncLongModePDPtr: PGM pool flushed (1) -> signal sync cr3\n"));
942 Assert(pVM->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL);
943 VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
944 return VINF_PGM_SYNC_CR3;
945 }
946 AssertRCReturn(rc, rc);
947 }
948 else
949 {
950 pShwPage = pgmPoolGetPage(pPool, pPml4e->u & X86_PML4E_PG_MASK);
951 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
952 }
953 /* The PDPT was cached or created; hook it up now. */
954 pPml4e->u |= pShwPage->Core.Key
955 | (pGstPml4e->u & ~(X86_PML4E_PG_MASK | X86_PML4E_AVL_MASK | X86_PML4E_PCD | X86_PML4E_PWT));
956
957 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
958 PX86PDPT pPdpt = (PX86PDPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
959 PX86PDPE pPdpe = &pPdpt->a[iPdPt];
960
961 /* Allocate page directory if not present. */
962 if ( !pPdpe->n.u1Present
963 && !(pPdpe->u & X86_PDPE_PG_MASK))
964 {
965 if (!fNestedPaging)
966 {
967 /** @todo why are we looking up the guest PDPTE here? Isn't pGstPdpe
968 * trustworthy? */
969 Pml4eGst.u = pgmGstGetLongModePML4E(&pVM->pgm.s, iPml4e);
970 PX86PDPT pPdptGst;
971 rc = PGM_GCPHYS_2_PTR(pVM, Pml4eGst.u & X86_PML4E_PG_MASK, &pPdptGst);
972 AssertRCReturn(rc, rc);
973
974 Assert(!(pPdpe->u & X86_PDPE_PG_MASK));
975 /* Create a reference back to the PDPT by using the index in its shadow page. */
976 rc = pgmPoolAlloc(pVM, pPdptGst->a[iPdPt].u & X86_PDPE_PG_MASK, PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD, pShwPage->idx, iPdPt, &pShwPage);
977 }
978 else
979 rc = pgmPoolAlloc(pVM, GCPtr + RT_BIT_64(62) /* hack: make the address unique */, PGMPOOLKIND_64BIT_PD_FOR_PHYS, pShwPage->idx, iPdPt, &pShwPage);
980
981 if (rc == VERR_PGM_POOL_FLUSHED)
982 {
983 Log(("PGMShwSyncLongModePDPtr: PGM pool flushed (2) -> signal sync cr3\n"));
984 Assert(pVM->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL);
985 VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
986 return VINF_PGM_SYNC_CR3;
987 }
988 AssertRCReturn(rc, rc);
989 }
990 else
991 {
992 pShwPage = pgmPoolGetPage(pPool, pPdpe->u & X86_PDPE_PG_MASK);
993 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
994 }
995 /* The PD was cached or created; hook it up now. */
996 pPdpe->u |= pShwPage->Core.Key
997 | (pGstPdpe->u & ~(X86_PDPE_PG_MASK | X86_PDPE_AVL_MASK | X86_PDPE_PCD | X86_PDPE_PWT));
998
999 *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1000 return VINF_SUCCESS;
1001}
1002
1003
1004/**
1005 * Gets the SHADOW page directory pointer for the specified address.
1006 *
1007 * @returns VBox status.
1008 * @param pVM VM handle.
1009 * @param GCPtr The address.
1010 * @param ppPdpt Receives address of pdpt
1011 * @param ppPD Receives address of page directory
1012 */
1013VMMDECL(int) PGMShwGetLongModePDPtr(PVM pVM, RTGCPTR64 GCPtr, PX86PDPT *ppPdpt, PX86PDPAE *ppPD)
1014{
1015 PPGM pPGM = &pVM->pgm.s;
1016 const unsigned iPml4e = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
1017 PPGMPOOL pPool = pPGM->CTX_SUFF(pPool);
1018 PX86PML4E pPml4e;
1019 PPGMPOOLPAGE pShwPage;
1020
1021 AssertReturn(pVM->pgm.s.pHCPaePML4, VERR_INTERNAL_ERROR);
1022
1023 pPml4e = &pPGM->pHCPaePML4->a[iPml4e];
1024 if (!pPml4e->n.u1Present)
1025 return VERR_PAGE_MAP_LEVEL4_NOT_PRESENT;
1026
1027 pShwPage = pgmPoolGetPage(pPool, pPml4e->u & X86_PML4E_PG_MASK);
1028 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1029
1030 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1031 PX86PDPT pPdpt = (PX86PDPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1032 PX86PDPE pPdpe = &pPdpt->a[iPdPt];
1033
1034 *ppPdpt = pPdpt;
1035 if (!pPdpe->n.u1Present)
1036 return VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT;
1037
1038 pShwPage = pgmPoolGetPage(pPool, pPdpe->u & X86_PDPE_PG_MASK);
1039 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1040
1041 *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1042 return VINF_SUCCESS;
1043}
1044
1045
1046/**
1047 * Syncs the SHADOW EPT page directory pointer for the specified address. Allocates
1048 * backing pages in case the PDPT or PML4 entry is missing.
1049 *
1050 * @returns VBox status.
1051 * @param pVM VM handle.
1052 * @param GCPtr The address.
1053 * @param ppPdpt Receives address of pdpt
1054 * @param ppPD Receives address of page directory
1055 */
1056VMMDECL(int) PGMShwGetEPTPDPtr(PVM pVM, RTGCPTR64 GCPtr, PEPTPDPT *ppPdpt, PEPTPD *ppPD)
1057{
1058 PPGM pPGM = &pVM->pgm.s;
1059 const unsigned iPml4e = (GCPtr >> EPT_PML4_SHIFT) & EPT_PML4_MASK;
1060 PPGMPOOL pPool = pPGM->CTX_SUFF(pPool);
1061 PEPTPML4 pPml4 = (PEPTPML4)pPGM->pHCNestedRoot;
1062 PEPTPML4E pPml4e;
1063 PPGMPOOLPAGE pShwPage;
1064 int rc;
1065
1066 Assert(HWACCMIsNestedPagingActive(pVM));
1067 Assert(pPml4);
1068
1069 /* Allocate page directory pointer table if not present. */
1070 pPml4e = &pPml4->a[iPml4e];
1071 if ( !pPml4e->n.u1Present
1072 && !(pPml4e->u & EPT_PML4E_PG_MASK))
1073 {
1074 Assert(!(pPml4e->u & EPT_PML4E_PG_MASK));
1075
1076 rc = pgmPoolAlloc(pVM, (GCPtr & EPT_PML4E_PG_MASK) + RT_BIT_64(63) /* hack: make the address unique */, PGMPOOLKIND_EPT_PDPT_FOR_PHYS, PGMPOOL_IDX_NESTED_ROOT, iPml4e, &pShwPage);
1077 if (rc == VERR_PGM_POOL_FLUSHED)
1078 {
1079 Log(("PGMShwSyncEPTPDPtr: PGM pool flushed (1) -> signal sync cr3\n"));
1080 Assert(pVM->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL);
1081 VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
1082 return VINF_PGM_SYNC_CR3;
1083 }
1084 AssertRCReturn(rc, rc);
1085 }
1086 else
1087 {
1088 pShwPage = pgmPoolGetPage(pPool, pPml4e->u & EPT_PML4E_PG_MASK);
1089 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1090 }
1091 /* The PDPT was cached or created; hook it up now and fill with the default value. */
1092 pPml4e->u = pShwPage->Core.Key;
1093 pPml4e->n.u1Present = 1;
1094 pPml4e->n.u1Write = 1;
1095 pPml4e->n.u1Execute = 1;
1096
1097 const unsigned iPdPt = (GCPtr >> EPT_PDPT_SHIFT) & EPT_PDPT_MASK;
1098 PEPTPDPT pPdpt = (PEPTPDPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1099 PEPTPDPTE pPdpe = &pPdpt->a[iPdPt];
1100
1101 if (ppPdpt)
1102 *ppPdpt = pPdpt;
1103
1104 /* Allocate page directory if not present. */
1105 if ( !pPdpe->n.u1Present
1106 && !(pPdpe->u & EPT_PDPTE_PG_MASK))
1107 {
1108 rc = pgmPoolAlloc(pVM, (GCPtr & EPT_PDPTE_PG_MASK) + RT_BIT_64(62) /* hack: make the address unique */, PGMPOOLKIND_64BIT_PD_FOR_PHYS, pShwPage->idx, iPdPt, &pShwPage);
1109 if (rc == VERR_PGM_POOL_FLUSHED)
1110 {
1111 Log(("PGMShwSyncEPTPDPtr: PGM pool flushed (2) -> signal sync cr3\n"));
1112 Assert(pVM->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL);
1113 VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
1114 return VINF_PGM_SYNC_CR3;
1115 }
1116 AssertRCReturn(rc, rc);
1117 }
1118 else
1119 {
1120 pShwPage = pgmPoolGetPage(pPool, pPdpe->u & EPT_PDPTE_PG_MASK);
1121 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1122 }
1123 /* The PD was cached or created; hook it up now and fill with the default value. */
1124 pPdpe->u = pShwPage->Core.Key;
1125 pPdpe->n.u1Present = 1;
1126 pPdpe->n.u1Write = 1;
1127 pPdpe->n.u1Execute = 1;
1128
1129 *ppPD = (PEPTPD)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1130 return VINF_SUCCESS;
1131}
1132
1133#endif /* IN_RC */
1134
1135/**
1136 * Gets effective Guest OS page information.
1137 *
1138 * When GCPtr is in a big page, the function will return as if it was a normal
1139 * 4KB page. If the need for distinguishing between big and normal page becomes
1140 * necessary at a later point, a PGMGstGetPage() will be created for that
1141 * purpose.
1142 *
1143 * @returns VBox status.
1144 * @param pVM VM Handle.
1145 * @param GCPtr Guest Context virtual address of the page.
1146 * @param pfFlags Where to store the flags. These are X86_PTE_*, even for big pages.
1147 * @param pGCPhys Where to store the GC physical address of the page.
1148 * This is page aligned. The fact that the
1149 */
1150VMMDECL(int) PGMGstGetPage(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys)
1151{
1152 return PGM_GST_PFN(GetPage,pVM)(pVM, GCPtr, pfFlags, pGCPhys);
1153}
1154
1155
1156/**
1157 * Checks if the page is present.
1158 *
1159 * @returns true if the page is present.
1160 * @returns false if the page is not present.
1161 * @param pVM The VM handle.
1162 * @param GCPtr Address within the page.
1163 */
1164VMMDECL(bool) PGMGstIsPagePresent(PVM pVM, RTGCPTR GCPtr)
1165{
1166 int rc = PGMGstGetPage(pVM, GCPtr, NULL, NULL);
1167 return RT_SUCCESS(rc);
1168}
1169
1170
1171/**
1172 * Sets (replaces) the page flags for a range of pages in the guest's tables.
1173 *
1174 * @returns VBox status.
1175 * @param pVM VM handle.
1176 * @param GCPtr The address of the first page.
1177 * @param cb The size of the range in bytes.
1178 * @param fFlags Page flags X86_PTE_*, excluding the page mask of course.
1179 */
1180VMMDECL(int) PGMGstSetPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags)
1181{
1182 return PGMGstModifyPage(pVM, GCPtr, cb, fFlags, 0);
1183}
1184
1185
1186/**
1187 * Modify page flags for a range of pages in the guest's tables
1188 *
1189 * The existing flags are ANDed with the fMask and ORed with the fFlags.
1190 *
1191 * @returns VBox status code.
1192 * @param pVM VM handle.
1193 * @param GCPtr Virtual address of the first page in the range.
1194 * @param cb Size (in bytes) of the range to apply the modification to.
1195 * @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
1196 * @param fMask The AND mask - page flags X86_PTE_*, excluding the page mask of course.
1197 * Be very CAREFUL when ~'ing constants which could be 32-bit!
1198 */
1199VMMDECL(int) PGMGstModifyPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
1200{
1201 STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,GstModifyPage), a);
1202
1203 /*
1204 * Validate input.
1205 */
1206 AssertMsg(!(fFlags & X86_PTE_PAE_PG_MASK), ("fFlags=%#llx\n", fFlags));
1207 Assert(cb);
1208
1209 LogFlow(("PGMGstModifyPage %RGv %d bytes fFlags=%08llx fMask=%08llx\n", GCPtr, cb, fFlags, fMask));
1210
1211 /*
1212 * Adjust input.
1213 */
1214 cb += GCPtr & PAGE_OFFSET_MASK;
1215 cb = RT_ALIGN_Z(cb, PAGE_SIZE);
1216 GCPtr = (GCPtr & PAGE_BASE_GC_MASK);
1217
1218 /*
1219 * Call worker.
1220 */
1221 int rc = PGM_GST_PFN(ModifyPage, pVM)(pVM, GCPtr, cb, fFlags, fMask);
1222
1223 STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,GstModifyPage), a);
1224 return rc;
1225}
1226
1227
1228/**
1229 * Gets the specified page directory pointer table entry.
1230 *
1231 * @returns PDP entry
1232 * @param pPGM Pointer to the PGM instance data.
1233 * @param iPdpt PDPT index
1234 */
1235VMMDECL(X86PDPE) PGMGstGetPaePDPtr(PVM pVM, unsigned iPdpt)
1236{
1237 Assert(iPdpt <= 3);
1238 return pgmGstGetPaePDPTPtr(&pVM->pgm.s)->a[iPdpt & 3];
1239}
1240
1241
1242/**
1243 * Gets the current CR3 register value for the shadow memory context.
1244 * @returns CR3 value.
1245 * @param pVM The VM handle.
1246 */
1247VMMDECL(RTHCPHYS) PGMGetHyperCR3(PVM pVM)
1248{
1249 PGMMODE enmShadowMode = pVM->pgm.s.enmShadowMode;
1250 switch (enmShadowMode)
1251 {
1252 case PGMMODE_32_BIT:
1253 return pVM->pgm.s.HCPhys32BitPD;
1254
1255 case PGMMODE_PAE:
1256 case PGMMODE_PAE_NX:
1257 return pVM->pgm.s.HCPhysPaePDPT;
1258
1259 case PGMMODE_AMD64:
1260 case PGMMODE_AMD64_NX:
1261 return pVM->pgm.s.HCPhysPaePML4;
1262
1263 case PGMMODE_EPT:
1264 return pVM->pgm.s.HCPhysNestedRoot;
1265
1266 case PGMMODE_NESTED:
1267 return PGMGetNestedCR3(pVM, PGMGetHostMode(pVM));
1268
1269 default:
1270 AssertMsgFailed(("enmShadowMode=%d\n", enmShadowMode));
1271 return ~0;
1272 }
1273}
1274
1275
1276/**
1277 * Gets the current CR3 register value for the nested memory context.
1278 * @returns CR3 value.
1279 * @param pVM The VM handle.
1280 */
1281VMMDECL(RTHCPHYS) PGMGetNestedCR3(PVM pVM, PGMMODE enmShadowMode)
1282{
1283 switch (enmShadowMode)
1284 {
1285 case PGMMODE_32_BIT:
1286 return pVM->pgm.s.HCPhys32BitPD;
1287
1288 case PGMMODE_PAE:
1289 case PGMMODE_PAE_NX:
1290 return pVM->pgm.s.HCPhysPaePDPT;
1291
1292 case PGMMODE_AMD64:
1293 case PGMMODE_AMD64_NX:
1294 return pVM->pgm.s.HCPhysPaePML4;
1295
1296 default:
1297 AssertMsgFailed(("enmShadowMode=%d\n", enmShadowMode));
1298 return ~0;
1299 }
1300}
1301
1302
1303/**
1304 * Gets the current CR3 register value for the EPT paging memory context.
1305 * @returns CR3 value.
1306 * @param pVM The VM handle.
1307 */
1308VMMDECL(RTHCPHYS) PGMGetEPTCR3(PVM pVM)
1309{
1310 return pVM->pgm.s.HCPhysNestedRoot;
1311}
1312
1313
1314/**
1315 * Gets the CR3 register value for the 32-Bit shadow memory context.
1316 * @returns CR3 value.
1317 * @param pVM The VM handle.
1318 */
1319VMMDECL(RTHCPHYS) PGMGetHyper32BitCR3(PVM pVM)
1320{
1321 return pVM->pgm.s.HCPhys32BitPD;
1322}
1323
1324
1325/**
1326 * Gets the CR3 register value for the PAE shadow memory context.
1327 * @returns CR3 value.
1328 * @param pVM The VM handle.
1329 */
1330VMMDECL(RTHCPHYS) PGMGetHyperPaeCR3(PVM pVM)
1331{
1332 return pVM->pgm.s.HCPhysPaePDPT;
1333}
1334
1335
1336/**
1337 * Gets the CR3 register value for the AMD64 shadow memory context.
1338 * @returns CR3 value.
1339 * @param pVM The VM handle.
1340 */
1341VMMDECL(RTHCPHYS) PGMGetHyperAmd64CR3(PVM pVM)
1342{
1343 return pVM->pgm.s.HCPhysPaePML4;
1344}
1345
1346
1347/**
1348 * Gets the current CR3 register value for the HC intermediate memory context.
1349 * @returns CR3 value.
1350 * @param pVM The VM handle.
1351 */
1352VMMDECL(RTHCPHYS) PGMGetInterHCCR3(PVM pVM)
1353{
1354 switch (pVM->pgm.s.enmHostMode)
1355 {
1356 case SUPPAGINGMODE_32_BIT:
1357 case SUPPAGINGMODE_32_BIT_GLOBAL:
1358 return pVM->pgm.s.HCPhysInterPD;
1359
1360 case SUPPAGINGMODE_PAE:
1361 case SUPPAGINGMODE_PAE_GLOBAL:
1362 case SUPPAGINGMODE_PAE_NX:
1363 case SUPPAGINGMODE_PAE_GLOBAL_NX:
1364 return pVM->pgm.s.HCPhysInterPaePDPT;
1365
1366 case SUPPAGINGMODE_AMD64:
1367 case SUPPAGINGMODE_AMD64_GLOBAL:
1368 case SUPPAGINGMODE_AMD64_NX:
1369 case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1370 return pVM->pgm.s.HCPhysInterPaePDPT;
1371
1372 default:
1373 AssertMsgFailed(("enmHostMode=%d\n", pVM->pgm.s.enmHostMode));
1374 return ~0;
1375 }
1376}
1377
1378
1379/**
1380 * Gets the current CR3 register value for the RC intermediate memory context.
1381 * @returns CR3 value.
1382 * @param pVM The VM handle.
1383 */
1384VMMDECL(RTHCPHYS) PGMGetInterRCCR3(PVM pVM)
1385{
1386 switch (pVM->pgm.s.enmShadowMode)
1387 {
1388 case PGMMODE_32_BIT:
1389 return pVM->pgm.s.HCPhysInterPD;
1390
1391 case PGMMODE_PAE:
1392 case PGMMODE_PAE_NX:
1393 return pVM->pgm.s.HCPhysInterPaePDPT;
1394
1395 case PGMMODE_AMD64:
1396 case PGMMODE_AMD64_NX:
1397 return pVM->pgm.s.HCPhysInterPaePML4;
1398
1399 case PGMMODE_EPT:
1400 case PGMMODE_NESTED:
1401 return 0; /* not relevant */
1402
1403 default:
1404 AssertMsgFailed(("enmShadowMode=%d\n", pVM->pgm.s.enmShadowMode));
1405 return ~0;
1406 }
1407}
1408
1409
1410/**
1411 * Gets the CR3 register value for the 32-Bit intermediate memory context.
1412 * @returns CR3 value.
1413 * @param pVM The VM handle.
1414 */
1415VMMDECL(RTHCPHYS) PGMGetInter32BitCR3(PVM pVM)
1416{
1417 return pVM->pgm.s.HCPhysInterPD;
1418}
1419
1420
1421/**
1422 * Gets the CR3 register value for the PAE intermediate memory context.
1423 * @returns CR3 value.
1424 * @param pVM The VM handle.
1425 */
1426VMMDECL(RTHCPHYS) PGMGetInterPaeCR3(PVM pVM)
1427{
1428 return pVM->pgm.s.HCPhysInterPaePDPT;
1429}
1430
1431
1432/**
1433 * Gets the CR3 register value for the AMD64 intermediate memory context.
1434 * @returns CR3 value.
1435 * @param pVM The VM handle.
1436 */
1437VMMDECL(RTHCPHYS) PGMGetInterAmd64CR3(PVM pVM)
1438{
1439 return pVM->pgm.s.HCPhysInterPaePML4;
1440}
1441
1442
1443/**
1444 * Performs and schedules necessary updates following a CR3 load or reload.
1445 *
1446 * This will normally involve mapping the guest PD or nPDPT
1447 *
1448 * @returns VBox status code.
1449 * @retval VINF_PGM_SYNC_CR3 if monitoring requires a CR3 sync. This can
1450 * safely be ignored and overridden since the FF will be set too then.
1451 * @param pVM VM handle.
1452 * @param cr3 The new cr3.
1453 * @param fGlobal Indicates whether this is a global flush or not.
1454 */
1455VMMDECL(int) PGMFlushTLB(PVM pVM, uint64_t cr3, bool fGlobal)
1456{
1457 STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,FlushTLB), a);
1458
1459 /*
1460 * Always flag the necessary updates; necessary for hardware acceleration
1461 */
1462 VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
1463 if (fGlobal)
1464 VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
1465 LogFlow(("PGMFlushTLB: cr3=%RX64 OldCr3=%RX64 fGlobal=%d\n", cr3, pVM->pgm.s.GCPhysCR3, fGlobal));
1466
1467 /*
1468 * Remap the CR3 content and adjust the monitoring if CR3 was actually changed.
1469 */
1470 int rc = VINF_SUCCESS;
1471 RTGCPHYS GCPhysCR3;
1472 if ( pVM->pgm.s.enmGuestMode == PGMMODE_PAE
1473 || pVM->pgm.s.enmGuestMode == PGMMODE_PAE_NX
1474 || pVM->pgm.s.enmGuestMode == PGMMODE_AMD64
1475 || pVM->pgm.s.enmGuestMode == PGMMODE_AMD64_NX)
1476 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAE_PAGE_MASK);
1477 else
1478 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAGE_MASK);
1479 if (pVM->pgm.s.GCPhysCR3 != GCPhysCR3)
1480 {
1481 pVM->pgm.s.GCPhysCR3 = GCPhysCR3;
1482 rc = PGM_GST_PFN(MapCR3, pVM)(pVM, GCPhysCR3);
1483 if (RT_SUCCESS(rc) && !pVM->pgm.s.fMappingsFixed)
1484 {
1485 pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
1486 rc = PGM_GST_PFN(MonitorCR3, pVM)(pVM, GCPhysCR3);
1487 }
1488 if (fGlobal)
1489 STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,FlushTLBNewCR3Global));
1490 else
1491 STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,FlushTLBNewCR3));
1492 }
1493 else
1494 {
1495 /*
1496 * Check if we have a pending update of the CR3 monitoring.
1497 */
1498 if (pVM->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
1499 {
1500 pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
1501 Assert(!pVM->pgm.s.fMappingsFixed);
1502 rc = PGM_GST_PFN(MonitorCR3, pVM)(pVM, GCPhysCR3);
1503 }
1504 if (fGlobal)
1505 STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,FlushTLBSameCR3Global));
1506 else
1507 STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,FlushTLBSameCR3));
1508 }
1509
1510 STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,FlushTLB), a);
1511 return rc;
1512}
1513
1514
1515/**
1516 * Performs and schedules necessary updates following a CR3 load or reload when
1517 * using nested or extended paging.
1518 *
1519 * This API is an alterantive to PDMFlushTLB that avoids actually flushing the
1520 * TLB and triggering a SyncCR3.
1521 *
1522 * This will normally involve mapping the guest PD or nPDPT
1523 *
1524 * @returns VBox status code.
1525 * @retval VINF_PGM_SYNC_CR3 if monitoring requires a CR3 sync. This can
1526 * safely be ignored and overridden since the FF will be set too then.
1527 * @param pVM VM handle.
1528 * @param cr3 The new cr3.
1529 */
1530VMMDECL(int) PGMUpdateCR3(PVM pVM, uint64_t cr3)
1531{
1532 LogFlow(("PGMUpdateCR3: cr3=%RX64 OldCr3=%RX64\n", cr3, pVM->pgm.s.GCPhysCR3));
1533
1534 /* We assume we're only called in nested paging mode. */
1535 Assert(pVM->pgm.s.fMappingsFixed);
1536 Assert(!(pVM->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3));
1537 Assert(pVM->pgm.s.enmShadowMode == PGMMODE_NESTED || pVM->pgm.s.enmShadowMode == PGMMODE_EPT);
1538
1539 /*
1540 * Remap the CR3 content and adjust the monitoring if CR3 was actually changed.
1541 */
1542 int rc = VINF_SUCCESS;
1543 RTGCPHYS GCPhysCR3;
1544 if ( pVM->pgm.s.enmGuestMode == PGMMODE_PAE
1545 || pVM->pgm.s.enmGuestMode == PGMMODE_PAE_NX
1546 || pVM->pgm.s.enmGuestMode == PGMMODE_AMD64
1547 || pVM->pgm.s.enmGuestMode == PGMMODE_AMD64_NX)
1548 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAE_PAGE_MASK);
1549 else
1550 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAGE_MASK);
1551 if (pVM->pgm.s.GCPhysCR3 != GCPhysCR3)
1552 {
1553 pVM->pgm.s.GCPhysCR3 = GCPhysCR3;
1554 rc = PGM_GST_PFN(MapCR3, pVM)(pVM, GCPhysCR3);
1555 }
1556 AssertRC(rc);
1557 return rc;
1558}
1559
1560
1561/**
1562 * Synchronize the paging structures.
1563 *
1564 * This function is called in response to the VM_FF_PGM_SYNC_CR3 and
1565 * VM_FF_PGM_SYNC_CR3_NONGLOBAL. Those two force action flags are set
1566 * in several places, most importantly whenever the CR3 is loaded.
1567 *
1568 * @returns VBox status code.
1569 * @param pVM The virtual machine.
1570 * @param cr0 Guest context CR0 register
1571 * @param cr3 Guest context CR3 register
1572 * @param cr4 Guest context CR4 register
1573 * @param fGlobal Including global page directories or not
1574 */
1575VMMDECL(int) PGMSyncCR3(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
1576{
1577 /*
1578 * We might be called when we shouldn't.
1579 *
1580 * The mode switching will ensure that the PD is resynced
1581 * after every mode switch. So, if we find ourselves here
1582 * when in protected or real mode we can safely disable the
1583 * FF and return immediately.
1584 */
1585 if (pVM->pgm.s.enmGuestMode <= PGMMODE_PROTECTED)
1586 {
1587 Assert((cr0 & (X86_CR0_PG | X86_CR0_PE)) != (X86_CR0_PG | X86_CR0_PE));
1588 VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3);
1589 VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
1590 return VINF_SUCCESS;
1591 }
1592
1593 /* If global pages are not supported, then all flushes are global */
1594 if (!(cr4 & X86_CR4_PGE))
1595 fGlobal = true;
1596 LogFlow(("PGMSyncCR3: cr0=%RX64 cr3=%RX64 cr4=%RX64 fGlobal=%d[%d,%d]\n", cr0, cr3, cr4, fGlobal,
1597 VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3), VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL)));
1598
1599 /*
1600 * Let the 'Bth' function do the work and we'll just keep track of the flags.
1601 */
1602 STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3), a);
1603 int rc = PGM_BTH_PFN(SyncCR3, pVM)(pVM, cr0, cr3, cr4, fGlobal);
1604 STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3), a);
1605 AssertMsg(rc == VINF_SUCCESS || rc == VINF_PGM_SYNC_CR3 || RT_FAILURE(rc), ("rc=%Rrc\n", rc));
1606 if (rc == VINF_SUCCESS)
1607 {
1608 if (!(pVM->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS))
1609 {
1610 VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3);
1611 VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
1612 }
1613
1614 /*
1615 * Check if we have a pending update of the CR3 monitoring.
1616 */
1617 if (pVM->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
1618 {
1619 pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
1620 Assert(!pVM->pgm.s.fMappingsFixed);
1621 Assert(pVM->pgm.s.GCPhysCR3 == pVM->pgm.s.GCPhysGstCR3Monitored);
1622 rc = PGM_GST_PFN(MonitorCR3, pVM)(pVM, pVM->pgm.s.GCPhysCR3);
1623 }
1624 }
1625
1626 /*
1627 * Now flush the CR3 (guest context).
1628 */
1629 if (rc == VINF_SUCCESS)
1630 PGM_INVL_GUEST_TLBS();
1631 return rc;
1632}
1633
1634
1635/**
1636 * Called whenever CR0 or CR4 in a way which may change
1637 * the paging mode.
1638 *
1639 * @returns VBox status code fit for scheduling in GC and R0.
1640 * @retval VINF_SUCCESS if the was no change, or it was successfully dealt with.
1641 * @retval VINF_PGM_CHANGE_MODE if we're in GC or R0 and the mode changes.
1642 * @param pVM VM handle.
1643 * @param cr0 The new cr0.
1644 * @param cr4 The new cr4.
1645 * @param efer The new extended feature enable register.
1646 */
1647VMMDECL(int) PGMChangeMode(PVM pVM, uint64_t cr0, uint64_t cr4, uint64_t efer)
1648{
1649 PGMMODE enmGuestMode;
1650
1651 /*
1652 * Calc the new guest mode.
1653 */
1654 if (!(cr0 & X86_CR0_PE))
1655 enmGuestMode = PGMMODE_REAL;
1656 else if (!(cr0 & X86_CR0_PG))
1657 enmGuestMode = PGMMODE_PROTECTED;
1658 else if (!(cr4 & X86_CR4_PAE))
1659 enmGuestMode = PGMMODE_32_BIT;
1660 else if (!(efer & MSR_K6_EFER_LME))
1661 {
1662 if (!(efer & MSR_K6_EFER_NXE))
1663 enmGuestMode = PGMMODE_PAE;
1664 else
1665 enmGuestMode = PGMMODE_PAE_NX;
1666 }
1667 else
1668 {
1669 if (!(efer & MSR_K6_EFER_NXE))
1670 enmGuestMode = PGMMODE_AMD64;
1671 else
1672 enmGuestMode = PGMMODE_AMD64_NX;
1673 }
1674
1675 /*
1676 * Did it change?
1677 */
1678 if (pVM->pgm.s.enmGuestMode == enmGuestMode)
1679 return VINF_SUCCESS;
1680
1681 /* Flush the TLB */
1682 PGM_INVL_GUEST_TLBS();
1683
1684#ifdef IN_RING3
1685 return PGMR3ChangeMode(pVM, enmGuestMode);
1686#else
1687 LogFlow(("PGMChangeMode: returns VINF_PGM_CHANGE_MODE.\n"));
1688 return VINF_PGM_CHANGE_MODE;
1689#endif
1690}
1691
1692
1693/**
1694 * Gets the current guest paging mode.
1695 *
1696 * If you just need the CPU mode (real/protected/long), use CPUMGetGuestMode().
1697 *
1698 * @returns The current paging mode.
1699 * @param pVM The VM handle.
1700 */
1701VMMDECL(PGMMODE) PGMGetGuestMode(PVM pVM)
1702{
1703 return pVM->pgm.s.enmGuestMode;
1704}
1705
1706
1707/**
1708 * Gets the current shadow paging mode.
1709 *
1710 * @returns The current paging mode.
1711 * @param pVM The VM handle.
1712 */
1713VMMDECL(PGMMODE) PGMGetShadowMode(PVM pVM)
1714{
1715 return pVM->pgm.s.enmShadowMode;
1716}
1717
1718/**
1719 * Gets the current host paging mode.
1720 *
1721 * @returns The current paging mode.
1722 * @param pVM The VM handle.
1723 */
1724VMMDECL(PGMMODE) PGMGetHostMode(PVM pVM)
1725{
1726 switch (pVM->pgm.s.enmHostMode)
1727 {
1728 case SUPPAGINGMODE_32_BIT:
1729 case SUPPAGINGMODE_32_BIT_GLOBAL:
1730 return PGMMODE_32_BIT;
1731
1732 case SUPPAGINGMODE_PAE:
1733 case SUPPAGINGMODE_PAE_GLOBAL:
1734 return PGMMODE_PAE;
1735
1736 case SUPPAGINGMODE_PAE_NX:
1737 case SUPPAGINGMODE_PAE_GLOBAL_NX:
1738 return PGMMODE_PAE_NX;
1739
1740 case SUPPAGINGMODE_AMD64:
1741 case SUPPAGINGMODE_AMD64_GLOBAL:
1742 return PGMMODE_AMD64;
1743
1744 case SUPPAGINGMODE_AMD64_NX:
1745 case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1746 return PGMMODE_AMD64_NX;
1747
1748 default: AssertMsgFailed(("enmHostMode=%d\n", pVM->pgm.s.enmHostMode)); break;
1749 }
1750
1751 return PGMMODE_INVALID;
1752}
1753
1754
1755/**
1756 * Get mode name.
1757 *
1758 * @returns read-only name string.
1759 * @param enmMode The mode which name is desired.
1760 */
1761VMMDECL(const char *) PGMGetModeName(PGMMODE enmMode)
1762{
1763 switch (enmMode)
1764 {
1765 case PGMMODE_REAL: return "Real";
1766 case PGMMODE_PROTECTED: return "Protected";
1767 case PGMMODE_32_BIT: return "32-bit";
1768 case PGMMODE_PAE: return "PAE";
1769 case PGMMODE_PAE_NX: return "PAE+NX";
1770 case PGMMODE_AMD64: return "AMD64";
1771 case PGMMODE_AMD64_NX: return "AMD64+NX";
1772 case PGMMODE_NESTED: return "Nested";
1773 case PGMMODE_EPT: return "EPT";
1774 default: return "unknown mode value";
1775 }
1776}
1777
1778
1779/**
1780 * Acquire the PGM lock.
1781 *
1782 * @returns VBox status code
1783 * @param pVM The VM to operate on.
1784 */
1785int pgmLock(PVM pVM)
1786{
1787 int rc = PDMCritSectEnter(&pVM->pgm.s.CritSect, VERR_SEM_BUSY);
1788#ifdef IN_RC
1789 if (rc == VERR_SEM_BUSY)
1790 rc = VMMGCCallHost(pVM, VMMCALLHOST_PGM_LOCK, 0);
1791#elif defined(IN_RING0)
1792 if (rc == VERR_SEM_BUSY)
1793 rc = VMMR0CallHost(pVM, VMMCALLHOST_PGM_LOCK, 0);
1794#endif
1795 AssertRC(rc);
1796 return rc;
1797}
1798
1799
1800/**
1801 * Release the PGM lock.
1802 *
1803 * @returns VBox status code
1804 * @param pVM The VM to operate on.
1805 */
1806void pgmUnlock(PVM pVM)
1807{
1808 PDMCritSectLeave(&pVM->pgm.s.CritSect);
1809}
1810
1811#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1812
1813/**
1814 * Temporarily maps one guest page specified by GC physical address.
1815 * These pages must have a physical mapping in HC, i.e. they cannot be MMIO pages.
1816 *
1817 * Be WARNED that the dynamic page mapping area is small, 8 pages, thus the space is
1818 * reused after 8 mappings (or perhaps a few more if you score with the cache).
1819 *
1820 * @returns VBox status.
1821 * @param pVM VM handle.
1822 * @param GCPhys GC Physical address of the page.
1823 * @param ppv Where to store the address of the mapping.
1824 */
1825VMMDECL(int) PGMDynMapGCPage(PVM pVM, RTGCPHYS GCPhys, void **ppv)
1826{
1827 AssertMsg(!(GCPhys & PAGE_OFFSET_MASK), ("GCPhys=%RGp\n", GCPhys));
1828
1829 /*
1830 * Get the ram range.
1831 */
1832 PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
1833 while (pRam && GCPhys - pRam->GCPhys >= pRam->cb)
1834 pRam = pRam->CTX_SUFF(pNext);
1835 if (!pRam)
1836 {
1837 AssertMsgFailed(("Invalid physical address %RGp!\n", GCPhys));
1838 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
1839 }
1840
1841 /*
1842 * Pass it on to PGMDynMapHCPage.
1843 */
1844 RTHCPHYS HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT]);
1845 //Log(("PGMDynMapGCPage: GCPhys=%RGp HCPhys=%RHp\n", GCPhys, HCPhys));
1846 return PGMDynMapHCPage(pVM, HCPhys, ppv);
1847}
1848
1849
1850/**
1851 * Temporarily maps one guest page specified by unaligned GC physical address.
1852 * These pages must have a physical mapping in HC, i.e. they cannot be MMIO pages.
1853 *
1854 * Be WARNED that the dynamic page mapping area is small, 8 pages, thus the space is
1855 * reused after 8 mappings (or perhaps a few more if you score with the cache).
1856 *
1857 * The caller is aware that only the speicifed page is mapped and that really bad things
1858 * will happen if writing beyond the page!
1859 *
1860 * @returns VBox status.
1861 * @param pVM VM handle.
1862 * @param GCPhys GC Physical address within the page to be mapped.
1863 * @param ppv Where to store the address of the mapping address corresponding to GCPhys.
1864 */
1865VMMDECL(int) PGMDynMapGCPageOff(PVM pVM, RTGCPHYS GCPhys, void **ppv)
1866{
1867 /*
1868 * Get the ram range.
1869 */
1870 PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
1871 while (pRam && GCPhys - pRam->GCPhys >= pRam->cb)
1872 pRam = pRam->CTX_SUFF(pNext);
1873 if (!pRam)
1874 {
1875 AssertMsgFailed(("Invalid physical address %RGp!\n", GCPhys));
1876 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
1877 }
1878
1879 /*
1880 * Pass it on to PGMDynMapHCPage.
1881 */
1882 RTHCPHYS HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT]);
1883 int rc = PGMDynMapHCPage(pVM, HCPhys, ppv);
1884 if (RT_SUCCESS(rc))
1885 *ppv = (void *)((uintptr_t)*ppv | (GCPhys & PAGE_OFFSET_MASK));
1886 return rc;
1887}
1888
1889
1890/**
1891 * Temporarily maps one host page specified by HC physical address.
1892 *
1893 * Be WARNED that the dynamic page mapping area is small, 8 pages, thus the space is
1894 * reused after 8 mappings (or perhaps a few more if you score with the cache).
1895 *
1896 * @returns VBox status.
1897 * @param pVM VM handle.
1898 * @param HCPhys HC Physical address of the page.
1899 * @param ppv Where to store the address of the mapping. This is the
1900 * address of the PAGE not the exact address corresponding
1901 * to HCPhys. Use PGMDynMapHCPageOff if you care for the
1902 * page offset.
1903 */
1904VMMDECL(int) PGMDynMapHCPage(PVM pVM, RTHCPHYS HCPhys, void **ppv)
1905{
1906 AssertMsg(!(HCPhys & PAGE_OFFSET_MASK), ("HCPhys=%RHp\n", HCPhys));
1907# ifdef IN_RC
1908
1909 /*
1910 * Check the cache.
1911 */
1912 register unsigned iCache;
1913 if ( pVM->pgm.s.aHCPhysDynPageMapCache[iCache = 0] == HCPhys
1914 || pVM->pgm.s.aHCPhysDynPageMapCache[iCache = 1] == HCPhys
1915 || pVM->pgm.s.aHCPhysDynPageMapCache[iCache = 2] == HCPhys
1916 || pVM->pgm.s.aHCPhysDynPageMapCache[iCache = 3] == HCPhys)
1917 {
1918 static const uint8_t au8Trans[MM_HYPER_DYNAMIC_SIZE >> PAGE_SHIFT][RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache)] =
1919 {
1920 { 0, 5, 6, 7 },
1921 { 0, 1, 6, 7 },
1922 { 0, 1, 2, 7 },
1923 { 0, 1, 2, 3 },
1924 { 4, 1, 2, 3 },
1925 { 4, 5, 2, 3 },
1926 { 4, 5, 6, 3 },
1927 { 4, 5, 6, 7 },
1928 };
1929 Assert(RT_ELEMENTS(au8Trans) == 8);
1930 Assert(RT_ELEMENTS(au8Trans[0]) == 4);
1931 int iPage = au8Trans[pVM->pgm.s.iDynPageMapLast][iCache];
1932 void *pv = pVM->pgm.s.pbDynPageMapBaseGC + (iPage << PAGE_SHIFT);
1933 *ppv = pv;
1934 STAM_COUNTER_INC(&pVM->pgm.s.StatRCDynMapCacheHits);
1935 //Log(("PGMGCDynMapHCPage: HCPhys=%RHp pv=%p iPage=%d iCache=%d\n", HCPhys, pv, iPage, iCache));
1936 return VINF_SUCCESS;
1937 }
1938 Assert(RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache) == 4);
1939 STAM_COUNTER_INC(&pVM->pgm.s.StatRCDynMapCacheMisses);
1940
1941 /*
1942 * Update the page tables.
1943 */
1944 register unsigned iPage = pVM->pgm.s.iDynPageMapLast;
1945 pVM->pgm.s.iDynPageMapLast = iPage = (iPage + 1) & ((MM_HYPER_DYNAMIC_SIZE >> PAGE_SHIFT) - 1);
1946 Assert((MM_HYPER_DYNAMIC_SIZE >> PAGE_SHIFT) == 8);
1947
1948 pVM->pgm.s.aHCPhysDynPageMapCache[iPage & (RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache) - 1)] = HCPhys;
1949 pVM->pgm.s.paDynPageMap32BitPTEsGC[iPage].u = (uint32_t)HCPhys | X86_PTE_P | X86_PTE_A | X86_PTE_D;
1950 pVM->pgm.s.paDynPageMapPaePTEsGC[iPage].u = HCPhys | X86_PTE_P | X86_PTE_A | X86_PTE_D;
1951
1952 void *pv = pVM->pgm.s.pbDynPageMapBaseGC + (iPage << PAGE_SHIFT);
1953 *ppv = pv;
1954 ASMInvalidatePage(pv);
1955 Log4(("PGMGCDynMapHCPage: HCPhys=%RHp pv=%p iPage=%d\n", HCPhys, pv, iPage));
1956 return VINF_SUCCESS;
1957
1958#else /* VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
1959 /** @todo @bugref{3202}: Implement ring-0 mapping cache similar to the one in
1960 * RC. To begin with, a simple but expensive one based on
1961 * RTR0MemObjEnterPhys can be used to get things started. Later a
1962 * global cache with mappings per CPU (to avoid shootdown) should be
1963 * employed. */
1964 AssertFailed();
1965 return VERR_NOT_IMPLEMENTED;
1966#endif /* VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
1967}
1968
1969
1970/**
1971 * Temporarily maps one host page specified by HC physical address, returning
1972 * pointer within the page.
1973 *
1974 * Be WARNED that the dynamic page mapping area is small, 8 pages, thus the space is
1975 * reused after 8 mappings (or perhaps a few more if you score with the cache).
1976 *
1977 * @returns VBox status.
1978 * @param pVM VM handle.
1979 * @param HCPhys HC Physical address of the page.
1980 * @param ppv Where to store the address corresponding to HCPhys.
1981 */
1982VMMDECL(int) PGMDynMapHCPageOff(PVM pVM, RTHCPHYS HCPhys, void **ppv)
1983{
1984 int rc = PGMDynMapHCPage(pVM, HCPhys & ~(RTHCPHYS)PAGE_OFFSET_MASK, ppv);
1985 if (RT_SUCCESS(rc))
1986 *ppv = (void *)((uintptr_t)*ppv | (HCPhys & PAGE_OFFSET_MASK));
1987 return rc;
1988}
1989
1990#endif /* IN_RC || VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
1991#ifdef VBOX_STRICT
1992
1993/**
1994 * Asserts that there are no mapping conflicts.
1995 *
1996 * @returns Number of conflicts.
1997 * @param pVM The VM Handle.
1998 */
1999VMMDECL(unsigned) PGMAssertNoMappingConflicts(PVM pVM)
2000{
2001 unsigned cErrors = 0;
2002
2003 /*
2004 * Check for mapping conflicts.
2005 */
2006 for (PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
2007 pMapping;
2008 pMapping = pMapping->CTX_SUFF(pNext))
2009 {
2010 /** @todo This is slow and should be optimized, but since it's just assertions I don't care now. */
2011 for (RTGCPTR GCPtr = pMapping->GCPtr;
2012 GCPtr <= pMapping->GCPtrLast;
2013 GCPtr += PAGE_SIZE)
2014 {
2015 int rc = PGMGstGetPage(pVM, (RTGCPTR)GCPtr, NULL, NULL);
2016 if (rc != VERR_PAGE_TABLE_NOT_PRESENT)
2017 {
2018 AssertMsgFailed(("Conflict at %RGv with %s\n", GCPtr, R3STRING(pMapping->pszDesc)));
2019 cErrors++;
2020 break;
2021 }
2022 }
2023 }
2024
2025 return cErrors;
2026}
2027
2028
2029/**
2030 * Asserts that everything related to the guest CR3 is correctly shadowed.
2031 *
2032 * This will call PGMAssertNoMappingConflicts() and PGMAssertHandlerAndFlagsInSync(),
2033 * and assert the correctness of the guest CR3 mapping before asserting that the
2034 * shadow page tables is in sync with the guest page tables.
2035 *
2036 * @returns Number of conflicts.
2037 * @param pVM The VM Handle.
2038 * @param cr3 The current guest CR3 register value.
2039 * @param cr4 The current guest CR4 register value.
2040 */
2041VMMDECL(unsigned) PGMAssertCR3(PVM pVM, uint64_t cr3, uint64_t cr4)
2042{
2043 STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3), a);
2044 unsigned cErrors = PGM_BTH_PFN(AssertCR3, pVM)(pVM, cr3, cr4, 0, ~(RTGCPTR)0);
2045 STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3), a);
2046 return cErrors;
2047 return 0;
2048}
2049
2050#endif /* VBOX_STRICT */
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