VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAll.cpp@ 15911

Last change on this file since 15911 was 15425, checked in by vboxsync, 16 years ago

PGMR0DynMapHCPage: always successful, or will bail out to ring-3.
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1/* $Id: PGMAll.cpp 15425 2008-12-13 09:22:59Z vboxsync $ */
2/** @file
3 * PGM - Page Manager and Monitor - All context code.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22/*******************************************************************************
23* Header Files *
24*******************************************************************************/
25#define LOG_GROUP LOG_GROUP_PGM
26#include <VBox/pgm.h>
27#include <VBox/cpum.h>
28#include <VBox/selm.h>
29#include <VBox/iom.h>
30#include <VBox/sup.h>
31#include <VBox/mm.h>
32#include <VBox/stam.h>
33#include <VBox/csam.h>
34#include <VBox/patm.h>
35#include <VBox/trpm.h>
36#include <VBox/rem.h>
37#include <VBox/em.h>
38#include <VBox/hwaccm.h>
39#include <VBox/hwacc_vmx.h>
40#include "PGMInternal.h"
41#include <VBox/vm.h>
42#include <iprt/assert.h>
43#include <iprt/asm.h>
44#include <iprt/string.h>
45#include <VBox/log.h>
46#include <VBox/param.h>
47#include <VBox/err.h>
48
49
50/*******************************************************************************
51* Structures and Typedefs *
52*******************************************************************************/
53/**
54 * Stated structure for PGM_GST_NAME(HandlerVirtualUpdate) that's
55 * passed to PGM_GST_NAME(VirtHandlerUpdateOne) during enumeration.
56 */
57typedef struct PGMHVUSTATE
58{
59 /** The VM handle. */
60 PVM pVM;
61 /** The todo flags. */
62 RTUINT fTodo;
63 /** The CR4 register value. */
64 uint32_t cr4;
65} PGMHVUSTATE, *PPGMHVUSTATE;
66
67
68/*******************************************************************************
69* Internal Functions *
70*******************************************************************************/
71DECLINLINE(int) pgmShwGetLongModePDPtr(PVM pVM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPT *ppPdpt, PX86PDPAE *ppPD);
72DECLINLINE(int) pgmShwSyncLongModePDPtr(PVM pVM, RTGCPTR64 GCPtr, PX86PML4E pGstPml4e, PX86PDPE pGstPdpe, PX86PDPAE *ppPD);
73DECLINLINE(int) pgmShwGetEPTPDPtr(PVM pVM, RTGCPTR64 GCPtr, PEPTPDPT *ppPdpt, PEPTPD *ppPD);
74DECLINLINE(int) pgmShwSyncPAEPDPtr(PVM pVM, RTGCPTR GCPtr, PX86PDPE pGstPdpe, PX86PDPAE *ppPD);
75DECLINLINE(int) pgmShwGetPAEPDPtr(PVM pVM, RTGCPTR GCPtr, PX86PDPT *ppPdpt, PX86PDPAE *ppPD);
76
77
78/*
79 * Shadow - 32-bit mode
80 */
81#define PGM_SHW_TYPE PGM_TYPE_32BIT
82#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
83#include "PGMAllShw.h"
84
85/* Guest - real mode */
86#define PGM_GST_TYPE PGM_TYPE_REAL
87#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
88#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
89#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
90#include "PGMAllGst.h"
91#include "PGMAllBth.h"
92#undef BTH_PGMPOOLKIND_PT_FOR_PT
93#undef PGM_BTH_NAME
94#undef PGM_GST_TYPE
95#undef PGM_GST_NAME
96
97/* Guest - protected mode */
98#define PGM_GST_TYPE PGM_TYPE_PROT
99#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
100#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
101#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
102#include "PGMAllGst.h"
103#include "PGMAllBth.h"
104#undef BTH_PGMPOOLKIND_PT_FOR_PT
105#undef PGM_BTH_NAME
106#undef PGM_GST_TYPE
107#undef PGM_GST_NAME
108
109/* Guest - 32-bit mode */
110#define PGM_GST_TYPE PGM_TYPE_32BIT
111#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
112#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
113#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
114#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
115#include "PGMAllGst.h"
116#include "PGMAllBth.h"
117#undef BTH_PGMPOOLKIND_PT_FOR_BIG
118#undef BTH_PGMPOOLKIND_PT_FOR_PT
119#undef PGM_BTH_NAME
120#undef PGM_GST_TYPE
121#undef PGM_GST_NAME
122
123#undef PGM_SHW_TYPE
124#undef PGM_SHW_NAME
125
126
127/*
128 * Shadow - PAE mode
129 */
130#define PGM_SHW_TYPE PGM_TYPE_PAE
131#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
132#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
133#include "PGMAllShw.h"
134
135/* Guest - real mode */
136#define PGM_GST_TYPE PGM_TYPE_REAL
137#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
138#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
139#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
140#include "PGMAllBth.h"
141#undef BTH_PGMPOOLKIND_PT_FOR_PT
142#undef PGM_BTH_NAME
143#undef PGM_GST_TYPE
144#undef PGM_GST_NAME
145
146/* Guest - protected mode */
147#define PGM_GST_TYPE PGM_TYPE_PROT
148#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
149#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
150#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
151#include "PGMAllBth.h"
152#undef BTH_PGMPOOLKIND_PT_FOR_PT
153#undef PGM_BTH_NAME
154#undef PGM_GST_TYPE
155#undef PGM_GST_NAME
156
157/* Guest - 32-bit mode */
158#define PGM_GST_TYPE PGM_TYPE_32BIT
159#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
160#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
161#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
162#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
163#include "PGMAllBth.h"
164#undef BTH_PGMPOOLKIND_PT_FOR_BIG
165#undef BTH_PGMPOOLKIND_PT_FOR_PT
166#undef PGM_BTH_NAME
167#undef PGM_GST_TYPE
168#undef PGM_GST_NAME
169
170
171/* Guest - PAE mode */
172#define PGM_GST_TYPE PGM_TYPE_PAE
173#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
174#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
175#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
176#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
177#include "PGMAllGst.h"
178#include "PGMAllBth.h"
179#undef BTH_PGMPOOLKIND_PT_FOR_BIG
180#undef BTH_PGMPOOLKIND_PT_FOR_PT
181#undef PGM_BTH_NAME
182#undef PGM_GST_TYPE
183#undef PGM_GST_NAME
184
185#undef PGM_SHW_TYPE
186#undef PGM_SHW_NAME
187
188
189#ifndef IN_RC /* AMD64 implies VT-x/AMD-V */
190/*
191 * Shadow - AMD64 mode
192 */
193# define PGM_SHW_TYPE PGM_TYPE_AMD64
194# define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
195# include "PGMAllShw.h"
196
197/* Guest - protected mode */
198# define PGM_GST_TYPE PGM_TYPE_PROT
199# define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
200# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_PROT(name)
201# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
202# include "PGMAllBth.h"
203# undef BTH_PGMPOOLKIND_PT_FOR_PT
204# undef PGM_BTH_NAME
205# undef PGM_GST_TYPE
206# undef PGM_GST_NAME
207
208# ifdef VBOX_WITH_64_BITS_GUESTS
209/* Guest - AMD64 mode */
210# define PGM_GST_TYPE PGM_TYPE_AMD64
211# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
212# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
213# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
214# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
215# include "PGMAllGst.h"
216# include "PGMAllBth.h"
217# undef BTH_PGMPOOLKIND_PT_FOR_BIG
218# undef BTH_PGMPOOLKIND_PT_FOR_PT
219# undef PGM_BTH_NAME
220# undef PGM_GST_TYPE
221# undef PGM_GST_NAME
222# endif /* VBOX_WITH_64_BITS_GUESTS */
223
224# undef PGM_SHW_TYPE
225# undef PGM_SHW_NAME
226
227
228/*
229 * Shadow - Nested paging mode
230 */
231# define PGM_SHW_TYPE PGM_TYPE_NESTED
232# define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED(name)
233# include "PGMAllShw.h"
234
235/* Guest - real mode */
236# define PGM_GST_TYPE PGM_TYPE_REAL
237# define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
238# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_REAL(name)
239# include "PGMAllBth.h"
240# undef PGM_BTH_NAME
241# undef PGM_GST_TYPE
242# undef PGM_GST_NAME
243
244/* Guest - protected mode */
245# define PGM_GST_TYPE PGM_TYPE_PROT
246# define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
247# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PROT(name)
248# include "PGMAllBth.h"
249# undef PGM_BTH_NAME
250# undef PGM_GST_TYPE
251# undef PGM_GST_NAME
252
253/* Guest - 32-bit mode */
254# define PGM_GST_TYPE PGM_TYPE_32BIT
255# define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
256# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT(name)
257# include "PGMAllBth.h"
258# undef PGM_BTH_NAME
259# undef PGM_GST_TYPE
260# undef PGM_GST_NAME
261
262/* Guest - PAE mode */
263# define PGM_GST_TYPE PGM_TYPE_PAE
264# define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
265# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE(name)
266# include "PGMAllBth.h"
267# undef PGM_BTH_NAME
268# undef PGM_GST_TYPE
269# undef PGM_GST_NAME
270
271# ifdef VBOX_WITH_64_BITS_GUESTS
272/* Guest - AMD64 mode */
273# define PGM_GST_TYPE PGM_TYPE_AMD64
274# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
275# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64(name)
276# include "PGMAllBth.h"
277# undef PGM_BTH_NAME
278# undef PGM_GST_TYPE
279# undef PGM_GST_NAME
280# endif /* VBOX_WITH_64_BITS_GUESTS */
281
282# undef PGM_SHW_TYPE
283# undef PGM_SHW_NAME
284
285
286/*
287 * Shadow - EPT
288 */
289# define PGM_SHW_TYPE PGM_TYPE_EPT
290# define PGM_SHW_NAME(name) PGM_SHW_NAME_EPT(name)
291# include "PGMAllShw.h"
292
293/* Guest - real mode */
294# define PGM_GST_TYPE PGM_TYPE_REAL
295# define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
296# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_REAL(name)
297# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
298# include "PGMAllBth.h"
299# undef BTH_PGMPOOLKIND_PT_FOR_PT
300# undef PGM_BTH_NAME
301# undef PGM_GST_TYPE
302# undef PGM_GST_NAME
303
304/* Guest - protected mode */
305# define PGM_GST_TYPE PGM_TYPE_PROT
306# define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
307# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PROT(name)
308# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
309# include "PGMAllBth.h"
310# undef BTH_PGMPOOLKIND_PT_FOR_PT
311# undef PGM_BTH_NAME
312# undef PGM_GST_TYPE
313# undef PGM_GST_NAME
314
315/* Guest - 32-bit mode */
316# define PGM_GST_TYPE PGM_TYPE_32BIT
317# define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
318# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_32BIT(name)
319# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
320# include "PGMAllBth.h"
321# undef BTH_PGMPOOLKIND_PT_FOR_PT
322# undef PGM_BTH_NAME
323# undef PGM_GST_TYPE
324# undef PGM_GST_NAME
325
326/* Guest - PAE mode */
327# define PGM_GST_TYPE PGM_TYPE_PAE
328# define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
329# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PAE(name)
330# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
331# include "PGMAllBth.h"
332# undef BTH_PGMPOOLKIND_PT_FOR_PT
333# undef PGM_BTH_NAME
334# undef PGM_GST_TYPE
335# undef PGM_GST_NAME
336
337# ifdef VBOX_WITH_64_BITS_GUESTS
338/* Guest - AMD64 mode */
339# define PGM_GST_TYPE PGM_TYPE_AMD64
340# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
341# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_AMD64(name)
342# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
343# include "PGMAllBth.h"
344# undef BTH_PGMPOOLKIND_PT_FOR_PT
345# undef PGM_BTH_NAME
346# undef PGM_GST_TYPE
347# undef PGM_GST_NAME
348# endif /* VBOX_WITH_64_BITS_GUESTS */
349
350# undef PGM_SHW_TYPE
351# undef PGM_SHW_NAME
352
353#endif /* !IN_RC */
354
355
356#ifndef IN_RING3
357/**
358 * #PF Handler.
359 *
360 * @returns VBox status code (appropriate for trap handling and GC return).
361 * @param pVM VM Handle.
362 * @param uErr The trap error code.
363 * @param pRegFrame Trap register frame.
364 * @param pvFault The fault address.
365 */
366VMMDECL(int) PGMTrap0eHandler(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
367{
368 LogFlow(("PGMTrap0eHandler: uErr=%RGu pvFault=%RGv eip=%RGv\n", uErr, pvFault, (RTGCPTR)pRegFrame->rip));
369 STAM_PROFILE_START(&pVM->pgm.s.StatRZTrap0e, a);
370 STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = NULL; } );
371
372
373#ifdef VBOX_WITH_STATISTICS
374 /*
375 * Error code stats.
376 */
377 if (uErr & X86_TRAP_PF_US)
378 {
379 if (!(uErr & X86_TRAP_PF_P))
380 {
381 if (uErr & X86_TRAP_PF_RW)
382 STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eUSNotPresentWrite);
383 else
384 STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eUSNotPresentRead);
385 }
386 else if (uErr & X86_TRAP_PF_RW)
387 STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eUSWrite);
388 else if (uErr & X86_TRAP_PF_RSVD)
389 STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eUSReserved);
390 else if (uErr & X86_TRAP_PF_ID)
391 STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eUSNXE);
392 else
393 STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eUSRead);
394 }
395 else
396 { /* Supervisor */
397 if (!(uErr & X86_TRAP_PF_P))
398 {
399 if (uErr & X86_TRAP_PF_RW)
400 STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eSVNotPresentWrite);
401 else
402 STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eSVNotPresentRead);
403 }
404 else if (uErr & X86_TRAP_PF_RW)
405 STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eSVWrite);
406 else if (uErr & X86_TRAP_PF_ID)
407 STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eSNXE);
408 else if (uErr & X86_TRAP_PF_RSVD)
409 STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eSVReserved);
410 }
411#endif /* VBOX_WITH_STATISTICS */
412
413 /*
414 * Call the worker.
415 */
416 int rc = PGM_BTH_PFN(Trap0eHandler, pVM)(pVM, uErr, pRegFrame, pvFault);
417 if (rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
418 rc = VINF_SUCCESS;
419 STAM_STATS({ if (rc == VINF_EM_RAW_GUEST_TRAP) STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eGuestPF); });
420 STAM_STATS({ if (!pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution))
421 pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2Misc; });
422 STAM_PROFILE_STOP_EX(&pVM->pgm.s.StatRZTrap0e, pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution), a);
423 return rc;
424}
425#endif /* !IN_RING3 */
426
427
428/**
429 * Prefetch a page
430 *
431 * Typically used to sync commonly used pages before entering raw mode
432 * after a CR3 reload.
433 *
434 * @returns VBox status code suitable for scheduling.
435 * @retval VINF_SUCCESS on success.
436 * @retval VINF_PGM_SYNC_CR3 if we're out of shadow pages or something like that.
437 * @param pVM VM handle.
438 * @param GCPtrPage Page to invalidate.
439 */
440VMMDECL(int) PGMPrefetchPage(PVM pVM, RTGCPTR GCPtrPage)
441{
442 STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,Prefetch), a);
443 int rc = PGM_BTH_PFN(PrefetchPage, pVM)(pVM, GCPtrPage);
444 STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,Prefetch), a);
445 AssertMsg(rc == VINF_SUCCESS || rc == VINF_PGM_SYNC_CR3 || RT_FAILURE(rc), ("rc=%Rrc\n", rc));
446 return rc;
447}
448
449
450/**
451 * Gets the mapping corresponding to the specified address (if any).
452 *
453 * @returns Pointer to the mapping.
454 * @returns NULL if not
455 *
456 * @param pVM The virtual machine.
457 * @param GCPtr The guest context pointer.
458 */
459PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr)
460{
461 PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
462 while (pMapping)
463 {
464 if ((uintptr_t)GCPtr < (uintptr_t)pMapping->GCPtr)
465 break;
466 if ((uintptr_t)GCPtr - (uintptr_t)pMapping->GCPtr < pMapping->cb)
467 return pMapping;
468 pMapping = pMapping->CTX_SUFF(pNext);
469 }
470 return NULL;
471}
472
473
474/**
475 * Verifies a range of pages for read or write access
476 *
477 * Only checks the guest's page tables
478 *
479 * @returns VBox status code.
480 * @param pVM VM handle.
481 * @param Addr Guest virtual address to check
482 * @param cbSize Access size
483 * @param fAccess Access type (r/w, user/supervisor (X86_PTE_*))
484 * @remarks Current not in use.
485 */
486VMMDECL(int) PGMIsValidAccess(PVM pVM, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess)
487{
488 /*
489 * Validate input.
490 */
491 if (fAccess & ~(X86_PTE_US | X86_PTE_RW))
492 {
493 AssertMsgFailed(("PGMIsValidAccess: invalid access type %08x\n", fAccess));
494 return VERR_INVALID_PARAMETER;
495 }
496
497 uint64_t fPage;
498 int rc = PGMGstGetPage(pVM, (RTGCPTR)Addr, &fPage, NULL);
499 if (RT_FAILURE(rc))
500 {
501 Log(("PGMIsValidAccess: access violation for %RGv rc=%d\n", Addr, rc));
502 return VINF_EM_RAW_GUEST_TRAP;
503 }
504
505 /*
506 * Check if the access would cause a page fault
507 *
508 * Note that hypervisor page directories are not present in the guest's tables, so this check
509 * is sufficient.
510 */
511 bool fWrite = !!(fAccess & X86_PTE_RW);
512 bool fUser = !!(fAccess & X86_PTE_US);
513 if ( !(fPage & X86_PTE_P)
514 || (fWrite && !(fPage & X86_PTE_RW))
515 || (fUser && !(fPage & X86_PTE_US)) )
516 {
517 Log(("PGMIsValidAccess: access violation for %RGv attr %#llx vs %d:%d\n", Addr, fPage, fWrite, fUser));
518 return VINF_EM_RAW_GUEST_TRAP;
519 }
520 if ( RT_SUCCESS(rc)
521 && PAGE_ADDRESS(Addr) != PAGE_ADDRESS(Addr + cbSize))
522 return PGMIsValidAccess(pVM, Addr + PAGE_SIZE, (cbSize > PAGE_SIZE) ? cbSize - PAGE_SIZE : 1, fAccess);
523 return rc;
524}
525
526
527/**
528 * Verifies a range of pages for read or write access
529 *
530 * Supports handling of pages marked for dirty bit tracking and CSAM
531 *
532 * @returns VBox status code.
533 * @param pVM VM handle.
534 * @param Addr Guest virtual address to check
535 * @param cbSize Access size
536 * @param fAccess Access type (r/w, user/supervisor (X86_PTE_*))
537 */
538VMMDECL(int) PGMVerifyAccess(PVM pVM, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess)
539{
540 AssertMsg(!(fAccess & ~(X86_PTE_US | X86_PTE_RW)), ("PGMVerifyAccess: invalid access type %08x\n", fAccess));
541
542 /*
543 * Get going.
544 */
545 uint64_t fPageGst;
546 int rc = PGMGstGetPage(pVM, (RTGCPTR)Addr, &fPageGst, NULL);
547 if (RT_FAILURE(rc))
548 {
549 Log(("PGMVerifyAccess: access violation for %RGv rc=%d\n", Addr, rc));
550 return VINF_EM_RAW_GUEST_TRAP;
551 }
552
553 /*
554 * Check if the access would cause a page fault
555 *
556 * Note that hypervisor page directories are not present in the guest's tables, so this check
557 * is sufficient.
558 */
559 const bool fWrite = !!(fAccess & X86_PTE_RW);
560 const bool fUser = !!(fAccess & X86_PTE_US);
561 if ( !(fPageGst & X86_PTE_P)
562 || (fWrite && !(fPageGst & X86_PTE_RW))
563 || (fUser && !(fPageGst & X86_PTE_US)) )
564 {
565 Log(("PGMVerifyAccess: access violation for %RGv attr %#llx vs %d:%d\n", Addr, fPageGst, fWrite, fUser));
566 return VINF_EM_RAW_GUEST_TRAP;
567 }
568
569 if (!HWACCMIsNestedPagingActive(pVM))
570 {
571 /*
572 * Next step is to verify if we protected this page for dirty bit tracking or for CSAM scanning
573 */
574 rc = PGMShwGetPage(pVM, (RTGCPTR)Addr, NULL, NULL);
575 if ( rc == VERR_PAGE_NOT_PRESENT
576 || rc == VERR_PAGE_TABLE_NOT_PRESENT)
577 {
578 /*
579 * Page is not present in our page tables.
580 * Try to sync it!
581 */
582 Assert(X86_TRAP_PF_RW == X86_PTE_RW && X86_TRAP_PF_US == X86_PTE_US);
583 uint32_t uErr = fAccess & (X86_TRAP_PF_RW | X86_TRAP_PF_US);
584 rc = PGM_BTH_PFN(VerifyAccessSyncPage, pVM)(pVM, Addr, fPageGst, uErr);
585 if (rc != VINF_SUCCESS)
586 return rc;
587 }
588 else
589 AssertMsg(rc == VINF_SUCCESS, ("PGMShwGetPage %RGv failed with %Rrc\n", Addr, rc));
590 }
591
592#if 0 /* def VBOX_STRICT; triggers too often now */
593 /*
594 * This check is a bit paranoid, but useful.
595 */
596 /** @note this will assert when writing to monitored pages (a bit annoying actually) */
597 uint64_t fPageShw;
598 rc = PGMShwGetPage(pVM, (RTGCPTR)Addr, &fPageShw, NULL);
599 if ( (rc == VERR_PAGE_NOT_PRESENT || RT_FAILURE(rc))
600 || (fWrite && !(fPageShw & X86_PTE_RW))
601 || (fUser && !(fPageShw & X86_PTE_US)) )
602 {
603 AssertMsgFailed(("Unexpected access violation for %RGv! rc=%Rrc write=%d user=%d\n",
604 Addr, rc, fWrite && !(fPageShw & X86_PTE_RW), fUser && !(fPageShw & X86_PTE_US)));
605 return VINF_EM_RAW_GUEST_TRAP;
606 }
607#endif
608
609 if ( RT_SUCCESS(rc)
610 && ( PAGE_ADDRESS(Addr) != PAGE_ADDRESS(Addr + cbSize - 1)
611 || Addr + cbSize < Addr))
612 {
613 /* Don't recursively call PGMVerifyAccess as we might run out of stack. */
614 for (;;)
615 {
616 Addr += PAGE_SIZE;
617 if (cbSize > PAGE_SIZE)
618 cbSize -= PAGE_SIZE;
619 else
620 cbSize = 1;
621 rc = PGMVerifyAccess(pVM, Addr, 1, fAccess);
622 if (rc != VINF_SUCCESS)
623 break;
624 if (PAGE_ADDRESS(Addr) == PAGE_ADDRESS(Addr + cbSize - 1))
625 break;
626 }
627 }
628 return rc;
629}
630
631
632/**
633 * Emulation of the invlpg instruction (HC only actually).
634 *
635 * @returns VBox status code, special care required.
636 * @retval VINF_PGM_SYNC_CR3 - handled.
637 * @retval VINF_EM_RAW_EMULATE_INSTR - not handled (RC only).
638 * @retval VERR_REM_FLUSHED_PAGES_OVERFLOW - not handled.
639 *
640 * @param pVM VM handle.
641 * @param GCPtrPage Page to invalidate.
642 *
643 * @remark ASSUMES the page table entry or page directory is valid. Fairly
644 * safe, but there could be edge cases!
645 *
646 * @todo Flush page or page directory only if necessary!
647 */
648VMMDECL(int) PGMInvalidatePage(PVM pVM, RTGCPTR GCPtrPage)
649{
650 int rc;
651 Log3(("PGMInvalidatePage: GCPtrPage=%RGv\n", GCPtrPage));
652
653#ifndef IN_RING3
654 /*
655 * Notify the recompiler so it can record this instruction.
656 * Failure happens when it's out of space. We'll return to HC in that case.
657 */
658 rc = REMNotifyInvalidatePage(pVM, GCPtrPage);
659 if (rc != VINF_SUCCESS)
660 return rc;
661#endif /* !IN_RING3 */
662
663
664#ifdef IN_RC
665 /*
666 * Check for conflicts and pending CR3 monitoring updates.
667 */
668 if (!pVM->pgm.s.fMappingsFixed)
669 {
670 if ( pgmGetMapping(pVM, GCPtrPage)
671 && PGMGstGetPage(pVM, GCPtrPage, NULL, NULL) != VERR_PAGE_TABLE_NOT_PRESENT)
672 {
673 LogFlow(("PGMGCInvalidatePage: Conflict!\n"));
674 VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
675 STAM_COUNTER_INC(&pVM->pgm.s.StatRCInvlPgConflict);
676 return VINF_PGM_SYNC_CR3;
677 }
678
679 if (pVM->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
680 {
681 LogFlow(("PGMGCInvalidatePage: PGM_SYNC_MONITOR_CR3 -> reinterpret instruction in R3\n"));
682 STAM_COUNTER_INC(&pVM->pgm.s.StatRCInvlPgSyncMonCR3);
683 return VINF_EM_RAW_EMULATE_INSTR;
684 }
685 }
686#endif /* IN_RC */
687
688 /*
689 * Call paging mode specific worker.
690 */
691 STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePage), a);
692 rc = PGM_BTH_PFN(InvalidatePage, pVM)(pVM, GCPtrPage);
693 STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePage), a);
694
695#ifdef IN_RING3
696 /*
697 * Check if we have a pending update of the CR3 monitoring.
698 */
699 if ( RT_SUCCESS(rc)
700 && (pVM->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3))
701 {
702 pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
703 Assert(!pVM->pgm.s.fMappingsFixed);
704 Assert(pVM->pgm.s.GCPhysCR3 == pVM->pgm.s.GCPhysGstCR3Monitored);
705 rc = PGM_GST_PFN(MonitorCR3, pVM)(pVM, pVM->pgm.s.GCPhysCR3);
706 }
707
708 /*
709 * Inform CSAM about the flush
710 *
711 * Note: This is to check if monitored pages have been changed; when we implement
712 * callbacks for virtual handlers, this is no longer required.
713 */
714 CSAMR3FlushPage(pVM, GCPtrPage);
715#endif /* IN_RING3 */
716 return rc;
717}
718
719
720/**
721 * Executes an instruction using the interpreter.
722 *
723 * @returns VBox status code (appropriate for trap handling and GC return).
724 * @param pVM VM handle.
725 * @param pRegFrame Register frame.
726 * @param pvFault Fault address.
727 */
728VMMDECL(int) PGMInterpretInstruction(PVM pVM, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
729{
730 uint32_t cb;
731 int rc = EMInterpretInstruction(pVM, pRegFrame, pvFault, &cb);
732 if (rc == VERR_EM_INTERPRETER)
733 rc = VINF_EM_RAW_EMULATE_INSTR;
734 if (rc != VINF_SUCCESS)
735 Log(("PGMInterpretInstruction: returns %Rrc (pvFault=%RGv)\n", rc, pvFault));
736 return rc;
737}
738
739
740/**
741 * Gets effective page information (from the VMM page directory).
742 *
743 * @returns VBox status.
744 * @param pVM VM Handle.
745 * @param GCPtr Guest Context virtual address of the page.
746 * @param pfFlags Where to store the flags. These are X86_PTE_*.
747 * @param pHCPhys Where to store the HC physical address of the page.
748 * This is page aligned.
749 * @remark You should use PGMMapGetPage() for pages in a mapping.
750 */
751VMMDECL(int) PGMShwGetPage(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys)
752{
753 return PGM_SHW_PFN(GetPage,pVM)(pVM, GCPtr, pfFlags, pHCPhys);
754}
755
756
757/**
758 * Sets (replaces) the page flags for a range of pages in the shadow context.
759 *
760 * @returns VBox status.
761 * @param pVM VM handle.
762 * @param GCPtr The address of the first page.
763 * @param cb The size of the range in bytes.
764 * @param fFlags Page flags X86_PTE_*, excluding the page mask of course.
765 * @remark You must use PGMMapSetPage() for pages in a mapping.
766 */
767VMMDECL(int) PGMShwSetPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags)
768{
769 return PGMShwModifyPage(pVM, GCPtr, cb, fFlags, 0);
770}
771
772
773/**
774 * Modify page flags for a range of pages in the shadow context.
775 *
776 * The existing flags are ANDed with the fMask and ORed with the fFlags.
777 *
778 * @returns VBox status code.
779 * @param pVM VM handle.
780 * @param GCPtr Virtual address of the first page in the range.
781 * @param cb Size (in bytes) of the range to apply the modification to.
782 * @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
783 * @param fMask The AND mask - page flags X86_PTE_*.
784 * Be very CAREFUL when ~'ing constants which could be 32-bit!
785 * @remark You must use PGMMapModifyPage() for pages in a mapping.
786 */
787VMMDECL(int) PGMShwModifyPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
788{
789 AssertMsg(!(fFlags & X86_PTE_PAE_PG_MASK), ("fFlags=%#llx\n", fFlags));
790 Assert(cb);
791
792 /*
793 * Align the input.
794 */
795 cb += GCPtr & PAGE_OFFSET_MASK;
796 cb = RT_ALIGN_Z(cb, PAGE_SIZE);
797 GCPtr = (GCPtr & PAGE_BASE_GC_MASK); /** @todo this ain't necessary, right... */
798
799 /*
800 * Call worker.
801 */
802 return PGM_SHW_PFN(ModifyPage, pVM)(pVM, GCPtr, cb, fFlags, fMask);
803}
804
805
806/**
807 * Syncs the SHADOW page directory pointer for the specified address.
808 *
809 * Allocates backing pages in case the PDPT entry is missing.
810 *
811 * @returns VBox status.
812 * @param pVM VM handle.
813 * @param GCPtr The address.
814 * @param pGstPdpe Guest PDPT entry
815 * @param ppPD Receives address of page directory
816 * @remarks Unused.
817 */
818DECLINLINE(int) pgmShwSyncPAEPDPtr(PVM pVM, RTGCPTR GCPtr, PX86PDPE pGstPdpe, PX86PDPAE *ppPD)
819{
820 PPGM pPGM = &pVM->pgm.s;
821 PPGMPOOL pPool = pPGM->CTX_SUFF(pPool);
822 PPGMPOOLPAGE pShwPage;
823 int rc;
824
825 Assert(!HWACCMIsNestedPagingActive(pVM));
826
827 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
828 PX86PDPT pPdpt = pgmShwGetPaePDPTPtr(&pVM->pgm.s);
829 PX86PDPE pPdpe = &pPdpt->a[iPdPt];
830
831 /* Allocate page directory if not present. */
832 if ( !pPdpe->n.u1Present
833 && !(pPdpe->u & X86_PDPE_PG_MASK))
834 {
835 PX86PDPE pPdptGst = pgmGstGetPaePDPEPtr(pPGM, GCPtr);
836
837 Assert(!(pPdpe->u & X86_PDPE_PG_MASK));
838 /* Create a reference back to the PDPT by using the index in its shadow page. */
839 rc = pgmPoolAlloc(pVM, pPdptGst->u & X86_PDPE_PG_MASK, PGMPOOLKIND_PAE_PD_FOR_PAE_PD, PGMPOOL_IDX_PDPT, iPdPt, &pShwPage);
840 if (rc == VERR_PGM_POOL_FLUSHED)
841 {
842 Assert(pVM->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL);
843 VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
844 return VINF_PGM_SYNC_CR3;
845 }
846 AssertRCReturn(rc, rc);
847 }
848 else
849 {
850 pShwPage = pgmPoolGetPage(pPool, pPdpe->u & X86_PDPE_PG_MASK);
851 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
852 }
853 /* The PD was cached or created; hook it up now. */
854 pPdpe->u |= pShwPage->Core.Key
855 | (pGstPdpe->u & ~(X86_PDPE_PG_MASK | X86_PDPE_AVL_MASK | X86_PDPE_PCD | X86_PDPE_PWT));
856
857 *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
858 return VINF_SUCCESS;
859}
860
861
862/**
863 * Gets the SHADOW page directory pointer for the specified address.
864 *
865 * @returns VBox status.
866 * @param pVM VM handle.
867 * @param GCPtr The address.
868 * @param ppPdpt Receives address of pdpt
869 * @param ppPD Receives address of page directory
870 * @remarks Unused.
871 */
872DECLINLINE(int) pgmShwGetPAEPDPtr(PVM pVM, RTGCPTR GCPtr, PX86PDPT *ppPdpt, PX86PDPAE *ppPD)
873{
874 PPGM pPGM = &pVM->pgm.s;
875 PPGMPOOL pPool = pPGM->CTX_SUFF(pPool);
876 PPGMPOOLPAGE pShwPage;
877
878 Assert(!HWACCMIsNestedPagingActive(pVM));
879
880 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
881 PX86PDPT pPdpt = pgmShwGetPaePDPTPtr(&pVM->pgm.s);
882 PX86PDPE pPdpe = &pPdpt->a[iPdPt];
883
884 *ppPdpt = pPdpt;
885 if (!pPdpe->n.u1Present)
886 return VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT;
887
888 pShwPage = pgmPoolGetPage(pPool, pPdpe->u & X86_PDPE_PG_MASK);
889 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
890
891 *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
892 return VINF_SUCCESS;
893}
894
895#ifndef IN_RC
896
897/**
898 * Syncs the SHADOW page directory pointer for the specified address.
899 *
900 * Allocates backing pages in case the PDPT or PML4 entry is missing.
901 *
902 * The caller is responsible for making sure the guest has a valid PD before
903 * calling this function.
904 *
905 * @returns VBox status.
906 * @param pVM VM handle.
907 * @param GCPtr The address.
908 * @param pGstPml4e Guest PML4 entry
909 * @param pGstPdpe Guest PDPT entry
910 * @param ppPD Receives address of page directory
911 */
912DECLINLINE(int) pgmShwSyncLongModePDPtr(PVM pVM, RTGCPTR64 GCPtr, PX86PML4E pGstPml4e, PX86PDPE pGstPdpe, PX86PDPAE *ppPD)
913{
914 PPGM pPGM = &pVM->pgm.s;
915 PPGMPOOL pPool = pPGM->CTX_SUFF(pPool);
916 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
917 PX86PML4E pPml4e = pgmShwGetLongModePML4EPtr(pPGM, iPml4);
918 bool fNestedPaging = HWACCMIsNestedPagingActive(pVM);
919 PPGMPOOLPAGE pShwPage;
920 X86PML4E Pml4eGst;
921 int rc;
922
923 /* Allocate page directory pointer table if not present. */
924 if ( !pPml4e->n.u1Present
925 && !(pPml4e->u & X86_PML4E_PG_MASK))
926 {
927 Assert(!(pPml4e->u & X86_PML4E_PG_MASK));
928 if (!fNestedPaging)
929 {
930 /** @todo why are we looking up the guest PML4E here? Isn't pGstPml4e
931 * trustworthy? (Remove pgmGstGetLongModePML4E if pGstPml4e and pGstPdpe
932 * are fine.) */
933 Assert(pVM->pgm.s.CTX_SUFF(pShwAmd64CR3));
934 Pml4eGst = pgmGstGetLongModePML4E(&pVM->pgm.s, iPml4);
935
936 rc = pgmPoolAlloc(pVM, Pml4eGst.u & X86_PML4E_PG_MASK,
937 PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT, pVM->pgm.s.CTX_SUFF(pShwAmd64CR3)->idx, iPml4, &pShwPage);
938 }
939 else
940 rc = pgmPoolAlloc(pVM, GCPtr + RT_BIT_64(63) /* hack: make the address unique */,
941 PGMPOOLKIND_64BIT_PDPT_FOR_PHYS, PGMPOOL_IDX_NESTED_ROOT, iPml4, &pShwPage);
942
943 if (rc == VERR_PGM_POOL_FLUSHED)
944 {
945 Log(("PGMShwSyncLongModePDPtr: PGM pool flushed (1) -> signal sync cr3\n"));
946 Assert(pVM->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL);
947 VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
948 return VINF_PGM_SYNC_CR3;
949 }
950 AssertRCReturn(rc, rc);
951 }
952 else
953 {
954 pShwPage = pgmPoolGetPage(pPool, pPml4e->u & X86_PML4E_PG_MASK);
955 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
956 }
957 /* The PDPT was cached or created; hook it up now. */
958 pPml4e->u |= pShwPage->Core.Key
959 | (pGstPml4e->u & ~(X86_PML4E_PG_MASK | X86_PML4E_AVL_MASK | X86_PML4E_PCD | X86_PML4E_PWT));
960
961 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
962 PX86PDPT pPdpt = (PX86PDPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
963 PX86PDPE pPdpe = &pPdpt->a[iPdPt];
964
965 /* Allocate page directory if not present. */
966 if ( !pPdpe->n.u1Present
967 && !(pPdpe->u & X86_PDPE_PG_MASK))
968 {
969 if (!fNestedPaging)
970 {
971 /** @todo why are we looking up the guest PDPTE here? Isn't pGstPdpe
972 * trustworthy? */
973 Pml4eGst = pgmGstGetLongModePML4E(&pVM->pgm.s, iPml4);
974 PX86PDPT pPdptGst;
975 rc = PGM_GCPHYS_2_PTR(pVM, Pml4eGst.u & X86_PML4E_PG_MASK, &pPdptGst);
976 AssertRCReturn(rc, rc);
977
978 Assert(!(pPdpe->u & X86_PDPE_PG_MASK));
979 /* Create a reference back to the PDPT by using the index in its shadow page. */
980 rc = pgmPoolAlloc(pVM, pPdptGst->a[iPdPt].u & X86_PDPE_PG_MASK, PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD, pShwPage->idx, iPdPt, &pShwPage);
981 }
982 else
983 rc = pgmPoolAlloc(pVM, GCPtr + RT_BIT_64(62) /* hack: make the address unique */, PGMPOOLKIND_64BIT_PD_FOR_PHYS, pShwPage->idx, iPdPt, &pShwPage);
984
985 if (rc == VERR_PGM_POOL_FLUSHED)
986 {
987 Log(("PGMShwSyncLongModePDPtr: PGM pool flushed (2) -> signal sync cr3\n"));
988 Assert(pVM->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL);
989 VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
990 return VINF_PGM_SYNC_CR3;
991 }
992 AssertRCReturn(rc, rc);
993 }
994 else
995 {
996 pShwPage = pgmPoolGetPage(pPool, pPdpe->u & X86_PDPE_PG_MASK);
997 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
998 }
999 /* The PD was cached or created; hook it up now. */
1000 pPdpe->u |= pShwPage->Core.Key
1001 | (pGstPdpe->u & ~(X86_PDPE_PG_MASK | X86_PDPE_AVL_MASK | X86_PDPE_PCD | X86_PDPE_PWT));
1002
1003 *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1004 return VINF_SUCCESS;
1005}
1006
1007
1008/**
1009 * Gets the SHADOW page directory pointer for the specified address (long mode).
1010 *
1011 * @returns VBox status.
1012 * @param pVM VM handle.
1013 * @param GCPtr The address.
1014 * @param ppPdpt Receives address of pdpt
1015 * @param ppPD Receives address of page directory
1016 */
1017DECLINLINE(int) pgmShwGetLongModePDPtr(PVM pVM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPT *ppPdpt, PX86PDPAE *ppPD)
1018{
1019 PPGM pPGM = &pVM->pgm.s;
1020 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
1021 PCX86PML4E pPml4e = pgmShwGetLongModePML4EPtr(pPGM, iPml4);
1022 AssertReturn(pPml4e, VERR_INTERNAL_ERROR);
1023 if (ppPml4e)
1024 *ppPml4e = (PX86PML4E)pPml4e;
1025 if (!pPml4e->n.u1Present)
1026 return VERR_PAGE_MAP_LEVEL4_NOT_PRESENT;
1027
1028 PPGMPOOL pPool = pPGM->CTX_SUFF(pPool);
1029 PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPml4e->u & X86_PML4E_PG_MASK);
1030 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1031
1032 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1033 PCX86PDPT pPdpt = *ppPdpt = (PX86PDPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1034 if (!pPdpt->a[iPdPt].n.u1Present)
1035 return VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT;
1036
1037 pShwPage = pgmPoolGetPage(pPool, pPdpt->a[iPdPt].u & X86_PDPE_PG_MASK);
1038 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1039
1040 *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1041 return VINF_SUCCESS;
1042}
1043
1044
1045/**
1046 * Syncs the SHADOW EPT page directory pointer for the specified address. Allocates
1047 * backing pages in case the PDPT or PML4 entry is missing.
1048 *
1049 * @returns VBox status.
1050 * @param pVM VM handle.
1051 * @param GCPtr The address.
1052 * @param ppPdpt Receives address of pdpt
1053 * @param ppPD Receives address of page directory
1054 */
1055DECLINLINE(int) pgmShwGetEPTPDPtr(PVM pVM, RTGCPTR64 GCPtr, PEPTPDPT *ppPdpt, PEPTPD *ppPD)
1056{
1057 PPGM pPGM = &pVM->pgm.s;
1058 const unsigned iPml4 = (GCPtr >> EPT_PML4_SHIFT) & EPT_PML4_MASK;
1059 PPGMPOOL pPool = pPGM->CTX_SUFF(pPool);
1060 PEPTPML4 pPml4;
1061 PEPTPML4E pPml4e;
1062 PPGMPOOLPAGE pShwPage;
1063 int rc;
1064
1065 Assert(HWACCMIsNestedPagingActive(pVM));
1066
1067# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
1068 rc = PGM_HCPHYS_2_PTR(pVM, pPGM->HCPhysShwNestedRoot, &pPml4);
1069 AssertRCReturn(rc, rc);
1070# else
1071 pPml4 = (PEPTPML4)pPGM->CTX_SUFF(pShwNestedRoot);
1072# endif
1073 Assert(pPml4);
1074
1075 /* Allocate page directory pointer table if not present. */
1076 pPml4e = &pPml4->a[iPml4];
1077 if ( !pPml4e->n.u1Present
1078 && !(pPml4e->u & EPT_PML4E_PG_MASK))
1079 {
1080 Assert(!(pPml4e->u & EPT_PML4E_PG_MASK));
1081
1082 rc = pgmPoolAlloc(pVM, (GCPtr & EPT_PML4E_PG_MASK) + RT_BIT_64(63) /* hack: make the address unique */, PGMPOOLKIND_EPT_PDPT_FOR_PHYS, PGMPOOL_IDX_NESTED_ROOT, iPml4, &pShwPage);
1083 if (rc == VERR_PGM_POOL_FLUSHED)
1084 {
1085 Log(("PGMShwSyncEPTPDPtr: PGM pool flushed (1) -> signal sync cr3\n"));
1086 Assert(pVM->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL);
1087 VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
1088 return VINF_PGM_SYNC_CR3;
1089 }
1090 AssertRCReturn(rc, rc);
1091 }
1092 else
1093 {
1094 pShwPage = pgmPoolGetPage(pPool, pPml4e->u & EPT_PML4E_PG_MASK);
1095 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1096 }
1097 /* The PDPT was cached or created; hook it up now and fill with the default value. */
1098 pPml4e->u = pShwPage->Core.Key;
1099 pPml4e->n.u1Present = 1;
1100 pPml4e->n.u1Write = 1;
1101 pPml4e->n.u1Execute = 1;
1102
1103 const unsigned iPdPt = (GCPtr >> EPT_PDPT_SHIFT) & EPT_PDPT_MASK;
1104 PEPTPDPT pPdpt = (PEPTPDPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1105 PEPTPDPTE pPdpe = &pPdpt->a[iPdPt];
1106
1107 if (ppPdpt)
1108 *ppPdpt = pPdpt;
1109
1110 /* Allocate page directory if not present. */
1111 if ( !pPdpe->n.u1Present
1112 && !(pPdpe->u & EPT_PDPTE_PG_MASK))
1113 {
1114 rc = pgmPoolAlloc(pVM, (GCPtr & EPT_PDPTE_PG_MASK) + RT_BIT_64(62) /* hack: make the address unique */, PGMPOOLKIND_64BIT_PD_FOR_PHYS, pShwPage->idx, iPdPt, &pShwPage);
1115 if (rc == VERR_PGM_POOL_FLUSHED)
1116 {
1117 Log(("PGMShwSyncEPTPDPtr: PGM pool flushed (2) -> signal sync cr3\n"));
1118 Assert(pVM->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL);
1119 VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
1120 return VINF_PGM_SYNC_CR3;
1121 }
1122 AssertRCReturn(rc, rc);
1123 }
1124 else
1125 {
1126 pShwPage = pgmPoolGetPage(pPool, pPdpe->u & EPT_PDPTE_PG_MASK);
1127 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1128 }
1129 /* The PD was cached or created; hook it up now and fill with the default value. */
1130 pPdpe->u = pShwPage->Core.Key;
1131 pPdpe->n.u1Present = 1;
1132 pPdpe->n.u1Write = 1;
1133 pPdpe->n.u1Execute = 1;
1134
1135 *ppPD = (PEPTPD)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1136 return VINF_SUCCESS;
1137}
1138
1139#endif /* IN_RC */
1140
1141/**
1142 * Gets effective Guest OS page information.
1143 *
1144 * When GCPtr is in a big page, the function will return as if it was a normal
1145 * 4KB page. If the need for distinguishing between big and normal page becomes
1146 * necessary at a later point, a PGMGstGetPage() will be created for that
1147 * purpose.
1148 *
1149 * @returns VBox status.
1150 * @param pVM VM Handle.
1151 * @param GCPtr Guest Context virtual address of the page.
1152 * @param pfFlags Where to store the flags. These are X86_PTE_*, even for big pages.
1153 * @param pGCPhys Where to store the GC physical address of the page.
1154 * This is page aligned. The fact that the
1155 */
1156VMMDECL(int) PGMGstGetPage(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys)
1157{
1158 return PGM_GST_PFN(GetPage,pVM)(pVM, GCPtr, pfFlags, pGCPhys);
1159}
1160
1161
1162/**
1163 * Checks if the page is present.
1164 *
1165 * @returns true if the page is present.
1166 * @returns false if the page is not present.
1167 * @param pVM The VM handle.
1168 * @param GCPtr Address within the page.
1169 */
1170VMMDECL(bool) PGMGstIsPagePresent(PVM pVM, RTGCPTR GCPtr)
1171{
1172 int rc = PGMGstGetPage(pVM, GCPtr, NULL, NULL);
1173 return RT_SUCCESS(rc);
1174}
1175
1176
1177/**
1178 * Sets (replaces) the page flags for a range of pages in the guest's tables.
1179 *
1180 * @returns VBox status.
1181 * @param pVM VM handle.
1182 * @param GCPtr The address of the first page.
1183 * @param cb The size of the range in bytes.
1184 * @param fFlags Page flags X86_PTE_*, excluding the page mask of course.
1185 */
1186VMMDECL(int) PGMGstSetPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags)
1187{
1188 return PGMGstModifyPage(pVM, GCPtr, cb, fFlags, 0);
1189}
1190
1191
1192/**
1193 * Modify page flags for a range of pages in the guest's tables
1194 *
1195 * The existing flags are ANDed with the fMask and ORed with the fFlags.
1196 *
1197 * @returns VBox status code.
1198 * @param pVM VM handle.
1199 * @param GCPtr Virtual address of the first page in the range.
1200 * @param cb Size (in bytes) of the range to apply the modification to.
1201 * @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
1202 * @param fMask The AND mask - page flags X86_PTE_*, excluding the page mask of course.
1203 * Be very CAREFUL when ~'ing constants which could be 32-bit!
1204 */
1205VMMDECL(int) PGMGstModifyPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
1206{
1207 STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,GstModifyPage), a);
1208
1209 /*
1210 * Validate input.
1211 */
1212 AssertMsg(!(fFlags & X86_PTE_PAE_PG_MASK), ("fFlags=%#llx\n", fFlags));
1213 Assert(cb);
1214
1215 LogFlow(("PGMGstModifyPage %RGv %d bytes fFlags=%08llx fMask=%08llx\n", GCPtr, cb, fFlags, fMask));
1216
1217 /*
1218 * Adjust input.
1219 */
1220 cb += GCPtr & PAGE_OFFSET_MASK;
1221 cb = RT_ALIGN_Z(cb, PAGE_SIZE);
1222 GCPtr = (GCPtr & PAGE_BASE_GC_MASK);
1223
1224 /*
1225 * Call worker.
1226 */
1227 int rc = PGM_GST_PFN(ModifyPage, pVM)(pVM, GCPtr, cb, fFlags, fMask);
1228
1229 STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,GstModifyPage), a);
1230 return rc;
1231}
1232
1233
1234/**
1235 * Gets the specified page directory pointer table entry.
1236 *
1237 * @returns PDP entry
1238 * @param pPGM Pointer to the PGM instance data.
1239 * @param iPdpt PDPT index
1240 */
1241VMMDECL(X86PDPE) PGMGstGetPaePDPtr(PVM pVM, unsigned iPdpt)
1242{
1243 Assert(iPdpt <= 3);
1244 return pgmGstGetPaePDPTPtr(&pVM->pgm.s)->a[iPdpt & 3];
1245}
1246
1247
1248/**
1249 * Gets the current CR3 register value for the shadow memory context.
1250 * @returns CR3 value.
1251 * @param pVM The VM handle.
1252 */
1253VMMDECL(RTHCPHYS) PGMGetHyperCR3(PVM pVM)
1254{
1255 PGMMODE enmShadowMode = pVM->pgm.s.enmShadowMode;
1256 switch (enmShadowMode)
1257 {
1258 case PGMMODE_32_BIT:
1259 return pVM->pgm.s.HCPhysShw32BitPD;
1260
1261 case PGMMODE_PAE:
1262 case PGMMODE_PAE_NX:
1263 return pVM->pgm.s.HCPhysShwPaePdpt;
1264
1265 case PGMMODE_AMD64:
1266 case PGMMODE_AMD64_NX:
1267 return pVM->pgm.s.HCPhysShwPaePml4;
1268
1269 case PGMMODE_EPT:
1270 return pVM->pgm.s.HCPhysShwNestedRoot;
1271
1272 case PGMMODE_NESTED:
1273 return PGMGetNestedCR3(pVM, PGMGetHostMode(pVM));
1274
1275 default:
1276 AssertMsgFailed(("enmShadowMode=%d\n", enmShadowMode));
1277 return ~0;
1278 }
1279}
1280
1281
1282/**
1283 * Gets the current CR3 register value for the nested memory context.
1284 * @returns CR3 value.
1285 * @param pVM The VM handle.
1286 */
1287VMMDECL(RTHCPHYS) PGMGetNestedCR3(PVM pVM, PGMMODE enmShadowMode)
1288{
1289 switch (enmShadowMode)
1290 {
1291 case PGMMODE_32_BIT:
1292 return pVM->pgm.s.HCPhysShw32BitPD;
1293
1294 case PGMMODE_PAE:
1295 case PGMMODE_PAE_NX:
1296 return pVM->pgm.s.HCPhysShwPaePdpt;
1297
1298 case PGMMODE_AMD64:
1299 case PGMMODE_AMD64_NX:
1300 return pVM->pgm.s.HCPhysShwPaePml4;
1301
1302 default:
1303 AssertMsgFailed(("enmShadowMode=%d\n", enmShadowMode));
1304 return ~0;
1305 }
1306}
1307
1308
1309/**
1310 * Gets the current CR3 register value for the EPT paging memory context.
1311 * @returns CR3 value.
1312 * @param pVM The VM handle.
1313 */
1314VMMDECL(RTHCPHYS) PGMGetEPTCR3(PVM pVM)
1315{
1316 return pVM->pgm.s.HCPhysShwNestedRoot;
1317}
1318
1319
1320/**
1321 * Gets the CR3 register value for the 32-Bit shadow memory context.
1322 * @returns CR3 value.
1323 * @param pVM The VM handle.
1324 */
1325VMMDECL(RTHCPHYS) PGMGetHyper32BitCR3(PVM pVM)
1326{
1327 return pVM->pgm.s.HCPhysShw32BitPD;
1328}
1329
1330
1331/**
1332 * Gets the CR3 register value for the PAE shadow memory context.
1333 * @returns CR3 value.
1334 * @param pVM The VM handle.
1335 */
1336VMMDECL(RTHCPHYS) PGMGetHyperPaeCR3(PVM pVM)
1337{
1338 return pVM->pgm.s.HCPhysShwPaePdpt;
1339}
1340
1341
1342/**
1343 * Gets the CR3 register value for the AMD64 shadow memory context.
1344 * @returns CR3 value.
1345 * @param pVM The VM handle.
1346 */
1347VMMDECL(RTHCPHYS) PGMGetHyperAmd64CR3(PVM pVM)
1348{
1349 return pVM->pgm.s.HCPhysShwPaePml4;
1350}
1351
1352
1353/**
1354 * Gets the current CR3 register value for the HC intermediate memory context.
1355 * @returns CR3 value.
1356 * @param pVM The VM handle.
1357 */
1358VMMDECL(RTHCPHYS) PGMGetInterHCCR3(PVM pVM)
1359{
1360 switch (pVM->pgm.s.enmHostMode)
1361 {
1362 case SUPPAGINGMODE_32_BIT:
1363 case SUPPAGINGMODE_32_BIT_GLOBAL:
1364 return pVM->pgm.s.HCPhysInterPD;
1365
1366 case SUPPAGINGMODE_PAE:
1367 case SUPPAGINGMODE_PAE_GLOBAL:
1368 case SUPPAGINGMODE_PAE_NX:
1369 case SUPPAGINGMODE_PAE_GLOBAL_NX:
1370 return pVM->pgm.s.HCPhysInterPaePDPT;
1371
1372 case SUPPAGINGMODE_AMD64:
1373 case SUPPAGINGMODE_AMD64_GLOBAL:
1374 case SUPPAGINGMODE_AMD64_NX:
1375 case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1376 return pVM->pgm.s.HCPhysInterPaePDPT;
1377
1378 default:
1379 AssertMsgFailed(("enmHostMode=%d\n", pVM->pgm.s.enmHostMode));
1380 return ~0;
1381 }
1382}
1383
1384
1385/**
1386 * Gets the current CR3 register value for the RC intermediate memory context.
1387 * @returns CR3 value.
1388 * @param pVM The VM handle.
1389 */
1390VMMDECL(RTHCPHYS) PGMGetInterRCCR3(PVM pVM)
1391{
1392 switch (pVM->pgm.s.enmShadowMode)
1393 {
1394 case PGMMODE_32_BIT:
1395 return pVM->pgm.s.HCPhysInterPD;
1396
1397 case PGMMODE_PAE:
1398 case PGMMODE_PAE_NX:
1399 return pVM->pgm.s.HCPhysInterPaePDPT;
1400
1401 case PGMMODE_AMD64:
1402 case PGMMODE_AMD64_NX:
1403 return pVM->pgm.s.HCPhysInterPaePML4;
1404
1405 case PGMMODE_EPT:
1406 case PGMMODE_NESTED:
1407 return 0; /* not relevant */
1408
1409 default:
1410 AssertMsgFailed(("enmShadowMode=%d\n", pVM->pgm.s.enmShadowMode));
1411 return ~0;
1412 }
1413}
1414
1415
1416/**
1417 * Gets the CR3 register value for the 32-Bit intermediate memory context.
1418 * @returns CR3 value.
1419 * @param pVM The VM handle.
1420 */
1421VMMDECL(RTHCPHYS) PGMGetInter32BitCR3(PVM pVM)
1422{
1423 return pVM->pgm.s.HCPhysInterPD;
1424}
1425
1426
1427/**
1428 * Gets the CR3 register value for the PAE intermediate memory context.
1429 * @returns CR3 value.
1430 * @param pVM The VM handle.
1431 */
1432VMMDECL(RTHCPHYS) PGMGetInterPaeCR3(PVM pVM)
1433{
1434 return pVM->pgm.s.HCPhysInterPaePDPT;
1435}
1436
1437
1438/**
1439 * Gets the CR3 register value for the AMD64 intermediate memory context.
1440 * @returns CR3 value.
1441 * @param pVM The VM handle.
1442 */
1443VMMDECL(RTHCPHYS) PGMGetInterAmd64CR3(PVM pVM)
1444{
1445 return pVM->pgm.s.HCPhysInterPaePML4;
1446}
1447
1448
1449/**
1450 * Performs and schedules necessary updates following a CR3 load or reload.
1451 *
1452 * This will normally involve mapping the guest PD or nPDPT
1453 *
1454 * @returns VBox status code.
1455 * @retval VINF_PGM_SYNC_CR3 if monitoring requires a CR3 sync. This can
1456 * safely be ignored and overridden since the FF will be set too then.
1457 * @param pVM VM handle.
1458 * @param cr3 The new cr3.
1459 * @param fGlobal Indicates whether this is a global flush or not.
1460 */
1461VMMDECL(int) PGMFlushTLB(PVM pVM, uint64_t cr3, bool fGlobal)
1462{
1463 STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,FlushTLB), a);
1464
1465 /*
1466 * Always flag the necessary updates; necessary for hardware acceleration
1467 */
1468 /** @todo optimize this, it shouldn't always be necessary. */
1469 VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
1470 if (fGlobal)
1471 VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
1472 LogFlow(("PGMFlushTLB: cr3=%RX64 OldCr3=%RX64 fGlobal=%d\n", cr3, pVM->pgm.s.GCPhysCR3, fGlobal));
1473
1474 /*
1475 * Remap the CR3 content and adjust the monitoring if CR3 was actually changed.
1476 */
1477 int rc = VINF_SUCCESS;
1478 RTGCPHYS GCPhysCR3;
1479 if ( pVM->pgm.s.enmGuestMode == PGMMODE_PAE
1480 || pVM->pgm.s.enmGuestMode == PGMMODE_PAE_NX
1481 || pVM->pgm.s.enmGuestMode == PGMMODE_AMD64
1482 || pVM->pgm.s.enmGuestMode == PGMMODE_AMD64_NX)
1483 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAE_PAGE_MASK);
1484 else
1485 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAGE_MASK);
1486 if (pVM->pgm.s.GCPhysCR3 != GCPhysCR3)
1487 {
1488 RTGCPHYS GCPhysOldCR3 = pVM->pgm.s.GCPhysCR3;
1489 pVM->pgm.s.GCPhysCR3 = GCPhysCR3;
1490 rc = PGM_GST_PFN(MapCR3, pVM)(pVM, GCPhysCR3);
1491 if (RT_LIKELY(rc == VINF_SUCCESS))
1492 {
1493 if (!pVM->pgm.s.fMappingsFixed)
1494 {
1495 pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
1496 rc = PGM_GST_PFN(MonitorCR3, pVM)(pVM, GCPhysCR3);
1497 }
1498 }
1499 else
1500 {
1501 AssertMsg(rc == VINF_PGM_SYNC_CR3, ("%Rrc\n", rc));
1502 Assert(VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL | VM_FF_PGM_SYNC_CR3));
1503 pVM->pgm.s.GCPhysCR3 = GCPhysOldCR3;
1504 pVM->pgm.s.fSyncFlags |= PGM_SYNC_MAP_CR3;
1505 if (!pVM->pgm.s.fMappingsFixed)
1506 pVM->pgm.s.fSyncFlags |= PGM_SYNC_MONITOR_CR3;
1507 }
1508
1509 if (fGlobal)
1510 STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,FlushTLBNewCR3Global));
1511 else
1512 STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,FlushTLBNewCR3));
1513 }
1514 else
1515 {
1516 /*
1517 * Check if we have a pending update of the CR3 monitoring.
1518 */
1519 if (pVM->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
1520 {
1521 pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
1522 Assert(!pVM->pgm.s.fMappingsFixed);
1523 rc = PGM_GST_PFN(MonitorCR3, pVM)(pVM, GCPhysCR3);
1524 }
1525 if (fGlobal)
1526 STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,FlushTLBSameCR3Global));
1527 else
1528 STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,FlushTLBSameCR3));
1529 }
1530
1531 STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,FlushTLB), a);
1532 return rc;
1533}
1534
1535
1536/**
1537 * Performs and schedules necessary updates following a CR3 load or reload when
1538 * using nested or extended paging.
1539 *
1540 * This API is an alterantive to PDMFlushTLB that avoids actually flushing the
1541 * TLB and triggering a SyncCR3.
1542 *
1543 * This will normally involve mapping the guest PD or nPDPT
1544 *
1545 * @returns VBox status code.
1546 * @retval VINF_SUCCESS.
1547 * @retval (If applied when not in nested mode: VINF_PGM_SYNC_CR3 if monitoring
1548 * requires a CR3 sync. This can safely be ignored and overridden since
1549 * the FF will be set too then.)
1550 * @param pVM VM handle.
1551 * @param cr3 The new cr3.
1552 */
1553VMMDECL(int) PGMUpdateCR3(PVM pVM, uint64_t cr3)
1554{
1555 LogFlow(("PGMUpdateCR3: cr3=%RX64 OldCr3=%RX64\n", cr3, pVM->pgm.s.GCPhysCR3));
1556
1557 /* We assume we're only called in nested paging mode. */
1558 Assert(pVM->pgm.s.fMappingsFixed);
1559 Assert(!(pVM->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3));
1560 Assert(pVM->pgm.s.enmShadowMode == PGMMODE_NESTED || pVM->pgm.s.enmShadowMode == PGMMODE_EPT);
1561
1562 /*
1563 * Remap the CR3 content and adjust the monitoring if CR3 was actually changed.
1564 */
1565 int rc = VINF_SUCCESS;
1566 RTGCPHYS GCPhysCR3;
1567 if ( pVM->pgm.s.enmGuestMode == PGMMODE_PAE
1568 || pVM->pgm.s.enmGuestMode == PGMMODE_PAE_NX
1569 || pVM->pgm.s.enmGuestMode == PGMMODE_AMD64
1570 || pVM->pgm.s.enmGuestMode == PGMMODE_AMD64_NX)
1571 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAE_PAGE_MASK);
1572 else
1573 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAGE_MASK);
1574 if (pVM->pgm.s.GCPhysCR3 != GCPhysCR3)
1575 {
1576 pVM->pgm.s.GCPhysCR3 = GCPhysCR3;
1577 rc = PGM_GST_PFN(MapCR3, pVM)(pVM, GCPhysCR3);
1578 AssertRCSuccess(rc); /* Assumes VINF_PGM_SYNC_CR3 doesn't apply to nested paging. */
1579 }
1580 return rc;
1581}
1582
1583
1584/**
1585 * Synchronize the paging structures.
1586 *
1587 * This function is called in response to the VM_FF_PGM_SYNC_CR3 and
1588 * VM_FF_PGM_SYNC_CR3_NONGLOBAL. Those two force action flags are set
1589 * in several places, most importantly whenever the CR3 is loaded.
1590 *
1591 * @returns VBox status code.
1592 * @param pVM The virtual machine.
1593 * @param cr0 Guest context CR0 register
1594 * @param cr3 Guest context CR3 register
1595 * @param cr4 Guest context CR4 register
1596 * @param fGlobal Including global page directories or not
1597 */
1598VMMDECL(int) PGMSyncCR3(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
1599{
1600 int rc;
1601
1602 /*
1603 * We might be called when we shouldn't.
1604 *
1605 * The mode switching will ensure that the PD is resynced
1606 * after every mode switch. So, if we find ourselves here
1607 * when in protected or real mode we can safely disable the
1608 * FF and return immediately.
1609 */
1610 if (pVM->pgm.s.enmGuestMode <= PGMMODE_PROTECTED)
1611 {
1612 Assert((cr0 & (X86_CR0_PG | X86_CR0_PE)) != (X86_CR0_PG | X86_CR0_PE));
1613 VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3);
1614 VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
1615 return VINF_SUCCESS;
1616 }
1617
1618 /* If global pages are not supported, then all flushes are global. */
1619 if (!(cr4 & X86_CR4_PGE))
1620 fGlobal = true;
1621 LogFlow(("PGMSyncCR3: cr0=%RX64 cr3=%RX64 cr4=%RX64 fGlobal=%d[%d,%d]\n", cr0, cr3, cr4, fGlobal,
1622 VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3), VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL)));
1623
1624#ifdef PGMPOOL_WITH_MONITORING
1625 /*
1626 * The pool may have pending stuff and even require a return to ring-3 to
1627 * clear the whole thing.
1628 */
1629 rc = pgmPoolSyncCR3(pVM);
1630 if (rc != VINF_SUCCESS)
1631 return rc;
1632#endif
1633
1634 /*
1635 * Check if we need to finish an aborted MapCR3 call (see PGMFlushTLB).
1636 * This should be done before SyncCR3.
1637 */
1638 if (pVM->pgm.s.fSyncFlags & PGM_SYNC_MAP_CR3)
1639 {
1640 pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_MAP_CR3;
1641
1642 RTGCPHYS GCPhysCR3Old = pVM->pgm.s.GCPhysCR3;
1643 RTGCPHYS GCPhysCR3;
1644 if ( pVM->pgm.s.enmGuestMode == PGMMODE_PAE
1645 || pVM->pgm.s.enmGuestMode == PGMMODE_PAE_NX
1646 || pVM->pgm.s.enmGuestMode == PGMMODE_AMD64
1647 || pVM->pgm.s.enmGuestMode == PGMMODE_AMD64_NX)
1648 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAE_PAGE_MASK);
1649 else
1650 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAGE_MASK);
1651 pVM->pgm.s.GCPhysCR3 = GCPhysCR3;
1652 rc = PGM_GST_PFN(MapCR3, pVM)(pVM, GCPhysCR3);
1653#ifdef IN_RING3
1654 if (rc == VINF_PGM_SYNC_CR3)
1655 rc = pgmPoolSyncCR3(pVM);
1656#else
1657 if (rc == VINF_PGM_SYNC_CR3)
1658 {
1659 pVM->pgm.s.GCPhysCR3 = GCPhysCR3Old;
1660 return rc;
1661 }
1662#endif
1663 AssertRCReturn(rc, rc);
1664 AssertRCSuccessReturn(rc, VERR_INTERNAL_ERROR);
1665 }
1666
1667 /*
1668 * Let the 'Bth' function do the work and we'll just keep track of the flags.
1669 */
1670 STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3), a);
1671 rc = PGM_BTH_PFN(SyncCR3, pVM)(pVM, cr0, cr3, cr4, fGlobal);
1672 STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3), a);
1673 AssertMsg(rc == VINF_SUCCESS || rc == VINF_PGM_SYNC_CR3 || RT_FAILURE(rc), ("rc=%Rrc\n", rc));
1674 if (rc == VINF_SUCCESS)
1675 {
1676 if (!(pVM->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS))
1677 {
1678 VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3);
1679 VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
1680 }
1681
1682 /*
1683 * Check if we have a pending update of the CR3 monitoring.
1684 */
1685 if (pVM->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
1686 {
1687 pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
1688 Assert(!pVM->pgm.s.fMappingsFixed);
1689 Assert(pVM->pgm.s.GCPhysCR3 == pVM->pgm.s.GCPhysGstCR3Monitored);
1690 rc = PGM_GST_PFN(MonitorCR3, pVM)(pVM, pVM->pgm.s.GCPhysCR3);
1691 }
1692 }
1693
1694 /*
1695 * Now flush the CR3 (guest context).
1696 */
1697 if (rc == VINF_SUCCESS)
1698 PGM_INVL_GUEST_TLBS();
1699 return rc;
1700}
1701
1702
1703/**
1704 * Called whenever CR0 or CR4 in a way which may change
1705 * the paging mode.
1706 *
1707 * @returns VBox status code fit for scheduling in GC and R0.
1708 * @retval VINF_SUCCESS if the was no change, or it was successfully dealt with.
1709 * @retval VINF_PGM_CHANGE_MODE if we're in GC or R0 and the mode changes.
1710 * @param pVM VM handle.
1711 * @param cr0 The new cr0.
1712 * @param cr4 The new cr4.
1713 * @param efer The new extended feature enable register.
1714 */
1715VMMDECL(int) PGMChangeMode(PVM pVM, uint64_t cr0, uint64_t cr4, uint64_t efer)
1716{
1717 PGMMODE enmGuestMode;
1718
1719 /*
1720 * Calc the new guest mode.
1721 */
1722 if (!(cr0 & X86_CR0_PE))
1723 enmGuestMode = PGMMODE_REAL;
1724 else if (!(cr0 & X86_CR0_PG))
1725 enmGuestMode = PGMMODE_PROTECTED;
1726 else if (!(cr4 & X86_CR4_PAE))
1727 enmGuestMode = PGMMODE_32_BIT;
1728 else if (!(efer & MSR_K6_EFER_LME))
1729 {
1730 if (!(efer & MSR_K6_EFER_NXE))
1731 enmGuestMode = PGMMODE_PAE;
1732 else
1733 enmGuestMode = PGMMODE_PAE_NX;
1734 }
1735 else
1736 {
1737 if (!(efer & MSR_K6_EFER_NXE))
1738 enmGuestMode = PGMMODE_AMD64;
1739 else
1740 enmGuestMode = PGMMODE_AMD64_NX;
1741 }
1742
1743 /*
1744 * Did it change?
1745 */
1746 if (pVM->pgm.s.enmGuestMode == enmGuestMode)
1747 return VINF_SUCCESS;
1748
1749 /* Flush the TLB */
1750 PGM_INVL_GUEST_TLBS();
1751
1752#ifdef IN_RING3
1753 return PGMR3ChangeMode(pVM, enmGuestMode);
1754#else
1755 LogFlow(("PGMChangeMode: returns VINF_PGM_CHANGE_MODE.\n"));
1756 return VINF_PGM_CHANGE_MODE;
1757#endif
1758}
1759
1760
1761/**
1762 * Gets the current guest paging mode.
1763 *
1764 * If you just need the CPU mode (real/protected/long), use CPUMGetGuestMode().
1765 *
1766 * @returns The current paging mode.
1767 * @param pVM The VM handle.
1768 */
1769VMMDECL(PGMMODE) PGMGetGuestMode(PVM pVM)
1770{
1771 return pVM->pgm.s.enmGuestMode;
1772}
1773
1774
1775/**
1776 * Gets the current shadow paging mode.
1777 *
1778 * @returns The current paging mode.
1779 * @param pVM The VM handle.
1780 */
1781VMMDECL(PGMMODE) PGMGetShadowMode(PVM pVM)
1782{
1783 return pVM->pgm.s.enmShadowMode;
1784}
1785
1786/**
1787 * Gets the current host paging mode.
1788 *
1789 * @returns The current paging mode.
1790 * @param pVM The VM handle.
1791 */
1792VMMDECL(PGMMODE) PGMGetHostMode(PVM pVM)
1793{
1794 switch (pVM->pgm.s.enmHostMode)
1795 {
1796 case SUPPAGINGMODE_32_BIT:
1797 case SUPPAGINGMODE_32_BIT_GLOBAL:
1798 return PGMMODE_32_BIT;
1799
1800 case SUPPAGINGMODE_PAE:
1801 case SUPPAGINGMODE_PAE_GLOBAL:
1802 return PGMMODE_PAE;
1803
1804 case SUPPAGINGMODE_PAE_NX:
1805 case SUPPAGINGMODE_PAE_GLOBAL_NX:
1806 return PGMMODE_PAE_NX;
1807
1808 case SUPPAGINGMODE_AMD64:
1809 case SUPPAGINGMODE_AMD64_GLOBAL:
1810 return PGMMODE_AMD64;
1811
1812 case SUPPAGINGMODE_AMD64_NX:
1813 case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1814 return PGMMODE_AMD64_NX;
1815
1816 default: AssertMsgFailed(("enmHostMode=%d\n", pVM->pgm.s.enmHostMode)); break;
1817 }
1818
1819 return PGMMODE_INVALID;
1820}
1821
1822
1823/**
1824 * Get mode name.
1825 *
1826 * @returns read-only name string.
1827 * @param enmMode The mode which name is desired.
1828 */
1829VMMDECL(const char *) PGMGetModeName(PGMMODE enmMode)
1830{
1831 switch (enmMode)
1832 {
1833 case PGMMODE_REAL: return "Real";
1834 case PGMMODE_PROTECTED: return "Protected";
1835 case PGMMODE_32_BIT: return "32-bit";
1836 case PGMMODE_PAE: return "PAE";
1837 case PGMMODE_PAE_NX: return "PAE+NX";
1838 case PGMMODE_AMD64: return "AMD64";
1839 case PGMMODE_AMD64_NX: return "AMD64+NX";
1840 case PGMMODE_NESTED: return "Nested";
1841 case PGMMODE_EPT: return "EPT";
1842 default: return "unknown mode value";
1843 }
1844}
1845
1846
1847/**
1848 * Acquire the PGM lock.
1849 *
1850 * @returns VBox status code
1851 * @param pVM The VM to operate on.
1852 */
1853int pgmLock(PVM pVM)
1854{
1855 int rc = PDMCritSectEnter(&pVM->pgm.s.CritSect, VERR_SEM_BUSY);
1856#ifdef IN_RC
1857 if (rc == VERR_SEM_BUSY)
1858 rc = VMMGCCallHost(pVM, VMMCALLHOST_PGM_LOCK, 0);
1859#elif defined(IN_RING0)
1860 if (rc == VERR_SEM_BUSY)
1861 rc = VMMR0CallHost(pVM, VMMCALLHOST_PGM_LOCK, 0);
1862#endif
1863 AssertRC(rc);
1864 return rc;
1865}
1866
1867
1868/**
1869 * Release the PGM lock.
1870 *
1871 * @returns VBox status code
1872 * @param pVM The VM to operate on.
1873 */
1874void pgmUnlock(PVM pVM)
1875{
1876 PDMCritSectLeave(&pVM->pgm.s.CritSect);
1877}
1878
1879#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1880
1881/**
1882 * Temporarily maps one guest page specified by GC physical address.
1883 * These pages must have a physical mapping in HC, i.e. they cannot be MMIO pages.
1884 *
1885 * Be WARNED that the dynamic page mapping area is small, 8 pages, thus the space is
1886 * reused after 8 mappings (or perhaps a few more if you score with the cache).
1887 *
1888 * @returns VBox status.
1889 * @param pVM VM handle.
1890 * @param GCPhys GC Physical address of the page.
1891 * @param ppv Where to store the address of the mapping.
1892 */
1893VMMDECL(int) PGMDynMapGCPage(PVM pVM, RTGCPHYS GCPhys, void **ppv)
1894{
1895 AssertMsg(!(GCPhys & PAGE_OFFSET_MASK), ("GCPhys=%RGp\n", GCPhys));
1896
1897 /*
1898 * Get the ram range.
1899 */
1900 PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
1901 while (pRam && GCPhys - pRam->GCPhys >= pRam->cb)
1902 pRam = pRam->CTX_SUFF(pNext);
1903 if (!pRam)
1904 {
1905 AssertMsgFailed(("Invalid physical address %RGp!\n", GCPhys));
1906 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
1907 }
1908
1909 /*
1910 * Pass it on to PGMDynMapHCPage.
1911 */
1912 RTHCPHYS HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT]);
1913 //Log(("PGMDynMapGCPage: GCPhys=%RGp HCPhys=%RHp\n", GCPhys, HCPhys));
1914#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
1915 pgmR0DynMapHCPageInlined(&pVM->pgm.s, HCPhys, ppv);
1916#else
1917 PGMDynMapHCPage(pVM, HCPhys, ppv);
1918#endif
1919 return VINF_SUCCESS;
1920}
1921
1922
1923/**
1924 * Temporarily maps one guest page specified by unaligned GC physical address.
1925 * These pages must have a physical mapping in HC, i.e. they cannot be MMIO pages.
1926 *
1927 * Be WARNED that the dynamic page mapping area is small, 8 pages, thus the space is
1928 * reused after 8 mappings (or perhaps a few more if you score with the cache).
1929 *
1930 * The caller is aware that only the speicifed page is mapped and that really bad things
1931 * will happen if writing beyond the page!
1932 *
1933 * @returns VBox status.
1934 * @param pVM VM handle.
1935 * @param GCPhys GC Physical address within the page to be mapped.
1936 * @param ppv Where to store the address of the mapping address corresponding to GCPhys.
1937 */
1938VMMDECL(int) PGMDynMapGCPageOff(PVM pVM, RTGCPHYS GCPhys, void **ppv)
1939{
1940 /*
1941 * Get the ram range.
1942 */
1943 PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
1944 while (pRam && GCPhys - pRam->GCPhys >= pRam->cb)
1945 pRam = pRam->CTX_SUFF(pNext);
1946 if (!pRam)
1947 {
1948 AssertMsgFailed(("Invalid physical address %RGp!\n", GCPhys));
1949 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
1950 }
1951
1952 /*
1953 * Pass it on to PGMDynMapHCPage.
1954 */
1955 RTHCPHYS HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT]);
1956#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
1957 pgmR0DynMapHCPageInlined(&pVM->pgm.s, HCPhys, ppv);
1958#else
1959 PGMDynMapHCPage(pVM, HCPhys, ppv);
1960#endif
1961 *ppv = (void *)((uintptr_t)*ppv | (GCPhys & PAGE_OFFSET_MASK));
1962 return VINF_SUCCESS;
1963}
1964
1965
1966# ifdef IN_RC
1967/**
1968 * Temporarily maps one host page specified by HC physical address.
1969 *
1970 * Be WARNED that the dynamic page mapping area is small, 8 pages, thus the space is
1971 * reused after 8 mappings (or perhaps a few more if you score with the cache).
1972 *
1973 * @returns VINF_SUCCESS, will bail out to ring-3 on failure.
1974 * @param pVM VM handle.
1975 * @param HCPhys HC Physical address of the page.
1976 * @param ppv Where to store the address of the mapping. This is the
1977 * address of the PAGE not the exact address corresponding
1978 * to HCPhys. Use PGMDynMapHCPageOff if you care for the
1979 * page offset.
1980 */
1981VMMDECL(int) PGMDynMapHCPage(PVM pVM, RTHCPHYS HCPhys, void **ppv)
1982{
1983 AssertMsg(!(HCPhys & PAGE_OFFSET_MASK), ("HCPhys=%RHp\n", HCPhys));
1984
1985 /*
1986 * Check the cache.
1987 */
1988 register unsigned iCache;
1989 if ( pVM->pgm.s.aHCPhysDynPageMapCache[iCache = 0] == HCPhys
1990 || pVM->pgm.s.aHCPhysDynPageMapCache[iCache = 1] == HCPhys
1991 || pVM->pgm.s.aHCPhysDynPageMapCache[iCache = 2] == HCPhys
1992 || pVM->pgm.s.aHCPhysDynPageMapCache[iCache = 3] == HCPhys)
1993 {
1994 static const uint8_t au8Trans[MM_HYPER_DYNAMIC_SIZE >> PAGE_SHIFT][RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache)] =
1995 {
1996 { 0, 5, 6, 7 },
1997 { 0, 1, 6, 7 },
1998 { 0, 1, 2, 7 },
1999 { 0, 1, 2, 3 },
2000 { 4, 1, 2, 3 },
2001 { 4, 5, 2, 3 },
2002 { 4, 5, 6, 3 },
2003 { 4, 5, 6, 7 },
2004 };
2005 Assert(RT_ELEMENTS(au8Trans) == 8);
2006 Assert(RT_ELEMENTS(au8Trans[0]) == 4);
2007 int iPage = au8Trans[pVM->pgm.s.iDynPageMapLast][iCache];
2008 void *pv = pVM->pgm.s.pbDynPageMapBaseGC + (iPage << PAGE_SHIFT);
2009 *ppv = pv;
2010 STAM_COUNTER_INC(&pVM->pgm.s.StatRCDynMapCacheHits);
2011 //Log(("PGMGCDynMapHCPage: HCPhys=%RHp pv=%p iPage=%d iCache=%d\n", HCPhys, pv, iPage, iCache));
2012 return VINF_SUCCESS;
2013 }
2014 Assert(RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache) == 4);
2015 STAM_COUNTER_INC(&pVM->pgm.s.StatRCDynMapCacheMisses);
2016
2017 /*
2018 * Update the page tables.
2019 */
2020 register unsigned iPage = pVM->pgm.s.iDynPageMapLast;
2021 pVM->pgm.s.iDynPageMapLast = iPage = (iPage + 1) & ((MM_HYPER_DYNAMIC_SIZE >> PAGE_SHIFT) - 1);
2022 Assert((MM_HYPER_DYNAMIC_SIZE >> PAGE_SHIFT) == 8);
2023
2024 pVM->pgm.s.aHCPhysDynPageMapCache[iPage & (RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache) - 1)] = HCPhys;
2025 pVM->pgm.s.paDynPageMap32BitPTEsGC[iPage].u = (uint32_t)HCPhys | X86_PTE_P | X86_PTE_A | X86_PTE_D;
2026 pVM->pgm.s.paDynPageMapPaePTEsGC[iPage].u = HCPhys | X86_PTE_P | X86_PTE_A | X86_PTE_D;
2027
2028 void *pv = pVM->pgm.s.pbDynPageMapBaseGC + (iPage << PAGE_SHIFT);
2029 *ppv = pv;
2030 ASMInvalidatePage(pv);
2031 Log4(("PGMGCDynMapHCPage: HCPhys=%RHp pv=%p iPage=%d\n", HCPhys, pv, iPage));
2032 return VINF_SUCCESS;
2033}
2034# endif /* IN_RC */
2035
2036#endif /* IN_RC || VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
2037#ifdef VBOX_STRICT
2038
2039/**
2040 * Asserts that there are no mapping conflicts.
2041 *
2042 * @returns Number of conflicts.
2043 * @param pVM The VM Handle.
2044 */
2045VMMDECL(unsigned) PGMAssertNoMappingConflicts(PVM pVM)
2046{
2047 unsigned cErrors = 0;
2048
2049 /*
2050 * Check for mapping conflicts.
2051 */
2052 for (PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
2053 pMapping;
2054 pMapping = pMapping->CTX_SUFF(pNext))
2055 {
2056 /** @todo This is slow and should be optimized, but since it's just assertions I don't care now. */
2057 for (RTGCPTR GCPtr = pMapping->GCPtr;
2058 GCPtr <= pMapping->GCPtrLast;
2059 GCPtr += PAGE_SIZE)
2060 {
2061 int rc = PGMGstGetPage(pVM, (RTGCPTR)GCPtr, NULL, NULL);
2062 if (rc != VERR_PAGE_TABLE_NOT_PRESENT)
2063 {
2064 AssertMsgFailed(("Conflict at %RGv with %s\n", GCPtr, R3STRING(pMapping->pszDesc)));
2065 cErrors++;
2066 break;
2067 }
2068 }
2069 }
2070
2071 return cErrors;
2072}
2073
2074
2075/**
2076 * Asserts that everything related to the guest CR3 is correctly shadowed.
2077 *
2078 * This will call PGMAssertNoMappingConflicts() and PGMAssertHandlerAndFlagsInSync(),
2079 * and assert the correctness of the guest CR3 mapping before asserting that the
2080 * shadow page tables is in sync with the guest page tables.
2081 *
2082 * @returns Number of conflicts.
2083 * @param pVM The VM Handle.
2084 * @param cr3 The current guest CR3 register value.
2085 * @param cr4 The current guest CR4 register value.
2086 */
2087VMMDECL(unsigned) PGMAssertCR3(PVM pVM, uint64_t cr3, uint64_t cr4)
2088{
2089 STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3), a);
2090 unsigned cErrors = PGM_BTH_PFN(AssertCR3, pVM)(pVM, cr3, cr4, 0, ~(RTGCPTR)0);
2091 STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3), a);
2092 return cErrors;
2093 return 0;
2094}
2095
2096#endif /* VBOX_STRICT */
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