VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAll.cpp@ 16907

Last change on this file since 16907 was 16907, checked in by vboxsync, 16 years ago

VBOX_WITH_PGMPOOL_PAGING_ONLY: changes for marking root pages as special.
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1/* $Id: PGMAll.cpp 16907 2009-02-18 15:04:16Z vboxsync $ */
2/** @file
3 * PGM - Page Manager and Monitor - All context code.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22/*******************************************************************************
23* Header Files *
24*******************************************************************************/
25#define LOG_GROUP LOG_GROUP_PGM
26#include <VBox/pgm.h>
27#include <VBox/cpum.h>
28#include <VBox/selm.h>
29#include <VBox/iom.h>
30#include <VBox/sup.h>
31#include <VBox/mm.h>
32#include <VBox/stam.h>
33#include <VBox/csam.h>
34#include <VBox/patm.h>
35#include <VBox/trpm.h>
36#include <VBox/rem.h>
37#include <VBox/em.h>
38#include <VBox/hwaccm.h>
39#include <VBox/hwacc_vmx.h>
40#include "PGMInternal.h"
41#include <VBox/vm.h>
42#include <iprt/assert.h>
43#include <iprt/asm.h>
44#include <iprt/string.h>
45#include <VBox/log.h>
46#include <VBox/param.h>
47#include <VBox/err.h>
48
49
50/*******************************************************************************
51* Structures and Typedefs *
52*******************************************************************************/
53/**
54 * Stated structure for PGM_GST_NAME(HandlerVirtualUpdate) that's
55 * passed to PGM_GST_NAME(VirtHandlerUpdateOne) during enumeration.
56 */
57typedef struct PGMHVUSTATE
58{
59 /** The VM handle. */
60 PVM pVM;
61 /** The todo flags. */
62 RTUINT fTodo;
63 /** The CR4 register value. */
64 uint32_t cr4;
65} PGMHVUSTATE, *PPGMHVUSTATE;
66
67
68/*******************************************************************************
69* Internal Functions *
70*******************************************************************************/
71DECLINLINE(int) pgmShwGetLongModePDPtr(PVM pVM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPT *ppPdpt, PX86PDPAE *ppPD);
72DECLINLINE(int) pgmShwGetPAEPDPtr(PVM pVM, RTGCPTR GCPtr, PX86PDPT *ppPdpt, PX86PDPAE *ppPD);
73#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
74DECLINLINE(int) pgmShwGetPaePoolPagePD(PPGM pPGM, RTGCPTR GCPtr, PPGMPOOLPAGE *ppShwPde);
75#endif
76
77/*
78 * Shadow - 32-bit mode
79 */
80#define PGM_SHW_TYPE PGM_TYPE_32BIT
81#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
82#include "PGMAllShw.h"
83
84/* Guest - real mode */
85#define PGM_GST_TYPE PGM_TYPE_REAL
86#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
87#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
88#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
89#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
90#include "PGMAllGst.h"
91#include "PGMAllBth.h"
92#undef BTH_PGMPOOLKIND_PT_FOR_PT
93#undef BTH_PGMPOOLKIND_ROOT
94#undef PGM_BTH_NAME
95#undef PGM_GST_TYPE
96#undef PGM_GST_NAME
97
98/* Guest - protected mode */
99#define PGM_GST_TYPE PGM_TYPE_PROT
100#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
101#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
102#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
103#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
104#include "PGMAllGst.h"
105#include "PGMAllBth.h"
106#undef BTH_PGMPOOLKIND_PT_FOR_PT
107#undef BTH_PGMPOOLKIND_ROOT
108#undef PGM_BTH_NAME
109#undef PGM_GST_TYPE
110#undef PGM_GST_NAME
111
112/* Guest - 32-bit mode */
113#define PGM_GST_TYPE PGM_TYPE_32BIT
114#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
115#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
116#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
117#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
118#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD
119#include "PGMAllGst.h"
120#include "PGMAllBth.h"
121#undef BTH_PGMPOOLKIND_PT_FOR_BIG
122#undef BTH_PGMPOOLKIND_PT_FOR_PT
123#undef BTH_PGMPOOLKIND_ROOT
124#undef PGM_BTH_NAME
125#undef PGM_GST_TYPE
126#undef PGM_GST_NAME
127
128#undef PGM_SHW_TYPE
129#undef PGM_SHW_NAME
130
131
132/*
133 * Shadow - PAE mode
134 */
135#define PGM_SHW_TYPE PGM_TYPE_PAE
136#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
137#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
138#include "PGMAllShw.h"
139
140/* Guest - real mode */
141#define PGM_GST_TYPE PGM_TYPE_REAL
142#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
143#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
144#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
145#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
146#include "PGMAllBth.h"
147#undef BTH_PGMPOOLKIND_PT_FOR_PT
148#undef BTH_PGMPOOLKIND_ROOT
149#undef PGM_BTH_NAME
150#undef PGM_GST_TYPE
151#undef PGM_GST_NAME
152
153/* Guest - protected mode */
154#define PGM_GST_TYPE PGM_TYPE_PROT
155#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
156#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
157#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
158#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
159#include "PGMAllBth.h"
160#undef BTH_PGMPOOLKIND_PT_FOR_PT
161#undef BTH_PGMPOOLKIND_ROOT
162#undef PGM_BTH_NAME
163#undef PGM_GST_TYPE
164#undef PGM_GST_NAME
165
166/* Guest - 32-bit mode */
167#define PGM_GST_TYPE PGM_TYPE_32BIT
168#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
169#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
170#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
171#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
172#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_FOR_32BIT
173#include "PGMAllBth.h"
174#undef BTH_PGMPOOLKIND_PT_FOR_BIG
175#undef BTH_PGMPOOLKIND_PT_FOR_PT
176#undef BTH_PGMPOOLKIND_ROOT
177#undef PGM_BTH_NAME
178#undef PGM_GST_TYPE
179#undef PGM_GST_NAME
180
181
182/* Guest - PAE mode */
183#define PGM_GST_TYPE PGM_TYPE_PAE
184#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
185#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
186#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
187#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
188#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT
189#include "PGMAllGst.h"
190#include "PGMAllBth.h"
191#undef BTH_PGMPOOLKIND_PT_FOR_BIG
192#undef BTH_PGMPOOLKIND_PT_FOR_PT
193#undef BTH_PGMPOOLKIND_ROOT
194#undef PGM_BTH_NAME
195#undef PGM_GST_TYPE
196#undef PGM_GST_NAME
197
198#undef PGM_SHW_TYPE
199#undef PGM_SHW_NAME
200
201
202#ifndef IN_RC /* AMD64 implies VT-x/AMD-V */
203/*
204 * Shadow - AMD64 mode
205 */
206# define PGM_SHW_TYPE PGM_TYPE_AMD64
207# define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
208# include "PGMAllShw.h"
209
210/* Guest - protected mode (only used for AMD-V nested paging in 64 bits mode) */
211# define PGM_GST_TYPE PGM_TYPE_PROT
212# define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
213# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_PROT(name)
214# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
215# define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PD_PHYS
216# include "PGMAllBth.h"
217# undef BTH_PGMPOOLKIND_PT_FOR_PT
218# undef BTH_PGMPOOLKIND_ROOT
219# undef PGM_BTH_NAME
220# undef PGM_GST_TYPE
221# undef PGM_GST_NAME
222
223# ifdef VBOX_WITH_64_BITS_GUESTS
224/* Guest - AMD64 mode */
225# define PGM_GST_TYPE PGM_TYPE_AMD64
226# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
227# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
228# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
229# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
230# define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_64BIT_PML4
231# include "PGMAllGst.h"
232# include "PGMAllBth.h"
233# undef BTH_PGMPOOLKIND_PT_FOR_BIG
234# undef BTH_PGMPOOLKIND_PT_FOR_PT
235# undef BTH_PGMPOOLKIND_ROOT
236# undef PGM_BTH_NAME
237# undef PGM_GST_TYPE
238# undef PGM_GST_NAME
239# endif /* VBOX_WITH_64_BITS_GUESTS */
240
241# undef PGM_SHW_TYPE
242# undef PGM_SHW_NAME
243
244
245/*
246 * Shadow - Nested paging mode
247 */
248# define PGM_SHW_TYPE PGM_TYPE_NESTED
249# define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED(name)
250# include "PGMAllShw.h"
251
252/* Guest - real mode */
253# define PGM_GST_TYPE PGM_TYPE_REAL
254# define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
255# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_REAL(name)
256# include "PGMAllBth.h"
257# undef PGM_BTH_NAME
258# undef PGM_GST_TYPE
259# undef PGM_GST_NAME
260
261/* Guest - protected mode */
262# define PGM_GST_TYPE PGM_TYPE_PROT
263# define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
264# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PROT(name)
265# include "PGMAllBth.h"
266# undef PGM_BTH_NAME
267# undef PGM_GST_TYPE
268# undef PGM_GST_NAME
269
270/* Guest - 32-bit mode */
271# define PGM_GST_TYPE PGM_TYPE_32BIT
272# define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
273# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT(name)
274# include "PGMAllBth.h"
275# undef PGM_BTH_NAME
276# undef PGM_GST_TYPE
277# undef PGM_GST_NAME
278
279/* Guest - PAE mode */
280# define PGM_GST_TYPE PGM_TYPE_PAE
281# define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
282# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE(name)
283# include "PGMAllBth.h"
284# undef PGM_BTH_NAME
285# undef PGM_GST_TYPE
286# undef PGM_GST_NAME
287
288# ifdef VBOX_WITH_64_BITS_GUESTS
289/* Guest - AMD64 mode */
290# define PGM_GST_TYPE PGM_TYPE_AMD64
291# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
292# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64(name)
293# include "PGMAllBth.h"
294# undef PGM_BTH_NAME
295# undef PGM_GST_TYPE
296# undef PGM_GST_NAME
297# endif /* VBOX_WITH_64_BITS_GUESTS */
298
299# undef PGM_SHW_TYPE
300# undef PGM_SHW_NAME
301
302
303/*
304 * Shadow - EPT
305 */
306# define PGM_SHW_TYPE PGM_TYPE_EPT
307# define PGM_SHW_NAME(name) PGM_SHW_NAME_EPT(name)
308# include "PGMAllShw.h"
309
310/* Guest - real mode */
311# define PGM_GST_TYPE PGM_TYPE_REAL
312# define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
313# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_REAL(name)
314# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
315# include "PGMAllBth.h"
316# undef BTH_PGMPOOLKIND_PT_FOR_PT
317# undef PGM_BTH_NAME
318# undef PGM_GST_TYPE
319# undef PGM_GST_NAME
320
321/* Guest - protected mode */
322# define PGM_GST_TYPE PGM_TYPE_PROT
323# define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
324# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PROT(name)
325# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
326# include "PGMAllBth.h"
327# undef BTH_PGMPOOLKIND_PT_FOR_PT
328# undef PGM_BTH_NAME
329# undef PGM_GST_TYPE
330# undef PGM_GST_NAME
331
332/* Guest - 32-bit mode */
333# define PGM_GST_TYPE PGM_TYPE_32BIT
334# define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
335# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_32BIT(name)
336# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
337# include "PGMAllBth.h"
338# undef BTH_PGMPOOLKIND_PT_FOR_PT
339# undef PGM_BTH_NAME
340# undef PGM_GST_TYPE
341# undef PGM_GST_NAME
342
343/* Guest - PAE mode */
344# define PGM_GST_TYPE PGM_TYPE_PAE
345# define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
346# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PAE(name)
347# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
348# include "PGMAllBth.h"
349# undef BTH_PGMPOOLKIND_PT_FOR_PT
350# undef PGM_BTH_NAME
351# undef PGM_GST_TYPE
352# undef PGM_GST_NAME
353
354# ifdef VBOX_WITH_64_BITS_GUESTS
355/* Guest - AMD64 mode */
356# define PGM_GST_TYPE PGM_TYPE_AMD64
357# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
358# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_AMD64(name)
359# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
360# include "PGMAllBth.h"
361# undef BTH_PGMPOOLKIND_PT_FOR_PT
362# undef PGM_BTH_NAME
363# undef PGM_GST_TYPE
364# undef PGM_GST_NAME
365# endif /* VBOX_WITH_64_BITS_GUESTS */
366
367# undef PGM_SHW_TYPE
368# undef PGM_SHW_NAME
369
370#endif /* !IN_RC */
371
372
373#ifndef IN_RING3
374/**
375 * #PF Handler.
376 *
377 * @returns VBox status code (appropriate for trap handling and GC return).
378 * @param pVM VM Handle.
379 * @param uErr The trap error code.
380 * @param pRegFrame Trap register frame.
381 * @param pvFault The fault address.
382 */
383VMMDECL(int) PGMTrap0eHandler(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
384{
385 LogFlow(("PGMTrap0eHandler: uErr=%RGu pvFault=%RGv eip=%RGv\n", uErr, pvFault, (RTGCPTR)pRegFrame->rip));
386 STAM_PROFILE_START(&pVM->pgm.s.StatRZTrap0e, a);
387 STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = NULL; } );
388
389
390#ifdef VBOX_WITH_STATISTICS
391 /*
392 * Error code stats.
393 */
394 if (uErr & X86_TRAP_PF_US)
395 {
396 if (!(uErr & X86_TRAP_PF_P))
397 {
398 if (uErr & X86_TRAP_PF_RW)
399 STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eUSNotPresentWrite);
400 else
401 STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eUSNotPresentRead);
402 }
403 else if (uErr & X86_TRAP_PF_RW)
404 STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eUSWrite);
405 else if (uErr & X86_TRAP_PF_RSVD)
406 STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eUSReserved);
407 else if (uErr & X86_TRAP_PF_ID)
408 STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eUSNXE);
409 else
410 STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eUSRead);
411 }
412 else
413 { /* Supervisor */
414 if (!(uErr & X86_TRAP_PF_P))
415 {
416 if (uErr & X86_TRAP_PF_RW)
417 STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eSVNotPresentWrite);
418 else
419 STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eSVNotPresentRead);
420 }
421 else if (uErr & X86_TRAP_PF_RW)
422 STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eSVWrite);
423 else if (uErr & X86_TRAP_PF_ID)
424 STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eSNXE);
425 else if (uErr & X86_TRAP_PF_RSVD)
426 STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eSVReserved);
427 }
428#endif /* VBOX_WITH_STATISTICS */
429
430 /*
431 * Call the worker.
432 */
433 int rc = PGM_BTH_PFN(Trap0eHandler, pVM)(pVM, uErr, pRegFrame, pvFault);
434 if (rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
435 rc = VINF_SUCCESS;
436 STAM_STATS({ if (rc == VINF_EM_RAW_GUEST_TRAP) STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eGuestPF); });
437 STAM_STATS({ if (!pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution))
438 pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2Misc; });
439 STAM_PROFILE_STOP_EX(&pVM->pgm.s.StatRZTrap0e, pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution), a);
440 return rc;
441}
442#endif /* !IN_RING3 */
443
444
445/**
446 * Prefetch a page
447 *
448 * Typically used to sync commonly used pages before entering raw mode
449 * after a CR3 reload.
450 *
451 * @returns VBox status code suitable for scheduling.
452 * @retval VINF_SUCCESS on success.
453 * @retval VINF_PGM_SYNC_CR3 if we're out of shadow pages or something like that.
454 * @param pVM VM handle.
455 * @param GCPtrPage Page to invalidate.
456 */
457VMMDECL(int) PGMPrefetchPage(PVM pVM, RTGCPTR GCPtrPage)
458{
459 STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,Prefetch), a);
460 int rc = PGM_BTH_PFN(PrefetchPage, pVM)(pVM, GCPtrPage);
461 STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,Prefetch), a);
462 AssertMsg(rc == VINF_SUCCESS || rc == VINF_PGM_SYNC_CR3 || RT_FAILURE(rc), ("rc=%Rrc\n", rc));
463 return rc;
464}
465
466
467/**
468 * Gets the mapping corresponding to the specified address (if any).
469 *
470 * @returns Pointer to the mapping.
471 * @returns NULL if not
472 *
473 * @param pVM The virtual machine.
474 * @param GCPtr The guest context pointer.
475 */
476PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr)
477{
478 PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
479 while (pMapping)
480 {
481 if ((uintptr_t)GCPtr < (uintptr_t)pMapping->GCPtr)
482 break;
483 if ((uintptr_t)GCPtr - (uintptr_t)pMapping->GCPtr < pMapping->cb)
484 return pMapping;
485 pMapping = pMapping->CTX_SUFF(pNext);
486 }
487 return NULL;
488}
489
490
491/**
492 * Verifies a range of pages for read or write access
493 *
494 * Only checks the guest's page tables
495 *
496 * @returns VBox status code.
497 * @param pVM VM handle.
498 * @param Addr Guest virtual address to check
499 * @param cbSize Access size
500 * @param fAccess Access type (r/w, user/supervisor (X86_PTE_*))
501 * @remarks Current not in use.
502 */
503VMMDECL(int) PGMIsValidAccess(PVM pVM, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess)
504{
505 /*
506 * Validate input.
507 */
508 if (fAccess & ~(X86_PTE_US | X86_PTE_RW))
509 {
510 AssertMsgFailed(("PGMIsValidAccess: invalid access type %08x\n", fAccess));
511 return VERR_INVALID_PARAMETER;
512 }
513
514 uint64_t fPage;
515 int rc = PGMGstGetPage(pVM, (RTGCPTR)Addr, &fPage, NULL);
516 if (RT_FAILURE(rc))
517 {
518 Log(("PGMIsValidAccess: access violation for %RGv rc=%d\n", Addr, rc));
519 return VINF_EM_RAW_GUEST_TRAP;
520 }
521
522 /*
523 * Check if the access would cause a page fault
524 *
525 * Note that hypervisor page directories are not present in the guest's tables, so this check
526 * is sufficient.
527 */
528 bool fWrite = !!(fAccess & X86_PTE_RW);
529 bool fUser = !!(fAccess & X86_PTE_US);
530 if ( !(fPage & X86_PTE_P)
531 || (fWrite && !(fPage & X86_PTE_RW))
532 || (fUser && !(fPage & X86_PTE_US)) )
533 {
534 Log(("PGMIsValidAccess: access violation for %RGv attr %#llx vs %d:%d\n", Addr, fPage, fWrite, fUser));
535 return VINF_EM_RAW_GUEST_TRAP;
536 }
537 if ( RT_SUCCESS(rc)
538 && PAGE_ADDRESS(Addr) != PAGE_ADDRESS(Addr + cbSize))
539 return PGMIsValidAccess(pVM, Addr + PAGE_SIZE, (cbSize > PAGE_SIZE) ? cbSize - PAGE_SIZE : 1, fAccess);
540 return rc;
541}
542
543
544/**
545 * Verifies a range of pages for read or write access
546 *
547 * Supports handling of pages marked for dirty bit tracking and CSAM
548 *
549 * @returns VBox status code.
550 * @param pVM VM handle.
551 * @param Addr Guest virtual address to check
552 * @param cbSize Access size
553 * @param fAccess Access type (r/w, user/supervisor (X86_PTE_*))
554 */
555VMMDECL(int) PGMVerifyAccess(PVM pVM, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess)
556{
557 AssertMsg(!(fAccess & ~(X86_PTE_US | X86_PTE_RW)), ("PGMVerifyAccess: invalid access type %08x\n", fAccess));
558
559 /*
560 * Get going.
561 */
562 uint64_t fPageGst;
563 int rc = PGMGstGetPage(pVM, (RTGCPTR)Addr, &fPageGst, NULL);
564 if (RT_FAILURE(rc))
565 {
566 Log(("PGMVerifyAccess: access violation for %RGv rc=%d\n", Addr, rc));
567 return VINF_EM_RAW_GUEST_TRAP;
568 }
569
570 /*
571 * Check if the access would cause a page fault
572 *
573 * Note that hypervisor page directories are not present in the guest's tables, so this check
574 * is sufficient.
575 */
576 const bool fWrite = !!(fAccess & X86_PTE_RW);
577 const bool fUser = !!(fAccess & X86_PTE_US);
578 if ( !(fPageGst & X86_PTE_P)
579 || (fWrite && !(fPageGst & X86_PTE_RW))
580 || (fUser && !(fPageGst & X86_PTE_US)) )
581 {
582 Log(("PGMVerifyAccess: access violation for %RGv attr %#llx vs %d:%d\n", Addr, fPageGst, fWrite, fUser));
583 return VINF_EM_RAW_GUEST_TRAP;
584 }
585
586 if (!HWACCMIsNestedPagingActive(pVM))
587 {
588 /*
589 * Next step is to verify if we protected this page for dirty bit tracking or for CSAM scanning
590 */
591 rc = PGMShwGetPage(pVM, (RTGCPTR)Addr, NULL, NULL);
592 if ( rc == VERR_PAGE_NOT_PRESENT
593 || rc == VERR_PAGE_TABLE_NOT_PRESENT)
594 {
595 /*
596 * Page is not present in our page tables.
597 * Try to sync it!
598 */
599 Assert(X86_TRAP_PF_RW == X86_PTE_RW && X86_TRAP_PF_US == X86_PTE_US);
600 uint32_t uErr = fAccess & (X86_TRAP_PF_RW | X86_TRAP_PF_US);
601 rc = PGM_BTH_PFN(VerifyAccessSyncPage, pVM)(pVM, Addr, fPageGst, uErr);
602 if (rc != VINF_SUCCESS)
603 return rc;
604 }
605 else
606 AssertMsg(rc == VINF_SUCCESS, ("PGMShwGetPage %RGv failed with %Rrc\n", Addr, rc));
607 }
608
609#if 0 /* def VBOX_STRICT; triggers too often now */
610 /*
611 * This check is a bit paranoid, but useful.
612 */
613 /** @note this will assert when writing to monitored pages (a bit annoying actually) */
614 uint64_t fPageShw;
615 rc = PGMShwGetPage(pVM, (RTGCPTR)Addr, &fPageShw, NULL);
616 if ( (rc == VERR_PAGE_NOT_PRESENT || RT_FAILURE(rc))
617 || (fWrite && !(fPageShw & X86_PTE_RW))
618 || (fUser && !(fPageShw & X86_PTE_US)) )
619 {
620 AssertMsgFailed(("Unexpected access violation for %RGv! rc=%Rrc write=%d user=%d\n",
621 Addr, rc, fWrite && !(fPageShw & X86_PTE_RW), fUser && !(fPageShw & X86_PTE_US)));
622 return VINF_EM_RAW_GUEST_TRAP;
623 }
624#endif
625
626 if ( RT_SUCCESS(rc)
627 && ( PAGE_ADDRESS(Addr) != PAGE_ADDRESS(Addr + cbSize - 1)
628 || Addr + cbSize < Addr))
629 {
630 /* Don't recursively call PGMVerifyAccess as we might run out of stack. */
631 for (;;)
632 {
633 Addr += PAGE_SIZE;
634 if (cbSize > PAGE_SIZE)
635 cbSize -= PAGE_SIZE;
636 else
637 cbSize = 1;
638 rc = PGMVerifyAccess(pVM, Addr, 1, fAccess);
639 if (rc != VINF_SUCCESS)
640 break;
641 if (PAGE_ADDRESS(Addr) == PAGE_ADDRESS(Addr + cbSize - 1))
642 break;
643 }
644 }
645 return rc;
646}
647
648
649/**
650 * Emulation of the invlpg instruction (HC only actually).
651 *
652 * @returns VBox status code, special care required.
653 * @retval VINF_PGM_SYNC_CR3 - handled.
654 * @retval VINF_EM_RAW_EMULATE_INSTR - not handled (RC only).
655 * @retval VERR_REM_FLUSHED_PAGES_OVERFLOW - not handled.
656 *
657 * @param pVM VM handle.
658 * @param GCPtrPage Page to invalidate.
659 *
660 * @remark ASSUMES the page table entry or page directory is valid. Fairly
661 * safe, but there could be edge cases!
662 *
663 * @todo Flush page or page directory only if necessary!
664 */
665VMMDECL(int) PGMInvalidatePage(PVM pVM, RTGCPTR GCPtrPage)
666{
667 int rc;
668 Log3(("PGMInvalidatePage: GCPtrPage=%RGv\n", GCPtrPage));
669
670#ifndef IN_RING3
671 /*
672 * Notify the recompiler so it can record this instruction.
673 * Failure happens when it's out of space. We'll return to HC in that case.
674 */
675 rc = REMNotifyInvalidatePage(pVM, GCPtrPage);
676 if (rc != VINF_SUCCESS)
677 return rc;
678#endif /* !IN_RING3 */
679
680
681#ifdef IN_RC
682 /*
683 * Check for conflicts and pending CR3 monitoring updates.
684 */
685 if (!pVM->pgm.s.fMappingsFixed)
686 {
687 if ( pgmGetMapping(pVM, GCPtrPage)
688 && PGMGstGetPage(pVM, GCPtrPage, NULL, NULL) != VERR_PAGE_TABLE_NOT_PRESENT)
689 {
690 LogFlow(("PGMGCInvalidatePage: Conflict!\n"));
691 VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
692 STAM_COUNTER_INC(&pVM->pgm.s.StatRCInvlPgConflict);
693 return VINF_PGM_SYNC_CR3;
694 }
695
696 if (pVM->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
697 {
698 LogFlow(("PGMGCInvalidatePage: PGM_SYNC_MONITOR_CR3 -> reinterpret instruction in R3\n"));
699 STAM_COUNTER_INC(&pVM->pgm.s.StatRCInvlPgSyncMonCR3);
700 return VINF_EM_RAW_EMULATE_INSTR;
701 }
702 }
703#endif /* IN_RC */
704
705 /*
706 * Call paging mode specific worker.
707 */
708 STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePage), a);
709 rc = PGM_BTH_PFN(InvalidatePage, pVM)(pVM, GCPtrPage);
710 STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePage), a);
711
712#ifdef IN_RING3
713 /*
714 * Check if we have a pending update of the CR3 monitoring.
715 */
716 if ( RT_SUCCESS(rc)
717 && (pVM->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3))
718 {
719 pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
720 Assert(!pVM->pgm.s.fMappingsFixed);
721 Assert(pVM->pgm.s.GCPhysCR3 == pVM->pgm.s.GCPhysGstCR3Monitored);
722 rc = PGM_GST_PFN(MonitorCR3, pVM)(pVM, pVM->pgm.s.GCPhysCR3);
723 }
724
725 /*
726 * Inform CSAM about the flush
727 *
728 * Note: This is to check if monitored pages have been changed; when we implement
729 * callbacks for virtual handlers, this is no longer required.
730 */
731 CSAMR3FlushPage(pVM, GCPtrPage);
732#endif /* IN_RING3 */
733 return rc;
734}
735
736
737/**
738 * Executes an instruction using the interpreter.
739 *
740 * @returns VBox status code (appropriate for trap handling and GC return).
741 * @param pVM VM handle.
742 * @param pRegFrame Register frame.
743 * @param pvFault Fault address.
744 */
745VMMDECL(int) PGMInterpretInstruction(PVM pVM, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
746{
747 uint32_t cb;
748 int rc = EMInterpretInstruction(pVM, pRegFrame, pvFault, &cb);
749 if (rc == VERR_EM_INTERPRETER)
750 rc = VINF_EM_RAW_EMULATE_INSTR;
751 if (rc != VINF_SUCCESS)
752 Log(("PGMInterpretInstruction: returns %Rrc (pvFault=%RGv)\n", rc, pvFault));
753 return rc;
754}
755
756
757/**
758 * Gets effective page information (from the VMM page directory).
759 *
760 * @returns VBox status.
761 * @param pVM VM Handle.
762 * @param GCPtr Guest Context virtual address of the page.
763 * @param pfFlags Where to store the flags. These are X86_PTE_*.
764 * @param pHCPhys Where to store the HC physical address of the page.
765 * This is page aligned.
766 * @remark You should use PGMMapGetPage() for pages in a mapping.
767 */
768VMMDECL(int) PGMShwGetPage(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys)
769{
770 return PGM_SHW_PFN(GetPage,pVM)(pVM, GCPtr, pfFlags, pHCPhys);
771}
772
773
774/**
775 * Sets (replaces) the page flags for a range of pages in the shadow context.
776 *
777 * @returns VBox status.
778 * @param pVM VM handle.
779 * @param GCPtr The address of the first page.
780 * @param cb The size of the range in bytes.
781 * @param fFlags Page flags X86_PTE_*, excluding the page mask of course.
782 * @remark You must use PGMMapSetPage() for pages in a mapping.
783 */
784VMMDECL(int) PGMShwSetPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags)
785{
786 return PGMShwModifyPage(pVM, GCPtr, cb, fFlags, 0);
787}
788
789
790/**
791 * Modify page flags for a range of pages in the shadow context.
792 *
793 * The existing flags are ANDed with the fMask and ORed with the fFlags.
794 *
795 * @returns VBox status code.
796 * @param pVM VM handle.
797 * @param GCPtr Virtual address of the first page in the range.
798 * @param cb Size (in bytes) of the range to apply the modification to.
799 * @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
800 * @param fMask The AND mask - page flags X86_PTE_*.
801 * Be very CAREFUL when ~'ing constants which could be 32-bit!
802 * @remark You must use PGMMapModifyPage() for pages in a mapping.
803 */
804VMMDECL(int) PGMShwModifyPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
805{
806 AssertMsg(!(fFlags & X86_PTE_PAE_PG_MASK), ("fFlags=%#llx\n", fFlags));
807 Assert(cb);
808
809 /*
810 * Align the input.
811 */
812 cb += GCPtr & PAGE_OFFSET_MASK;
813 cb = RT_ALIGN_Z(cb, PAGE_SIZE);
814 GCPtr = (GCPtr & PAGE_BASE_GC_MASK); /** @todo this ain't necessary, right... */
815
816 /*
817 * Call worker.
818 */
819 return PGM_SHW_PFN(ModifyPage, pVM)(pVM, GCPtr, cb, fFlags, fMask);
820}
821
822
823/**
824 * Gets the SHADOW page directory pointer for the specified address.
825 *
826 * @returns VBox status.
827 * @param pVM VM handle.
828 * @param GCPtr The address.
829 * @param ppPdpt Receives address of pdpt
830 * @param ppPD Receives address of page directory
831 * @remarks Unused.
832 */
833DECLINLINE(int) pgmShwGetPAEPDPtr(PVM pVM, RTGCPTR GCPtr, PX86PDPT *ppPdpt, PX86PDPAE *ppPD)
834{
835 PPGM pPGM = &pVM->pgm.s;
836 PPGMPOOL pPool = pPGM->CTX_SUFF(pPool);
837 PPGMPOOLPAGE pShwPage;
838
839 Assert(!HWACCMIsNestedPagingActive(pVM));
840
841 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
842 PX86PDPT pPdpt = pgmShwGetPaePDPTPtr(&pVM->pgm.s);
843 PX86PDPE pPdpe = &pPdpt->a[iPdPt];
844
845 *ppPdpt = pPdpt;
846 if (!pPdpe->n.u1Present)
847 return VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT;
848
849 pShwPage = pgmPoolGetPage(pPool, pPdpe->u & X86_PDPE_PG_MASK);
850 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
851
852 *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
853 return VINF_SUCCESS;
854}
855
856#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
857
858/**
859 * Gets the shadow page directory for the specified address, PAE.
860 *
861 * @returns Pointer to the shadow PD.
862 * @param pVM VM handle.
863 * @param GCPtr The address.
864 * @param pGstPdpe Guest PDPT entry
865 * @param ppPD Receives address of page directory
866 */
867int pgmShwSyncPaePDPtr(PVM pVM, RTGCPTR GCPtr, PX86PDPE pGstPdpe, PX86PDPAE *ppPD)
868{
869 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
870 PX86PDPT pPdpt = pgmShwGetPaePDPTPtr(&pVM->pgm.s);
871 PX86PDPE pPdpe = &pPdpt->a[iPdPt];
872 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
873 PPGMPOOLPAGE pShwPage;
874 int rc;
875
876 /* Allocate page directory if not present. */
877 if ( !pPdpe->n.u1Present
878 && !(pPdpe->u & X86_PDPE_PG_MASK))
879 {
880 bool fNestedPaging = HWACCMIsNestedPagingActive(pVM);
881 bool fPaging = !!(CPUMGetGuestCR0(pVM) & X86_CR0_PG);
882 RTGCPTR64 GCPdPt;
883 PGMPOOLKIND enmKind;
884
885 if (fNestedPaging || !fPaging)
886 {
887 /* AMD-V nested paging or real/protected mode without paging */
888 GCPdPt = (RTGCPTR64)iPdPt << X86_PDPT_SHIFT;
889 enmKind = PGMPOOLKIND_PAE_PD_PHYS;
890 }
891 else
892 {
893 Assert(pGstPdpe);
894
895 if (CPUMGetGuestCR4(pVM) & X86_CR4_PAE)
896 {
897 GCPdPt = pGstPdpe->u & X86_PDPE_PG_MASK;
898 enmKind = PGMPOOLKIND_PAE_PD_FOR_PAE_PD;
899 }
900 else
901 {
902 GCPdPt = CPUMGetGuestCR3(pVM);
903 enmKind = (PGMPOOLKIND)(PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD + iPdPt);
904 }
905 }
906
907 /* Create a reference back to the PDPT by using the index in its shadow page. */
908 rc = pgmPoolAlloc(pVM, GCPdPt, enmKind, pVM->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPdPt, &pShwPage);
909 if (rc == VERR_PGM_POOL_FLUSHED)
910 {
911 Log(("pgmShwSyncPaePDPtr: PGM pool flushed -> signal sync cr3\n"));
912 Assert(pVM->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL);
913 VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
914 return VINF_PGM_SYNC_CR3;
915 }
916 AssertRCReturn(rc, rc);
917 }
918 else
919 {
920 pShwPage = pgmPoolGetPage(pPool, pPdpe->u & X86_PDPE_PG_MASK);
921 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
922 }
923 /* The PD was cached or created; hook it up now. */
924 pPdpe->u |= pShwPage->Core.Key
925 | (pGstPdpe->u & ~(X86_PDPE_PG_MASK | X86_PDPE_AVL_MASK | X86_PDPE_PCD | X86_PDPE_PWT));
926
927 *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
928 return VINF_SUCCESS;
929}
930
931/**
932 * Gets the pointer to the shadow page directory entry for an address, PAE.
933 *
934 * @returns Pointer to the PDE.
935 * @param pPGM Pointer to the PGM instance data.
936 * @param GCPtr The address.
937 * @param ppShwPde Receives the address of the pgm pool page for the shadow page directory
938 */
939DECLINLINE(int) pgmShwGetPaePoolPagePD(PPGM pPGM, RTGCPTR GCPtr, PPGMPOOLPAGE *ppShwPde)
940{
941 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
942 PX86PDPT pPdpt = pgmShwGetPaePDPTPtr(pPGM);
943 AssertReturn(pPdpt, VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT); /* can't happen */
944 if (!pPdpt->a[iPdPt].n.u1Present)
945 return VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT;
946
947 /* Fetch the pgm pool shadow descriptor. */
948 PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(PGM2VM(pPGM), pPdpt->a[iPdPt].u & X86_PDPE_PG_MASK);
949 AssertReturn(pShwPde, VERR_INTERNAL_ERROR);
950
951 *ppShwPde = pShwPde;
952 return VINF_SUCCESS;
953}
954#endif
955
956#ifndef IN_RC
957
958/**
959 * Syncs the SHADOW page directory pointer for the specified address.
960 *
961 * Allocates backing pages in case the PDPT or PML4 entry is missing.
962 *
963 * The caller is responsible for making sure the guest has a valid PD before
964 * calling this function.
965 *
966 * @returns VBox status.
967 * @param pVM VM handle.
968 * @param GCPtr The address.
969 * @param pGstPml4e Guest PML4 entry
970 * @param pGstPdpe Guest PDPT entry
971 * @param ppPD Receives address of page directory
972 */
973int pgmShwSyncLongModePDPtr(PVM pVM, RTGCPTR64 GCPtr, PX86PML4E pGstPml4e, PX86PDPE pGstPdpe, PX86PDPAE *ppPD)
974{
975 PPGM pPGM = &pVM->pgm.s;
976 PPGMPOOL pPool = pPGM->CTX_SUFF(pPool);
977 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
978 PX86PML4E pPml4e = pgmShwGetLongModePML4EPtr(pPGM, iPml4);
979 bool fNestedPaging = HWACCMIsNestedPagingActive(pVM);
980#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
981 bool fPaging = !!(CPUMGetGuestCR0(pVM) & X86_CR0_PG);
982#endif
983 PPGMPOOLPAGE pShwPage;
984 int rc;
985
986 /* Allocate page directory pointer table if not present. */
987 if ( !pPml4e->n.u1Present
988 && !(pPml4e->u & X86_PML4E_PG_MASK))
989 {
990#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
991 RTGCPTR64 GCPml4;
992 PGMPOOLKIND enmKind;
993
994 Assert(pVM->pgm.s.CTX_SUFF(pShwPageCR3));
995
996 if (fNestedPaging || !fPaging)
997 {
998 /* AMD-V nested paging or real/protected mode without paging */
999 GCPml4 = (RTGCPTR64)iPml4 << X86_PML4_SHIFT;
1000 enmKind = PGMPOOLKIND_64BIT_PDPT_FOR_PHYS;
1001 }
1002 else
1003 {
1004 Assert(pGstPml4e && pGstPdpe);
1005
1006 GCPml4 = pGstPml4e->u & X86_PML4E_PG_MASK;
1007 enmKind = PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT;
1008 }
1009
1010 /* Create a reference back to the PDPT by using the index in its shadow page. */
1011 rc = pgmPoolAlloc(pVM, GCPml4, enmKind, pVM->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPml4, &pShwPage);
1012#else
1013 if (!fNestedPaging)
1014 {
1015 Assert(pGstPml4e && pGstPdpe);
1016 Assert(pVM->pgm.s.CTX_SUFF(pShwPageCR3));
1017
1018 rc = pgmPoolAlloc(pVM, pGstPml4e->u & X86_PML4E_PG_MASK,
1019 PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT, pVM->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPml4, &pShwPage);
1020 }
1021 else
1022 {
1023 /* AMD-V nested paging. (Intel EPT never comes here) */
1024 RTGCPTR64 GCPml4 = (RTGCPTR64)iPml4 << EPT_PML4_SHIFT;
1025 rc = pgmPoolAlloc(pVM, GCPml4 + RT_BIT_64(63) /* hack: make the address unique */,
1026 PGMPOOLKIND_64BIT_PDPT_FOR_PHYS, PGMPOOL_IDX_NESTED_ROOT, iPml4, &pShwPage);
1027 }
1028#endif
1029 if (rc == VERR_PGM_POOL_FLUSHED)
1030 {
1031 Log(("PGMShwSyncLongModePDPtr: PGM pool flushed (1) -> signal sync cr3\n"));
1032 Assert(pVM->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL);
1033 VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
1034 return VINF_PGM_SYNC_CR3;
1035 }
1036 AssertRCReturn(rc, rc);
1037 }
1038 else
1039 {
1040 pShwPage = pgmPoolGetPage(pPool, pPml4e->u & X86_PML4E_PG_MASK);
1041 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1042 }
1043 /* The PDPT was cached or created; hook it up now. */
1044 pPml4e->u |= pShwPage->Core.Key
1045 | (pGstPml4e->u & ~(X86_PML4E_PG_MASK | X86_PML4E_AVL_MASK | X86_PML4E_PCD | X86_PML4E_PWT));
1046
1047 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1048 PX86PDPT pPdpt = (PX86PDPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1049 PX86PDPE pPdpe = &pPdpt->a[iPdPt];
1050
1051 /* Allocate page directory if not present. */
1052 if ( !pPdpe->n.u1Present
1053 && !(pPdpe->u & X86_PDPE_PG_MASK))
1054 {
1055#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
1056 RTGCPTR64 GCPdPt;
1057 PGMPOOLKIND enmKind;
1058
1059 if (fNestedPaging || !fPaging)
1060 {
1061 /* AMD-V nested paging or real/protected mode without paging */
1062 GCPdPt = (RTGCPTR64)iPdPt << X86_PDPT_SHIFT;
1063 enmKind = PGMPOOLKIND_64BIT_PD_FOR_PHYS;
1064 }
1065 else
1066 {
1067 Assert(pGstPdpe);
1068
1069 GCPdPt = pGstPdpe->u & X86_PDPE_PG_MASK;
1070 enmKind = PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD;
1071 }
1072
1073 /* Create a reference back to the PDPT by using the index in its shadow page. */
1074 rc = pgmPoolAlloc(pVM, GCPdPt, enmKind, pShwPage->idx, iPdPt, &pShwPage);
1075#else
1076 if (!fNestedPaging)
1077 {
1078 Assert(pGstPml4e && pGstPdpe);
1079 Assert(!(pPdpe->u & X86_PDPE_PG_MASK));
1080 /* Create a reference back to the PDPT by using the index in its shadow page. */
1081 rc = pgmPoolAlloc(pVM, pGstPdpe->u & X86_PDPE_PG_MASK, PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD, pShwPage->idx, iPdPt, &pShwPage);
1082 }
1083 else
1084 {
1085 /* AMD-V nested paging. (Intel EPT never comes here) */
1086 RTGCPTR64 GCPdPt = (RTGCPTR64)iPdPt << EPT_PDPT_SHIFT;
1087
1088 rc = pgmPoolAlloc(pVM, GCPdPt + RT_BIT_64(62) /* hack: make the address unique */, PGMPOOLKIND_64BIT_PD_FOR_PHYS, pShwPage->idx, iPdPt, &pShwPage);
1089 }
1090#endif
1091 if (rc == VERR_PGM_POOL_FLUSHED)
1092 {
1093 Log(("PGMShwSyncLongModePDPtr: PGM pool flushed (2) -> signal sync cr3\n"));
1094 Assert(pVM->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL);
1095 VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
1096 return VINF_PGM_SYNC_CR3;
1097 }
1098 AssertRCReturn(rc, rc);
1099 }
1100 else
1101 {
1102 pShwPage = pgmPoolGetPage(pPool, pPdpe->u & X86_PDPE_PG_MASK);
1103 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1104 }
1105 /* The PD was cached or created; hook it up now. */
1106 pPdpe->u |= pShwPage->Core.Key
1107 | (pGstPdpe->u & ~(X86_PDPE_PG_MASK | X86_PDPE_AVL_MASK | X86_PDPE_PCD | X86_PDPE_PWT));
1108
1109 *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1110 return VINF_SUCCESS;
1111}
1112
1113
1114/**
1115 * Gets the SHADOW page directory pointer for the specified address (long mode).
1116 *
1117 * @returns VBox status.
1118 * @param pVM VM handle.
1119 * @param GCPtr The address.
1120 * @param ppPdpt Receives address of pdpt
1121 * @param ppPD Receives address of page directory
1122 */
1123DECLINLINE(int) pgmShwGetLongModePDPtr(PVM pVM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPT *ppPdpt, PX86PDPAE *ppPD)
1124{
1125 PPGM pPGM = &pVM->pgm.s;
1126 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
1127 PCX86PML4E pPml4e = pgmShwGetLongModePML4EPtr(pPGM, iPml4);
1128 AssertReturn(pPml4e, VERR_INTERNAL_ERROR);
1129 if (ppPml4e)
1130 *ppPml4e = (PX86PML4E)pPml4e;
1131 if (!pPml4e->n.u1Present)
1132 return VERR_PAGE_MAP_LEVEL4_NOT_PRESENT;
1133
1134 PPGMPOOL pPool = pPGM->CTX_SUFF(pPool);
1135 PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPml4e->u & X86_PML4E_PG_MASK);
1136 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1137
1138 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1139 PCX86PDPT pPdpt = *ppPdpt = (PX86PDPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1140 if (!pPdpt->a[iPdPt].n.u1Present)
1141 return VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT;
1142
1143 pShwPage = pgmPoolGetPage(pPool, pPdpt->a[iPdPt].u & X86_PDPE_PG_MASK);
1144 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1145
1146 *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1147 return VINF_SUCCESS;
1148}
1149
1150
1151/**
1152 * Syncs the SHADOW EPT page directory pointer for the specified address. Allocates
1153 * backing pages in case the PDPT or PML4 entry is missing.
1154 *
1155 * @returns VBox status.
1156 * @param pVM VM handle.
1157 * @param GCPtr The address.
1158 * @param ppPdpt Receives address of pdpt
1159 * @param ppPD Receives address of page directory
1160 */
1161int pgmShwGetEPTPDPtr(PVM pVM, RTGCPTR64 GCPtr, PEPTPDPT *ppPdpt, PEPTPD *ppPD)
1162{
1163 PPGM pPGM = &pVM->pgm.s;
1164 const unsigned iPml4 = (GCPtr >> EPT_PML4_SHIFT) & EPT_PML4_MASK;
1165 PPGMPOOL pPool = pPGM->CTX_SUFF(pPool);
1166 PEPTPML4 pPml4;
1167 PEPTPML4E pPml4e;
1168 PPGMPOOLPAGE pShwPage;
1169 int rc;
1170
1171 Assert(HWACCMIsNestedPagingActive(pVM));
1172
1173# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
1174 rc = PGM_HCPHYS_2_PTR(pVM, pPGM->HCPhysShwNestedRoot, &pPml4);
1175 AssertRCReturn(rc, rc);
1176# else
1177 pPml4 = (PEPTPML4)pPGM->CTX_SUFF(pShwNestedRoot);
1178# endif
1179 Assert(pPml4);
1180
1181 /* Allocate page directory pointer table if not present. */
1182 pPml4e = &pPml4->a[iPml4];
1183 if ( !pPml4e->n.u1Present
1184 && !(pPml4e->u & EPT_PML4E_PG_MASK))
1185 {
1186 Assert(!(pPml4e->u & EPT_PML4E_PG_MASK));
1187 RTGCPTR64 GCPml4 = (RTGCPTR64)iPml4 << EPT_PML4_SHIFT;
1188
1189#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
1190 rc = pgmPoolAlloc(pVM, GCPml4, PGMPOOLKIND_EPT_PDPT_FOR_PHYS, PGMPOOL_IDX_NESTED_ROOT, iPml4, &pShwPage);
1191#else
1192 rc = pgmPoolAlloc(pVM, GCPml4 + RT_BIT_64(63) /* hack: make the address unique */, PGMPOOLKIND_EPT_PDPT_FOR_PHYS, PGMPOOL_IDX_NESTED_ROOT, iPml4, &pShwPage);
1193#endif
1194 if (rc == VERR_PGM_POOL_FLUSHED)
1195 {
1196 Log(("PGMShwSyncEPTPDPtr: PGM pool flushed (1) -> signal sync cr3\n"));
1197 Assert(pVM->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL);
1198 VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
1199 return VINF_PGM_SYNC_CR3;
1200 }
1201 AssertRCReturn(rc, rc);
1202 }
1203 else
1204 {
1205 pShwPage = pgmPoolGetPage(pPool, pPml4e->u & EPT_PML4E_PG_MASK);
1206 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1207 }
1208 /* The PDPT was cached or created; hook it up now and fill with the default value. */
1209 pPml4e->u = pShwPage->Core.Key;
1210 pPml4e->n.u1Present = 1;
1211 pPml4e->n.u1Write = 1;
1212 pPml4e->n.u1Execute = 1;
1213
1214 const unsigned iPdPt = (GCPtr >> EPT_PDPT_SHIFT) & EPT_PDPT_MASK;
1215 PEPTPDPT pPdpt = (PEPTPDPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1216 PEPTPDPTE pPdpe = &pPdpt->a[iPdPt];
1217
1218 if (ppPdpt)
1219 *ppPdpt = pPdpt;
1220
1221 /* Allocate page directory if not present. */
1222 if ( !pPdpe->n.u1Present
1223 && !(pPdpe->u & EPT_PDPTE_PG_MASK))
1224 {
1225 RTGCPTR64 GCPdPt = (RTGCPTR64)iPdPt << EPT_PDPT_SHIFT;
1226
1227#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
1228 rc = pgmPoolAlloc(pVM, GCPdPt, PGMPOOLKIND_64BIT_PD_FOR_PHYS, pShwPage->idx, iPdPt, &pShwPage);
1229#else
1230 rc = pgmPoolAlloc(pVM, GCPdPt + RT_BIT_64(62) /* hack: make the address unique */, PGMPOOLKIND_64BIT_PD_FOR_PHYS, pShwPage->idx, iPdPt, &pShwPage);
1231#endif
1232 if (rc == VERR_PGM_POOL_FLUSHED)
1233 {
1234 Log(("PGMShwSyncEPTPDPtr: PGM pool flushed (2) -> signal sync cr3\n"));
1235 Assert(pVM->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL);
1236 VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
1237 return VINF_PGM_SYNC_CR3;
1238 }
1239 AssertRCReturn(rc, rc);
1240 }
1241 else
1242 {
1243 pShwPage = pgmPoolGetPage(pPool, pPdpe->u & EPT_PDPTE_PG_MASK);
1244 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1245 }
1246 /* The PD was cached or created; hook it up now and fill with the default value. */
1247 pPdpe->u = pShwPage->Core.Key;
1248 pPdpe->n.u1Present = 1;
1249 pPdpe->n.u1Write = 1;
1250 pPdpe->n.u1Execute = 1;
1251
1252 *ppPD = (PEPTPD)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1253 return VINF_SUCCESS;
1254}
1255
1256#endif /* IN_RC */
1257
1258/**
1259 * Gets effective Guest OS page information.
1260 *
1261 * When GCPtr is in a big page, the function will return as if it was a normal
1262 * 4KB page. If the need for distinguishing between big and normal page becomes
1263 * necessary at a later point, a PGMGstGetPage() will be created for that
1264 * purpose.
1265 *
1266 * @returns VBox status.
1267 * @param pVM VM Handle.
1268 * @param GCPtr Guest Context virtual address of the page.
1269 * @param pfFlags Where to store the flags. These are X86_PTE_*, even for big pages.
1270 * @param pGCPhys Where to store the GC physical address of the page.
1271 * This is page aligned. The fact that the
1272 */
1273VMMDECL(int) PGMGstGetPage(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys)
1274{
1275 return PGM_GST_PFN(GetPage,pVM)(pVM, GCPtr, pfFlags, pGCPhys);
1276}
1277
1278
1279/**
1280 * Checks if the page is present.
1281 *
1282 * @returns true if the page is present.
1283 * @returns false if the page is not present.
1284 * @param pVM The VM handle.
1285 * @param GCPtr Address within the page.
1286 */
1287VMMDECL(bool) PGMGstIsPagePresent(PVM pVM, RTGCPTR GCPtr)
1288{
1289 int rc = PGMGstGetPage(pVM, GCPtr, NULL, NULL);
1290 return RT_SUCCESS(rc);
1291}
1292
1293
1294/**
1295 * Sets (replaces) the page flags for a range of pages in the guest's tables.
1296 *
1297 * @returns VBox status.
1298 * @param pVM VM handle.
1299 * @param GCPtr The address of the first page.
1300 * @param cb The size of the range in bytes.
1301 * @param fFlags Page flags X86_PTE_*, excluding the page mask of course.
1302 */
1303VMMDECL(int) PGMGstSetPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags)
1304{
1305 return PGMGstModifyPage(pVM, GCPtr, cb, fFlags, 0);
1306}
1307
1308
1309/**
1310 * Modify page flags for a range of pages in the guest's tables
1311 *
1312 * The existing flags are ANDed with the fMask and ORed with the fFlags.
1313 *
1314 * @returns VBox status code.
1315 * @param pVM VM handle.
1316 * @param GCPtr Virtual address of the first page in the range.
1317 * @param cb Size (in bytes) of the range to apply the modification to.
1318 * @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
1319 * @param fMask The AND mask - page flags X86_PTE_*, excluding the page mask of course.
1320 * Be very CAREFUL when ~'ing constants which could be 32-bit!
1321 */
1322VMMDECL(int) PGMGstModifyPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
1323{
1324 STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,GstModifyPage), a);
1325
1326 /*
1327 * Validate input.
1328 */
1329 AssertMsg(!(fFlags & X86_PTE_PAE_PG_MASK), ("fFlags=%#llx\n", fFlags));
1330 Assert(cb);
1331
1332 LogFlow(("PGMGstModifyPage %RGv %d bytes fFlags=%08llx fMask=%08llx\n", GCPtr, cb, fFlags, fMask));
1333
1334 /*
1335 * Adjust input.
1336 */
1337 cb += GCPtr & PAGE_OFFSET_MASK;
1338 cb = RT_ALIGN_Z(cb, PAGE_SIZE);
1339 GCPtr = (GCPtr & PAGE_BASE_GC_MASK);
1340
1341 /*
1342 * Call worker.
1343 */
1344 int rc = PGM_GST_PFN(ModifyPage, pVM)(pVM, GCPtr, cb, fFlags, fMask);
1345
1346 STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,GstModifyPage), a);
1347 return rc;
1348}
1349
1350
1351/**
1352 * Gets the specified page directory pointer table entry.
1353 *
1354 * @returns PDP entry
1355 * @param pPGM Pointer to the PGM instance data.
1356 * @param iPdpt PDPT index
1357 */
1358VMMDECL(X86PDPE) PGMGstGetPaePDPtr(PVM pVM, unsigned iPdpt)
1359{
1360 Assert(iPdpt <= 3);
1361 return pgmGstGetPaePDPTPtr(&pVM->pgm.s)->a[iPdpt & 3];
1362}
1363
1364
1365/**
1366 * Gets the current CR3 register value for the shadow memory context.
1367 * @returns CR3 value.
1368 * @param pVM The VM handle.
1369 */
1370VMMDECL(RTHCPHYS) PGMGetHyperCR3(PVM pVM)
1371{
1372#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
1373 PGMMODE enmShadowMode = pVM->pgm.s.enmShadowMode;
1374 switch (enmShadowMode)
1375 {
1376 case PGMMODE_EPT:
1377 return pVM->pgm.s.HCPhysShwNestedRoot;
1378
1379 default:
1380 return pVM->pgm.s.HCPhysShwCR3;
1381 }
1382#else
1383 PGMMODE enmShadowMode = pVM->pgm.s.enmShadowMode;
1384 switch (enmShadowMode)
1385 {
1386 case PGMMODE_32_BIT:
1387 return pVM->pgm.s.HCPhysShw32BitPD;
1388
1389 case PGMMODE_PAE:
1390 case PGMMODE_PAE_NX:
1391 return pVM->pgm.s.HCPhysShwPaePdpt;
1392
1393 case PGMMODE_AMD64:
1394 case PGMMODE_AMD64_NX:
1395 return pVM->pgm.s.HCPhysShwCR3;
1396
1397 case PGMMODE_EPT:
1398 return pVM->pgm.s.HCPhysShwNestedRoot;
1399
1400 case PGMMODE_NESTED:
1401 return PGMGetNestedCR3(pVM, PGMGetHostMode(pVM));
1402
1403 default:
1404 AssertMsgFailed(("enmShadowMode=%d\n", enmShadowMode));
1405 return ~0;
1406 }
1407#endif
1408}
1409
1410
1411/**
1412 * Gets the current CR3 register value for the nested memory context.
1413 * @returns CR3 value.
1414 * @param pVM The VM handle.
1415 */
1416VMMDECL(RTHCPHYS) PGMGetNestedCR3(PVM pVM, PGMMODE enmShadowMode)
1417{
1418#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
1419 return pVM->pgm.s.HCPhysShwCR3;
1420#else
1421 switch (enmShadowMode)
1422 {
1423 case PGMMODE_32_BIT:
1424 return pVM->pgm.s.HCPhysShw32BitPD;
1425
1426 case PGMMODE_PAE:
1427 case PGMMODE_PAE_NX:
1428 return pVM->pgm.s.HCPhysShwPaePdpt;
1429
1430 case PGMMODE_AMD64:
1431 case PGMMODE_AMD64_NX:
1432 return pVM->pgm.s.HCPhysShwCR3;
1433
1434 default:
1435 AssertMsgFailed(("enmShadowMode=%d\n", enmShadowMode));
1436 return ~0;
1437 }
1438#endif
1439}
1440
1441
1442/**
1443 * Gets the current CR3 register value for the EPT paging memory context.
1444 * @returns CR3 value.
1445 * @param pVM The VM handle.
1446 */
1447VMMDECL(RTHCPHYS) PGMGetEPTCR3(PVM pVM)
1448{
1449 return pVM->pgm.s.HCPhysShwNestedRoot;
1450}
1451
1452
1453/**
1454 * Gets the CR3 register value for the 32-Bit shadow memory context.
1455 * @returns CR3 value.
1456 * @param pVM The VM handle.
1457 */
1458VMMDECL(RTHCPHYS) PGMGetHyper32BitCR3(PVM pVM)
1459{
1460#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
1461 return pVM->pgm.s.HCPhysShwCR3;
1462#else
1463 return pVM->pgm.s.HCPhysShw32BitPD;
1464#endif
1465}
1466
1467
1468/**
1469 * Gets the CR3 register value for the PAE shadow memory context.
1470 * @returns CR3 value.
1471 * @param pVM The VM handle.
1472 */
1473VMMDECL(RTHCPHYS) PGMGetHyperPaeCR3(PVM pVM)
1474{
1475#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
1476 return pVM->pgm.s.HCPhysShwCR3;
1477#else
1478 return pVM->pgm.s.HCPhysShwPaePdpt;
1479#endif
1480}
1481
1482
1483/**
1484 * Gets the CR3 register value for the AMD64 shadow memory context.
1485 * @returns CR3 value.
1486 * @param pVM The VM handle.
1487 */
1488VMMDECL(RTHCPHYS) PGMGetHyperAmd64CR3(PVM pVM)
1489{
1490 return pVM->pgm.s.HCPhysShwCR3;
1491}
1492
1493/**
1494 * Gets the current CR3 register value for the HC intermediate memory context.
1495 * @returns CR3 value.
1496 * @param pVM The VM handle.
1497 */
1498VMMDECL(RTHCPHYS) PGMGetInterHCCR3(PVM pVM)
1499{
1500 switch (pVM->pgm.s.enmHostMode)
1501 {
1502 case SUPPAGINGMODE_32_BIT:
1503 case SUPPAGINGMODE_32_BIT_GLOBAL:
1504 return pVM->pgm.s.HCPhysInterPD;
1505
1506 case SUPPAGINGMODE_PAE:
1507 case SUPPAGINGMODE_PAE_GLOBAL:
1508 case SUPPAGINGMODE_PAE_NX:
1509 case SUPPAGINGMODE_PAE_GLOBAL_NX:
1510 return pVM->pgm.s.HCPhysInterPaePDPT;
1511
1512 case SUPPAGINGMODE_AMD64:
1513 case SUPPAGINGMODE_AMD64_GLOBAL:
1514 case SUPPAGINGMODE_AMD64_NX:
1515 case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1516 return pVM->pgm.s.HCPhysInterPaePDPT;
1517
1518 default:
1519 AssertMsgFailed(("enmHostMode=%d\n", pVM->pgm.s.enmHostMode));
1520 return ~0;
1521 }
1522}
1523
1524
1525/**
1526 * Gets the current CR3 register value for the RC intermediate memory context.
1527 * @returns CR3 value.
1528 * @param pVM The VM handle.
1529 */
1530VMMDECL(RTHCPHYS) PGMGetInterRCCR3(PVM pVM)
1531{
1532 switch (pVM->pgm.s.enmShadowMode)
1533 {
1534 case PGMMODE_32_BIT:
1535 return pVM->pgm.s.HCPhysInterPD;
1536
1537 case PGMMODE_PAE:
1538 case PGMMODE_PAE_NX:
1539 return pVM->pgm.s.HCPhysInterPaePDPT;
1540
1541 case PGMMODE_AMD64:
1542 case PGMMODE_AMD64_NX:
1543 return pVM->pgm.s.HCPhysInterPaePML4;
1544
1545 case PGMMODE_EPT:
1546 case PGMMODE_NESTED:
1547 return 0; /* not relevant */
1548
1549 default:
1550 AssertMsgFailed(("enmShadowMode=%d\n", pVM->pgm.s.enmShadowMode));
1551 return ~0;
1552 }
1553}
1554
1555
1556/**
1557 * Gets the CR3 register value for the 32-Bit intermediate memory context.
1558 * @returns CR3 value.
1559 * @param pVM The VM handle.
1560 */
1561VMMDECL(RTHCPHYS) PGMGetInter32BitCR3(PVM pVM)
1562{
1563 return pVM->pgm.s.HCPhysInterPD;
1564}
1565
1566
1567/**
1568 * Gets the CR3 register value for the PAE intermediate memory context.
1569 * @returns CR3 value.
1570 * @param pVM The VM handle.
1571 */
1572VMMDECL(RTHCPHYS) PGMGetInterPaeCR3(PVM pVM)
1573{
1574 return pVM->pgm.s.HCPhysInterPaePDPT;
1575}
1576
1577
1578/**
1579 * Gets the CR3 register value for the AMD64 intermediate memory context.
1580 * @returns CR3 value.
1581 * @param pVM The VM handle.
1582 */
1583VMMDECL(RTHCPHYS) PGMGetInterAmd64CR3(PVM pVM)
1584{
1585 return pVM->pgm.s.HCPhysInterPaePML4;
1586}
1587
1588
1589/**
1590 * Performs and schedules necessary updates following a CR3 load or reload.
1591 *
1592 * This will normally involve mapping the guest PD or nPDPT
1593 *
1594 * @returns VBox status code.
1595 * @retval VINF_PGM_SYNC_CR3 if monitoring requires a CR3 sync. This can
1596 * safely be ignored and overridden since the FF will be set too then.
1597 * @param pVM VM handle.
1598 * @param cr3 The new cr3.
1599 * @param fGlobal Indicates whether this is a global flush or not.
1600 */
1601VMMDECL(int) PGMFlushTLB(PVM pVM, uint64_t cr3, bool fGlobal)
1602{
1603 STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,FlushTLB), a);
1604
1605 /*
1606 * Always flag the necessary updates; necessary for hardware acceleration
1607 */
1608 /** @todo optimize this, it shouldn't always be necessary. */
1609 VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
1610 if (fGlobal)
1611 VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
1612 LogFlow(("PGMFlushTLB: cr3=%RX64 OldCr3=%RX64 fGlobal=%d\n", cr3, pVM->pgm.s.GCPhysCR3, fGlobal));
1613
1614 /*
1615 * Remap the CR3 content and adjust the monitoring if CR3 was actually changed.
1616 */
1617 int rc = VINF_SUCCESS;
1618 RTGCPHYS GCPhysCR3;
1619 if ( pVM->pgm.s.enmGuestMode == PGMMODE_PAE
1620 || pVM->pgm.s.enmGuestMode == PGMMODE_PAE_NX
1621 || pVM->pgm.s.enmGuestMode == PGMMODE_AMD64
1622 || pVM->pgm.s.enmGuestMode == PGMMODE_AMD64_NX)
1623 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAE_PAGE_MASK);
1624 else
1625 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAGE_MASK);
1626 if (pVM->pgm.s.GCPhysCR3 != GCPhysCR3)
1627 {
1628#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
1629 /* Unmap the old CR3 value before activating the new one. */
1630 rc = PGM_BTH_PFN(UnmapCR3, pVM)(pVM);
1631 AssertRC(rc);
1632#endif
1633 RTGCPHYS GCPhysOldCR3 = pVM->pgm.s.GCPhysCR3;
1634 pVM->pgm.s.GCPhysCR3 = GCPhysCR3;
1635 rc = PGM_BTH_PFN(MapCR3, pVM)(pVM, GCPhysCR3);
1636 if (RT_LIKELY(rc == VINF_SUCCESS))
1637 {
1638 if (!pVM->pgm.s.fMappingsFixed)
1639 {
1640 pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
1641 rc = PGM_GST_PFN(MonitorCR3, pVM)(pVM, GCPhysCR3);
1642 }
1643 }
1644 else
1645 {
1646 AssertMsg(rc == VINF_PGM_SYNC_CR3, ("%Rrc\n", rc));
1647 Assert(VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL | VM_FF_PGM_SYNC_CR3));
1648 pVM->pgm.s.GCPhysCR3 = GCPhysOldCR3;
1649 pVM->pgm.s.fSyncFlags |= PGM_SYNC_MAP_CR3;
1650 if (!pVM->pgm.s.fMappingsFixed)
1651 pVM->pgm.s.fSyncFlags |= PGM_SYNC_MONITOR_CR3;
1652 }
1653
1654 if (fGlobal)
1655 STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,FlushTLBNewCR3Global));
1656 else
1657 STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,FlushTLBNewCR3));
1658 }
1659 else
1660 {
1661 /*
1662 * Check if we have a pending update of the CR3 monitoring.
1663 */
1664 if (pVM->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
1665 {
1666 pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
1667 Assert(!pVM->pgm.s.fMappingsFixed);
1668 rc = PGM_GST_PFN(MonitorCR3, pVM)(pVM, GCPhysCR3);
1669 }
1670 if (fGlobal)
1671 STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,FlushTLBSameCR3Global));
1672 else
1673 STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,FlushTLBSameCR3));
1674 }
1675
1676 STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,FlushTLB), a);
1677 return rc;
1678}
1679
1680
1681/**
1682 * Performs and schedules necessary updates following a CR3 load or reload when
1683 * using nested or extended paging.
1684 *
1685 * This API is an alterantive to PDMFlushTLB that avoids actually flushing the
1686 * TLB and triggering a SyncCR3.
1687 *
1688 * This will normally involve mapping the guest PD or nPDPT
1689 *
1690 * @returns VBox status code.
1691 * @retval VINF_SUCCESS.
1692 * @retval (If applied when not in nested mode: VINF_PGM_SYNC_CR3 if monitoring
1693 * requires a CR3 sync. This can safely be ignored and overridden since
1694 * the FF will be set too then.)
1695 * @param pVM VM handle.
1696 * @param cr3 The new cr3.
1697 */
1698VMMDECL(int) PGMUpdateCR3(PVM pVM, uint64_t cr3)
1699{
1700 LogFlow(("PGMUpdateCR3: cr3=%RX64 OldCr3=%RX64\n", cr3, pVM->pgm.s.GCPhysCR3));
1701
1702 /* We assume we're only called in nested paging mode. */
1703 Assert(pVM->pgm.s.fMappingsFixed);
1704 Assert(!(pVM->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3));
1705 Assert(pVM->pgm.s.enmShadowMode == PGMMODE_NESTED || pVM->pgm.s.enmShadowMode == PGMMODE_EPT);
1706
1707 /*
1708 * Remap the CR3 content and adjust the monitoring if CR3 was actually changed.
1709 */
1710 int rc = VINF_SUCCESS;
1711 RTGCPHYS GCPhysCR3;
1712 if ( pVM->pgm.s.enmGuestMode == PGMMODE_PAE
1713 || pVM->pgm.s.enmGuestMode == PGMMODE_PAE_NX
1714 || pVM->pgm.s.enmGuestMode == PGMMODE_AMD64
1715 || pVM->pgm.s.enmGuestMode == PGMMODE_AMD64_NX)
1716 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAE_PAGE_MASK);
1717 else
1718 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAGE_MASK);
1719 if (pVM->pgm.s.GCPhysCR3 != GCPhysCR3)
1720 {
1721 pVM->pgm.s.GCPhysCR3 = GCPhysCR3;
1722 rc = PGM_BTH_PFN(MapCR3, pVM)(pVM, GCPhysCR3);
1723 AssertRCSuccess(rc); /* Assumes VINF_PGM_SYNC_CR3 doesn't apply to nested paging. */
1724 }
1725 return rc;
1726}
1727
1728
1729/**
1730 * Synchronize the paging structures.
1731 *
1732 * This function is called in response to the VM_FF_PGM_SYNC_CR3 and
1733 * VM_FF_PGM_SYNC_CR3_NONGLOBAL. Those two force action flags are set
1734 * in several places, most importantly whenever the CR3 is loaded.
1735 *
1736 * @returns VBox status code.
1737 * @param pVM The virtual machine.
1738 * @param cr0 Guest context CR0 register
1739 * @param cr3 Guest context CR3 register
1740 * @param cr4 Guest context CR4 register
1741 * @param fGlobal Including global page directories or not
1742 */
1743VMMDECL(int) PGMSyncCR3(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
1744{
1745 int rc;
1746
1747 /*
1748 * We might be called when we shouldn't.
1749 *
1750 * The mode switching will ensure that the PD is resynced
1751 * after every mode switch. So, if we find ourselves here
1752 * when in protected or real mode we can safely disable the
1753 * FF and return immediately.
1754 */
1755 if (pVM->pgm.s.enmGuestMode <= PGMMODE_PROTECTED)
1756 {
1757 Assert((cr0 & (X86_CR0_PG | X86_CR0_PE)) != (X86_CR0_PG | X86_CR0_PE));
1758 VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3);
1759 VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
1760 return VINF_SUCCESS;
1761 }
1762
1763 /* If global pages are not supported, then all flushes are global. */
1764 if (!(cr4 & X86_CR4_PGE))
1765 fGlobal = true;
1766 LogFlow(("PGMSyncCR3: cr0=%RX64 cr3=%RX64 cr4=%RX64 fGlobal=%d[%d,%d]\n", cr0, cr3, cr4, fGlobal,
1767 VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3), VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL)));
1768
1769#ifdef PGMPOOL_WITH_MONITORING
1770 /*
1771 * The pool may have pending stuff and even require a return to ring-3 to
1772 * clear the whole thing.
1773 */
1774 rc = pgmPoolSyncCR3(pVM);
1775 if (rc != VINF_SUCCESS)
1776 return rc;
1777#endif
1778
1779 /*
1780 * Check if we need to finish an aborted MapCR3 call (see PGMFlushTLB).
1781 * This should be done before SyncCR3.
1782 */
1783 if (pVM->pgm.s.fSyncFlags & PGM_SYNC_MAP_CR3)
1784 {
1785 pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_MAP_CR3;
1786
1787 RTGCPHYS GCPhysCR3Old = pVM->pgm.s.GCPhysCR3;
1788 RTGCPHYS GCPhysCR3;
1789 if ( pVM->pgm.s.enmGuestMode == PGMMODE_PAE
1790 || pVM->pgm.s.enmGuestMode == PGMMODE_PAE_NX
1791 || pVM->pgm.s.enmGuestMode == PGMMODE_AMD64
1792 || pVM->pgm.s.enmGuestMode == PGMMODE_AMD64_NX)
1793 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAE_PAGE_MASK);
1794 else
1795 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAGE_MASK);
1796
1797#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
1798 if (pVM->pgm.s.GCPhysCR3 != GCPhysCR3)
1799 {
1800 /* Unmap the old CR3 value before activating the new one. */
1801 rc = PGM_BTH_PFN(UnmapCR3, pVM)(pVM);
1802 AssertRC(rc);
1803 }
1804#endif
1805
1806 pVM->pgm.s.GCPhysCR3 = GCPhysCR3;
1807 rc = PGM_BTH_PFN(MapCR3, pVM)(pVM, GCPhysCR3);
1808#ifdef IN_RING3
1809 if (rc == VINF_PGM_SYNC_CR3)
1810 rc = pgmPoolSyncCR3(pVM);
1811#else
1812 if (rc == VINF_PGM_SYNC_CR3)
1813 {
1814 pVM->pgm.s.GCPhysCR3 = GCPhysCR3Old;
1815 return rc;
1816 }
1817#endif
1818 AssertRCReturn(rc, rc);
1819 AssertRCSuccessReturn(rc, VERR_INTERNAL_ERROR);
1820 }
1821
1822 /*
1823 * Let the 'Bth' function do the work and we'll just keep track of the flags.
1824 */
1825 STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3), a);
1826 rc = PGM_BTH_PFN(SyncCR3, pVM)(pVM, cr0, cr3, cr4, fGlobal);
1827 STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3), a);
1828 AssertMsg(rc == VINF_SUCCESS || rc == VINF_PGM_SYNC_CR3 || RT_FAILURE(rc), ("rc=%Rrc\n", rc));
1829 if (rc == VINF_SUCCESS)
1830 {
1831 if (!(pVM->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS))
1832 {
1833 VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3);
1834 VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
1835 }
1836
1837 /*
1838 * Check if we have a pending update of the CR3 monitoring.
1839 */
1840 if (pVM->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
1841 {
1842 pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
1843 Assert(!pVM->pgm.s.fMappingsFixed);
1844 Assert(pVM->pgm.s.GCPhysCR3 == pVM->pgm.s.GCPhysGstCR3Monitored);
1845 rc = PGM_GST_PFN(MonitorCR3, pVM)(pVM, pVM->pgm.s.GCPhysCR3);
1846 }
1847 }
1848
1849 /*
1850 * Now flush the CR3 (guest context).
1851 */
1852 if (rc == VINF_SUCCESS)
1853 PGM_INVL_GUEST_TLBS();
1854 return rc;
1855}
1856
1857
1858/**
1859 * Called whenever CR0 or CR4 in a way which may change
1860 * the paging mode.
1861 *
1862 * @returns VBox status code fit for scheduling in GC and R0.
1863 * @retval VINF_SUCCESS if the was no change, or it was successfully dealt with.
1864 * @retval VINF_PGM_CHANGE_MODE if we're in GC or R0 and the mode changes.
1865 * @param pVM VM handle.
1866 * @param cr0 The new cr0.
1867 * @param cr4 The new cr4.
1868 * @param efer The new extended feature enable register.
1869 */
1870VMMDECL(int) PGMChangeMode(PVM pVM, uint64_t cr0, uint64_t cr4, uint64_t efer)
1871{
1872 PGMMODE enmGuestMode;
1873
1874 /*
1875 * Calc the new guest mode.
1876 */
1877 if (!(cr0 & X86_CR0_PE))
1878 enmGuestMode = PGMMODE_REAL;
1879 else if (!(cr0 & X86_CR0_PG))
1880 enmGuestMode = PGMMODE_PROTECTED;
1881 else if (!(cr4 & X86_CR4_PAE))
1882 enmGuestMode = PGMMODE_32_BIT;
1883 else if (!(efer & MSR_K6_EFER_LME))
1884 {
1885 if (!(efer & MSR_K6_EFER_NXE))
1886 enmGuestMode = PGMMODE_PAE;
1887 else
1888 enmGuestMode = PGMMODE_PAE_NX;
1889 }
1890 else
1891 {
1892 if (!(efer & MSR_K6_EFER_NXE))
1893 enmGuestMode = PGMMODE_AMD64;
1894 else
1895 enmGuestMode = PGMMODE_AMD64_NX;
1896 }
1897
1898 /*
1899 * Did it change?
1900 */
1901 if (pVM->pgm.s.enmGuestMode == enmGuestMode)
1902 return VINF_SUCCESS;
1903
1904 /* Flush the TLB */
1905 PGM_INVL_GUEST_TLBS();
1906
1907#ifdef IN_RING3
1908 return PGMR3ChangeMode(pVM, enmGuestMode);
1909#else
1910 LogFlow(("PGMChangeMode: returns VINF_PGM_CHANGE_MODE.\n"));
1911 return VINF_PGM_CHANGE_MODE;
1912#endif
1913}
1914
1915
1916/**
1917 * Gets the current guest paging mode.
1918 *
1919 * If you just need the CPU mode (real/protected/long), use CPUMGetGuestMode().
1920 *
1921 * @returns The current paging mode.
1922 * @param pVM The VM handle.
1923 */
1924VMMDECL(PGMMODE) PGMGetGuestMode(PVM pVM)
1925{
1926 return pVM->pgm.s.enmGuestMode;
1927}
1928
1929
1930/**
1931 * Gets the current shadow paging mode.
1932 *
1933 * @returns The current paging mode.
1934 * @param pVM The VM handle.
1935 */
1936VMMDECL(PGMMODE) PGMGetShadowMode(PVM pVM)
1937{
1938 return pVM->pgm.s.enmShadowMode;
1939}
1940
1941/**
1942 * Gets the current host paging mode.
1943 *
1944 * @returns The current paging mode.
1945 * @param pVM The VM handle.
1946 */
1947VMMDECL(PGMMODE) PGMGetHostMode(PVM pVM)
1948{
1949 switch (pVM->pgm.s.enmHostMode)
1950 {
1951 case SUPPAGINGMODE_32_BIT:
1952 case SUPPAGINGMODE_32_BIT_GLOBAL:
1953 return PGMMODE_32_BIT;
1954
1955 case SUPPAGINGMODE_PAE:
1956 case SUPPAGINGMODE_PAE_GLOBAL:
1957 return PGMMODE_PAE;
1958
1959 case SUPPAGINGMODE_PAE_NX:
1960 case SUPPAGINGMODE_PAE_GLOBAL_NX:
1961 return PGMMODE_PAE_NX;
1962
1963 case SUPPAGINGMODE_AMD64:
1964 case SUPPAGINGMODE_AMD64_GLOBAL:
1965 return PGMMODE_AMD64;
1966
1967 case SUPPAGINGMODE_AMD64_NX:
1968 case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1969 return PGMMODE_AMD64_NX;
1970
1971 default: AssertMsgFailed(("enmHostMode=%d\n", pVM->pgm.s.enmHostMode)); break;
1972 }
1973
1974 return PGMMODE_INVALID;
1975}
1976
1977
1978/**
1979 * Get mode name.
1980 *
1981 * @returns read-only name string.
1982 * @param enmMode The mode which name is desired.
1983 */
1984VMMDECL(const char *) PGMGetModeName(PGMMODE enmMode)
1985{
1986 switch (enmMode)
1987 {
1988 case PGMMODE_REAL: return "Real";
1989 case PGMMODE_PROTECTED: return "Protected";
1990 case PGMMODE_32_BIT: return "32-bit";
1991 case PGMMODE_PAE: return "PAE";
1992 case PGMMODE_PAE_NX: return "PAE+NX";
1993 case PGMMODE_AMD64: return "AMD64";
1994 case PGMMODE_AMD64_NX: return "AMD64+NX";
1995 case PGMMODE_NESTED: return "Nested";
1996 case PGMMODE_EPT: return "EPT";
1997 default: return "unknown mode value";
1998 }
1999}
2000
2001
2002/**
2003 * Acquire the PGM lock.
2004 *
2005 * @returns VBox status code
2006 * @param pVM The VM to operate on.
2007 */
2008int pgmLock(PVM pVM)
2009{
2010 int rc = PDMCritSectEnter(&pVM->pgm.s.CritSect, VERR_SEM_BUSY);
2011#ifdef IN_RC
2012 if (rc == VERR_SEM_BUSY)
2013 rc = VMMGCCallHost(pVM, VMMCALLHOST_PGM_LOCK, 0);
2014#elif defined(IN_RING0)
2015 if (rc == VERR_SEM_BUSY)
2016 rc = VMMR0CallHost(pVM, VMMCALLHOST_PGM_LOCK, 0);
2017#endif
2018 AssertRC(rc);
2019 return rc;
2020}
2021
2022
2023/**
2024 * Release the PGM lock.
2025 *
2026 * @returns VBox status code
2027 * @param pVM The VM to operate on.
2028 */
2029void pgmUnlock(PVM pVM)
2030{
2031 PDMCritSectLeave(&pVM->pgm.s.CritSect);
2032}
2033
2034#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2035
2036/**
2037 * Temporarily maps one guest page specified by GC physical address.
2038 * These pages must have a physical mapping in HC, i.e. they cannot be MMIO pages.
2039 *
2040 * Be WARNED that the dynamic page mapping area is small, 8 pages, thus the space is
2041 * reused after 8 mappings (or perhaps a few more if you score with the cache).
2042 *
2043 * @returns VBox status.
2044 * @param pVM VM handle.
2045 * @param GCPhys GC Physical address of the page.
2046 * @param ppv Where to store the address of the mapping.
2047 */
2048VMMDECL(int) PGMDynMapGCPage(PVM pVM, RTGCPHYS GCPhys, void **ppv)
2049{
2050 AssertMsg(!(GCPhys & PAGE_OFFSET_MASK), ("GCPhys=%RGp\n", GCPhys));
2051
2052 /*
2053 * Get the ram range.
2054 */
2055 PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
2056 while (pRam && GCPhys - pRam->GCPhys >= pRam->cb)
2057 pRam = pRam->CTX_SUFF(pNext);
2058 if (!pRam)
2059 {
2060 AssertMsgFailed(("Invalid physical address %RGp!\n", GCPhys));
2061 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2062 }
2063
2064 /*
2065 * Pass it on to PGMDynMapHCPage.
2066 */
2067 RTHCPHYS HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT]);
2068 //Log(("PGMDynMapGCPage: GCPhys=%RGp HCPhys=%RHp\n", GCPhys, HCPhys));
2069#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2070 pgmR0DynMapHCPageInlined(&pVM->pgm.s, HCPhys, ppv);
2071#else
2072 PGMDynMapHCPage(pVM, HCPhys, ppv);
2073#endif
2074 return VINF_SUCCESS;
2075}
2076
2077
2078/**
2079 * Temporarily maps one guest page specified by unaligned GC physical address.
2080 * These pages must have a physical mapping in HC, i.e. they cannot be MMIO pages.
2081 *
2082 * Be WARNED that the dynamic page mapping area is small, 8 pages, thus the space is
2083 * reused after 8 mappings (or perhaps a few more if you score with the cache).
2084 *
2085 * The caller is aware that only the speicifed page is mapped and that really bad things
2086 * will happen if writing beyond the page!
2087 *
2088 * @returns VBox status.
2089 * @param pVM VM handle.
2090 * @param GCPhys GC Physical address within the page to be mapped.
2091 * @param ppv Where to store the address of the mapping address corresponding to GCPhys.
2092 */
2093VMMDECL(int) PGMDynMapGCPageOff(PVM pVM, RTGCPHYS GCPhys, void **ppv)
2094{
2095 /*
2096 * Get the ram range.
2097 */
2098 PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
2099 while (pRam && GCPhys - pRam->GCPhys >= pRam->cb)
2100 pRam = pRam->CTX_SUFF(pNext);
2101 if (!pRam)
2102 {
2103 AssertMsgFailed(("Invalid physical address %RGp!\n", GCPhys));
2104 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2105 }
2106
2107 /*
2108 * Pass it on to PGMDynMapHCPage.
2109 */
2110 RTHCPHYS HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT]);
2111#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2112 pgmR0DynMapHCPageInlined(&pVM->pgm.s, HCPhys, ppv);
2113#else
2114 PGMDynMapHCPage(pVM, HCPhys, ppv);
2115#endif
2116 *ppv = (void *)((uintptr_t)*ppv | (GCPhys & PAGE_OFFSET_MASK));
2117 return VINF_SUCCESS;
2118}
2119
2120
2121# ifdef IN_RC
2122/**
2123 * Temporarily maps one host page specified by HC physical address.
2124 *
2125 * Be WARNED that the dynamic page mapping area is small, 8 pages, thus the space is
2126 * reused after 8 mappings (or perhaps a few more if you score with the cache).
2127 *
2128 * @returns VINF_SUCCESS, will bail out to ring-3 on failure.
2129 * @param pVM VM handle.
2130 * @param HCPhys HC Physical address of the page.
2131 * @param ppv Where to store the address of the mapping. This is the
2132 * address of the PAGE not the exact address corresponding
2133 * to HCPhys. Use PGMDynMapHCPageOff if you care for the
2134 * page offset.
2135 */
2136VMMDECL(int) PGMDynMapHCPage(PVM pVM, RTHCPHYS HCPhys, void **ppv)
2137{
2138 AssertMsg(!(HCPhys & PAGE_OFFSET_MASK), ("HCPhys=%RHp\n", HCPhys));
2139
2140 /*
2141 * Check the cache.
2142 */
2143 register unsigned iCache;
2144 if ( pVM->pgm.s.aHCPhysDynPageMapCache[iCache = 0] == HCPhys
2145 || pVM->pgm.s.aHCPhysDynPageMapCache[iCache = 1] == HCPhys
2146 || pVM->pgm.s.aHCPhysDynPageMapCache[iCache = 2] == HCPhys
2147 || pVM->pgm.s.aHCPhysDynPageMapCache[iCache = 3] == HCPhys)
2148 {
2149 static const uint8_t au8Trans[MM_HYPER_DYNAMIC_SIZE >> PAGE_SHIFT][RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache)] =
2150 {
2151 { 0, 5, 6, 7 },
2152 { 0, 1, 6, 7 },
2153 { 0, 1, 2, 7 },
2154 { 0, 1, 2, 3 },
2155 { 4, 1, 2, 3 },
2156 { 4, 5, 2, 3 },
2157 { 4, 5, 6, 3 },
2158 { 4, 5, 6, 7 },
2159 };
2160 Assert(RT_ELEMENTS(au8Trans) == 8);
2161 Assert(RT_ELEMENTS(au8Trans[0]) == 4);
2162 int iPage = au8Trans[pVM->pgm.s.iDynPageMapLast][iCache];
2163 void *pv = pVM->pgm.s.pbDynPageMapBaseGC + (iPage << PAGE_SHIFT);
2164 *ppv = pv;
2165 STAM_COUNTER_INC(&pVM->pgm.s.StatRCDynMapCacheHits);
2166 //Log(("PGMGCDynMapHCPage: HCPhys=%RHp pv=%p iPage=%d iCache=%d\n", HCPhys, pv, iPage, iCache));
2167 return VINF_SUCCESS;
2168 }
2169 Assert(RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache) == 4);
2170 STAM_COUNTER_INC(&pVM->pgm.s.StatRCDynMapCacheMisses);
2171
2172 /*
2173 * Update the page tables.
2174 */
2175 register unsigned iPage = pVM->pgm.s.iDynPageMapLast;
2176 pVM->pgm.s.iDynPageMapLast = iPage = (iPage + 1) & ((MM_HYPER_DYNAMIC_SIZE >> PAGE_SHIFT) - 1);
2177 Assert((MM_HYPER_DYNAMIC_SIZE >> PAGE_SHIFT) == 8);
2178
2179 pVM->pgm.s.aHCPhysDynPageMapCache[iPage & (RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache) - 1)] = HCPhys;
2180 pVM->pgm.s.paDynPageMap32BitPTEsGC[iPage].u = (uint32_t)HCPhys | X86_PTE_P | X86_PTE_A | X86_PTE_D;
2181 pVM->pgm.s.paDynPageMapPaePTEsGC[iPage].u = HCPhys | X86_PTE_P | X86_PTE_A | X86_PTE_D;
2182
2183 void *pv = pVM->pgm.s.pbDynPageMapBaseGC + (iPage << PAGE_SHIFT);
2184 *ppv = pv;
2185 ASMInvalidatePage(pv);
2186 Log4(("PGMGCDynMapHCPage: HCPhys=%RHp pv=%p iPage=%d\n", HCPhys, pv, iPage));
2187 return VINF_SUCCESS;
2188}
2189# endif /* IN_RC */
2190
2191#endif /* IN_RC || VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
2192#ifdef VBOX_STRICT
2193
2194/**
2195 * Asserts that there are no mapping conflicts.
2196 *
2197 * @returns Number of conflicts.
2198 * @param pVM The VM Handle.
2199 */
2200VMMDECL(unsigned) PGMAssertNoMappingConflicts(PVM pVM)
2201{
2202 unsigned cErrors = 0;
2203
2204 /*
2205 * Check for mapping conflicts.
2206 */
2207 for (PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
2208 pMapping;
2209 pMapping = pMapping->CTX_SUFF(pNext))
2210 {
2211 /** @todo This is slow and should be optimized, but since it's just assertions I don't care now. */
2212 for (RTGCPTR GCPtr = pMapping->GCPtr;
2213 GCPtr <= pMapping->GCPtrLast;
2214 GCPtr += PAGE_SIZE)
2215 {
2216 int rc = PGMGstGetPage(pVM, (RTGCPTR)GCPtr, NULL, NULL);
2217 if (rc != VERR_PAGE_TABLE_NOT_PRESENT)
2218 {
2219 AssertMsgFailed(("Conflict at %RGv with %s\n", GCPtr, R3STRING(pMapping->pszDesc)));
2220 cErrors++;
2221 break;
2222 }
2223 }
2224 }
2225
2226 return cErrors;
2227}
2228
2229
2230/**
2231 * Asserts that everything related to the guest CR3 is correctly shadowed.
2232 *
2233 * This will call PGMAssertNoMappingConflicts() and PGMAssertHandlerAndFlagsInSync(),
2234 * and assert the correctness of the guest CR3 mapping before asserting that the
2235 * shadow page tables is in sync with the guest page tables.
2236 *
2237 * @returns Number of conflicts.
2238 * @param pVM The VM Handle.
2239 * @param cr3 The current guest CR3 register value.
2240 * @param cr4 The current guest CR4 register value.
2241 */
2242VMMDECL(unsigned) PGMAssertCR3(PVM pVM, uint64_t cr3, uint64_t cr4)
2243{
2244 STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3), a);
2245 unsigned cErrors = PGM_BTH_PFN(AssertCR3, pVM)(pVM, cr3, cr4, 0, ~(RTGCPTR)0);
2246 STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3), a);
2247 return cErrors;
2248 return 0;
2249}
2250
2251#endif /* VBOX_STRICT */
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