VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAll.cpp@ 17158

Last change on this file since 17158 was 17158, checked in by vboxsync, 16 years ago

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1/* $Id: PGMAll.cpp 17158 2009-02-26 12:19:48Z vboxsync $ */
2/** @file
3 * PGM - Page Manager and Monitor - All context code.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22/*******************************************************************************
23* Header Files *
24*******************************************************************************/
25#define LOG_GROUP LOG_GROUP_PGM
26#include <VBox/pgm.h>
27#include <VBox/cpum.h>
28#include <VBox/selm.h>
29#include <VBox/iom.h>
30#include <VBox/sup.h>
31#include <VBox/mm.h>
32#include <VBox/stam.h>
33#include <VBox/csam.h>
34#include <VBox/patm.h>
35#include <VBox/trpm.h>
36#include <VBox/rem.h>
37#include <VBox/em.h>
38#include <VBox/hwaccm.h>
39#include <VBox/hwacc_vmx.h>
40#include "PGMInternal.h"
41#include <VBox/vm.h>
42#include <iprt/assert.h>
43#include <iprt/asm.h>
44#include <iprt/string.h>
45#include <VBox/log.h>
46#include <VBox/param.h>
47#include <VBox/err.h>
48
49
50/*******************************************************************************
51* Structures and Typedefs *
52*******************************************************************************/
53/**
54 * Stated structure for PGM_GST_NAME(HandlerVirtualUpdate) that's
55 * passed to PGM_GST_NAME(VirtHandlerUpdateOne) during enumeration.
56 */
57typedef struct PGMHVUSTATE
58{
59 /** The VM handle. */
60 PVM pVM;
61 /** The todo flags. */
62 RTUINT fTodo;
63 /** The CR4 register value. */
64 uint32_t cr4;
65} PGMHVUSTATE, *PPGMHVUSTATE;
66
67
68/*******************************************************************************
69* Internal Functions *
70*******************************************************************************/
71DECLINLINE(int) pgmShwGetLongModePDPtr(PVM pVM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPT *ppPdpt, PX86PDPAE *ppPD);
72DECLINLINE(int) pgmShwGetPAEPDPtr(PVM pVM, RTGCPTR GCPtr, PX86PDPT *ppPdpt, PX86PDPAE *ppPD);
73#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
74DECLINLINE(int) pgmShwGetPaePoolPagePD(PPGM pPGM, RTGCPTR GCPtr, PPGMPOOLPAGE *ppShwPde);
75#endif
76
77/*
78 * Shadow - 32-bit mode
79 */
80#define PGM_SHW_TYPE PGM_TYPE_32BIT
81#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
82#include "PGMAllShw.h"
83
84/* Guest - real mode */
85#define PGM_GST_TYPE PGM_TYPE_REAL
86#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
87#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
88#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
89#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
90#include "PGMAllGst.h"
91#include "PGMAllBth.h"
92#undef BTH_PGMPOOLKIND_PT_FOR_PT
93#undef BTH_PGMPOOLKIND_ROOT
94#undef PGM_BTH_NAME
95#undef PGM_GST_TYPE
96#undef PGM_GST_NAME
97
98/* Guest - protected mode */
99#define PGM_GST_TYPE PGM_TYPE_PROT
100#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
101#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
102#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
103#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
104#include "PGMAllGst.h"
105#include "PGMAllBth.h"
106#undef BTH_PGMPOOLKIND_PT_FOR_PT
107#undef BTH_PGMPOOLKIND_ROOT
108#undef PGM_BTH_NAME
109#undef PGM_GST_TYPE
110#undef PGM_GST_NAME
111
112/* Guest - 32-bit mode */
113#define PGM_GST_TYPE PGM_TYPE_32BIT
114#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
115#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
116#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
117#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
118#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD
119#include "PGMAllGst.h"
120#include "PGMAllBth.h"
121#undef BTH_PGMPOOLKIND_PT_FOR_BIG
122#undef BTH_PGMPOOLKIND_PT_FOR_PT
123#undef BTH_PGMPOOLKIND_ROOT
124#undef PGM_BTH_NAME
125#undef PGM_GST_TYPE
126#undef PGM_GST_NAME
127
128#undef PGM_SHW_TYPE
129#undef PGM_SHW_NAME
130
131
132/*
133 * Shadow - PAE mode
134 */
135#define PGM_SHW_TYPE PGM_TYPE_PAE
136#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
137#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
138#include "PGMAllShw.h"
139
140/* Guest - real mode */
141#define PGM_GST_TYPE PGM_TYPE_REAL
142#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
143#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
144#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
145#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
146#include "PGMAllBth.h"
147#undef BTH_PGMPOOLKIND_PT_FOR_PT
148#undef BTH_PGMPOOLKIND_ROOT
149#undef PGM_BTH_NAME
150#undef PGM_GST_TYPE
151#undef PGM_GST_NAME
152
153/* Guest - protected mode */
154#define PGM_GST_TYPE PGM_TYPE_PROT
155#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
156#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
157#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
158#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
159#include "PGMAllBth.h"
160#undef BTH_PGMPOOLKIND_PT_FOR_PT
161#undef BTH_PGMPOOLKIND_ROOT
162#undef PGM_BTH_NAME
163#undef PGM_GST_TYPE
164#undef PGM_GST_NAME
165
166/* Guest - 32-bit mode */
167#define PGM_GST_TYPE PGM_TYPE_32BIT
168#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
169#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
170#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
171#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
172#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_FOR_32BIT
173#include "PGMAllBth.h"
174#undef BTH_PGMPOOLKIND_PT_FOR_BIG
175#undef BTH_PGMPOOLKIND_PT_FOR_PT
176#undef BTH_PGMPOOLKIND_ROOT
177#undef PGM_BTH_NAME
178#undef PGM_GST_TYPE
179#undef PGM_GST_NAME
180
181
182/* Guest - PAE mode */
183#define PGM_GST_TYPE PGM_TYPE_PAE
184#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
185#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
186#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
187#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
188#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT
189#include "PGMAllGst.h"
190#include "PGMAllBth.h"
191#undef BTH_PGMPOOLKIND_PT_FOR_BIG
192#undef BTH_PGMPOOLKIND_PT_FOR_PT
193#undef BTH_PGMPOOLKIND_ROOT
194#undef PGM_BTH_NAME
195#undef PGM_GST_TYPE
196#undef PGM_GST_NAME
197
198#undef PGM_SHW_TYPE
199#undef PGM_SHW_NAME
200
201
202#ifndef IN_RC /* AMD64 implies VT-x/AMD-V */
203/*
204 * Shadow - AMD64 mode
205 */
206# define PGM_SHW_TYPE PGM_TYPE_AMD64
207# define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
208# include "PGMAllShw.h"
209
210/* Guest - protected mode (only used for AMD-V nested paging in 64 bits mode) */
211# define PGM_GST_TYPE PGM_TYPE_PROT
212# define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
213# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_PROT(name)
214# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
215# define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PD_PHYS
216# include "PGMAllBth.h"
217# undef BTH_PGMPOOLKIND_PT_FOR_PT
218# undef BTH_PGMPOOLKIND_ROOT
219# undef PGM_BTH_NAME
220# undef PGM_GST_TYPE
221# undef PGM_GST_NAME
222
223# ifdef VBOX_WITH_64_BITS_GUESTS
224/* Guest - AMD64 mode */
225# define PGM_GST_TYPE PGM_TYPE_AMD64
226# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
227# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
228# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
229# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
230# define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_64BIT_PML4
231# include "PGMAllGst.h"
232# include "PGMAllBth.h"
233# undef BTH_PGMPOOLKIND_PT_FOR_BIG
234# undef BTH_PGMPOOLKIND_PT_FOR_PT
235# undef BTH_PGMPOOLKIND_ROOT
236# undef PGM_BTH_NAME
237# undef PGM_GST_TYPE
238# undef PGM_GST_NAME
239# endif /* VBOX_WITH_64_BITS_GUESTS */
240
241# undef PGM_SHW_TYPE
242# undef PGM_SHW_NAME
243
244
245/*
246 * Shadow - Nested paging mode
247 */
248# define PGM_SHW_TYPE PGM_TYPE_NESTED
249# define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED(name)
250# include "PGMAllShw.h"
251
252/* Guest - real mode */
253# define PGM_GST_TYPE PGM_TYPE_REAL
254# define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
255# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_REAL(name)
256# include "PGMAllBth.h"
257# undef PGM_BTH_NAME
258# undef PGM_GST_TYPE
259# undef PGM_GST_NAME
260
261/* Guest - protected mode */
262# define PGM_GST_TYPE PGM_TYPE_PROT
263# define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
264# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PROT(name)
265# include "PGMAllBth.h"
266# undef PGM_BTH_NAME
267# undef PGM_GST_TYPE
268# undef PGM_GST_NAME
269
270/* Guest - 32-bit mode */
271# define PGM_GST_TYPE PGM_TYPE_32BIT
272# define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
273# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT(name)
274# include "PGMAllBth.h"
275# undef PGM_BTH_NAME
276# undef PGM_GST_TYPE
277# undef PGM_GST_NAME
278
279/* Guest - PAE mode */
280# define PGM_GST_TYPE PGM_TYPE_PAE
281# define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
282# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE(name)
283# include "PGMAllBth.h"
284# undef PGM_BTH_NAME
285# undef PGM_GST_TYPE
286# undef PGM_GST_NAME
287
288# ifdef VBOX_WITH_64_BITS_GUESTS
289/* Guest - AMD64 mode */
290# define PGM_GST_TYPE PGM_TYPE_AMD64
291# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
292# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64(name)
293# include "PGMAllBth.h"
294# undef PGM_BTH_NAME
295# undef PGM_GST_TYPE
296# undef PGM_GST_NAME
297# endif /* VBOX_WITH_64_BITS_GUESTS */
298
299# undef PGM_SHW_TYPE
300# undef PGM_SHW_NAME
301
302
303/*
304 * Shadow - EPT
305 */
306# define PGM_SHW_TYPE PGM_TYPE_EPT
307# define PGM_SHW_NAME(name) PGM_SHW_NAME_EPT(name)
308# include "PGMAllShw.h"
309
310/* Guest - real mode */
311# define PGM_GST_TYPE PGM_TYPE_REAL
312# define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
313# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_REAL(name)
314# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
315# include "PGMAllBth.h"
316# undef BTH_PGMPOOLKIND_PT_FOR_PT
317# undef PGM_BTH_NAME
318# undef PGM_GST_TYPE
319# undef PGM_GST_NAME
320
321/* Guest - protected mode */
322# define PGM_GST_TYPE PGM_TYPE_PROT
323# define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
324# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PROT(name)
325# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
326# include "PGMAllBth.h"
327# undef BTH_PGMPOOLKIND_PT_FOR_PT
328# undef PGM_BTH_NAME
329# undef PGM_GST_TYPE
330# undef PGM_GST_NAME
331
332/* Guest - 32-bit mode */
333# define PGM_GST_TYPE PGM_TYPE_32BIT
334# define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
335# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_32BIT(name)
336# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
337# include "PGMAllBth.h"
338# undef BTH_PGMPOOLKIND_PT_FOR_PT
339# undef PGM_BTH_NAME
340# undef PGM_GST_TYPE
341# undef PGM_GST_NAME
342
343/* Guest - PAE mode */
344# define PGM_GST_TYPE PGM_TYPE_PAE
345# define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
346# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PAE(name)
347# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
348# include "PGMAllBth.h"
349# undef BTH_PGMPOOLKIND_PT_FOR_PT
350# undef PGM_BTH_NAME
351# undef PGM_GST_TYPE
352# undef PGM_GST_NAME
353
354# ifdef VBOX_WITH_64_BITS_GUESTS
355/* Guest - AMD64 mode */
356# define PGM_GST_TYPE PGM_TYPE_AMD64
357# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
358# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_AMD64(name)
359# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
360# include "PGMAllBth.h"
361# undef BTH_PGMPOOLKIND_PT_FOR_PT
362# undef PGM_BTH_NAME
363# undef PGM_GST_TYPE
364# undef PGM_GST_NAME
365# endif /* VBOX_WITH_64_BITS_GUESTS */
366
367# undef PGM_SHW_TYPE
368# undef PGM_SHW_NAME
369
370#endif /* !IN_RC */
371
372
373#ifndef IN_RING3
374/**
375 * #PF Handler.
376 *
377 * @returns VBox status code (appropriate for trap handling and GC return).
378 * @param pVM VM Handle.
379 * @param uErr The trap error code.
380 * @param pRegFrame Trap register frame.
381 * @param pvFault The fault address.
382 */
383VMMDECL(int) PGMTrap0eHandler(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
384{
385 LogFlow(("PGMTrap0eHandler: uErr=%RGu pvFault=%RGv eip=%RGv\n", uErr, pvFault, (RTGCPTR)pRegFrame->rip));
386 STAM_PROFILE_START(&pVM->pgm.s.StatRZTrap0e, a);
387 STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = NULL; } );
388
389
390#ifdef VBOX_WITH_STATISTICS
391 /*
392 * Error code stats.
393 */
394 if (uErr & X86_TRAP_PF_US)
395 {
396 if (!(uErr & X86_TRAP_PF_P))
397 {
398 if (uErr & X86_TRAP_PF_RW)
399 STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eUSNotPresentWrite);
400 else
401 STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eUSNotPresentRead);
402 }
403 else if (uErr & X86_TRAP_PF_RW)
404 STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eUSWrite);
405 else if (uErr & X86_TRAP_PF_RSVD)
406 STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eUSReserved);
407 else if (uErr & X86_TRAP_PF_ID)
408 STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eUSNXE);
409 else
410 STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eUSRead);
411 }
412 else
413 { /* Supervisor */
414 if (!(uErr & X86_TRAP_PF_P))
415 {
416 if (uErr & X86_TRAP_PF_RW)
417 STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eSVNotPresentWrite);
418 else
419 STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eSVNotPresentRead);
420 }
421 else if (uErr & X86_TRAP_PF_RW)
422 STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eSVWrite);
423 else if (uErr & X86_TRAP_PF_ID)
424 STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eSNXE);
425 else if (uErr & X86_TRAP_PF_RSVD)
426 STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eSVReserved);
427 }
428#endif /* VBOX_WITH_STATISTICS */
429
430 /*
431 * Call the worker.
432 */
433 int rc = PGM_BTH_PFN(Trap0eHandler, pVM)(pVM, uErr, pRegFrame, pvFault);
434 if (rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
435 rc = VINF_SUCCESS;
436 STAM_STATS({ if (rc == VINF_EM_RAW_GUEST_TRAP) STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eGuestPF); });
437 STAM_STATS({ if (!pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution))
438 pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2Misc; });
439 STAM_PROFILE_STOP_EX(&pVM->pgm.s.StatRZTrap0e, pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution), a);
440 return rc;
441}
442#endif /* !IN_RING3 */
443
444
445/**
446 * Prefetch a page
447 *
448 * Typically used to sync commonly used pages before entering raw mode
449 * after a CR3 reload.
450 *
451 * @returns VBox status code suitable for scheduling.
452 * @retval VINF_SUCCESS on success.
453 * @retval VINF_PGM_SYNC_CR3 if we're out of shadow pages or something like that.
454 * @param pVM VM handle.
455 * @param GCPtrPage Page to invalidate.
456 */
457VMMDECL(int) PGMPrefetchPage(PVM pVM, RTGCPTR GCPtrPage)
458{
459 STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,Prefetch), a);
460 int rc = PGM_BTH_PFN(PrefetchPage, pVM)(pVM, GCPtrPage);
461 STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,Prefetch), a);
462 AssertMsg(rc == VINF_SUCCESS || rc == VINF_PGM_SYNC_CR3 || RT_FAILURE(rc), ("rc=%Rrc\n", rc));
463 return rc;
464}
465
466
467/**
468 * Gets the mapping corresponding to the specified address (if any).
469 *
470 * @returns Pointer to the mapping.
471 * @returns NULL if not
472 *
473 * @param pVM The virtual machine.
474 * @param GCPtr The guest context pointer.
475 */
476PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr)
477{
478 PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
479 while (pMapping)
480 {
481 if ((uintptr_t)GCPtr < (uintptr_t)pMapping->GCPtr)
482 break;
483 if ((uintptr_t)GCPtr - (uintptr_t)pMapping->GCPtr < pMapping->cb)
484 return pMapping;
485 pMapping = pMapping->CTX_SUFF(pNext);
486 }
487 return NULL;
488}
489
490
491/**
492 * Verifies a range of pages for read or write access
493 *
494 * Only checks the guest's page tables
495 *
496 * @returns VBox status code.
497 * @param pVM VM handle.
498 * @param Addr Guest virtual address to check
499 * @param cbSize Access size
500 * @param fAccess Access type (r/w, user/supervisor (X86_PTE_*))
501 * @remarks Current not in use.
502 */
503VMMDECL(int) PGMIsValidAccess(PVM pVM, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess)
504{
505 /*
506 * Validate input.
507 */
508 if (fAccess & ~(X86_PTE_US | X86_PTE_RW))
509 {
510 AssertMsgFailed(("PGMIsValidAccess: invalid access type %08x\n", fAccess));
511 return VERR_INVALID_PARAMETER;
512 }
513
514 uint64_t fPage;
515 int rc = PGMGstGetPage(pVM, (RTGCPTR)Addr, &fPage, NULL);
516 if (RT_FAILURE(rc))
517 {
518 Log(("PGMIsValidAccess: access violation for %RGv rc=%d\n", Addr, rc));
519 return VINF_EM_RAW_GUEST_TRAP;
520 }
521
522 /*
523 * Check if the access would cause a page fault
524 *
525 * Note that hypervisor page directories are not present in the guest's tables, so this check
526 * is sufficient.
527 */
528 bool fWrite = !!(fAccess & X86_PTE_RW);
529 bool fUser = !!(fAccess & X86_PTE_US);
530 if ( !(fPage & X86_PTE_P)
531 || (fWrite && !(fPage & X86_PTE_RW))
532 || (fUser && !(fPage & X86_PTE_US)) )
533 {
534 Log(("PGMIsValidAccess: access violation for %RGv attr %#llx vs %d:%d\n", Addr, fPage, fWrite, fUser));
535 return VINF_EM_RAW_GUEST_TRAP;
536 }
537 if ( RT_SUCCESS(rc)
538 && PAGE_ADDRESS(Addr) != PAGE_ADDRESS(Addr + cbSize))
539 return PGMIsValidAccess(pVM, Addr + PAGE_SIZE, (cbSize > PAGE_SIZE) ? cbSize - PAGE_SIZE : 1, fAccess);
540 return rc;
541}
542
543
544/**
545 * Verifies a range of pages for read or write access
546 *
547 * Supports handling of pages marked for dirty bit tracking and CSAM
548 *
549 * @returns VBox status code.
550 * @param pVM VM handle.
551 * @param Addr Guest virtual address to check
552 * @param cbSize Access size
553 * @param fAccess Access type (r/w, user/supervisor (X86_PTE_*))
554 */
555VMMDECL(int) PGMVerifyAccess(PVM pVM, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess)
556{
557 AssertMsg(!(fAccess & ~(X86_PTE_US | X86_PTE_RW)), ("PGMVerifyAccess: invalid access type %08x\n", fAccess));
558
559 /*
560 * Get going.
561 */
562 uint64_t fPageGst;
563 int rc = PGMGstGetPage(pVM, (RTGCPTR)Addr, &fPageGst, NULL);
564 if (RT_FAILURE(rc))
565 {
566 Log(("PGMVerifyAccess: access violation for %RGv rc=%d\n", Addr, rc));
567 return VINF_EM_RAW_GUEST_TRAP;
568 }
569
570 /*
571 * Check if the access would cause a page fault
572 *
573 * Note that hypervisor page directories are not present in the guest's tables, so this check
574 * is sufficient.
575 */
576 const bool fWrite = !!(fAccess & X86_PTE_RW);
577 const bool fUser = !!(fAccess & X86_PTE_US);
578 if ( !(fPageGst & X86_PTE_P)
579 || (fWrite && !(fPageGst & X86_PTE_RW))
580 || (fUser && !(fPageGst & X86_PTE_US)) )
581 {
582 Log(("PGMVerifyAccess: access violation for %RGv attr %#llx vs %d:%d\n", Addr, fPageGst, fWrite, fUser));
583 return VINF_EM_RAW_GUEST_TRAP;
584 }
585
586 if (!HWACCMIsNestedPagingActive(pVM))
587 {
588 /*
589 * Next step is to verify if we protected this page for dirty bit tracking or for CSAM scanning
590 */
591 rc = PGMShwGetPage(pVM, (RTGCPTR)Addr, NULL, NULL);
592 if ( rc == VERR_PAGE_NOT_PRESENT
593 || rc == VERR_PAGE_TABLE_NOT_PRESENT)
594 {
595 /*
596 * Page is not present in our page tables.
597 * Try to sync it!
598 */
599 Assert(X86_TRAP_PF_RW == X86_PTE_RW && X86_TRAP_PF_US == X86_PTE_US);
600 uint32_t uErr = fAccess & (X86_TRAP_PF_RW | X86_TRAP_PF_US);
601 rc = PGM_BTH_PFN(VerifyAccessSyncPage, pVM)(pVM, Addr, fPageGst, uErr);
602 if (rc != VINF_SUCCESS)
603 return rc;
604 }
605 else
606 AssertMsg(rc == VINF_SUCCESS, ("PGMShwGetPage %RGv failed with %Rrc\n", Addr, rc));
607 }
608
609#if 0 /* def VBOX_STRICT; triggers too often now */
610 /*
611 * This check is a bit paranoid, but useful.
612 */
613 /** @note this will assert when writing to monitored pages (a bit annoying actually) */
614 uint64_t fPageShw;
615 rc = PGMShwGetPage(pVM, (RTGCPTR)Addr, &fPageShw, NULL);
616 if ( (rc == VERR_PAGE_NOT_PRESENT || RT_FAILURE(rc))
617 || (fWrite && !(fPageShw & X86_PTE_RW))
618 || (fUser && !(fPageShw & X86_PTE_US)) )
619 {
620 AssertMsgFailed(("Unexpected access violation for %RGv! rc=%Rrc write=%d user=%d\n",
621 Addr, rc, fWrite && !(fPageShw & X86_PTE_RW), fUser && !(fPageShw & X86_PTE_US)));
622 return VINF_EM_RAW_GUEST_TRAP;
623 }
624#endif
625
626 if ( RT_SUCCESS(rc)
627 && ( PAGE_ADDRESS(Addr) != PAGE_ADDRESS(Addr + cbSize - 1)
628 || Addr + cbSize < Addr))
629 {
630 /* Don't recursively call PGMVerifyAccess as we might run out of stack. */
631 for (;;)
632 {
633 Addr += PAGE_SIZE;
634 if (cbSize > PAGE_SIZE)
635 cbSize -= PAGE_SIZE;
636 else
637 cbSize = 1;
638 rc = PGMVerifyAccess(pVM, Addr, 1, fAccess);
639 if (rc != VINF_SUCCESS)
640 break;
641 if (PAGE_ADDRESS(Addr) == PAGE_ADDRESS(Addr + cbSize - 1))
642 break;
643 }
644 }
645 return rc;
646}
647
648
649/**
650 * Emulation of the invlpg instruction (HC only actually).
651 *
652 * @returns VBox status code, special care required.
653 * @retval VINF_PGM_SYNC_CR3 - handled.
654 * @retval VINF_EM_RAW_EMULATE_INSTR - not handled (RC only).
655 * @retval VERR_REM_FLUSHED_PAGES_OVERFLOW - not handled.
656 *
657 * @param pVM VM handle.
658 * @param GCPtrPage Page to invalidate.
659 *
660 * @remark ASSUMES the page table entry or page directory is valid. Fairly
661 * safe, but there could be edge cases!
662 *
663 * @todo Flush page or page directory only if necessary!
664 */
665VMMDECL(int) PGMInvalidatePage(PVM pVM, RTGCPTR GCPtrPage)
666{
667 int rc;
668 Log3(("PGMInvalidatePage: GCPtrPage=%RGv\n", GCPtrPage));
669
670#ifndef IN_RING3
671 /*
672 * Notify the recompiler so it can record this instruction.
673 * Failure happens when it's out of space. We'll return to HC in that case.
674 */
675 rc = REMNotifyInvalidatePage(pVM, GCPtrPage);
676 if (rc != VINF_SUCCESS)
677 return rc;
678#endif /* !IN_RING3 */
679
680
681#ifdef IN_RC
682 /*
683 * Check for conflicts and pending CR3 monitoring updates.
684 */
685 if (!pVM->pgm.s.fMappingsFixed)
686 {
687 if ( pgmGetMapping(pVM, GCPtrPage)
688 && PGMGstGetPage(pVM, GCPtrPage, NULL, NULL) != VERR_PAGE_TABLE_NOT_PRESENT)
689 {
690 LogFlow(("PGMGCInvalidatePage: Conflict!\n"));
691 VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
692 STAM_COUNTER_INC(&pVM->pgm.s.StatRCInvlPgConflict);
693 return VINF_PGM_SYNC_CR3;
694 }
695
696 if (pVM->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
697 {
698 LogFlow(("PGMGCInvalidatePage: PGM_SYNC_MONITOR_CR3 -> reinterpret instruction in R3\n"));
699 STAM_COUNTER_INC(&pVM->pgm.s.StatRCInvlPgSyncMonCR3);
700 return VINF_EM_RAW_EMULATE_INSTR;
701 }
702 }
703#endif /* IN_RC */
704
705 /*
706 * Call paging mode specific worker.
707 */
708 STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePage), a);
709 rc = PGM_BTH_PFN(InvalidatePage, pVM)(pVM, GCPtrPage);
710 STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePage), a);
711
712#ifdef IN_RING3
713 /*
714 * Check if we have a pending update of the CR3 monitoring.
715 */
716 if ( RT_SUCCESS(rc)
717 && (pVM->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3))
718 {
719 pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
720 Assert(!pVM->pgm.s.fMappingsFixed);
721#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
722 Assert(pVM->pgm.s.GCPhysCR3 == pVM->pgm.s.GCPhysGstCR3Monitored);
723 rc = PGM_GST_PFN(MonitorCR3, pVM)(pVM, pVM->pgm.s.GCPhysCR3);
724#endif
725 }
726
727 /*
728 * Inform CSAM about the flush
729 *
730 * Note: This is to check if monitored pages have been changed; when we implement
731 * callbacks for virtual handlers, this is no longer required.
732 */
733 CSAMR3FlushPage(pVM, GCPtrPage);
734#endif /* IN_RING3 */
735 return rc;
736}
737
738
739/**
740 * Executes an instruction using the interpreter.
741 *
742 * @returns VBox status code (appropriate for trap handling and GC return).
743 * @param pVM VM handle.
744 * @param pRegFrame Register frame.
745 * @param pvFault Fault address.
746 */
747VMMDECL(int) PGMInterpretInstruction(PVM pVM, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
748{
749 uint32_t cb;
750 int rc = EMInterpretInstruction(pVM, pRegFrame, pvFault, &cb);
751 if (rc == VERR_EM_INTERPRETER)
752 rc = VINF_EM_RAW_EMULATE_INSTR;
753 if (rc != VINF_SUCCESS)
754 Log(("PGMInterpretInstruction: returns %Rrc (pvFault=%RGv)\n", rc, pvFault));
755 return rc;
756}
757
758
759/**
760 * Gets effective page information (from the VMM page directory).
761 *
762 * @returns VBox status.
763 * @param pVM VM Handle.
764 * @param GCPtr Guest Context virtual address of the page.
765 * @param pfFlags Where to store the flags. These are X86_PTE_*.
766 * @param pHCPhys Where to store the HC physical address of the page.
767 * This is page aligned.
768 * @remark You should use PGMMapGetPage() for pages in a mapping.
769 */
770VMMDECL(int) PGMShwGetPage(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys)
771{
772 return PGM_SHW_PFN(GetPage,pVM)(pVM, GCPtr, pfFlags, pHCPhys);
773}
774
775
776/**
777 * Sets (replaces) the page flags for a range of pages in the shadow context.
778 *
779 * @returns VBox status.
780 * @param pVM VM handle.
781 * @param GCPtr The address of the first page.
782 * @param cb The size of the range in bytes.
783 * @param fFlags Page flags X86_PTE_*, excluding the page mask of course.
784 * @remark You must use PGMMapSetPage() for pages in a mapping.
785 */
786VMMDECL(int) PGMShwSetPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags)
787{
788 return PGMShwModifyPage(pVM, GCPtr, cb, fFlags, 0);
789}
790
791
792/**
793 * Modify page flags for a range of pages in the shadow context.
794 *
795 * The existing flags are ANDed with the fMask and ORed with the fFlags.
796 *
797 * @returns VBox status code.
798 * @param pVM VM handle.
799 * @param GCPtr Virtual address of the first page in the range.
800 * @param cb Size (in bytes) of the range to apply the modification to.
801 * @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
802 * @param fMask The AND mask - page flags X86_PTE_*.
803 * Be very CAREFUL when ~'ing constants which could be 32-bit!
804 * @remark You must use PGMMapModifyPage() for pages in a mapping.
805 */
806VMMDECL(int) PGMShwModifyPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
807{
808 AssertMsg(!(fFlags & X86_PTE_PAE_PG_MASK), ("fFlags=%#llx\n", fFlags));
809 Assert(cb);
810
811 /*
812 * Align the input.
813 */
814 cb += GCPtr & PAGE_OFFSET_MASK;
815 cb = RT_ALIGN_Z(cb, PAGE_SIZE);
816 GCPtr = (GCPtr & PAGE_BASE_GC_MASK); /** @todo this ain't necessary, right... */
817
818 /*
819 * Call worker.
820 */
821 return PGM_SHW_PFN(ModifyPage, pVM)(pVM, GCPtr, cb, fFlags, fMask);
822}
823
824
825/**
826 * Gets the SHADOW page directory pointer for the specified address.
827 *
828 * @returns VBox status.
829 * @param pVM VM handle.
830 * @param GCPtr The address.
831 * @param ppPdpt Receives address of pdpt
832 * @param ppPD Receives address of page directory
833 * @remarks Unused.
834 */
835DECLINLINE(int) pgmShwGetPAEPDPtr(PVM pVM, RTGCPTR GCPtr, PX86PDPT *ppPdpt, PX86PDPAE *ppPD)
836{
837 PPGM pPGM = &pVM->pgm.s;
838 PPGMPOOL pPool = pPGM->CTX_SUFF(pPool);
839 PPGMPOOLPAGE pShwPage;
840
841 Assert(!HWACCMIsNestedPagingActive(pVM));
842
843 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
844 PX86PDPT pPdpt = pgmShwGetPaePDPTPtr(&pVM->pgm.s);
845 PX86PDPE pPdpe = &pPdpt->a[iPdPt];
846
847 *ppPdpt = pPdpt;
848 if (!pPdpe->n.u1Present)
849 return VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT;
850
851 pShwPage = pgmPoolGetPage(pPool, pPdpe->u & X86_PDPE_PG_MASK);
852 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
853
854 *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
855 return VINF_SUCCESS;
856}
857
858#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
859
860/**
861 * Gets the shadow page directory for the specified address, PAE.
862 *
863 * @returns Pointer to the shadow PD.
864 * @param pVM VM handle.
865 * @param GCPtr The address.
866 * @param pGstPdpe Guest PDPT entry
867 * @param ppPD Receives address of page directory
868 */
869int pgmShwSyncPaePDPtr(PVM pVM, RTGCPTR GCPtr, PX86PDPE pGstPdpe, PX86PDPAE *ppPD)
870{
871 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
872 PX86PDPT pPdpt = pgmShwGetPaePDPTPtr(&pVM->pgm.s);
873 PX86PDPE pPdpe = &pPdpt->a[iPdPt];
874 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
875 PPGMPOOLPAGE pShwPage;
876 int rc;
877
878 /* Allocate page directory if not present. */
879 if ( !pPdpe->n.u1Present
880 && !(pPdpe->u & X86_PDPE_PG_MASK))
881 {
882 bool fNestedPaging = HWACCMIsNestedPagingActive(pVM);
883 bool fPaging = !!(CPUMGetGuestCR0(pVM) & X86_CR0_PG);
884 RTGCPTR64 GCPdPt;
885 PGMPOOLKIND enmKind;
886
887 if (fNestedPaging || !fPaging)
888 {
889 /* AMD-V nested paging or real/protected mode without paging */
890 GCPdPt = (RTGCPTR64)iPdPt << X86_PDPT_SHIFT;
891 enmKind = PGMPOOLKIND_PAE_PD_PHYS;
892 }
893 else
894 {
895 Assert(pGstPdpe);
896
897 if (CPUMGetGuestCR4(pVM) & X86_CR4_PAE)
898 {
899 GCPdPt = pGstPdpe->u & X86_PDPE_PG_MASK;
900 enmKind = PGMPOOLKIND_PAE_PD_FOR_PAE_PD;
901 }
902 else
903 {
904 GCPdPt = CPUMGetGuestCR3(pVM);
905 enmKind = (PGMPOOLKIND)(PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD + iPdPt);
906 }
907 }
908
909 /* Create a reference back to the PDPT by using the index in its shadow page. */
910 rc = pgmPoolAlloc(pVM, GCPdPt, enmKind, pVM->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPdPt, &pShwPage);
911 if (rc == VERR_PGM_POOL_FLUSHED)
912 {
913 Log(("pgmShwSyncPaePDPtr: PGM pool flushed -> signal sync cr3\n"));
914 Assert(pVM->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL);
915 VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
916 return VINF_PGM_SYNC_CR3;
917 }
918 AssertRCReturn(rc, rc);
919 }
920 else
921 {
922 pShwPage = pgmPoolGetPage(pPool, pPdpe->u & X86_PDPE_PG_MASK);
923 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
924 }
925 /* The PD was cached or created; hook it up now. */
926 pPdpe->u |= pShwPage->Core.Key
927 | (pGstPdpe->u & ~(X86_PDPE_PG_MASK | X86_PDPE_AVL_MASK | X86_PDPE_PCD | X86_PDPE_PWT));
928
929 *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
930 return VINF_SUCCESS;
931}
932
933/**
934 * Gets the pointer to the shadow page directory entry for an address, PAE.
935 *
936 * @returns Pointer to the PDE.
937 * @param pPGM Pointer to the PGM instance data.
938 * @param GCPtr The address.
939 * @param ppShwPde Receives the address of the pgm pool page for the shadow page directory
940 */
941DECLINLINE(int) pgmShwGetPaePoolPagePD(PPGM pPGM, RTGCPTR GCPtr, PPGMPOOLPAGE *ppShwPde)
942{
943 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
944 PX86PDPT pPdpt = pgmShwGetPaePDPTPtr(pPGM);
945 AssertReturn(pPdpt, VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT); /* can't happen */
946 if (!pPdpt->a[iPdPt].n.u1Present)
947 {
948 LogFlow(("pgmShwGetPaePoolPagePD: PD %d not present (%RX64)\n", iPdPt, pPdpt->a[iPdPt].u));
949 return VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT;
950 }
951
952 /* Fetch the pgm pool shadow descriptor. */
953 PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(PGM2VM(pPGM), pPdpt->a[iPdPt].u & X86_PDPE_PG_MASK);
954 AssertReturn(pShwPde, VERR_INTERNAL_ERROR);
955
956 *ppShwPde = pShwPde;
957 return VINF_SUCCESS;
958}
959#endif
960
961#ifndef IN_RC
962
963/**
964 * Syncs the SHADOW page directory pointer for the specified address.
965 *
966 * Allocates backing pages in case the PDPT or PML4 entry is missing.
967 *
968 * The caller is responsible for making sure the guest has a valid PD before
969 * calling this function.
970 *
971 * @returns VBox status.
972 * @param pVM VM handle.
973 * @param GCPtr The address.
974 * @param pGstPml4e Guest PML4 entry
975 * @param pGstPdpe Guest PDPT entry
976 * @param ppPD Receives address of page directory
977 */
978int pgmShwSyncLongModePDPtr(PVM pVM, RTGCPTR64 GCPtr, PX86PML4E pGstPml4e, PX86PDPE pGstPdpe, PX86PDPAE *ppPD)
979{
980 PPGM pPGM = &pVM->pgm.s;
981 PPGMPOOL pPool = pPGM->CTX_SUFF(pPool);
982 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
983 PX86PML4E pPml4e = pgmShwGetLongModePML4EPtr(pPGM, iPml4);
984 bool fNestedPaging = HWACCMIsNestedPagingActive(pVM);
985#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
986 bool fPaging = !!(CPUMGetGuestCR0(pVM) & X86_CR0_PG);
987#endif
988 PPGMPOOLPAGE pShwPage;
989 int rc;
990
991 /* Allocate page directory pointer table if not present. */
992 if ( !pPml4e->n.u1Present
993 && !(pPml4e->u & X86_PML4E_PG_MASK))
994 {
995#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
996 RTGCPTR64 GCPml4;
997 PGMPOOLKIND enmKind;
998
999 Assert(pVM->pgm.s.CTX_SUFF(pShwPageCR3));
1000
1001 if (fNestedPaging || !fPaging)
1002 {
1003 /* AMD-V nested paging or real/protected mode without paging */
1004 GCPml4 = (RTGCPTR64)iPml4 << X86_PML4_SHIFT;
1005 enmKind = PGMPOOLKIND_64BIT_PDPT_FOR_PHYS;
1006 }
1007 else
1008 {
1009 Assert(pGstPml4e && pGstPdpe);
1010
1011 GCPml4 = pGstPml4e->u & X86_PML4E_PG_MASK;
1012 enmKind = PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT;
1013 }
1014
1015 /* Create a reference back to the PDPT by using the index in its shadow page. */
1016 rc = pgmPoolAlloc(pVM, GCPml4, enmKind, pVM->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPml4, &pShwPage);
1017#else
1018 if (!fNestedPaging)
1019 {
1020 Assert(pGstPml4e && pGstPdpe);
1021 Assert(pVM->pgm.s.CTX_SUFF(pShwPageCR3));
1022
1023 rc = pgmPoolAlloc(pVM, pGstPml4e->u & X86_PML4E_PG_MASK,
1024 PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT, pVM->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPml4, &pShwPage);
1025 }
1026 else
1027 {
1028 /* AMD-V nested paging. (Intel EPT never comes here) */
1029 RTGCPTR64 GCPml4 = (RTGCPTR64)iPml4 << EPT_PML4_SHIFT;
1030 rc = pgmPoolAlloc(pVM, GCPml4 + RT_BIT_64(63) /* hack: make the address unique */,
1031 PGMPOOLKIND_64BIT_PDPT_FOR_PHYS, PGMPOOL_IDX_NESTED_ROOT, iPml4, &pShwPage);
1032 }
1033#endif
1034 if (rc == VERR_PGM_POOL_FLUSHED)
1035 {
1036 Log(("PGMShwSyncLongModePDPtr: PGM pool flushed (1) -> signal sync cr3\n"));
1037 Assert(pVM->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL);
1038 VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
1039 return VINF_PGM_SYNC_CR3;
1040 }
1041 AssertRCReturn(rc, rc);
1042 }
1043 else
1044 {
1045 pShwPage = pgmPoolGetPage(pPool, pPml4e->u & X86_PML4E_PG_MASK);
1046 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1047 }
1048 /* The PDPT was cached or created; hook it up now. */
1049 pPml4e->u |= pShwPage->Core.Key
1050 | (pGstPml4e->u & ~(X86_PML4E_PG_MASK | X86_PML4E_AVL_MASK | X86_PML4E_PCD | X86_PML4E_PWT));
1051
1052 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1053 PX86PDPT pPdpt = (PX86PDPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1054 PX86PDPE pPdpe = &pPdpt->a[iPdPt];
1055
1056 /* Allocate page directory if not present. */
1057 if ( !pPdpe->n.u1Present
1058 && !(pPdpe->u & X86_PDPE_PG_MASK))
1059 {
1060#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
1061 RTGCPTR64 GCPdPt;
1062 PGMPOOLKIND enmKind;
1063
1064 if (fNestedPaging || !fPaging)
1065 {
1066 /* AMD-V nested paging or real/protected mode without paging */
1067 GCPdPt = (RTGCPTR64)iPdPt << X86_PDPT_SHIFT;
1068 enmKind = PGMPOOLKIND_64BIT_PD_FOR_PHYS;
1069 }
1070 else
1071 {
1072 Assert(pGstPdpe);
1073
1074 GCPdPt = pGstPdpe->u & X86_PDPE_PG_MASK;
1075 enmKind = PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD;
1076 }
1077
1078 /* Create a reference back to the PDPT by using the index in its shadow page. */
1079 rc = pgmPoolAlloc(pVM, GCPdPt, enmKind, pShwPage->idx, iPdPt, &pShwPage);
1080#else
1081 if (!fNestedPaging)
1082 {
1083 Assert(pGstPml4e && pGstPdpe);
1084 Assert(!(pPdpe->u & X86_PDPE_PG_MASK));
1085 /* Create a reference back to the PDPT by using the index in its shadow page. */
1086 rc = pgmPoolAlloc(pVM, pGstPdpe->u & X86_PDPE_PG_MASK, PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD, pShwPage->idx, iPdPt, &pShwPage);
1087 }
1088 else
1089 {
1090 /* AMD-V nested paging. (Intel EPT never comes here) */
1091 RTGCPTR64 GCPdPt = (RTGCPTR64)iPdPt << EPT_PDPT_SHIFT;
1092
1093 rc = pgmPoolAlloc(pVM, GCPdPt + RT_BIT_64(62) /* hack: make the address unique */, PGMPOOLKIND_64BIT_PD_FOR_PHYS, pShwPage->idx, iPdPt, &pShwPage);
1094 }
1095#endif
1096 if (rc == VERR_PGM_POOL_FLUSHED)
1097 {
1098 Log(("PGMShwSyncLongModePDPtr: PGM pool flushed (2) -> signal sync cr3\n"));
1099 Assert(pVM->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL);
1100 VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
1101 return VINF_PGM_SYNC_CR3;
1102 }
1103 AssertRCReturn(rc, rc);
1104 }
1105 else
1106 {
1107 pShwPage = pgmPoolGetPage(pPool, pPdpe->u & X86_PDPE_PG_MASK);
1108 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1109 }
1110 /* The PD was cached or created; hook it up now. */
1111 pPdpe->u |= pShwPage->Core.Key
1112 | (pGstPdpe->u & ~(X86_PDPE_PG_MASK | X86_PDPE_AVL_MASK | X86_PDPE_PCD | X86_PDPE_PWT));
1113
1114 *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1115 return VINF_SUCCESS;
1116}
1117
1118
1119/**
1120 * Gets the SHADOW page directory pointer for the specified address (long mode).
1121 *
1122 * @returns VBox status.
1123 * @param pVM VM handle.
1124 * @param GCPtr The address.
1125 * @param ppPdpt Receives address of pdpt
1126 * @param ppPD Receives address of page directory
1127 */
1128DECLINLINE(int) pgmShwGetLongModePDPtr(PVM pVM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPT *ppPdpt, PX86PDPAE *ppPD)
1129{
1130 PPGM pPGM = &pVM->pgm.s;
1131 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
1132 PCX86PML4E pPml4e = pgmShwGetLongModePML4EPtr(pPGM, iPml4);
1133 AssertReturn(pPml4e, VERR_INTERNAL_ERROR);
1134 if (ppPml4e)
1135 *ppPml4e = (PX86PML4E)pPml4e;
1136 if (!pPml4e->n.u1Present)
1137 return VERR_PAGE_MAP_LEVEL4_NOT_PRESENT;
1138
1139 PPGMPOOL pPool = pPGM->CTX_SUFF(pPool);
1140 PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPml4e->u & X86_PML4E_PG_MASK);
1141 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1142
1143 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1144 PCX86PDPT pPdpt = *ppPdpt = (PX86PDPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1145 if (!pPdpt->a[iPdPt].n.u1Present)
1146 return VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT;
1147
1148 pShwPage = pgmPoolGetPage(pPool, pPdpt->a[iPdPt].u & X86_PDPE_PG_MASK);
1149 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1150
1151 *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1152 return VINF_SUCCESS;
1153}
1154
1155
1156/**
1157 * Syncs the SHADOW EPT page directory pointer for the specified address. Allocates
1158 * backing pages in case the PDPT or PML4 entry is missing.
1159 *
1160 * @returns VBox status.
1161 * @param pVM VM handle.
1162 * @param GCPtr The address.
1163 * @param ppPdpt Receives address of pdpt
1164 * @param ppPD Receives address of page directory
1165 */
1166int pgmShwGetEPTPDPtr(PVM pVM, RTGCPTR64 GCPtr, PEPTPDPT *ppPdpt, PEPTPD *ppPD)
1167{
1168 PPGM pPGM = &pVM->pgm.s;
1169 const unsigned iPml4 = (GCPtr >> EPT_PML4_SHIFT) & EPT_PML4_MASK;
1170 PPGMPOOL pPool = pPGM->CTX_SUFF(pPool);
1171 PEPTPML4 pPml4;
1172 PEPTPML4E pPml4e;
1173 PPGMPOOLPAGE pShwPage;
1174 int rc;
1175
1176 Assert(HWACCMIsNestedPagingActive(pVM));
1177
1178# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
1179 rc = PGM_HCPHYS_2_PTR(pVM, pPGM->HCPhysShwNestedRoot, &pPml4);
1180 AssertRCReturn(rc, rc);
1181# else
1182 pPml4 = (PEPTPML4)pPGM->CTX_SUFF(pShwNestedRoot);
1183# endif
1184 Assert(pPml4);
1185
1186 /* Allocate page directory pointer table if not present. */
1187 pPml4e = &pPml4->a[iPml4];
1188 if ( !pPml4e->n.u1Present
1189 && !(pPml4e->u & EPT_PML4E_PG_MASK))
1190 {
1191 Assert(!(pPml4e->u & EPT_PML4E_PG_MASK));
1192 RTGCPTR64 GCPml4 = (RTGCPTR64)iPml4 << EPT_PML4_SHIFT;
1193
1194#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
1195 rc = pgmPoolAlloc(pVM, GCPml4, PGMPOOLKIND_EPT_PDPT_FOR_PHYS, PGMPOOL_IDX_NESTED_ROOT, iPml4, &pShwPage);
1196#else
1197 rc = pgmPoolAlloc(pVM, GCPml4 + RT_BIT_64(63) /* hack: make the address unique */, PGMPOOLKIND_EPT_PDPT_FOR_PHYS, PGMPOOL_IDX_NESTED_ROOT, iPml4, &pShwPage);
1198#endif
1199 if (rc == VERR_PGM_POOL_FLUSHED)
1200 {
1201 Log(("PGMShwSyncEPTPDPtr: PGM pool flushed (1) -> signal sync cr3\n"));
1202 Assert(pVM->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL);
1203 VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
1204 return VINF_PGM_SYNC_CR3;
1205 }
1206 AssertRCReturn(rc, rc);
1207 }
1208 else
1209 {
1210 pShwPage = pgmPoolGetPage(pPool, pPml4e->u & EPT_PML4E_PG_MASK);
1211 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1212 }
1213 /* The PDPT was cached or created; hook it up now and fill with the default value. */
1214 pPml4e->u = pShwPage->Core.Key;
1215 pPml4e->n.u1Present = 1;
1216 pPml4e->n.u1Write = 1;
1217 pPml4e->n.u1Execute = 1;
1218
1219 const unsigned iPdPt = (GCPtr >> EPT_PDPT_SHIFT) & EPT_PDPT_MASK;
1220 PEPTPDPT pPdpt = (PEPTPDPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1221 PEPTPDPTE pPdpe = &pPdpt->a[iPdPt];
1222
1223 if (ppPdpt)
1224 *ppPdpt = pPdpt;
1225
1226 /* Allocate page directory if not present. */
1227 if ( !pPdpe->n.u1Present
1228 && !(pPdpe->u & EPT_PDPTE_PG_MASK))
1229 {
1230 RTGCPTR64 GCPdPt = (RTGCPTR64)iPdPt << EPT_PDPT_SHIFT;
1231
1232#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
1233 rc = pgmPoolAlloc(pVM, GCPdPt, PGMPOOLKIND_64BIT_PD_FOR_PHYS, pShwPage->idx, iPdPt, &pShwPage);
1234#else
1235 rc = pgmPoolAlloc(pVM, GCPdPt + RT_BIT_64(62) /* hack: make the address unique */, PGMPOOLKIND_64BIT_PD_FOR_PHYS, pShwPage->idx, iPdPt, &pShwPage);
1236#endif
1237 if (rc == VERR_PGM_POOL_FLUSHED)
1238 {
1239 Log(("PGMShwSyncEPTPDPtr: PGM pool flushed (2) -> signal sync cr3\n"));
1240 Assert(pVM->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL);
1241 VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
1242 return VINF_PGM_SYNC_CR3;
1243 }
1244 AssertRCReturn(rc, rc);
1245 }
1246 else
1247 {
1248 pShwPage = pgmPoolGetPage(pPool, pPdpe->u & EPT_PDPTE_PG_MASK);
1249 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1250 }
1251 /* The PD was cached or created; hook it up now and fill with the default value. */
1252 pPdpe->u = pShwPage->Core.Key;
1253 pPdpe->n.u1Present = 1;
1254 pPdpe->n.u1Write = 1;
1255 pPdpe->n.u1Execute = 1;
1256
1257 *ppPD = (PEPTPD)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1258 return VINF_SUCCESS;
1259}
1260
1261#endif /* IN_RC */
1262
1263/**
1264 * Gets effective Guest OS page information.
1265 *
1266 * When GCPtr is in a big page, the function will return as if it was a normal
1267 * 4KB page. If the need for distinguishing between big and normal page becomes
1268 * necessary at a later point, a PGMGstGetPage() will be created for that
1269 * purpose.
1270 *
1271 * @returns VBox status.
1272 * @param pVM VM Handle.
1273 * @param GCPtr Guest Context virtual address of the page.
1274 * @param pfFlags Where to store the flags. These are X86_PTE_*, even for big pages.
1275 * @param pGCPhys Where to store the GC physical address of the page.
1276 * This is page aligned. The fact that the
1277 */
1278VMMDECL(int) PGMGstGetPage(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys)
1279{
1280 return PGM_GST_PFN(GetPage,pVM)(pVM, GCPtr, pfFlags, pGCPhys);
1281}
1282
1283
1284/**
1285 * Checks if the page is present.
1286 *
1287 * @returns true if the page is present.
1288 * @returns false if the page is not present.
1289 * @param pVM The VM handle.
1290 * @param GCPtr Address within the page.
1291 */
1292VMMDECL(bool) PGMGstIsPagePresent(PVM pVM, RTGCPTR GCPtr)
1293{
1294 int rc = PGMGstGetPage(pVM, GCPtr, NULL, NULL);
1295 return RT_SUCCESS(rc);
1296}
1297
1298
1299/**
1300 * Sets (replaces) the page flags for a range of pages in the guest's tables.
1301 *
1302 * @returns VBox status.
1303 * @param pVM VM handle.
1304 * @param GCPtr The address of the first page.
1305 * @param cb The size of the range in bytes.
1306 * @param fFlags Page flags X86_PTE_*, excluding the page mask of course.
1307 */
1308VMMDECL(int) PGMGstSetPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags)
1309{
1310 return PGMGstModifyPage(pVM, GCPtr, cb, fFlags, 0);
1311}
1312
1313
1314/**
1315 * Modify page flags for a range of pages in the guest's tables
1316 *
1317 * The existing flags are ANDed with the fMask and ORed with the fFlags.
1318 *
1319 * @returns VBox status code.
1320 * @param pVM VM handle.
1321 * @param GCPtr Virtual address of the first page in the range.
1322 * @param cb Size (in bytes) of the range to apply the modification to.
1323 * @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
1324 * @param fMask The AND mask - page flags X86_PTE_*, excluding the page mask of course.
1325 * Be very CAREFUL when ~'ing constants which could be 32-bit!
1326 */
1327VMMDECL(int) PGMGstModifyPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
1328{
1329 STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,GstModifyPage), a);
1330
1331 /*
1332 * Validate input.
1333 */
1334 AssertMsg(!(fFlags & X86_PTE_PAE_PG_MASK), ("fFlags=%#llx\n", fFlags));
1335 Assert(cb);
1336
1337 LogFlow(("PGMGstModifyPage %RGv %d bytes fFlags=%08llx fMask=%08llx\n", GCPtr, cb, fFlags, fMask));
1338
1339 /*
1340 * Adjust input.
1341 */
1342 cb += GCPtr & PAGE_OFFSET_MASK;
1343 cb = RT_ALIGN_Z(cb, PAGE_SIZE);
1344 GCPtr = (GCPtr & PAGE_BASE_GC_MASK);
1345
1346 /*
1347 * Call worker.
1348 */
1349 int rc = PGM_GST_PFN(ModifyPage, pVM)(pVM, GCPtr, cb, fFlags, fMask);
1350
1351 STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,GstModifyPage), a);
1352 return rc;
1353}
1354
1355
1356/**
1357 * Gets the specified page directory pointer table entry.
1358 *
1359 * @returns PDP entry
1360 * @param pPGM Pointer to the PGM instance data.
1361 * @param iPdpt PDPT index
1362 */
1363VMMDECL(X86PDPE) PGMGstGetPaePDPtr(PVM pVM, unsigned iPdpt)
1364{
1365 Assert(iPdpt <= 3);
1366 return pgmGstGetPaePDPTPtr(&pVM->pgm.s)->a[iPdpt & 3];
1367}
1368
1369
1370/**
1371 * Gets the current CR3 register value for the shadow memory context.
1372 * @returns CR3 value.
1373 * @param pVM The VM handle.
1374 */
1375VMMDECL(RTHCPHYS) PGMGetHyperCR3(PVM pVM)
1376{
1377#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
1378 PGMMODE enmShadowMode = pVM->pgm.s.enmShadowMode;
1379 switch (enmShadowMode)
1380 {
1381 case PGMMODE_EPT:
1382 return pVM->pgm.s.HCPhysShwNestedRoot;
1383
1384 default:
1385 return pVM->pgm.s.HCPhysShwCR3;
1386 }
1387#else
1388 PGMMODE enmShadowMode = pVM->pgm.s.enmShadowMode;
1389 switch (enmShadowMode)
1390 {
1391 case PGMMODE_32_BIT:
1392 return pVM->pgm.s.HCPhysShw32BitPD;
1393
1394 case PGMMODE_PAE:
1395 case PGMMODE_PAE_NX:
1396 return pVM->pgm.s.HCPhysShwPaePdpt;
1397
1398 case PGMMODE_AMD64:
1399 case PGMMODE_AMD64_NX:
1400 return pVM->pgm.s.HCPhysShwCR3;
1401
1402 case PGMMODE_EPT:
1403 return pVM->pgm.s.HCPhysShwNestedRoot;
1404
1405 case PGMMODE_NESTED:
1406 return PGMGetNestedCR3(pVM, PGMGetHostMode(pVM));
1407
1408 default:
1409 AssertMsgFailed(("enmShadowMode=%d\n", enmShadowMode));
1410 return ~0;
1411 }
1412#endif
1413}
1414
1415
1416/**
1417 * Gets the current CR3 register value for the nested memory context.
1418 * @returns CR3 value.
1419 * @param pVM The VM handle.
1420 */
1421VMMDECL(RTHCPHYS) PGMGetNestedCR3(PVM pVM, PGMMODE enmShadowMode)
1422{
1423#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
1424 return pVM->pgm.s.HCPhysShwCR3;
1425#else
1426 switch (enmShadowMode)
1427 {
1428 case PGMMODE_32_BIT:
1429 return pVM->pgm.s.HCPhysShw32BitPD;
1430
1431 case PGMMODE_PAE:
1432 case PGMMODE_PAE_NX:
1433 return pVM->pgm.s.HCPhysShwPaePdpt;
1434
1435 case PGMMODE_AMD64:
1436 case PGMMODE_AMD64_NX:
1437 return pVM->pgm.s.HCPhysShwCR3;
1438
1439 default:
1440 AssertMsgFailed(("enmShadowMode=%d\n", enmShadowMode));
1441 return ~0;
1442 }
1443#endif
1444}
1445
1446
1447/**
1448 * Gets the current CR3 register value for the EPT paging memory context.
1449 * @returns CR3 value.
1450 * @param pVM The VM handle.
1451 */
1452VMMDECL(RTHCPHYS) PGMGetEPTCR3(PVM pVM)
1453{
1454 return pVM->pgm.s.HCPhysShwNestedRoot;
1455}
1456
1457
1458/**
1459 * Gets the CR3 register value for the 32-Bit shadow memory context.
1460 * @returns CR3 value.
1461 * @param pVM The VM handle.
1462 */
1463VMMDECL(RTHCPHYS) PGMGetHyper32BitCR3(PVM pVM)
1464{
1465#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
1466 return pVM->pgm.s.HCPhysShwCR3;
1467#else
1468 return pVM->pgm.s.HCPhysShw32BitPD;
1469#endif
1470}
1471
1472
1473/**
1474 * Gets the CR3 register value for the PAE shadow memory context.
1475 * @returns CR3 value.
1476 * @param pVM The VM handle.
1477 */
1478VMMDECL(RTHCPHYS) PGMGetHyperPaeCR3(PVM pVM)
1479{
1480#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
1481 return pVM->pgm.s.HCPhysShwCR3;
1482#else
1483 return pVM->pgm.s.HCPhysShwPaePdpt;
1484#endif
1485}
1486
1487
1488/**
1489 * Gets the CR3 register value for the AMD64 shadow memory context.
1490 * @returns CR3 value.
1491 * @param pVM The VM handle.
1492 */
1493VMMDECL(RTHCPHYS) PGMGetHyperAmd64CR3(PVM pVM)
1494{
1495 return pVM->pgm.s.HCPhysShwCR3;
1496}
1497
1498/**
1499 * Gets the current CR3 register value for the HC intermediate memory context.
1500 * @returns CR3 value.
1501 * @param pVM The VM handle.
1502 */
1503VMMDECL(RTHCPHYS) PGMGetInterHCCR3(PVM pVM)
1504{
1505 switch (pVM->pgm.s.enmHostMode)
1506 {
1507 case SUPPAGINGMODE_32_BIT:
1508 case SUPPAGINGMODE_32_BIT_GLOBAL:
1509 return pVM->pgm.s.HCPhysInterPD;
1510
1511 case SUPPAGINGMODE_PAE:
1512 case SUPPAGINGMODE_PAE_GLOBAL:
1513 case SUPPAGINGMODE_PAE_NX:
1514 case SUPPAGINGMODE_PAE_GLOBAL_NX:
1515 return pVM->pgm.s.HCPhysInterPaePDPT;
1516
1517 case SUPPAGINGMODE_AMD64:
1518 case SUPPAGINGMODE_AMD64_GLOBAL:
1519 case SUPPAGINGMODE_AMD64_NX:
1520 case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1521 return pVM->pgm.s.HCPhysInterPaePDPT;
1522
1523 default:
1524 AssertMsgFailed(("enmHostMode=%d\n", pVM->pgm.s.enmHostMode));
1525 return ~0;
1526 }
1527}
1528
1529
1530/**
1531 * Gets the current CR3 register value for the RC intermediate memory context.
1532 * @returns CR3 value.
1533 * @param pVM The VM handle.
1534 */
1535VMMDECL(RTHCPHYS) PGMGetInterRCCR3(PVM pVM)
1536{
1537 switch (pVM->pgm.s.enmShadowMode)
1538 {
1539 case PGMMODE_32_BIT:
1540 return pVM->pgm.s.HCPhysInterPD;
1541
1542 case PGMMODE_PAE:
1543 case PGMMODE_PAE_NX:
1544 return pVM->pgm.s.HCPhysInterPaePDPT;
1545
1546 case PGMMODE_AMD64:
1547 case PGMMODE_AMD64_NX:
1548 return pVM->pgm.s.HCPhysInterPaePML4;
1549
1550 case PGMMODE_EPT:
1551 case PGMMODE_NESTED:
1552 return 0; /* not relevant */
1553
1554 default:
1555 AssertMsgFailed(("enmShadowMode=%d\n", pVM->pgm.s.enmShadowMode));
1556 return ~0;
1557 }
1558}
1559
1560
1561/**
1562 * Gets the CR3 register value for the 32-Bit intermediate memory context.
1563 * @returns CR3 value.
1564 * @param pVM The VM handle.
1565 */
1566VMMDECL(RTHCPHYS) PGMGetInter32BitCR3(PVM pVM)
1567{
1568 return pVM->pgm.s.HCPhysInterPD;
1569}
1570
1571
1572/**
1573 * Gets the CR3 register value for the PAE intermediate memory context.
1574 * @returns CR3 value.
1575 * @param pVM The VM handle.
1576 */
1577VMMDECL(RTHCPHYS) PGMGetInterPaeCR3(PVM pVM)
1578{
1579 return pVM->pgm.s.HCPhysInterPaePDPT;
1580}
1581
1582
1583/**
1584 * Gets the CR3 register value for the AMD64 intermediate memory context.
1585 * @returns CR3 value.
1586 * @param pVM The VM handle.
1587 */
1588VMMDECL(RTHCPHYS) PGMGetInterAmd64CR3(PVM pVM)
1589{
1590 return pVM->pgm.s.HCPhysInterPaePML4;
1591}
1592
1593
1594/**
1595 * Performs and schedules necessary updates following a CR3 load or reload.
1596 *
1597 * This will normally involve mapping the guest PD or nPDPT
1598 *
1599 * @returns VBox status code.
1600 * @retval VINF_PGM_SYNC_CR3 if monitoring requires a CR3 sync. This can
1601 * safely be ignored and overridden since the FF will be set too then.
1602 * @param pVM VM handle.
1603 * @param cr3 The new cr3.
1604 * @param fGlobal Indicates whether this is a global flush or not.
1605 */
1606VMMDECL(int) PGMFlushTLB(PVM pVM, uint64_t cr3, bool fGlobal)
1607{
1608 STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,FlushTLB), a);
1609
1610 /*
1611 * Always flag the necessary updates; necessary for hardware acceleration
1612 */
1613 /** @todo optimize this, it shouldn't always be necessary. */
1614 VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
1615 if (fGlobal)
1616 VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
1617 LogFlow(("PGMFlushTLB: cr3=%RX64 OldCr3=%RX64 fGlobal=%d\n", cr3, pVM->pgm.s.GCPhysCR3, fGlobal));
1618
1619 /*
1620 * Remap the CR3 content and adjust the monitoring if CR3 was actually changed.
1621 */
1622 int rc = VINF_SUCCESS;
1623 RTGCPHYS GCPhysCR3;
1624 if ( pVM->pgm.s.enmGuestMode == PGMMODE_PAE
1625 || pVM->pgm.s.enmGuestMode == PGMMODE_PAE_NX
1626 || pVM->pgm.s.enmGuestMode == PGMMODE_AMD64
1627 || pVM->pgm.s.enmGuestMode == PGMMODE_AMD64_NX)
1628 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAE_PAGE_MASK);
1629 else
1630 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAGE_MASK);
1631 if (pVM->pgm.s.GCPhysCR3 != GCPhysCR3)
1632 {
1633#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
1634 /* Unmap the old CR3 value before activating the new one. */
1635 rc = PGM_BTH_PFN(UnmapCR3, pVM)(pVM);
1636 AssertRC(rc);
1637#endif
1638 RTGCPHYS GCPhysOldCR3 = pVM->pgm.s.GCPhysCR3;
1639 pVM->pgm.s.GCPhysCR3 = GCPhysCR3;
1640 rc = PGM_BTH_PFN(MapCR3, pVM)(pVM, GCPhysCR3);
1641 if (RT_LIKELY(rc == VINF_SUCCESS))
1642 {
1643 if (!pVM->pgm.s.fMappingsFixed)
1644 {
1645 pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
1646#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1647 rc = PGM_GST_PFN(MonitorCR3, pVM)(pVM, GCPhysCR3);
1648#endif
1649 }
1650 }
1651 else
1652 {
1653 AssertMsg(rc == VINF_PGM_SYNC_CR3, ("%Rrc\n", rc));
1654 Assert(VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL | VM_FF_PGM_SYNC_CR3));
1655 pVM->pgm.s.GCPhysCR3 = GCPhysOldCR3;
1656 pVM->pgm.s.fSyncFlags |= PGM_SYNC_MAP_CR3;
1657 if (!pVM->pgm.s.fMappingsFixed)
1658 pVM->pgm.s.fSyncFlags |= PGM_SYNC_MONITOR_CR3;
1659 }
1660
1661 if (fGlobal)
1662 STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,FlushTLBNewCR3Global));
1663 else
1664 STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,FlushTLBNewCR3));
1665 }
1666 else
1667 {
1668 /*
1669 * Check if we have a pending update of the CR3 monitoring.
1670 */
1671 if (pVM->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
1672 {
1673 pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
1674 Assert(!pVM->pgm.s.fMappingsFixed);
1675#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1676 rc = PGM_GST_PFN(MonitorCR3, pVM)(pVM, GCPhysCR3);
1677#endif
1678 }
1679 if (fGlobal)
1680 STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,FlushTLBSameCR3Global));
1681 else
1682 STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,FlushTLBSameCR3));
1683 }
1684
1685 STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,FlushTLB), a);
1686 return rc;
1687}
1688
1689
1690/**
1691 * Performs and schedules necessary updates following a CR3 load or reload when
1692 * using nested or extended paging.
1693 *
1694 * This API is an alterantive to PDMFlushTLB that avoids actually flushing the
1695 * TLB and triggering a SyncCR3.
1696 *
1697 * This will normally involve mapping the guest PD or nPDPT
1698 *
1699 * @returns VBox status code.
1700 * @retval VINF_SUCCESS.
1701 * @retval (If applied when not in nested mode: VINF_PGM_SYNC_CR3 if monitoring
1702 * requires a CR3 sync. This can safely be ignored and overridden since
1703 * the FF will be set too then.)
1704 * @param pVM VM handle.
1705 * @param cr3 The new cr3.
1706 */
1707VMMDECL(int) PGMUpdateCR3(PVM pVM, uint64_t cr3)
1708{
1709 LogFlow(("PGMUpdateCR3: cr3=%RX64 OldCr3=%RX64\n", cr3, pVM->pgm.s.GCPhysCR3));
1710
1711 /* We assume we're only called in nested paging mode. */
1712 Assert(pVM->pgm.s.fMappingsFixed);
1713 Assert(!(pVM->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3));
1714 Assert(pVM->pgm.s.enmShadowMode == PGMMODE_NESTED || pVM->pgm.s.enmShadowMode == PGMMODE_EPT);
1715
1716 /*
1717 * Remap the CR3 content and adjust the monitoring if CR3 was actually changed.
1718 */
1719 int rc = VINF_SUCCESS;
1720 RTGCPHYS GCPhysCR3;
1721 if ( pVM->pgm.s.enmGuestMode == PGMMODE_PAE
1722 || pVM->pgm.s.enmGuestMode == PGMMODE_PAE_NX
1723 || pVM->pgm.s.enmGuestMode == PGMMODE_AMD64
1724 || pVM->pgm.s.enmGuestMode == PGMMODE_AMD64_NX)
1725 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAE_PAGE_MASK);
1726 else
1727 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAGE_MASK);
1728 if (pVM->pgm.s.GCPhysCR3 != GCPhysCR3)
1729 {
1730 pVM->pgm.s.GCPhysCR3 = GCPhysCR3;
1731 rc = PGM_BTH_PFN(MapCR3, pVM)(pVM, GCPhysCR3);
1732 AssertRCSuccess(rc); /* Assumes VINF_PGM_SYNC_CR3 doesn't apply to nested paging. */
1733 }
1734 return rc;
1735}
1736
1737
1738/**
1739 * Synchronize the paging structures.
1740 *
1741 * This function is called in response to the VM_FF_PGM_SYNC_CR3 and
1742 * VM_FF_PGM_SYNC_CR3_NONGLOBAL. Those two force action flags are set
1743 * in several places, most importantly whenever the CR3 is loaded.
1744 *
1745 * @returns VBox status code.
1746 * @param pVM The virtual machine.
1747 * @param cr0 Guest context CR0 register
1748 * @param cr3 Guest context CR3 register
1749 * @param cr4 Guest context CR4 register
1750 * @param fGlobal Including global page directories or not
1751 */
1752VMMDECL(int) PGMSyncCR3(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
1753{
1754 int rc;
1755
1756 /*
1757 * We might be called when we shouldn't.
1758 *
1759 * The mode switching will ensure that the PD is resynced
1760 * after every mode switch. So, if we find ourselves here
1761 * when in protected or real mode we can safely disable the
1762 * FF and return immediately.
1763 */
1764 if (pVM->pgm.s.enmGuestMode <= PGMMODE_PROTECTED)
1765 {
1766 Assert((cr0 & (X86_CR0_PG | X86_CR0_PE)) != (X86_CR0_PG | X86_CR0_PE));
1767 VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3);
1768 VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
1769 return VINF_SUCCESS;
1770 }
1771
1772 /* If global pages are not supported, then all flushes are global. */
1773 if (!(cr4 & X86_CR4_PGE))
1774 fGlobal = true;
1775 LogFlow(("PGMSyncCR3: cr0=%RX64 cr3=%RX64 cr4=%RX64 fGlobal=%d[%d,%d]\n", cr0, cr3, cr4, fGlobal,
1776 VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3), VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL)));
1777
1778#ifdef PGMPOOL_WITH_MONITORING
1779 /*
1780 * The pool may have pending stuff and even require a return to ring-3 to
1781 * clear the whole thing.
1782 */
1783 rc = pgmPoolSyncCR3(pVM);
1784 if (rc != VINF_SUCCESS)
1785 return rc;
1786#endif
1787
1788 /*
1789 * Check if we need to finish an aborted MapCR3 call (see PGMFlushTLB).
1790 * This should be done before SyncCR3.
1791 */
1792 if (pVM->pgm.s.fSyncFlags & PGM_SYNC_MAP_CR3)
1793 {
1794 pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_MAP_CR3;
1795
1796 RTGCPHYS GCPhysCR3Old = pVM->pgm.s.GCPhysCR3;
1797 RTGCPHYS GCPhysCR3;
1798 if ( pVM->pgm.s.enmGuestMode == PGMMODE_PAE
1799 || pVM->pgm.s.enmGuestMode == PGMMODE_PAE_NX
1800 || pVM->pgm.s.enmGuestMode == PGMMODE_AMD64
1801 || pVM->pgm.s.enmGuestMode == PGMMODE_AMD64_NX)
1802 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAE_PAGE_MASK);
1803 else
1804 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAGE_MASK);
1805
1806#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
1807 if (pVM->pgm.s.GCPhysCR3 != GCPhysCR3)
1808 {
1809 /* Unmap the old CR3 value before activating the new one. */
1810 rc = PGM_BTH_PFN(UnmapCR3, pVM)(pVM);
1811 AssertRC(rc);
1812 }
1813#endif
1814
1815 pVM->pgm.s.GCPhysCR3 = GCPhysCR3;
1816 rc = PGM_BTH_PFN(MapCR3, pVM)(pVM, GCPhysCR3);
1817#ifdef IN_RING3
1818 if (rc == VINF_PGM_SYNC_CR3)
1819 rc = pgmPoolSyncCR3(pVM);
1820#else
1821 if (rc == VINF_PGM_SYNC_CR3)
1822 {
1823 pVM->pgm.s.GCPhysCR3 = GCPhysCR3Old;
1824 return rc;
1825 }
1826#endif
1827 AssertRCReturn(rc, rc);
1828 AssertRCSuccessReturn(rc, VERR_INTERNAL_ERROR);
1829 }
1830
1831 /*
1832 * Let the 'Bth' function do the work and we'll just keep track of the flags.
1833 */
1834 STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3), a);
1835 rc = PGM_BTH_PFN(SyncCR3, pVM)(pVM, cr0, cr3, cr4, fGlobal);
1836 STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3), a);
1837 AssertMsg(rc == VINF_SUCCESS || rc == VINF_PGM_SYNC_CR3 || RT_FAILURE(rc), ("rc=%Rrc\n", rc));
1838 if (rc == VINF_SUCCESS)
1839 {
1840 if (!(pVM->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS))
1841 {
1842 VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3);
1843 VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
1844 }
1845
1846 /*
1847 * Check if we have a pending update of the CR3 monitoring.
1848 */
1849 if (pVM->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
1850 {
1851 pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
1852 Assert(!pVM->pgm.s.fMappingsFixed);
1853#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1854 Assert(pVM->pgm.s.GCPhysCR3 == pVM->pgm.s.GCPhysGstCR3Monitored);
1855 rc = PGM_GST_PFN(MonitorCR3, pVM)(pVM, pVM->pgm.s.GCPhysCR3);
1856#endif
1857 }
1858 }
1859
1860 /*
1861 * Now flush the CR3 (guest context).
1862 */
1863 if (rc == VINF_SUCCESS)
1864 PGM_INVL_GUEST_TLBS();
1865 return rc;
1866}
1867
1868
1869/**
1870 * Called whenever CR0 or CR4 in a way which may change
1871 * the paging mode.
1872 *
1873 * @returns VBox status code fit for scheduling in GC and R0.
1874 * @retval VINF_SUCCESS if the was no change, or it was successfully dealt with.
1875 * @retval VINF_PGM_CHANGE_MODE if we're in GC or R0 and the mode changes.
1876 * @param pVM VM handle.
1877 * @param cr0 The new cr0.
1878 * @param cr4 The new cr4.
1879 * @param efer The new extended feature enable register.
1880 */
1881VMMDECL(int) PGMChangeMode(PVM pVM, uint64_t cr0, uint64_t cr4, uint64_t efer)
1882{
1883 PGMMODE enmGuestMode;
1884
1885 /*
1886 * Calc the new guest mode.
1887 */
1888 if (!(cr0 & X86_CR0_PE))
1889 enmGuestMode = PGMMODE_REAL;
1890 else if (!(cr0 & X86_CR0_PG))
1891 enmGuestMode = PGMMODE_PROTECTED;
1892 else if (!(cr4 & X86_CR4_PAE))
1893 enmGuestMode = PGMMODE_32_BIT;
1894 else if (!(efer & MSR_K6_EFER_LME))
1895 {
1896 if (!(efer & MSR_K6_EFER_NXE))
1897 enmGuestMode = PGMMODE_PAE;
1898 else
1899 enmGuestMode = PGMMODE_PAE_NX;
1900 }
1901 else
1902 {
1903 if (!(efer & MSR_K6_EFER_NXE))
1904 enmGuestMode = PGMMODE_AMD64;
1905 else
1906 enmGuestMode = PGMMODE_AMD64_NX;
1907 }
1908
1909 /*
1910 * Did it change?
1911 */
1912 if (pVM->pgm.s.enmGuestMode == enmGuestMode)
1913 return VINF_SUCCESS;
1914
1915 /* Flush the TLB */
1916 PGM_INVL_GUEST_TLBS();
1917
1918#ifdef IN_RING3
1919 return PGMR3ChangeMode(pVM, enmGuestMode);
1920#else
1921 LogFlow(("PGMChangeMode: returns VINF_PGM_CHANGE_MODE.\n"));
1922 return VINF_PGM_CHANGE_MODE;
1923#endif
1924}
1925
1926
1927/**
1928 * Gets the current guest paging mode.
1929 *
1930 * If you just need the CPU mode (real/protected/long), use CPUMGetGuestMode().
1931 *
1932 * @returns The current paging mode.
1933 * @param pVM The VM handle.
1934 */
1935VMMDECL(PGMMODE) PGMGetGuestMode(PVM pVM)
1936{
1937 return pVM->pgm.s.enmGuestMode;
1938}
1939
1940
1941/**
1942 * Gets the current shadow paging mode.
1943 *
1944 * @returns The current paging mode.
1945 * @param pVM The VM handle.
1946 */
1947VMMDECL(PGMMODE) PGMGetShadowMode(PVM pVM)
1948{
1949 return pVM->pgm.s.enmShadowMode;
1950}
1951
1952/**
1953 * Gets the current host paging mode.
1954 *
1955 * @returns The current paging mode.
1956 * @param pVM The VM handle.
1957 */
1958VMMDECL(PGMMODE) PGMGetHostMode(PVM pVM)
1959{
1960 switch (pVM->pgm.s.enmHostMode)
1961 {
1962 case SUPPAGINGMODE_32_BIT:
1963 case SUPPAGINGMODE_32_BIT_GLOBAL:
1964 return PGMMODE_32_BIT;
1965
1966 case SUPPAGINGMODE_PAE:
1967 case SUPPAGINGMODE_PAE_GLOBAL:
1968 return PGMMODE_PAE;
1969
1970 case SUPPAGINGMODE_PAE_NX:
1971 case SUPPAGINGMODE_PAE_GLOBAL_NX:
1972 return PGMMODE_PAE_NX;
1973
1974 case SUPPAGINGMODE_AMD64:
1975 case SUPPAGINGMODE_AMD64_GLOBAL:
1976 return PGMMODE_AMD64;
1977
1978 case SUPPAGINGMODE_AMD64_NX:
1979 case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1980 return PGMMODE_AMD64_NX;
1981
1982 default: AssertMsgFailed(("enmHostMode=%d\n", pVM->pgm.s.enmHostMode)); break;
1983 }
1984
1985 return PGMMODE_INVALID;
1986}
1987
1988
1989/**
1990 * Get mode name.
1991 *
1992 * @returns read-only name string.
1993 * @param enmMode The mode which name is desired.
1994 */
1995VMMDECL(const char *) PGMGetModeName(PGMMODE enmMode)
1996{
1997 switch (enmMode)
1998 {
1999 case PGMMODE_REAL: return "Real";
2000 case PGMMODE_PROTECTED: return "Protected";
2001 case PGMMODE_32_BIT: return "32-bit";
2002 case PGMMODE_PAE: return "PAE";
2003 case PGMMODE_PAE_NX: return "PAE+NX";
2004 case PGMMODE_AMD64: return "AMD64";
2005 case PGMMODE_AMD64_NX: return "AMD64+NX";
2006 case PGMMODE_NESTED: return "Nested";
2007 case PGMMODE_EPT: return "EPT";
2008 default: return "unknown mode value";
2009 }
2010}
2011
2012
2013/**
2014 * Acquire the PGM lock.
2015 *
2016 * @returns VBox status code
2017 * @param pVM The VM to operate on.
2018 */
2019int pgmLock(PVM pVM)
2020{
2021 int rc = PDMCritSectEnter(&pVM->pgm.s.CritSect, VERR_SEM_BUSY);
2022#ifdef IN_RC
2023 if (rc == VERR_SEM_BUSY)
2024 rc = VMMGCCallHost(pVM, VMMCALLHOST_PGM_LOCK, 0);
2025#elif defined(IN_RING0)
2026 if (rc == VERR_SEM_BUSY)
2027 rc = VMMR0CallHost(pVM, VMMCALLHOST_PGM_LOCK, 0);
2028#endif
2029 AssertRC(rc);
2030 return rc;
2031}
2032
2033
2034/**
2035 * Release the PGM lock.
2036 *
2037 * @returns VBox status code
2038 * @param pVM The VM to operate on.
2039 */
2040void pgmUnlock(PVM pVM)
2041{
2042 PDMCritSectLeave(&pVM->pgm.s.CritSect);
2043}
2044
2045#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2046
2047/**
2048 * Temporarily maps one guest page specified by GC physical address.
2049 * These pages must have a physical mapping in HC, i.e. they cannot be MMIO pages.
2050 *
2051 * Be WARNED that the dynamic page mapping area is small, 8 pages, thus the space is
2052 * reused after 8 mappings (or perhaps a few more if you score with the cache).
2053 *
2054 * @returns VBox status.
2055 * @param pVM VM handle.
2056 * @param GCPhys GC Physical address of the page.
2057 * @param ppv Where to store the address of the mapping.
2058 */
2059VMMDECL(int) PGMDynMapGCPage(PVM pVM, RTGCPHYS GCPhys, void **ppv)
2060{
2061 AssertMsg(!(GCPhys & PAGE_OFFSET_MASK), ("GCPhys=%RGp\n", GCPhys));
2062
2063 /*
2064 * Get the ram range.
2065 */
2066 PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
2067 while (pRam && GCPhys - pRam->GCPhys >= pRam->cb)
2068 pRam = pRam->CTX_SUFF(pNext);
2069 if (!pRam)
2070 {
2071 AssertMsgFailed(("Invalid physical address %RGp!\n", GCPhys));
2072 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2073 }
2074
2075 /*
2076 * Pass it on to PGMDynMapHCPage.
2077 */
2078 RTHCPHYS HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT]);
2079 //Log(("PGMDynMapGCPage: GCPhys=%RGp HCPhys=%RHp\n", GCPhys, HCPhys));
2080#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2081 pgmR0DynMapHCPageInlined(&pVM->pgm.s, HCPhys, ppv);
2082#else
2083 PGMDynMapHCPage(pVM, HCPhys, ppv);
2084#endif
2085 return VINF_SUCCESS;
2086}
2087
2088
2089/**
2090 * Temporarily maps one guest page specified by unaligned GC physical address.
2091 * These pages must have a physical mapping in HC, i.e. they cannot be MMIO pages.
2092 *
2093 * Be WARNED that the dynamic page mapping area is small, 8 pages, thus the space is
2094 * reused after 8 mappings (or perhaps a few more if you score with the cache).
2095 *
2096 * The caller is aware that only the speicifed page is mapped and that really bad things
2097 * will happen if writing beyond the page!
2098 *
2099 * @returns VBox status.
2100 * @param pVM VM handle.
2101 * @param GCPhys GC Physical address within the page to be mapped.
2102 * @param ppv Where to store the address of the mapping address corresponding to GCPhys.
2103 */
2104VMMDECL(int) PGMDynMapGCPageOff(PVM pVM, RTGCPHYS GCPhys, void **ppv)
2105{
2106 /*
2107 * Get the ram range.
2108 */
2109 PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
2110 while (pRam && GCPhys - pRam->GCPhys >= pRam->cb)
2111 pRam = pRam->CTX_SUFF(pNext);
2112 if (!pRam)
2113 {
2114 AssertMsgFailed(("Invalid physical address %RGp!\n", GCPhys));
2115 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2116 }
2117
2118 /*
2119 * Pass it on to PGMDynMapHCPage.
2120 */
2121 RTHCPHYS HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT]);
2122#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2123 pgmR0DynMapHCPageInlined(&pVM->pgm.s, HCPhys, ppv);
2124#else
2125 PGMDynMapHCPage(pVM, HCPhys, ppv);
2126#endif
2127 *ppv = (void *)((uintptr_t)*ppv | (GCPhys & PAGE_OFFSET_MASK));
2128 return VINF_SUCCESS;
2129}
2130
2131
2132# ifdef IN_RC
2133/**
2134 * Temporarily maps one host page specified by HC physical address.
2135 *
2136 * Be WARNED that the dynamic page mapping area is small, 16 pages, thus the space is
2137 * reused after 16 mappings (or perhaps a few more if you score with the cache).
2138 *
2139 * @returns VINF_SUCCESS, will bail out to ring-3 on failure.
2140 * @param pVM VM handle.
2141 * @param HCPhys HC Physical address of the page.
2142 * @param ppv Where to store the address of the mapping. This is the
2143 * address of the PAGE not the exact address corresponding
2144 * to HCPhys. Use PGMDynMapHCPageOff if you care for the
2145 * page offset.
2146 */
2147VMMDECL(int) PGMDynMapHCPage(PVM pVM, RTHCPHYS HCPhys, void **ppv)
2148{
2149 AssertMsg(!(HCPhys & PAGE_OFFSET_MASK), ("HCPhys=%RHp\n", HCPhys));
2150
2151 /*
2152 * Check the cache.
2153 */
2154 register unsigned iCache;
2155 for (iCache = 0;iCache < RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache);iCache++)
2156 {
2157 static const uint8_t au8Trans[MM_HYPER_DYNAMIC_SIZE >> PAGE_SHIFT][RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache)] =
2158 {
2159 { 0, 9, 10, 11, 12, 13, 14, 15},
2160 { 0, 1, 10, 11, 12, 13, 14, 15},
2161 { 0, 1, 2, 11, 12, 13, 14, 15},
2162 { 0, 1, 2, 3, 12, 13, 14, 15},
2163 { 0, 1, 2, 3, 4, 13, 14, 15},
2164 { 0, 1, 2, 3, 4, 5, 14, 15},
2165 { 0, 1, 2, 3, 4, 5, 6, 15},
2166 { 0, 1, 2, 3, 4, 5, 6, 7},
2167 { 8, 1, 2, 3, 4, 5, 6, 7},
2168 { 8, 9, 2, 3, 4, 5, 6, 7},
2169 { 8, 9, 10, 3, 4, 5, 6, 7},
2170 { 8, 9, 10, 11, 4, 5, 6, 7},
2171 { 8, 9, 10, 11, 12, 5, 6, 7},
2172 { 8, 9, 10, 11, 12, 13, 6, 7},
2173 { 8, 9, 10, 11, 12, 13, 14, 7},
2174 { 8, 9, 10, 11, 12, 13, 14, 15},
2175 };
2176 AssertCompile(RT_ELEMENTS(au8Trans) == 16);
2177 AssertCompile(RT_ELEMENTS(au8Trans[0]) == 8);
2178
2179 if (pVM->pgm.s.aHCPhysDynPageMapCache[iCache] == HCPhys)
2180 {
2181 int iPage = au8Trans[pVM->pgm.s.iDynPageMapLast][iCache];
2182 void *pv = pVM->pgm.s.pbDynPageMapBaseGC + (iPage << PAGE_SHIFT);
2183 *ppv = pv;
2184 STAM_COUNTER_INC(&pVM->pgm.s.StatRCDynMapCacheHits);
2185 Log4(("PGMGCDynMapHCPage: HCPhys=%RHp pv=%p iPage=%d iCache=%d\n", HCPhys, pv, iPage, iCache));
2186 return VINF_SUCCESS;
2187 }
2188 }
2189 AssertCompile(RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache) == 8);
2190 AssertCompile((MM_HYPER_DYNAMIC_SIZE >> PAGE_SHIFT) == 16);
2191 STAM_COUNTER_INC(&pVM->pgm.s.StatRCDynMapCacheMisses);
2192
2193 /*
2194 * Update the page tables.
2195 */
2196 register unsigned iPage = pVM->pgm.s.iDynPageMapLast;
2197# ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
2198 unsigned i;
2199 for (i=0;i<(MM_HYPER_DYNAMIC_SIZE >> PAGE_SHIFT);i++)
2200 {
2201 pVM->pgm.s.iDynPageMapLast = iPage = (iPage + 1) & ((MM_HYPER_DYNAMIC_SIZE >> PAGE_SHIFT) - 1);
2202 if (!(pVM->pgm.s.paDynPageMap32BitPTEsGC[iPage].u & PGM_PTFLAGS_DYN_LOCKED))
2203 break;
2204 iPage++;
2205 }
2206 AssertRelease(i != (MM_HYPER_DYNAMIC_SIZE >> PAGE_SHIFT));
2207# else
2208 pVM->pgm.s.iDynPageMapLast = iPage = (iPage + 1) & ((MM_HYPER_DYNAMIC_SIZE >> PAGE_SHIFT) - 1);
2209# endif
2210
2211 pVM->pgm.s.aHCPhysDynPageMapCache[iPage & (RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache) - 1)] = HCPhys;
2212 pVM->pgm.s.paDynPageMap32BitPTEsGC[iPage].u = (uint32_t)HCPhys | X86_PTE_P | X86_PTE_A | X86_PTE_D;
2213 pVM->pgm.s.paDynPageMapPaePTEsGC[iPage].u = HCPhys | X86_PTE_P | X86_PTE_A | X86_PTE_D;
2214
2215 void *pv = pVM->pgm.s.pbDynPageMapBaseGC + (iPage << PAGE_SHIFT);
2216 *ppv = pv;
2217 ASMInvalidatePage(pv);
2218 Log4(("PGMGCDynMapHCPage: HCPhys=%RHp pv=%p iPage=%d\n", HCPhys, pv, iPage));
2219 return VINF_SUCCESS;
2220}
2221
2222/**
2223 * Temporarily lock a dynamic page to prevent it from being reused.
2224 *
2225 * @returns VINF_SUCCESS, will bail out to ring-3 on failure.
2226 * @param pVM VM handle.
2227 * @param GCPage GC address of page
2228 */
2229VMMDECL(int) PGMDynLockHCPage(PVM pVM, RCPTRTYPE(uint8_t *) GCPage)
2230{
2231 unsigned iPage;
2232
2233 Assert(GCPage >= pVM->pgm.s.pbDynPageMapBaseGC && GCPage < (pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE));
2234 iPage = ((uintptr_t)(GCPage - pVM->pgm.s.pbDynPageMapBaseGC)) >> PAGE_SHIFT;
2235 Assert(!(pVM->pgm.s.paDynPageMap32BitPTEsGC[iPage].u & PGM_PTFLAGS_DYN_LOCKED));
2236 pVM->pgm.s.paDynPageMap32BitPTEsGC[iPage].u |= PGM_PTFLAGS_DYN_LOCKED;
2237 return VINF_SUCCESS;
2238}
2239
2240/**
2241 * Unlock a dynamic page
2242 *
2243 * @returns VINF_SUCCESS, will bail out to ring-3 on failure.
2244 * @param pVM VM handle.
2245 * @param GCPage GC address of page
2246 */
2247VMMDECL(int) PGMDynUnlockHCPage(PVM pVM, RCPTRTYPE(uint8_t *) GCPage)
2248{
2249 unsigned iPage;
2250
2251 Assert(GCPage >= pVM->pgm.s.pbDynPageMapBaseGC && GCPage < (pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE));
2252 iPage = ((uintptr_t)(GCPage - pVM->pgm.s.pbDynPageMapBaseGC)) >> PAGE_SHIFT;
2253 Assert(pVM->pgm.s.paDynPageMap32BitPTEsGC[iPage].u & PGM_PTFLAGS_DYN_LOCKED);
2254 pVM->pgm.s.paDynPageMap32BitPTEsGC[iPage].u &= ~PGM_PTFLAGS_DYN_LOCKED;
2255 return VINF_SUCCESS;
2256}
2257
2258# ifdef VBOX_STRICT
2259/**
2260 * Check for lock leaks.
2261 *
2262 * @param pVM VM handle.
2263 */
2264VMMDECL(void) PGMDynCheckLocks(PVM pVM)
2265{
2266 for (unsigned i=0;i<(MM_HYPER_DYNAMIC_SIZE >> PAGE_SHIFT);i++)
2267 Assert(!(pVM->pgm.s.paDynPageMap32BitPTEsGC[i].u & PGM_PTFLAGS_DYN_LOCKED));
2268}
2269# endif
2270# endif /* IN_RC */
2271
2272#endif /* IN_RC || VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
2273#ifdef VBOX_STRICT
2274
2275/**
2276 * Asserts that there are no mapping conflicts.
2277 *
2278 * @returns Number of conflicts.
2279 * @param pVM The VM Handle.
2280 */
2281VMMDECL(unsigned) PGMAssertNoMappingConflicts(PVM pVM)
2282{
2283 unsigned cErrors = 0;
2284
2285 /*
2286 * Check for mapping conflicts.
2287 */
2288 for (PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
2289 pMapping;
2290 pMapping = pMapping->CTX_SUFF(pNext))
2291 {
2292 /** @todo This is slow and should be optimized, but since it's just assertions I don't care now. */
2293 for (RTGCPTR GCPtr = pMapping->GCPtr;
2294 GCPtr <= pMapping->GCPtrLast;
2295 GCPtr += PAGE_SIZE)
2296 {
2297 int rc = PGMGstGetPage(pVM, (RTGCPTR)GCPtr, NULL, NULL);
2298 if (rc != VERR_PAGE_TABLE_NOT_PRESENT)
2299 {
2300 AssertMsgFailed(("Conflict at %RGv with %s\n", GCPtr, R3STRING(pMapping->pszDesc)));
2301 cErrors++;
2302 break;
2303 }
2304 }
2305 }
2306
2307 return cErrors;
2308}
2309
2310
2311/**
2312 * Asserts that everything related to the guest CR3 is correctly shadowed.
2313 *
2314 * This will call PGMAssertNoMappingConflicts() and PGMAssertHandlerAndFlagsInSync(),
2315 * and assert the correctness of the guest CR3 mapping before asserting that the
2316 * shadow page tables is in sync with the guest page tables.
2317 *
2318 * @returns Number of conflicts.
2319 * @param pVM The VM Handle.
2320 * @param cr3 The current guest CR3 register value.
2321 * @param cr4 The current guest CR4 register value.
2322 */
2323VMMDECL(unsigned) PGMAssertCR3(PVM pVM, uint64_t cr3, uint64_t cr4)
2324{
2325 STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3), a);
2326 unsigned cErrors = PGM_BTH_PFN(AssertCR3, pVM)(pVM, cr3, cr4, 0, ~(RTGCPTR)0);
2327 STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3), a);
2328 return cErrors;
2329}
2330
2331#endif /* VBOX_STRICT */
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