VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAll.cpp@ 17178

Last change on this file since 17178 was 17178, checked in by vboxsync, 16 years ago

VBOX_WITH_PGMPOOL_PAGING_ONLY: Properly flush the TLB for PAE PDPT entries.
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1/* $Id: PGMAll.cpp 17178 2009-02-26 17:23:42Z vboxsync $ */
2/** @file
3 * PGM - Page Manager and Monitor - All context code.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22/*******************************************************************************
23* Header Files *
24*******************************************************************************/
25#define LOG_GROUP LOG_GROUP_PGM
26#include <VBox/pgm.h>
27#include <VBox/cpum.h>
28#include <VBox/selm.h>
29#include <VBox/iom.h>
30#include <VBox/sup.h>
31#include <VBox/mm.h>
32#include <VBox/stam.h>
33#include <VBox/csam.h>
34#include <VBox/patm.h>
35#include <VBox/trpm.h>
36#include <VBox/rem.h>
37#include <VBox/em.h>
38#include <VBox/hwaccm.h>
39#include <VBox/hwacc_vmx.h>
40#include "PGMInternal.h"
41#include <VBox/vm.h>
42#include <iprt/assert.h>
43#include <iprt/asm.h>
44#include <iprt/string.h>
45#include <VBox/log.h>
46#include <VBox/param.h>
47#include <VBox/err.h>
48
49
50/*******************************************************************************
51* Structures and Typedefs *
52*******************************************************************************/
53/**
54 * Stated structure for PGM_GST_NAME(HandlerVirtualUpdate) that's
55 * passed to PGM_GST_NAME(VirtHandlerUpdateOne) during enumeration.
56 */
57typedef struct PGMHVUSTATE
58{
59 /** The VM handle. */
60 PVM pVM;
61 /** The todo flags. */
62 RTUINT fTodo;
63 /** The CR4 register value. */
64 uint32_t cr4;
65} PGMHVUSTATE, *PPGMHVUSTATE;
66
67
68/*******************************************************************************
69* Internal Functions *
70*******************************************************************************/
71DECLINLINE(int) pgmShwGetLongModePDPtr(PVM pVM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPT *ppPdpt, PX86PDPAE *ppPD);
72DECLINLINE(int) pgmShwGetPAEPDPtr(PVM pVM, RTGCPTR GCPtr, PX86PDPT *ppPdpt, PX86PDPAE *ppPD);
73#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
74DECLINLINE(int) pgmShwGetPaePoolPagePD(PPGM pPGM, RTGCPTR GCPtr, PPGMPOOLPAGE *ppShwPde);
75#endif
76
77/*
78 * Shadow - 32-bit mode
79 */
80#define PGM_SHW_TYPE PGM_TYPE_32BIT
81#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
82#include "PGMAllShw.h"
83
84/* Guest - real mode */
85#define PGM_GST_TYPE PGM_TYPE_REAL
86#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
87#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
88#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
89#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
90#include "PGMAllGst.h"
91#include "PGMAllBth.h"
92#undef BTH_PGMPOOLKIND_PT_FOR_PT
93#undef BTH_PGMPOOLKIND_ROOT
94#undef PGM_BTH_NAME
95#undef PGM_GST_TYPE
96#undef PGM_GST_NAME
97
98/* Guest - protected mode */
99#define PGM_GST_TYPE PGM_TYPE_PROT
100#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
101#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
102#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
103#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
104#include "PGMAllGst.h"
105#include "PGMAllBth.h"
106#undef BTH_PGMPOOLKIND_PT_FOR_PT
107#undef BTH_PGMPOOLKIND_ROOT
108#undef PGM_BTH_NAME
109#undef PGM_GST_TYPE
110#undef PGM_GST_NAME
111
112/* Guest - 32-bit mode */
113#define PGM_GST_TYPE PGM_TYPE_32BIT
114#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
115#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
116#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
117#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
118#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD
119#include "PGMAllGst.h"
120#include "PGMAllBth.h"
121#undef BTH_PGMPOOLKIND_PT_FOR_BIG
122#undef BTH_PGMPOOLKIND_PT_FOR_PT
123#undef BTH_PGMPOOLKIND_ROOT
124#undef PGM_BTH_NAME
125#undef PGM_GST_TYPE
126#undef PGM_GST_NAME
127
128#undef PGM_SHW_TYPE
129#undef PGM_SHW_NAME
130
131
132/*
133 * Shadow - PAE mode
134 */
135#define PGM_SHW_TYPE PGM_TYPE_PAE
136#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
137#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
138#include "PGMAllShw.h"
139
140/* Guest - real mode */
141#define PGM_GST_TYPE PGM_TYPE_REAL
142#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
143#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
144#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
145#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
146#include "PGMAllBth.h"
147#undef BTH_PGMPOOLKIND_PT_FOR_PT
148#undef BTH_PGMPOOLKIND_ROOT
149#undef PGM_BTH_NAME
150#undef PGM_GST_TYPE
151#undef PGM_GST_NAME
152
153/* Guest - protected mode */
154#define PGM_GST_TYPE PGM_TYPE_PROT
155#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
156#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
157#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
158#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
159#include "PGMAllBth.h"
160#undef BTH_PGMPOOLKIND_PT_FOR_PT
161#undef BTH_PGMPOOLKIND_ROOT
162#undef PGM_BTH_NAME
163#undef PGM_GST_TYPE
164#undef PGM_GST_NAME
165
166/* Guest - 32-bit mode */
167#define PGM_GST_TYPE PGM_TYPE_32BIT
168#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
169#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
170#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
171#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
172#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_FOR_32BIT
173#include "PGMAllBth.h"
174#undef BTH_PGMPOOLKIND_PT_FOR_BIG
175#undef BTH_PGMPOOLKIND_PT_FOR_PT
176#undef BTH_PGMPOOLKIND_ROOT
177#undef PGM_BTH_NAME
178#undef PGM_GST_TYPE
179#undef PGM_GST_NAME
180
181
182/* Guest - PAE mode */
183#define PGM_GST_TYPE PGM_TYPE_PAE
184#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
185#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
186#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
187#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
188#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT
189#include "PGMAllGst.h"
190#include "PGMAllBth.h"
191#undef BTH_PGMPOOLKIND_PT_FOR_BIG
192#undef BTH_PGMPOOLKIND_PT_FOR_PT
193#undef BTH_PGMPOOLKIND_ROOT
194#undef PGM_BTH_NAME
195#undef PGM_GST_TYPE
196#undef PGM_GST_NAME
197
198#undef PGM_SHW_TYPE
199#undef PGM_SHW_NAME
200
201
202#ifndef IN_RC /* AMD64 implies VT-x/AMD-V */
203/*
204 * Shadow - AMD64 mode
205 */
206# define PGM_SHW_TYPE PGM_TYPE_AMD64
207# define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
208# include "PGMAllShw.h"
209
210/* Guest - protected mode (only used for AMD-V nested paging in 64 bits mode) */
211# define PGM_GST_TYPE PGM_TYPE_PROT
212# define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
213# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_PROT(name)
214# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
215# define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PD_PHYS
216# include "PGMAllBth.h"
217# undef BTH_PGMPOOLKIND_PT_FOR_PT
218# undef BTH_PGMPOOLKIND_ROOT
219# undef PGM_BTH_NAME
220# undef PGM_GST_TYPE
221# undef PGM_GST_NAME
222
223# ifdef VBOX_WITH_64_BITS_GUESTS
224/* Guest - AMD64 mode */
225# define PGM_GST_TYPE PGM_TYPE_AMD64
226# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
227# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
228# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
229# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
230# define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_64BIT_PML4
231# include "PGMAllGst.h"
232# include "PGMAllBth.h"
233# undef BTH_PGMPOOLKIND_PT_FOR_BIG
234# undef BTH_PGMPOOLKIND_PT_FOR_PT
235# undef BTH_PGMPOOLKIND_ROOT
236# undef PGM_BTH_NAME
237# undef PGM_GST_TYPE
238# undef PGM_GST_NAME
239# endif /* VBOX_WITH_64_BITS_GUESTS */
240
241# undef PGM_SHW_TYPE
242# undef PGM_SHW_NAME
243
244
245/*
246 * Shadow - Nested paging mode
247 */
248# define PGM_SHW_TYPE PGM_TYPE_NESTED
249# define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED(name)
250# include "PGMAllShw.h"
251
252/* Guest - real mode */
253# define PGM_GST_TYPE PGM_TYPE_REAL
254# define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
255# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_REAL(name)
256# include "PGMAllBth.h"
257# undef PGM_BTH_NAME
258# undef PGM_GST_TYPE
259# undef PGM_GST_NAME
260
261/* Guest - protected mode */
262# define PGM_GST_TYPE PGM_TYPE_PROT
263# define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
264# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PROT(name)
265# include "PGMAllBth.h"
266# undef PGM_BTH_NAME
267# undef PGM_GST_TYPE
268# undef PGM_GST_NAME
269
270/* Guest - 32-bit mode */
271# define PGM_GST_TYPE PGM_TYPE_32BIT
272# define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
273# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT(name)
274# include "PGMAllBth.h"
275# undef PGM_BTH_NAME
276# undef PGM_GST_TYPE
277# undef PGM_GST_NAME
278
279/* Guest - PAE mode */
280# define PGM_GST_TYPE PGM_TYPE_PAE
281# define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
282# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE(name)
283# include "PGMAllBth.h"
284# undef PGM_BTH_NAME
285# undef PGM_GST_TYPE
286# undef PGM_GST_NAME
287
288# ifdef VBOX_WITH_64_BITS_GUESTS
289/* Guest - AMD64 mode */
290# define PGM_GST_TYPE PGM_TYPE_AMD64
291# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
292# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64(name)
293# include "PGMAllBth.h"
294# undef PGM_BTH_NAME
295# undef PGM_GST_TYPE
296# undef PGM_GST_NAME
297# endif /* VBOX_WITH_64_BITS_GUESTS */
298
299# undef PGM_SHW_TYPE
300# undef PGM_SHW_NAME
301
302
303/*
304 * Shadow - EPT
305 */
306# define PGM_SHW_TYPE PGM_TYPE_EPT
307# define PGM_SHW_NAME(name) PGM_SHW_NAME_EPT(name)
308# include "PGMAllShw.h"
309
310/* Guest - real mode */
311# define PGM_GST_TYPE PGM_TYPE_REAL
312# define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
313# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_REAL(name)
314# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
315# include "PGMAllBth.h"
316# undef BTH_PGMPOOLKIND_PT_FOR_PT
317# undef PGM_BTH_NAME
318# undef PGM_GST_TYPE
319# undef PGM_GST_NAME
320
321/* Guest - protected mode */
322# define PGM_GST_TYPE PGM_TYPE_PROT
323# define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
324# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PROT(name)
325# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
326# include "PGMAllBth.h"
327# undef BTH_PGMPOOLKIND_PT_FOR_PT
328# undef PGM_BTH_NAME
329# undef PGM_GST_TYPE
330# undef PGM_GST_NAME
331
332/* Guest - 32-bit mode */
333# define PGM_GST_TYPE PGM_TYPE_32BIT
334# define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
335# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_32BIT(name)
336# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
337# include "PGMAllBth.h"
338# undef BTH_PGMPOOLKIND_PT_FOR_PT
339# undef PGM_BTH_NAME
340# undef PGM_GST_TYPE
341# undef PGM_GST_NAME
342
343/* Guest - PAE mode */
344# define PGM_GST_TYPE PGM_TYPE_PAE
345# define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
346# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PAE(name)
347# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
348# include "PGMAllBth.h"
349# undef BTH_PGMPOOLKIND_PT_FOR_PT
350# undef PGM_BTH_NAME
351# undef PGM_GST_TYPE
352# undef PGM_GST_NAME
353
354# ifdef VBOX_WITH_64_BITS_GUESTS
355/* Guest - AMD64 mode */
356# define PGM_GST_TYPE PGM_TYPE_AMD64
357# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
358# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_AMD64(name)
359# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
360# include "PGMAllBth.h"
361# undef BTH_PGMPOOLKIND_PT_FOR_PT
362# undef PGM_BTH_NAME
363# undef PGM_GST_TYPE
364# undef PGM_GST_NAME
365# endif /* VBOX_WITH_64_BITS_GUESTS */
366
367# undef PGM_SHW_TYPE
368# undef PGM_SHW_NAME
369
370#endif /* !IN_RC */
371
372
373#ifndef IN_RING3
374/**
375 * #PF Handler.
376 *
377 * @returns VBox status code (appropriate for trap handling and GC return).
378 * @param pVM VM Handle.
379 * @param uErr The trap error code.
380 * @param pRegFrame Trap register frame.
381 * @param pvFault The fault address.
382 */
383VMMDECL(int) PGMTrap0eHandler(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
384{
385 LogFlow(("PGMTrap0eHandler: uErr=%RGu pvFault=%RGv eip=%RGv\n", uErr, pvFault, (RTGCPTR)pRegFrame->rip));
386 STAM_PROFILE_START(&pVM->pgm.s.StatRZTrap0e, a);
387 STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = NULL; } );
388
389
390#ifdef VBOX_WITH_STATISTICS
391 /*
392 * Error code stats.
393 */
394 if (uErr & X86_TRAP_PF_US)
395 {
396 if (!(uErr & X86_TRAP_PF_P))
397 {
398 if (uErr & X86_TRAP_PF_RW)
399 STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eUSNotPresentWrite);
400 else
401 STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eUSNotPresentRead);
402 }
403 else if (uErr & X86_TRAP_PF_RW)
404 STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eUSWrite);
405 else if (uErr & X86_TRAP_PF_RSVD)
406 STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eUSReserved);
407 else if (uErr & X86_TRAP_PF_ID)
408 STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eUSNXE);
409 else
410 STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eUSRead);
411 }
412 else
413 { /* Supervisor */
414 if (!(uErr & X86_TRAP_PF_P))
415 {
416 if (uErr & X86_TRAP_PF_RW)
417 STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eSVNotPresentWrite);
418 else
419 STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eSVNotPresentRead);
420 }
421 else if (uErr & X86_TRAP_PF_RW)
422 STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eSVWrite);
423 else if (uErr & X86_TRAP_PF_ID)
424 STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eSNXE);
425 else if (uErr & X86_TRAP_PF_RSVD)
426 STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eSVReserved);
427 }
428#endif /* VBOX_WITH_STATISTICS */
429
430 /*
431 * Call the worker.
432 */
433 int rc = PGM_BTH_PFN(Trap0eHandler, pVM)(pVM, uErr, pRegFrame, pvFault);
434 if (rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
435 rc = VINF_SUCCESS;
436 STAM_STATS({ if (rc == VINF_EM_RAW_GUEST_TRAP) STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eGuestPF); });
437 STAM_STATS({ if (!pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution))
438 pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2Misc; });
439 STAM_PROFILE_STOP_EX(&pVM->pgm.s.StatRZTrap0e, pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution), a);
440 return rc;
441}
442#endif /* !IN_RING3 */
443
444
445/**
446 * Prefetch a page
447 *
448 * Typically used to sync commonly used pages before entering raw mode
449 * after a CR3 reload.
450 *
451 * @returns VBox status code suitable for scheduling.
452 * @retval VINF_SUCCESS on success.
453 * @retval VINF_PGM_SYNC_CR3 if we're out of shadow pages or something like that.
454 * @param pVM VM handle.
455 * @param GCPtrPage Page to invalidate.
456 */
457VMMDECL(int) PGMPrefetchPage(PVM pVM, RTGCPTR GCPtrPage)
458{
459 STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,Prefetch), a);
460 int rc = PGM_BTH_PFN(PrefetchPage, pVM)(pVM, GCPtrPage);
461 STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,Prefetch), a);
462 AssertMsg(rc == VINF_SUCCESS || rc == VINF_PGM_SYNC_CR3 || RT_FAILURE(rc), ("rc=%Rrc\n", rc));
463 return rc;
464}
465
466
467/**
468 * Gets the mapping corresponding to the specified address (if any).
469 *
470 * @returns Pointer to the mapping.
471 * @returns NULL if not
472 *
473 * @param pVM The virtual machine.
474 * @param GCPtr The guest context pointer.
475 */
476PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr)
477{
478 PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
479 while (pMapping)
480 {
481 if ((uintptr_t)GCPtr < (uintptr_t)pMapping->GCPtr)
482 break;
483 if ((uintptr_t)GCPtr - (uintptr_t)pMapping->GCPtr < pMapping->cb)
484 return pMapping;
485 pMapping = pMapping->CTX_SUFF(pNext);
486 }
487 return NULL;
488}
489
490
491/**
492 * Verifies a range of pages for read or write access
493 *
494 * Only checks the guest's page tables
495 *
496 * @returns VBox status code.
497 * @param pVM VM handle.
498 * @param Addr Guest virtual address to check
499 * @param cbSize Access size
500 * @param fAccess Access type (r/w, user/supervisor (X86_PTE_*))
501 * @remarks Current not in use.
502 */
503VMMDECL(int) PGMIsValidAccess(PVM pVM, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess)
504{
505 /*
506 * Validate input.
507 */
508 if (fAccess & ~(X86_PTE_US | X86_PTE_RW))
509 {
510 AssertMsgFailed(("PGMIsValidAccess: invalid access type %08x\n", fAccess));
511 return VERR_INVALID_PARAMETER;
512 }
513
514 uint64_t fPage;
515 int rc = PGMGstGetPage(pVM, (RTGCPTR)Addr, &fPage, NULL);
516 if (RT_FAILURE(rc))
517 {
518 Log(("PGMIsValidAccess: access violation for %RGv rc=%d\n", Addr, rc));
519 return VINF_EM_RAW_GUEST_TRAP;
520 }
521
522 /*
523 * Check if the access would cause a page fault
524 *
525 * Note that hypervisor page directories are not present in the guest's tables, so this check
526 * is sufficient.
527 */
528 bool fWrite = !!(fAccess & X86_PTE_RW);
529 bool fUser = !!(fAccess & X86_PTE_US);
530 if ( !(fPage & X86_PTE_P)
531 || (fWrite && !(fPage & X86_PTE_RW))
532 || (fUser && !(fPage & X86_PTE_US)) )
533 {
534 Log(("PGMIsValidAccess: access violation for %RGv attr %#llx vs %d:%d\n", Addr, fPage, fWrite, fUser));
535 return VINF_EM_RAW_GUEST_TRAP;
536 }
537 if ( RT_SUCCESS(rc)
538 && PAGE_ADDRESS(Addr) != PAGE_ADDRESS(Addr + cbSize))
539 return PGMIsValidAccess(pVM, Addr + PAGE_SIZE, (cbSize > PAGE_SIZE) ? cbSize - PAGE_SIZE : 1, fAccess);
540 return rc;
541}
542
543
544/**
545 * Verifies a range of pages for read or write access
546 *
547 * Supports handling of pages marked for dirty bit tracking and CSAM
548 *
549 * @returns VBox status code.
550 * @param pVM VM handle.
551 * @param Addr Guest virtual address to check
552 * @param cbSize Access size
553 * @param fAccess Access type (r/w, user/supervisor (X86_PTE_*))
554 */
555VMMDECL(int) PGMVerifyAccess(PVM pVM, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess)
556{
557 AssertMsg(!(fAccess & ~(X86_PTE_US | X86_PTE_RW)), ("PGMVerifyAccess: invalid access type %08x\n", fAccess));
558
559 /*
560 * Get going.
561 */
562 uint64_t fPageGst;
563 int rc = PGMGstGetPage(pVM, (RTGCPTR)Addr, &fPageGst, NULL);
564 if (RT_FAILURE(rc))
565 {
566 Log(("PGMVerifyAccess: access violation for %RGv rc=%d\n", Addr, rc));
567 return VINF_EM_RAW_GUEST_TRAP;
568 }
569
570 /*
571 * Check if the access would cause a page fault
572 *
573 * Note that hypervisor page directories are not present in the guest's tables, so this check
574 * is sufficient.
575 */
576 const bool fWrite = !!(fAccess & X86_PTE_RW);
577 const bool fUser = !!(fAccess & X86_PTE_US);
578 if ( !(fPageGst & X86_PTE_P)
579 || (fWrite && !(fPageGst & X86_PTE_RW))
580 || (fUser && !(fPageGst & X86_PTE_US)) )
581 {
582 Log(("PGMVerifyAccess: access violation for %RGv attr %#llx vs %d:%d\n", Addr, fPageGst, fWrite, fUser));
583 return VINF_EM_RAW_GUEST_TRAP;
584 }
585
586 if (!HWACCMIsNestedPagingActive(pVM))
587 {
588 /*
589 * Next step is to verify if we protected this page for dirty bit tracking or for CSAM scanning
590 */
591 rc = PGMShwGetPage(pVM, (RTGCPTR)Addr, NULL, NULL);
592 if ( rc == VERR_PAGE_NOT_PRESENT
593 || rc == VERR_PAGE_TABLE_NOT_PRESENT)
594 {
595 /*
596 * Page is not present in our page tables.
597 * Try to sync it!
598 */
599 Assert(X86_TRAP_PF_RW == X86_PTE_RW && X86_TRAP_PF_US == X86_PTE_US);
600 uint32_t uErr = fAccess & (X86_TRAP_PF_RW | X86_TRAP_PF_US);
601 rc = PGM_BTH_PFN(VerifyAccessSyncPage, pVM)(pVM, Addr, fPageGst, uErr);
602 if (rc != VINF_SUCCESS)
603 return rc;
604 }
605 else
606 AssertMsg(rc == VINF_SUCCESS, ("PGMShwGetPage %RGv failed with %Rrc\n", Addr, rc));
607 }
608
609#if 0 /* def VBOX_STRICT; triggers too often now */
610 /*
611 * This check is a bit paranoid, but useful.
612 */
613 /** @note this will assert when writing to monitored pages (a bit annoying actually) */
614 uint64_t fPageShw;
615 rc = PGMShwGetPage(pVM, (RTGCPTR)Addr, &fPageShw, NULL);
616 if ( (rc == VERR_PAGE_NOT_PRESENT || RT_FAILURE(rc))
617 || (fWrite && !(fPageShw & X86_PTE_RW))
618 || (fUser && !(fPageShw & X86_PTE_US)) )
619 {
620 AssertMsgFailed(("Unexpected access violation for %RGv! rc=%Rrc write=%d user=%d\n",
621 Addr, rc, fWrite && !(fPageShw & X86_PTE_RW), fUser && !(fPageShw & X86_PTE_US)));
622 return VINF_EM_RAW_GUEST_TRAP;
623 }
624#endif
625
626 if ( RT_SUCCESS(rc)
627 && ( PAGE_ADDRESS(Addr) != PAGE_ADDRESS(Addr + cbSize - 1)
628 || Addr + cbSize < Addr))
629 {
630 /* Don't recursively call PGMVerifyAccess as we might run out of stack. */
631 for (;;)
632 {
633 Addr += PAGE_SIZE;
634 if (cbSize > PAGE_SIZE)
635 cbSize -= PAGE_SIZE;
636 else
637 cbSize = 1;
638 rc = PGMVerifyAccess(pVM, Addr, 1, fAccess);
639 if (rc != VINF_SUCCESS)
640 break;
641 if (PAGE_ADDRESS(Addr) == PAGE_ADDRESS(Addr + cbSize - 1))
642 break;
643 }
644 }
645 return rc;
646}
647
648
649/**
650 * Emulation of the invlpg instruction (HC only actually).
651 *
652 * @returns VBox status code, special care required.
653 * @retval VINF_PGM_SYNC_CR3 - handled.
654 * @retval VINF_EM_RAW_EMULATE_INSTR - not handled (RC only).
655 * @retval VERR_REM_FLUSHED_PAGES_OVERFLOW - not handled.
656 *
657 * @param pVM VM handle.
658 * @param GCPtrPage Page to invalidate.
659 *
660 * @remark ASSUMES the page table entry or page directory is valid. Fairly
661 * safe, but there could be edge cases!
662 *
663 * @todo Flush page or page directory only if necessary!
664 */
665VMMDECL(int) PGMInvalidatePage(PVM pVM, RTGCPTR GCPtrPage)
666{
667 int rc;
668 Log3(("PGMInvalidatePage: GCPtrPage=%RGv\n", GCPtrPage));
669
670#ifndef IN_RING3
671 /*
672 * Notify the recompiler so it can record this instruction.
673 * Failure happens when it's out of space. We'll return to HC in that case.
674 */
675 rc = REMNotifyInvalidatePage(pVM, GCPtrPage);
676 if (rc != VINF_SUCCESS)
677 return rc;
678#endif /* !IN_RING3 */
679
680
681#ifdef IN_RC
682 /*
683 * Check for conflicts and pending CR3 monitoring updates.
684 */
685 if (!pVM->pgm.s.fMappingsFixed)
686 {
687 if ( pgmGetMapping(pVM, GCPtrPage)
688 && PGMGstGetPage(pVM, GCPtrPage, NULL, NULL) != VERR_PAGE_TABLE_NOT_PRESENT)
689 {
690 LogFlow(("PGMGCInvalidatePage: Conflict!\n"));
691 VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
692 STAM_COUNTER_INC(&pVM->pgm.s.StatRCInvlPgConflict);
693 return VINF_PGM_SYNC_CR3;
694 }
695
696 if (pVM->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
697 {
698 LogFlow(("PGMGCInvalidatePage: PGM_SYNC_MONITOR_CR3 -> reinterpret instruction in R3\n"));
699 STAM_COUNTER_INC(&pVM->pgm.s.StatRCInvlPgSyncMonCR3);
700 return VINF_EM_RAW_EMULATE_INSTR;
701 }
702 }
703#endif /* IN_RC */
704
705 /*
706 * Call paging mode specific worker.
707 */
708 STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePage), a);
709 rc = PGM_BTH_PFN(InvalidatePage, pVM)(pVM, GCPtrPage);
710 STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePage), a);
711
712#ifdef IN_RING3
713 /*
714 * Check if we have a pending update of the CR3 monitoring.
715 */
716 if ( RT_SUCCESS(rc)
717 && (pVM->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3))
718 {
719 pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
720 Assert(!pVM->pgm.s.fMappingsFixed);
721#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
722 Assert(pVM->pgm.s.GCPhysCR3 == pVM->pgm.s.GCPhysGstCR3Monitored);
723 rc = PGM_GST_PFN(MonitorCR3, pVM)(pVM, pVM->pgm.s.GCPhysCR3);
724#endif
725 }
726
727 /*
728 * Inform CSAM about the flush
729 *
730 * Note: This is to check if monitored pages have been changed; when we implement
731 * callbacks for virtual handlers, this is no longer required.
732 */
733 CSAMR3FlushPage(pVM, GCPtrPage);
734#endif /* IN_RING3 */
735 return rc;
736}
737
738
739/**
740 * Executes an instruction using the interpreter.
741 *
742 * @returns VBox status code (appropriate for trap handling and GC return).
743 * @param pVM VM handle.
744 * @param pRegFrame Register frame.
745 * @param pvFault Fault address.
746 */
747VMMDECL(int) PGMInterpretInstruction(PVM pVM, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
748{
749 uint32_t cb;
750 int rc = EMInterpretInstruction(pVM, pRegFrame, pvFault, &cb);
751 if (rc == VERR_EM_INTERPRETER)
752 rc = VINF_EM_RAW_EMULATE_INSTR;
753 if (rc != VINF_SUCCESS)
754 Log(("PGMInterpretInstruction: returns %Rrc (pvFault=%RGv)\n", rc, pvFault));
755 return rc;
756}
757
758
759/**
760 * Gets effective page information (from the VMM page directory).
761 *
762 * @returns VBox status.
763 * @param pVM VM Handle.
764 * @param GCPtr Guest Context virtual address of the page.
765 * @param pfFlags Where to store the flags. These are X86_PTE_*.
766 * @param pHCPhys Where to store the HC physical address of the page.
767 * This is page aligned.
768 * @remark You should use PGMMapGetPage() for pages in a mapping.
769 */
770VMMDECL(int) PGMShwGetPage(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys)
771{
772 return PGM_SHW_PFN(GetPage,pVM)(pVM, GCPtr, pfFlags, pHCPhys);
773}
774
775
776/**
777 * Sets (replaces) the page flags for a range of pages in the shadow context.
778 *
779 * @returns VBox status.
780 * @param pVM VM handle.
781 * @param GCPtr The address of the first page.
782 * @param cb The size of the range in bytes.
783 * @param fFlags Page flags X86_PTE_*, excluding the page mask of course.
784 * @remark You must use PGMMapSetPage() for pages in a mapping.
785 */
786VMMDECL(int) PGMShwSetPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags)
787{
788 return PGMShwModifyPage(pVM, GCPtr, cb, fFlags, 0);
789}
790
791
792/**
793 * Modify page flags for a range of pages in the shadow context.
794 *
795 * The existing flags are ANDed with the fMask and ORed with the fFlags.
796 *
797 * @returns VBox status code.
798 * @param pVM VM handle.
799 * @param GCPtr Virtual address of the first page in the range.
800 * @param cb Size (in bytes) of the range to apply the modification to.
801 * @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
802 * @param fMask The AND mask - page flags X86_PTE_*.
803 * Be very CAREFUL when ~'ing constants which could be 32-bit!
804 * @remark You must use PGMMapModifyPage() for pages in a mapping.
805 */
806VMMDECL(int) PGMShwModifyPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
807{
808 AssertMsg(!(fFlags & X86_PTE_PAE_PG_MASK), ("fFlags=%#llx\n", fFlags));
809 Assert(cb);
810
811 /*
812 * Align the input.
813 */
814 cb += GCPtr & PAGE_OFFSET_MASK;
815 cb = RT_ALIGN_Z(cb, PAGE_SIZE);
816 GCPtr = (GCPtr & PAGE_BASE_GC_MASK); /** @todo this ain't necessary, right... */
817
818 /*
819 * Call worker.
820 */
821 return PGM_SHW_PFN(ModifyPage, pVM)(pVM, GCPtr, cb, fFlags, fMask);
822}
823
824
825/**
826 * Gets the SHADOW page directory pointer for the specified address.
827 *
828 * @returns VBox status.
829 * @param pVM VM handle.
830 * @param GCPtr The address.
831 * @param ppPdpt Receives address of pdpt
832 * @param ppPD Receives address of page directory
833 * @remarks Unused.
834 */
835DECLINLINE(int) pgmShwGetPAEPDPtr(PVM pVM, RTGCPTR GCPtr, PX86PDPT *ppPdpt, PX86PDPAE *ppPD)
836{
837 PPGM pPGM = &pVM->pgm.s;
838 PPGMPOOL pPool = pPGM->CTX_SUFF(pPool);
839 PPGMPOOLPAGE pShwPage;
840
841 Assert(!HWACCMIsNestedPagingActive(pVM));
842
843 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
844 PX86PDPT pPdpt = pgmShwGetPaePDPTPtr(&pVM->pgm.s);
845 PX86PDPE pPdpe = &pPdpt->a[iPdPt];
846
847 *ppPdpt = pPdpt;
848 if (!pPdpe->n.u1Present)
849 return VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT;
850
851 pShwPage = pgmPoolGetPage(pPool, pPdpe->u & X86_PDPE_PG_MASK);
852 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
853
854 *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
855 return VINF_SUCCESS;
856}
857
858#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
859
860/**
861 * Gets the shadow page directory for the specified address, PAE.
862 *
863 * @returns Pointer to the shadow PD.
864 * @param pVM VM handle.
865 * @param GCPtr The address.
866 * @param pGstPdpe Guest PDPT entry
867 * @param ppPD Receives address of page directory
868 */
869int pgmShwSyncPaePDPtr(PVM pVM, RTGCPTR GCPtr, PX86PDPE pGstPdpe, PX86PDPAE *ppPD)
870{
871 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
872 PX86PDPT pPdpt = pgmShwGetPaePDPTPtr(&pVM->pgm.s);
873 PX86PDPE pPdpe = &pPdpt->a[iPdPt];
874 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
875 PPGMPOOLPAGE pShwPage;
876 int rc;
877
878 /* Allocate page directory if not present. */
879 if ( !pPdpe->n.u1Present
880 && !(pPdpe->u & X86_PDPE_PG_MASK))
881 {
882 bool fNestedPaging = HWACCMIsNestedPagingActive(pVM);
883 bool fPaging = !!(CPUMGetGuestCR0(pVM) & X86_CR0_PG);
884 RTGCPTR64 GCPdPt;
885 PGMPOOLKIND enmKind;
886
887# if defined(IN_RC) && defined(VBOX_WITH_PGMPOOL_PAGING_ONLY)
888 /* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
889 PGMDynLockHCPage(pVM, (uint8_t *)pPdpe);
890# endif
891
892 if (fNestedPaging || !fPaging)
893 {
894 /* AMD-V nested paging or real/protected mode without paging */
895 GCPdPt = (RTGCPTR64)iPdPt << X86_PDPT_SHIFT;
896 enmKind = PGMPOOLKIND_PAE_PD_PHYS;
897 }
898 else
899 {
900 Assert(pGstPdpe);
901
902 if (CPUMGetGuestCR4(pVM) & X86_CR4_PAE)
903 {
904 GCPdPt = pGstPdpe->u & X86_PDPE_PG_MASK;
905 enmKind = PGMPOOLKIND_PAE_PD_FOR_PAE_PD;
906 }
907 else
908 {
909 GCPdPt = CPUMGetGuestCR3(pVM);
910 enmKind = (PGMPOOLKIND)(PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD + iPdPt);
911 }
912 }
913
914 /* Create a reference back to the PDPT by using the index in its shadow page. */
915 rc = pgmPoolAlloc(pVM, GCPdPt, enmKind, pVM->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPdPt, &pShwPage);
916 if (rc == VERR_PGM_POOL_FLUSHED)
917 {
918 Log(("pgmShwSyncPaePDPtr: PGM pool flushed -> signal sync cr3\n"));
919 Assert(pVM->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL);
920 VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
921# if defined(IN_RC) && defined(VBOX_WITH_PGMPOOL_PAGING_ONLY)
922 PGMDynUnlockHCPage(pVM, (uint8_t *)pPdpe);
923# endif
924 return VINF_PGM_SYNC_CR3;
925 }
926 AssertRCReturn(rc, rc);
927
928 /* The PD was cached or created; hook it up now. */
929 pPdpe->u |= pShwPage->Core.Key
930 | (pGstPdpe->u & ~(X86_PDPE_PG_MASK | X86_PDPE_AVL_MASK | X86_PDPE_PCD | X86_PDPE_PWT));
931
932# if defined(IN_RC) && defined(VBOX_WITH_PGMPOOL_PAGING_ONLY)
933 /* In 32 bits PAE mode we *must* invalidate the TLB when changing a PDPT entry; the CPU fetches them only during cr3 load, so any
934 * non-present PDPT will continue to cause page faults.
935 */
936 ASMReloadCR3();
937 PGMDynUnlockHCPage(pVM, (uint8_t *)pPdpe);
938# endif
939 }
940 else
941 {
942 pShwPage = pgmPoolGetPage(pPool, pPdpe->u & X86_PDPE_PG_MASK);
943 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
944
945 Assert((pPdpe->u & X86_PDPE_PG_MASK) == pShwPage->Core.Key));
946 }
947 *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
948 return VINF_SUCCESS;
949}
950
951/**
952 * Gets the pointer to the shadow page directory entry for an address, PAE.
953 *
954 * @returns Pointer to the PDE.
955 * @param pPGM Pointer to the PGM instance data.
956 * @param GCPtr The address.
957 * @param ppShwPde Receives the address of the pgm pool page for the shadow page directory
958 */
959DECLINLINE(int) pgmShwGetPaePoolPagePD(PPGM pPGM, RTGCPTR GCPtr, PPGMPOOLPAGE *ppShwPde)
960{
961 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
962 PX86PDPT pPdpt = pgmShwGetPaePDPTPtr(pPGM);
963 AssertReturn(pPdpt, VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT); /* can't happen */
964 if (!pPdpt->a[iPdPt].n.u1Present)
965 {
966 LogFlow(("pgmShwGetPaePoolPagePD: PD %d not present (%RX64)\n", iPdPt, pPdpt->a[iPdPt].u));
967 return VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT;
968 }
969
970 /* Fetch the pgm pool shadow descriptor. */
971 PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(PGM2VM(pPGM), pPdpt->a[iPdPt].u & X86_PDPE_PG_MASK);
972 AssertReturn(pShwPde, VERR_INTERNAL_ERROR);
973
974 *ppShwPde = pShwPde;
975 return VINF_SUCCESS;
976}
977#endif
978
979#ifndef IN_RC
980
981/**
982 * Syncs the SHADOW page directory pointer for the specified address.
983 *
984 * Allocates backing pages in case the PDPT or PML4 entry is missing.
985 *
986 * The caller is responsible for making sure the guest has a valid PD before
987 * calling this function.
988 *
989 * @returns VBox status.
990 * @param pVM VM handle.
991 * @param GCPtr The address.
992 * @param pGstPml4e Guest PML4 entry
993 * @param pGstPdpe Guest PDPT entry
994 * @param ppPD Receives address of page directory
995 */
996int pgmShwSyncLongModePDPtr(PVM pVM, RTGCPTR64 GCPtr, PX86PML4E pGstPml4e, PX86PDPE pGstPdpe, PX86PDPAE *ppPD)
997{
998 PPGM pPGM = &pVM->pgm.s;
999 PPGMPOOL pPool = pPGM->CTX_SUFF(pPool);
1000 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
1001 PX86PML4E pPml4e = pgmShwGetLongModePML4EPtr(pPGM, iPml4);
1002 bool fNestedPaging = HWACCMIsNestedPagingActive(pVM);
1003#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
1004 bool fPaging = !!(CPUMGetGuestCR0(pVM) & X86_CR0_PG);
1005#endif
1006 PPGMPOOLPAGE pShwPage;
1007 int rc;
1008
1009 /* Allocate page directory pointer table if not present. */
1010 if ( !pPml4e->n.u1Present
1011 && !(pPml4e->u & X86_PML4E_PG_MASK))
1012 {
1013#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
1014 RTGCPTR64 GCPml4;
1015 PGMPOOLKIND enmKind;
1016
1017 Assert(pVM->pgm.s.CTX_SUFF(pShwPageCR3));
1018
1019 if (fNestedPaging || !fPaging)
1020 {
1021 /* AMD-V nested paging or real/protected mode without paging */
1022 GCPml4 = (RTGCPTR64)iPml4 << X86_PML4_SHIFT;
1023 enmKind = PGMPOOLKIND_64BIT_PDPT_FOR_PHYS;
1024 }
1025 else
1026 {
1027 Assert(pGstPml4e && pGstPdpe);
1028
1029 GCPml4 = pGstPml4e->u & X86_PML4E_PG_MASK;
1030 enmKind = PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT;
1031 }
1032
1033 /* Create a reference back to the PDPT by using the index in its shadow page. */
1034 rc = pgmPoolAlloc(pVM, GCPml4, enmKind, pVM->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPml4, &pShwPage);
1035#else
1036 if (!fNestedPaging)
1037 {
1038 Assert(pGstPml4e && pGstPdpe);
1039 Assert(pVM->pgm.s.CTX_SUFF(pShwPageCR3));
1040
1041 rc = pgmPoolAlloc(pVM, pGstPml4e->u & X86_PML4E_PG_MASK,
1042 PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT, pVM->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPml4, &pShwPage);
1043 }
1044 else
1045 {
1046 /* AMD-V nested paging. (Intel EPT never comes here) */
1047 RTGCPTR64 GCPml4 = (RTGCPTR64)iPml4 << EPT_PML4_SHIFT;
1048 rc = pgmPoolAlloc(pVM, GCPml4 + RT_BIT_64(63) /* hack: make the address unique */,
1049 PGMPOOLKIND_64BIT_PDPT_FOR_PHYS, PGMPOOL_IDX_NESTED_ROOT, iPml4, &pShwPage);
1050 }
1051#endif
1052 if (rc == VERR_PGM_POOL_FLUSHED)
1053 {
1054 Log(("PGMShwSyncLongModePDPtr: PGM pool flushed (1) -> signal sync cr3\n"));
1055 Assert(pVM->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL);
1056 VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
1057 return VINF_PGM_SYNC_CR3;
1058 }
1059 AssertRCReturn(rc, rc);
1060 }
1061 else
1062 {
1063 pShwPage = pgmPoolGetPage(pPool, pPml4e->u & X86_PML4E_PG_MASK);
1064 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1065 }
1066 /* The PDPT was cached or created; hook it up now. */
1067 pPml4e->u |= pShwPage->Core.Key
1068 | (pGstPml4e->u & ~(X86_PML4E_PG_MASK | X86_PML4E_AVL_MASK | X86_PML4E_PCD | X86_PML4E_PWT));
1069
1070 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1071 PX86PDPT pPdpt = (PX86PDPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1072 PX86PDPE pPdpe = &pPdpt->a[iPdPt];
1073
1074 /* Allocate page directory if not present. */
1075 if ( !pPdpe->n.u1Present
1076 && !(pPdpe->u & X86_PDPE_PG_MASK))
1077 {
1078#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
1079 RTGCPTR64 GCPdPt;
1080 PGMPOOLKIND enmKind;
1081
1082 if (fNestedPaging || !fPaging)
1083 {
1084 /* AMD-V nested paging or real/protected mode without paging */
1085 GCPdPt = (RTGCPTR64)iPdPt << X86_PDPT_SHIFT;
1086 enmKind = PGMPOOLKIND_64BIT_PD_FOR_PHYS;
1087 }
1088 else
1089 {
1090 Assert(pGstPdpe);
1091
1092 GCPdPt = pGstPdpe->u & X86_PDPE_PG_MASK;
1093 enmKind = PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD;
1094 }
1095
1096 /* Create a reference back to the PDPT by using the index in its shadow page. */
1097 rc = pgmPoolAlloc(pVM, GCPdPt, enmKind, pShwPage->idx, iPdPt, &pShwPage);
1098#else
1099 if (!fNestedPaging)
1100 {
1101 Assert(pGstPml4e && pGstPdpe);
1102 Assert(!(pPdpe->u & X86_PDPE_PG_MASK));
1103 /* Create a reference back to the PDPT by using the index in its shadow page. */
1104 rc = pgmPoolAlloc(pVM, pGstPdpe->u & X86_PDPE_PG_MASK, PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD, pShwPage->idx, iPdPt, &pShwPage);
1105 }
1106 else
1107 {
1108 /* AMD-V nested paging. (Intel EPT never comes here) */
1109 RTGCPTR64 GCPdPt = (RTGCPTR64)iPdPt << EPT_PDPT_SHIFT;
1110
1111 rc = pgmPoolAlloc(pVM, GCPdPt + RT_BIT_64(62) /* hack: make the address unique */, PGMPOOLKIND_64BIT_PD_FOR_PHYS, pShwPage->idx, iPdPt, &pShwPage);
1112 }
1113#endif
1114 if (rc == VERR_PGM_POOL_FLUSHED)
1115 {
1116 Log(("PGMShwSyncLongModePDPtr: PGM pool flushed (2) -> signal sync cr3\n"));
1117 Assert(pVM->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL);
1118 VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
1119 return VINF_PGM_SYNC_CR3;
1120 }
1121 AssertRCReturn(rc, rc);
1122 }
1123 else
1124 {
1125 pShwPage = pgmPoolGetPage(pPool, pPdpe->u & X86_PDPE_PG_MASK);
1126 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1127 }
1128 /* The PD was cached or created; hook it up now. */
1129 pPdpe->u |= pShwPage->Core.Key
1130 | (pGstPdpe->u & ~(X86_PDPE_PG_MASK | X86_PDPE_AVL_MASK | X86_PDPE_PCD | X86_PDPE_PWT));
1131
1132 *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1133 return VINF_SUCCESS;
1134}
1135
1136
1137/**
1138 * Gets the SHADOW page directory pointer for the specified address (long mode).
1139 *
1140 * @returns VBox status.
1141 * @param pVM VM handle.
1142 * @param GCPtr The address.
1143 * @param ppPdpt Receives address of pdpt
1144 * @param ppPD Receives address of page directory
1145 */
1146DECLINLINE(int) pgmShwGetLongModePDPtr(PVM pVM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPT *ppPdpt, PX86PDPAE *ppPD)
1147{
1148 PPGM pPGM = &pVM->pgm.s;
1149 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
1150 PCX86PML4E pPml4e = pgmShwGetLongModePML4EPtr(pPGM, iPml4);
1151 AssertReturn(pPml4e, VERR_INTERNAL_ERROR);
1152 if (ppPml4e)
1153 *ppPml4e = (PX86PML4E)pPml4e;
1154 if (!pPml4e->n.u1Present)
1155 return VERR_PAGE_MAP_LEVEL4_NOT_PRESENT;
1156
1157 PPGMPOOL pPool = pPGM->CTX_SUFF(pPool);
1158 PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPml4e->u & X86_PML4E_PG_MASK);
1159 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1160
1161 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1162 PCX86PDPT pPdpt = *ppPdpt = (PX86PDPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1163 if (!pPdpt->a[iPdPt].n.u1Present)
1164 return VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT;
1165
1166 pShwPage = pgmPoolGetPage(pPool, pPdpt->a[iPdPt].u & X86_PDPE_PG_MASK);
1167 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1168
1169 *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1170 return VINF_SUCCESS;
1171}
1172
1173
1174/**
1175 * Syncs the SHADOW EPT page directory pointer for the specified address. Allocates
1176 * backing pages in case the PDPT or PML4 entry is missing.
1177 *
1178 * @returns VBox status.
1179 * @param pVM VM handle.
1180 * @param GCPtr The address.
1181 * @param ppPdpt Receives address of pdpt
1182 * @param ppPD Receives address of page directory
1183 */
1184int pgmShwGetEPTPDPtr(PVM pVM, RTGCPTR64 GCPtr, PEPTPDPT *ppPdpt, PEPTPD *ppPD)
1185{
1186 PPGM pPGM = &pVM->pgm.s;
1187 const unsigned iPml4 = (GCPtr >> EPT_PML4_SHIFT) & EPT_PML4_MASK;
1188 PPGMPOOL pPool = pPGM->CTX_SUFF(pPool);
1189 PEPTPML4 pPml4;
1190 PEPTPML4E pPml4e;
1191 PPGMPOOLPAGE pShwPage;
1192 int rc;
1193
1194 Assert(HWACCMIsNestedPagingActive(pVM));
1195
1196# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
1197 rc = PGM_HCPHYS_2_PTR(pVM, pPGM->HCPhysShwNestedRoot, &pPml4);
1198 AssertRCReturn(rc, rc);
1199# else
1200 pPml4 = (PEPTPML4)pPGM->CTX_SUFF(pShwNestedRoot);
1201# endif
1202 Assert(pPml4);
1203
1204 /* Allocate page directory pointer table if not present. */
1205 pPml4e = &pPml4->a[iPml4];
1206 if ( !pPml4e->n.u1Present
1207 && !(pPml4e->u & EPT_PML4E_PG_MASK))
1208 {
1209 Assert(!(pPml4e->u & EPT_PML4E_PG_MASK));
1210 RTGCPTR64 GCPml4 = (RTGCPTR64)iPml4 << EPT_PML4_SHIFT;
1211
1212#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
1213 rc = pgmPoolAlloc(pVM, GCPml4, PGMPOOLKIND_EPT_PDPT_FOR_PHYS, PGMPOOL_IDX_NESTED_ROOT, iPml4, &pShwPage);
1214#else
1215 rc = pgmPoolAlloc(pVM, GCPml4 + RT_BIT_64(63) /* hack: make the address unique */, PGMPOOLKIND_EPT_PDPT_FOR_PHYS, PGMPOOL_IDX_NESTED_ROOT, iPml4, &pShwPage);
1216#endif
1217 if (rc == VERR_PGM_POOL_FLUSHED)
1218 {
1219 Log(("PGMShwSyncEPTPDPtr: PGM pool flushed (1) -> signal sync cr3\n"));
1220 Assert(pVM->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL);
1221 VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
1222 return VINF_PGM_SYNC_CR3;
1223 }
1224 AssertRCReturn(rc, rc);
1225 }
1226 else
1227 {
1228 pShwPage = pgmPoolGetPage(pPool, pPml4e->u & EPT_PML4E_PG_MASK);
1229 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1230 }
1231 /* The PDPT was cached or created; hook it up now and fill with the default value. */
1232 pPml4e->u = pShwPage->Core.Key;
1233 pPml4e->n.u1Present = 1;
1234 pPml4e->n.u1Write = 1;
1235 pPml4e->n.u1Execute = 1;
1236
1237 const unsigned iPdPt = (GCPtr >> EPT_PDPT_SHIFT) & EPT_PDPT_MASK;
1238 PEPTPDPT pPdpt = (PEPTPDPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1239 PEPTPDPTE pPdpe = &pPdpt->a[iPdPt];
1240
1241 if (ppPdpt)
1242 *ppPdpt = pPdpt;
1243
1244 /* Allocate page directory if not present. */
1245 if ( !pPdpe->n.u1Present
1246 && !(pPdpe->u & EPT_PDPTE_PG_MASK))
1247 {
1248 RTGCPTR64 GCPdPt = (RTGCPTR64)iPdPt << EPT_PDPT_SHIFT;
1249
1250#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
1251 rc = pgmPoolAlloc(pVM, GCPdPt, PGMPOOLKIND_64BIT_PD_FOR_PHYS, pShwPage->idx, iPdPt, &pShwPage);
1252#else
1253 rc = pgmPoolAlloc(pVM, GCPdPt + RT_BIT_64(62) /* hack: make the address unique */, PGMPOOLKIND_64BIT_PD_FOR_PHYS, pShwPage->idx, iPdPt, &pShwPage);
1254#endif
1255 if (rc == VERR_PGM_POOL_FLUSHED)
1256 {
1257 Log(("PGMShwSyncEPTPDPtr: PGM pool flushed (2) -> signal sync cr3\n"));
1258 Assert(pVM->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL);
1259 VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
1260 return VINF_PGM_SYNC_CR3;
1261 }
1262 AssertRCReturn(rc, rc);
1263 }
1264 else
1265 {
1266 pShwPage = pgmPoolGetPage(pPool, pPdpe->u & EPT_PDPTE_PG_MASK);
1267 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1268 }
1269 /* The PD was cached or created; hook it up now and fill with the default value. */
1270 pPdpe->u = pShwPage->Core.Key;
1271 pPdpe->n.u1Present = 1;
1272 pPdpe->n.u1Write = 1;
1273 pPdpe->n.u1Execute = 1;
1274
1275 *ppPD = (PEPTPD)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1276 return VINF_SUCCESS;
1277}
1278
1279#endif /* IN_RC */
1280
1281/**
1282 * Gets effective Guest OS page information.
1283 *
1284 * When GCPtr is in a big page, the function will return as if it was a normal
1285 * 4KB page. If the need for distinguishing between big and normal page becomes
1286 * necessary at a later point, a PGMGstGetPage() will be created for that
1287 * purpose.
1288 *
1289 * @returns VBox status.
1290 * @param pVM VM Handle.
1291 * @param GCPtr Guest Context virtual address of the page.
1292 * @param pfFlags Where to store the flags. These are X86_PTE_*, even for big pages.
1293 * @param pGCPhys Where to store the GC physical address of the page.
1294 * This is page aligned. The fact that the
1295 */
1296VMMDECL(int) PGMGstGetPage(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys)
1297{
1298 return PGM_GST_PFN(GetPage,pVM)(pVM, GCPtr, pfFlags, pGCPhys);
1299}
1300
1301
1302/**
1303 * Checks if the page is present.
1304 *
1305 * @returns true if the page is present.
1306 * @returns false if the page is not present.
1307 * @param pVM The VM handle.
1308 * @param GCPtr Address within the page.
1309 */
1310VMMDECL(bool) PGMGstIsPagePresent(PVM pVM, RTGCPTR GCPtr)
1311{
1312 int rc = PGMGstGetPage(pVM, GCPtr, NULL, NULL);
1313 return RT_SUCCESS(rc);
1314}
1315
1316
1317/**
1318 * Sets (replaces) the page flags for a range of pages in the guest's tables.
1319 *
1320 * @returns VBox status.
1321 * @param pVM VM handle.
1322 * @param GCPtr The address of the first page.
1323 * @param cb The size of the range in bytes.
1324 * @param fFlags Page flags X86_PTE_*, excluding the page mask of course.
1325 */
1326VMMDECL(int) PGMGstSetPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags)
1327{
1328 return PGMGstModifyPage(pVM, GCPtr, cb, fFlags, 0);
1329}
1330
1331
1332/**
1333 * Modify page flags for a range of pages in the guest's tables
1334 *
1335 * The existing flags are ANDed with the fMask and ORed with the fFlags.
1336 *
1337 * @returns VBox status code.
1338 * @param pVM VM handle.
1339 * @param GCPtr Virtual address of the first page in the range.
1340 * @param cb Size (in bytes) of the range to apply the modification to.
1341 * @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
1342 * @param fMask The AND mask - page flags X86_PTE_*, excluding the page mask of course.
1343 * Be very CAREFUL when ~'ing constants which could be 32-bit!
1344 */
1345VMMDECL(int) PGMGstModifyPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
1346{
1347 STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,GstModifyPage), a);
1348
1349 /*
1350 * Validate input.
1351 */
1352 AssertMsg(!(fFlags & X86_PTE_PAE_PG_MASK), ("fFlags=%#llx\n", fFlags));
1353 Assert(cb);
1354
1355 LogFlow(("PGMGstModifyPage %RGv %d bytes fFlags=%08llx fMask=%08llx\n", GCPtr, cb, fFlags, fMask));
1356
1357 /*
1358 * Adjust input.
1359 */
1360 cb += GCPtr & PAGE_OFFSET_MASK;
1361 cb = RT_ALIGN_Z(cb, PAGE_SIZE);
1362 GCPtr = (GCPtr & PAGE_BASE_GC_MASK);
1363
1364 /*
1365 * Call worker.
1366 */
1367 int rc = PGM_GST_PFN(ModifyPage, pVM)(pVM, GCPtr, cb, fFlags, fMask);
1368
1369 STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,GstModifyPage), a);
1370 return rc;
1371}
1372
1373
1374/**
1375 * Gets the specified page directory pointer table entry.
1376 *
1377 * @returns PDP entry
1378 * @param pPGM Pointer to the PGM instance data.
1379 * @param iPdpt PDPT index
1380 */
1381VMMDECL(X86PDPE) PGMGstGetPaePDPtr(PVM pVM, unsigned iPdpt)
1382{
1383 Assert(iPdpt <= 3);
1384 return pgmGstGetPaePDPTPtr(&pVM->pgm.s)->a[iPdpt & 3];
1385}
1386
1387
1388/**
1389 * Gets the current CR3 register value for the shadow memory context.
1390 * @returns CR3 value.
1391 * @param pVM The VM handle.
1392 */
1393VMMDECL(RTHCPHYS) PGMGetHyperCR3(PVM pVM)
1394{
1395#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
1396 PGMMODE enmShadowMode = pVM->pgm.s.enmShadowMode;
1397 switch (enmShadowMode)
1398 {
1399 case PGMMODE_EPT:
1400 return pVM->pgm.s.HCPhysShwNestedRoot;
1401
1402 default:
1403 return pVM->pgm.s.HCPhysShwCR3;
1404 }
1405#else
1406 PGMMODE enmShadowMode = pVM->pgm.s.enmShadowMode;
1407 switch (enmShadowMode)
1408 {
1409 case PGMMODE_32_BIT:
1410 return pVM->pgm.s.HCPhysShw32BitPD;
1411
1412 case PGMMODE_PAE:
1413 case PGMMODE_PAE_NX:
1414 return pVM->pgm.s.HCPhysShwPaePdpt;
1415
1416 case PGMMODE_AMD64:
1417 case PGMMODE_AMD64_NX:
1418 return pVM->pgm.s.HCPhysShwCR3;
1419
1420 case PGMMODE_EPT:
1421 return pVM->pgm.s.HCPhysShwNestedRoot;
1422
1423 case PGMMODE_NESTED:
1424 return PGMGetNestedCR3(pVM, PGMGetHostMode(pVM));
1425
1426 default:
1427 AssertMsgFailed(("enmShadowMode=%d\n", enmShadowMode));
1428 return ~0;
1429 }
1430#endif
1431}
1432
1433
1434/**
1435 * Gets the current CR3 register value for the nested memory context.
1436 * @returns CR3 value.
1437 * @param pVM The VM handle.
1438 */
1439VMMDECL(RTHCPHYS) PGMGetNestedCR3(PVM pVM, PGMMODE enmShadowMode)
1440{
1441#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
1442 return pVM->pgm.s.HCPhysShwCR3;
1443#else
1444 switch (enmShadowMode)
1445 {
1446 case PGMMODE_32_BIT:
1447 return pVM->pgm.s.HCPhysShw32BitPD;
1448
1449 case PGMMODE_PAE:
1450 case PGMMODE_PAE_NX:
1451 return pVM->pgm.s.HCPhysShwPaePdpt;
1452
1453 case PGMMODE_AMD64:
1454 case PGMMODE_AMD64_NX:
1455 return pVM->pgm.s.HCPhysShwCR3;
1456
1457 default:
1458 AssertMsgFailed(("enmShadowMode=%d\n", enmShadowMode));
1459 return ~0;
1460 }
1461#endif
1462}
1463
1464
1465/**
1466 * Gets the current CR3 register value for the EPT paging memory context.
1467 * @returns CR3 value.
1468 * @param pVM The VM handle.
1469 */
1470VMMDECL(RTHCPHYS) PGMGetEPTCR3(PVM pVM)
1471{
1472 return pVM->pgm.s.HCPhysShwNestedRoot;
1473}
1474
1475
1476/**
1477 * Gets the CR3 register value for the 32-Bit shadow memory context.
1478 * @returns CR3 value.
1479 * @param pVM The VM handle.
1480 */
1481VMMDECL(RTHCPHYS) PGMGetHyper32BitCR3(PVM pVM)
1482{
1483#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
1484 return pVM->pgm.s.HCPhysShwCR3;
1485#else
1486 return pVM->pgm.s.HCPhysShw32BitPD;
1487#endif
1488}
1489
1490
1491/**
1492 * Gets the CR3 register value for the PAE shadow memory context.
1493 * @returns CR3 value.
1494 * @param pVM The VM handle.
1495 */
1496VMMDECL(RTHCPHYS) PGMGetHyperPaeCR3(PVM pVM)
1497{
1498#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
1499 return pVM->pgm.s.HCPhysShwCR3;
1500#else
1501 return pVM->pgm.s.HCPhysShwPaePdpt;
1502#endif
1503}
1504
1505
1506/**
1507 * Gets the CR3 register value for the AMD64 shadow memory context.
1508 * @returns CR3 value.
1509 * @param pVM The VM handle.
1510 */
1511VMMDECL(RTHCPHYS) PGMGetHyperAmd64CR3(PVM pVM)
1512{
1513 return pVM->pgm.s.HCPhysShwCR3;
1514}
1515
1516/**
1517 * Gets the current CR3 register value for the HC intermediate memory context.
1518 * @returns CR3 value.
1519 * @param pVM The VM handle.
1520 */
1521VMMDECL(RTHCPHYS) PGMGetInterHCCR3(PVM pVM)
1522{
1523 switch (pVM->pgm.s.enmHostMode)
1524 {
1525 case SUPPAGINGMODE_32_BIT:
1526 case SUPPAGINGMODE_32_BIT_GLOBAL:
1527 return pVM->pgm.s.HCPhysInterPD;
1528
1529 case SUPPAGINGMODE_PAE:
1530 case SUPPAGINGMODE_PAE_GLOBAL:
1531 case SUPPAGINGMODE_PAE_NX:
1532 case SUPPAGINGMODE_PAE_GLOBAL_NX:
1533 return pVM->pgm.s.HCPhysInterPaePDPT;
1534
1535 case SUPPAGINGMODE_AMD64:
1536 case SUPPAGINGMODE_AMD64_GLOBAL:
1537 case SUPPAGINGMODE_AMD64_NX:
1538 case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1539 return pVM->pgm.s.HCPhysInterPaePDPT;
1540
1541 default:
1542 AssertMsgFailed(("enmHostMode=%d\n", pVM->pgm.s.enmHostMode));
1543 return ~0;
1544 }
1545}
1546
1547
1548/**
1549 * Gets the current CR3 register value for the RC intermediate memory context.
1550 * @returns CR3 value.
1551 * @param pVM The VM handle.
1552 */
1553VMMDECL(RTHCPHYS) PGMGetInterRCCR3(PVM pVM)
1554{
1555 switch (pVM->pgm.s.enmShadowMode)
1556 {
1557 case PGMMODE_32_BIT:
1558 return pVM->pgm.s.HCPhysInterPD;
1559
1560 case PGMMODE_PAE:
1561 case PGMMODE_PAE_NX:
1562 return pVM->pgm.s.HCPhysInterPaePDPT;
1563
1564 case PGMMODE_AMD64:
1565 case PGMMODE_AMD64_NX:
1566 return pVM->pgm.s.HCPhysInterPaePML4;
1567
1568 case PGMMODE_EPT:
1569 case PGMMODE_NESTED:
1570 return 0; /* not relevant */
1571
1572 default:
1573 AssertMsgFailed(("enmShadowMode=%d\n", pVM->pgm.s.enmShadowMode));
1574 return ~0;
1575 }
1576}
1577
1578
1579/**
1580 * Gets the CR3 register value for the 32-Bit intermediate memory context.
1581 * @returns CR3 value.
1582 * @param pVM The VM handle.
1583 */
1584VMMDECL(RTHCPHYS) PGMGetInter32BitCR3(PVM pVM)
1585{
1586 return pVM->pgm.s.HCPhysInterPD;
1587}
1588
1589
1590/**
1591 * Gets the CR3 register value for the PAE intermediate memory context.
1592 * @returns CR3 value.
1593 * @param pVM The VM handle.
1594 */
1595VMMDECL(RTHCPHYS) PGMGetInterPaeCR3(PVM pVM)
1596{
1597 return pVM->pgm.s.HCPhysInterPaePDPT;
1598}
1599
1600
1601/**
1602 * Gets the CR3 register value for the AMD64 intermediate memory context.
1603 * @returns CR3 value.
1604 * @param pVM The VM handle.
1605 */
1606VMMDECL(RTHCPHYS) PGMGetInterAmd64CR3(PVM pVM)
1607{
1608 return pVM->pgm.s.HCPhysInterPaePML4;
1609}
1610
1611
1612/**
1613 * Performs and schedules necessary updates following a CR3 load or reload.
1614 *
1615 * This will normally involve mapping the guest PD or nPDPT
1616 *
1617 * @returns VBox status code.
1618 * @retval VINF_PGM_SYNC_CR3 if monitoring requires a CR3 sync. This can
1619 * safely be ignored and overridden since the FF will be set too then.
1620 * @param pVM VM handle.
1621 * @param cr3 The new cr3.
1622 * @param fGlobal Indicates whether this is a global flush or not.
1623 */
1624VMMDECL(int) PGMFlushTLB(PVM pVM, uint64_t cr3, bool fGlobal)
1625{
1626 STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,FlushTLB), a);
1627
1628 /*
1629 * Always flag the necessary updates; necessary for hardware acceleration
1630 */
1631 /** @todo optimize this, it shouldn't always be necessary. */
1632 VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
1633 if (fGlobal)
1634 VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
1635 LogFlow(("PGMFlushTLB: cr3=%RX64 OldCr3=%RX64 fGlobal=%d\n", cr3, pVM->pgm.s.GCPhysCR3, fGlobal));
1636
1637 /*
1638 * Remap the CR3 content and adjust the monitoring if CR3 was actually changed.
1639 */
1640 int rc = VINF_SUCCESS;
1641 RTGCPHYS GCPhysCR3;
1642 if ( pVM->pgm.s.enmGuestMode == PGMMODE_PAE
1643 || pVM->pgm.s.enmGuestMode == PGMMODE_PAE_NX
1644 || pVM->pgm.s.enmGuestMode == PGMMODE_AMD64
1645 || pVM->pgm.s.enmGuestMode == PGMMODE_AMD64_NX)
1646 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAE_PAGE_MASK);
1647 else
1648 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAGE_MASK);
1649 if (pVM->pgm.s.GCPhysCR3 != GCPhysCR3)
1650 {
1651#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
1652 /* Unmap the old CR3 value before activating the new one. */
1653 rc = PGM_BTH_PFN(UnmapCR3, pVM)(pVM);
1654 AssertRC(rc);
1655#endif
1656 RTGCPHYS GCPhysOldCR3 = pVM->pgm.s.GCPhysCR3;
1657 pVM->pgm.s.GCPhysCR3 = GCPhysCR3;
1658 rc = PGM_BTH_PFN(MapCR3, pVM)(pVM, GCPhysCR3);
1659 if (RT_LIKELY(rc == VINF_SUCCESS))
1660 {
1661 if (!pVM->pgm.s.fMappingsFixed)
1662 {
1663 pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
1664#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1665 rc = PGM_GST_PFN(MonitorCR3, pVM)(pVM, GCPhysCR3);
1666#endif
1667 }
1668 }
1669 else
1670 {
1671 AssertMsg(rc == VINF_PGM_SYNC_CR3, ("%Rrc\n", rc));
1672 Assert(VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL | VM_FF_PGM_SYNC_CR3));
1673 pVM->pgm.s.GCPhysCR3 = GCPhysOldCR3;
1674 pVM->pgm.s.fSyncFlags |= PGM_SYNC_MAP_CR3;
1675 if (!pVM->pgm.s.fMappingsFixed)
1676 pVM->pgm.s.fSyncFlags |= PGM_SYNC_MONITOR_CR3;
1677 }
1678
1679 if (fGlobal)
1680 STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,FlushTLBNewCR3Global));
1681 else
1682 STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,FlushTLBNewCR3));
1683 }
1684 else
1685 {
1686 /*
1687 * Check if we have a pending update of the CR3 monitoring.
1688 */
1689 if (pVM->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
1690 {
1691 pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
1692 Assert(!pVM->pgm.s.fMappingsFixed);
1693#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1694 rc = PGM_GST_PFN(MonitorCR3, pVM)(pVM, GCPhysCR3);
1695#endif
1696 }
1697 if (fGlobal)
1698 STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,FlushTLBSameCR3Global));
1699 else
1700 STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,FlushTLBSameCR3));
1701 }
1702
1703 STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,FlushTLB), a);
1704 return rc;
1705}
1706
1707
1708/**
1709 * Performs and schedules necessary updates following a CR3 load or reload when
1710 * using nested or extended paging.
1711 *
1712 * This API is an alterantive to PDMFlushTLB that avoids actually flushing the
1713 * TLB and triggering a SyncCR3.
1714 *
1715 * This will normally involve mapping the guest PD or nPDPT
1716 *
1717 * @returns VBox status code.
1718 * @retval VINF_SUCCESS.
1719 * @retval (If applied when not in nested mode: VINF_PGM_SYNC_CR3 if monitoring
1720 * requires a CR3 sync. This can safely be ignored and overridden since
1721 * the FF will be set too then.)
1722 * @param pVM VM handle.
1723 * @param cr3 The new cr3.
1724 */
1725VMMDECL(int) PGMUpdateCR3(PVM pVM, uint64_t cr3)
1726{
1727 LogFlow(("PGMUpdateCR3: cr3=%RX64 OldCr3=%RX64\n", cr3, pVM->pgm.s.GCPhysCR3));
1728
1729 /* We assume we're only called in nested paging mode. */
1730 Assert(pVM->pgm.s.fMappingsFixed);
1731 Assert(!(pVM->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3));
1732 Assert(pVM->pgm.s.enmShadowMode == PGMMODE_NESTED || pVM->pgm.s.enmShadowMode == PGMMODE_EPT);
1733
1734 /*
1735 * Remap the CR3 content and adjust the monitoring if CR3 was actually changed.
1736 */
1737 int rc = VINF_SUCCESS;
1738 RTGCPHYS GCPhysCR3;
1739 if ( pVM->pgm.s.enmGuestMode == PGMMODE_PAE
1740 || pVM->pgm.s.enmGuestMode == PGMMODE_PAE_NX
1741 || pVM->pgm.s.enmGuestMode == PGMMODE_AMD64
1742 || pVM->pgm.s.enmGuestMode == PGMMODE_AMD64_NX)
1743 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAE_PAGE_MASK);
1744 else
1745 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAGE_MASK);
1746 if (pVM->pgm.s.GCPhysCR3 != GCPhysCR3)
1747 {
1748 pVM->pgm.s.GCPhysCR3 = GCPhysCR3;
1749 rc = PGM_BTH_PFN(MapCR3, pVM)(pVM, GCPhysCR3);
1750 AssertRCSuccess(rc); /* Assumes VINF_PGM_SYNC_CR3 doesn't apply to nested paging. */
1751 }
1752 return rc;
1753}
1754
1755
1756/**
1757 * Synchronize the paging structures.
1758 *
1759 * This function is called in response to the VM_FF_PGM_SYNC_CR3 and
1760 * VM_FF_PGM_SYNC_CR3_NONGLOBAL. Those two force action flags are set
1761 * in several places, most importantly whenever the CR3 is loaded.
1762 *
1763 * @returns VBox status code.
1764 * @param pVM The virtual machine.
1765 * @param cr0 Guest context CR0 register
1766 * @param cr3 Guest context CR3 register
1767 * @param cr4 Guest context CR4 register
1768 * @param fGlobal Including global page directories or not
1769 */
1770VMMDECL(int) PGMSyncCR3(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
1771{
1772 int rc;
1773
1774 /*
1775 * We might be called when we shouldn't.
1776 *
1777 * The mode switching will ensure that the PD is resynced
1778 * after every mode switch. So, if we find ourselves here
1779 * when in protected or real mode we can safely disable the
1780 * FF and return immediately.
1781 */
1782 if (pVM->pgm.s.enmGuestMode <= PGMMODE_PROTECTED)
1783 {
1784 Assert((cr0 & (X86_CR0_PG | X86_CR0_PE)) != (X86_CR0_PG | X86_CR0_PE));
1785 VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3);
1786 VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
1787 return VINF_SUCCESS;
1788 }
1789
1790 /* If global pages are not supported, then all flushes are global. */
1791 if (!(cr4 & X86_CR4_PGE))
1792 fGlobal = true;
1793 LogFlow(("PGMSyncCR3: cr0=%RX64 cr3=%RX64 cr4=%RX64 fGlobal=%d[%d,%d]\n", cr0, cr3, cr4, fGlobal,
1794 VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3), VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL)));
1795
1796#ifdef PGMPOOL_WITH_MONITORING
1797 /*
1798 * The pool may have pending stuff and even require a return to ring-3 to
1799 * clear the whole thing.
1800 */
1801 rc = pgmPoolSyncCR3(pVM);
1802 if (rc != VINF_SUCCESS)
1803 return rc;
1804#endif
1805
1806 /*
1807 * Check if we need to finish an aborted MapCR3 call (see PGMFlushTLB).
1808 * This should be done before SyncCR3.
1809 */
1810 if (pVM->pgm.s.fSyncFlags & PGM_SYNC_MAP_CR3)
1811 {
1812 pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_MAP_CR3;
1813
1814 RTGCPHYS GCPhysCR3Old = pVM->pgm.s.GCPhysCR3;
1815 RTGCPHYS GCPhysCR3;
1816 if ( pVM->pgm.s.enmGuestMode == PGMMODE_PAE
1817 || pVM->pgm.s.enmGuestMode == PGMMODE_PAE_NX
1818 || pVM->pgm.s.enmGuestMode == PGMMODE_AMD64
1819 || pVM->pgm.s.enmGuestMode == PGMMODE_AMD64_NX)
1820 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAE_PAGE_MASK);
1821 else
1822 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAGE_MASK);
1823
1824#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
1825 if (pVM->pgm.s.GCPhysCR3 != GCPhysCR3)
1826 {
1827 /* Unmap the old CR3 value before activating the new one. */
1828 rc = PGM_BTH_PFN(UnmapCR3, pVM)(pVM);
1829 AssertRC(rc);
1830 }
1831#endif
1832
1833 pVM->pgm.s.GCPhysCR3 = GCPhysCR3;
1834 rc = PGM_BTH_PFN(MapCR3, pVM)(pVM, GCPhysCR3);
1835#ifdef IN_RING3
1836 if (rc == VINF_PGM_SYNC_CR3)
1837 rc = pgmPoolSyncCR3(pVM);
1838#else
1839 if (rc == VINF_PGM_SYNC_CR3)
1840 {
1841 pVM->pgm.s.GCPhysCR3 = GCPhysCR3Old;
1842 return rc;
1843 }
1844#endif
1845 AssertRCReturn(rc, rc);
1846 AssertRCSuccessReturn(rc, VERR_INTERNAL_ERROR);
1847 }
1848
1849 /*
1850 * Let the 'Bth' function do the work and we'll just keep track of the flags.
1851 */
1852 STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3), a);
1853 rc = PGM_BTH_PFN(SyncCR3, pVM)(pVM, cr0, cr3, cr4, fGlobal);
1854 STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3), a);
1855 AssertMsg(rc == VINF_SUCCESS || rc == VINF_PGM_SYNC_CR3 || RT_FAILURE(rc), ("rc=%Rrc\n", rc));
1856 if (rc == VINF_SUCCESS)
1857 {
1858 if (!(pVM->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS))
1859 {
1860 VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3);
1861 VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
1862 }
1863
1864 /*
1865 * Check if we have a pending update of the CR3 monitoring.
1866 */
1867 if (pVM->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
1868 {
1869 pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
1870 Assert(!pVM->pgm.s.fMappingsFixed);
1871#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1872 Assert(pVM->pgm.s.GCPhysCR3 == pVM->pgm.s.GCPhysGstCR3Monitored);
1873 rc = PGM_GST_PFN(MonitorCR3, pVM)(pVM, pVM->pgm.s.GCPhysCR3);
1874#endif
1875 }
1876 }
1877
1878 /*
1879 * Now flush the CR3 (guest context).
1880 */
1881 if (rc == VINF_SUCCESS)
1882 PGM_INVL_GUEST_TLBS();
1883 return rc;
1884}
1885
1886
1887/**
1888 * Called whenever CR0 or CR4 in a way which may change
1889 * the paging mode.
1890 *
1891 * @returns VBox status code fit for scheduling in GC and R0.
1892 * @retval VINF_SUCCESS if the was no change, or it was successfully dealt with.
1893 * @retval VINF_PGM_CHANGE_MODE if we're in GC or R0 and the mode changes.
1894 * @param pVM VM handle.
1895 * @param cr0 The new cr0.
1896 * @param cr4 The new cr4.
1897 * @param efer The new extended feature enable register.
1898 */
1899VMMDECL(int) PGMChangeMode(PVM pVM, uint64_t cr0, uint64_t cr4, uint64_t efer)
1900{
1901 PGMMODE enmGuestMode;
1902
1903 /*
1904 * Calc the new guest mode.
1905 */
1906 if (!(cr0 & X86_CR0_PE))
1907 enmGuestMode = PGMMODE_REAL;
1908 else if (!(cr0 & X86_CR0_PG))
1909 enmGuestMode = PGMMODE_PROTECTED;
1910 else if (!(cr4 & X86_CR4_PAE))
1911 enmGuestMode = PGMMODE_32_BIT;
1912 else if (!(efer & MSR_K6_EFER_LME))
1913 {
1914 if (!(efer & MSR_K6_EFER_NXE))
1915 enmGuestMode = PGMMODE_PAE;
1916 else
1917 enmGuestMode = PGMMODE_PAE_NX;
1918 }
1919 else
1920 {
1921 if (!(efer & MSR_K6_EFER_NXE))
1922 enmGuestMode = PGMMODE_AMD64;
1923 else
1924 enmGuestMode = PGMMODE_AMD64_NX;
1925 }
1926
1927 /*
1928 * Did it change?
1929 */
1930 if (pVM->pgm.s.enmGuestMode == enmGuestMode)
1931 return VINF_SUCCESS;
1932
1933 /* Flush the TLB */
1934 PGM_INVL_GUEST_TLBS();
1935
1936#ifdef IN_RING3
1937 return PGMR3ChangeMode(pVM, enmGuestMode);
1938#else
1939 LogFlow(("PGMChangeMode: returns VINF_PGM_CHANGE_MODE.\n"));
1940 return VINF_PGM_CHANGE_MODE;
1941#endif
1942}
1943
1944
1945/**
1946 * Gets the current guest paging mode.
1947 *
1948 * If you just need the CPU mode (real/protected/long), use CPUMGetGuestMode().
1949 *
1950 * @returns The current paging mode.
1951 * @param pVM The VM handle.
1952 */
1953VMMDECL(PGMMODE) PGMGetGuestMode(PVM pVM)
1954{
1955 return pVM->pgm.s.enmGuestMode;
1956}
1957
1958
1959/**
1960 * Gets the current shadow paging mode.
1961 *
1962 * @returns The current paging mode.
1963 * @param pVM The VM handle.
1964 */
1965VMMDECL(PGMMODE) PGMGetShadowMode(PVM pVM)
1966{
1967 return pVM->pgm.s.enmShadowMode;
1968}
1969
1970/**
1971 * Gets the current host paging mode.
1972 *
1973 * @returns The current paging mode.
1974 * @param pVM The VM handle.
1975 */
1976VMMDECL(PGMMODE) PGMGetHostMode(PVM pVM)
1977{
1978 switch (pVM->pgm.s.enmHostMode)
1979 {
1980 case SUPPAGINGMODE_32_BIT:
1981 case SUPPAGINGMODE_32_BIT_GLOBAL:
1982 return PGMMODE_32_BIT;
1983
1984 case SUPPAGINGMODE_PAE:
1985 case SUPPAGINGMODE_PAE_GLOBAL:
1986 return PGMMODE_PAE;
1987
1988 case SUPPAGINGMODE_PAE_NX:
1989 case SUPPAGINGMODE_PAE_GLOBAL_NX:
1990 return PGMMODE_PAE_NX;
1991
1992 case SUPPAGINGMODE_AMD64:
1993 case SUPPAGINGMODE_AMD64_GLOBAL:
1994 return PGMMODE_AMD64;
1995
1996 case SUPPAGINGMODE_AMD64_NX:
1997 case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1998 return PGMMODE_AMD64_NX;
1999
2000 default: AssertMsgFailed(("enmHostMode=%d\n", pVM->pgm.s.enmHostMode)); break;
2001 }
2002
2003 return PGMMODE_INVALID;
2004}
2005
2006
2007/**
2008 * Get mode name.
2009 *
2010 * @returns read-only name string.
2011 * @param enmMode The mode which name is desired.
2012 */
2013VMMDECL(const char *) PGMGetModeName(PGMMODE enmMode)
2014{
2015 switch (enmMode)
2016 {
2017 case PGMMODE_REAL: return "Real";
2018 case PGMMODE_PROTECTED: return "Protected";
2019 case PGMMODE_32_BIT: return "32-bit";
2020 case PGMMODE_PAE: return "PAE";
2021 case PGMMODE_PAE_NX: return "PAE+NX";
2022 case PGMMODE_AMD64: return "AMD64";
2023 case PGMMODE_AMD64_NX: return "AMD64+NX";
2024 case PGMMODE_NESTED: return "Nested";
2025 case PGMMODE_EPT: return "EPT";
2026 default: return "unknown mode value";
2027 }
2028}
2029
2030
2031/**
2032 * Acquire the PGM lock.
2033 *
2034 * @returns VBox status code
2035 * @param pVM The VM to operate on.
2036 */
2037int pgmLock(PVM pVM)
2038{
2039 int rc = PDMCritSectEnter(&pVM->pgm.s.CritSect, VERR_SEM_BUSY);
2040#ifdef IN_RC
2041 if (rc == VERR_SEM_BUSY)
2042 rc = VMMGCCallHost(pVM, VMMCALLHOST_PGM_LOCK, 0);
2043#elif defined(IN_RING0)
2044 if (rc == VERR_SEM_BUSY)
2045 rc = VMMR0CallHost(pVM, VMMCALLHOST_PGM_LOCK, 0);
2046#endif
2047 AssertRC(rc);
2048 return rc;
2049}
2050
2051
2052/**
2053 * Release the PGM lock.
2054 *
2055 * @returns VBox status code
2056 * @param pVM The VM to operate on.
2057 */
2058void pgmUnlock(PVM pVM)
2059{
2060 PDMCritSectLeave(&pVM->pgm.s.CritSect);
2061}
2062
2063#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2064
2065/**
2066 * Temporarily maps one guest page specified by GC physical address.
2067 * These pages must have a physical mapping in HC, i.e. they cannot be MMIO pages.
2068 *
2069 * Be WARNED that the dynamic page mapping area is small, 8 pages, thus the space is
2070 * reused after 8 mappings (or perhaps a few more if you score with the cache).
2071 *
2072 * @returns VBox status.
2073 * @param pVM VM handle.
2074 * @param GCPhys GC Physical address of the page.
2075 * @param ppv Where to store the address of the mapping.
2076 */
2077VMMDECL(int) PGMDynMapGCPage(PVM pVM, RTGCPHYS GCPhys, void **ppv)
2078{
2079 AssertMsg(!(GCPhys & PAGE_OFFSET_MASK), ("GCPhys=%RGp\n", GCPhys));
2080
2081 /*
2082 * Get the ram range.
2083 */
2084 PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
2085 while (pRam && GCPhys - pRam->GCPhys >= pRam->cb)
2086 pRam = pRam->CTX_SUFF(pNext);
2087 if (!pRam)
2088 {
2089 AssertMsgFailed(("Invalid physical address %RGp!\n", GCPhys));
2090 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2091 }
2092
2093 /*
2094 * Pass it on to PGMDynMapHCPage.
2095 */
2096 RTHCPHYS HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT]);
2097 //Log(("PGMDynMapGCPage: GCPhys=%RGp HCPhys=%RHp\n", GCPhys, HCPhys));
2098#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2099 pgmR0DynMapHCPageInlined(&pVM->pgm.s, HCPhys, ppv);
2100#else
2101 PGMDynMapHCPage(pVM, HCPhys, ppv);
2102#endif
2103 return VINF_SUCCESS;
2104}
2105
2106
2107/**
2108 * Temporarily maps one guest page specified by unaligned GC physical address.
2109 * These pages must have a physical mapping in HC, i.e. they cannot be MMIO pages.
2110 *
2111 * Be WARNED that the dynamic page mapping area is small, 8 pages, thus the space is
2112 * reused after 8 mappings (or perhaps a few more if you score with the cache).
2113 *
2114 * The caller is aware that only the speicifed page is mapped and that really bad things
2115 * will happen if writing beyond the page!
2116 *
2117 * @returns VBox status.
2118 * @param pVM VM handle.
2119 * @param GCPhys GC Physical address within the page to be mapped.
2120 * @param ppv Where to store the address of the mapping address corresponding to GCPhys.
2121 */
2122VMMDECL(int) PGMDynMapGCPageOff(PVM pVM, RTGCPHYS GCPhys, void **ppv)
2123{
2124 /*
2125 * Get the ram range.
2126 */
2127 PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
2128 while (pRam && GCPhys - pRam->GCPhys >= pRam->cb)
2129 pRam = pRam->CTX_SUFF(pNext);
2130 if (!pRam)
2131 {
2132 AssertMsgFailed(("Invalid physical address %RGp!\n", GCPhys));
2133 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2134 }
2135
2136 /*
2137 * Pass it on to PGMDynMapHCPage.
2138 */
2139 RTHCPHYS HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT]);
2140#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2141 pgmR0DynMapHCPageInlined(&pVM->pgm.s, HCPhys, ppv);
2142#else
2143 PGMDynMapHCPage(pVM, HCPhys, ppv);
2144#endif
2145 *ppv = (void *)((uintptr_t)*ppv | (GCPhys & PAGE_OFFSET_MASK));
2146 return VINF_SUCCESS;
2147}
2148
2149
2150# ifdef IN_RC
2151/**
2152 * Temporarily maps one host page specified by HC physical address.
2153 *
2154 * Be WARNED that the dynamic page mapping area is small, 16 pages, thus the space is
2155 * reused after 16 mappings (or perhaps a few more if you score with the cache).
2156 *
2157 * @returns VINF_SUCCESS, will bail out to ring-3 on failure.
2158 * @param pVM VM handle.
2159 * @param HCPhys HC Physical address of the page.
2160 * @param ppv Where to store the address of the mapping. This is the
2161 * address of the PAGE not the exact address corresponding
2162 * to HCPhys. Use PGMDynMapHCPageOff if you care for the
2163 * page offset.
2164 */
2165VMMDECL(int) PGMDynMapHCPage(PVM pVM, RTHCPHYS HCPhys, void **ppv)
2166{
2167 AssertMsg(!(HCPhys & PAGE_OFFSET_MASK), ("HCPhys=%RHp\n", HCPhys));
2168
2169 /*
2170 * Check the cache.
2171 */
2172 register unsigned iCache;
2173 for (iCache = 0;iCache < RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache);iCache++)
2174 {
2175 static const uint8_t au8Trans[MM_HYPER_DYNAMIC_SIZE >> PAGE_SHIFT][RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache)] =
2176 {
2177 { 0, 9, 10, 11, 12, 13, 14, 15},
2178 { 0, 1, 10, 11, 12, 13, 14, 15},
2179 { 0, 1, 2, 11, 12, 13, 14, 15},
2180 { 0, 1, 2, 3, 12, 13, 14, 15},
2181 { 0, 1, 2, 3, 4, 13, 14, 15},
2182 { 0, 1, 2, 3, 4, 5, 14, 15},
2183 { 0, 1, 2, 3, 4, 5, 6, 15},
2184 { 0, 1, 2, 3, 4, 5, 6, 7},
2185 { 8, 1, 2, 3, 4, 5, 6, 7},
2186 { 8, 9, 2, 3, 4, 5, 6, 7},
2187 { 8, 9, 10, 3, 4, 5, 6, 7},
2188 { 8, 9, 10, 11, 4, 5, 6, 7},
2189 { 8, 9, 10, 11, 12, 5, 6, 7},
2190 { 8, 9, 10, 11, 12, 13, 6, 7},
2191 { 8, 9, 10, 11, 12, 13, 14, 7},
2192 { 8, 9, 10, 11, 12, 13, 14, 15},
2193 };
2194 AssertCompile(RT_ELEMENTS(au8Trans) == 16);
2195 AssertCompile(RT_ELEMENTS(au8Trans[0]) == 8);
2196
2197 if (pVM->pgm.s.aHCPhysDynPageMapCache[iCache] == HCPhys)
2198 {
2199 int iPage = au8Trans[pVM->pgm.s.iDynPageMapLast][iCache];
2200 void *pv = pVM->pgm.s.pbDynPageMapBaseGC + (iPage << PAGE_SHIFT);
2201 *ppv = pv;
2202 STAM_COUNTER_INC(&pVM->pgm.s.StatRCDynMapCacheHits);
2203 Log4(("PGMGCDynMapHCPage: HCPhys=%RHp pv=%p iPage=%d iCache=%d\n", HCPhys, pv, iPage, iCache));
2204 return VINF_SUCCESS;
2205 }
2206 }
2207 AssertCompile(RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache) == 8);
2208 AssertCompile((MM_HYPER_DYNAMIC_SIZE >> PAGE_SHIFT) == 16);
2209 STAM_COUNTER_INC(&pVM->pgm.s.StatRCDynMapCacheMisses);
2210
2211 /*
2212 * Update the page tables.
2213 */
2214 register unsigned iPage = pVM->pgm.s.iDynPageMapLast;
2215# ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
2216 unsigned i;
2217 for (i=0;i<(MM_HYPER_DYNAMIC_SIZE >> PAGE_SHIFT);i++)
2218 {
2219 pVM->pgm.s.iDynPageMapLast = iPage = (iPage + 1) & ((MM_HYPER_DYNAMIC_SIZE >> PAGE_SHIFT) - 1);
2220 if (!(pVM->pgm.s.paDynPageMap32BitPTEsGC[iPage].u & PGM_PTFLAGS_DYN_LOCKED))
2221 break;
2222 iPage++;
2223 }
2224 AssertRelease(i != (MM_HYPER_DYNAMIC_SIZE >> PAGE_SHIFT));
2225# else
2226 pVM->pgm.s.iDynPageMapLast = iPage = (iPage + 1) & ((MM_HYPER_DYNAMIC_SIZE >> PAGE_SHIFT) - 1);
2227# endif
2228
2229 pVM->pgm.s.aHCPhysDynPageMapCache[iPage & (RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache) - 1)] = HCPhys;
2230 pVM->pgm.s.paDynPageMap32BitPTEsGC[iPage].u = (uint32_t)HCPhys | X86_PTE_P | X86_PTE_A | X86_PTE_D;
2231 pVM->pgm.s.paDynPageMapPaePTEsGC[iPage].u = HCPhys | X86_PTE_P | X86_PTE_A | X86_PTE_D;
2232
2233 void *pv = pVM->pgm.s.pbDynPageMapBaseGC + (iPage << PAGE_SHIFT);
2234 *ppv = pv;
2235 ASMInvalidatePage(pv);
2236 Log4(("PGMGCDynMapHCPage: HCPhys=%RHp pv=%p iPage=%d\n", HCPhys, pv, iPage));
2237 return VINF_SUCCESS;
2238}
2239
2240/**
2241 * Temporarily lock a dynamic page to prevent it from being reused.
2242 *
2243 * @returns VINF_SUCCESS, will bail out to ring-3 on failure.
2244 * @param pVM VM handle.
2245 * @param GCPage GC address of page
2246 */
2247VMMDECL(int) PGMDynLockHCPage(PVM pVM, RCPTRTYPE(uint8_t *) GCPage)
2248{
2249 unsigned iPage;
2250
2251 Assert(GCPage >= pVM->pgm.s.pbDynPageMapBaseGC && GCPage < (pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE));
2252 iPage = ((uintptr_t)(GCPage - pVM->pgm.s.pbDynPageMapBaseGC)) >> PAGE_SHIFT;
2253 Assert(!(pVM->pgm.s.paDynPageMap32BitPTEsGC[iPage].u & PGM_PTFLAGS_DYN_LOCKED));
2254 pVM->pgm.s.paDynPageMap32BitPTEsGC[iPage].u |= PGM_PTFLAGS_DYN_LOCKED;
2255 return VINF_SUCCESS;
2256}
2257
2258/**
2259 * Unlock a dynamic page
2260 *
2261 * @returns VINF_SUCCESS, will bail out to ring-3 on failure.
2262 * @param pVM VM handle.
2263 * @param GCPage GC address of page
2264 */
2265VMMDECL(int) PGMDynUnlockHCPage(PVM pVM, RCPTRTYPE(uint8_t *) GCPage)
2266{
2267 unsigned iPage;
2268
2269 Assert(GCPage >= pVM->pgm.s.pbDynPageMapBaseGC && GCPage < (pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE));
2270 iPage = ((uintptr_t)(GCPage - pVM->pgm.s.pbDynPageMapBaseGC)) >> PAGE_SHIFT;
2271 Assert(pVM->pgm.s.paDynPageMap32BitPTEsGC[iPage].u & PGM_PTFLAGS_DYN_LOCKED);
2272 pVM->pgm.s.paDynPageMap32BitPTEsGC[iPage].u &= ~PGM_PTFLAGS_DYN_LOCKED;
2273 return VINF_SUCCESS;
2274}
2275
2276# ifdef VBOX_STRICT
2277/**
2278 * Check for lock leaks.
2279 *
2280 * @param pVM VM handle.
2281 */
2282VMMDECL(void) PGMDynCheckLocks(PVM pVM)
2283{
2284 for (unsigned i=0;i<(MM_HYPER_DYNAMIC_SIZE >> PAGE_SHIFT);i++)
2285 Assert(!(pVM->pgm.s.paDynPageMap32BitPTEsGC[i].u & PGM_PTFLAGS_DYN_LOCKED));
2286}
2287# endif
2288# endif /* IN_RC */
2289
2290#endif /* IN_RC || VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
2291#ifdef VBOX_STRICT
2292
2293/**
2294 * Asserts that there are no mapping conflicts.
2295 *
2296 * @returns Number of conflicts.
2297 * @param pVM The VM Handle.
2298 */
2299VMMDECL(unsigned) PGMAssertNoMappingConflicts(PVM pVM)
2300{
2301 unsigned cErrors = 0;
2302
2303 /*
2304 * Check for mapping conflicts.
2305 */
2306 for (PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
2307 pMapping;
2308 pMapping = pMapping->CTX_SUFF(pNext))
2309 {
2310 /** @todo This is slow and should be optimized, but since it's just assertions I don't care now. */
2311 for (RTGCPTR GCPtr = pMapping->GCPtr;
2312 GCPtr <= pMapping->GCPtrLast;
2313 GCPtr += PAGE_SIZE)
2314 {
2315 int rc = PGMGstGetPage(pVM, (RTGCPTR)GCPtr, NULL, NULL);
2316 if (rc != VERR_PAGE_TABLE_NOT_PRESENT)
2317 {
2318 AssertMsgFailed(("Conflict at %RGv with %s\n", GCPtr, R3STRING(pMapping->pszDesc)));
2319 cErrors++;
2320 break;
2321 }
2322 }
2323 }
2324
2325 return cErrors;
2326}
2327
2328
2329/**
2330 * Asserts that everything related to the guest CR3 is correctly shadowed.
2331 *
2332 * This will call PGMAssertNoMappingConflicts() and PGMAssertHandlerAndFlagsInSync(),
2333 * and assert the correctness of the guest CR3 mapping before asserting that the
2334 * shadow page tables is in sync with the guest page tables.
2335 *
2336 * @returns Number of conflicts.
2337 * @param pVM The VM Handle.
2338 * @param cr3 The current guest CR3 register value.
2339 * @param cr4 The current guest CR4 register value.
2340 */
2341VMMDECL(unsigned) PGMAssertCR3(PVM pVM, uint64_t cr3, uint64_t cr4)
2342{
2343 STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3), a);
2344 unsigned cErrors = PGM_BTH_PFN(AssertCR3, pVM)(pVM, cr3, cr4, 0, ~(RTGCPTR)0);
2345 STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3), a);
2346 return cErrors;
2347}
2348
2349#endif /* VBOX_STRICT */
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