PGMAll.cpp@ 18279

Last change on this file since 18279 was 18131, checked in by vboxsync, 16 years ago
darwin build fix.
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1	/* $Id: PGMAll.cpp 18131 2009-03-23 10:32:05Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor - All context code.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	/*******************************************************************************
23	* Header Files *
24	*******************************************************************************/
25	#define LOG_GROUP LOG_GROUP_PGM
26	#include <VBox/pgm.h>
27	#include <VBox/cpum.h>
28	#include <VBox/selm.h>
29	#include <VBox/iom.h>
30	#include <VBox/sup.h>
31	#include <VBox/mm.h>
32	#include <VBox/stam.h>
33	#include <VBox/csam.h>
34	#include <VBox/patm.h>
35	#include <VBox/trpm.h>
36	#include <VBox/rem.h>
37	#include <VBox/em.h>
38	#include <VBox/hwaccm.h>
39	#include <VBox/hwacc_vmx.h>
40	#include "PGMInternal.h"
41	#include <VBox/vm.h>
42	#include <iprt/assert.h>
43	#include <iprt/asm.h>
44	#include <iprt/string.h>
45	#include <VBox/log.h>
46	#include <VBox/param.h>
47	#include <VBox/err.h>
48
49
50	/*******************************************************************************
51	* Structures and Typedefs *
52	*******************************************************************************/
53	/**
54	* Stated structure for PGM_GST_NAME(HandlerVirtualUpdate) that's
55	* passed to PGM_GST_NAME(VirtHandlerUpdateOne) during enumeration.
56	*/
57	typedef struct PGMHVUSTATE
58	{
59	/** The VM handle. */
60	PVM pVM;
61	/** The todo flags. */
62	RTUINT fTodo;
63	/** The CR4 register value. */
64	uint32_t cr4;
65	} PGMHVUSTATE, *PPGMHVUSTATE;
66
67
68	/*******************************************************************************
69	* Internal Functions *
70	*******************************************************************************/
71	DECLINLINE(int) pgmShwGetLongModePDPtr(PVM pVM, RTGCPTR64 GCPtr, PX86PML4E ppPml4e, PX86PDPT ppPdpt, PX86PDPAE *ppPD);
72	DECLINLINE(int) pgmShwGetPAEPDPtr(PVM pVM, RTGCPTR GCPtr, PX86PDPT ppPdpt, PX86PDPAE ppPD);
73	DECLINLINE(int) pgmShwGetPaePoolPagePD(PPGM pPGM, RTGCPTR GCPtr, PPGMPOOLPAGE *ppShwPde);
74
75	/*
76	* Shadow - 32-bit mode
77	*/
78	#define PGM_SHW_TYPE PGM_TYPE_32BIT
79	#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
80	#include "PGMAllShw.h"
81
82	/* Guest - real mode */
83	#define PGM_GST_TYPE PGM_TYPE_REAL
84	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
85	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
86	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
87	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
88	#include "PGMGstDefs.h"
89	#include "PGMAllGst.h"
90	#include "PGMAllBth.h"
91	#undef BTH_PGMPOOLKIND_PT_FOR_PT
92	#undef BTH_PGMPOOLKIND_ROOT
93	#undef PGM_BTH_NAME
94	#undef PGM_GST_TYPE
95	#undef PGM_GST_NAME
96
97	/* Guest - protected mode */
98	#define PGM_GST_TYPE PGM_TYPE_PROT
99	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
100	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
101	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
102	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
103	#include "PGMGstDefs.h"
104	#include "PGMAllGst.h"
105	#include "PGMAllBth.h"
106	#undef BTH_PGMPOOLKIND_PT_FOR_PT
107	#undef BTH_PGMPOOLKIND_ROOT
108	#undef PGM_BTH_NAME
109	#undef PGM_GST_TYPE
110	#undef PGM_GST_NAME
111
112	/* Guest - 32-bit mode */
113	#define PGM_GST_TYPE PGM_TYPE_32BIT
114	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
115	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
116	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
117	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
118	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD
119	#include "PGMGstDefs.h"
120	#include "PGMAllGst.h"
121	#include "PGMAllBth.h"
122	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
123	#undef BTH_PGMPOOLKIND_PT_FOR_PT
124	#undef BTH_PGMPOOLKIND_ROOT
125	#undef PGM_BTH_NAME
126	#undef PGM_GST_TYPE
127	#undef PGM_GST_NAME
128
129	#undef PGM_SHW_TYPE
130	#undef PGM_SHW_NAME
131
132
133	/*
134	* Shadow - PAE mode
135	*/
136	#define PGM_SHW_TYPE PGM_TYPE_PAE
137	#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
138	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
139	#include "PGMAllShw.h"
140
141	/* Guest - real mode */
142	#define PGM_GST_TYPE PGM_TYPE_REAL
143	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
144	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
145	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
146	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
147	#include "PGMGstDefs.h"
148	#include "PGMAllBth.h"
149	#undef BTH_PGMPOOLKIND_PT_FOR_PT
150	#undef BTH_PGMPOOLKIND_ROOT
151	#undef PGM_BTH_NAME
152	#undef PGM_GST_TYPE
153	#undef PGM_GST_NAME
154
155	/* Guest - protected mode */
156	#define PGM_GST_TYPE PGM_TYPE_PROT
157	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
158	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
159	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
160	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
161	#include "PGMGstDefs.h"
162	#include "PGMAllBth.h"
163	#undef BTH_PGMPOOLKIND_PT_FOR_PT
164	#undef BTH_PGMPOOLKIND_ROOT
165	#undef PGM_BTH_NAME
166	#undef PGM_GST_TYPE
167	#undef PGM_GST_NAME
168
169	/* Guest - 32-bit mode */
170	#define PGM_GST_TYPE PGM_TYPE_32BIT
171	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
172	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
173	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
174	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
175	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_FOR_32BIT
176	#include "PGMGstDefs.h"
177	#include "PGMAllBth.h"
178	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
179	#undef BTH_PGMPOOLKIND_PT_FOR_PT
180	#undef BTH_PGMPOOLKIND_ROOT
181	#undef PGM_BTH_NAME
182	#undef PGM_GST_TYPE
183	#undef PGM_GST_NAME
184
185
186	/* Guest - PAE mode */
187	#define PGM_GST_TYPE PGM_TYPE_PAE
188	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
189	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
190	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
191	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
192	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT
193	#include "PGMGstDefs.h"
194	#include "PGMAllGst.h"
195	#include "PGMAllBth.h"
196	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
197	#undef BTH_PGMPOOLKIND_PT_FOR_PT
198	#undef BTH_PGMPOOLKIND_ROOT
199	#undef PGM_BTH_NAME
200	#undef PGM_GST_TYPE
201	#undef PGM_GST_NAME
202
203	#undef PGM_SHW_TYPE
204	#undef PGM_SHW_NAME
205
206
207	#ifndef IN_RC /* AMD64 implies VT-x/AMD-V */
208	/*
209	* Shadow - AMD64 mode
210	*/
211	# define PGM_SHW_TYPE PGM_TYPE_AMD64
212	# define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
213	# include "PGMAllShw.h"
214
215	/* Guest - protected mode (only used for AMD-V nested paging in 64 bits mode) */
216	# define PGM_GST_TYPE PGM_TYPE_PROT
217	# define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
218	# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_PROT(name)
219	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
220	# define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PD_PHYS
221	# include "PGMGstDefs.h"
222	# include "PGMAllBth.h"
223	# undef BTH_PGMPOOLKIND_PT_FOR_PT
224	# undef BTH_PGMPOOLKIND_ROOT
225	# undef PGM_BTH_NAME
226	# undef PGM_GST_TYPE
227	# undef PGM_GST_NAME
228
229	# ifdef VBOX_WITH_64_BITS_GUESTS
230	/* Guest - AMD64 mode */
231	# define PGM_GST_TYPE PGM_TYPE_AMD64
232	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
233	# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
234	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
235	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
236	# define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_64BIT_PML4
237	# include "PGMGstDefs.h"
238	# include "PGMAllGst.h"
239	# include "PGMAllBth.h"
240	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
241	# undef BTH_PGMPOOLKIND_PT_FOR_PT
242	# undef BTH_PGMPOOLKIND_ROOT
243	# undef PGM_BTH_NAME
244	# undef PGM_GST_TYPE
245	# undef PGM_GST_NAME
246	# endif /* VBOX_WITH_64_BITS_GUESTS */
247
248	# undef PGM_SHW_TYPE
249	# undef PGM_SHW_NAME
250
251
252	/*
253	* Shadow - Nested paging mode
254	*/
255	# define PGM_SHW_TYPE PGM_TYPE_NESTED
256	# define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED(name)
257	# include "PGMAllShw.h"
258
259	/* Guest - real mode */
260	# define PGM_GST_TYPE PGM_TYPE_REAL
261	# define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
262	# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_REAL(name)
263	# include "PGMGstDefs.h"
264	# include "PGMAllBth.h"
265	# undef PGM_BTH_NAME
266	# undef PGM_GST_TYPE
267	# undef PGM_GST_NAME
268
269	/* Guest - protected mode */
270	# define PGM_GST_TYPE PGM_TYPE_PROT
271	# define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
272	# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PROT(name)
273	# include "PGMGstDefs.h"
274	# include "PGMAllBth.h"
275	# undef PGM_BTH_NAME
276	# undef PGM_GST_TYPE
277	# undef PGM_GST_NAME
278
279	/* Guest - 32-bit mode */
280	# define PGM_GST_TYPE PGM_TYPE_32BIT
281	# define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
282	# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT(name)
283	# include "PGMGstDefs.h"
284	# include "PGMAllBth.h"
285	# undef PGM_BTH_NAME
286	# undef PGM_GST_TYPE
287	# undef PGM_GST_NAME
288
289	/* Guest - PAE mode */
290	# define PGM_GST_TYPE PGM_TYPE_PAE
291	# define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
292	# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE(name)
293	# include "PGMGstDefs.h"
294	# include "PGMAllBth.h"
295	# undef PGM_BTH_NAME
296	# undef PGM_GST_TYPE
297	# undef PGM_GST_NAME
298
299	# ifdef VBOX_WITH_64_BITS_GUESTS
300	/* Guest - AMD64 mode */
301	# define PGM_GST_TYPE PGM_TYPE_AMD64
302	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
303	# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64(name)
304	# include "PGMGstDefs.h"
305	# include "PGMAllBth.h"
306	# undef PGM_BTH_NAME
307	# undef PGM_GST_TYPE
308	# undef PGM_GST_NAME
309	# endif /* VBOX_WITH_64_BITS_GUESTS */
310
311	# undef PGM_SHW_TYPE
312	# undef PGM_SHW_NAME
313
314
315	/*
316	* Shadow - EPT
317	*/
318	# define PGM_SHW_TYPE PGM_TYPE_EPT
319	# define PGM_SHW_NAME(name) PGM_SHW_NAME_EPT(name)
320	# include "PGMAllShw.h"
321
322	/* Guest - real mode */
323	# define PGM_GST_TYPE PGM_TYPE_REAL
324	# define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
325	# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_REAL(name)
326	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
327	# include "PGMGstDefs.h"
328	# include "PGMAllBth.h"
329	# undef BTH_PGMPOOLKIND_PT_FOR_PT
330	# undef PGM_BTH_NAME
331	# undef PGM_GST_TYPE
332	# undef PGM_GST_NAME
333
334	/* Guest - protected mode */
335	# define PGM_GST_TYPE PGM_TYPE_PROT
336	# define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
337	# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PROT(name)
338	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
339	# include "PGMGstDefs.h"
340	# include "PGMAllBth.h"
341	# undef BTH_PGMPOOLKIND_PT_FOR_PT
342	# undef PGM_BTH_NAME
343	# undef PGM_GST_TYPE
344	# undef PGM_GST_NAME
345
346	/* Guest - 32-bit mode */
347	# define PGM_GST_TYPE PGM_TYPE_32BIT
348	# define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
349	# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_32BIT(name)
350	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
351	# include "PGMGstDefs.h"
352	# include "PGMAllBth.h"
353	# undef BTH_PGMPOOLKIND_PT_FOR_PT
354	# undef PGM_BTH_NAME
355	# undef PGM_GST_TYPE
356	# undef PGM_GST_NAME
357
358	/* Guest - PAE mode */
359	# define PGM_GST_TYPE PGM_TYPE_PAE
360	# define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
361	# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PAE(name)
362	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
363	# include "PGMGstDefs.h"
364	# include "PGMAllBth.h"
365	# undef BTH_PGMPOOLKIND_PT_FOR_PT
366	# undef PGM_BTH_NAME
367	# undef PGM_GST_TYPE
368	# undef PGM_GST_NAME
369
370	# ifdef VBOX_WITH_64_BITS_GUESTS
371	/* Guest - AMD64 mode */
372	# define PGM_GST_TYPE PGM_TYPE_AMD64
373	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
374	# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_AMD64(name)
375	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
376	# include "PGMGstDefs.h"
377	# include "PGMAllBth.h"
378	# undef BTH_PGMPOOLKIND_PT_FOR_PT
379	# undef PGM_BTH_NAME
380	# undef PGM_GST_TYPE
381	# undef PGM_GST_NAME
382	# endif /* VBOX_WITH_64_BITS_GUESTS */
383
384	# undef PGM_SHW_TYPE
385	# undef PGM_SHW_NAME
386
387	#endif /* !IN_RC */
388
389
390	#ifndef IN_RING3
391	/**
392	* #PF Handler.
393	*
394	* @returns VBox status code (appropriate for trap handling and GC return).
395	* @param pVM VM Handle.
396	* @param uErr The trap error code.
397	* @param pRegFrame Trap register frame.
398	* @param pvFault The fault address.
399	*/
400	VMMDECL(int) PGMTrap0eHandler(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
401	{
402	LogFlow(("PGMTrap0eHandler: uErr=%RGu pvFault=%RGv eip=%RGv\n", uErr, pvFault, (RTGCPTR)pRegFrame->rip));
403	STAM_PROFILE_START(&pVM->pgm.s.StatRZTrap0e, a);
404	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = NULL; } );
405
406
407	#ifdef VBOX_WITH_STATISTICS
408	/*
409	* Error code stats.
410	*/
411	if (uErr & X86_TRAP_PF_US)
412	{
413	if (!(uErr & X86_TRAP_PF_P))
414	{
415	if (uErr & X86_TRAP_PF_RW)
416	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eUSNotPresentWrite);
417	else
418	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eUSNotPresentRead);
419	}
420	else if (uErr & X86_TRAP_PF_RW)
421	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eUSWrite);
422	else if (uErr & X86_TRAP_PF_RSVD)
423	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eUSReserved);
424	else if (uErr & X86_TRAP_PF_ID)
425	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eUSNXE);
426	else
427	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eUSRead);
428	}
429	else
430	{ /* Supervisor */
431	if (!(uErr & X86_TRAP_PF_P))
432	{
433	if (uErr & X86_TRAP_PF_RW)
434	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eSVNotPresentWrite);
435	else
436	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eSVNotPresentRead);
437	}
438	else if (uErr & X86_TRAP_PF_RW)
439	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eSVWrite);
440	else if (uErr & X86_TRAP_PF_ID)
441	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eSNXE);
442	else if (uErr & X86_TRAP_PF_RSVD)
443	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eSVReserved);
444	}
445	#endif /* VBOX_WITH_STATISTICS */
446
447	/*
448	* Call the worker.
449	*/
450	int rc = PGM_BTH_PFN(Trap0eHandler, pVM)(pVM, uErr, pRegFrame, pvFault);
451	if (rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
452	rc = VINF_SUCCESS;
453	STAM_STATS({ if (rc == VINF_EM_RAW_GUEST_TRAP) STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eGuestPF); });
454	STAM_STATS({ if (!pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution))
455	pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2Misc; });
456	STAM_PROFILE_STOP_EX(&pVM->pgm.s.StatRZTrap0e, pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution), a);
457	return rc;
458	}
459	#endif /* !IN_RING3 */
460
461
462	/**
463	* Prefetch a page
464	*
465	* Typically used to sync commonly used pages before entering raw mode
466	* after a CR3 reload.
467	*
468	* @returns VBox status code suitable for scheduling.
469	* @retval VINF_SUCCESS on success.
470	* @retval VINF_PGM_SYNC_CR3 if we're out of shadow pages or something like that.
471	* @param pVM VM handle.
472	* @param GCPtrPage Page to invalidate.
473	*/
474	VMMDECL(int) PGMPrefetchPage(PVM pVM, RTGCPTR GCPtrPage)
475	{
476	STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,Prefetch), a);
477	int rc = PGM_BTH_PFN(PrefetchPage, pVM)(pVM, GCPtrPage);
478	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,Prefetch), a);
479	AssertMsg(rc == VINF_SUCCESS \|\| rc == VINF_PGM_SYNC_CR3 \|\| RT_FAILURE(rc), ("rc=%Rrc\n", rc));
480	return rc;
481	}
482
483
484	/**
485	* Gets the mapping corresponding to the specified address (if any).
486	*
487	* @returns Pointer to the mapping.
488	* @returns NULL if not
489	*
490	* @param pVM The virtual machine.
491	* @param GCPtr The guest context pointer.
492	*/
493	PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr)
494	{
495	PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
496	while (pMapping)
497	{
498	if ((uintptr_t)GCPtr < (uintptr_t)pMapping->GCPtr)
499	break;
500	if ((uintptr_t)GCPtr - (uintptr_t)pMapping->GCPtr < pMapping->cb)
501	return pMapping;
502	pMapping = pMapping->CTX_SUFF(pNext);
503	}
504	return NULL;
505	}
506
507
508	/**
509	* Verifies a range of pages for read or write access
510	*
511	* Only checks the guest's page tables
512	*
513	* @returns VBox status code.
514	* @param pVM VM handle.
515	* @param Addr Guest virtual address to check
516	* @param cbSize Access size
517	* @param fAccess Access type (r/w, user/supervisor (X86_PTE_*))
518	* @remarks Current not in use.
519	*/
520	VMMDECL(int) PGMIsValidAccess(PVM pVM, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess)
521	{
522	/*
523	* Validate input.
524	*/
525	if (fAccess & ~(X86_PTE_US \| X86_PTE_RW))
526	{
527	AssertMsgFailed(("PGMIsValidAccess: invalid access type %08x\n", fAccess));
528	return VERR_INVALID_PARAMETER;
529	}
530
531	uint64_t fPage;
532	int rc = PGMGstGetPage(pVM, (RTGCPTR)Addr, &fPage, NULL);
533	if (RT_FAILURE(rc))
534	{
535	Log(("PGMIsValidAccess: access violation for %RGv rc=%d\n", Addr, rc));
536	return VINF_EM_RAW_GUEST_TRAP;
537	}
538
539	/*
540	* Check if the access would cause a page fault
541	*
542	* Note that hypervisor page directories are not present in the guest's tables, so this check
543	* is sufficient.
544	*/
545	bool fWrite = !!(fAccess & X86_PTE_RW);
546	bool fUser = !!(fAccess & X86_PTE_US);
547	if ( !(fPage & X86_PTE_P)
548	\|\| (fWrite && !(fPage & X86_PTE_RW))
549	\|\| (fUser && !(fPage & X86_PTE_US)) )
550	{
551	Log(("PGMIsValidAccess: access violation for %RGv attr %#llx vs %d:%d\n", Addr, fPage, fWrite, fUser));
552	return VINF_EM_RAW_GUEST_TRAP;
553	}
554	if ( RT_SUCCESS(rc)
555	&& PAGE_ADDRESS(Addr) != PAGE_ADDRESS(Addr + cbSize))
556	return PGMIsValidAccess(pVM, Addr + PAGE_SIZE, (cbSize > PAGE_SIZE) ? cbSize - PAGE_SIZE : 1, fAccess);
557	return rc;
558	}
559
560
561	/**
562	* Verifies a range of pages for read or write access
563	*
564	* Supports handling of pages marked for dirty bit tracking and CSAM
565	*
566	* @returns VBox status code.
567	* @param pVM VM handle.
568	* @param Addr Guest virtual address to check
569	* @param cbSize Access size
570	* @param fAccess Access type (r/w, user/supervisor (X86_PTE_*))
571	*/
572	VMMDECL(int) PGMVerifyAccess(PVM pVM, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess)
573	{
574	AssertMsg(!(fAccess & ~(X86_PTE_US \| X86_PTE_RW)), ("PGMVerifyAccess: invalid access type %08x\n", fAccess));
575
576	/*
577	* Get going.
578	*/
579	uint64_t fPageGst;
580	int rc = PGMGstGetPage(pVM, (RTGCPTR)Addr, &fPageGst, NULL);
581	if (RT_FAILURE(rc))
582	{
583	Log(("PGMVerifyAccess: access violation for %RGv rc=%d\n", Addr, rc));
584	return VINF_EM_RAW_GUEST_TRAP;
585	}
586
587	/*
588	* Check if the access would cause a page fault
589	*
590	* Note that hypervisor page directories are not present in the guest's tables, so this check
591	* is sufficient.
592	*/
593	const bool fWrite = !!(fAccess & X86_PTE_RW);
594	const bool fUser = !!(fAccess & X86_PTE_US);
595	if ( !(fPageGst & X86_PTE_P)
596	\|\| (fWrite && !(fPageGst & X86_PTE_RW))
597	\|\| (fUser && !(fPageGst & X86_PTE_US)) )
598	{
599	Log(("PGMVerifyAccess: access violation for %RGv attr %#llx vs %d:%d\n", Addr, fPageGst, fWrite, fUser));
600	return VINF_EM_RAW_GUEST_TRAP;
601	}
602
603	if (!HWACCMIsNestedPagingActive(pVM))
604	{
605	/*
606	* Next step is to verify if we protected this page for dirty bit tracking or for CSAM scanning
607	*/
608	rc = PGMShwGetPage(pVM, (RTGCPTR)Addr, NULL, NULL);
609	if ( rc == VERR_PAGE_NOT_PRESENT
610	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT)
611	{
612	/*
613	* Page is not present in our page tables.
614	* Try to sync it!
615	*/
616	Assert(X86_TRAP_PF_RW == X86_PTE_RW && X86_TRAP_PF_US == X86_PTE_US);
617	uint32_t uErr = fAccess & (X86_TRAP_PF_RW \| X86_TRAP_PF_US);
618	rc = PGM_BTH_PFN(VerifyAccessSyncPage, pVM)(pVM, Addr, fPageGst, uErr);
619	if (rc != VINF_SUCCESS)
620	return rc;
621	}
622	else
623	AssertMsg(rc == VINF_SUCCESS, ("PGMShwGetPage %RGv failed with %Rrc\n", Addr, rc));
624	}
625
626	#if 0 /* def VBOX_STRICT; triggers too often now */
627	/*
628	* This check is a bit paranoid, but useful.
629	*/
630	/** @note this will assert when writing to monitored pages (a bit annoying actually) */
631	uint64_t fPageShw;
632	rc = PGMShwGetPage(pVM, (RTGCPTR)Addr, &fPageShw, NULL);
633	if ( (rc == VERR_PAGE_NOT_PRESENT \|\| RT_FAILURE(rc))
634	\|\| (fWrite && !(fPageShw & X86_PTE_RW))
635	\|\| (fUser && !(fPageShw & X86_PTE_US)) )
636	{
637	AssertMsgFailed(("Unexpected access violation for %RGv! rc=%Rrc write=%d user=%d\n",
638	Addr, rc, fWrite && !(fPageShw & X86_PTE_RW), fUser && !(fPageShw & X86_PTE_US)));
639	return VINF_EM_RAW_GUEST_TRAP;
640	}
641	#endif
642
643	if ( RT_SUCCESS(rc)
644	&& ( PAGE_ADDRESS(Addr) != PAGE_ADDRESS(Addr + cbSize - 1)
645	\|\| Addr + cbSize < Addr))
646	{
647	/* Don't recursively call PGMVerifyAccess as we might run out of stack. */
648	for (;;)
649	{
650	Addr += PAGE_SIZE;
651	if (cbSize > PAGE_SIZE)
652	cbSize -= PAGE_SIZE;
653	else
654	cbSize = 1;
655	rc = PGMVerifyAccess(pVM, Addr, 1, fAccess);
656	if (rc != VINF_SUCCESS)
657	break;
658	if (PAGE_ADDRESS(Addr) == PAGE_ADDRESS(Addr + cbSize - 1))
659	break;
660	}
661	}
662	return rc;
663	}
664
665
666	/**
667	* Emulation of the invlpg instruction (HC only actually).
668	*
669	* @returns VBox status code, special care required.
670	* @retval VINF_PGM_SYNC_CR3 - handled.
671	* @retval VINF_EM_RAW_EMULATE_INSTR - not handled (RC only).
672	* @retval VERR_REM_FLUSHED_PAGES_OVERFLOW - not handled.
673	*
674	* @param pVM VM handle.
675	* @param GCPtrPage Page to invalidate.
676	*
677	* @remark ASSUMES the page table entry or page directory is valid. Fairly
678	* safe, but there could be edge cases!
679	*
680	* @todo Flush page or page directory only if necessary!
681	*/
682	VMMDECL(int) PGMInvalidatePage(PVM pVM, RTGCPTR GCPtrPage)
683	{
684	int rc;
685	Log3(("PGMInvalidatePage: GCPtrPage=%RGv\n", GCPtrPage));
686
687	#ifndef IN_RING3
688	/*
689	* Notify the recompiler so it can record this instruction.
690	* Failure happens when it's out of space. We'll return to HC in that case.
691	*/
692	rc = REMNotifyInvalidatePage(pVM, GCPtrPage);
693	if (rc != VINF_SUCCESS)
694	return rc;
695	#endif /* !IN_RING3 */
696
697
698	#ifdef IN_RC
699	/*
700	* Check for conflicts and pending CR3 monitoring updates.
701	*/
702	if (!pVM->pgm.s.fMappingsFixed)
703	{
704	if ( pgmGetMapping(pVM, GCPtrPage)
705	&& PGMGstGetPage(pVM, GCPtrPage, NULL, NULL) != VERR_PAGE_TABLE_NOT_PRESENT)
706	{
707	LogFlow(("PGMGCInvalidatePage: Conflict!\n"));
708	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
709	STAM_COUNTER_INC(&pVM->pgm.s.StatRCInvlPgConflict);
710	return VINF_PGM_SYNC_CR3;
711	}
712
713	if (pVM->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
714	{
715	LogFlow(("PGMGCInvalidatePage: PGM_SYNC_MONITOR_CR3 -> reinterpret instruction in R3\n"));
716	STAM_COUNTER_INC(&pVM->pgm.s.StatRCInvlPgSyncMonCR3);
717	return VINF_EM_RAW_EMULATE_INSTR;
718	}
719	}
720	#endif /* IN_RC */
721
722	/*
723	* Call paging mode specific worker.
724	*/
725	STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePage), a);
726	rc = PGM_BTH_PFN(InvalidatePage, pVM)(pVM, GCPtrPage);
727	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePage), a);
728
729	#ifdef IN_RING3
730	/*
731	* Check if we have a pending update of the CR3 monitoring.
732	*/
733	if ( RT_SUCCESS(rc)
734	&& (pVM->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3))
735	{
736	pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
737	Assert(!pVM->pgm.s.fMappingsFixed);
738	}
739
740	/*
741	* Inform CSAM about the flush
742	*
743	* Note: This is to check if monitored pages have been changed; when we implement
744	* callbacks for virtual handlers, this is no longer required.
745	*/
746	CSAMR3FlushPage(pVM, GCPtrPage);
747	#endif /* IN_RING3 */
748	return rc;
749	}
750
751
752	/**
753	* Executes an instruction using the interpreter.
754	*
755	* @returns VBox status code (appropriate for trap handling and GC return).
756	* @param pVM VM handle.
757	* @param pRegFrame Register frame.
758	* @param pvFault Fault address.
759	*/
760	VMMDECL(int) PGMInterpretInstruction(PVM pVM, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
761	{
762	uint32_t cb;
763	int rc = EMInterpretInstruction(pVM, pRegFrame, pvFault, &cb);
764	if (rc == VERR_EM_INTERPRETER)
765	rc = VINF_EM_RAW_EMULATE_INSTR;
766	if (rc != VINF_SUCCESS)
767	Log(("PGMInterpretInstruction: returns %Rrc (pvFault=%RGv)\n", rc, pvFault));
768	return rc;
769	}
770
771
772	/**
773	* Gets effective page information (from the VMM page directory).
774	*
775	* @returns VBox status.
776	* @param pVM VM Handle.
777	* @param GCPtr Guest Context virtual address of the page.
778	* @param pfFlags Where to store the flags. These are X86_PTE_*.
779	* @param pHCPhys Where to store the HC physical address of the page.
780	* This is page aligned.
781	* @remark You should use PGMMapGetPage() for pages in a mapping.
782	*/
783	VMMDECL(int) PGMShwGetPage(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys)
784	{
785	return PGM_SHW_PFN(GetPage,pVM)(pVM, GCPtr, pfFlags, pHCPhys);
786	}
787
788
789	/**
790	* Sets (replaces) the page flags for a range of pages in the shadow context.
791	*
792	* @returns VBox status.
793	* @param pVM VM handle.
794	* @param GCPtr The address of the first page.
795	* @param cb The size of the range in bytes.
796	* @param fFlags Page flags X86_PTE_*, excluding the page mask of course.
797	* @remark You must use PGMMapSetPage() for pages in a mapping.
798	*/
799	VMMDECL(int) PGMShwSetPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags)
800	{
801	return PGMShwModifyPage(pVM, GCPtr, cb, fFlags, 0);
802	}
803
804
805	/**
806	* Modify page flags for a range of pages in the shadow context.
807	*
808	* The existing flags are ANDed with the fMask and ORed with the fFlags.
809	*
810	* @returns VBox status code.
811	* @param pVM VM handle.
812	* @param GCPtr Virtual address of the first page in the range.
813	* @param cb Size (in bytes) of the range to apply the modification to.
814	* @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
815	* @param fMask The AND mask - page flags X86_PTE_*.
816	* Be very CAREFUL when ~'ing constants which could be 32-bit!
817	* @remark You must use PGMMapModifyPage() for pages in a mapping.
818	*/
819	VMMDECL(int) PGMShwModifyPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
820	{
821	AssertMsg(!(fFlags & X86_PTE_PAE_PG_MASK), ("fFlags=%#llx\n", fFlags));
822	Assert(cb);
823
824	/*
825	* Align the input.
826	*/
827	cb += GCPtr & PAGE_OFFSET_MASK;
828	cb = RT_ALIGN_Z(cb, PAGE_SIZE);
829	GCPtr = (GCPtr & PAGE_BASE_GC_MASK); /** @todo this ain't necessary, right... */
830
831	/*
832	* Call worker.
833	*/
834	return PGM_SHW_PFN(ModifyPage, pVM)(pVM, GCPtr, cb, fFlags, fMask);
835	}
836
837
838	/**
839	* Gets the SHADOW page directory pointer for the specified address.
840	*
841	* @returns VBox status.
842	* @param pVM VM handle.
843	* @param GCPtr The address.
844	* @param ppPdpt Receives address of pdpt
845	* @param ppPD Receives address of page directory
846	* @remarks Unused.
847	*/
848	DECLINLINE(int) pgmShwGetPAEPDPtr(PVM pVM, RTGCPTR GCPtr, PX86PDPT ppPdpt, PX86PDPAE ppPD)
849	{
850	PPGM pPGM = &pVM->pgm.s;
851	PPGMPOOL pPool = pPGM->CTX_SUFF(pPool);
852	PPGMPOOLPAGE pShwPage;
853
854	Assert(!HWACCMIsNestedPagingActive(pVM));
855
856	const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
857	PX86PDPT pPdpt = pgmShwGetPaePDPTPtr(&pVM->pgm.s);
858	PX86PDPE pPdpe = &pPdpt->a[iPdPt];
859
860	*ppPdpt = pPdpt;
861	if (!pPdpe->n.u1Present)
862	return VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT;
863
864	Assert(pPdpe->u & X86_PDPE_PG_MASK);
865	pShwPage = pgmPoolGetPage(pPool, pPdpe->u & X86_PDPE_PG_MASK);
866	AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
867
868	*ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
869	return VINF_SUCCESS;
870	}
871
872	/**
873	* Gets the shadow page directory for the specified address, PAE.
874	*
875	* @returns Pointer to the shadow PD.
876	* @param pVM VM handle.
877	* @param GCPtr The address.
878	* @param pGstPdpe Guest PDPT entry
879	* @param ppPD Receives address of page directory
880	*/
881	int pgmShwSyncPaePDPtr(PVM pVM, RTGCPTR GCPtr, PX86PDPE pGstPdpe, PX86PDPAE *ppPD)
882	{
883	const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
884	PX86PDPT pPdpt = pgmShwGetPaePDPTPtr(&pVM->pgm.s);
885	PX86PDPE pPdpe = &pPdpt->a[iPdPt];
886	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
887	PPGMPOOLPAGE pShwPage;
888	int rc;
889
890	/* Allocate page directory if not present. */
891	if ( !pPdpe->n.u1Present
892	&& !(pPdpe->u & X86_PDPE_PG_MASK))
893	{
894	bool fNestedPaging = HWACCMIsNestedPagingActive(pVM);
895	bool fPaging = !!(CPUMGetGuestCR0(pVM) & X86_CR0_PG);
896	RTGCPTR64 GCPdPt;
897	PGMPOOLKIND enmKind;
898
899	# if defined(IN_RC)
900	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
901	PGMDynLockHCPage(pVM, (uint8_t *)pPdpe);
902	# endif
903
904	if (fNestedPaging \|\| !fPaging)
905	{
906	/* AMD-V nested paging or real/protected mode without paging */
907	GCPdPt = (RTGCPTR64)iPdPt << X86_PDPT_SHIFT;
908	enmKind = PGMPOOLKIND_PAE_PD_PHYS;
909	}
910	else
911	{
912	Assert(pGstPdpe);
913
914	if (CPUMGetGuestCR4(pVM) & X86_CR4_PAE)
915	{
916	if (!pGstPdpe->n.u1Present)
917	{
918	/* PD not present; guest must reload CR3 to change it.
919	* No need to monitor anything in this case.
920	*/
921	Assert(!HWACCMIsEnabled(pVM));
922
923	GCPdPt = pGstPdpe->u & X86_PDPE_PG_MASK;
924	enmKind = PGMPOOLKIND_PAE_PD_PHYS;
925	pGstPdpe->n.u1Present = 1;
926	}
927	else
928	{
929	GCPdPt = pGstPdpe->u & X86_PDPE_PG_MASK;
930	enmKind = PGMPOOLKIND_PAE_PD_FOR_PAE_PD;
931	}
932	}
933	else
934	{
935	GCPdPt = CPUMGetGuestCR3(pVM);
936	enmKind = (PGMPOOLKIND)(PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD + iPdPt);
937	}
938	}
939
940	/* Create a reference back to the PDPT by using the index in its shadow page. */
941	rc = pgmPoolAlloc(pVM, GCPdPt, enmKind, pVM->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPdPt, &pShwPage);
942	AssertRCReturn(rc, rc);
943
944	/* The PD was cached or created; hook it up now. */
945	pPdpe->u \|= pShwPage->Core.Key
946	\| (pGstPdpe->u & ~(X86_PDPE_PG_MASK \| X86_PDPE_AVL_MASK \| X86_PDPE_PCD \| X86_PDPE_PWT));
947
948	# if defined(IN_RC)
949	/* In 32 bits PAE mode we must invalidate the TLB when changing a PDPT entry; the CPU fetches them only during cr3 load, so any
950	* non-present PDPT will continue to cause page faults.
951	*/
952	ASMReloadCR3();
953	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdpe);
954	# endif
955	}
956	else
957	{
958	pShwPage = pgmPoolGetPage(pPool, pPdpe->u & X86_PDPE_PG_MASK);
959	AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
960
961	Assert((pPdpe->u & X86_PDPE_PG_MASK) == pShwPage->Core.Key);
962	}
963	*ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
964	return VINF_SUCCESS;
965	}
966
967
968	/**
969	* Gets the pointer to the shadow page directory entry for an address, PAE.
970	*
971	* @returns Pointer to the PDE.
972	* @param pPGM Pointer to the PGM instance data.
973	* @param GCPtr The address.
974	* @param ppShwPde Receives the address of the pgm pool page for the shadow page directory
975	*/
976	DECLINLINE(int) pgmShwGetPaePoolPagePD(PPGM pPGM, RTGCPTR GCPtr, PPGMPOOLPAGE *ppShwPde)
977	{
978	const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
979	PX86PDPT pPdpt = pgmShwGetPaePDPTPtr(pPGM);
980	AssertReturn(pPdpt, VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT); /* can't happen */
981	if (!pPdpt->a[iPdPt].n.u1Present)
982	{
983	LogFlow(("pgmShwGetPaePoolPagePD: PD %d not present (%RX64)\n", iPdPt, pPdpt->a[iPdPt].u));
984	return VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT;
985	}
986	AssertMsg(pPdpt->a[iPdPt].u & X86_PDPE_PG_MASK, ("GCPtr=%RGv\n", GCPtr));
987
988	/* Fetch the pgm pool shadow descriptor. */
989	PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(PGM2VM(pPGM), pPdpt->a[iPdPt].u & X86_PDPE_PG_MASK);
990	AssertReturn(pShwPde, VERR_INTERNAL_ERROR);
991
992	*ppShwPde = pShwPde;
993	return VINF_SUCCESS;
994	}
995
996	#ifndef IN_RC
997
998	/**
999	* Syncs the SHADOW page directory pointer for the specified address.
1000	*
1001	* Allocates backing pages in case the PDPT or PML4 entry is missing.
1002	*
1003	* The caller is responsible for making sure the guest has a valid PD before
1004	* calling this function.
1005	*
1006	* @returns VBox status.
1007	* @param pVM VM handle.
1008	* @param GCPtr The address.
1009	* @param pGstPml4e Guest PML4 entry
1010	* @param pGstPdpe Guest PDPT entry
1011	* @param ppPD Receives address of page directory
1012	*/
1013	int pgmShwSyncLongModePDPtr(PVM pVM, RTGCPTR64 GCPtr, PX86PML4E pGstPml4e, PX86PDPE pGstPdpe, PX86PDPAE *ppPD)
1014	{
1015	PPGM pPGM = &pVM->pgm.s;
1016	PPGMPOOL pPool = pPGM->CTX_SUFF(pPool);
1017	const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
1018	PX86PML4E pPml4e = pgmShwGetLongModePML4EPtr(pPGM, iPml4);
1019	bool fNestedPaging = HWACCMIsNestedPagingActive(pVM);
1020	bool fPaging = !!(CPUMGetGuestCR0(pVM) & X86_CR0_PG);
1021	PPGMPOOLPAGE pShwPage;
1022	int rc;
1023
1024	/* Allocate page directory pointer table if not present. */
1025	if ( !pPml4e->n.u1Present
1026	&& !(pPml4e->u & X86_PML4E_PG_MASK))
1027	{
1028	RTGCPTR64 GCPml4;
1029	PGMPOOLKIND enmKind;
1030
1031	Assert(pVM->pgm.s.CTX_SUFF(pShwPageCR3));
1032
1033	if (fNestedPaging \|\| !fPaging)
1034	{
1035	/* AMD-V nested paging or real/protected mode without paging */
1036	GCPml4 = (RTGCPTR64)iPml4 << X86_PML4_SHIFT;
1037	enmKind = PGMPOOLKIND_64BIT_PDPT_FOR_PHYS;
1038	}
1039	else
1040	{
1041	Assert(pGstPml4e && pGstPdpe);
1042
1043	GCPml4 = pGstPml4e->u & X86_PML4E_PG_MASK;
1044	enmKind = PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT;
1045	}
1046
1047	/* Create a reference back to the PDPT by using the index in its shadow page. */
1048	rc = pgmPoolAlloc(pVM, GCPml4, enmKind, pVM->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPml4, &pShwPage);
1049	AssertRCReturn(rc, rc);
1050	}
1051	else
1052	{
1053	pShwPage = pgmPoolGetPage(pPool, pPml4e->u & X86_PML4E_PG_MASK);
1054	AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1055	}
1056	/* The PDPT was cached or created; hook it up now. */
1057	pPml4e->u \|= pShwPage->Core.Key
1058	\| (pGstPml4e->u & ~(X86_PML4E_PG_MASK \| X86_PML4E_AVL_MASK \| X86_PML4E_PCD \| X86_PML4E_PWT));
1059
1060	const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1061	PX86PDPT pPdpt = (PX86PDPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1062	PX86PDPE pPdpe = &pPdpt->a[iPdPt];
1063
1064	/* Allocate page directory if not present. */
1065	if ( !pPdpe->n.u1Present
1066	&& !(pPdpe->u & X86_PDPE_PG_MASK))
1067	{
1068	RTGCPTR64 GCPdPt;
1069	PGMPOOLKIND enmKind;
1070
1071	if (fNestedPaging \|\| !fPaging)
1072	{
1073	/* AMD-V nested paging or real/protected mode without paging */
1074	GCPdPt = (RTGCPTR64)iPdPt << X86_PDPT_SHIFT;
1075	enmKind = PGMPOOLKIND_64BIT_PD_FOR_PHYS;
1076	}
1077	else
1078	{
1079	Assert(pGstPdpe);
1080
1081	GCPdPt = pGstPdpe->u & X86_PDPE_PG_MASK;
1082	enmKind = PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD;
1083	}
1084
1085	/* Create a reference back to the PDPT by using the index in its shadow page. */
1086	rc = pgmPoolAlloc(pVM, GCPdPt, enmKind, pShwPage->idx, iPdPt, &pShwPage);
1087	AssertRCReturn(rc, rc);
1088	}
1089	else
1090	{
1091	pShwPage = pgmPoolGetPage(pPool, pPdpe->u & X86_PDPE_PG_MASK);
1092	AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1093	}
1094	/* The PD was cached or created; hook it up now. */
1095	pPdpe->u \|= pShwPage->Core.Key
1096	\| (pGstPdpe->u & ~(X86_PDPE_PG_MASK \| X86_PDPE_AVL_MASK \| X86_PDPE_PCD \| X86_PDPE_PWT));
1097
1098	*ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1099	return VINF_SUCCESS;
1100	}
1101
1102
1103	/**
1104	* Gets the SHADOW page directory pointer for the specified address (long mode).
1105	*
1106	* @returns VBox status.
1107	* @param pVM VM handle.
1108	* @param GCPtr The address.
1109	* @param ppPdpt Receives address of pdpt
1110	* @param ppPD Receives address of page directory
1111	*/
1112	DECLINLINE(int) pgmShwGetLongModePDPtr(PVM pVM, RTGCPTR64 GCPtr, PX86PML4E ppPml4e, PX86PDPT ppPdpt, PX86PDPAE *ppPD)
1113	{
1114	PPGM pPGM = &pVM->pgm.s;
1115	const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
1116	PCX86PML4E pPml4e = pgmShwGetLongModePML4EPtr(pPGM, iPml4);
1117	AssertReturn(pPml4e, VERR_INTERNAL_ERROR);
1118	if (ppPml4e)
1119	*ppPml4e = (PX86PML4E)pPml4e;
1120	if (!pPml4e->n.u1Present)
1121	return VERR_PAGE_MAP_LEVEL4_NOT_PRESENT;
1122
1123	PPGMPOOL pPool = pPGM->CTX_SUFF(pPool);
1124	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPml4e->u & X86_PML4E_PG_MASK);
1125	AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1126
1127	const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1128	PCX86PDPT pPdpt = *ppPdpt = (PX86PDPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1129	if (!pPdpt->a[iPdPt].n.u1Present)
1130	return VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT;
1131
1132	pShwPage = pgmPoolGetPage(pPool, pPdpt->a[iPdPt].u & X86_PDPE_PG_MASK);
1133	AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1134
1135	*ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1136	return VINF_SUCCESS;
1137	}
1138
1139
1140	/**
1141	* Syncs the SHADOW EPT page directory pointer for the specified address. Allocates
1142	* backing pages in case the PDPT or PML4 entry is missing.
1143	*
1144	* @returns VBox status.
1145	* @param pVM VM handle.
1146	* @param GCPtr The address.
1147	* @param ppPdpt Receives address of pdpt
1148	* @param ppPD Receives address of page directory
1149	*/
1150	int pgmShwGetEPTPDPtr(PVM pVM, RTGCPTR64 GCPtr, PEPTPDPT ppPdpt, PEPTPD ppPD)
1151	{
1152	PPGM pPGM = &pVM->pgm.s;
1153	const unsigned iPml4 = (GCPtr >> EPT_PML4_SHIFT) & EPT_PML4_MASK;
1154	PPGMPOOL pPool = pPGM->CTX_SUFF(pPool);
1155	PEPTPML4 pPml4;
1156	PEPTPML4E pPml4e;
1157	PPGMPOOLPAGE pShwPage;
1158	int rc;
1159
1160	Assert(HWACCMIsNestedPagingActive(pVM));
1161
1162	pPml4 = (PEPTPML4)PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
1163	Assert(pPml4);
1164
1165	/* Allocate page directory pointer table if not present. */
1166	pPml4e = &pPml4->a[iPml4];
1167	if ( !pPml4e->n.u1Present
1168	&& !(pPml4e->u & EPT_PML4E_PG_MASK))
1169	{
1170	Assert(!(pPml4e->u & EPT_PML4E_PG_MASK));
1171	RTGCPTR64 GCPml4 = (RTGCPTR64)iPml4 << EPT_PML4_SHIFT;
1172
1173	rc = pgmPoolAlloc(pVM, GCPml4, PGMPOOLKIND_EPT_PDPT_FOR_PHYS, PGMPOOL_IDX_NESTED_ROOT, iPml4, &pShwPage);
1174	AssertRCReturn(rc, rc);
1175	}
1176	else
1177	{
1178	pShwPage = pgmPoolGetPage(pPool, pPml4e->u & EPT_PML4E_PG_MASK);
1179	AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1180	}
1181	/* The PDPT was cached or created; hook it up now and fill with the default value. */
1182	pPml4e->u = pShwPage->Core.Key;
1183	pPml4e->n.u1Present = 1;
1184	pPml4e->n.u1Write = 1;
1185	pPml4e->n.u1Execute = 1;
1186
1187	const unsigned iPdPt = (GCPtr >> EPT_PDPT_SHIFT) & EPT_PDPT_MASK;
1188	PEPTPDPT pPdpt = (PEPTPDPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1189	PEPTPDPTE pPdpe = &pPdpt->a[iPdPt];
1190
1191	if (ppPdpt)
1192	*ppPdpt = pPdpt;
1193
1194	/* Allocate page directory if not present. */
1195	if ( !pPdpe->n.u1Present
1196	&& !(pPdpe->u & EPT_PDPTE_PG_MASK))
1197	{
1198	RTGCPTR64 GCPdPt = (RTGCPTR64)iPdPt << EPT_PDPT_SHIFT;
1199
1200	rc = pgmPoolAlloc(pVM, GCPdPt, PGMPOOLKIND_64BIT_PD_FOR_PHYS, pShwPage->idx, iPdPt, &pShwPage);
1201	AssertRCReturn(rc, rc);
1202	}
1203	else
1204	{
1205	pShwPage = pgmPoolGetPage(pPool, pPdpe->u & EPT_PDPTE_PG_MASK);
1206	AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1207	}
1208	/* The PD was cached or created; hook it up now and fill with the default value. */
1209	pPdpe->u = pShwPage->Core.Key;
1210	pPdpe->n.u1Present = 1;
1211	pPdpe->n.u1Write = 1;
1212	pPdpe->n.u1Execute = 1;
1213
1214	*ppPD = (PEPTPD)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1215	return VINF_SUCCESS;
1216	}
1217
1218	#endif /* IN_RC */
1219
1220	/**
1221	* Gets effective Guest OS page information.
1222	*
1223	* When GCPtr is in a big page, the function will return as if it was a normal
1224	* 4KB page. If the need for distinguishing between big and normal page becomes
1225	* necessary at a later point, a PGMGstGetPage() will be created for that
1226	* purpose.
1227	*
1228	* @returns VBox status.
1229	* @param pVM VM Handle.
1230	* @param GCPtr Guest Context virtual address of the page.
1231	* @param pfFlags Where to store the flags. These are X86_PTE_*, even for big pages.
1232	* @param pGCPhys Where to store the GC physical address of the page.
1233	* This is page aligned. The fact that the
1234	*/
1235	VMMDECL(int) PGMGstGetPage(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys)
1236	{
1237	return PGM_GST_PFN(GetPage,pVM)(pVM, GCPtr, pfFlags, pGCPhys);
1238	}
1239
1240
1241	/**
1242	* Checks if the page is present.
1243	*
1244	* @returns true if the page is present.
1245	* @returns false if the page is not present.
1246	* @param pVM The VM handle.
1247	* @param GCPtr Address within the page.
1248	*/
1249	VMMDECL(bool) PGMGstIsPagePresent(PVM pVM, RTGCPTR GCPtr)
1250	{
1251	int rc = PGMGstGetPage(pVM, GCPtr, NULL, NULL);
1252	return RT_SUCCESS(rc);
1253	}
1254
1255
1256	/**
1257	* Sets (replaces) the page flags for a range of pages in the guest's tables.
1258	*
1259	* @returns VBox status.
1260	* @param pVM VM handle.
1261	* @param GCPtr The address of the first page.
1262	* @param cb The size of the range in bytes.
1263	* @param fFlags Page flags X86_PTE_*, excluding the page mask of course.
1264	*/
1265	VMMDECL(int) PGMGstSetPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags)
1266	{
1267	return PGMGstModifyPage(pVM, GCPtr, cb, fFlags, 0);
1268	}
1269
1270
1271	/**
1272	* Modify page flags for a range of pages in the guest's tables
1273	*
1274	* The existing flags are ANDed with the fMask and ORed with the fFlags.
1275	*
1276	* @returns VBox status code.
1277	* @param pVM VM handle.
1278	* @param GCPtr Virtual address of the first page in the range.
1279	* @param cb Size (in bytes) of the range to apply the modification to.
1280	* @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
1281	* @param fMask The AND mask - page flags X86_PTE_*, excluding the page mask of course.
1282	* Be very CAREFUL when ~'ing constants which could be 32-bit!
1283	*/
1284	VMMDECL(int) PGMGstModifyPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
1285	{
1286	STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,GstModifyPage), a);
1287
1288	/*
1289	* Validate input.
1290	*/
1291	AssertMsg(!(fFlags & X86_PTE_PAE_PG_MASK), ("fFlags=%#llx\n", fFlags));
1292	Assert(cb);
1293
1294	LogFlow(("PGMGstModifyPage %RGv %d bytes fFlags=%08llx fMask=%08llx\n", GCPtr, cb, fFlags, fMask));
1295
1296	/*
1297	* Adjust input.
1298	*/
1299	cb += GCPtr & PAGE_OFFSET_MASK;
1300	cb = RT_ALIGN_Z(cb, PAGE_SIZE);
1301	GCPtr = (GCPtr & PAGE_BASE_GC_MASK);
1302
1303	/*
1304	* Call worker.
1305	*/
1306	int rc = PGM_GST_PFN(ModifyPage, pVM)(pVM, GCPtr, cb, fFlags, fMask);
1307
1308	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,GstModifyPage), a);
1309	return rc;
1310	}
1311
1312	#ifdef VBOX_WITH_NEW_PHYS_CODE
1313	#ifdef IN_RING3
1314
1315	/**
1316	* Performs the lazy mapping of the 32-bit guest PD.
1317	*
1318	* @returns Pointer to the mapping.
1319	* @param pPGM The PGM instance data.
1320	*/
1321	PX86PD pgmGstLazyMap32BitPD(PPGM pPGM)
1322	{
1323	Assert(!pPGM->CTX_SUFF(pGst32BitPd));
1324	PVM pVM = PGM2VM(pPGM);
1325	pgmLock(pVM);
1326
1327	PPGMPAGE pPage = pgmPhysGetPage(pPGM, pPGM->GCPhysCR3);
1328	AssertReturn(pPage, NULL);
1329
1330	RTHCPTR HCPtrGuestCR3;
1331	int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, pPGM->GCPhysCR3 & X86_CR3_PAGE_MASK, (void **)&HCPtrGuestCR3);
1332	AssertRCReturn(rc, NULL);
1333
1334	pPGM->pGst32BitPdR3 = (R3PTRTYPE(PX86PD))HCPtrGuestCR3;
1335	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1336	pPGM->pGst32BitPdR0 = (R0PTRTYPE(PX86PD))HCPtrGuestCR3;
1337	# endif
1338
1339	pgmUnlock(pVM);
1340	return pPGM->CTX_SUFF(pGst32BitPd);
1341	}
1342
1343
1344	/**
1345	* Performs the lazy mapping of the PAE guest PDPT.
1346	*
1347	* @returns Pointer to the mapping.
1348	* @param pPGM The PGM instance data.
1349	*/
1350	PX86PDPT pgmGstLazyMapPaePDPT(PPGM pPGM)
1351	{
1352	Assert(!pPGM->CTX_SUFF(pGstPaePdpt));
1353	PVM pVM = PGM2VM(pPGM);
1354	pgmLock(pVM);
1355
1356	PPGMPAGE pPage = pgmPhysGetPage(pPGM, pPGM->GCPhysCR3);
1357	AssertReturn(pPage, NULL);
1358
1359	RTHCPTR HCPtrGuestCR3;
1360	int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, pPGM->GCPhysCR3 & X86_CR3_PAE_PAGE_MASK, (void **)&HCPtrGuestCR3);
1361	AssertRCReturn(rc, NULL);
1362
1363	pPGM->pGstPaePdptR3 = (R3PTRTYPE(PX86PDPT))HCPtrGuestCR3;
1364	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1365	pPGM->pGstPaePdptR0 = (R0PTRTYPE(PX86PDPT))HCPtrGuestCR3;
1366	# endif
1367
1368	pgmUnlock(pVM);
1369	return pPGM->CTX_SUFF(pGstPaePdpt);
1370	}
1371
1372	#endif /* IN_RING3 */
1373
1374	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
1375	/**
1376	* Performs the lazy mapping / updating of a PAE guest PD.
1377	*
1378	* @returns Pointer to the mapping.
1379	* @param pPGM The PGM instance data.
1380	* @param iPdpt Which PD entry to map (0..3).
1381	*/
1382	PX86PDPAE pgmGstLazyMapPaePD(PPGM pPGM, uint32_t iPdpt)
1383	{
1384	PVM pVM = PGM2VM(pPGM);
1385	pgmLock(pVM);
1386
1387	PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
1388	Assert(pGuestPDPT);
1389	Assert(pGuestPDPT->a[iPdpt].n.u1Present);
1390	RTGCPHYS GCPhys = pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK;
1391	bool const fChanged = pPGM->aGCPhysGstPaePDs[iPdpt] != GCPhys;
1392
1393	PPGMPAGE pPage = pgmPhysGetPage(pPGM, GCPhys);
1394	if (RT_LIKELY(pPage))
1395	{
1396	int rc = VINF_SUCCESS;
1397	RTRCPTR RCPtr = NIL_RTRCPTR;
1398	RTHCPTR HCPtr = NIL_RTHCPTR;
1399	#if !defined(IN_RC) && !defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1400	rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, &HCPtr);
1401	AssertRC(rc);
1402	#endif
1403	if (RT_SUCCESS(rc) && fChanged)
1404	{
1405	RCPtr = (RTRCPTR)(RTRCUINTPTR)(pPGM->GCPtrCR3Mapping + (1 + iPdpt) * PAGE_SIZE);
1406	rc = PGMMap(pVM, (RTRCUINTPTR)RCPtr, PGM_PAGE_GET_HCPHYS(pPage), PAGE_SIZE, 0);
1407	}
1408	if (RT_SUCCESS(rc))
1409	{
1410	pPGM->apGstPaePDsR3[iPdpt] = (R3PTRTYPE(PX86PDPAE))HCPtr;
1411	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1412	pPGM->apGstPaePDsR0[iPdpt] = (R0PTRTYPE(PX86PDPAE))HCPtr;
1413	# endif
1414	if (fChanged)
1415	{
1416	pPGM->aGCPhysGstPaePDs[iPdpt] = GCPhys;
1417	pPGM->apGstPaePDsRC[iPdpt] = (RCPTRTYPE(PX86PDPAE))RCPtr;
1418	}
1419
1420	pgmUnlock(pVM);
1421	return pPGM->CTX_SUFF(apGstPaePDs)[iPdpt];
1422	}
1423	}
1424
1425	/* Invalid page or some failure, invalidate the entry. */
1426	pPGM->aGCPhysGstPaePDs[iPdpt] = NIL_RTGCPHYS;
1427	pPGM->apGstPaePDsR3[iPdpt] = 0;
1428	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1429	pPGM->apGstPaePDsR0[iPdpt] = 0;
1430	# endif
1431	pPGM->apGstPaePDsRC[iPdpt] = 0;
1432
1433	pgmUnlock(pVM);
1434	return NULL;
1435	}
1436	#endif /* !VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
1437
1438
1439	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R3
1440	/**
1441	* Performs the lazy mapping of the 32-bit guest PD.
1442	*
1443	* @returns Pointer to the mapping.
1444	* @param pPGM The PGM instance data.
1445	*/
1446	PX86PML4 pgmGstLazyMapPml4(PPGM pPGM)
1447	{
1448	Assert(!pPGM->CTX_SUFF(pGstAmd64Pml4));
1449	PVM pVM = PGM2VM(pPGM);
1450	pgmLock(pVM);
1451
1452	PPGMPAGE pPage = pgmPhysGetPage(pPGM, pPGM->GCPhysCR3);
1453	AssertReturn(pPage, NULL);
1454
1455	RTHCPTR HCPtrGuestCR3;
1456	int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, pPGM->GCPhysCR3 & X86_CR3_AMD64_PAGE_MASK, (void **)&HCPtrGuestCR3);
1457	AssertRCReturn(rc, NULL);
1458
1459	pPGM->pGstAmd64Pml4R3 = (R3PTRTYPE(PX86PML4))HCPtrGuestCR3;
1460	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1461	pPGM->pGstAmd64Pml4R0 = (R0PTRTYPE(PX86PML4))HCPtrGuestCR3;
1462	# endif
1463
1464	pgmUnlock(pVM);
1465	return pPGM->CTX_SUFF(pGstAmd64Pml4);
1466	}
1467	#endif /* VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R3 */
1468
1469	#endif /* VBOX_WITH_NEW_PHYS_CODE */
1470
1471	/**
1472	* Gets the specified page directory pointer table entry.
1473	*
1474	* @returns PDP entry
1475	* @param pPGM Pointer to the PGM instance data.
1476	* @param iPdpt PDPT index
1477	*/
1478	VMMDECL(X86PDPE) PGMGstGetPaePDPtr(PVM pVM, unsigned iPdpt)
1479	{
1480	Assert(iPdpt <= 3);
1481	return pgmGstGetPaePDPTPtr(&pVM->pgm.s)->a[iPdpt & 3];
1482	}
1483
1484
1485	/**
1486	* Gets the current CR3 register value for the shadow memory context.
1487	* @returns CR3 value.
1488	* @param pVM The VM handle.
1489	*/
1490	VMMDECL(RTHCPHYS) PGMGetHyperCR3(PVM pVM)
1491	{
1492	PPGMPOOLPAGE pPoolPage = pVM->pgm.s.CTX_SUFF(pShwPageCR3);
1493	AssertPtrReturn(pPoolPage, 0);
1494	return pPoolPage->Core.Key;
1495	}
1496
1497
1498	/**
1499	* Gets the current CR3 register value for the nested memory context.
1500	* @returns CR3 value.
1501	* @param pVM The VM handle.
1502	*/
1503	VMMDECL(RTHCPHYS) PGMGetNestedCR3(PVM pVM, PGMMODE enmShadowMode)
1504	{
1505	Assert(pVM->pgm.s.CTX_SUFF(pShwPageCR3));
1506	return pVM->pgm.s.CTX_SUFF(pShwPageCR3)->Core.Key;
1507	}
1508
1509
1510	/**
1511	* Gets the CR3 register value for the 32-Bit shadow memory context.
1512	* @returns CR3 value.
1513	* @param pVM The VM handle.
1514	*/
1515	VMMDECL(RTHCPHYS) PGMGetHyper32BitCR3(PVM pVM)
1516	{
1517	Assert(pVM->pgm.s.CTX_SUFF(pShwPageCR3));
1518	return pVM->pgm.s.CTX_SUFF(pShwPageCR3)->Core.Key;
1519	}
1520
1521
1522	/**
1523	* Gets the CR3 register value for the PAE shadow memory context.
1524	* @returns CR3 value.
1525	* @param pVM The VM handle.
1526	*/
1527	VMMDECL(RTHCPHYS) PGMGetHyperPaeCR3(PVM pVM)
1528	{
1529	Assert(pVM->pgm.s.CTX_SUFF(pShwPageCR3));
1530	return pVM->pgm.s.CTX_SUFF(pShwPageCR3)->Core.Key;
1531	}
1532
1533
1534	/**
1535	* Gets the CR3 register value for the AMD64 shadow memory context.
1536	* @returns CR3 value.
1537	* @param pVM The VM handle.
1538	*/
1539	VMMDECL(RTHCPHYS) PGMGetHyperAmd64CR3(PVM pVM)
1540	{
1541	Assert(pVM->pgm.s.CTX_SUFF(pShwPageCR3));
1542	return pVM->pgm.s.CTX_SUFF(pShwPageCR3)->Core.Key;
1543	}
1544
1545
1546	/**
1547	* Gets the current CR3 register value for the HC intermediate memory context.
1548	* @returns CR3 value.
1549	* @param pVM The VM handle.
1550	*/
1551	VMMDECL(RTHCPHYS) PGMGetInterHCCR3(PVM pVM)
1552	{
1553	switch (pVM->pgm.s.enmHostMode)
1554	{
1555	case SUPPAGINGMODE_32_BIT:
1556	case SUPPAGINGMODE_32_BIT_GLOBAL:
1557	return pVM->pgm.s.HCPhysInterPD;
1558
1559	case SUPPAGINGMODE_PAE:
1560	case SUPPAGINGMODE_PAE_GLOBAL:
1561	case SUPPAGINGMODE_PAE_NX:
1562	case SUPPAGINGMODE_PAE_GLOBAL_NX:
1563	return pVM->pgm.s.HCPhysInterPaePDPT;
1564
1565	case SUPPAGINGMODE_AMD64:
1566	case SUPPAGINGMODE_AMD64_GLOBAL:
1567	case SUPPAGINGMODE_AMD64_NX:
1568	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1569	return pVM->pgm.s.HCPhysInterPaePDPT;
1570
1571	default:
1572	AssertMsgFailed(("enmHostMode=%d\n", pVM->pgm.s.enmHostMode));
1573	return ~0;
1574	}
1575	}
1576
1577
1578	/**
1579	* Gets the current CR3 register value for the RC intermediate memory context.
1580	* @returns CR3 value.
1581	* @param pVM The VM handle.
1582	*/
1583	VMMDECL(RTHCPHYS) PGMGetInterRCCR3(PVM pVM)
1584	{
1585	switch (pVM->pgm.s.enmShadowMode)
1586	{
1587	case PGMMODE_32_BIT:
1588	return pVM->pgm.s.HCPhysInterPD;
1589
1590	case PGMMODE_PAE:
1591	case PGMMODE_PAE_NX:
1592	return pVM->pgm.s.HCPhysInterPaePDPT;
1593
1594	case PGMMODE_AMD64:
1595	case PGMMODE_AMD64_NX:
1596	return pVM->pgm.s.HCPhysInterPaePML4;
1597
1598	case PGMMODE_EPT:
1599	case PGMMODE_NESTED:
1600	return 0; /* not relevant */
1601
1602	default:
1603	AssertMsgFailed(("enmShadowMode=%d\n", pVM->pgm.s.enmShadowMode));
1604	return ~0;
1605	}
1606	}
1607
1608
1609	/**
1610	* Gets the CR3 register value for the 32-Bit intermediate memory context.
1611	* @returns CR3 value.
1612	* @param pVM The VM handle.
1613	*/
1614	VMMDECL(RTHCPHYS) PGMGetInter32BitCR3(PVM pVM)
1615	{
1616	return pVM->pgm.s.HCPhysInterPD;
1617	}
1618
1619
1620	/**
1621	* Gets the CR3 register value for the PAE intermediate memory context.
1622	* @returns CR3 value.
1623	* @param pVM The VM handle.
1624	*/
1625	VMMDECL(RTHCPHYS) PGMGetInterPaeCR3(PVM pVM)
1626	{
1627	return pVM->pgm.s.HCPhysInterPaePDPT;
1628	}
1629
1630
1631	/**
1632	* Gets the CR3 register value for the AMD64 intermediate memory context.
1633	* @returns CR3 value.
1634	* @param pVM The VM handle.
1635	*/
1636	VMMDECL(RTHCPHYS) PGMGetInterAmd64CR3(PVM pVM)
1637	{
1638	return pVM->pgm.s.HCPhysInterPaePML4;
1639	}
1640
1641
1642	/**
1643	* Performs and schedules necessary updates following a CR3 load or reload.
1644	*
1645	* This will normally involve mapping the guest PD or nPDPT
1646	*
1647	* @returns VBox status code.
1648	* @retval VINF_PGM_SYNC_CR3 if monitoring requires a CR3 sync. This can
1649	* safely be ignored and overridden since the FF will be set too then.
1650	* @param pVM VM handle.
1651	* @param cr3 The new cr3.
1652	* @param fGlobal Indicates whether this is a global flush or not.
1653	*/
1654	VMMDECL(int) PGMFlushTLB(PVM pVM, uint64_t cr3, bool fGlobal)
1655	{
1656	STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,FlushTLB), a);
1657
1658	/*
1659	* Always flag the necessary updates; necessary for hardware acceleration
1660	*/
1661	/** @todo optimize this, it shouldn't always be necessary. */
1662	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
1663	if (fGlobal)
1664	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
1665	LogFlow(("PGMFlushTLB: cr3=%RX64 OldCr3=%RX64 fGlobal=%d\n", cr3, pVM->pgm.s.GCPhysCR3, fGlobal));
1666
1667	/*
1668	* Remap the CR3 content and adjust the monitoring if CR3 was actually changed.
1669	*/
1670	int rc = VINF_SUCCESS;
1671	RTGCPHYS GCPhysCR3;
1672	switch (pVM->pgm.s.enmGuestMode)
1673	{
1674	case PGMMODE_PAE:
1675	case PGMMODE_PAE_NX:
1676	GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAE_PAGE_MASK);
1677	break;
1678	case PGMMODE_AMD64:
1679	case PGMMODE_AMD64_NX:
1680	GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_AMD64_PAGE_MASK);
1681	break;
1682	default:
1683	GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAGE_MASK);
1684	break;
1685	}
1686
1687	if (pVM->pgm.s.GCPhysCR3 != GCPhysCR3)
1688	{
1689	RTGCPHYS GCPhysOldCR3 = pVM->pgm.s.GCPhysCR3;
1690	pVM->pgm.s.GCPhysCR3 = GCPhysCR3;
1691	rc = PGM_BTH_PFN(MapCR3, pVM)(pVM, GCPhysCR3);
1692	if (RT_LIKELY(rc == VINF_SUCCESS))
1693	{
1694	if (!pVM->pgm.s.fMappingsFixed)
1695	{
1696	pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
1697	}
1698	}
1699	else
1700	{
1701	AssertMsg(rc == VINF_PGM_SYNC_CR3, ("%Rrc\n", rc));
1702	Assert(VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL \| VM_FF_PGM_SYNC_CR3));
1703	pVM->pgm.s.GCPhysCR3 = GCPhysOldCR3;
1704	pVM->pgm.s.fSyncFlags \|= PGM_SYNC_MAP_CR3;
1705	if (!pVM->pgm.s.fMappingsFixed)
1706	pVM->pgm.s.fSyncFlags \|= PGM_SYNC_MONITOR_CR3;
1707	}
1708
1709	if (fGlobal)
1710	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,FlushTLBNewCR3Global));
1711	else
1712	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,FlushTLBNewCR3));
1713	}
1714	else
1715	{
1716	/*
1717	* Check if we have a pending update of the CR3 monitoring.
1718	*/
1719	if (pVM->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
1720	{
1721	pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
1722	Assert(!pVM->pgm.s.fMappingsFixed);
1723	}
1724	if (fGlobal)
1725	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,FlushTLBSameCR3Global));
1726	else
1727	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,FlushTLBSameCR3));
1728	}
1729
1730	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,FlushTLB), a);
1731	return rc;
1732	}
1733
1734
1735	/**
1736	* Performs and schedules necessary updates following a CR3 load or reload when
1737	* using nested or extended paging.
1738	*
1739	* This API is an alterantive to PDMFlushTLB that avoids actually flushing the
1740	* TLB and triggering a SyncCR3.
1741	*
1742	* This will normally involve mapping the guest PD or nPDPT
1743	*
1744	* @returns VBox status code.
1745	* @retval VINF_SUCCESS.
1746	* @retval (If applied when not in nested mode: VINF_PGM_SYNC_CR3 if monitoring
1747	* requires a CR3 sync. This can safely be ignored and overridden since
1748	* the FF will be set too then.)
1749	* @param pVM VM handle.
1750	* @param cr3 The new cr3.
1751	*/
1752	VMMDECL(int) PGMUpdateCR3(PVM pVM, uint64_t cr3)
1753	{
1754	LogFlow(("PGMUpdateCR3: cr3=%RX64 OldCr3=%RX64\n", cr3, pVM->pgm.s.GCPhysCR3));
1755
1756	/* We assume we're only called in nested paging mode. */
1757	Assert(pVM->pgm.s.fMappingsFixed);
1758	Assert(!(pVM->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3));
1759	Assert(pVM->pgm.s.enmShadowMode == PGMMODE_NESTED \|\| pVM->pgm.s.enmShadowMode == PGMMODE_EPT);
1760
1761	/*
1762	* Remap the CR3 content and adjust the monitoring if CR3 was actually changed.
1763	*/
1764	int rc = VINF_SUCCESS;
1765	RTGCPHYS GCPhysCR3;
1766	switch (pVM->pgm.s.enmGuestMode)
1767	{
1768	case PGMMODE_PAE:
1769	case PGMMODE_PAE_NX:
1770	GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAE_PAGE_MASK);
1771	break;
1772	case PGMMODE_AMD64:
1773	case PGMMODE_AMD64_NX:
1774	GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_AMD64_PAGE_MASK);
1775	break;
1776	default:
1777	GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAGE_MASK);
1778	break;
1779	}
1780	if (pVM->pgm.s.GCPhysCR3 != GCPhysCR3)
1781	{
1782	pVM->pgm.s.GCPhysCR3 = GCPhysCR3;
1783	rc = PGM_BTH_PFN(MapCR3, pVM)(pVM, GCPhysCR3);
1784	AssertRCSuccess(rc); /* Assumes VINF_PGM_SYNC_CR3 doesn't apply to nested paging. / /* @todo this isn't true for the mac, but we need hw to test/fix this. */
1785	}
1786	return rc;
1787	}
1788
1789
1790	/**
1791	* Synchronize the paging structures.
1792	*
1793	* This function is called in response to the VM_FF_PGM_SYNC_CR3 and
1794	* VM_FF_PGM_SYNC_CR3_NONGLOBAL. Those two force action flags are set
1795	* in several places, most importantly whenever the CR3 is loaded.
1796	*
1797	* @returns VBox status code.
1798	* @param pVM The virtual machine.
1799	* @param cr0 Guest context CR0 register
1800	* @param cr3 Guest context CR3 register
1801	* @param cr4 Guest context CR4 register
1802	* @param fGlobal Including global page directories or not
1803	*/
1804	VMMDECL(int) PGMSyncCR3(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
1805	{
1806	int rc;
1807
1808	/*
1809	* We might be called when we shouldn't.
1810	*
1811	* The mode switching will ensure that the PD is resynced
1812	* after every mode switch. So, if we find ourselves here
1813	* when in protected or real mode we can safely disable the
1814	* FF and return immediately.
1815	*/
1816	if (pVM->pgm.s.enmGuestMode <= PGMMODE_PROTECTED)
1817	{
1818	Assert((cr0 & (X86_CR0_PG \| X86_CR0_PE)) != (X86_CR0_PG \| X86_CR0_PE));
1819	VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3);
1820	VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
1821	return VINF_SUCCESS;
1822	}
1823
1824	/* If global pages are not supported, then all flushes are global. */
1825	if (!(cr4 & X86_CR4_PGE))
1826	fGlobal = true;
1827	LogFlow(("PGMSyncCR3: cr0=%RX64 cr3=%RX64 cr4=%RX64 fGlobal=%d[%d,%d]\n", cr0, cr3, cr4, fGlobal,
1828	VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3), VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL)));
1829
1830	#ifdef PGMPOOL_WITH_MONITORING
1831	/*
1832	* The pool may have pending stuff and even require a return to ring-3 to
1833	* clear the whole thing.
1834	*/
1835	rc = pgmPoolSyncCR3(pVM);
1836	if (rc != VINF_SUCCESS)
1837	return rc;
1838	#endif
1839
1840	/*
1841	* Check if we need to finish an aborted MapCR3 call (see PGMFlushTLB).
1842	* This should be done before SyncCR3.
1843	*/
1844	if (pVM->pgm.s.fSyncFlags & PGM_SYNC_MAP_CR3)
1845	{
1846	pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_MAP_CR3;
1847
1848	RTGCPHYS GCPhysCR3Old = pVM->pgm.s.GCPhysCR3;
1849	RTGCPHYS GCPhysCR3;
1850	switch (pVM->pgm.s.enmGuestMode)
1851	{
1852	case PGMMODE_PAE:
1853	case PGMMODE_PAE_NX:
1854	GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAE_PAGE_MASK);
1855	break;
1856	case PGMMODE_AMD64:
1857	case PGMMODE_AMD64_NX:
1858	GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_AMD64_PAGE_MASK);
1859	break;
1860	default:
1861	GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAGE_MASK);
1862	break;
1863	}
1864
1865	if (pVM->pgm.s.GCPhysCR3 != GCPhysCR3)
1866	{
1867	pVM->pgm.s.GCPhysCR3 = GCPhysCR3;
1868	rc = PGM_BTH_PFN(MapCR3, pVM)(pVM, GCPhysCR3);
1869	}
1870	#ifdef IN_RING3
1871	if (rc == VINF_PGM_SYNC_CR3)
1872	rc = pgmPoolSyncCR3(pVM);
1873	#else
1874	if (rc == VINF_PGM_SYNC_CR3)
1875	{
1876	pVM->pgm.s.GCPhysCR3 = GCPhysCR3Old;
1877	return rc;
1878	}
1879	#endif
1880	AssertRCReturn(rc, rc);
1881	AssertRCSuccessReturn(rc, VERR_INTERNAL_ERROR);
1882	}
1883
1884	/*
1885	* Let the 'Bth' function do the work and we'll just keep track of the flags.
1886	*/
1887	STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3), a);
1888	rc = PGM_BTH_PFN(SyncCR3, pVM)(pVM, cr0, cr3, cr4, fGlobal);
1889	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3), a);
1890	AssertMsg(rc == VINF_SUCCESS \|\| rc == VINF_PGM_SYNC_CR3 \|\| RT_FAILURE(rc), ("rc=%Rrc\n", rc));
1891	if (rc == VINF_SUCCESS)
1892	{
1893	if (!(pVM->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS))
1894	{
1895	VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3);
1896	VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
1897	}
1898
1899	/*
1900	* Check if we have a pending update of the CR3 monitoring.
1901	*/
1902	if (pVM->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
1903	{
1904	pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
1905	Assert(!pVM->pgm.s.fMappingsFixed);
1906	}
1907	}
1908
1909	/*
1910	* Now flush the CR3 (guest context).
1911	*/
1912	if (rc == VINF_SUCCESS)
1913	PGM_INVL_GUEST_TLBS();
1914	return rc;
1915	}
1916
1917
1918	/**
1919	* Called whenever CR0 or CR4 in a way which may change
1920	* the paging mode.
1921	*
1922	* @returns VBox status code fit for scheduling in GC and R0.
1923	* @retval VINF_SUCCESS if the was no change, or it was successfully dealt with.
1924	* @retval VINF_PGM_CHANGE_MODE if we're in GC or R0 and the mode changes.
1925	* @param pVM VM handle.
1926	* @param cr0 The new cr0.
1927	* @param cr4 The new cr4.
1928	* @param efer The new extended feature enable register.
1929	*/
1930	VMMDECL(int) PGMChangeMode(PVM pVM, uint64_t cr0, uint64_t cr4, uint64_t efer)
1931	{
1932	PGMMODE enmGuestMode;
1933
1934	/*
1935	* Calc the new guest mode.
1936	*/
1937	if (!(cr0 & X86_CR0_PE))
1938	enmGuestMode = PGMMODE_REAL;
1939	else if (!(cr0 & X86_CR0_PG))
1940	enmGuestMode = PGMMODE_PROTECTED;
1941	else if (!(cr4 & X86_CR4_PAE))
1942	enmGuestMode = PGMMODE_32_BIT;
1943	else if (!(efer & MSR_K6_EFER_LME))
1944	{
1945	if (!(efer & MSR_K6_EFER_NXE))
1946	enmGuestMode = PGMMODE_PAE;
1947	else
1948	enmGuestMode = PGMMODE_PAE_NX;
1949	}
1950	else
1951	{
1952	if (!(efer & MSR_K6_EFER_NXE))
1953	enmGuestMode = PGMMODE_AMD64;
1954	else
1955	enmGuestMode = PGMMODE_AMD64_NX;
1956	}
1957
1958	/*
1959	* Did it change?
1960	*/
1961	if (pVM->pgm.s.enmGuestMode == enmGuestMode)
1962	return VINF_SUCCESS;
1963
1964	/* Flush the TLB */
1965	PGM_INVL_GUEST_TLBS();
1966
1967	#ifdef IN_RING3
1968	return PGMR3ChangeMode(pVM, enmGuestMode);
1969	#else
1970	LogFlow(("PGMChangeMode: returns VINF_PGM_CHANGE_MODE.\n"));
1971	return VINF_PGM_CHANGE_MODE;
1972	#endif
1973	}
1974
1975
1976	/**
1977	* Gets the current guest paging mode.
1978	*
1979	* If you just need the CPU mode (real/protected/long), use CPUMGetGuestMode().
1980	*
1981	* @returns The current paging mode.
1982	* @param pVM The VM handle.
1983	*/
1984	VMMDECL(PGMMODE) PGMGetGuestMode(PVM pVM)
1985	{
1986	return pVM->pgm.s.enmGuestMode;
1987	}
1988
1989
1990	/**
1991	* Gets the current shadow paging mode.
1992	*
1993	* @returns The current paging mode.
1994	* @param pVM The VM handle.
1995	*/
1996	VMMDECL(PGMMODE) PGMGetShadowMode(PVM pVM)
1997	{
1998	return pVM->pgm.s.enmShadowMode;
1999	}
2000
2001	/**
2002	* Gets the current host paging mode.
2003	*
2004	* @returns The current paging mode.
2005	* @param pVM The VM handle.
2006	*/
2007	VMMDECL(PGMMODE) PGMGetHostMode(PVM pVM)
2008	{
2009	switch (pVM->pgm.s.enmHostMode)
2010	{
2011	case SUPPAGINGMODE_32_BIT:
2012	case SUPPAGINGMODE_32_BIT_GLOBAL:
2013	return PGMMODE_32_BIT;
2014
2015	case SUPPAGINGMODE_PAE:
2016	case SUPPAGINGMODE_PAE_GLOBAL:
2017	return PGMMODE_PAE;
2018
2019	case SUPPAGINGMODE_PAE_NX:
2020	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2021	return PGMMODE_PAE_NX;
2022
2023	case SUPPAGINGMODE_AMD64:
2024	case SUPPAGINGMODE_AMD64_GLOBAL:
2025	return PGMMODE_AMD64;
2026
2027	case SUPPAGINGMODE_AMD64_NX:
2028	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2029	return PGMMODE_AMD64_NX;
2030
2031	default: AssertMsgFailed(("enmHostMode=%d\n", pVM->pgm.s.enmHostMode)); break;
2032	}
2033
2034	return PGMMODE_INVALID;
2035	}
2036
2037
2038	/**
2039	* Get mode name.
2040	*
2041	* @returns read-only name string.
2042	* @param enmMode The mode which name is desired.
2043	*/
2044	VMMDECL(const char *) PGMGetModeName(PGMMODE enmMode)
2045	{
2046	switch (enmMode)
2047	{
2048	case PGMMODE_REAL: return "Real";
2049	case PGMMODE_PROTECTED: return "Protected";
2050	case PGMMODE_32_BIT: return "32-bit";
2051	case PGMMODE_PAE: return "PAE";
2052	case PGMMODE_PAE_NX: return "PAE+NX";
2053	case PGMMODE_AMD64: return "AMD64";
2054	case PGMMODE_AMD64_NX: return "AMD64+NX";
2055	case PGMMODE_NESTED: return "Nested";
2056	case PGMMODE_EPT: return "EPT";
2057	default: return "unknown mode value";
2058	}
2059	}
2060
2061
2062	/**
2063	* Acquire the PGM lock.
2064	*
2065	* @returns VBox status code
2066	* @param pVM The VM to operate on.
2067	*/
2068	int pgmLock(PVM pVM)
2069	{
2070	int rc = PDMCritSectEnter(&pVM->pgm.s.CritSect, VERR_SEM_BUSY);
2071	#ifdef IN_RC
2072	if (rc == VERR_SEM_BUSY)
2073	rc = VMMGCCallHost(pVM, VMMCALLHOST_PGM_LOCK, 0);
2074	#elif defined(IN_RING0)
2075	if (rc == VERR_SEM_BUSY)
2076	rc = VMMR0CallHost(pVM, VMMCALLHOST_PGM_LOCK, 0);
2077	#endif
2078	AssertMsg(rc == VINF_SUCCESS, ("%Rrc\n", rc));
2079	return rc;
2080	}
2081
2082
2083	/**
2084	* Release the PGM lock.
2085	*
2086	* @returns VBox status code
2087	* @param pVM The VM to operate on.
2088	*/
2089	void pgmUnlock(PVM pVM)
2090	{
2091	PDMCritSectLeave(&pVM->pgm.s.CritSect);
2092	}
2093
2094	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2095
2096	/**
2097	* Temporarily maps one guest page specified by GC physical address.
2098	* These pages must have a physical mapping in HC, i.e. they cannot be MMIO pages.
2099	*
2100	* Be WARNED that the dynamic page mapping area is small, 8 pages, thus the space is
2101	* reused after 8 mappings (or perhaps a few more if you score with the cache).
2102	*
2103	* @returns VBox status.
2104	* @param pVM VM handle.
2105	* @param GCPhys GC Physical address of the page.
2106	* @param ppv Where to store the address of the mapping.
2107	*/
2108	VMMDECL(int) PGMDynMapGCPage(PVM pVM, RTGCPHYS GCPhys, void **ppv)
2109	{
2110	AssertMsg(!(GCPhys & PAGE_OFFSET_MASK), ("GCPhys=%RGp\n", GCPhys));
2111
2112	/*
2113	* Get the ram range.
2114	*/
2115	PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
2116	while (pRam && GCPhys - pRam->GCPhys >= pRam->cb)
2117	pRam = pRam->CTX_SUFF(pNext);
2118	if (!pRam)
2119	{
2120	AssertMsgFailed(("Invalid physical address %RGp!\n", GCPhys));
2121	return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2122	}
2123
2124	/*
2125	* Pass it on to PGMDynMapHCPage.
2126	*/
2127	RTHCPHYS HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT]);
2128	//Log(("PGMDynMapGCPage: GCPhys=%RGp HCPhys=%RHp\n", GCPhys, HCPhys));
2129	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2130	pgmR0DynMapHCPageInlined(&pVM->pgm.s, HCPhys, ppv);
2131	#else
2132	PGMDynMapHCPage(pVM, HCPhys, ppv);
2133	#endif
2134	return VINF_SUCCESS;
2135	}
2136
2137
2138	/**
2139	* Temporarily maps one guest page specified by unaligned GC physical address.
2140	* These pages must have a physical mapping in HC, i.e. they cannot be MMIO pages.
2141	*
2142	* Be WARNED that the dynamic page mapping area is small, 8 pages, thus the space is
2143	* reused after 8 mappings (or perhaps a few more if you score with the cache).
2144	*
2145	* The caller is aware that only the speicifed page is mapped and that really bad things
2146	* will happen if writing beyond the page!
2147	*
2148	* @returns VBox status.
2149	* @param pVM VM handle.
2150	* @param GCPhys GC Physical address within the page to be mapped.
2151	* @param ppv Where to store the address of the mapping address corresponding to GCPhys.
2152	*/
2153	VMMDECL(int) PGMDynMapGCPageOff(PVM pVM, RTGCPHYS GCPhys, void **ppv)
2154	{
2155	/*
2156	* Get the ram range.
2157	*/
2158	PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
2159	while (pRam && GCPhys - pRam->GCPhys >= pRam->cb)
2160	pRam = pRam->CTX_SUFF(pNext);
2161	if (!pRam)
2162	{
2163	AssertMsgFailed(("Invalid physical address %RGp!\n", GCPhys));
2164	return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2165	}
2166
2167	/*
2168	* Pass it on to PGMDynMapHCPage.
2169	*/
2170	RTHCPHYS HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT]);
2171	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2172	pgmR0DynMapHCPageInlined(&pVM->pgm.s, HCPhys, ppv);
2173	#else
2174	PGMDynMapHCPage(pVM, HCPhys, ppv);
2175	#endif
2176	ppv = (void )((uintptr_t)*ppv \| (GCPhys & PAGE_OFFSET_MASK));
2177	return VINF_SUCCESS;
2178	}
2179
2180	# ifdef IN_RC
2181
2182	/**
2183	* Temporarily maps one host page specified by HC physical address.
2184	*
2185	* Be WARNED that the dynamic page mapping area is small, 16 pages, thus the space is
2186	* reused after 16 mappings (or perhaps a few more if you score with the cache).
2187	*
2188	* @returns VINF_SUCCESS, will bail out to ring-3 on failure.
2189	* @param pVM VM handle.
2190	* @param HCPhys HC Physical address of the page.
2191	* @param ppv Where to store the address of the mapping. This is the
2192	* address of the PAGE not the exact address corresponding
2193	* to HCPhys. Use PGMDynMapHCPageOff if you care for the
2194	* page offset.
2195	*/
2196	VMMDECL(int) PGMDynMapHCPage(PVM pVM, RTHCPHYS HCPhys, void **ppv)
2197	{
2198	AssertMsg(!(HCPhys & PAGE_OFFSET_MASK), ("HCPhys=%RHp\n", HCPhys));
2199
2200	/*
2201	* Check the cache.
2202	*/
2203	register unsigned iCache;
2204	for (iCache = 0;iCache < RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache);iCache++)
2205	{
2206	static const uint8_t au8Trans[MM_HYPER_DYNAMIC_SIZE >> PAGE_SHIFT][RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache)] =
2207	{
2208	{ 0, 9, 10, 11, 12, 13, 14, 15},
2209	{ 0, 1, 10, 11, 12, 13, 14, 15},
2210	{ 0, 1, 2, 11, 12, 13, 14, 15},
2211	{ 0, 1, 2, 3, 12, 13, 14, 15},
2212	{ 0, 1, 2, 3, 4, 13, 14, 15},
2213	{ 0, 1, 2, 3, 4, 5, 14, 15},
2214	{ 0, 1, 2, 3, 4, 5, 6, 15},
2215	{ 0, 1, 2, 3, 4, 5, 6, 7},
2216	{ 8, 1, 2, 3, 4, 5, 6, 7},
2217	{ 8, 9, 2, 3, 4, 5, 6, 7},
2218	{ 8, 9, 10, 3, 4, 5, 6, 7},
2219	{ 8, 9, 10, 11, 4, 5, 6, 7},
2220	{ 8, 9, 10, 11, 12, 5, 6, 7},
2221	{ 8, 9, 10, 11, 12, 13, 6, 7},
2222	{ 8, 9, 10, 11, 12, 13, 14, 7},
2223	{ 8, 9, 10, 11, 12, 13, 14, 15},
2224	};
2225	AssertCompile(RT_ELEMENTS(au8Trans) == 16);
2226	AssertCompile(RT_ELEMENTS(au8Trans[0]) == 8);
2227
2228	if (pVM->pgm.s.aHCPhysDynPageMapCache[iCache] == HCPhys)
2229	{
2230	int iPage = au8Trans[pVM->pgm.s.iDynPageMapLast][iCache];
2231
2232	/* The cache can get out of sync with locked entries. (10 locked, 2 overwrites its cache position, last = 11, lookup 2 -> page 10 instead of 2) */
2233	if ((pVM->pgm.s.paDynPageMap32BitPTEsGC[iPage].u & X86_PTE_PG_MASK) == HCPhys)
2234	{
2235	void *pv = pVM->pgm.s.pbDynPageMapBaseGC + (iPage << PAGE_SHIFT);
2236	*ppv = pv;
2237	STAM_COUNTER_INC(&pVM->pgm.s.StatRCDynMapCacheHits);
2238	Log4(("PGMGCDynMapHCPage: HCPhys=%RHp pv=%p iPage=%d iCache=%d\n", HCPhys, pv, iPage, iCache));
2239	return VINF_SUCCESS;
2240	}
2241	else
2242	LogFlow(("Out of sync entry %d\n", iPage));
2243	}
2244	}
2245	AssertCompile(RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache) == 8);
2246	AssertCompile((MM_HYPER_DYNAMIC_SIZE >> PAGE_SHIFT) == 16);
2247	STAM_COUNTER_INC(&pVM->pgm.s.StatRCDynMapCacheMisses);
2248
2249	/*
2250	* Update the page tables.
2251	*/
2252	register unsigned iPage = pVM->pgm.s.iDynPageMapLast;
2253	unsigned i;
2254	for (i=0;i<(MM_HYPER_DYNAMIC_SIZE >> PAGE_SHIFT);i++)
2255	{
2256	pVM->pgm.s.iDynPageMapLast = iPage = (iPage + 1) & ((MM_HYPER_DYNAMIC_SIZE >> PAGE_SHIFT) - 1);
2257	if (!pVM->pgm.s.aLockedDynPageMapCache[iPage])
2258	break;
2259	iPage++;
2260	}
2261	AssertRelease(i != (MM_HYPER_DYNAMIC_SIZE >> PAGE_SHIFT));
2262
2263	pVM->pgm.s.aHCPhysDynPageMapCache[iPage & (RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache) - 1)] = HCPhys;
2264	pVM->pgm.s.paDynPageMap32BitPTEsGC[iPage].u = (uint32_t)HCPhys \| X86_PTE_P \| X86_PTE_A \| X86_PTE_D;
2265	pVM->pgm.s.paDynPageMapPaePTEsGC[iPage].u = HCPhys \| X86_PTE_P \| X86_PTE_A \| X86_PTE_D;
2266	pVM->pgm.s.aLockedDynPageMapCache[iPage] = 0;
2267
2268	void *pv = pVM->pgm.s.pbDynPageMapBaseGC + (iPage << PAGE_SHIFT);
2269	*ppv = pv;
2270	ASMInvalidatePage(pv);
2271	Log4(("PGMGCDynMapHCPage: HCPhys=%RHp pv=%p iPage=%d\n", HCPhys, pv, iPage));
2272	return VINF_SUCCESS;
2273	}
2274
2275
2276	/**
2277	* Temporarily lock a dynamic page to prevent it from being reused.
2278	*
2279	* @param pVM VM handle.
2280	* @param GCPage GC address of page
2281	*/
2282	VMMDECL(void) PGMDynLockHCPage(PVM pVM, RCPTRTYPE(uint8_t *) GCPage)
2283	{
2284	unsigned iPage;
2285
2286	Assert(GCPage >= pVM->pgm.s.pbDynPageMapBaseGC && GCPage < (pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE));
2287	iPage = ((uintptr_t)(GCPage - pVM->pgm.s.pbDynPageMapBaseGC)) >> PAGE_SHIFT;
2288	ASMAtomicIncU32(&pVM->pgm.s.aLockedDynPageMapCache[iPage]);
2289	Log4(("PGMDynLockHCPage %RRv iPage=%d\n", GCPage, iPage));
2290	}
2291
2292
2293	/**
2294	* Unlock a dynamic page
2295	*
2296	* @param pVM VM handle.
2297	* @param GCPage GC address of page
2298	*/
2299	VMMDECL(void) PGMDynUnlockHCPage(PVM pVM, RCPTRTYPE(uint8_t *) GCPage)
2300	{
2301	unsigned iPage;
2302
2303	AssertCompile(RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache) == RT_ELEMENTS(pVM->pgm.s.aLockedDynPageMapCache));
2304
2305	Assert(GCPage >= pVM->pgm.s.pbDynPageMapBaseGC && GCPage < (pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE));
2306	iPage = ((uintptr_t)(GCPage - pVM->pgm.s.pbDynPageMapBaseGC)) >> PAGE_SHIFT;
2307	Assert(pVM->pgm.s.aLockedDynPageMapCache[iPage]);
2308	ASMAtomicDecU32(&pVM->pgm.s.aLockedDynPageMapCache[iPage]);
2309	Log4(("PGMDynUnlockHCPage %RRv iPage=%d\n", GCPage, iPage));
2310	}
2311
2312
2313	# ifdef VBOX_STRICT
2314	/**
2315	* Check for lock leaks.
2316	*
2317	* @param pVM VM handle.
2318	*/
2319	VMMDECL(void) PGMDynCheckLocks(PVM pVM)
2320	{
2321	for (unsigned i=0;i<RT_ELEMENTS(pVM->pgm.s.aLockedDynPageMapCache);i++)
2322	Assert(!pVM->pgm.s.aLockedDynPageMapCache[i]);
2323	}
2324	# endif /* VBOX_STRICT */
2325
2326	# endif /* IN_RC */
2327	#endif /* IN_RC \|\| VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
2328
2329	#if !defined(IN_R0) \|\| defined(LOG_ENABLED)
2330
2331	/** Format handler for PGMPAGE.
2332	* @copydoc FNRTSTRFORMATTYPE */
2333	static DECLCALLBACK(size_t) pgmFormatTypeHandlerPage(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
2334	const char pszType, void const pvValue,
2335	int cchWidth, int cchPrecision, unsigned fFlags,
2336	void *pvUser)
2337	{
2338	size_t cch;
2339	PCPGMPAGE pPage = (PCPGMPAGE)pvValue;
2340	if (VALID_PTR(pPage))
2341	{
2342	char szTmp[64+80];
2343
2344	cch = 0;
2345
2346	/* The single char state stuff. */
2347	static const char s_achPageStates[4] = { 'Z', 'A', 'W', 'S' };
2348	szTmp[cch++] = s_achPageStates[PGM_PAGE_GET_STATE(pPage)];
2349
2350	#define IS_PART_INCLUDED(lvl) ( !(fFlags & RTSTR_F_PRECISION) \|\| cchPrecision == (lvl) \|\| cchPrecision >= (lvl)+10 )
2351	if (IS_PART_INCLUDED(5))
2352	{
2353	static const char s_achHandlerStates[4] = { '-', 't', 'w', 'a' };
2354	szTmp[cch++] = s_achHandlerStates[PGM_PAGE_GET_HNDL_PHYS_STATE(pPage)];
2355	szTmp[cch++] = s_achHandlerStates[PGM_PAGE_GET_HNDL_VIRT_STATE(pPage)];
2356	}
2357
2358	/* The type. */
2359	if (IS_PART_INCLUDED(4))
2360	{
2361	szTmp[cch++] = ':';
2362	static const char s_achPageTypes[8][4] = { "INV", "RAM", "MI2", "M2A", "SHA", "ROM", "MIO", "BAD" };
2363	szTmp[cch++] = s_achPageTypes[PGM_PAGE_GET_TYPE(pPage)][0];
2364	szTmp[cch++] = s_achPageTypes[PGM_PAGE_GET_TYPE(pPage)][1];
2365	szTmp[cch++] = s_achPageTypes[PGM_PAGE_GET_TYPE(pPage)][2];
2366	}
2367
2368	/* The numbers. */
2369	if (IS_PART_INCLUDED(3))
2370	{
2371	szTmp[cch++] = ':';
2372	cch += RTStrFormatNumber(&szTmp[cch], PGM_PAGE_GET_HCPHYS(pPage), 16, 12, 0, RTSTR_F_ZEROPAD \| RTSTR_F_64BIT);
2373	}
2374
2375	if (IS_PART_INCLUDED(2))
2376	{
2377	szTmp[cch++] = ':';
2378	cch += RTStrFormatNumber(&szTmp[cch], PGM_PAGE_GET_PAGEID(pPage), 16, 7, 0, RTSTR_F_ZEROPAD \| RTSTR_F_32BIT);
2379	}
2380
2381	if (IS_PART_INCLUDED(6))
2382	{
2383	szTmp[cch++] = ':';
2384	static const char s_achRefs[4] = { '-', 'U', '!', 'L' };
2385	szTmp[cch++] = s_achRefs[PGM_PAGE_GET_TD_CREFS(pPage)];
2386	cch += RTStrFormatNumber(&szTmp[cch], PGM_PAGE_GET_TD_IDX(pPage), 16, 4, 0, RTSTR_F_ZEROPAD \| RTSTR_F_16BIT);
2387	}
2388	#undef IS_PART_INCLUDED
2389
2390	cch = pfnOutput(pvArgOutput, szTmp, cch);
2391	}
2392	else
2393	cch = pfnOutput(pvArgOutput, "<bad-pgmpage-ptr>", sizeof("<bad-pgmpage-ptr>") - 1);
2394	return cch;
2395	}
2396
2397
2398	/** Format handler for PGMRAMRANGE.
2399	* @copydoc FNRTSTRFORMATTYPE */
2400	static DECLCALLBACK(size_t) pgmFormatTypeHandlerRamRange(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
2401	const char pszType, void const pvValue,
2402	int cchWidth, int cchPrecision, unsigned fFlags,
2403	void *pvUser)
2404	{
2405	size_t cch;
2406	PGMRAMRANGE const pRam = (PGMRAMRANGE const )pvValue;
2407	if (VALID_PTR(pRam))
2408	{
2409	char szTmp[80];
2410	cch = RTStrPrintf(szTmp, sizeof(szTmp), "%RGp-%RGp", pRam->GCPhys, pRam->GCPhysLast);
2411	cch = pfnOutput(pvArgOutput, szTmp, cch);
2412	}
2413	else
2414	cch = pfnOutput(pvArgOutput, "<bad-pgmramrange-ptr>", sizeof("<bad-pgmramrange-ptr>") - 1);
2415	return cch;
2416	}
2417
2418	/** Format type andlers to be registered/deregistered. */
2419	static const struct
2420	{
2421	char szType[24];
2422	PFNRTSTRFORMATTYPE pfnHandler;
2423	} g_aPgmFormatTypes[] =
2424	{
2425	{ "pgmpage", pgmFormatTypeHandlerPage },
2426	{ "pgmramrange", pgmFormatTypeHandlerRamRange }
2427	};
2428
2429	#endif /* !IN_R0 \|\| LOG_ENABLED */
2430
2431
2432	/**
2433	* Registers the global string format types.
2434	*
2435	* This should be called at module load time or in some other manner that ensure
2436	* that it's called exactly one time.
2437	*
2438	* @returns IPRT status code on RTStrFormatTypeRegister failure.
2439	*/
2440	VMMDECL(int) PGMRegisterStringFormatTypes(void)
2441	{
2442	#if !defined(IN_R0) \|\| defined(LOG_ENABLED)
2443	int rc = VINF_SUCCESS;
2444	unsigned i;
2445	for (i = 0; RT_SUCCESS(rc) && i < RT_ELEMENTS(g_aPgmFormatTypes); i++)
2446	{
2447	rc = RTStrFormatTypeRegister(g_aPgmFormatTypes[i].szType, g_aPgmFormatTypes[i].pfnHandler, NULL);
2448	# ifdef IN_RING0
2449	if (rc == VERR_ALREADY_EXISTS)
2450	{
2451	/* in case of cleanup failure in ring-0 */
2452	RTStrFormatTypeDeregister(g_aPgmFormatTypes[i].szType);
2453	rc = RTStrFormatTypeRegister(g_aPgmFormatTypes[i].szType, g_aPgmFormatTypes[i].pfnHandler, NULL);
2454	}
2455	# endif
2456	}
2457	if (RT_FAILURE(rc))
2458	while (i-- > 0)
2459	RTStrFormatTypeDeregister(g_aPgmFormatTypes[i].szType);
2460
2461	return rc;
2462	#else
2463	return VINF_SUCCESS;
2464	#endif
2465	}
2466
2467
2468	/**
2469	* Deregisters the global string format types.
2470	*
2471	* This should be called at module unload time or in some other manner that
2472	* ensure that it's called exactly one time.
2473	*/
2474	VMMDECL(void) PGMDeregisterStringFormatTypes(void)
2475	{
2476	#if !defined(IN_R0) \|\| defined(LOG_ENABLED)
2477	for (unsigned i = 0; i < RT_ELEMENTS(g_aPgmFormatTypes); i++)
2478	RTStrFormatTypeDeregister(g_aPgmFormatTypes[i].szType);
2479	#endif
2480	}
2481
2482	#ifdef VBOX_STRICT
2483
2484	/**
2485	* Asserts that there are no mapping conflicts.
2486	*
2487	* @returns Number of conflicts.
2488	* @param pVM The VM Handle.
2489	*/
2490	VMMDECL(unsigned) PGMAssertNoMappingConflicts(PVM pVM)
2491	{
2492	unsigned cErrors = 0;
2493
2494	/*
2495	* Check for mapping conflicts.
2496	*/
2497	for (PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
2498	pMapping;
2499	pMapping = pMapping->CTX_SUFF(pNext))
2500	{
2501	/** @todo This is slow and should be optimized, but since it's just assertions I don't care now. */
2502	for (RTGCPTR GCPtr = pMapping->GCPtr;
2503	GCPtr <= pMapping->GCPtrLast;
2504	GCPtr += PAGE_SIZE)
2505	{
2506	int rc = PGMGstGetPage(pVM, (RTGCPTR)GCPtr, NULL, NULL);
2507	if (rc != VERR_PAGE_TABLE_NOT_PRESENT)
2508	{
2509	AssertMsgFailed(("Conflict at %RGv with %s\n", GCPtr, R3STRING(pMapping->pszDesc)));
2510	cErrors++;
2511	break;
2512	}
2513	}
2514	}
2515
2516	return cErrors;
2517	}
2518
2519
2520	/**
2521	* Asserts that everything related to the guest CR3 is correctly shadowed.
2522	*
2523	* This will call PGMAssertNoMappingConflicts() and PGMAssertHandlerAndFlagsInSync(),
2524	* and assert the correctness of the guest CR3 mapping before asserting that the
2525	* shadow page tables is in sync with the guest page tables.
2526	*
2527	* @returns Number of conflicts.
2528	* @param pVM The VM Handle.
2529	* @param cr3 The current guest CR3 register value.
2530	* @param cr4 The current guest CR4 register value.
2531	*/
2532	VMMDECL(unsigned) PGMAssertCR3(PVM pVM, uint64_t cr3, uint64_t cr4)
2533	{
2534	STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3), a);
2535	unsigned cErrors = PGM_BTH_PFN(AssertCR3, pVM)(pVM, cr3, cr4, 0, ~(RTGCPTR)0);
2536	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3), a);
2537	return cErrors;
2538	}
2539
2540	#endif /* VBOX_STRICT */

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAll.cpp@ 18279

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