PGMAll.cpp@ 19790

Last change on this file since 19790 was 19790, checked in by vboxsync, 16 years ago
Protect InvalidatePage with the pgm lock.
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1	/* $Id: PGMAll.cpp 19790 2009-05-18 14:10:49Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor - All context code.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	/*******************************************************************************
23	* Header Files *
24	*******************************************************************************/
25	#define LOG_GROUP LOG_GROUP_PGM
26	#include <VBox/pgm.h>
27	#include <VBox/cpum.h>
28	#include <VBox/selm.h>
29	#include <VBox/iom.h>
30	#include <VBox/sup.h>
31	#include <VBox/mm.h>
32	#include <VBox/stam.h>
33	#include <VBox/csam.h>
34	#include <VBox/patm.h>
35	#include <VBox/trpm.h>
36	#include <VBox/rem.h>
37	#include <VBox/em.h>
38	#include <VBox/hwaccm.h>
39	#include <VBox/hwacc_vmx.h>
40	#include "PGMInternal.h"
41	#include <VBox/vm.h>
42	#include <iprt/assert.h>
43	#include <iprt/asm.h>
44	#include <iprt/string.h>
45	#include <VBox/log.h>
46	#include <VBox/param.h>
47	#include <VBox/err.h>
48
49
50	/*******************************************************************************
51	* Structures and Typedefs *
52	*******************************************************************************/
53	/**
54	* Stated structure for PGM_GST_NAME(HandlerVirtualUpdate) that's
55	* passed to PGM_GST_NAME(VirtHandlerUpdateOne) during enumeration.
56	*/
57	typedef struct PGMHVUSTATE
58	{
59	/** The VM handle. */
60	PVM pVM;
61	/** The VMCPU handle. */
62	PVMCPU pVCpu;
63	/** The todo flags. */
64	RTUINT fTodo;
65	/** The CR4 register value. */
66	uint32_t cr4;
67	} PGMHVUSTATE, *PPGMHVUSTATE;
68
69
70	/*******************************************************************************
71	* Internal Functions *
72	*******************************************************************************/
73	DECLINLINE(int) pgmShwGetLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PX86PML4E ppPml4e, PX86PDPT ppPdpt, PX86PDPAE *ppPD);
74	DECLINLINE(int) pgmShwGetPaePoolPagePD(PPGMCPU pPGM, RTGCPTR GCPtr, PPGMPOOLPAGE *ppShwPde);
75
76	/*
77	* Shadow - 32-bit mode
78	*/
79	#define PGM_SHW_TYPE PGM_TYPE_32BIT
80	#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
81	#include "PGMAllShw.h"
82
83	/* Guest - real mode */
84	#define PGM_GST_TYPE PGM_TYPE_REAL
85	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
86	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
87	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
88	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
89	#include "PGMGstDefs.h"
90	#include "PGMAllGst.h"
91	#include "PGMAllBth.h"
92	#undef BTH_PGMPOOLKIND_PT_FOR_PT
93	#undef BTH_PGMPOOLKIND_ROOT
94	#undef PGM_BTH_NAME
95	#undef PGM_GST_TYPE
96	#undef PGM_GST_NAME
97
98	/* Guest - protected mode */
99	#define PGM_GST_TYPE PGM_TYPE_PROT
100	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
101	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
102	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
103	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
104	#include "PGMGstDefs.h"
105	#include "PGMAllGst.h"
106	#include "PGMAllBth.h"
107	#undef BTH_PGMPOOLKIND_PT_FOR_PT
108	#undef BTH_PGMPOOLKIND_ROOT
109	#undef PGM_BTH_NAME
110	#undef PGM_GST_TYPE
111	#undef PGM_GST_NAME
112
113	/* Guest - 32-bit mode */
114	#define PGM_GST_TYPE PGM_TYPE_32BIT
115	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
116	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
117	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
118	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
119	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD
120	#include "PGMGstDefs.h"
121	#include "PGMAllGst.h"
122	#include "PGMAllBth.h"
123	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
124	#undef BTH_PGMPOOLKIND_PT_FOR_PT
125	#undef BTH_PGMPOOLKIND_ROOT
126	#undef PGM_BTH_NAME
127	#undef PGM_GST_TYPE
128	#undef PGM_GST_NAME
129
130	#undef PGM_SHW_TYPE
131	#undef PGM_SHW_NAME
132
133
134	/*
135	* Shadow - PAE mode
136	*/
137	#define PGM_SHW_TYPE PGM_TYPE_PAE
138	#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
139	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
140	#include "PGMAllShw.h"
141
142	/* Guest - real mode */
143	#define PGM_GST_TYPE PGM_TYPE_REAL
144	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
145	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
146	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
147	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
148	#include "PGMGstDefs.h"
149	#include "PGMAllBth.h"
150	#undef BTH_PGMPOOLKIND_PT_FOR_PT
151	#undef BTH_PGMPOOLKIND_ROOT
152	#undef PGM_BTH_NAME
153	#undef PGM_GST_TYPE
154	#undef PGM_GST_NAME
155
156	/* Guest - protected mode */
157	#define PGM_GST_TYPE PGM_TYPE_PROT
158	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
159	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
160	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
161	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
162	#include "PGMGstDefs.h"
163	#include "PGMAllBth.h"
164	#undef BTH_PGMPOOLKIND_PT_FOR_PT
165	#undef BTH_PGMPOOLKIND_ROOT
166	#undef PGM_BTH_NAME
167	#undef PGM_GST_TYPE
168	#undef PGM_GST_NAME
169
170	/* Guest - 32-bit mode */
171	#define PGM_GST_TYPE PGM_TYPE_32BIT
172	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
173	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
174	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
175	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
176	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_FOR_32BIT
177	#include "PGMGstDefs.h"
178	#include "PGMAllBth.h"
179	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
180	#undef BTH_PGMPOOLKIND_PT_FOR_PT
181	#undef BTH_PGMPOOLKIND_ROOT
182	#undef PGM_BTH_NAME
183	#undef PGM_GST_TYPE
184	#undef PGM_GST_NAME
185
186
187	/* Guest - PAE mode */
188	#define PGM_GST_TYPE PGM_TYPE_PAE
189	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
190	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
191	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
192	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
193	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT
194	#include "PGMGstDefs.h"
195	#include "PGMAllGst.h"
196	#include "PGMAllBth.h"
197	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
198	#undef BTH_PGMPOOLKIND_PT_FOR_PT
199	#undef BTH_PGMPOOLKIND_ROOT
200	#undef PGM_BTH_NAME
201	#undef PGM_GST_TYPE
202	#undef PGM_GST_NAME
203
204	#undef PGM_SHW_TYPE
205	#undef PGM_SHW_NAME
206
207
208	#ifndef IN_RC /* AMD64 implies VT-x/AMD-V */
209	/*
210	* Shadow - AMD64 mode
211	*/
212	# define PGM_SHW_TYPE PGM_TYPE_AMD64
213	# define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
214	# include "PGMAllShw.h"
215
216	/* Guest - protected mode (only used for AMD-V nested paging in 64 bits mode) */
217	# define PGM_GST_TYPE PGM_TYPE_PROT
218	# define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
219	# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_PROT(name)
220	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
221	# define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PD_PHYS
222	# include "PGMGstDefs.h"
223	# include "PGMAllBth.h"
224	# undef BTH_PGMPOOLKIND_PT_FOR_PT
225	# undef BTH_PGMPOOLKIND_ROOT
226	# undef PGM_BTH_NAME
227	# undef PGM_GST_TYPE
228	# undef PGM_GST_NAME
229
230	# ifdef VBOX_WITH_64_BITS_GUESTS
231	/* Guest - AMD64 mode */
232	# define PGM_GST_TYPE PGM_TYPE_AMD64
233	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
234	# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
235	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
236	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
237	# define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_64BIT_PML4
238	# include "PGMGstDefs.h"
239	# include "PGMAllGst.h"
240	# include "PGMAllBth.h"
241	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
242	# undef BTH_PGMPOOLKIND_PT_FOR_PT
243	# undef BTH_PGMPOOLKIND_ROOT
244	# undef PGM_BTH_NAME
245	# undef PGM_GST_TYPE
246	# undef PGM_GST_NAME
247	# endif /* VBOX_WITH_64_BITS_GUESTS */
248
249	# undef PGM_SHW_TYPE
250	# undef PGM_SHW_NAME
251
252
253	/*
254	* Shadow - Nested paging mode
255	*/
256	# define PGM_SHW_TYPE PGM_TYPE_NESTED
257	# define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED(name)
258	# include "PGMAllShw.h"
259
260	/* Guest - real mode */
261	# define PGM_GST_TYPE PGM_TYPE_REAL
262	# define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
263	# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_REAL(name)
264	# include "PGMGstDefs.h"
265	# include "PGMAllBth.h"
266	# undef PGM_BTH_NAME
267	# undef PGM_GST_TYPE
268	# undef PGM_GST_NAME
269
270	/* Guest - protected mode */
271	# define PGM_GST_TYPE PGM_TYPE_PROT
272	# define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
273	# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PROT(name)
274	# include "PGMGstDefs.h"
275	# include "PGMAllBth.h"
276	# undef PGM_BTH_NAME
277	# undef PGM_GST_TYPE
278	# undef PGM_GST_NAME
279
280	/* Guest - 32-bit mode */
281	# define PGM_GST_TYPE PGM_TYPE_32BIT
282	# define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
283	# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT(name)
284	# include "PGMGstDefs.h"
285	# include "PGMAllBth.h"
286	# undef PGM_BTH_NAME
287	# undef PGM_GST_TYPE
288	# undef PGM_GST_NAME
289
290	/* Guest - PAE mode */
291	# define PGM_GST_TYPE PGM_TYPE_PAE
292	# define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
293	# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE(name)
294	# include "PGMGstDefs.h"
295	# include "PGMAllBth.h"
296	# undef PGM_BTH_NAME
297	# undef PGM_GST_TYPE
298	# undef PGM_GST_NAME
299
300	# ifdef VBOX_WITH_64_BITS_GUESTS
301	/* Guest - AMD64 mode */
302	# define PGM_GST_TYPE PGM_TYPE_AMD64
303	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
304	# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64(name)
305	# include "PGMGstDefs.h"
306	# include "PGMAllBth.h"
307	# undef PGM_BTH_NAME
308	# undef PGM_GST_TYPE
309	# undef PGM_GST_NAME
310	# endif /* VBOX_WITH_64_BITS_GUESTS */
311
312	# undef PGM_SHW_TYPE
313	# undef PGM_SHW_NAME
314
315
316	/*
317	* Shadow - EPT
318	*/
319	# define PGM_SHW_TYPE PGM_TYPE_EPT
320	# define PGM_SHW_NAME(name) PGM_SHW_NAME_EPT(name)
321	# include "PGMAllShw.h"
322
323	/* Guest - real mode */
324	# define PGM_GST_TYPE PGM_TYPE_REAL
325	# define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
326	# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_REAL(name)
327	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
328	# include "PGMGstDefs.h"
329	# include "PGMAllBth.h"
330	# undef BTH_PGMPOOLKIND_PT_FOR_PT
331	# undef PGM_BTH_NAME
332	# undef PGM_GST_TYPE
333	# undef PGM_GST_NAME
334
335	/* Guest - protected mode */
336	# define PGM_GST_TYPE PGM_TYPE_PROT
337	# define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
338	# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PROT(name)
339	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
340	# include "PGMGstDefs.h"
341	# include "PGMAllBth.h"
342	# undef BTH_PGMPOOLKIND_PT_FOR_PT
343	# undef PGM_BTH_NAME
344	# undef PGM_GST_TYPE
345	# undef PGM_GST_NAME
346
347	/* Guest - 32-bit mode */
348	# define PGM_GST_TYPE PGM_TYPE_32BIT
349	# define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
350	# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_32BIT(name)
351	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
352	# include "PGMGstDefs.h"
353	# include "PGMAllBth.h"
354	# undef BTH_PGMPOOLKIND_PT_FOR_PT
355	# undef PGM_BTH_NAME
356	# undef PGM_GST_TYPE
357	# undef PGM_GST_NAME
358
359	/* Guest - PAE mode */
360	# define PGM_GST_TYPE PGM_TYPE_PAE
361	# define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
362	# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PAE(name)
363	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
364	# include "PGMGstDefs.h"
365	# include "PGMAllBth.h"
366	# undef BTH_PGMPOOLKIND_PT_FOR_PT
367	# undef PGM_BTH_NAME
368	# undef PGM_GST_TYPE
369	# undef PGM_GST_NAME
370
371	# ifdef VBOX_WITH_64_BITS_GUESTS
372	/* Guest - AMD64 mode */
373	# define PGM_GST_TYPE PGM_TYPE_AMD64
374	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
375	# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_AMD64(name)
376	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
377	# include "PGMGstDefs.h"
378	# include "PGMAllBth.h"
379	# undef BTH_PGMPOOLKIND_PT_FOR_PT
380	# undef PGM_BTH_NAME
381	# undef PGM_GST_TYPE
382	# undef PGM_GST_NAME
383	# endif /* VBOX_WITH_64_BITS_GUESTS */
384
385	# undef PGM_SHW_TYPE
386	# undef PGM_SHW_NAME
387
388	#endif /* !IN_RC */
389
390
391	#ifndef IN_RING3
392	/**
393	* #PF Handler.
394	*
395	* @returns VBox status code (appropriate for trap handling and GC return).
396	* @param pVCpu VMCPU handle.
397	* @param uErr The trap error code.
398	* @param pRegFrame Trap register frame.
399	* @param pvFault The fault address.
400	*/
401	VMMDECL(int) PGMTrap0eHandler(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
402	{
403	LogFlow(("PGMTrap0eHandler: uErr=%RGu pvFault=%RGv eip=%04x:%RGv\n", uErr, pvFault, pRegFrame->cs, (RTGCPTR)pRegFrame->rip));
404	STAM_PROFILE_START(&pVCpu->pgm.s.StatRZTrap0e, a);
405	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = NULL; } );
406
407
408	#ifdef VBOX_WITH_STATISTICS
409	/*
410	* Error code stats.
411	*/
412	if (uErr & X86_TRAP_PF_US)
413	{
414	if (!(uErr & X86_TRAP_PF_P))
415	{
416	if (uErr & X86_TRAP_PF_RW)
417	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eUSNotPresentWrite);
418	else
419	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eUSNotPresentRead);
420	}
421	else if (uErr & X86_TRAP_PF_RW)
422	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eUSWrite);
423	else if (uErr & X86_TRAP_PF_RSVD)
424	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eUSReserved);
425	else if (uErr & X86_TRAP_PF_ID)
426	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eUSNXE);
427	else
428	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eUSRead);
429	}
430	else
431	{ /* Supervisor */
432	if (!(uErr & X86_TRAP_PF_P))
433	{
434	if (uErr & X86_TRAP_PF_RW)
435	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eSVNotPresentWrite);
436	else
437	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eSVNotPresentRead);
438	}
439	else if (uErr & X86_TRAP_PF_RW)
440	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eSVWrite);
441	else if (uErr & X86_TRAP_PF_ID)
442	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eSNXE);
443	else if (uErr & X86_TRAP_PF_RSVD)
444	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eSVReserved);
445	}
446	#endif /* VBOX_WITH_STATISTICS */
447
448	/*
449	* Call the worker.
450	*/
451	int rc = PGM_BTH_PFN(Trap0eHandler, pVCpu)(pVCpu, uErr, pRegFrame, pvFault);
452	if (rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
453	rc = VINF_SUCCESS;
454	STAM_STATS({ if (rc == VINF_EM_RAW_GUEST_TRAP) STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eGuestPF); });
455	STAM_STATS({ if (!pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution))
456	pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2Misc; });
457	STAM_PROFILE_STOP_EX(&pVCpu->pgm.s.StatRZTrap0e, pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution), a);
458	return rc;
459	}
460	#endif /* !IN_RING3 */
461
462
463	/**
464	* Prefetch a page
465	*
466	* Typically used to sync commonly used pages before entering raw mode
467	* after a CR3 reload.
468	*
469	* @returns VBox status code suitable for scheduling.
470	* @retval VINF_SUCCESS on success.
471	* @retval VINF_PGM_SYNC_CR3 if we're out of shadow pages or something like that.
472	* @param pVCpu VMCPU handle.
473	* @param GCPtrPage Page to invalidate.
474	*/
475	VMMDECL(int) PGMPrefetchPage(PVMCPU pVCpu, RTGCPTR GCPtrPage)
476	{
477	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_MID_Z(Stat,Prefetch), a);
478	int rc = PGM_BTH_PFN(PrefetchPage, pVCpu)(pVCpu, GCPtrPage);
479	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,Prefetch), a);
480	AssertMsg(rc == VINF_SUCCESS \|\| rc == VINF_PGM_SYNC_CR3 \|\| RT_FAILURE(rc), ("rc=%Rrc\n", rc));
481	return rc;
482	}
483
484
485	/**
486	* Gets the mapping corresponding to the specified address (if any).
487	*
488	* @returns Pointer to the mapping.
489	* @returns NULL if not
490	*
491	* @param pVM The virtual machine.
492	* @param GCPtr The guest context pointer.
493	*/
494	PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr)
495	{
496	PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
497	while (pMapping)
498	{
499	if ((uintptr_t)GCPtr < (uintptr_t)pMapping->GCPtr)
500	break;
501	if ((uintptr_t)GCPtr - (uintptr_t)pMapping->GCPtr < pMapping->cb)
502	return pMapping;
503	pMapping = pMapping->CTX_SUFF(pNext);
504	}
505	return NULL;
506	}
507
508
509	/**
510	* Verifies a range of pages for read or write access
511	*
512	* Only checks the guest's page tables
513	*
514	* @returns VBox status code.
515	* @param pVCpu VMCPU handle.
516	* @param Addr Guest virtual address to check
517	* @param cbSize Access size
518	* @param fAccess Access type (r/w, user/supervisor (X86_PTE_*))
519	* @remarks Current not in use.
520	*/
521	VMMDECL(int) PGMIsValidAccess(PVMCPU pVCpu, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess)
522	{
523	/*
524	* Validate input.
525	*/
526	if (fAccess & ~(X86_PTE_US \| X86_PTE_RW))
527	{
528	AssertMsgFailed(("PGMIsValidAccess: invalid access type %08x\n", fAccess));
529	return VERR_INVALID_PARAMETER;
530	}
531
532	uint64_t fPage;
533	int rc = PGMGstGetPage(pVCpu, (RTGCPTR)Addr, &fPage, NULL);
534	if (RT_FAILURE(rc))
535	{
536	Log(("PGMIsValidAccess: access violation for %RGv rc=%d\n", Addr, rc));
537	return VINF_EM_RAW_GUEST_TRAP;
538	}
539
540	/*
541	* Check if the access would cause a page fault
542	*
543	* Note that hypervisor page directories are not present in the guest's tables, so this check
544	* is sufficient.
545	*/
546	bool fWrite = !!(fAccess & X86_PTE_RW);
547	bool fUser = !!(fAccess & X86_PTE_US);
548	if ( !(fPage & X86_PTE_P)
549	\|\| (fWrite && !(fPage & X86_PTE_RW))
550	\|\| (fUser && !(fPage & X86_PTE_US)) )
551	{
552	Log(("PGMIsValidAccess: access violation for %RGv attr %#llx vs %d:%d\n", Addr, fPage, fWrite, fUser));
553	return VINF_EM_RAW_GUEST_TRAP;
554	}
555	if ( RT_SUCCESS(rc)
556	&& PAGE_ADDRESS(Addr) != PAGE_ADDRESS(Addr + cbSize))
557	return PGMIsValidAccess(pVCpu, Addr + PAGE_SIZE, (cbSize > PAGE_SIZE) ? cbSize - PAGE_SIZE : 1, fAccess);
558	return rc;
559	}
560
561
562	/**
563	* Verifies a range of pages for read or write access
564	*
565	* Supports handling of pages marked for dirty bit tracking and CSAM
566	*
567	* @returns VBox status code.
568	* @param pVCpu VMCPU handle.
569	* @param Addr Guest virtual address to check
570	* @param cbSize Access size
571	* @param fAccess Access type (r/w, user/supervisor (X86_PTE_*))
572	*/
573	VMMDECL(int) PGMVerifyAccess(PVMCPU pVCpu, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess)
574	{
575	PVM pVM = pVCpu->CTX_SUFF(pVM);
576
577	AssertMsg(!(fAccess & ~(X86_PTE_US \| X86_PTE_RW)), ("PGMVerifyAccess: invalid access type %08x\n", fAccess));
578
579	/*
580	* Get going.
581	*/
582	uint64_t fPageGst;
583	int rc = PGMGstGetPage(pVCpu, (RTGCPTR)Addr, &fPageGst, NULL);
584	if (RT_FAILURE(rc))
585	{
586	Log(("PGMVerifyAccess: access violation for %RGv rc=%d\n", Addr, rc));
587	return VINF_EM_RAW_GUEST_TRAP;
588	}
589
590	/*
591	* Check if the access would cause a page fault
592	*
593	* Note that hypervisor page directories are not present in the guest's tables, so this check
594	* is sufficient.
595	*/
596	const bool fWrite = !!(fAccess & X86_PTE_RW);
597	const bool fUser = !!(fAccess & X86_PTE_US);
598	if ( !(fPageGst & X86_PTE_P)
599	\|\| (fWrite && !(fPageGst & X86_PTE_RW))
600	\|\| (fUser && !(fPageGst & X86_PTE_US)) )
601	{
602	Log(("PGMVerifyAccess: access violation for %RGv attr %#llx vs %d:%d\n", Addr, fPageGst, fWrite, fUser));
603	return VINF_EM_RAW_GUEST_TRAP;
604	}
605
606	if (!HWACCMIsNestedPagingActive(pVM))
607	{
608	/*
609	* Next step is to verify if we protected this page for dirty bit tracking or for CSAM scanning
610	*/
611	rc = PGMShwGetPage(pVCpu, (RTGCPTR)Addr, NULL, NULL);
612	if ( rc == VERR_PAGE_NOT_PRESENT
613	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT)
614	{
615	/*
616	* Page is not present in our page tables.
617	* Try to sync it!
618	*/
619	Assert(X86_TRAP_PF_RW == X86_PTE_RW && X86_TRAP_PF_US == X86_PTE_US);
620	uint32_t uErr = fAccess & (X86_TRAP_PF_RW \| X86_TRAP_PF_US);
621	rc = PGM_BTH_PFN(VerifyAccessSyncPage, pVCpu)(pVCpu, Addr, fPageGst, uErr);
622	if (rc != VINF_SUCCESS)
623	return rc;
624	}
625	else
626	AssertMsg(rc == VINF_SUCCESS, ("PGMShwGetPage %RGv failed with %Rrc\n", Addr, rc));
627	}
628
629	#if 0 /* def VBOX_STRICT; triggers too often now */
630	/*
631	* This check is a bit paranoid, but useful.
632	*/
633	/** @note this will assert when writing to monitored pages (a bit annoying actually) */
634	uint64_t fPageShw;
635	rc = PGMShwGetPage(pVCpu, (RTGCPTR)Addr, &fPageShw, NULL);
636	if ( (rc == VERR_PAGE_NOT_PRESENT \|\| RT_FAILURE(rc))
637	\|\| (fWrite && !(fPageShw & X86_PTE_RW))
638	\|\| (fUser && !(fPageShw & X86_PTE_US)) )
639	{
640	AssertMsgFailed(("Unexpected access violation for %RGv! rc=%Rrc write=%d user=%d\n",
641	Addr, rc, fWrite && !(fPageShw & X86_PTE_RW), fUser && !(fPageShw & X86_PTE_US)));
642	return VINF_EM_RAW_GUEST_TRAP;
643	}
644	#endif
645
646	if ( RT_SUCCESS(rc)
647	&& ( PAGE_ADDRESS(Addr) != PAGE_ADDRESS(Addr + cbSize - 1)
648	\|\| Addr + cbSize < Addr))
649	{
650	/* Don't recursively call PGMVerifyAccess as we might run out of stack. */
651	for (;;)
652	{
653	Addr += PAGE_SIZE;
654	if (cbSize > PAGE_SIZE)
655	cbSize -= PAGE_SIZE;
656	else
657	cbSize = 1;
658	rc = PGMVerifyAccess(pVCpu, Addr, 1, fAccess);
659	if (rc != VINF_SUCCESS)
660	break;
661	if (PAGE_ADDRESS(Addr) == PAGE_ADDRESS(Addr + cbSize - 1))
662	break;
663	}
664	}
665	return rc;
666	}
667
668
669	/**
670	* Emulation of the invlpg instruction (HC only actually).
671	*
672	* @returns VBox status code, special care required.
673	* @retval VINF_PGM_SYNC_CR3 - handled.
674	* @retval VINF_EM_RAW_EMULATE_INSTR - not handled (RC only).
675	* @retval VERR_REM_FLUSHED_PAGES_OVERFLOW - not handled.
676	*
677	* @param pVCpu VMCPU handle.
678	* @param GCPtrPage Page to invalidate.
679	*
680	* @remark ASSUMES the page table entry or page directory is valid. Fairly
681	* safe, but there could be edge cases!
682	*
683	* @todo Flush page or page directory only if necessary!
684	*/
685	VMMDECL(int) PGMInvalidatePage(PVMCPU pVCpu, RTGCPTR GCPtrPage)
686	{
687	PVM pVM = pVCpu->CTX_SUFF(pVM);
688	int rc;
689	Log3(("PGMInvalidatePage: GCPtrPage=%RGv\n", GCPtrPage));
690
691	#ifndef IN_RING3
692	/*
693	* Notify the recompiler so it can record this instruction.
694	* Failure happens when it's out of space. We'll return to HC in that case.
695	*/
696	rc = REMNotifyInvalidatePage(pVM, GCPtrPage);
697	if (rc != VINF_SUCCESS)
698	return rc;
699	#endif /* !IN_RING3 */
700
701
702	#ifdef IN_RC
703	/*
704	* Check for conflicts and pending CR3 monitoring updates.
705	*/
706	if (!pVM->pgm.s.fMappingsFixed)
707	{
708	if ( pgmGetMapping(pVM, GCPtrPage)
709	&& PGMGstGetPage(pVCpu, GCPtrPage, NULL, NULL) != VERR_PAGE_TABLE_NOT_PRESENT)
710	{
711	LogFlow(("PGMGCInvalidatePage: Conflict!\n"));
712	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
713	STAM_COUNTER_INC(&pVM->pgm.s.StatRCInvlPgConflict);
714	return VINF_PGM_SYNC_CR3;
715	}
716
717	if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
718	{
719	LogFlow(("PGMGCInvalidatePage: PGM_SYNC_MONITOR_CR3 -> reinterpret instruction in R3\n"));
720	STAM_COUNTER_INC(&pVM->pgm.s.StatRCInvlPgSyncMonCR3);
721	return VINF_EM_RAW_EMULATE_INSTR;
722	}
723	}
724	#endif /* IN_RC */
725
726	/*
727	* Call paging mode specific worker.
728	*/
729	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePage), a);
730	pgmLock(pVM);
731	rc = PGM_BTH_PFN(InvalidatePage, pVCpu)(pVCpu, GCPtrPage);
732	pgmUnlock(pVM);
733	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePage), a);
734
735	#ifdef IN_RING3
736	/*
737	* Check if we have a pending update of the CR3 monitoring.
738	*/
739	if ( RT_SUCCESS(rc)
740	&& (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3))
741	{
742	pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
743	Assert(!pVM->pgm.s.fMappingsFixed);
744	}
745
746	/*
747	* Inform CSAM about the flush
748	*
749	* Note: This is to check if monitored pages have been changed; when we implement
750	* callbacks for virtual handlers, this is no longer required.
751	*/
752	CSAMR3FlushPage(pVM, GCPtrPage);
753	#endif /* IN_RING3 */
754	return rc;
755	}
756
757
758	/**
759	* Executes an instruction using the interpreter.
760	*
761	* @returns VBox status code (appropriate for trap handling and GC return).
762	* @param pVM VM handle.
763	* @param pVCpu VMCPU handle.
764	* @param pRegFrame Register frame.
765	* @param pvFault Fault address.
766	*/
767	VMMDECL(int) PGMInterpretInstruction(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
768	{
769	uint32_t cb;
770	int rc = EMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault, &cb);
771	if (rc == VERR_EM_INTERPRETER)
772	rc = VINF_EM_RAW_EMULATE_INSTR;
773	if (rc != VINF_SUCCESS)
774	Log(("PGMInterpretInstruction: returns %Rrc (pvFault=%RGv)\n", rc, pvFault));
775	return rc;
776	}
777
778
779	/**
780	* Gets effective page information (from the VMM page directory).
781	*
782	* @returns VBox status.
783	* @param pVCpu VMCPU handle.
784	* @param GCPtr Guest Context virtual address of the page.
785	* @param pfFlags Where to store the flags. These are X86_PTE_*.
786	* @param pHCPhys Where to store the HC physical address of the page.
787	* This is page aligned.
788	* @remark You should use PGMMapGetPage() for pages in a mapping.
789	*/
790	VMMDECL(int) PGMShwGetPage(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys)
791	{
792	return PGM_SHW_PFN(GetPage, pVCpu)(pVCpu, GCPtr, pfFlags, pHCPhys);
793	}
794
795
796	/**
797	* Sets (replaces) the page flags for a range of pages in the shadow context.
798	*
799	* @returns VBox status.
800	* @param pVCpu VMCPU handle.
801	* @param GCPtr The address of the first page.
802	* @param cb The size of the range in bytes.
803	* @param fFlags Page flags X86_PTE_*, excluding the page mask of course.
804	* @remark You must use PGMMapSetPage() for pages in a mapping.
805	*/
806	VMMDECL(int) PGMShwSetPage(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags)
807	{
808	return PGMShwModifyPage(pVCpu, GCPtr, cb, fFlags, 0);
809	}
810
811
812	/**
813	* Modify page flags for a range of pages in the shadow context.
814	*
815	* The existing flags are ANDed with the fMask and ORed with the fFlags.
816	*
817	* @returns VBox status code.
818	* @param pVCpu VMCPU handle.
819	* @param GCPtr Virtual address of the first page in the range.
820	* @param cb Size (in bytes) of the range to apply the modification to.
821	* @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
822	* @param fMask The AND mask - page flags X86_PTE_*.
823	* Be very CAREFUL when ~'ing constants which could be 32-bit!
824	* @remark You must use PGMMapModifyPage() for pages in a mapping.
825	*/
826	VMMDECL(int) PGMShwModifyPage(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
827	{
828	AssertMsg(!(fFlags & X86_PTE_PAE_PG_MASK), ("fFlags=%#llx\n", fFlags));
829	Assert(cb);
830
831	/*
832	* Align the input.
833	*/
834	cb += GCPtr & PAGE_OFFSET_MASK;
835	cb = RT_ALIGN_Z(cb, PAGE_SIZE);
836	GCPtr = (GCPtr & PAGE_BASE_GC_MASK); /** @todo this ain't necessary, right... */
837
838	/*
839	* Call worker.
840	*/
841	return PGM_SHW_PFN(ModifyPage, pVCpu)(pVCpu, GCPtr, cb, fFlags, fMask);
842	}
843
844	/**
845	* Gets the shadow page directory for the specified address, PAE.
846	*
847	* @returns Pointer to the shadow PD.
848	* @param pVCpu The VMCPU handle.
849	* @param GCPtr The address.
850	* @param pGstPdpe Guest PDPT entry
851	* @param ppPD Receives address of page directory
852	*/
853	int pgmShwSyncPaePDPtr(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDPE pGstPdpe, PX86PDPAE *ppPD)
854	{
855	const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
856	PX86PDPT pPdpt = pgmShwGetPaePDPTPtr(&pVCpu->pgm.s);
857	PX86PDPE pPdpe = &pPdpt->a[iPdPt];
858	PVM pVM = pVCpu->CTX_SUFF(pVM);
859	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
860	PPGMPOOLPAGE pShwPage;
861	int rc;
862
863	/* Allocate page directory if not present. */
864	if ( !pPdpe->n.u1Present
865	&& !(pPdpe->u & X86_PDPE_PG_MASK))
866	{
867	bool fNestedPaging = HWACCMIsNestedPagingActive(pVM);
868	bool fPaging = !!(CPUMGetGuestCR0(pVCpu) & X86_CR0_PG);
869	RTGCPTR64 GCPdPt;
870	PGMPOOLKIND enmKind;
871
872	# if defined(IN_RC)
873	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
874	PGMDynLockHCPage(pVM, (uint8_t *)pPdpe);
875	# endif
876
877	if (fNestedPaging \|\| !fPaging)
878	{
879	/* AMD-V nested paging or real/protected mode without paging */
880	GCPdPt = (RTGCPTR64)iPdPt << X86_PDPT_SHIFT;
881	enmKind = PGMPOOLKIND_PAE_PD_PHYS;
882	}
883	else
884	{
885	Assert(pGstPdpe);
886
887	if (CPUMGetGuestCR4(pVCpu) & X86_CR4_PAE)
888	{
889	if (!pGstPdpe->n.u1Present)
890	{
891	/* PD not present; guest must reload CR3 to change it.
892	* No need to monitor anything in this case.
893	*/
894	Assert(!HWACCMIsEnabled(pVM));
895
896	GCPdPt = pGstPdpe->u & X86_PDPE_PG_MASK;
897	enmKind = PGMPOOLKIND_PAE_PD_PHYS;
898	pGstPdpe->n.u1Present = 1;
899	}
900	else
901	{
902	GCPdPt = pGstPdpe->u & X86_PDPE_PG_MASK;
903	enmKind = PGMPOOLKIND_PAE_PD_FOR_PAE_PD;
904	}
905	}
906	else
907	{
908	GCPdPt = CPUMGetGuestCR3(pVCpu);
909	enmKind = (PGMPOOLKIND)(PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD + iPdPt);
910	}
911	}
912
913	/* Create a reference back to the PDPT by using the index in its shadow page. */
914	rc = pgmPoolAlloc(pVM, GCPdPt, enmKind, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPdPt, &pShwPage);
915	AssertRCReturn(rc, rc);
916
917	/* The PD was cached or created; hook it up now. */
918	pPdpe->u \|= pShwPage->Core.Key
919	\| (pGstPdpe->u & ~(X86_PDPE_PG_MASK \| X86_PDPE_AVL_MASK \| X86_PDPE_PCD \| X86_PDPE_PWT));
920
921	# if defined(IN_RC)
922	/* In 32 bits PAE mode we must invalidate the TLB when changing a PDPT entry; the CPU fetches them only during cr3 load, so any
923	* non-present PDPT will continue to cause page faults.
924	*/
925	ASMReloadCR3();
926	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdpe);
927	# endif
928	}
929	else
930	{
931	pShwPage = pgmPoolGetPage(pPool, pPdpe->u & X86_PDPE_PG_MASK);
932	AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
933	Assert((pPdpe->u & X86_PDPE_PG_MASK) == pShwPage->Core.Key);
934
935	pgmPoolCacheUsed(pPool, pShwPage);
936	}
937	*ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
938	return VINF_SUCCESS;
939	}
940
941
942	/**
943	* Gets the pointer to the shadow page directory entry for an address, PAE.
944	*
945	* @returns Pointer to the PDE.
946	* @param pPGM Pointer to the PGMCPU instance data.
947	* @param GCPtr The address.
948	* @param ppShwPde Receives the address of the pgm pool page for the shadow page directory
949	*/
950	DECLINLINE(int) pgmShwGetPaePoolPagePD(PPGMCPU pPGM, RTGCPTR GCPtr, PPGMPOOLPAGE *ppShwPde)
951	{
952	const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
953	PX86PDPT pPdpt = pgmShwGetPaePDPTPtr(pPGM);
954	AssertReturn(pPdpt, VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT); /* can't happen */
955	if (!pPdpt->a[iPdPt].n.u1Present)
956	{
957	LogFlow(("pgmShwGetPaePoolPagePD: PD %d not present (%RX64)\n", iPdPt, pPdpt->a[iPdPt].u));
958	return VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT;
959	}
960	AssertMsg(pPdpt->a[iPdPt].u & X86_PDPE_PG_MASK, ("GCPtr=%RGv\n", GCPtr));
961
962	/* Fetch the pgm pool shadow descriptor. */
963	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(PGMCPU2PGM(pPGM)->CTX_SUFF(pPool), pPdpt->a[iPdPt].u & X86_PDPE_PG_MASK);
964	AssertReturn(pShwPde, VERR_INTERNAL_ERROR);
965
966	*ppShwPde = pShwPde;
967	return VINF_SUCCESS;
968	}
969
970	#ifndef IN_RC
971
972	/**
973	* Syncs the SHADOW page directory pointer for the specified address.
974	*
975	* Allocates backing pages in case the PDPT or PML4 entry is missing.
976	*
977	* The caller is responsible for making sure the guest has a valid PD before
978	* calling this function.
979	*
980	* @returns VBox status.
981	* @param pVCpu VMCPU handle.
982	* @param GCPtr The address.
983	* @param pGstPml4e Guest PML4 entry
984	* @param pGstPdpe Guest PDPT entry
985	* @param ppPD Receives address of page directory
986	*/
987	int pgmShwSyncLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PX86PML4E pGstPml4e, PX86PDPE pGstPdpe, PX86PDPAE *ppPD)
988	{
989	PPGMCPU pPGM = &pVCpu->pgm.s;
990	PVM pVM = pVCpu->CTX_SUFF(pVM);
991	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
992	const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
993	PX86PML4E pPml4e = pgmShwGetLongModePML4EPtr(pPGM, iPml4);
994	bool fNestedPaging = HWACCMIsNestedPagingActive(pVM);
995	bool fPaging = !!(CPUMGetGuestCR0(pVCpu) & X86_CR0_PG);
996	PPGMPOOLPAGE pShwPage;
997	int rc;
998
999	/* Allocate page directory pointer table if not present. */
1000	if ( !pPml4e->n.u1Present
1001	&& !(pPml4e->u & X86_PML4E_PG_MASK))
1002	{
1003	RTGCPTR64 GCPml4;
1004	PGMPOOLKIND enmKind;
1005
1006	Assert(pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
1007
1008	if (fNestedPaging \|\| !fPaging)
1009	{
1010	/* AMD-V nested paging or real/protected mode without paging */
1011	GCPml4 = (RTGCPTR64)iPml4 << X86_PML4_SHIFT;
1012	enmKind = PGMPOOLKIND_64BIT_PDPT_FOR_PHYS;
1013	}
1014	else
1015	{
1016	Assert(pGstPml4e && pGstPdpe);
1017
1018	GCPml4 = pGstPml4e->u & X86_PML4E_PG_MASK;
1019	enmKind = PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT;
1020	}
1021
1022	/* Create a reference back to the PDPT by using the index in its shadow page. */
1023	rc = pgmPoolAlloc(pVM, GCPml4, enmKind, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPml4, &pShwPage);
1024	AssertRCReturn(rc, rc);
1025	}
1026	else
1027	{
1028	pShwPage = pgmPoolGetPage(pPool, pPml4e->u & X86_PML4E_PG_MASK);
1029	AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1030
1031	pgmPoolCacheUsed(pPool, pShwPage);
1032	}
1033	/* The PDPT was cached or created; hook it up now. */
1034	pPml4e->u \|= pShwPage->Core.Key
1035	\| (pGstPml4e->u & ~(X86_PML4E_PG_MASK \| X86_PML4E_AVL_MASK \| X86_PML4E_PCD \| X86_PML4E_PWT));
1036
1037	const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1038	PX86PDPT pPdpt = (PX86PDPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1039	PX86PDPE pPdpe = &pPdpt->a[iPdPt];
1040
1041	/* Allocate page directory if not present. */
1042	if ( !pPdpe->n.u1Present
1043	&& !(pPdpe->u & X86_PDPE_PG_MASK))
1044	{
1045	RTGCPTR64 GCPdPt;
1046	PGMPOOLKIND enmKind;
1047
1048	if (fNestedPaging \|\| !fPaging)
1049	{
1050	/* AMD-V nested paging or real/protected mode without paging */
1051	GCPdPt = (RTGCPTR64)iPdPt << X86_PDPT_SHIFT;
1052	enmKind = PGMPOOLKIND_64BIT_PD_FOR_PHYS;
1053	}
1054	else
1055	{
1056	Assert(pGstPdpe);
1057
1058	GCPdPt = pGstPdpe->u & X86_PDPE_PG_MASK;
1059	enmKind = PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD;
1060	}
1061
1062	/* Create a reference back to the PDPT by using the index in its shadow page. */
1063	rc = pgmPoolAlloc(pVM, GCPdPt, enmKind, pShwPage->idx, iPdPt, &pShwPage);
1064	AssertRCReturn(rc, rc);
1065	}
1066	else
1067	{
1068	pShwPage = pgmPoolGetPage(pPool, pPdpe->u & X86_PDPE_PG_MASK);
1069	AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1070
1071	pgmPoolCacheUsed(pPool, pShwPage);
1072	}
1073	/* The PD was cached or created; hook it up now. */
1074	pPdpe->u \|= pShwPage->Core.Key
1075	\| (pGstPdpe->u & ~(X86_PDPE_PG_MASK \| X86_PDPE_AVL_MASK \| X86_PDPE_PCD \| X86_PDPE_PWT));
1076
1077	*ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1078	return VINF_SUCCESS;
1079	}
1080
1081
1082	/**
1083	* Gets the SHADOW page directory pointer for the specified address (long mode).
1084	*
1085	* @returns VBox status.
1086	* @param pVCpu VMCPU handle.
1087	* @param GCPtr The address.
1088	* @param ppPdpt Receives address of pdpt
1089	* @param ppPD Receives address of page directory
1090	*/
1091	DECLINLINE(int) pgmShwGetLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PX86PML4E ppPml4e, PX86PDPT ppPdpt, PX86PDPAE *ppPD)
1092	{
1093	PPGMCPU pPGM = &pVCpu->pgm.s;
1094	const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
1095	PCX86PML4E pPml4e = pgmShwGetLongModePML4EPtr(pPGM, iPml4);
1096	AssertReturn(pPml4e, VERR_INTERNAL_ERROR);
1097	if (ppPml4e)
1098	*ppPml4e = (PX86PML4E)pPml4e;
1099
1100	Log4(("pgmShwGetLongModePDPtr %VGv (%VHv) %RX64\n", GCPtr, pPml4e, pPml4e->u));
1101
1102	if (!pPml4e->n.u1Present)
1103	return VERR_PAGE_MAP_LEVEL4_NOT_PRESENT;
1104
1105	PVM pVM = pVCpu->CTX_SUFF(pVM);
1106	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1107	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPml4e->u & X86_PML4E_PG_MASK);
1108	AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1109
1110	const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1111	PCX86PDPT pPdpt = *ppPdpt = (PX86PDPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1112	if (!pPdpt->a[iPdPt].n.u1Present)
1113	return VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT;
1114
1115	pShwPage = pgmPoolGetPage(pPool, pPdpt->a[iPdPt].u & X86_PDPE_PG_MASK);
1116	AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1117
1118	*ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1119	return VINF_SUCCESS;
1120	}
1121
1122
1123	/**
1124	* Syncs the SHADOW EPT page directory pointer for the specified address. Allocates
1125	* backing pages in case the PDPT or PML4 entry is missing.
1126	*
1127	* @returns VBox status.
1128	* @param pVCpu VMCPU handle.
1129	* @param GCPtr The address.
1130	* @param ppPdpt Receives address of pdpt
1131	* @param ppPD Receives address of page directory
1132	*/
1133	int pgmShwGetEPTPDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PEPTPDPT ppPdpt, PEPTPD ppPD)
1134	{
1135	PPGMCPU pPGM = &pVCpu->pgm.s;
1136	PVM pVM = pVCpu->CTX_SUFF(pVM);
1137	const unsigned iPml4 = (GCPtr >> EPT_PML4_SHIFT) & EPT_PML4_MASK;
1138	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1139	PEPTPML4 pPml4;
1140	PEPTPML4E pPml4e;
1141	PPGMPOOLPAGE pShwPage;
1142	int rc;
1143
1144	Assert(HWACCMIsNestedPagingActive(pVM));
1145
1146	pPml4 = (PEPTPML4)PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
1147	Assert(pPml4);
1148
1149	/* Allocate page directory pointer table if not present. */
1150	pPml4e = &pPml4->a[iPml4];
1151	if ( !pPml4e->n.u1Present
1152	&& !(pPml4e->u & EPT_PML4E_PG_MASK))
1153	{
1154	Assert(!(pPml4e->u & EPT_PML4E_PG_MASK));
1155	RTGCPTR64 GCPml4 = (RTGCPTR64)iPml4 << EPT_PML4_SHIFT;
1156
1157	rc = pgmPoolAlloc(pVM, GCPml4, PGMPOOLKIND_EPT_PDPT_FOR_PHYS, PGMPOOL_IDX_NESTED_ROOT, iPml4, &pShwPage);
1158	AssertRCReturn(rc, rc);
1159	}
1160	else
1161	{
1162	pShwPage = pgmPoolGetPage(pPool, pPml4e->u & EPT_PML4E_PG_MASK);
1163	AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1164
1165	pgmPoolCacheUsed(pPool, pShwPage);
1166	}
1167	/* The PDPT was cached or created; hook it up now and fill with the default value. */
1168	pPml4e->u = pShwPage->Core.Key;
1169	pPml4e->n.u1Present = 1;
1170	pPml4e->n.u1Write = 1;
1171	pPml4e->n.u1Execute = 1;
1172
1173	const unsigned iPdPt = (GCPtr >> EPT_PDPT_SHIFT) & EPT_PDPT_MASK;
1174	PEPTPDPT pPdpt = (PEPTPDPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1175	PEPTPDPTE pPdpe = &pPdpt->a[iPdPt];
1176
1177	if (ppPdpt)
1178	*ppPdpt = pPdpt;
1179
1180	/* Allocate page directory if not present. */
1181	if ( !pPdpe->n.u1Present
1182	&& !(pPdpe->u & EPT_PDPTE_PG_MASK))
1183	{
1184	RTGCPTR64 GCPdPt = (RTGCPTR64)iPdPt << EPT_PDPT_SHIFT;
1185
1186	rc = pgmPoolAlloc(pVM, GCPdPt, PGMPOOLKIND_64BIT_PD_FOR_PHYS, pShwPage->idx, iPdPt, &pShwPage);
1187	AssertRCReturn(rc, rc);
1188	}
1189	else
1190	{
1191	pShwPage = pgmPoolGetPage(pPool, pPdpe->u & EPT_PDPTE_PG_MASK);
1192	AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1193
1194	pgmPoolCacheUsed(pPool, pShwPage);
1195	}
1196	/* The PD was cached or created; hook it up now and fill with the default value. */
1197	pPdpe->u = pShwPage->Core.Key;
1198	pPdpe->n.u1Present = 1;
1199	pPdpe->n.u1Write = 1;
1200	pPdpe->n.u1Execute = 1;
1201
1202	*ppPD = (PEPTPD)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1203	return VINF_SUCCESS;
1204	}
1205
1206	#endif /* IN_RC */
1207
1208	/**
1209	* Gets effective Guest OS page information.
1210	*
1211	* When GCPtr is in a big page, the function will return as if it was a normal
1212	* 4KB page. If the need for distinguishing between big and normal page becomes
1213	* necessary at a later point, a PGMGstGetPage() will be created for that
1214	* purpose.
1215	*
1216	* @returns VBox status.
1217	* @param pVCpu VMCPU handle.
1218	* @param GCPtr Guest Context virtual address of the page.
1219	* @param pfFlags Where to store the flags. These are X86_PTE_*, even for big pages.
1220	* @param pGCPhys Where to store the GC physical address of the page.
1221	* This is page aligned. The fact that the
1222	*/
1223	VMMDECL(int) PGMGstGetPage(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys)
1224	{
1225	return PGM_GST_PFN(GetPage, pVCpu)(pVCpu, GCPtr, pfFlags, pGCPhys);
1226	}
1227
1228
1229	/**
1230	* Checks if the page is present.
1231	*
1232	* @returns true if the page is present.
1233	* @returns false if the page is not present.
1234	* @param pVCpu VMCPU handle.
1235	* @param GCPtr Address within the page.
1236	*/
1237	VMMDECL(bool) PGMGstIsPagePresent(PVMCPU pVCpu, RTGCPTR GCPtr)
1238	{
1239	int rc = PGMGstGetPage(pVCpu, GCPtr, NULL, NULL);
1240	return RT_SUCCESS(rc);
1241	}
1242
1243
1244	/**
1245	* Sets (replaces) the page flags for a range of pages in the guest's tables.
1246	*
1247	* @returns VBox status.
1248	* @param pVCpu VMCPU handle.
1249	* @param GCPtr The address of the first page.
1250	* @param cb The size of the range in bytes.
1251	* @param fFlags Page flags X86_PTE_*, excluding the page mask of course.
1252	*/
1253	VMMDECL(int) PGMGstSetPage(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags)
1254	{
1255	return PGMGstModifyPage(pVCpu, GCPtr, cb, fFlags, 0);
1256	}
1257
1258
1259	/**
1260	* Modify page flags for a range of pages in the guest's tables
1261	*
1262	* The existing flags are ANDed with the fMask and ORed with the fFlags.
1263	*
1264	* @returns VBox status code.
1265	* @param pVCpu VMCPU handle.
1266	* @param GCPtr Virtual address of the first page in the range.
1267	* @param cb Size (in bytes) of the range to apply the modification to.
1268	* @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
1269	* @param fMask The AND mask - page flags X86_PTE_*, excluding the page mask of course.
1270	* Be very CAREFUL when ~'ing constants which could be 32-bit!
1271	*/
1272	VMMDECL(int) PGMGstModifyPage(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
1273	{
1274	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_MID_Z(Stat,GstModifyPage), a);
1275
1276	/*
1277	* Validate input.
1278	*/
1279	AssertMsg(!(fFlags & X86_PTE_PAE_PG_MASK), ("fFlags=%#llx\n", fFlags));
1280	Assert(cb);
1281
1282	LogFlow(("PGMGstModifyPage %RGv %d bytes fFlags=%08llx fMask=%08llx\n", GCPtr, cb, fFlags, fMask));
1283
1284	/*
1285	* Adjust input.
1286	*/
1287	cb += GCPtr & PAGE_OFFSET_MASK;
1288	cb = RT_ALIGN_Z(cb, PAGE_SIZE);
1289	GCPtr = (GCPtr & PAGE_BASE_GC_MASK);
1290
1291	/*
1292	* Call worker.
1293	*/
1294	int rc = PGM_GST_PFN(ModifyPage, pVCpu)(pVCpu, GCPtr, cb, fFlags, fMask);
1295
1296	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,GstModifyPage), a);
1297	return rc;
1298	}
1299
1300	#ifdef IN_RING3
1301
1302	/**
1303	* Performs the lazy mapping of the 32-bit guest PD.
1304	*
1305	* @returns Pointer to the mapping.
1306	* @param pPGM The PGM instance data.
1307	*/
1308	PX86PD pgmGstLazyMap32BitPD(PPGMCPU pPGM)
1309	{
1310	Assert(!pPGM->CTX_SUFF(pGst32BitPd));
1311	PVM pVM = PGMCPU2VM(pPGM);
1312	pgmLock(pVM);
1313
1314	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, pPGM->GCPhysCR3);
1315	AssertReturn(pPage, NULL);
1316
1317	RTHCPTR HCPtrGuestCR3;
1318	int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, pPGM->GCPhysCR3 & X86_CR3_PAGE_MASK, (void **)&HCPtrGuestCR3);
1319	AssertRCReturn(rc, NULL);
1320
1321	pPGM->pGst32BitPdR3 = (R3PTRTYPE(PX86PD))HCPtrGuestCR3;
1322	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1323	pPGM->pGst32BitPdR0 = (R0PTRTYPE(PX86PD))HCPtrGuestCR3;
1324	# endif
1325
1326	pgmUnlock(pVM);
1327	return pPGM->CTX_SUFF(pGst32BitPd);
1328	}
1329
1330
1331	/**
1332	* Performs the lazy mapping of the PAE guest PDPT.
1333	*
1334	* @returns Pointer to the mapping.
1335	* @param pPGM The PGM instance data.
1336	*/
1337	PX86PDPT pgmGstLazyMapPaePDPT(PPGMCPU pPGM)
1338	{
1339	Assert(!pPGM->CTX_SUFF(pGstPaePdpt));
1340	PVM pVM = PGMCPU2VM(pPGM);
1341	pgmLock(pVM);
1342
1343	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, pPGM->GCPhysCR3);
1344	AssertReturn(pPage, NULL);
1345
1346	RTHCPTR HCPtrGuestCR3;
1347	int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, pPGM->GCPhysCR3 & X86_CR3_PAE_PAGE_MASK, (void **)&HCPtrGuestCR3);
1348	AssertRCReturn(rc, NULL);
1349
1350	pPGM->pGstPaePdptR3 = (R3PTRTYPE(PX86PDPT))HCPtrGuestCR3;
1351	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1352	pPGM->pGstPaePdptR0 = (R0PTRTYPE(PX86PDPT))HCPtrGuestCR3;
1353	# endif
1354
1355	pgmUnlock(pVM);
1356	return pPGM->CTX_SUFF(pGstPaePdpt);
1357	}
1358
1359	#endif /* IN_RING3 */
1360
1361	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
1362	/**
1363	* Performs the lazy mapping / updating of a PAE guest PD.
1364	*
1365	* @returns Pointer to the mapping.
1366	* @param pPGM The PGM instance data.
1367	* @param iPdpt Which PD entry to map (0..3).
1368	*/
1369	PX86PDPAE pgmGstLazyMapPaePD(PPGMCPU pPGM, uint32_t iPdpt)
1370	{
1371	PVM pVM = PGMCPU2VM(pPGM);
1372	pgmLock(pVM);
1373
1374	PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
1375	Assert(pGuestPDPT);
1376	Assert(pGuestPDPT->a[iPdpt].n.u1Present);
1377	RTGCPHYS GCPhys = pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK;
1378	bool const fChanged = pPGM->aGCPhysGstPaePDs[iPdpt] != GCPhys;
1379
1380	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, GCPhys);
1381	if (RT_LIKELY(pPage))
1382	{
1383	int rc = VINF_SUCCESS;
1384	RTRCPTR RCPtr = NIL_RTRCPTR;
1385	RTHCPTR HCPtr = NIL_RTHCPTR;
1386	#if !defined(IN_RC) && !defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1387	rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, &HCPtr);
1388	AssertRC(rc);
1389	#endif
1390	if (RT_SUCCESS(rc) && fChanged)
1391	{
1392	RCPtr = (RTRCPTR)(RTRCUINTPTR)(pVM->pgm.s.GCPtrCR3Mapping + (1 + iPdpt) * PAGE_SIZE);
1393	rc = PGMMap(pVM, (RTRCUINTPTR)RCPtr, PGM_PAGE_GET_HCPHYS(pPage), PAGE_SIZE, 0);
1394	}
1395	if (RT_SUCCESS(rc))
1396	{
1397	pPGM->apGstPaePDsR3[iPdpt] = (R3PTRTYPE(PX86PDPAE))HCPtr;
1398	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1399	pPGM->apGstPaePDsR0[iPdpt] = (R0PTRTYPE(PX86PDPAE))HCPtr;
1400	# endif
1401	if (fChanged)
1402	{
1403	pPGM->aGCPhysGstPaePDs[iPdpt] = GCPhys;
1404	pPGM->apGstPaePDsRC[iPdpt] = (RCPTRTYPE(PX86PDPAE))RCPtr;
1405	}
1406
1407	pgmUnlock(pVM);
1408	return pPGM->CTX_SUFF(apGstPaePDs)[iPdpt];
1409	}
1410	}
1411
1412	/* Invalid page or some failure, invalidate the entry. */
1413	pPGM->aGCPhysGstPaePDs[iPdpt] = NIL_RTGCPHYS;
1414	pPGM->apGstPaePDsR3[iPdpt] = 0;
1415	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1416	pPGM->apGstPaePDsR0[iPdpt] = 0;
1417	# endif
1418	pPGM->apGstPaePDsRC[iPdpt] = 0;
1419
1420	pgmUnlock(pVM);
1421	return NULL;
1422	}
1423	#endif /* !VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
1424
1425
1426	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R3
1427	/**
1428	* Performs the lazy mapping of the 32-bit guest PD.
1429	*
1430	* @returns Pointer to the mapping.
1431	* @param pPGM The PGM instance data.
1432	*/
1433	PX86PML4 pgmGstLazyMapPml4(PPGMCPU pPGM)
1434	{
1435	Assert(!pPGM->CTX_SUFF(pGstAmd64Pml4));
1436	PVM pVM = PGMCPU2VM(pPGM);
1437	pgmLock(pVM);
1438
1439	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, pPGM->GCPhysCR3);
1440	AssertReturn(pPage, NULL);
1441
1442	RTHCPTR HCPtrGuestCR3;
1443	int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, pPGM->GCPhysCR3 & X86_CR3_AMD64_PAGE_MASK, (void **)&HCPtrGuestCR3);
1444	AssertRCReturn(rc, NULL);
1445
1446	pPGM->pGstAmd64Pml4R3 = (R3PTRTYPE(PX86PML4))HCPtrGuestCR3;
1447	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1448	pPGM->pGstAmd64Pml4R0 = (R0PTRTYPE(PX86PML4))HCPtrGuestCR3;
1449	# endif
1450
1451	pgmUnlock(pVM);
1452	return pPGM->CTX_SUFF(pGstAmd64Pml4);
1453	}
1454	#endif /* VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R3 */
1455
1456
1457	/**
1458	* Gets the specified page directory pointer table entry.
1459	*
1460	* @returns PDP entry
1461	* @param pVCpu VMCPU handle.
1462	* @param iPdpt PDPT index
1463	*/
1464	VMMDECL(X86PDPE) PGMGstGetPaePDPtr(PVMCPU pVCpu, unsigned iPdpt)
1465	{
1466	Assert(iPdpt <= 3);
1467	return pgmGstGetPaePDPTPtr(&pVCpu->pgm.s)->a[iPdpt & 3];
1468	}
1469
1470
1471	/**
1472	* Gets the current CR3 register value for the shadow memory context.
1473	* @returns CR3 value.
1474	* @param pVCpu VMCPU handle.
1475	*/
1476	VMMDECL(RTHCPHYS) PGMGetHyperCR3(PVMCPU pVCpu)
1477	{
1478	PPGMPOOLPAGE pPoolPage = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
1479	AssertPtrReturn(pPoolPage, 0);
1480	return pPoolPage->Core.Key;
1481	}
1482
1483
1484	/**
1485	* Gets the current CR3 register value for the nested memory context.
1486	* @returns CR3 value.
1487	* @param pVCpu VMCPU handle.
1488	*/
1489	VMMDECL(RTHCPHYS) PGMGetNestedCR3(PVMCPU pVCpu, PGMMODE enmShadowMode)
1490	{
1491	Assert(pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
1492	return pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->Core.Key;
1493	}
1494
1495
1496	/**
1497	* Gets the current CR3 register value for the HC intermediate memory context.
1498	* @returns CR3 value.
1499	* @param pVM The VM handle.
1500	*/
1501	VMMDECL(RTHCPHYS) PGMGetInterHCCR3(PVM pVM)
1502	{
1503	switch (pVM->pgm.s.enmHostMode)
1504	{
1505	case SUPPAGINGMODE_32_BIT:
1506	case SUPPAGINGMODE_32_BIT_GLOBAL:
1507	return pVM->pgm.s.HCPhysInterPD;
1508
1509	case SUPPAGINGMODE_PAE:
1510	case SUPPAGINGMODE_PAE_GLOBAL:
1511	case SUPPAGINGMODE_PAE_NX:
1512	case SUPPAGINGMODE_PAE_GLOBAL_NX:
1513	return pVM->pgm.s.HCPhysInterPaePDPT;
1514
1515	case SUPPAGINGMODE_AMD64:
1516	case SUPPAGINGMODE_AMD64_GLOBAL:
1517	case SUPPAGINGMODE_AMD64_NX:
1518	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1519	return pVM->pgm.s.HCPhysInterPaePDPT;
1520
1521	default:
1522	AssertMsgFailed(("enmHostMode=%d\n", pVM->pgm.s.enmHostMode));
1523	return ~0;
1524	}
1525	}
1526
1527
1528	/**
1529	* Gets the current CR3 register value for the RC intermediate memory context.
1530	* @returns CR3 value.
1531	* @param pVM The VM handle.
1532	* @param pVCpu VMCPU handle.
1533	*/
1534	VMMDECL(RTHCPHYS) PGMGetInterRCCR3(PVM pVM, PVMCPU pVCpu)
1535	{
1536	switch (pVCpu->pgm.s.enmShadowMode)
1537	{
1538	case PGMMODE_32_BIT:
1539	return pVM->pgm.s.HCPhysInterPD;
1540
1541	case PGMMODE_PAE:
1542	case PGMMODE_PAE_NX:
1543	return pVM->pgm.s.HCPhysInterPaePDPT;
1544
1545	case PGMMODE_AMD64:
1546	case PGMMODE_AMD64_NX:
1547	return pVM->pgm.s.HCPhysInterPaePML4;
1548
1549	case PGMMODE_EPT:
1550	case PGMMODE_NESTED:
1551	return 0; /* not relevant */
1552
1553	default:
1554	AssertMsgFailed(("enmShadowMode=%d\n", pVCpu->pgm.s.enmShadowMode));
1555	return ~0;
1556	}
1557	}
1558
1559
1560	/**
1561	* Gets the CR3 register value for the 32-Bit intermediate memory context.
1562	* @returns CR3 value.
1563	* @param pVM The VM handle.
1564	*/
1565	VMMDECL(RTHCPHYS) PGMGetInter32BitCR3(PVM pVM)
1566	{
1567	return pVM->pgm.s.HCPhysInterPD;
1568	}
1569
1570
1571	/**
1572	* Gets the CR3 register value for the PAE intermediate memory context.
1573	* @returns CR3 value.
1574	* @param pVM The VM handle.
1575	*/
1576	VMMDECL(RTHCPHYS) PGMGetInterPaeCR3(PVM pVM)
1577	{
1578	return pVM->pgm.s.HCPhysInterPaePDPT;
1579	}
1580
1581
1582	/**
1583	* Gets the CR3 register value for the AMD64 intermediate memory context.
1584	* @returns CR3 value.
1585	* @param pVM The VM handle.
1586	*/
1587	VMMDECL(RTHCPHYS) PGMGetInterAmd64CR3(PVM pVM)
1588	{
1589	return pVM->pgm.s.HCPhysInterPaePML4;
1590	}
1591
1592
1593	/**
1594	* Performs and schedules necessary updates following a CR3 load or reload.
1595	*
1596	* This will normally involve mapping the guest PD or nPDPT
1597	*
1598	* @returns VBox status code.
1599	* @retval VINF_PGM_SYNC_CR3 if monitoring requires a CR3 sync. This can
1600	* safely be ignored and overridden since the FF will be set too then.
1601	* @param pVCpu VMCPU handle.
1602	* @param cr3 The new cr3.
1603	* @param fGlobal Indicates whether this is a global flush or not.
1604	*/
1605	VMMDECL(int) PGMFlushTLB(PVMCPU pVCpu, uint64_t cr3, bool fGlobal)
1606	{
1607	PVM pVM = pVCpu->CTX_SUFF(pVM);
1608
1609	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_MID_Z(Stat,FlushTLB), a);
1610
1611	/*
1612	* Always flag the necessary updates; necessary for hardware acceleration
1613	*/
1614	/** @todo optimize this, it shouldn't always be necessary. */
1615	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
1616	if (fGlobal)
1617	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
1618	LogFlow(("PGMFlushTLB: cr3=%RX64 OldCr3=%RX64 fGlobal=%d\n", cr3, pVCpu->pgm.s.GCPhysCR3, fGlobal));
1619
1620	/*
1621	* Remap the CR3 content and adjust the monitoring if CR3 was actually changed.
1622	*/
1623	int rc = VINF_SUCCESS;
1624	RTGCPHYS GCPhysCR3;
1625	switch (pVCpu->pgm.s.enmGuestMode)
1626	{
1627	case PGMMODE_PAE:
1628	case PGMMODE_PAE_NX:
1629	GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAE_PAGE_MASK);
1630	break;
1631	case PGMMODE_AMD64:
1632	case PGMMODE_AMD64_NX:
1633	GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_AMD64_PAGE_MASK);
1634	break;
1635	default:
1636	GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAGE_MASK);
1637	break;
1638	}
1639
1640	if (pVCpu->pgm.s.GCPhysCR3 != GCPhysCR3)
1641	{
1642	RTGCPHYS GCPhysOldCR3 = pVCpu->pgm.s.GCPhysCR3;
1643	pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3;
1644	rc = PGM_BTH_PFN(MapCR3, pVCpu)(pVCpu, GCPhysCR3);
1645	if (RT_LIKELY(rc == VINF_SUCCESS))
1646	{
1647	if (!pVM->pgm.s.fMappingsFixed)
1648	{
1649	pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
1650	}
1651	}
1652	else
1653	{
1654	AssertMsg(rc == VINF_PGM_SYNC_CR3, ("%Rrc\n", rc));
1655	Assert(VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \| VMCPU_FF_PGM_SYNC_CR3));
1656	pVCpu->pgm.s.GCPhysCR3 = GCPhysOldCR3;
1657	pVCpu->pgm.s.fSyncFlags \|= PGM_SYNC_MAP_CR3;
1658	if (!pVM->pgm.s.fMappingsFixed)
1659	pVCpu->pgm.s.fSyncFlags \|= PGM_SYNC_MONITOR_CR3;
1660	}
1661
1662	if (fGlobal)
1663	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,FlushTLBNewCR3Global));
1664	else
1665	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,FlushTLBNewCR3));
1666	}
1667	else
1668	{
1669	/*
1670	* Check if we have a pending update of the CR3 monitoring.
1671	*/
1672	if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
1673	{
1674	pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
1675	Assert(!pVM->pgm.s.fMappingsFixed);
1676	}
1677	if (fGlobal)
1678	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,FlushTLBSameCR3Global));
1679	else
1680	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,FlushTLBSameCR3));
1681	}
1682
1683	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,FlushTLB), a);
1684	return rc;
1685	}
1686
1687
1688	/**
1689	* Performs and schedules necessary updates following a CR3 load or reload when
1690	* using nested or extended paging.
1691	*
1692	* This API is an alterantive to PDMFlushTLB that avoids actually flushing the
1693	* TLB and triggering a SyncCR3.
1694	*
1695	* This will normally involve mapping the guest PD or nPDPT
1696	*
1697	* @returns VBox status code.
1698	* @retval VINF_SUCCESS.
1699	* @retval (If applied when not in nested mode: VINF_PGM_SYNC_CR3 if monitoring
1700	* requires a CR3 sync. This can safely be ignored and overridden since
1701	* the FF will be set too then.)
1702	* @param pVCpu VMCPU handle.
1703	* @param cr3 The new cr3.
1704	*/
1705	VMMDECL(int) PGMUpdateCR3(PVMCPU pVCpu, uint64_t cr3)
1706	{
1707	PVM pVM = pVCpu->CTX_SUFF(pVM);
1708
1709	LogFlow(("PGMUpdateCR3: cr3=%RX64 OldCr3=%RX64\n", cr3, pVCpu->pgm.s.GCPhysCR3));
1710
1711	/* We assume we're only called in nested paging mode. */
1712	Assert(pVM->pgm.s.fMappingsFixed);
1713	Assert(!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3));
1714	Assert(HWACCMIsNestedPagingActive(pVM) \|\| pVCpu->pgm.s.enmShadowMode == PGMMODE_EPT);
1715
1716	/*
1717	* Remap the CR3 content and adjust the monitoring if CR3 was actually changed.
1718	*/
1719	int rc = VINF_SUCCESS;
1720	RTGCPHYS GCPhysCR3;
1721	switch (pVCpu->pgm.s.enmGuestMode)
1722	{
1723	case PGMMODE_PAE:
1724	case PGMMODE_PAE_NX:
1725	GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAE_PAGE_MASK);
1726	break;
1727	case PGMMODE_AMD64:
1728	case PGMMODE_AMD64_NX:
1729	GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_AMD64_PAGE_MASK);
1730	break;
1731	default:
1732	GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAGE_MASK);
1733	break;
1734	}
1735	if (pVCpu->pgm.s.GCPhysCR3 != GCPhysCR3)
1736	{
1737	pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3;
1738	rc = PGM_BTH_PFN(MapCR3, pVCpu)(pVCpu, GCPhysCR3);
1739	AssertRCSuccess(rc); /* Assumes VINF_PGM_SYNC_CR3 doesn't apply to nested paging. / /* @todo this isn't true for the mac, but we need hw to test/fix this. */
1740	}
1741	return rc;
1742	}
1743
1744
1745	/**
1746	* Synchronize the paging structures.
1747	*
1748	* This function is called in response to the VM_FF_PGM_SYNC_CR3 and
1749	* VM_FF_PGM_SYNC_CR3_NONGLOBAL. Those two force action flags are set
1750	* in several places, most importantly whenever the CR3 is loaded.
1751	*
1752	* @returns VBox status code.
1753	* @param pVCpu VMCPU handle.
1754	* @param cr0 Guest context CR0 register
1755	* @param cr3 Guest context CR3 register
1756	* @param cr4 Guest context CR4 register
1757	* @param fGlobal Including global page directories or not
1758	*/
1759	VMMDECL(int) PGMSyncCR3(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
1760	{
1761	PVM pVM = pVCpu->CTX_SUFF(pVM);
1762	int rc;
1763
1764	#ifdef PGMPOOL_WITH_MONITORING
1765	/*
1766	* The pool may have pending stuff and even require a return to ring-3 to
1767	* clear the whole thing.
1768	*/
1769	rc = pgmPoolSyncCR3(pVM);
1770	if (rc != VINF_SUCCESS)
1771	return rc;
1772	#endif
1773
1774	/*
1775	* We might be called when we shouldn't.
1776	*
1777	* The mode switching will ensure that the PD is resynced
1778	* after every mode switch. So, if we find ourselves here
1779	* when in protected or real mode we can safely disable the
1780	* FF and return immediately.
1781	*/
1782	if (pVCpu->pgm.s.enmGuestMode <= PGMMODE_PROTECTED)
1783	{
1784	Assert((cr0 & (X86_CR0_PG \| X86_CR0_PE)) != (X86_CR0_PG \| X86_CR0_PE));
1785	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
1786	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
1787	return VINF_SUCCESS;
1788	}
1789
1790	/* If global pages are not supported, then all flushes are global. */
1791	if (!(cr4 & X86_CR4_PGE))
1792	fGlobal = true;
1793	LogFlow(("PGMSyncCR3: cr0=%RX64 cr3=%RX64 cr4=%RX64 fGlobal=%d[%d,%d]\n", cr0, cr3, cr4, fGlobal,
1794	VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3), VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)));
1795
1796	/*
1797	* Check if we need to finish an aborted MapCR3 call (see PGMFlushTLB).
1798	* This should be done before SyncCR3.
1799	*/
1800	if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MAP_CR3)
1801	{
1802	pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MAP_CR3;
1803
1804	RTGCPHYS GCPhysCR3Old = pVCpu->pgm.s.GCPhysCR3;
1805	RTGCPHYS GCPhysCR3;
1806	switch (pVCpu->pgm.s.enmGuestMode)
1807	{
1808	case PGMMODE_PAE:
1809	case PGMMODE_PAE_NX:
1810	GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAE_PAGE_MASK);
1811	break;
1812	case PGMMODE_AMD64:
1813	case PGMMODE_AMD64_NX:
1814	GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_AMD64_PAGE_MASK);
1815	break;
1816	default:
1817	GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAGE_MASK);
1818	break;
1819	}
1820
1821	if (pVCpu->pgm.s.GCPhysCR3 != GCPhysCR3)
1822	{
1823	pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3;
1824	rc = PGM_BTH_PFN(MapCR3, pVCpu)(pVCpu, GCPhysCR3);
1825	}
1826	#ifdef IN_RING3
1827	if (rc == VINF_PGM_SYNC_CR3)
1828	rc = pgmPoolSyncCR3(pVM);
1829	#else
1830	if (rc == VINF_PGM_SYNC_CR3)
1831	{
1832	pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3Old;
1833	return rc;
1834	}
1835	#endif
1836	AssertRCReturn(rc, rc);
1837	AssertRCSuccessReturn(rc, VERR_INTERNAL_ERROR);
1838	}
1839
1840	/*
1841	* Let the 'Bth' function do the work and we'll just keep track of the flags.
1842	*/
1843	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncCR3), a);
1844	rc = PGM_BTH_PFN(SyncCR3, pVCpu)(pVCpu, cr0, cr3, cr4, fGlobal);
1845	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncCR3), a);
1846	AssertMsg(rc == VINF_SUCCESS \|\| rc == VINF_PGM_SYNC_CR3 \|\| RT_FAILURE(rc), ("rc=%Rrc\n", rc));
1847	if (rc == VINF_SUCCESS)
1848	{
1849	if (!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS))
1850	{
1851	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
1852	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
1853	}
1854
1855	/*
1856	* Check if we have a pending update of the CR3 monitoring.
1857	*/
1858	if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
1859	{
1860	pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
1861	Assert(!pVM->pgm.s.fMappingsFixed);
1862	}
1863	}
1864
1865	/*
1866	* Now flush the CR3 (guest context).
1867	*/
1868	if (rc == VINF_SUCCESS)
1869	PGM_INVL_GUEST_TLBS();
1870	return rc;
1871	}
1872
1873
1874	/**
1875	* Called whenever CR0 or CR4 in a way which may change
1876	* the paging mode.
1877	*
1878	* @returns VBox status code, with the following informational code for
1879	* VM scheduling.
1880	* @retval VINF_SUCCESS if the was no change, or it was successfully dealt with.
1881	* @retval VINF_PGM_CHANGE_MODE if we're in RC or R0 and the mode changes.
1882	* (I.e. not in R3.)
1883	* @retval VINF_EM_SUSPEND or VINF_EM_OFF on a fatal runtime error. (R3 only)
1884	*
1885	* @param pVCpu VMCPU handle.
1886	* @param cr0 The new cr0.
1887	* @param cr4 The new cr4.
1888	* @param efer The new extended feature enable register.
1889	*/
1890	VMMDECL(int) PGMChangeMode(PVMCPU pVCpu, uint64_t cr0, uint64_t cr4, uint64_t efer)
1891	{
1892	PVM pVM = pVCpu->CTX_SUFF(pVM);
1893	PGMMODE enmGuestMode;
1894
1895	/*
1896	* Calc the new guest mode.
1897	*/
1898	if (!(cr0 & X86_CR0_PE))
1899	enmGuestMode = PGMMODE_REAL;
1900	else if (!(cr0 & X86_CR0_PG))
1901	enmGuestMode = PGMMODE_PROTECTED;
1902	else if (!(cr4 & X86_CR4_PAE))
1903	enmGuestMode = PGMMODE_32_BIT;
1904	else if (!(efer & MSR_K6_EFER_LME))
1905	{
1906	if (!(efer & MSR_K6_EFER_NXE))
1907	enmGuestMode = PGMMODE_PAE;
1908	else
1909	enmGuestMode = PGMMODE_PAE_NX;
1910	}
1911	else
1912	{
1913	if (!(efer & MSR_K6_EFER_NXE))
1914	enmGuestMode = PGMMODE_AMD64;
1915	else
1916	enmGuestMode = PGMMODE_AMD64_NX;
1917	}
1918
1919	/*
1920	* Did it change?
1921	*/
1922	if (pVCpu->pgm.s.enmGuestMode == enmGuestMode)
1923	return VINF_SUCCESS;
1924
1925	/* Flush the TLB */
1926	PGM_INVL_GUEST_TLBS();
1927
1928	#ifdef IN_RING3
1929	return PGMR3ChangeMode(pVM, pVCpu, enmGuestMode);
1930	#else
1931	LogFlow(("PGMChangeMode: returns VINF_PGM_CHANGE_MODE.\n"));
1932	return VINF_PGM_CHANGE_MODE;
1933	#endif
1934	}
1935
1936
1937	/**
1938	* Gets the current guest paging mode.
1939	*
1940	* If you just need the CPU mode (real/protected/long), use CPUMGetGuestMode().
1941	*
1942	* @returns The current paging mode.
1943	* @param pVCpu VMCPU handle.
1944	*/
1945	VMMDECL(PGMMODE) PGMGetGuestMode(PVMCPU pVCpu)
1946	{
1947	return pVCpu->pgm.s.enmGuestMode;
1948	}
1949
1950
1951	/**
1952	* Gets the current shadow paging mode.
1953	*
1954	* @returns The current paging mode.
1955	* @param pVCpu VMCPU handle.
1956	*/
1957	VMMDECL(PGMMODE) PGMGetShadowMode(PVMCPU pVCpu)
1958	{
1959	return pVCpu->pgm.s.enmShadowMode;
1960	}
1961
1962	/**
1963	* Gets the current host paging mode.
1964	*
1965	* @returns The current paging mode.
1966	* @param pVM The VM handle.
1967	*/
1968	VMMDECL(PGMMODE) PGMGetHostMode(PVM pVM)
1969	{
1970	switch (pVM->pgm.s.enmHostMode)
1971	{
1972	case SUPPAGINGMODE_32_BIT:
1973	case SUPPAGINGMODE_32_BIT_GLOBAL:
1974	return PGMMODE_32_BIT;
1975
1976	case SUPPAGINGMODE_PAE:
1977	case SUPPAGINGMODE_PAE_GLOBAL:
1978	return PGMMODE_PAE;
1979
1980	case SUPPAGINGMODE_PAE_NX:
1981	case SUPPAGINGMODE_PAE_GLOBAL_NX:
1982	return PGMMODE_PAE_NX;
1983
1984	case SUPPAGINGMODE_AMD64:
1985	case SUPPAGINGMODE_AMD64_GLOBAL:
1986	return PGMMODE_AMD64;
1987
1988	case SUPPAGINGMODE_AMD64_NX:
1989	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1990	return PGMMODE_AMD64_NX;
1991
1992	default: AssertMsgFailed(("enmHostMode=%d\n", pVM->pgm.s.enmHostMode)); break;
1993	}
1994
1995	return PGMMODE_INVALID;
1996	}
1997
1998
1999	/**
2000	* Get mode name.
2001	*
2002	* @returns read-only name string.
2003	* @param enmMode The mode which name is desired.
2004	*/
2005	VMMDECL(const char *) PGMGetModeName(PGMMODE enmMode)
2006	{
2007	switch (enmMode)
2008	{
2009	case PGMMODE_REAL: return "Real";
2010	case PGMMODE_PROTECTED: return "Protected";
2011	case PGMMODE_32_BIT: return "32-bit";
2012	case PGMMODE_PAE: return "PAE";
2013	case PGMMODE_PAE_NX: return "PAE+NX";
2014	case PGMMODE_AMD64: return "AMD64";
2015	case PGMMODE_AMD64_NX: return "AMD64+NX";
2016	case PGMMODE_NESTED: return "Nested";
2017	case PGMMODE_EPT: return "EPT";
2018	default: return "unknown mode value";
2019	}
2020	}
2021
2022
2023	/**
2024	* Check if the PGM lock is currently taken.
2025	*
2026	* @returns bool locked/not locked
2027	* @param pVM The VM to operate on.
2028	*/
2029	VMMDECL(bool) PGMIsLocked(PVM pVM)
2030	{
2031	return PDMCritSectIsLocked(&pVM->pgm.s.CritSect);
2032	}
2033
2034	/**
2035	* Check if this VCPU currently owns the PGM lock.
2036	*
2037	* @returns bool owner/not owner
2038	* @param pVM The VM to operate on.
2039	*/
2040	VMMDECL(bool) PGMIsLockOwner(PVM pVM)
2041	{
2042	return PDMCritSectIsOwner(&pVM->pgm.s.CritSect);
2043	}
2044
2045
2046	/**
2047	* Acquire the PGM lock.
2048	*
2049	* @returns VBox status code
2050	* @param pVM The VM to operate on.
2051	*/
2052	int pgmLock(PVM pVM)
2053	{
2054	int rc = PDMCritSectEnter(&pVM->pgm.s.CritSect, VERR_SEM_BUSY);
2055	#ifdef IN_RC
2056	if (rc == VERR_SEM_BUSY)
2057	rc = VMMGCCallHost(pVM, VMMCALLHOST_PGM_LOCK, 0);
2058	#elif defined(IN_RING0)
2059	if (rc == VERR_SEM_BUSY)
2060	rc = VMMR0CallHost(pVM, VMMCALLHOST_PGM_LOCK, 0);
2061	#endif
2062	AssertMsg(rc == VINF_SUCCESS, ("%Rrc\n", rc));
2063	return rc;
2064	}
2065
2066
2067	/**
2068	* Release the PGM lock.
2069	*
2070	* @returns VBox status code
2071	* @param pVM The VM to operate on.
2072	*/
2073	void pgmUnlock(PVM pVM)
2074	{
2075	PDMCritSectLeave(&pVM->pgm.s.CritSect);
2076	}
2077
2078	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2079
2080	/**
2081	* Temporarily maps one guest page specified by GC physical address.
2082	* These pages must have a physical mapping in HC, i.e. they cannot be MMIO pages.
2083	*
2084	* Be WARNED that the dynamic page mapping area is small, 8 pages, thus the space is
2085	* reused after 8 mappings (or perhaps a few more if you score with the cache).
2086	*
2087	* @returns VBox status.
2088	* @param pVM VM handle.
2089	* @param GCPhys GC Physical address of the page.
2090	* @param ppv Where to store the address of the mapping.
2091	*/
2092	VMMDECL(int) PGMDynMapGCPage(PVM pVM, RTGCPHYS GCPhys, void **ppv)
2093	{
2094	AssertMsg(!(GCPhys & PAGE_OFFSET_MASK), ("GCPhys=%RGp\n", GCPhys));
2095
2096	/*
2097	* Get the ram range.
2098	*/
2099	PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
2100	while (pRam && GCPhys - pRam->GCPhys >= pRam->cb)
2101	pRam = pRam->CTX_SUFF(pNext);
2102	if (!pRam)
2103	{
2104	AssertMsgFailed(("Invalid physical address %RGp!\n", GCPhys));
2105	return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2106	}
2107
2108	/*
2109	* Pass it on to PGMDynMapHCPage.
2110	*/
2111	RTHCPHYS HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT]);
2112	//Log(("PGMDynMapGCPage: GCPhys=%RGp HCPhys=%RHp\n", GCPhys, HCPhys));
2113	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2114	pgmR0DynMapHCPageInlined(&pVM->pgm.s, HCPhys, ppv);
2115	#else
2116	PGMDynMapHCPage(pVM, HCPhys, ppv);
2117	#endif
2118	return VINF_SUCCESS;
2119	}
2120
2121
2122	/**
2123	* Temporarily maps one guest page specified by unaligned GC physical address.
2124	* These pages must have a physical mapping in HC, i.e. they cannot be MMIO pages.
2125	*
2126	* Be WARNED that the dynamic page mapping area is small, 8 pages, thus the space is
2127	* reused after 8 mappings (or perhaps a few more if you score with the cache).
2128	*
2129	* The caller is aware that only the speicifed page is mapped and that really bad things
2130	* will happen if writing beyond the page!
2131	*
2132	* @returns VBox status.
2133	* @param pVM VM handle.
2134	* @param GCPhys GC Physical address within the page to be mapped.
2135	* @param ppv Where to store the address of the mapping address corresponding to GCPhys.
2136	*/
2137	VMMDECL(int) PGMDynMapGCPageOff(PVM pVM, RTGCPHYS GCPhys, void **ppv)
2138	{
2139	/*
2140	* Get the ram range.
2141	*/
2142	PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
2143	while (pRam && GCPhys - pRam->GCPhys >= pRam->cb)
2144	pRam = pRam->CTX_SUFF(pNext);
2145	if (!pRam)
2146	{
2147	AssertMsgFailed(("Invalid physical address %RGp!\n", GCPhys));
2148	return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2149	}
2150
2151	/*
2152	* Pass it on to PGMDynMapHCPage.
2153	*/
2154	RTHCPHYS HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT]);
2155	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2156	pgmR0DynMapHCPageInlined(&pVM->pgm.s, HCPhys, ppv);
2157	#else
2158	PGMDynMapHCPage(pVM, HCPhys, ppv);
2159	#endif
2160	ppv = (void )((uintptr_t)*ppv \| (GCPhys & PAGE_OFFSET_MASK));
2161	return VINF_SUCCESS;
2162	}
2163
2164	# ifdef IN_RC
2165
2166	/**
2167	* Temporarily maps one host page specified by HC physical address.
2168	*
2169	* Be WARNED that the dynamic page mapping area is small, 16 pages, thus the space is
2170	* reused after 16 mappings (or perhaps a few more if you score with the cache).
2171	*
2172	* @returns VINF_SUCCESS, will bail out to ring-3 on failure.
2173	* @param pVM VM handle.
2174	* @param HCPhys HC Physical address of the page.
2175	* @param ppv Where to store the address of the mapping. This is the
2176	* address of the PAGE not the exact address corresponding
2177	* to HCPhys. Use PGMDynMapHCPageOff if you care for the
2178	* page offset.
2179	*/
2180	VMMDECL(int) PGMDynMapHCPage(PVM pVM, RTHCPHYS HCPhys, void **ppv)
2181	{
2182	AssertMsg(!(HCPhys & PAGE_OFFSET_MASK), ("HCPhys=%RHp\n", HCPhys));
2183
2184	/*
2185	* Check the cache.
2186	*/
2187	register unsigned iCache;
2188	for (iCache = 0;iCache < RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache);iCache++)
2189	{
2190	static const uint8_t au8Trans[MM_HYPER_DYNAMIC_SIZE >> PAGE_SHIFT][RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache)] =
2191	{
2192	{ 0, 9, 10, 11, 12, 13, 14, 15},
2193	{ 0, 1, 10, 11, 12, 13, 14, 15},
2194	{ 0, 1, 2, 11, 12, 13, 14, 15},
2195	{ 0, 1, 2, 3, 12, 13, 14, 15},
2196	{ 0, 1, 2, 3, 4, 13, 14, 15},
2197	{ 0, 1, 2, 3, 4, 5, 14, 15},
2198	{ 0, 1, 2, 3, 4, 5, 6, 15},
2199	{ 0, 1, 2, 3, 4, 5, 6, 7},
2200	{ 8, 1, 2, 3, 4, 5, 6, 7},
2201	{ 8, 9, 2, 3, 4, 5, 6, 7},
2202	{ 8, 9, 10, 3, 4, 5, 6, 7},
2203	{ 8, 9, 10, 11, 4, 5, 6, 7},
2204	{ 8, 9, 10, 11, 12, 5, 6, 7},
2205	{ 8, 9, 10, 11, 12, 13, 6, 7},
2206	{ 8, 9, 10, 11, 12, 13, 14, 7},
2207	{ 8, 9, 10, 11, 12, 13, 14, 15},
2208	};
2209	AssertCompile(RT_ELEMENTS(au8Trans) == 16);
2210	AssertCompile(RT_ELEMENTS(au8Trans[0]) == 8);
2211
2212	if (pVM->pgm.s.aHCPhysDynPageMapCache[iCache] == HCPhys)
2213	{
2214	int iPage = au8Trans[pVM->pgm.s.iDynPageMapLast][iCache];
2215
2216	/* The cache can get out of sync with locked entries. (10 locked, 2 overwrites its cache position, last = 11, lookup 2 -> page 10 instead of 2) */
2217	if ((pVM->pgm.s.paDynPageMap32BitPTEsGC[iPage].u & X86_PTE_PG_MASK) == HCPhys)
2218	{
2219	void *pv = pVM->pgm.s.pbDynPageMapBaseGC + (iPage << PAGE_SHIFT);
2220	*ppv = pv;
2221	STAM_COUNTER_INC(&pVM->pgm.s.StatRCDynMapCacheHits);
2222	Log4(("PGMGCDynMapHCPage: HCPhys=%RHp pv=%p iPage=%d iCache=%d\n", HCPhys, pv, iPage, iCache));
2223	return VINF_SUCCESS;
2224	}
2225	else
2226	LogFlow(("Out of sync entry %d\n", iPage));
2227	}
2228	}
2229	AssertCompile(RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache) == 8);
2230	AssertCompile((MM_HYPER_DYNAMIC_SIZE >> PAGE_SHIFT) == 16);
2231	STAM_COUNTER_INC(&pVM->pgm.s.StatRCDynMapCacheMisses);
2232
2233	/*
2234	* Update the page tables.
2235	*/
2236	register unsigned iPage = pVM->pgm.s.iDynPageMapLast;
2237	unsigned i;
2238	for (i=0;i<(MM_HYPER_DYNAMIC_SIZE >> PAGE_SHIFT);i++)
2239	{
2240	pVM->pgm.s.iDynPageMapLast = iPage = (iPage + 1) & ((MM_HYPER_DYNAMIC_SIZE >> PAGE_SHIFT) - 1);
2241	if (!pVM->pgm.s.aLockedDynPageMapCache[iPage])
2242	break;
2243	iPage++;
2244	}
2245	AssertRelease(i != (MM_HYPER_DYNAMIC_SIZE >> PAGE_SHIFT));
2246
2247	pVM->pgm.s.aHCPhysDynPageMapCache[iPage & (RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache) - 1)] = HCPhys;
2248	pVM->pgm.s.paDynPageMap32BitPTEsGC[iPage].u = (uint32_t)HCPhys \| X86_PTE_P \| X86_PTE_A \| X86_PTE_D;
2249	pVM->pgm.s.paDynPageMapPaePTEsGC[iPage].u = HCPhys \| X86_PTE_P \| X86_PTE_A \| X86_PTE_D;
2250	pVM->pgm.s.aLockedDynPageMapCache[iPage] = 0;
2251
2252	void *pv = pVM->pgm.s.pbDynPageMapBaseGC + (iPage << PAGE_SHIFT);
2253	*ppv = pv;
2254	ASMInvalidatePage(pv);
2255	Log4(("PGMGCDynMapHCPage: HCPhys=%RHp pv=%p iPage=%d\n", HCPhys, pv, iPage));
2256	return VINF_SUCCESS;
2257	}
2258
2259
2260	/**
2261	* Temporarily lock a dynamic page to prevent it from being reused.
2262	*
2263	* @param pVM VM handle.
2264	* @param GCPage GC address of page
2265	*/
2266	VMMDECL(void) PGMDynLockHCPage(PVM pVM, RCPTRTYPE(uint8_t *) GCPage)
2267	{
2268	unsigned iPage;
2269
2270	Assert(GCPage >= pVM->pgm.s.pbDynPageMapBaseGC && GCPage < (pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE));
2271	iPage = ((uintptr_t)(GCPage - pVM->pgm.s.pbDynPageMapBaseGC)) >> PAGE_SHIFT;
2272	ASMAtomicIncU32(&pVM->pgm.s.aLockedDynPageMapCache[iPage]);
2273	Log4(("PGMDynLockHCPage %RRv iPage=%d\n", GCPage, iPage));
2274	}
2275
2276
2277	/**
2278	* Unlock a dynamic page
2279	*
2280	* @param pVM VM handle.
2281	* @param GCPage GC address of page
2282	*/
2283	VMMDECL(void) PGMDynUnlockHCPage(PVM pVM, RCPTRTYPE(uint8_t *) GCPage)
2284	{
2285	unsigned iPage;
2286
2287	AssertCompile(RT_ELEMENTS(pVM->pgm.s.aLockedDynPageMapCache) == 2* RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache));
2288	AssertCompileMemberSize(VM, pgm.s.aLockedDynPageMapCache, sizeof(uint32_t) * (MM_HYPER_DYNAMIC_SIZE >> (PAGE_SHIFT)));
2289
2290	Assert(GCPage >= pVM->pgm.s.pbDynPageMapBaseGC && GCPage < (pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE));
2291	iPage = ((uintptr_t)(GCPage - pVM->pgm.s.pbDynPageMapBaseGC)) >> PAGE_SHIFT;
2292	Assert(pVM->pgm.s.aLockedDynPageMapCache[iPage]);
2293	ASMAtomicDecU32(&pVM->pgm.s.aLockedDynPageMapCache[iPage]);
2294	Log4(("PGMDynUnlockHCPage %RRv iPage=%d\n", GCPage, iPage));
2295	}
2296
2297
2298	# ifdef VBOX_STRICT
2299	/**
2300	* Check for lock leaks.
2301	*
2302	* @param pVM VM handle.
2303	*/
2304	VMMDECL(void) PGMDynCheckLocks(PVM pVM)
2305	{
2306	for (unsigned i=0;i<RT_ELEMENTS(pVM->pgm.s.aLockedDynPageMapCache);i++)
2307	Assert(!pVM->pgm.s.aLockedDynPageMapCache[i]);
2308	}
2309	# endif /* VBOX_STRICT */
2310
2311	# endif /* IN_RC */
2312	#endif /* IN_RC \|\| VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
2313
2314	#if !defined(IN_R0) \|\| defined(LOG_ENABLED)
2315
2316	/** Format handler for PGMPAGE.
2317	* @copydoc FNRTSTRFORMATTYPE */
2318	static DECLCALLBACK(size_t) pgmFormatTypeHandlerPage(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
2319	const char pszType, void const pvValue,
2320	int cchWidth, int cchPrecision, unsigned fFlags,
2321	void *pvUser)
2322	{
2323	size_t cch;
2324	PCPGMPAGE pPage = (PCPGMPAGE)pvValue;
2325	if (VALID_PTR(pPage))
2326	{
2327	char szTmp[64+80];
2328
2329	cch = 0;
2330
2331	/* The single char state stuff. */
2332	static const char s_achPageStates[4] = { 'Z', 'A', 'W', 'S' };
2333	szTmp[cch++] = s_achPageStates[PGM_PAGE_GET_STATE(pPage)];
2334
2335	#define IS_PART_INCLUDED(lvl) ( !(fFlags & RTSTR_F_PRECISION) \|\| cchPrecision == (lvl) \|\| cchPrecision >= (lvl)+10 )
2336	if (IS_PART_INCLUDED(5))
2337	{
2338	static const char s_achHandlerStates[4] = { '-', 't', 'w', 'a' };
2339	szTmp[cch++] = s_achHandlerStates[PGM_PAGE_GET_HNDL_PHYS_STATE(pPage)];
2340	szTmp[cch++] = s_achHandlerStates[PGM_PAGE_GET_HNDL_VIRT_STATE(pPage)];
2341	}
2342
2343	/* The type. */
2344	if (IS_PART_INCLUDED(4))
2345	{
2346	szTmp[cch++] = ':';
2347	static const char s_achPageTypes[8][4] = { "INV", "RAM", "MI2", "M2A", "SHA", "ROM", "MIO", "BAD" };
2348	szTmp[cch++] = s_achPageTypes[PGM_PAGE_GET_TYPE(pPage)][0];
2349	szTmp[cch++] = s_achPageTypes[PGM_PAGE_GET_TYPE(pPage)][1];
2350	szTmp[cch++] = s_achPageTypes[PGM_PAGE_GET_TYPE(pPage)][2];
2351	}
2352
2353	/* The numbers. */
2354	if (IS_PART_INCLUDED(3))
2355	{
2356	szTmp[cch++] = ':';
2357	cch += RTStrFormatNumber(&szTmp[cch], PGM_PAGE_GET_HCPHYS(pPage), 16, 12, 0, RTSTR_F_ZEROPAD \| RTSTR_F_64BIT);
2358	}
2359
2360	if (IS_PART_INCLUDED(2))
2361	{
2362	szTmp[cch++] = ':';
2363	cch += RTStrFormatNumber(&szTmp[cch], PGM_PAGE_GET_PAGEID(pPage), 16, 7, 0, RTSTR_F_ZEROPAD \| RTSTR_F_32BIT);
2364	}
2365
2366	if (IS_PART_INCLUDED(6))
2367	{
2368	szTmp[cch++] = ':';
2369	static const char s_achRefs[4] = { '-', 'U', '!', 'L' };
2370	szTmp[cch++] = s_achRefs[PGM_PAGE_GET_TD_CREFS(pPage)];
2371	cch += RTStrFormatNumber(&szTmp[cch], PGM_PAGE_GET_TD_IDX(pPage), 16, 4, 0, RTSTR_F_ZEROPAD \| RTSTR_F_16BIT);
2372	}
2373	#undef IS_PART_INCLUDED
2374
2375	cch = pfnOutput(pvArgOutput, szTmp, cch);
2376	}
2377	else
2378	cch = pfnOutput(pvArgOutput, "<bad-pgmpage-ptr>", sizeof("<bad-pgmpage-ptr>") - 1);
2379	return cch;
2380	}
2381
2382
2383	/** Format handler for PGMRAMRANGE.
2384	* @copydoc FNRTSTRFORMATTYPE */
2385	static DECLCALLBACK(size_t) pgmFormatTypeHandlerRamRange(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
2386	const char pszType, void const pvValue,
2387	int cchWidth, int cchPrecision, unsigned fFlags,
2388	void *pvUser)
2389	{
2390	size_t cch;
2391	PGMRAMRANGE const pRam = (PGMRAMRANGE const )pvValue;
2392	if (VALID_PTR(pRam))
2393	{
2394	char szTmp[80];
2395	cch = RTStrPrintf(szTmp, sizeof(szTmp), "%RGp-%RGp", pRam->GCPhys, pRam->GCPhysLast);
2396	cch = pfnOutput(pvArgOutput, szTmp, cch);
2397	}
2398	else
2399	cch = pfnOutput(pvArgOutput, "<bad-pgmramrange-ptr>", sizeof("<bad-pgmramrange-ptr>") - 1);
2400	return cch;
2401	}
2402
2403	/** Format type andlers to be registered/deregistered. */
2404	static const struct
2405	{
2406	char szType[24];
2407	PFNRTSTRFORMATTYPE pfnHandler;
2408	} g_aPgmFormatTypes[] =
2409	{
2410	{ "pgmpage", pgmFormatTypeHandlerPage },
2411	{ "pgmramrange", pgmFormatTypeHandlerRamRange }
2412	};
2413
2414	#endif /* !IN_R0 \|\| LOG_ENABLED */
2415
2416
2417	/**
2418	* Registers the global string format types.
2419	*
2420	* This should be called at module load time or in some other manner that ensure
2421	* that it's called exactly one time.
2422	*
2423	* @returns IPRT status code on RTStrFormatTypeRegister failure.
2424	*/
2425	VMMDECL(int) PGMRegisterStringFormatTypes(void)
2426	{
2427	#if !defined(IN_R0) \|\| defined(LOG_ENABLED)
2428	int rc = VINF_SUCCESS;
2429	unsigned i;
2430	for (i = 0; RT_SUCCESS(rc) && i < RT_ELEMENTS(g_aPgmFormatTypes); i++)
2431	{
2432	rc = RTStrFormatTypeRegister(g_aPgmFormatTypes[i].szType, g_aPgmFormatTypes[i].pfnHandler, NULL);
2433	# ifdef IN_RING0
2434	if (rc == VERR_ALREADY_EXISTS)
2435	{
2436	/* in case of cleanup failure in ring-0 */
2437	RTStrFormatTypeDeregister(g_aPgmFormatTypes[i].szType);
2438	rc = RTStrFormatTypeRegister(g_aPgmFormatTypes[i].szType, g_aPgmFormatTypes[i].pfnHandler, NULL);
2439	}
2440	# endif
2441	}
2442	if (RT_FAILURE(rc))
2443	while (i-- > 0)
2444	RTStrFormatTypeDeregister(g_aPgmFormatTypes[i].szType);
2445
2446	return rc;
2447	#else
2448	return VINF_SUCCESS;
2449	#endif
2450	}
2451
2452
2453	/**
2454	* Deregisters the global string format types.
2455	*
2456	* This should be called at module unload time or in some other manner that
2457	* ensure that it's called exactly one time.
2458	*/
2459	VMMDECL(void) PGMDeregisterStringFormatTypes(void)
2460	{
2461	#if !defined(IN_R0) \|\| defined(LOG_ENABLED)
2462	for (unsigned i = 0; i < RT_ELEMENTS(g_aPgmFormatTypes); i++)
2463	RTStrFormatTypeDeregister(g_aPgmFormatTypes[i].szType);
2464	#endif
2465	}
2466
2467	#ifdef VBOX_STRICT
2468
2469	/**
2470	* Asserts that there are no mapping conflicts.
2471	*
2472	* @returns Number of conflicts.
2473	* @param pVM The VM Handle.
2474	*/
2475	VMMDECL(unsigned) PGMAssertNoMappingConflicts(PVM pVM)
2476	{
2477	unsigned cErrors = 0;
2478
2479	/* Only applies to raw mode -> 1 VPCU */
2480	Assert(pVM->cCPUs == 1);
2481	PVMCPU pVCpu = &pVM->aCpus[0];
2482
2483	/*
2484	* Check for mapping conflicts.
2485	*/
2486	for (PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
2487	pMapping;
2488	pMapping = pMapping->CTX_SUFF(pNext))
2489	{
2490	/** @todo This is slow and should be optimized, but since it's just assertions I don't care now. */
2491	for (RTGCPTR GCPtr = pMapping->GCPtr;
2492	GCPtr <= pMapping->GCPtrLast;
2493	GCPtr += PAGE_SIZE)
2494	{
2495	int rc = PGMGstGetPage(pVCpu, (RTGCPTR)GCPtr, NULL, NULL);
2496	if (rc != VERR_PAGE_TABLE_NOT_PRESENT)
2497	{
2498	AssertMsgFailed(("Conflict at %RGv with %s\n", GCPtr, R3STRING(pMapping->pszDesc)));
2499	cErrors++;
2500	break;
2501	}
2502	}
2503	}
2504
2505	return cErrors;
2506	}
2507
2508
2509	/**
2510	* Asserts that everything related to the guest CR3 is correctly shadowed.
2511	*
2512	* This will call PGMAssertNoMappingConflicts() and PGMAssertHandlerAndFlagsInSync(),
2513	* and assert the correctness of the guest CR3 mapping before asserting that the
2514	* shadow page tables is in sync with the guest page tables.
2515	*
2516	* @returns Number of conflicts.
2517	* @param pVM The VM Handle.
2518	* @param pVCpu VMCPU handle.
2519	* @param cr3 The current guest CR3 register value.
2520	* @param cr4 The current guest CR4 register value.
2521	*/
2522	VMMDECL(unsigned) PGMAssertCR3(PVM pVM, PVMCPU pVCpu, uint64_t cr3, uint64_t cr4)
2523	{
2524	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncCR3), a);
2525	unsigned cErrors = PGM_BTH_PFN(AssertCR3, pVCpu)(pVCpu, cr3, cr4, 0, ~(RTGCPTR)0);
2526	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncCR3), a);
2527	return cErrors;
2528	}
2529
2530	#endif /* VBOX_STRICT */

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAll.cpp@ 19790

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