PGMAll.cpp@ 19979

Last change on this file since 19979 was 19874, checked in by vboxsync, 16 years ago
Protect PGMShwModifyPage
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1	/* $Id: PGMAll.cpp 19874 2009-05-20 15:41:35Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor - All context code.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	/*******************************************************************************
23	* Header Files *
24	*******************************************************************************/
25	#define LOG_GROUP LOG_GROUP_PGM
26	#include <VBox/pgm.h>
27	#include <VBox/cpum.h>
28	#include <VBox/selm.h>
29	#include <VBox/iom.h>
30	#include <VBox/sup.h>
31	#include <VBox/mm.h>
32	#include <VBox/stam.h>
33	#include <VBox/csam.h>
34	#include <VBox/patm.h>
35	#include <VBox/trpm.h>
36	#include <VBox/rem.h>
37	#include <VBox/em.h>
38	#include <VBox/hwaccm.h>
39	#include <VBox/hwacc_vmx.h>
40	#include "PGMInternal.h"
41	#include <VBox/vm.h>
42	#include <iprt/assert.h>
43	#include <iprt/asm.h>
44	#include <iprt/string.h>
45	#include <VBox/log.h>
46	#include <VBox/param.h>
47	#include <VBox/err.h>
48
49
50	/*******************************************************************************
51	* Structures and Typedefs *
52	*******************************************************************************/
53	/**
54	* Stated structure for PGM_GST_NAME(HandlerVirtualUpdate) that's
55	* passed to PGM_GST_NAME(VirtHandlerUpdateOne) during enumeration.
56	*/
57	typedef struct PGMHVUSTATE
58	{
59	/** The VM handle. */
60	PVM pVM;
61	/** The VMCPU handle. */
62	PVMCPU pVCpu;
63	/** The todo flags. */
64	RTUINT fTodo;
65	/** The CR4 register value. */
66	uint32_t cr4;
67	} PGMHVUSTATE, *PPGMHVUSTATE;
68
69
70	/*******************************************************************************
71	* Internal Functions *
72	*******************************************************************************/
73	DECLINLINE(int) pgmShwGetLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PX86PML4E ppPml4e, PX86PDPT ppPdpt, PX86PDPAE *ppPD);
74	DECLINLINE(int) pgmShwGetPaePoolPagePD(PPGMCPU pPGM, RTGCPTR GCPtr, PPGMPOOLPAGE *ppShwPde);
75
76	/*
77	* Shadow - 32-bit mode
78	*/
79	#define PGM_SHW_TYPE PGM_TYPE_32BIT
80	#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
81	#include "PGMAllShw.h"
82
83	/* Guest - real mode */
84	#define PGM_GST_TYPE PGM_TYPE_REAL
85	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
86	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
87	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
88	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
89	#include "PGMGstDefs.h"
90	#include "PGMAllGst.h"
91	#include "PGMAllBth.h"
92	#undef BTH_PGMPOOLKIND_PT_FOR_PT
93	#undef BTH_PGMPOOLKIND_ROOT
94	#undef PGM_BTH_NAME
95	#undef PGM_GST_TYPE
96	#undef PGM_GST_NAME
97
98	/* Guest - protected mode */
99	#define PGM_GST_TYPE PGM_TYPE_PROT
100	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
101	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
102	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
103	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
104	#include "PGMGstDefs.h"
105	#include "PGMAllGst.h"
106	#include "PGMAllBth.h"
107	#undef BTH_PGMPOOLKIND_PT_FOR_PT
108	#undef BTH_PGMPOOLKIND_ROOT
109	#undef PGM_BTH_NAME
110	#undef PGM_GST_TYPE
111	#undef PGM_GST_NAME
112
113	/* Guest - 32-bit mode */
114	#define PGM_GST_TYPE PGM_TYPE_32BIT
115	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
116	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
117	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
118	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
119	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD
120	#include "PGMGstDefs.h"
121	#include "PGMAllGst.h"
122	#include "PGMAllBth.h"
123	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
124	#undef BTH_PGMPOOLKIND_PT_FOR_PT
125	#undef BTH_PGMPOOLKIND_ROOT
126	#undef PGM_BTH_NAME
127	#undef PGM_GST_TYPE
128	#undef PGM_GST_NAME
129
130	#undef PGM_SHW_TYPE
131	#undef PGM_SHW_NAME
132
133
134	/*
135	* Shadow - PAE mode
136	*/
137	#define PGM_SHW_TYPE PGM_TYPE_PAE
138	#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
139	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
140	#include "PGMAllShw.h"
141
142	/* Guest - real mode */
143	#define PGM_GST_TYPE PGM_TYPE_REAL
144	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
145	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
146	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
147	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
148	#include "PGMGstDefs.h"
149	#include "PGMAllBth.h"
150	#undef BTH_PGMPOOLKIND_PT_FOR_PT
151	#undef BTH_PGMPOOLKIND_ROOT
152	#undef PGM_BTH_NAME
153	#undef PGM_GST_TYPE
154	#undef PGM_GST_NAME
155
156	/* Guest - protected mode */
157	#define PGM_GST_TYPE PGM_TYPE_PROT
158	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
159	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
160	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
161	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
162	#include "PGMGstDefs.h"
163	#include "PGMAllBth.h"
164	#undef BTH_PGMPOOLKIND_PT_FOR_PT
165	#undef BTH_PGMPOOLKIND_ROOT
166	#undef PGM_BTH_NAME
167	#undef PGM_GST_TYPE
168	#undef PGM_GST_NAME
169
170	/* Guest - 32-bit mode */
171	#define PGM_GST_TYPE PGM_TYPE_32BIT
172	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
173	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
174	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
175	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
176	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_FOR_32BIT
177	#include "PGMGstDefs.h"
178	#include "PGMAllBth.h"
179	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
180	#undef BTH_PGMPOOLKIND_PT_FOR_PT
181	#undef BTH_PGMPOOLKIND_ROOT
182	#undef PGM_BTH_NAME
183	#undef PGM_GST_TYPE
184	#undef PGM_GST_NAME
185
186
187	/* Guest - PAE mode */
188	#define PGM_GST_TYPE PGM_TYPE_PAE
189	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
190	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
191	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
192	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
193	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT
194	#include "PGMGstDefs.h"
195	#include "PGMAllGst.h"
196	#include "PGMAllBth.h"
197	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
198	#undef BTH_PGMPOOLKIND_PT_FOR_PT
199	#undef BTH_PGMPOOLKIND_ROOT
200	#undef PGM_BTH_NAME
201	#undef PGM_GST_TYPE
202	#undef PGM_GST_NAME
203
204	#undef PGM_SHW_TYPE
205	#undef PGM_SHW_NAME
206
207
208	#ifndef IN_RC /* AMD64 implies VT-x/AMD-V */
209	/*
210	* Shadow - AMD64 mode
211	*/
212	# define PGM_SHW_TYPE PGM_TYPE_AMD64
213	# define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
214	# include "PGMAllShw.h"
215
216	/* Guest - protected mode (only used for AMD-V nested paging in 64 bits mode) */
217	# define PGM_GST_TYPE PGM_TYPE_PROT
218	# define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
219	# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_PROT(name)
220	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
221	# define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PD_PHYS
222	# include "PGMGstDefs.h"
223	# include "PGMAllBth.h"
224	# undef BTH_PGMPOOLKIND_PT_FOR_PT
225	# undef BTH_PGMPOOLKIND_ROOT
226	# undef PGM_BTH_NAME
227	# undef PGM_GST_TYPE
228	# undef PGM_GST_NAME
229
230	# ifdef VBOX_WITH_64_BITS_GUESTS
231	/* Guest - AMD64 mode */
232	# define PGM_GST_TYPE PGM_TYPE_AMD64
233	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
234	# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
235	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
236	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
237	# define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_64BIT_PML4
238	# include "PGMGstDefs.h"
239	# include "PGMAllGst.h"
240	# include "PGMAllBth.h"
241	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
242	# undef BTH_PGMPOOLKIND_PT_FOR_PT
243	# undef BTH_PGMPOOLKIND_ROOT
244	# undef PGM_BTH_NAME
245	# undef PGM_GST_TYPE
246	# undef PGM_GST_NAME
247	# endif /* VBOX_WITH_64_BITS_GUESTS */
248
249	# undef PGM_SHW_TYPE
250	# undef PGM_SHW_NAME
251
252
253	/*
254	* Shadow - Nested paging mode
255	*/
256	# define PGM_SHW_TYPE PGM_TYPE_NESTED
257	# define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED(name)
258	# include "PGMAllShw.h"
259
260	/* Guest - real mode */
261	# define PGM_GST_TYPE PGM_TYPE_REAL
262	# define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
263	# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_REAL(name)
264	# include "PGMGstDefs.h"
265	# include "PGMAllBth.h"
266	# undef PGM_BTH_NAME
267	# undef PGM_GST_TYPE
268	# undef PGM_GST_NAME
269
270	/* Guest - protected mode */
271	# define PGM_GST_TYPE PGM_TYPE_PROT
272	# define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
273	# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PROT(name)
274	# include "PGMGstDefs.h"
275	# include "PGMAllBth.h"
276	# undef PGM_BTH_NAME
277	# undef PGM_GST_TYPE
278	# undef PGM_GST_NAME
279
280	/* Guest - 32-bit mode */
281	# define PGM_GST_TYPE PGM_TYPE_32BIT
282	# define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
283	# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT(name)
284	# include "PGMGstDefs.h"
285	# include "PGMAllBth.h"
286	# undef PGM_BTH_NAME
287	# undef PGM_GST_TYPE
288	# undef PGM_GST_NAME
289
290	/* Guest - PAE mode */
291	# define PGM_GST_TYPE PGM_TYPE_PAE
292	# define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
293	# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE(name)
294	# include "PGMGstDefs.h"
295	# include "PGMAllBth.h"
296	# undef PGM_BTH_NAME
297	# undef PGM_GST_TYPE
298	# undef PGM_GST_NAME
299
300	# ifdef VBOX_WITH_64_BITS_GUESTS
301	/* Guest - AMD64 mode */
302	# define PGM_GST_TYPE PGM_TYPE_AMD64
303	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
304	# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64(name)
305	# include "PGMGstDefs.h"
306	# include "PGMAllBth.h"
307	# undef PGM_BTH_NAME
308	# undef PGM_GST_TYPE
309	# undef PGM_GST_NAME
310	# endif /* VBOX_WITH_64_BITS_GUESTS */
311
312	# undef PGM_SHW_TYPE
313	# undef PGM_SHW_NAME
314
315
316	/*
317	* Shadow - EPT
318	*/
319	# define PGM_SHW_TYPE PGM_TYPE_EPT
320	# define PGM_SHW_NAME(name) PGM_SHW_NAME_EPT(name)
321	# include "PGMAllShw.h"
322
323	/* Guest - real mode */
324	# define PGM_GST_TYPE PGM_TYPE_REAL
325	# define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
326	# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_REAL(name)
327	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
328	# include "PGMGstDefs.h"
329	# include "PGMAllBth.h"
330	# undef BTH_PGMPOOLKIND_PT_FOR_PT
331	# undef PGM_BTH_NAME
332	# undef PGM_GST_TYPE
333	# undef PGM_GST_NAME
334
335	/* Guest - protected mode */
336	# define PGM_GST_TYPE PGM_TYPE_PROT
337	# define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
338	# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PROT(name)
339	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
340	# include "PGMGstDefs.h"
341	# include "PGMAllBth.h"
342	# undef BTH_PGMPOOLKIND_PT_FOR_PT
343	# undef PGM_BTH_NAME
344	# undef PGM_GST_TYPE
345	# undef PGM_GST_NAME
346
347	/* Guest - 32-bit mode */
348	# define PGM_GST_TYPE PGM_TYPE_32BIT
349	# define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
350	# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_32BIT(name)
351	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
352	# include "PGMGstDefs.h"
353	# include "PGMAllBth.h"
354	# undef BTH_PGMPOOLKIND_PT_FOR_PT
355	# undef PGM_BTH_NAME
356	# undef PGM_GST_TYPE
357	# undef PGM_GST_NAME
358
359	/* Guest - PAE mode */
360	# define PGM_GST_TYPE PGM_TYPE_PAE
361	# define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
362	# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PAE(name)
363	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
364	# include "PGMGstDefs.h"
365	# include "PGMAllBth.h"
366	# undef BTH_PGMPOOLKIND_PT_FOR_PT
367	# undef PGM_BTH_NAME
368	# undef PGM_GST_TYPE
369	# undef PGM_GST_NAME
370
371	# ifdef VBOX_WITH_64_BITS_GUESTS
372	/* Guest - AMD64 mode */
373	# define PGM_GST_TYPE PGM_TYPE_AMD64
374	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
375	# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_AMD64(name)
376	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
377	# include "PGMGstDefs.h"
378	# include "PGMAllBth.h"
379	# undef BTH_PGMPOOLKIND_PT_FOR_PT
380	# undef PGM_BTH_NAME
381	# undef PGM_GST_TYPE
382	# undef PGM_GST_NAME
383	# endif /* VBOX_WITH_64_BITS_GUESTS */
384
385	# undef PGM_SHW_TYPE
386	# undef PGM_SHW_NAME
387
388	#endif /* !IN_RC */
389
390
391	#ifndef IN_RING3
392	/**
393	* #PF Handler.
394	*
395	* @returns VBox status code (appropriate for trap handling and GC return).
396	* @param pVCpu VMCPU handle.
397	* @param uErr The trap error code.
398	* @param pRegFrame Trap register frame.
399	* @param pvFault The fault address.
400	*/
401	VMMDECL(int) PGMTrap0eHandler(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
402	{
403	LogFlow(("PGMTrap0eHandler: uErr=%RGu pvFault=%RGv eip=%04x:%RGv\n", uErr, pvFault, pRegFrame->cs, (RTGCPTR)pRegFrame->rip));
404	STAM_PROFILE_START(&pVCpu->pgm.s.StatRZTrap0e, a);
405	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = NULL; } );
406
407
408	#ifdef VBOX_WITH_STATISTICS
409	/*
410	* Error code stats.
411	*/
412	if (uErr & X86_TRAP_PF_US)
413	{
414	if (!(uErr & X86_TRAP_PF_P))
415	{
416	if (uErr & X86_TRAP_PF_RW)
417	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eUSNotPresentWrite);
418	else
419	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eUSNotPresentRead);
420	}
421	else if (uErr & X86_TRAP_PF_RW)
422	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eUSWrite);
423	else if (uErr & X86_TRAP_PF_RSVD)
424	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eUSReserved);
425	else if (uErr & X86_TRAP_PF_ID)
426	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eUSNXE);
427	else
428	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eUSRead);
429	}
430	else
431	{ /* Supervisor */
432	if (!(uErr & X86_TRAP_PF_P))
433	{
434	if (uErr & X86_TRAP_PF_RW)
435	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eSVNotPresentWrite);
436	else
437	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eSVNotPresentRead);
438	}
439	else if (uErr & X86_TRAP_PF_RW)
440	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eSVWrite);
441	else if (uErr & X86_TRAP_PF_ID)
442	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eSNXE);
443	else if (uErr & X86_TRAP_PF_RSVD)
444	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eSVReserved);
445	}
446	#endif /* VBOX_WITH_STATISTICS */
447
448	/*
449	* Call the worker.
450	*/
451	int rc = PGM_BTH_PFN(Trap0eHandler, pVCpu)(pVCpu, uErr, pRegFrame, pvFault);
452	if (rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
453	rc = VINF_SUCCESS;
454	STAM_STATS({ if (rc == VINF_EM_RAW_GUEST_TRAP) STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eGuestPF); });
455	STAM_STATS({ if (!pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution))
456	pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2Misc; });
457	STAM_PROFILE_STOP_EX(&pVCpu->pgm.s.StatRZTrap0e, pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution), a);
458	return rc;
459	}
460	#endif /* !IN_RING3 */
461
462
463	/**
464	* Prefetch a page
465	*
466	* Typically used to sync commonly used pages before entering raw mode
467	* after a CR3 reload.
468	*
469	* @returns VBox status code suitable for scheduling.
470	* @retval VINF_SUCCESS on success.
471	* @retval VINF_PGM_SYNC_CR3 if we're out of shadow pages or something like that.
472	* @param pVCpu VMCPU handle.
473	* @param GCPtrPage Page to invalidate.
474	*/
475	VMMDECL(int) PGMPrefetchPage(PVMCPU pVCpu, RTGCPTR GCPtrPage)
476	{
477	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_MID_Z(Stat,Prefetch), a);
478	int rc = PGM_BTH_PFN(PrefetchPage, pVCpu)(pVCpu, GCPtrPage);
479	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,Prefetch), a);
480	AssertMsg(rc == VINF_SUCCESS \|\| rc == VINF_PGM_SYNC_CR3 \|\| RT_FAILURE(rc), ("rc=%Rrc\n", rc));
481	return rc;
482	}
483
484
485	/**
486	* Gets the mapping corresponding to the specified address (if any).
487	*
488	* @returns Pointer to the mapping.
489	* @returns NULL if not
490	*
491	* @param pVM The virtual machine.
492	* @param GCPtr The guest context pointer.
493	*/
494	PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr)
495	{
496	PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
497	while (pMapping)
498	{
499	if ((uintptr_t)GCPtr < (uintptr_t)pMapping->GCPtr)
500	break;
501	if ((uintptr_t)GCPtr - (uintptr_t)pMapping->GCPtr < pMapping->cb)
502	return pMapping;
503	pMapping = pMapping->CTX_SUFF(pNext);
504	}
505	return NULL;
506	}
507
508
509	/**
510	* Verifies a range of pages for read or write access
511	*
512	* Only checks the guest's page tables
513	*
514	* @returns VBox status code.
515	* @param pVCpu VMCPU handle.
516	* @param Addr Guest virtual address to check
517	* @param cbSize Access size
518	* @param fAccess Access type (r/w, user/supervisor (X86_PTE_*))
519	* @remarks Current not in use.
520	*/
521	VMMDECL(int) PGMIsValidAccess(PVMCPU pVCpu, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess)
522	{
523	/*
524	* Validate input.
525	*/
526	if (fAccess & ~(X86_PTE_US \| X86_PTE_RW))
527	{
528	AssertMsgFailed(("PGMIsValidAccess: invalid access type %08x\n", fAccess));
529	return VERR_INVALID_PARAMETER;
530	}
531
532	uint64_t fPage;
533	int rc = PGMGstGetPage(pVCpu, (RTGCPTR)Addr, &fPage, NULL);
534	if (RT_FAILURE(rc))
535	{
536	Log(("PGMIsValidAccess: access violation for %RGv rc=%d\n", Addr, rc));
537	return VINF_EM_RAW_GUEST_TRAP;
538	}
539
540	/*
541	* Check if the access would cause a page fault
542	*
543	* Note that hypervisor page directories are not present in the guest's tables, so this check
544	* is sufficient.
545	*/
546	bool fWrite = !!(fAccess & X86_PTE_RW);
547	bool fUser = !!(fAccess & X86_PTE_US);
548	if ( !(fPage & X86_PTE_P)
549	\|\| (fWrite && !(fPage & X86_PTE_RW))
550	\|\| (fUser && !(fPage & X86_PTE_US)) )
551	{
552	Log(("PGMIsValidAccess: access violation for %RGv attr %#llx vs %d:%d\n", Addr, fPage, fWrite, fUser));
553	return VINF_EM_RAW_GUEST_TRAP;
554	}
555	if ( RT_SUCCESS(rc)
556	&& PAGE_ADDRESS(Addr) != PAGE_ADDRESS(Addr + cbSize))
557	return PGMIsValidAccess(pVCpu, Addr + PAGE_SIZE, (cbSize > PAGE_SIZE) ? cbSize - PAGE_SIZE : 1, fAccess);
558	return rc;
559	}
560
561
562	/**
563	* Verifies a range of pages for read or write access
564	*
565	* Supports handling of pages marked for dirty bit tracking and CSAM
566	*
567	* @returns VBox status code.
568	* @param pVCpu VMCPU handle.
569	* @param Addr Guest virtual address to check
570	* @param cbSize Access size
571	* @param fAccess Access type (r/w, user/supervisor (X86_PTE_*))
572	*/
573	VMMDECL(int) PGMVerifyAccess(PVMCPU pVCpu, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess)
574	{
575	PVM pVM = pVCpu->CTX_SUFF(pVM);
576
577	AssertMsg(!(fAccess & ~(X86_PTE_US \| X86_PTE_RW)), ("PGMVerifyAccess: invalid access type %08x\n", fAccess));
578
579	/*
580	* Get going.
581	*/
582	uint64_t fPageGst;
583	int rc = PGMGstGetPage(pVCpu, (RTGCPTR)Addr, &fPageGst, NULL);
584	if (RT_FAILURE(rc))
585	{
586	Log(("PGMVerifyAccess: access violation for %RGv rc=%d\n", Addr, rc));
587	return VINF_EM_RAW_GUEST_TRAP;
588	}
589
590	/*
591	* Check if the access would cause a page fault
592	*
593	* Note that hypervisor page directories are not present in the guest's tables, so this check
594	* is sufficient.
595	*/
596	const bool fWrite = !!(fAccess & X86_PTE_RW);
597	const bool fUser = !!(fAccess & X86_PTE_US);
598	if ( !(fPageGst & X86_PTE_P)
599	\|\| (fWrite && !(fPageGst & X86_PTE_RW))
600	\|\| (fUser && !(fPageGst & X86_PTE_US)) )
601	{
602	Log(("PGMVerifyAccess: access violation for %RGv attr %#llx vs %d:%d\n", Addr, fPageGst, fWrite, fUser));
603	return VINF_EM_RAW_GUEST_TRAP;
604	}
605
606	if (!HWACCMIsNestedPagingActive(pVM))
607	{
608	/*
609	* Next step is to verify if we protected this page for dirty bit tracking or for CSAM scanning
610	*/
611	rc = PGMShwGetPage(pVCpu, (RTGCPTR)Addr, NULL, NULL);
612	if ( rc == VERR_PAGE_NOT_PRESENT
613	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT)
614	{
615	/*
616	* Page is not present in our page tables.
617	* Try to sync it!
618	*/
619	Assert(X86_TRAP_PF_RW == X86_PTE_RW && X86_TRAP_PF_US == X86_PTE_US);
620	uint32_t uErr = fAccess & (X86_TRAP_PF_RW \| X86_TRAP_PF_US);
621	rc = PGM_BTH_PFN(VerifyAccessSyncPage, pVCpu)(pVCpu, Addr, fPageGst, uErr);
622	if (rc != VINF_SUCCESS)
623	return rc;
624	}
625	else
626	AssertMsg(rc == VINF_SUCCESS, ("PGMShwGetPage %RGv failed with %Rrc\n", Addr, rc));
627	}
628
629	#if 0 /* def VBOX_STRICT; triggers too often now */
630	/*
631	* This check is a bit paranoid, but useful.
632	*/
633	/** @note this will assert when writing to monitored pages (a bit annoying actually) */
634	uint64_t fPageShw;
635	rc = PGMShwGetPage(pVCpu, (RTGCPTR)Addr, &fPageShw, NULL);
636	if ( (rc == VERR_PAGE_NOT_PRESENT \|\| RT_FAILURE(rc))
637	\|\| (fWrite && !(fPageShw & X86_PTE_RW))
638	\|\| (fUser && !(fPageShw & X86_PTE_US)) )
639	{
640	AssertMsgFailed(("Unexpected access violation for %RGv! rc=%Rrc write=%d user=%d\n",
641	Addr, rc, fWrite && !(fPageShw & X86_PTE_RW), fUser && !(fPageShw & X86_PTE_US)));
642	return VINF_EM_RAW_GUEST_TRAP;
643	}
644	#endif
645
646	if ( RT_SUCCESS(rc)
647	&& ( PAGE_ADDRESS(Addr) != PAGE_ADDRESS(Addr + cbSize - 1)
648	\|\| Addr + cbSize < Addr))
649	{
650	/* Don't recursively call PGMVerifyAccess as we might run out of stack. */
651	for (;;)
652	{
653	Addr += PAGE_SIZE;
654	if (cbSize > PAGE_SIZE)
655	cbSize -= PAGE_SIZE;
656	else
657	cbSize = 1;
658	rc = PGMVerifyAccess(pVCpu, Addr, 1, fAccess);
659	if (rc != VINF_SUCCESS)
660	break;
661	if (PAGE_ADDRESS(Addr) == PAGE_ADDRESS(Addr + cbSize - 1))
662	break;
663	}
664	}
665	return rc;
666	}
667
668
669	/**
670	* Emulation of the invlpg instruction (HC only actually).
671	*
672	* @returns VBox status code, special care required.
673	* @retval VINF_PGM_SYNC_CR3 - handled.
674	* @retval VINF_EM_RAW_EMULATE_INSTR - not handled (RC only).
675	* @retval VERR_REM_FLUSHED_PAGES_OVERFLOW - not handled.
676	*
677	* @param pVCpu VMCPU handle.
678	* @param GCPtrPage Page to invalidate.
679	*
680	* @remark ASSUMES the page table entry or page directory is valid. Fairly
681	* safe, but there could be edge cases!
682	*
683	* @todo Flush page or page directory only if necessary!
684	*/
685	VMMDECL(int) PGMInvalidatePage(PVMCPU pVCpu, RTGCPTR GCPtrPage)
686	{
687	PVM pVM = pVCpu->CTX_SUFF(pVM);
688	int rc;
689	Log3(("PGMInvalidatePage: GCPtrPage=%RGv\n", GCPtrPage));
690
691	#ifndef IN_RING3
692	/*
693	* Notify the recompiler so it can record this instruction.
694	* Failure happens when it's out of space. We'll return to HC in that case.
695	*/
696	rc = REMNotifyInvalidatePage(pVM, GCPtrPage);
697	if (rc != VINF_SUCCESS)
698	return rc;
699	#endif /* !IN_RING3 */
700
701
702	#ifdef IN_RC
703	/*
704	* Check for conflicts and pending CR3 monitoring updates.
705	*/
706	if (!pVM->pgm.s.fMappingsFixed)
707	{
708	if ( pgmGetMapping(pVM, GCPtrPage)
709	&& PGMGstGetPage(pVCpu, GCPtrPage, NULL, NULL) != VERR_PAGE_TABLE_NOT_PRESENT)
710	{
711	LogFlow(("PGMGCInvalidatePage: Conflict!\n"));
712	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
713	STAM_COUNTER_INC(&pVM->pgm.s.StatRCInvlPgConflict);
714	return VINF_PGM_SYNC_CR3;
715	}
716
717	if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
718	{
719	LogFlow(("PGMGCInvalidatePage: PGM_SYNC_MONITOR_CR3 -> reinterpret instruction in R3\n"));
720	STAM_COUNTER_INC(&pVM->pgm.s.StatRCInvlPgSyncMonCR3);
721	return VINF_EM_RAW_EMULATE_INSTR;
722	}
723	}
724	#endif /* IN_RC */
725
726	/*
727	* Call paging mode specific worker.
728	*/
729	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePage), a);
730	pgmLock(pVM);
731	rc = PGM_BTH_PFN(InvalidatePage, pVCpu)(pVCpu, GCPtrPage);
732	pgmUnlock(pVM);
733	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePage), a);
734
735	#ifdef IN_RING3
736	/*
737	* Check if we have a pending update of the CR3 monitoring.
738	*/
739	if ( RT_SUCCESS(rc)
740	&& (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3))
741	{
742	pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
743	Assert(!pVM->pgm.s.fMappingsFixed);
744	}
745
746	/*
747	* Inform CSAM about the flush
748	*
749	* Note: This is to check if monitored pages have been changed; when we implement
750	* callbacks for virtual handlers, this is no longer required.
751	*/
752	CSAMR3FlushPage(pVM, GCPtrPage);
753	#endif /* IN_RING3 */
754	return rc;
755	}
756
757
758	/**
759	* Executes an instruction using the interpreter.
760	*
761	* @returns VBox status code (appropriate for trap handling and GC return).
762	* @param pVM VM handle.
763	* @param pVCpu VMCPU handle.
764	* @param pRegFrame Register frame.
765	* @param pvFault Fault address.
766	*/
767	VMMDECL(int) PGMInterpretInstruction(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
768	{
769	uint32_t cb;
770	int rc = EMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault, &cb);
771	if (rc == VERR_EM_INTERPRETER)
772	rc = VINF_EM_RAW_EMULATE_INSTR;
773	if (rc != VINF_SUCCESS)
774	Log(("PGMInterpretInstruction: returns %Rrc (pvFault=%RGv)\n", rc, pvFault));
775	return rc;
776	}
777
778
779	/**
780	* Gets effective page information (from the VMM page directory).
781	*
782	* @returns VBox status.
783	* @param pVCpu VMCPU handle.
784	* @param GCPtr Guest Context virtual address of the page.
785	* @param pfFlags Where to store the flags. These are X86_PTE_*.
786	* @param pHCPhys Where to store the HC physical address of the page.
787	* This is page aligned.
788	* @remark You should use PGMMapGetPage() for pages in a mapping.
789	*/
790	VMMDECL(int) PGMShwGetPage(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys)
791	{
792	return PGM_SHW_PFN(GetPage, pVCpu)(pVCpu, GCPtr, pfFlags, pHCPhys);
793	}
794
795
796	/**
797	* Sets (replaces) the page flags for a range of pages in the shadow context.
798	*
799	* @returns VBox status.
800	* @param pVCpu VMCPU handle.
801	* @param GCPtr The address of the first page.
802	* @param cb The size of the range in bytes.
803	* @param fFlags Page flags X86_PTE_*, excluding the page mask of course.
804	* @remark You must use PGMMapSetPage() for pages in a mapping.
805	*/
806	VMMDECL(int) PGMShwSetPage(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags)
807	{
808	return PGMShwModifyPage(pVCpu, GCPtr, cb, fFlags, 0);
809	}
810
811
812	/**
813	* Modify page flags for a range of pages in the shadow context.
814	*
815	* The existing flags are ANDed with the fMask and ORed with the fFlags.
816	*
817	* @returns VBox status code.
818	* @param pVCpu VMCPU handle.
819	* @param GCPtr Virtual address of the first page in the range.
820	* @param cb Size (in bytes) of the range to apply the modification to.
821	* @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
822	* @param fMask The AND mask - page flags X86_PTE_*.
823	* Be very CAREFUL when ~'ing constants which could be 32-bit!
824	* @remark You must use PGMMapModifyPage() for pages in a mapping.
825	*/
826	VMMDECL(int) PGMShwModifyPage(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
827	{
828	AssertMsg(!(fFlags & X86_PTE_PAE_PG_MASK), ("fFlags=%#llx\n", fFlags));
829	Assert(cb);
830
831	/*
832	* Align the input.
833	*/
834	cb += GCPtr & PAGE_OFFSET_MASK;
835	cb = RT_ALIGN_Z(cb, PAGE_SIZE);
836	GCPtr = (GCPtr & PAGE_BASE_GC_MASK); /** @todo this ain't necessary, right... */
837
838	/*
839	* Call worker.
840	*/
841	PVM pVM = pVCpu->CTX_SUFF(pVM);
842	pgmLock(pVM);
843	int rc = PGM_SHW_PFN(ModifyPage, pVCpu)(pVCpu, GCPtr, cb, fFlags, fMask);
844	pgmUnlock(pVM);
845	return rc;
846	}
847
848	/**
849	* Gets the shadow page directory for the specified address, PAE.
850	*
851	* @returns Pointer to the shadow PD.
852	* @param pVCpu The VMCPU handle.
853	* @param GCPtr The address.
854	* @param pGstPdpe Guest PDPT entry
855	* @param ppPD Receives address of page directory
856	*/
857	int pgmShwSyncPaePDPtr(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDPE pGstPdpe, PX86PDPAE *ppPD)
858	{
859	const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
860	PX86PDPT pPdpt = pgmShwGetPaePDPTPtr(&pVCpu->pgm.s);
861	PX86PDPE pPdpe = &pPdpt->a[iPdPt];
862	PVM pVM = pVCpu->CTX_SUFF(pVM);
863	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
864	PPGMPOOLPAGE pShwPage;
865	int rc;
866
867	/* Allocate page directory if not present. */
868	if ( !pPdpe->n.u1Present
869	&& !(pPdpe->u & X86_PDPE_PG_MASK))
870	{
871	bool fNestedPaging = HWACCMIsNestedPagingActive(pVM);
872	bool fPaging = !!(CPUMGetGuestCR0(pVCpu) & X86_CR0_PG);
873	RTGCPTR64 GCPdPt;
874	PGMPOOLKIND enmKind;
875
876	# if defined(IN_RC)
877	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
878	PGMDynLockHCPage(pVM, (uint8_t *)pPdpe);
879	# endif
880
881	if (fNestedPaging \|\| !fPaging)
882	{
883	/* AMD-V nested paging or real/protected mode without paging */
884	GCPdPt = (RTGCPTR64)iPdPt << X86_PDPT_SHIFT;
885	enmKind = PGMPOOLKIND_PAE_PD_PHYS;
886	}
887	else
888	{
889	Assert(pGstPdpe);
890
891	if (CPUMGetGuestCR4(pVCpu) & X86_CR4_PAE)
892	{
893	if (!pGstPdpe->n.u1Present)
894	{
895	/* PD not present; guest must reload CR3 to change it.
896	* No need to monitor anything in this case.
897	*/
898	Assert(!HWACCMIsEnabled(pVM));
899
900	GCPdPt = pGstPdpe->u & X86_PDPE_PG_MASK;
901	enmKind = PGMPOOLKIND_PAE_PD_PHYS;
902	pGstPdpe->n.u1Present = 1;
903	}
904	else
905	{
906	GCPdPt = pGstPdpe->u & X86_PDPE_PG_MASK;
907	enmKind = PGMPOOLKIND_PAE_PD_FOR_PAE_PD;
908	}
909	}
910	else
911	{
912	GCPdPt = CPUMGetGuestCR3(pVCpu);
913	enmKind = (PGMPOOLKIND)(PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD + iPdPt);
914	}
915	}
916
917	/* Create a reference back to the PDPT by using the index in its shadow page. */
918	rc = pgmPoolAlloc(pVM, GCPdPt, enmKind, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPdPt, &pShwPage);
919	AssertRCReturn(rc, rc);
920
921	/* The PD was cached or created; hook it up now. */
922	pPdpe->u \|= pShwPage->Core.Key
923	\| (pGstPdpe->u & ~(X86_PDPE_PG_MASK \| X86_PDPE_AVL_MASK \| X86_PDPE_PCD \| X86_PDPE_PWT));
924
925	# if defined(IN_RC)
926	/* In 32 bits PAE mode we must invalidate the TLB when changing a PDPT entry; the CPU fetches them only during cr3 load, so any
927	* non-present PDPT will continue to cause page faults.
928	*/
929	ASMReloadCR3();
930	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdpe);
931	# endif
932	}
933	else
934	{
935	pShwPage = pgmPoolGetPage(pPool, pPdpe->u & X86_PDPE_PG_MASK);
936	AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
937	Assert((pPdpe->u & X86_PDPE_PG_MASK) == pShwPage->Core.Key);
938
939	pgmPoolCacheUsed(pPool, pShwPage);
940	}
941	*ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
942	return VINF_SUCCESS;
943	}
944
945
946	/**
947	* Gets the pointer to the shadow page directory entry for an address, PAE.
948	*
949	* @returns Pointer to the PDE.
950	* @param pPGM Pointer to the PGMCPU instance data.
951	* @param GCPtr The address.
952	* @param ppShwPde Receives the address of the pgm pool page for the shadow page directory
953	*/
954	DECLINLINE(int) pgmShwGetPaePoolPagePD(PPGMCPU pPGM, RTGCPTR GCPtr, PPGMPOOLPAGE *ppShwPde)
955	{
956	const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
957	PX86PDPT pPdpt = pgmShwGetPaePDPTPtr(pPGM);
958	AssertReturn(pPdpt, VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT); /* can't happen */
959	if (!pPdpt->a[iPdPt].n.u1Present)
960	{
961	LogFlow(("pgmShwGetPaePoolPagePD: PD %d not present (%RX64)\n", iPdPt, pPdpt->a[iPdPt].u));
962	return VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT;
963	}
964	AssertMsg(pPdpt->a[iPdPt].u & X86_PDPE_PG_MASK, ("GCPtr=%RGv\n", GCPtr));
965
966	/* Fetch the pgm pool shadow descriptor. */
967	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(PGMCPU2PGM(pPGM)->CTX_SUFF(pPool), pPdpt->a[iPdPt].u & X86_PDPE_PG_MASK);
968	AssertReturn(pShwPde, VERR_INTERNAL_ERROR);
969
970	*ppShwPde = pShwPde;
971	return VINF_SUCCESS;
972	}
973
974	#ifndef IN_RC
975
976	/**
977	* Syncs the SHADOW page directory pointer for the specified address.
978	*
979	* Allocates backing pages in case the PDPT or PML4 entry is missing.
980	*
981	* The caller is responsible for making sure the guest has a valid PD before
982	* calling this function.
983	*
984	* @returns VBox status.
985	* @param pVCpu VMCPU handle.
986	* @param GCPtr The address.
987	* @param pGstPml4e Guest PML4 entry
988	* @param pGstPdpe Guest PDPT entry
989	* @param ppPD Receives address of page directory
990	*/
991	int pgmShwSyncLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PX86PML4E pGstPml4e, PX86PDPE pGstPdpe, PX86PDPAE *ppPD)
992	{
993	PPGMCPU pPGM = &pVCpu->pgm.s;
994	PVM pVM = pVCpu->CTX_SUFF(pVM);
995	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
996	const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
997	PX86PML4E pPml4e = pgmShwGetLongModePML4EPtr(pPGM, iPml4);
998	bool fNestedPaging = HWACCMIsNestedPagingActive(pVM);
999	bool fPaging = !!(CPUMGetGuestCR0(pVCpu) & X86_CR0_PG);
1000	PPGMPOOLPAGE pShwPage;
1001	int rc;
1002
1003	/* Allocate page directory pointer table if not present. */
1004	if ( !pPml4e->n.u1Present
1005	&& !(pPml4e->u & X86_PML4E_PG_MASK))
1006	{
1007	RTGCPTR64 GCPml4;
1008	PGMPOOLKIND enmKind;
1009
1010	Assert(pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
1011
1012	if (fNestedPaging \|\| !fPaging)
1013	{
1014	/* AMD-V nested paging or real/protected mode without paging */
1015	GCPml4 = (RTGCPTR64)iPml4 << X86_PML4_SHIFT;
1016	enmKind = PGMPOOLKIND_64BIT_PDPT_FOR_PHYS;
1017	}
1018	else
1019	{
1020	Assert(pGstPml4e && pGstPdpe);
1021
1022	GCPml4 = pGstPml4e->u & X86_PML4E_PG_MASK;
1023	enmKind = PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT;
1024	}
1025
1026	/* Create a reference back to the PDPT by using the index in its shadow page. */
1027	rc = pgmPoolAlloc(pVM, GCPml4, enmKind, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPml4, &pShwPage);
1028	AssertRCReturn(rc, rc);
1029	}
1030	else
1031	{
1032	pShwPage = pgmPoolGetPage(pPool, pPml4e->u & X86_PML4E_PG_MASK);
1033	AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1034
1035	pgmPoolCacheUsed(pPool, pShwPage);
1036	}
1037	/* The PDPT was cached or created; hook it up now. */
1038	pPml4e->u \|= pShwPage->Core.Key
1039	\| (pGstPml4e->u & ~(X86_PML4E_PG_MASK \| X86_PML4E_AVL_MASK \| X86_PML4E_PCD \| X86_PML4E_PWT));
1040
1041	const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1042	PX86PDPT pPdpt = (PX86PDPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1043	PX86PDPE pPdpe = &pPdpt->a[iPdPt];
1044
1045	/* Allocate page directory if not present. */
1046	if ( !pPdpe->n.u1Present
1047	&& !(pPdpe->u & X86_PDPE_PG_MASK))
1048	{
1049	RTGCPTR64 GCPdPt;
1050	PGMPOOLKIND enmKind;
1051
1052	if (fNestedPaging \|\| !fPaging)
1053	{
1054	/* AMD-V nested paging or real/protected mode without paging */
1055	GCPdPt = (RTGCPTR64)iPdPt << X86_PDPT_SHIFT;
1056	enmKind = PGMPOOLKIND_64BIT_PD_FOR_PHYS;
1057	}
1058	else
1059	{
1060	Assert(pGstPdpe);
1061
1062	GCPdPt = pGstPdpe->u & X86_PDPE_PG_MASK;
1063	enmKind = PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD;
1064	}
1065
1066	/* Create a reference back to the PDPT by using the index in its shadow page. */
1067	rc = pgmPoolAlloc(pVM, GCPdPt, enmKind, pShwPage->idx, iPdPt, &pShwPage);
1068	AssertRCReturn(rc, rc);
1069	}
1070	else
1071	{
1072	pShwPage = pgmPoolGetPage(pPool, pPdpe->u & X86_PDPE_PG_MASK);
1073	AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1074
1075	pgmPoolCacheUsed(pPool, pShwPage);
1076	}
1077	/* The PD was cached or created; hook it up now. */
1078	pPdpe->u \|= pShwPage->Core.Key
1079	\| (pGstPdpe->u & ~(X86_PDPE_PG_MASK \| X86_PDPE_AVL_MASK \| X86_PDPE_PCD \| X86_PDPE_PWT));
1080
1081	*ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1082	return VINF_SUCCESS;
1083	}
1084
1085
1086	/**
1087	* Gets the SHADOW page directory pointer for the specified address (long mode).
1088	*
1089	* @returns VBox status.
1090	* @param pVCpu VMCPU handle.
1091	* @param GCPtr The address.
1092	* @param ppPdpt Receives address of pdpt
1093	* @param ppPD Receives address of page directory
1094	*/
1095	DECLINLINE(int) pgmShwGetLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PX86PML4E ppPml4e, PX86PDPT ppPdpt, PX86PDPAE *ppPD)
1096	{
1097	PPGMCPU pPGM = &pVCpu->pgm.s;
1098	const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
1099	PCX86PML4E pPml4e = pgmShwGetLongModePML4EPtr(pPGM, iPml4);
1100	AssertReturn(pPml4e, VERR_INTERNAL_ERROR);
1101	if (ppPml4e)
1102	*ppPml4e = (PX86PML4E)pPml4e;
1103
1104	Log4(("pgmShwGetLongModePDPtr %VGv (%VHv) %RX64\n", GCPtr, pPml4e, pPml4e->u));
1105
1106	if (!pPml4e->n.u1Present)
1107	return VERR_PAGE_MAP_LEVEL4_NOT_PRESENT;
1108
1109	PVM pVM = pVCpu->CTX_SUFF(pVM);
1110	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1111	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPml4e->u & X86_PML4E_PG_MASK);
1112	AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1113
1114	const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1115	PCX86PDPT pPdpt = *ppPdpt = (PX86PDPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1116	if (!pPdpt->a[iPdPt].n.u1Present)
1117	return VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT;
1118
1119	pShwPage = pgmPoolGetPage(pPool, pPdpt->a[iPdPt].u & X86_PDPE_PG_MASK);
1120	AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1121
1122	*ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1123	return VINF_SUCCESS;
1124	}
1125
1126
1127	/**
1128	* Syncs the SHADOW EPT page directory pointer for the specified address. Allocates
1129	* backing pages in case the PDPT or PML4 entry is missing.
1130	*
1131	* @returns VBox status.
1132	* @param pVCpu VMCPU handle.
1133	* @param GCPtr The address.
1134	* @param ppPdpt Receives address of pdpt
1135	* @param ppPD Receives address of page directory
1136	*/
1137	int pgmShwGetEPTPDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PEPTPDPT ppPdpt, PEPTPD ppPD)
1138	{
1139	PPGMCPU pPGM = &pVCpu->pgm.s;
1140	PVM pVM = pVCpu->CTX_SUFF(pVM);
1141	const unsigned iPml4 = (GCPtr >> EPT_PML4_SHIFT) & EPT_PML4_MASK;
1142	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1143	PEPTPML4 pPml4;
1144	PEPTPML4E pPml4e;
1145	PPGMPOOLPAGE pShwPage;
1146	int rc;
1147
1148	Assert(HWACCMIsNestedPagingActive(pVM));
1149
1150	pPml4 = (PEPTPML4)PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
1151	Assert(pPml4);
1152
1153	/* Allocate page directory pointer table if not present. */
1154	pPml4e = &pPml4->a[iPml4];
1155	if ( !pPml4e->n.u1Present
1156	&& !(pPml4e->u & EPT_PML4E_PG_MASK))
1157	{
1158	Assert(!(pPml4e->u & EPT_PML4E_PG_MASK));
1159	RTGCPTR64 GCPml4 = (RTGCPTR64)iPml4 << EPT_PML4_SHIFT;
1160
1161	rc = pgmPoolAlloc(pVM, GCPml4, PGMPOOLKIND_EPT_PDPT_FOR_PHYS, PGMPOOL_IDX_NESTED_ROOT, iPml4, &pShwPage);
1162	AssertRCReturn(rc, rc);
1163	}
1164	else
1165	{
1166	pShwPage = pgmPoolGetPage(pPool, pPml4e->u & EPT_PML4E_PG_MASK);
1167	AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1168
1169	pgmPoolCacheUsed(pPool, pShwPage);
1170	}
1171	/* The PDPT was cached or created; hook it up now and fill with the default value. */
1172	pPml4e->u = pShwPage->Core.Key;
1173	pPml4e->n.u1Present = 1;
1174	pPml4e->n.u1Write = 1;
1175	pPml4e->n.u1Execute = 1;
1176
1177	const unsigned iPdPt = (GCPtr >> EPT_PDPT_SHIFT) & EPT_PDPT_MASK;
1178	PEPTPDPT pPdpt = (PEPTPDPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1179	PEPTPDPTE pPdpe = &pPdpt->a[iPdPt];
1180
1181	if (ppPdpt)
1182	*ppPdpt = pPdpt;
1183
1184	/* Allocate page directory if not present. */
1185	if ( !pPdpe->n.u1Present
1186	&& !(pPdpe->u & EPT_PDPTE_PG_MASK))
1187	{
1188	RTGCPTR64 GCPdPt = (RTGCPTR64)iPdPt << EPT_PDPT_SHIFT;
1189
1190	rc = pgmPoolAlloc(pVM, GCPdPt, PGMPOOLKIND_64BIT_PD_FOR_PHYS, pShwPage->idx, iPdPt, &pShwPage);
1191	AssertRCReturn(rc, rc);
1192	}
1193	else
1194	{
1195	pShwPage = pgmPoolGetPage(pPool, pPdpe->u & EPT_PDPTE_PG_MASK);
1196	AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1197
1198	pgmPoolCacheUsed(pPool, pShwPage);
1199	}
1200	/* The PD was cached or created; hook it up now and fill with the default value. */
1201	pPdpe->u = pShwPage->Core.Key;
1202	pPdpe->n.u1Present = 1;
1203	pPdpe->n.u1Write = 1;
1204	pPdpe->n.u1Execute = 1;
1205
1206	*ppPD = (PEPTPD)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1207	return VINF_SUCCESS;
1208	}
1209
1210	#endif /* IN_RC */
1211
1212	/**
1213	* Gets effective Guest OS page information.
1214	*
1215	* When GCPtr is in a big page, the function will return as if it was a normal
1216	* 4KB page. If the need for distinguishing between big and normal page becomes
1217	* necessary at a later point, a PGMGstGetPage() will be created for that
1218	* purpose.
1219	*
1220	* @returns VBox status.
1221	* @param pVCpu VMCPU handle.
1222	* @param GCPtr Guest Context virtual address of the page.
1223	* @param pfFlags Where to store the flags. These are X86_PTE_*, even for big pages.
1224	* @param pGCPhys Where to store the GC physical address of the page.
1225	* This is page aligned. The fact that the
1226	*/
1227	VMMDECL(int) PGMGstGetPage(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys)
1228	{
1229	return PGM_GST_PFN(GetPage, pVCpu)(pVCpu, GCPtr, pfFlags, pGCPhys);
1230	}
1231
1232
1233	/**
1234	* Checks if the page is present.
1235	*
1236	* @returns true if the page is present.
1237	* @returns false if the page is not present.
1238	* @param pVCpu VMCPU handle.
1239	* @param GCPtr Address within the page.
1240	*/
1241	VMMDECL(bool) PGMGstIsPagePresent(PVMCPU pVCpu, RTGCPTR GCPtr)
1242	{
1243	int rc = PGMGstGetPage(pVCpu, GCPtr, NULL, NULL);
1244	return RT_SUCCESS(rc);
1245	}
1246
1247
1248	/**
1249	* Sets (replaces) the page flags for a range of pages in the guest's tables.
1250	*
1251	* @returns VBox status.
1252	* @param pVCpu VMCPU handle.
1253	* @param GCPtr The address of the first page.
1254	* @param cb The size of the range in bytes.
1255	* @param fFlags Page flags X86_PTE_*, excluding the page mask of course.
1256	*/
1257	VMMDECL(int) PGMGstSetPage(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags)
1258	{
1259	return PGMGstModifyPage(pVCpu, GCPtr, cb, fFlags, 0);
1260	}
1261
1262
1263	/**
1264	* Modify page flags for a range of pages in the guest's tables
1265	*
1266	* The existing flags are ANDed with the fMask and ORed with the fFlags.
1267	*
1268	* @returns VBox status code.
1269	* @param pVCpu VMCPU handle.
1270	* @param GCPtr Virtual address of the first page in the range.
1271	* @param cb Size (in bytes) of the range to apply the modification to.
1272	* @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
1273	* @param fMask The AND mask - page flags X86_PTE_*, excluding the page mask of course.
1274	* Be very CAREFUL when ~'ing constants which could be 32-bit!
1275	*/
1276	VMMDECL(int) PGMGstModifyPage(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
1277	{
1278	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_MID_Z(Stat,GstModifyPage), a);
1279
1280	/*
1281	* Validate input.
1282	*/
1283	AssertMsg(!(fFlags & X86_PTE_PAE_PG_MASK), ("fFlags=%#llx\n", fFlags));
1284	Assert(cb);
1285
1286	LogFlow(("PGMGstModifyPage %RGv %d bytes fFlags=%08llx fMask=%08llx\n", GCPtr, cb, fFlags, fMask));
1287
1288	/*
1289	* Adjust input.
1290	*/
1291	cb += GCPtr & PAGE_OFFSET_MASK;
1292	cb = RT_ALIGN_Z(cb, PAGE_SIZE);
1293	GCPtr = (GCPtr & PAGE_BASE_GC_MASK);
1294
1295	/*
1296	* Call worker.
1297	*/
1298	int rc = PGM_GST_PFN(ModifyPage, pVCpu)(pVCpu, GCPtr, cb, fFlags, fMask);
1299
1300	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,GstModifyPage), a);
1301	return rc;
1302	}
1303
1304	#ifdef IN_RING3
1305
1306	/**
1307	* Performs the lazy mapping of the 32-bit guest PD.
1308	*
1309	* @returns Pointer to the mapping.
1310	* @param pPGM The PGM instance data.
1311	*/
1312	PX86PD pgmGstLazyMap32BitPD(PPGMCPU pPGM)
1313	{
1314	Assert(!pPGM->CTX_SUFF(pGst32BitPd));
1315	PVM pVM = PGMCPU2VM(pPGM);
1316	pgmLock(pVM);
1317
1318	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, pPGM->GCPhysCR3);
1319	AssertReturn(pPage, NULL);
1320
1321	RTHCPTR HCPtrGuestCR3;
1322	int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, pPGM->GCPhysCR3 & X86_CR3_PAGE_MASK, (void **)&HCPtrGuestCR3);
1323	AssertRCReturn(rc, NULL);
1324
1325	pPGM->pGst32BitPdR3 = (R3PTRTYPE(PX86PD))HCPtrGuestCR3;
1326	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1327	pPGM->pGst32BitPdR0 = (R0PTRTYPE(PX86PD))HCPtrGuestCR3;
1328	# endif
1329
1330	pgmUnlock(pVM);
1331	return pPGM->CTX_SUFF(pGst32BitPd);
1332	}
1333
1334
1335	/**
1336	* Performs the lazy mapping of the PAE guest PDPT.
1337	*
1338	* @returns Pointer to the mapping.
1339	* @param pPGM The PGM instance data.
1340	*/
1341	PX86PDPT pgmGstLazyMapPaePDPT(PPGMCPU pPGM)
1342	{
1343	Assert(!pPGM->CTX_SUFF(pGstPaePdpt));
1344	PVM pVM = PGMCPU2VM(pPGM);
1345	pgmLock(pVM);
1346
1347	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, pPGM->GCPhysCR3);
1348	AssertReturn(pPage, NULL);
1349
1350	RTHCPTR HCPtrGuestCR3;
1351	int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, pPGM->GCPhysCR3 & X86_CR3_PAE_PAGE_MASK, (void **)&HCPtrGuestCR3);
1352	AssertRCReturn(rc, NULL);
1353
1354	pPGM->pGstPaePdptR3 = (R3PTRTYPE(PX86PDPT))HCPtrGuestCR3;
1355	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1356	pPGM->pGstPaePdptR0 = (R0PTRTYPE(PX86PDPT))HCPtrGuestCR3;
1357	# endif
1358
1359	pgmUnlock(pVM);
1360	return pPGM->CTX_SUFF(pGstPaePdpt);
1361	}
1362
1363	#endif /* IN_RING3 */
1364
1365	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
1366	/**
1367	* Performs the lazy mapping / updating of a PAE guest PD.
1368	*
1369	* @returns Pointer to the mapping.
1370	* @param pPGM The PGM instance data.
1371	* @param iPdpt Which PD entry to map (0..3).
1372	*/
1373	PX86PDPAE pgmGstLazyMapPaePD(PPGMCPU pPGM, uint32_t iPdpt)
1374	{
1375	PVM pVM = PGMCPU2VM(pPGM);
1376	pgmLock(pVM);
1377
1378	PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
1379	Assert(pGuestPDPT);
1380	Assert(pGuestPDPT->a[iPdpt].n.u1Present);
1381	RTGCPHYS GCPhys = pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK;
1382	bool const fChanged = pPGM->aGCPhysGstPaePDs[iPdpt] != GCPhys;
1383
1384	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, GCPhys);
1385	if (RT_LIKELY(pPage))
1386	{
1387	int rc = VINF_SUCCESS;
1388	RTRCPTR RCPtr = NIL_RTRCPTR;
1389	RTHCPTR HCPtr = NIL_RTHCPTR;
1390	#if !defined(IN_RC) && !defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1391	rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, &HCPtr);
1392	AssertRC(rc);
1393	#endif
1394	if (RT_SUCCESS(rc) && fChanged)
1395	{
1396	RCPtr = (RTRCPTR)(RTRCUINTPTR)(pVM->pgm.s.GCPtrCR3Mapping + (1 + iPdpt) * PAGE_SIZE);
1397	rc = PGMMap(pVM, (RTRCUINTPTR)RCPtr, PGM_PAGE_GET_HCPHYS(pPage), PAGE_SIZE, 0);
1398	}
1399	if (RT_SUCCESS(rc))
1400	{
1401	pPGM->apGstPaePDsR3[iPdpt] = (R3PTRTYPE(PX86PDPAE))HCPtr;
1402	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1403	pPGM->apGstPaePDsR0[iPdpt] = (R0PTRTYPE(PX86PDPAE))HCPtr;
1404	# endif
1405	if (fChanged)
1406	{
1407	pPGM->aGCPhysGstPaePDs[iPdpt] = GCPhys;
1408	pPGM->apGstPaePDsRC[iPdpt] = (RCPTRTYPE(PX86PDPAE))RCPtr;
1409	}
1410
1411	pgmUnlock(pVM);
1412	return pPGM->CTX_SUFF(apGstPaePDs)[iPdpt];
1413	}
1414	}
1415
1416	/* Invalid page or some failure, invalidate the entry. */
1417	pPGM->aGCPhysGstPaePDs[iPdpt] = NIL_RTGCPHYS;
1418	pPGM->apGstPaePDsR3[iPdpt] = 0;
1419	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1420	pPGM->apGstPaePDsR0[iPdpt] = 0;
1421	# endif
1422	pPGM->apGstPaePDsRC[iPdpt] = 0;
1423
1424	pgmUnlock(pVM);
1425	return NULL;
1426	}
1427	#endif /* !VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
1428
1429
1430	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R3
1431	/**
1432	* Performs the lazy mapping of the 32-bit guest PD.
1433	*
1434	* @returns Pointer to the mapping.
1435	* @param pPGM The PGM instance data.
1436	*/
1437	PX86PML4 pgmGstLazyMapPml4(PPGMCPU pPGM)
1438	{
1439	Assert(!pPGM->CTX_SUFF(pGstAmd64Pml4));
1440	PVM pVM = PGMCPU2VM(pPGM);
1441	pgmLock(pVM);
1442
1443	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, pPGM->GCPhysCR3);
1444	AssertReturn(pPage, NULL);
1445
1446	RTHCPTR HCPtrGuestCR3;
1447	int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, pPGM->GCPhysCR3 & X86_CR3_AMD64_PAGE_MASK, (void **)&HCPtrGuestCR3);
1448	AssertRCReturn(rc, NULL);
1449
1450	pPGM->pGstAmd64Pml4R3 = (R3PTRTYPE(PX86PML4))HCPtrGuestCR3;
1451	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1452	pPGM->pGstAmd64Pml4R0 = (R0PTRTYPE(PX86PML4))HCPtrGuestCR3;
1453	# endif
1454
1455	pgmUnlock(pVM);
1456	return pPGM->CTX_SUFF(pGstAmd64Pml4);
1457	}
1458	#endif /* VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R3 */
1459
1460
1461	/**
1462	* Gets the specified page directory pointer table entry.
1463	*
1464	* @returns PDP entry
1465	* @param pVCpu VMCPU handle.
1466	* @param iPdpt PDPT index
1467	*/
1468	VMMDECL(X86PDPE) PGMGstGetPaePDPtr(PVMCPU pVCpu, unsigned iPdpt)
1469	{
1470	Assert(iPdpt <= 3);
1471	return pgmGstGetPaePDPTPtr(&pVCpu->pgm.s)->a[iPdpt & 3];
1472	}
1473
1474
1475	/**
1476	* Gets the current CR3 register value for the shadow memory context.
1477	* @returns CR3 value.
1478	* @param pVCpu VMCPU handle.
1479	*/
1480	VMMDECL(RTHCPHYS) PGMGetHyperCR3(PVMCPU pVCpu)
1481	{
1482	PPGMPOOLPAGE pPoolPage = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
1483	AssertPtrReturn(pPoolPage, 0);
1484	return pPoolPage->Core.Key;
1485	}
1486
1487
1488	/**
1489	* Gets the current CR3 register value for the nested memory context.
1490	* @returns CR3 value.
1491	* @param pVCpu VMCPU handle.
1492	*/
1493	VMMDECL(RTHCPHYS) PGMGetNestedCR3(PVMCPU pVCpu, PGMMODE enmShadowMode)
1494	{
1495	Assert(pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
1496	return pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->Core.Key;
1497	}
1498
1499
1500	/**
1501	* Gets the current CR3 register value for the HC intermediate memory context.
1502	* @returns CR3 value.
1503	* @param pVM The VM handle.
1504	*/
1505	VMMDECL(RTHCPHYS) PGMGetInterHCCR3(PVM pVM)
1506	{
1507	switch (pVM->pgm.s.enmHostMode)
1508	{
1509	case SUPPAGINGMODE_32_BIT:
1510	case SUPPAGINGMODE_32_BIT_GLOBAL:
1511	return pVM->pgm.s.HCPhysInterPD;
1512
1513	case SUPPAGINGMODE_PAE:
1514	case SUPPAGINGMODE_PAE_GLOBAL:
1515	case SUPPAGINGMODE_PAE_NX:
1516	case SUPPAGINGMODE_PAE_GLOBAL_NX:
1517	return pVM->pgm.s.HCPhysInterPaePDPT;
1518
1519	case SUPPAGINGMODE_AMD64:
1520	case SUPPAGINGMODE_AMD64_GLOBAL:
1521	case SUPPAGINGMODE_AMD64_NX:
1522	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1523	return pVM->pgm.s.HCPhysInterPaePDPT;
1524
1525	default:
1526	AssertMsgFailed(("enmHostMode=%d\n", pVM->pgm.s.enmHostMode));
1527	return ~0;
1528	}
1529	}
1530
1531
1532	/**
1533	* Gets the current CR3 register value for the RC intermediate memory context.
1534	* @returns CR3 value.
1535	* @param pVM The VM handle.
1536	* @param pVCpu VMCPU handle.
1537	*/
1538	VMMDECL(RTHCPHYS) PGMGetInterRCCR3(PVM pVM, PVMCPU pVCpu)
1539	{
1540	switch (pVCpu->pgm.s.enmShadowMode)
1541	{
1542	case PGMMODE_32_BIT:
1543	return pVM->pgm.s.HCPhysInterPD;
1544
1545	case PGMMODE_PAE:
1546	case PGMMODE_PAE_NX:
1547	return pVM->pgm.s.HCPhysInterPaePDPT;
1548
1549	case PGMMODE_AMD64:
1550	case PGMMODE_AMD64_NX:
1551	return pVM->pgm.s.HCPhysInterPaePML4;
1552
1553	case PGMMODE_EPT:
1554	case PGMMODE_NESTED:
1555	return 0; /* not relevant */
1556
1557	default:
1558	AssertMsgFailed(("enmShadowMode=%d\n", pVCpu->pgm.s.enmShadowMode));
1559	return ~0;
1560	}
1561	}
1562
1563
1564	/**
1565	* Gets the CR3 register value for the 32-Bit intermediate memory context.
1566	* @returns CR3 value.
1567	* @param pVM The VM handle.
1568	*/
1569	VMMDECL(RTHCPHYS) PGMGetInter32BitCR3(PVM pVM)
1570	{
1571	return pVM->pgm.s.HCPhysInterPD;
1572	}
1573
1574
1575	/**
1576	* Gets the CR3 register value for the PAE intermediate memory context.
1577	* @returns CR3 value.
1578	* @param pVM The VM handle.
1579	*/
1580	VMMDECL(RTHCPHYS) PGMGetInterPaeCR3(PVM pVM)
1581	{
1582	return pVM->pgm.s.HCPhysInterPaePDPT;
1583	}
1584
1585
1586	/**
1587	* Gets the CR3 register value for the AMD64 intermediate memory context.
1588	* @returns CR3 value.
1589	* @param pVM The VM handle.
1590	*/
1591	VMMDECL(RTHCPHYS) PGMGetInterAmd64CR3(PVM pVM)
1592	{
1593	return pVM->pgm.s.HCPhysInterPaePML4;
1594	}
1595
1596
1597	/**
1598	* Performs and schedules necessary updates following a CR3 load or reload.
1599	*
1600	* This will normally involve mapping the guest PD or nPDPT
1601	*
1602	* @returns VBox status code.
1603	* @retval VINF_PGM_SYNC_CR3 if monitoring requires a CR3 sync. This can
1604	* safely be ignored and overridden since the FF will be set too then.
1605	* @param pVCpu VMCPU handle.
1606	* @param cr3 The new cr3.
1607	* @param fGlobal Indicates whether this is a global flush or not.
1608	*/
1609	VMMDECL(int) PGMFlushTLB(PVMCPU pVCpu, uint64_t cr3, bool fGlobal)
1610	{
1611	PVM pVM = pVCpu->CTX_SUFF(pVM);
1612
1613	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_MID_Z(Stat,FlushTLB), a);
1614
1615	/*
1616	* Always flag the necessary updates; necessary for hardware acceleration
1617	*/
1618	/** @todo optimize this, it shouldn't always be necessary. */
1619	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
1620	if (fGlobal)
1621	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
1622	LogFlow(("PGMFlushTLB: cr3=%RX64 OldCr3=%RX64 fGlobal=%d\n", cr3, pVCpu->pgm.s.GCPhysCR3, fGlobal));
1623
1624	/*
1625	* Remap the CR3 content and adjust the monitoring if CR3 was actually changed.
1626	*/
1627	int rc = VINF_SUCCESS;
1628	RTGCPHYS GCPhysCR3;
1629	switch (pVCpu->pgm.s.enmGuestMode)
1630	{
1631	case PGMMODE_PAE:
1632	case PGMMODE_PAE_NX:
1633	GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAE_PAGE_MASK);
1634	break;
1635	case PGMMODE_AMD64:
1636	case PGMMODE_AMD64_NX:
1637	GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_AMD64_PAGE_MASK);
1638	break;
1639	default:
1640	GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAGE_MASK);
1641	break;
1642	}
1643
1644	if (pVCpu->pgm.s.GCPhysCR3 != GCPhysCR3)
1645	{
1646	RTGCPHYS GCPhysOldCR3 = pVCpu->pgm.s.GCPhysCR3;
1647	pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3;
1648	rc = PGM_BTH_PFN(MapCR3, pVCpu)(pVCpu, GCPhysCR3);
1649	if (RT_LIKELY(rc == VINF_SUCCESS))
1650	{
1651	if (!pVM->pgm.s.fMappingsFixed)
1652	{
1653	pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
1654	}
1655	}
1656	else
1657	{
1658	AssertMsg(rc == VINF_PGM_SYNC_CR3, ("%Rrc\n", rc));
1659	Assert(VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \| VMCPU_FF_PGM_SYNC_CR3));
1660	pVCpu->pgm.s.GCPhysCR3 = GCPhysOldCR3;
1661	pVCpu->pgm.s.fSyncFlags \|= PGM_SYNC_MAP_CR3;
1662	if (!pVM->pgm.s.fMappingsFixed)
1663	pVCpu->pgm.s.fSyncFlags \|= PGM_SYNC_MONITOR_CR3;
1664	}
1665
1666	if (fGlobal)
1667	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,FlushTLBNewCR3Global));
1668	else
1669	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,FlushTLBNewCR3));
1670	}
1671	else
1672	{
1673	/*
1674	* Check if we have a pending update of the CR3 monitoring.
1675	*/
1676	if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
1677	{
1678	pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
1679	Assert(!pVM->pgm.s.fMappingsFixed);
1680	}
1681	if (fGlobal)
1682	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,FlushTLBSameCR3Global));
1683	else
1684	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,FlushTLBSameCR3));
1685	}
1686
1687	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,FlushTLB), a);
1688	return rc;
1689	}
1690
1691
1692	/**
1693	* Performs and schedules necessary updates following a CR3 load or reload when
1694	* using nested or extended paging.
1695	*
1696	* This API is an alterantive to PDMFlushTLB that avoids actually flushing the
1697	* TLB and triggering a SyncCR3.
1698	*
1699	* This will normally involve mapping the guest PD or nPDPT
1700	*
1701	* @returns VBox status code.
1702	* @retval VINF_SUCCESS.
1703	* @retval (If applied when not in nested mode: VINF_PGM_SYNC_CR3 if monitoring
1704	* requires a CR3 sync. This can safely be ignored and overridden since
1705	* the FF will be set too then.)
1706	* @param pVCpu VMCPU handle.
1707	* @param cr3 The new cr3.
1708	*/
1709	VMMDECL(int) PGMUpdateCR3(PVMCPU pVCpu, uint64_t cr3)
1710	{
1711	PVM pVM = pVCpu->CTX_SUFF(pVM);
1712
1713	LogFlow(("PGMUpdateCR3: cr3=%RX64 OldCr3=%RX64\n", cr3, pVCpu->pgm.s.GCPhysCR3));
1714
1715	/* We assume we're only called in nested paging mode. */
1716	Assert(pVM->pgm.s.fMappingsFixed);
1717	Assert(!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3));
1718	Assert(HWACCMIsNestedPagingActive(pVM) \|\| pVCpu->pgm.s.enmShadowMode == PGMMODE_EPT);
1719
1720	/*
1721	* Remap the CR3 content and adjust the monitoring if CR3 was actually changed.
1722	*/
1723	int rc = VINF_SUCCESS;
1724	RTGCPHYS GCPhysCR3;
1725	switch (pVCpu->pgm.s.enmGuestMode)
1726	{
1727	case PGMMODE_PAE:
1728	case PGMMODE_PAE_NX:
1729	GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAE_PAGE_MASK);
1730	break;
1731	case PGMMODE_AMD64:
1732	case PGMMODE_AMD64_NX:
1733	GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_AMD64_PAGE_MASK);
1734	break;
1735	default:
1736	GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAGE_MASK);
1737	break;
1738	}
1739	if (pVCpu->pgm.s.GCPhysCR3 != GCPhysCR3)
1740	{
1741	pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3;
1742	rc = PGM_BTH_PFN(MapCR3, pVCpu)(pVCpu, GCPhysCR3);
1743	AssertRCSuccess(rc); /* Assumes VINF_PGM_SYNC_CR3 doesn't apply to nested paging. / /* @todo this isn't true for the mac, but we need hw to test/fix this. */
1744	}
1745	return rc;
1746	}
1747
1748
1749	/**
1750	* Synchronize the paging structures.
1751	*
1752	* This function is called in response to the VM_FF_PGM_SYNC_CR3 and
1753	* VM_FF_PGM_SYNC_CR3_NONGLOBAL. Those two force action flags are set
1754	* in several places, most importantly whenever the CR3 is loaded.
1755	*
1756	* @returns VBox status code.
1757	* @param pVCpu VMCPU handle.
1758	* @param cr0 Guest context CR0 register
1759	* @param cr3 Guest context CR3 register
1760	* @param cr4 Guest context CR4 register
1761	* @param fGlobal Including global page directories or not
1762	*/
1763	VMMDECL(int) PGMSyncCR3(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
1764	{
1765	PVM pVM = pVCpu->CTX_SUFF(pVM);
1766	int rc;
1767
1768	#ifdef PGMPOOL_WITH_MONITORING
1769	/*
1770	* The pool may have pending stuff and even require a return to ring-3 to
1771	* clear the whole thing.
1772	*/
1773	rc = pgmPoolSyncCR3(pVM);
1774	if (rc != VINF_SUCCESS)
1775	return rc;
1776	#endif
1777
1778	/*
1779	* We might be called when we shouldn't.
1780	*
1781	* The mode switching will ensure that the PD is resynced
1782	* after every mode switch. So, if we find ourselves here
1783	* when in protected or real mode we can safely disable the
1784	* FF and return immediately.
1785	*/
1786	if (pVCpu->pgm.s.enmGuestMode <= PGMMODE_PROTECTED)
1787	{
1788	Assert((cr0 & (X86_CR0_PG \| X86_CR0_PE)) != (X86_CR0_PG \| X86_CR0_PE));
1789	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
1790	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
1791	return VINF_SUCCESS;
1792	}
1793
1794	/* If global pages are not supported, then all flushes are global. */
1795	if (!(cr4 & X86_CR4_PGE))
1796	fGlobal = true;
1797	LogFlow(("PGMSyncCR3: cr0=%RX64 cr3=%RX64 cr4=%RX64 fGlobal=%d[%d,%d]\n", cr0, cr3, cr4, fGlobal,
1798	VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3), VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)));
1799
1800	/*
1801	* Check if we need to finish an aborted MapCR3 call (see PGMFlushTLB).
1802	* This should be done before SyncCR3.
1803	*/
1804	if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MAP_CR3)
1805	{
1806	pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MAP_CR3;
1807
1808	RTGCPHYS GCPhysCR3Old = pVCpu->pgm.s.GCPhysCR3;
1809	RTGCPHYS GCPhysCR3;
1810	switch (pVCpu->pgm.s.enmGuestMode)
1811	{
1812	case PGMMODE_PAE:
1813	case PGMMODE_PAE_NX:
1814	GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAE_PAGE_MASK);
1815	break;
1816	case PGMMODE_AMD64:
1817	case PGMMODE_AMD64_NX:
1818	GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_AMD64_PAGE_MASK);
1819	break;
1820	default:
1821	GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAGE_MASK);
1822	break;
1823	}
1824
1825	if (pVCpu->pgm.s.GCPhysCR3 != GCPhysCR3)
1826	{
1827	pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3;
1828	rc = PGM_BTH_PFN(MapCR3, pVCpu)(pVCpu, GCPhysCR3);
1829	}
1830	#ifdef IN_RING3
1831	if (rc == VINF_PGM_SYNC_CR3)
1832	rc = pgmPoolSyncCR3(pVM);
1833	#else
1834	if (rc == VINF_PGM_SYNC_CR3)
1835	{
1836	pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3Old;
1837	return rc;
1838	}
1839	#endif
1840	AssertRCReturn(rc, rc);
1841	AssertRCSuccessReturn(rc, VERR_INTERNAL_ERROR);
1842	}
1843
1844	/*
1845	* Let the 'Bth' function do the work and we'll just keep track of the flags.
1846	*/
1847	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncCR3), a);
1848	rc = PGM_BTH_PFN(SyncCR3, pVCpu)(pVCpu, cr0, cr3, cr4, fGlobal);
1849	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncCR3), a);
1850	AssertMsg(rc == VINF_SUCCESS \|\| rc == VINF_PGM_SYNC_CR3 \|\| RT_FAILURE(rc), ("rc=%Rrc\n", rc));
1851	if (rc == VINF_SUCCESS)
1852	{
1853	if (!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS))
1854	{
1855	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
1856	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
1857	}
1858
1859	/*
1860	* Check if we have a pending update of the CR3 monitoring.
1861	*/
1862	if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
1863	{
1864	pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
1865	Assert(!pVM->pgm.s.fMappingsFixed);
1866	}
1867	}
1868
1869	/*
1870	* Now flush the CR3 (guest context).
1871	*/
1872	if (rc == VINF_SUCCESS)
1873	PGM_INVL_VCPU_TLBS(pVCpu);
1874	return rc;
1875	}
1876
1877
1878	/**
1879	* Called whenever CR0 or CR4 in a way which may change
1880	* the paging mode.
1881	*
1882	* @returns VBox status code, with the following informational code for
1883	* VM scheduling.
1884	* @retval VINF_SUCCESS if the was no change, or it was successfully dealt with.
1885	* @retval VINF_PGM_CHANGE_MODE if we're in RC or R0 and the mode changes.
1886	* (I.e. not in R3.)
1887	* @retval VINF_EM_SUSPEND or VINF_EM_OFF on a fatal runtime error. (R3 only)
1888	*
1889	* @param pVCpu VMCPU handle.
1890	* @param cr0 The new cr0.
1891	* @param cr4 The new cr4.
1892	* @param efer The new extended feature enable register.
1893	*/
1894	VMMDECL(int) PGMChangeMode(PVMCPU pVCpu, uint64_t cr0, uint64_t cr4, uint64_t efer)
1895	{
1896	PVM pVM = pVCpu->CTX_SUFF(pVM);
1897	PGMMODE enmGuestMode;
1898
1899	/*
1900	* Calc the new guest mode.
1901	*/
1902	if (!(cr0 & X86_CR0_PE))
1903	enmGuestMode = PGMMODE_REAL;
1904	else if (!(cr0 & X86_CR0_PG))
1905	enmGuestMode = PGMMODE_PROTECTED;
1906	else if (!(cr4 & X86_CR4_PAE))
1907	enmGuestMode = PGMMODE_32_BIT;
1908	else if (!(efer & MSR_K6_EFER_LME))
1909	{
1910	if (!(efer & MSR_K6_EFER_NXE))
1911	enmGuestMode = PGMMODE_PAE;
1912	else
1913	enmGuestMode = PGMMODE_PAE_NX;
1914	}
1915	else
1916	{
1917	if (!(efer & MSR_K6_EFER_NXE))
1918	enmGuestMode = PGMMODE_AMD64;
1919	else
1920	enmGuestMode = PGMMODE_AMD64_NX;
1921	}
1922
1923	/*
1924	* Did it change?
1925	*/
1926	if (pVCpu->pgm.s.enmGuestMode == enmGuestMode)
1927	return VINF_SUCCESS;
1928
1929	/* Flush the TLB */
1930	PGM_INVL_VCPU_TLBS(pVCpu);
1931
1932	#ifdef IN_RING3
1933	return PGMR3ChangeMode(pVM, pVCpu, enmGuestMode);
1934	#else
1935	LogFlow(("PGMChangeMode: returns VINF_PGM_CHANGE_MODE.\n"));
1936	return VINF_PGM_CHANGE_MODE;
1937	#endif
1938	}
1939
1940
1941	/**
1942	* Gets the current guest paging mode.
1943	*
1944	* If you just need the CPU mode (real/protected/long), use CPUMGetGuestMode().
1945	*
1946	* @returns The current paging mode.
1947	* @param pVCpu VMCPU handle.
1948	*/
1949	VMMDECL(PGMMODE) PGMGetGuestMode(PVMCPU pVCpu)
1950	{
1951	return pVCpu->pgm.s.enmGuestMode;
1952	}
1953
1954
1955	/**
1956	* Gets the current shadow paging mode.
1957	*
1958	* @returns The current paging mode.
1959	* @param pVCpu VMCPU handle.
1960	*/
1961	VMMDECL(PGMMODE) PGMGetShadowMode(PVMCPU pVCpu)
1962	{
1963	return pVCpu->pgm.s.enmShadowMode;
1964	}
1965
1966	/**
1967	* Gets the current host paging mode.
1968	*
1969	* @returns The current paging mode.
1970	* @param pVM The VM handle.
1971	*/
1972	VMMDECL(PGMMODE) PGMGetHostMode(PVM pVM)
1973	{
1974	switch (pVM->pgm.s.enmHostMode)
1975	{
1976	case SUPPAGINGMODE_32_BIT:
1977	case SUPPAGINGMODE_32_BIT_GLOBAL:
1978	return PGMMODE_32_BIT;
1979
1980	case SUPPAGINGMODE_PAE:
1981	case SUPPAGINGMODE_PAE_GLOBAL:
1982	return PGMMODE_PAE;
1983
1984	case SUPPAGINGMODE_PAE_NX:
1985	case SUPPAGINGMODE_PAE_GLOBAL_NX:
1986	return PGMMODE_PAE_NX;
1987
1988	case SUPPAGINGMODE_AMD64:
1989	case SUPPAGINGMODE_AMD64_GLOBAL:
1990	return PGMMODE_AMD64;
1991
1992	case SUPPAGINGMODE_AMD64_NX:
1993	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1994	return PGMMODE_AMD64_NX;
1995
1996	default: AssertMsgFailed(("enmHostMode=%d\n", pVM->pgm.s.enmHostMode)); break;
1997	}
1998
1999	return PGMMODE_INVALID;
2000	}
2001
2002
2003	/**
2004	* Get mode name.
2005	*
2006	* @returns read-only name string.
2007	* @param enmMode The mode which name is desired.
2008	*/
2009	VMMDECL(const char *) PGMGetModeName(PGMMODE enmMode)
2010	{
2011	switch (enmMode)
2012	{
2013	case PGMMODE_REAL: return "Real";
2014	case PGMMODE_PROTECTED: return "Protected";
2015	case PGMMODE_32_BIT: return "32-bit";
2016	case PGMMODE_PAE: return "PAE";
2017	case PGMMODE_PAE_NX: return "PAE+NX";
2018	case PGMMODE_AMD64: return "AMD64";
2019	case PGMMODE_AMD64_NX: return "AMD64+NX";
2020	case PGMMODE_NESTED: return "Nested";
2021	case PGMMODE_EPT: return "EPT";
2022	default: return "unknown mode value";
2023	}
2024	}
2025
2026
2027	/**
2028	* Check if the PGM lock is currently taken.
2029	*
2030	* @returns bool locked/not locked
2031	* @param pVM The VM to operate on.
2032	*/
2033	VMMDECL(bool) PGMIsLocked(PVM pVM)
2034	{
2035	return PDMCritSectIsLocked(&pVM->pgm.s.CritSect);
2036	}
2037
2038	/**
2039	* Check if this VCPU currently owns the PGM lock.
2040	*
2041	* @returns bool owner/not owner
2042	* @param pVM The VM to operate on.
2043	*/
2044	VMMDECL(bool) PGMIsLockOwner(PVM pVM)
2045	{
2046	return PDMCritSectIsOwner(&pVM->pgm.s.CritSect);
2047	}
2048
2049
2050	/**
2051	* Acquire the PGM lock.
2052	*
2053	* @returns VBox status code
2054	* @param pVM The VM to operate on.
2055	*/
2056	int pgmLock(PVM pVM)
2057	{
2058	int rc = PDMCritSectEnter(&pVM->pgm.s.CritSect, VERR_SEM_BUSY);
2059	#ifdef IN_RC
2060	if (rc == VERR_SEM_BUSY)
2061	rc = VMMGCCallHost(pVM, VMMCALLHOST_PGM_LOCK, 0);
2062	#elif defined(IN_RING0)
2063	if (rc == VERR_SEM_BUSY)
2064	rc = VMMR0CallHost(pVM, VMMCALLHOST_PGM_LOCK, 0);
2065	#endif
2066	AssertMsg(rc == VINF_SUCCESS, ("%Rrc\n", rc));
2067	return rc;
2068	}
2069
2070
2071	/**
2072	* Release the PGM lock.
2073	*
2074	* @returns VBox status code
2075	* @param pVM The VM to operate on.
2076	*/
2077	void pgmUnlock(PVM pVM)
2078	{
2079	PDMCritSectLeave(&pVM->pgm.s.CritSect);
2080	}
2081
2082	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2083
2084	/**
2085	* Temporarily maps one guest page specified by GC physical address.
2086	* These pages must have a physical mapping in HC, i.e. they cannot be MMIO pages.
2087	*
2088	* Be WARNED that the dynamic page mapping area is small, 8 pages, thus the space is
2089	* reused after 8 mappings (or perhaps a few more if you score with the cache).
2090	*
2091	* @returns VBox status.
2092	* @param pVM VM handle.
2093	* @param GCPhys GC Physical address of the page.
2094	* @param ppv Where to store the address of the mapping.
2095	*/
2096	VMMDECL(int) PGMDynMapGCPage(PVM pVM, RTGCPHYS GCPhys, void **ppv)
2097	{
2098	AssertMsg(!(GCPhys & PAGE_OFFSET_MASK), ("GCPhys=%RGp\n", GCPhys));
2099
2100	/*
2101	* Get the ram range.
2102	*/
2103	PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
2104	while (pRam && GCPhys - pRam->GCPhys >= pRam->cb)
2105	pRam = pRam->CTX_SUFF(pNext);
2106	if (!pRam)
2107	{
2108	AssertMsgFailed(("Invalid physical address %RGp!\n", GCPhys));
2109	return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2110	}
2111
2112	/*
2113	* Pass it on to PGMDynMapHCPage.
2114	*/
2115	RTHCPHYS HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT]);
2116	//Log(("PGMDynMapGCPage: GCPhys=%RGp HCPhys=%RHp\n", GCPhys, HCPhys));
2117	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2118	pgmR0DynMapHCPageInlined(&pVM->pgm.s, HCPhys, ppv);
2119	#else
2120	PGMDynMapHCPage(pVM, HCPhys, ppv);
2121	#endif
2122	return VINF_SUCCESS;
2123	}
2124
2125
2126	/**
2127	* Temporarily maps one guest page specified by unaligned GC physical address.
2128	* These pages must have a physical mapping in HC, i.e. they cannot be MMIO pages.
2129	*
2130	* Be WARNED that the dynamic page mapping area is small, 8 pages, thus the space is
2131	* reused after 8 mappings (or perhaps a few more if you score with the cache).
2132	*
2133	* The caller is aware that only the speicifed page is mapped and that really bad things
2134	* will happen if writing beyond the page!
2135	*
2136	* @returns VBox status.
2137	* @param pVM VM handle.
2138	* @param GCPhys GC Physical address within the page to be mapped.
2139	* @param ppv Where to store the address of the mapping address corresponding to GCPhys.
2140	*/
2141	VMMDECL(int) PGMDynMapGCPageOff(PVM pVM, RTGCPHYS GCPhys, void **ppv)
2142	{
2143	/*
2144	* Get the ram range.
2145	*/
2146	PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
2147	while (pRam && GCPhys - pRam->GCPhys >= pRam->cb)
2148	pRam = pRam->CTX_SUFF(pNext);
2149	if (!pRam)
2150	{
2151	AssertMsgFailed(("Invalid physical address %RGp!\n", GCPhys));
2152	return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2153	}
2154
2155	/*
2156	* Pass it on to PGMDynMapHCPage.
2157	*/
2158	RTHCPHYS HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT]);
2159	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2160	pgmR0DynMapHCPageInlined(&pVM->pgm.s, HCPhys, ppv);
2161	#else
2162	PGMDynMapHCPage(pVM, HCPhys, ppv);
2163	#endif
2164	ppv = (void )((uintptr_t)*ppv \| (GCPhys & PAGE_OFFSET_MASK));
2165	return VINF_SUCCESS;
2166	}
2167
2168	# ifdef IN_RC
2169
2170	/**
2171	* Temporarily maps one host page specified by HC physical address.
2172	*
2173	* Be WARNED that the dynamic page mapping area is small, 16 pages, thus the space is
2174	* reused after 16 mappings (or perhaps a few more if you score with the cache).
2175	*
2176	* @returns VINF_SUCCESS, will bail out to ring-3 on failure.
2177	* @param pVM VM handle.
2178	* @param HCPhys HC Physical address of the page.
2179	* @param ppv Where to store the address of the mapping. This is the
2180	* address of the PAGE not the exact address corresponding
2181	* to HCPhys. Use PGMDynMapHCPageOff if you care for the
2182	* page offset.
2183	*/
2184	VMMDECL(int) PGMDynMapHCPage(PVM pVM, RTHCPHYS HCPhys, void **ppv)
2185	{
2186	AssertMsg(!(HCPhys & PAGE_OFFSET_MASK), ("HCPhys=%RHp\n", HCPhys));
2187
2188	/*
2189	* Check the cache.
2190	*/
2191	register unsigned iCache;
2192	for (iCache = 0;iCache < RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache);iCache++)
2193	{
2194	static const uint8_t au8Trans[MM_HYPER_DYNAMIC_SIZE >> PAGE_SHIFT][RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache)] =
2195	{
2196	{ 0, 9, 10, 11, 12, 13, 14, 15},
2197	{ 0, 1, 10, 11, 12, 13, 14, 15},
2198	{ 0, 1, 2, 11, 12, 13, 14, 15},
2199	{ 0, 1, 2, 3, 12, 13, 14, 15},
2200	{ 0, 1, 2, 3, 4, 13, 14, 15},
2201	{ 0, 1, 2, 3, 4, 5, 14, 15},
2202	{ 0, 1, 2, 3, 4, 5, 6, 15},
2203	{ 0, 1, 2, 3, 4, 5, 6, 7},
2204	{ 8, 1, 2, 3, 4, 5, 6, 7},
2205	{ 8, 9, 2, 3, 4, 5, 6, 7},
2206	{ 8, 9, 10, 3, 4, 5, 6, 7},
2207	{ 8, 9, 10, 11, 4, 5, 6, 7},
2208	{ 8, 9, 10, 11, 12, 5, 6, 7},
2209	{ 8, 9, 10, 11, 12, 13, 6, 7},
2210	{ 8, 9, 10, 11, 12, 13, 14, 7},
2211	{ 8, 9, 10, 11, 12, 13, 14, 15},
2212	};
2213	AssertCompile(RT_ELEMENTS(au8Trans) == 16);
2214	AssertCompile(RT_ELEMENTS(au8Trans[0]) == 8);
2215
2216	if (pVM->pgm.s.aHCPhysDynPageMapCache[iCache] == HCPhys)
2217	{
2218	int iPage = au8Trans[pVM->pgm.s.iDynPageMapLast][iCache];
2219
2220	/* The cache can get out of sync with locked entries. (10 locked, 2 overwrites its cache position, last = 11, lookup 2 -> page 10 instead of 2) */
2221	if ((pVM->pgm.s.paDynPageMap32BitPTEsGC[iPage].u & X86_PTE_PG_MASK) == HCPhys)
2222	{
2223	void *pv = pVM->pgm.s.pbDynPageMapBaseGC + (iPage << PAGE_SHIFT);
2224	*ppv = pv;
2225	STAM_COUNTER_INC(&pVM->pgm.s.StatRCDynMapCacheHits);
2226	Log4(("PGMGCDynMapHCPage: HCPhys=%RHp pv=%p iPage=%d iCache=%d\n", HCPhys, pv, iPage, iCache));
2227	return VINF_SUCCESS;
2228	}
2229	else
2230	LogFlow(("Out of sync entry %d\n", iPage));
2231	}
2232	}
2233	AssertCompile(RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache) == 8);
2234	AssertCompile((MM_HYPER_DYNAMIC_SIZE >> PAGE_SHIFT) == 16);
2235	STAM_COUNTER_INC(&pVM->pgm.s.StatRCDynMapCacheMisses);
2236
2237	/*
2238	* Update the page tables.
2239	*/
2240	register unsigned iPage = pVM->pgm.s.iDynPageMapLast;
2241	unsigned i;
2242	for (i=0;i<(MM_HYPER_DYNAMIC_SIZE >> PAGE_SHIFT);i++)
2243	{
2244	pVM->pgm.s.iDynPageMapLast = iPage = (iPage + 1) & ((MM_HYPER_DYNAMIC_SIZE >> PAGE_SHIFT) - 1);
2245	if (!pVM->pgm.s.aLockedDynPageMapCache[iPage])
2246	break;
2247	iPage++;
2248	}
2249	AssertRelease(i != (MM_HYPER_DYNAMIC_SIZE >> PAGE_SHIFT));
2250
2251	pVM->pgm.s.aHCPhysDynPageMapCache[iPage & (RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache) - 1)] = HCPhys;
2252	pVM->pgm.s.paDynPageMap32BitPTEsGC[iPage].u = (uint32_t)HCPhys \| X86_PTE_P \| X86_PTE_A \| X86_PTE_D;
2253	pVM->pgm.s.paDynPageMapPaePTEsGC[iPage].u = HCPhys \| X86_PTE_P \| X86_PTE_A \| X86_PTE_D;
2254	pVM->pgm.s.aLockedDynPageMapCache[iPage] = 0;
2255
2256	void *pv = pVM->pgm.s.pbDynPageMapBaseGC + (iPage << PAGE_SHIFT);
2257	*ppv = pv;
2258	ASMInvalidatePage(pv);
2259	Log4(("PGMGCDynMapHCPage: HCPhys=%RHp pv=%p iPage=%d\n", HCPhys, pv, iPage));
2260	return VINF_SUCCESS;
2261	}
2262
2263
2264	/**
2265	* Temporarily lock a dynamic page to prevent it from being reused.
2266	*
2267	* @param pVM VM handle.
2268	* @param GCPage GC address of page
2269	*/
2270	VMMDECL(void) PGMDynLockHCPage(PVM pVM, RCPTRTYPE(uint8_t *) GCPage)
2271	{
2272	unsigned iPage;
2273
2274	Assert(GCPage >= pVM->pgm.s.pbDynPageMapBaseGC && GCPage < (pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE));
2275	iPage = ((uintptr_t)(GCPage - pVM->pgm.s.pbDynPageMapBaseGC)) >> PAGE_SHIFT;
2276	ASMAtomicIncU32(&pVM->pgm.s.aLockedDynPageMapCache[iPage]);
2277	Log4(("PGMDynLockHCPage %RRv iPage=%d\n", GCPage, iPage));
2278	}
2279
2280
2281	/**
2282	* Unlock a dynamic page
2283	*
2284	* @param pVM VM handle.
2285	* @param GCPage GC address of page
2286	*/
2287	VMMDECL(void) PGMDynUnlockHCPage(PVM pVM, RCPTRTYPE(uint8_t *) GCPage)
2288	{
2289	unsigned iPage;
2290
2291	AssertCompile(RT_ELEMENTS(pVM->pgm.s.aLockedDynPageMapCache) == 2* RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache));
2292	AssertCompileMemberSize(VM, pgm.s.aLockedDynPageMapCache, sizeof(uint32_t) * (MM_HYPER_DYNAMIC_SIZE >> (PAGE_SHIFT)));
2293
2294	Assert(GCPage >= pVM->pgm.s.pbDynPageMapBaseGC && GCPage < (pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE));
2295	iPage = ((uintptr_t)(GCPage - pVM->pgm.s.pbDynPageMapBaseGC)) >> PAGE_SHIFT;
2296	Assert(pVM->pgm.s.aLockedDynPageMapCache[iPage]);
2297	ASMAtomicDecU32(&pVM->pgm.s.aLockedDynPageMapCache[iPage]);
2298	Log4(("PGMDynUnlockHCPage %RRv iPage=%d\n", GCPage, iPage));
2299	}
2300
2301
2302	# ifdef VBOX_STRICT
2303	/**
2304	* Check for lock leaks.
2305	*
2306	* @param pVM VM handle.
2307	*/
2308	VMMDECL(void) PGMDynCheckLocks(PVM pVM)
2309	{
2310	for (unsigned i=0;i<RT_ELEMENTS(pVM->pgm.s.aLockedDynPageMapCache);i++)
2311	Assert(!pVM->pgm.s.aLockedDynPageMapCache[i]);
2312	}
2313	# endif /* VBOX_STRICT */
2314
2315	# endif /* IN_RC */
2316	#endif /* IN_RC \|\| VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
2317
2318	#if !defined(IN_R0) \|\| defined(LOG_ENABLED)
2319
2320	/** Format handler for PGMPAGE.
2321	* @copydoc FNRTSTRFORMATTYPE */
2322	static DECLCALLBACK(size_t) pgmFormatTypeHandlerPage(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
2323	const char pszType, void const pvValue,
2324	int cchWidth, int cchPrecision, unsigned fFlags,
2325	void *pvUser)
2326	{
2327	size_t cch;
2328	PCPGMPAGE pPage = (PCPGMPAGE)pvValue;
2329	if (VALID_PTR(pPage))
2330	{
2331	char szTmp[64+80];
2332
2333	cch = 0;
2334
2335	/* The single char state stuff. */
2336	static const char s_achPageStates[4] = { 'Z', 'A', 'W', 'S' };
2337	szTmp[cch++] = s_achPageStates[PGM_PAGE_GET_STATE(pPage)];
2338
2339	#define IS_PART_INCLUDED(lvl) ( !(fFlags & RTSTR_F_PRECISION) \|\| cchPrecision == (lvl) \|\| cchPrecision >= (lvl)+10 )
2340	if (IS_PART_INCLUDED(5))
2341	{
2342	static const char s_achHandlerStates[4] = { '-', 't', 'w', 'a' };
2343	szTmp[cch++] = s_achHandlerStates[PGM_PAGE_GET_HNDL_PHYS_STATE(pPage)];
2344	szTmp[cch++] = s_achHandlerStates[PGM_PAGE_GET_HNDL_VIRT_STATE(pPage)];
2345	}
2346
2347	/* The type. */
2348	if (IS_PART_INCLUDED(4))
2349	{
2350	szTmp[cch++] = ':';
2351	static const char s_achPageTypes[8][4] = { "INV", "RAM", "MI2", "M2A", "SHA", "ROM", "MIO", "BAD" };
2352	szTmp[cch++] = s_achPageTypes[PGM_PAGE_GET_TYPE(pPage)][0];
2353	szTmp[cch++] = s_achPageTypes[PGM_PAGE_GET_TYPE(pPage)][1];
2354	szTmp[cch++] = s_achPageTypes[PGM_PAGE_GET_TYPE(pPage)][2];
2355	}
2356
2357	/* The numbers. */
2358	if (IS_PART_INCLUDED(3))
2359	{
2360	szTmp[cch++] = ':';
2361	cch += RTStrFormatNumber(&szTmp[cch], PGM_PAGE_GET_HCPHYS(pPage), 16, 12, 0, RTSTR_F_ZEROPAD \| RTSTR_F_64BIT);
2362	}
2363
2364	if (IS_PART_INCLUDED(2))
2365	{
2366	szTmp[cch++] = ':';
2367	cch += RTStrFormatNumber(&szTmp[cch], PGM_PAGE_GET_PAGEID(pPage), 16, 7, 0, RTSTR_F_ZEROPAD \| RTSTR_F_32BIT);
2368	}
2369
2370	if (IS_PART_INCLUDED(6))
2371	{
2372	szTmp[cch++] = ':';
2373	static const char s_achRefs[4] = { '-', 'U', '!', 'L' };
2374	szTmp[cch++] = s_achRefs[PGM_PAGE_GET_TD_CREFS(pPage)];
2375	cch += RTStrFormatNumber(&szTmp[cch], PGM_PAGE_GET_TD_IDX(pPage), 16, 4, 0, RTSTR_F_ZEROPAD \| RTSTR_F_16BIT);
2376	}
2377	#undef IS_PART_INCLUDED
2378
2379	cch = pfnOutput(pvArgOutput, szTmp, cch);
2380	}
2381	else
2382	cch = pfnOutput(pvArgOutput, "<bad-pgmpage-ptr>", sizeof("<bad-pgmpage-ptr>") - 1);
2383	return cch;
2384	}
2385
2386
2387	/** Format handler for PGMRAMRANGE.
2388	* @copydoc FNRTSTRFORMATTYPE */
2389	static DECLCALLBACK(size_t) pgmFormatTypeHandlerRamRange(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
2390	const char pszType, void const pvValue,
2391	int cchWidth, int cchPrecision, unsigned fFlags,
2392	void *pvUser)
2393	{
2394	size_t cch;
2395	PGMRAMRANGE const pRam = (PGMRAMRANGE const )pvValue;
2396	if (VALID_PTR(pRam))
2397	{
2398	char szTmp[80];
2399	cch = RTStrPrintf(szTmp, sizeof(szTmp), "%RGp-%RGp", pRam->GCPhys, pRam->GCPhysLast);
2400	cch = pfnOutput(pvArgOutput, szTmp, cch);
2401	}
2402	else
2403	cch = pfnOutput(pvArgOutput, "<bad-pgmramrange-ptr>", sizeof("<bad-pgmramrange-ptr>") - 1);
2404	return cch;
2405	}
2406
2407	/** Format type andlers to be registered/deregistered. */
2408	static const struct
2409	{
2410	char szType[24];
2411	PFNRTSTRFORMATTYPE pfnHandler;
2412	} g_aPgmFormatTypes[] =
2413	{
2414	{ "pgmpage", pgmFormatTypeHandlerPage },
2415	{ "pgmramrange", pgmFormatTypeHandlerRamRange }
2416	};
2417
2418	#endif /* !IN_R0 \|\| LOG_ENABLED */
2419
2420
2421	/**
2422	* Registers the global string format types.
2423	*
2424	* This should be called at module load time or in some other manner that ensure
2425	* that it's called exactly one time.
2426	*
2427	* @returns IPRT status code on RTStrFormatTypeRegister failure.
2428	*/
2429	VMMDECL(int) PGMRegisterStringFormatTypes(void)
2430	{
2431	#if !defined(IN_R0) \|\| defined(LOG_ENABLED)
2432	int rc = VINF_SUCCESS;
2433	unsigned i;
2434	for (i = 0; RT_SUCCESS(rc) && i < RT_ELEMENTS(g_aPgmFormatTypes); i++)
2435	{
2436	rc = RTStrFormatTypeRegister(g_aPgmFormatTypes[i].szType, g_aPgmFormatTypes[i].pfnHandler, NULL);
2437	# ifdef IN_RING0
2438	if (rc == VERR_ALREADY_EXISTS)
2439	{
2440	/* in case of cleanup failure in ring-0 */
2441	RTStrFormatTypeDeregister(g_aPgmFormatTypes[i].szType);
2442	rc = RTStrFormatTypeRegister(g_aPgmFormatTypes[i].szType, g_aPgmFormatTypes[i].pfnHandler, NULL);
2443	}
2444	# endif
2445	}
2446	if (RT_FAILURE(rc))
2447	while (i-- > 0)
2448	RTStrFormatTypeDeregister(g_aPgmFormatTypes[i].szType);
2449
2450	return rc;
2451	#else
2452	return VINF_SUCCESS;
2453	#endif
2454	}
2455
2456
2457	/**
2458	* Deregisters the global string format types.
2459	*
2460	* This should be called at module unload time or in some other manner that
2461	* ensure that it's called exactly one time.
2462	*/
2463	VMMDECL(void) PGMDeregisterStringFormatTypes(void)
2464	{
2465	#if !defined(IN_R0) \|\| defined(LOG_ENABLED)
2466	for (unsigned i = 0; i < RT_ELEMENTS(g_aPgmFormatTypes); i++)
2467	RTStrFormatTypeDeregister(g_aPgmFormatTypes[i].szType);
2468	#endif
2469	}
2470
2471	#ifdef VBOX_STRICT
2472
2473	/**
2474	* Asserts that there are no mapping conflicts.
2475	*
2476	* @returns Number of conflicts.
2477	* @param pVM The VM Handle.
2478	*/
2479	VMMDECL(unsigned) PGMAssertNoMappingConflicts(PVM pVM)
2480	{
2481	unsigned cErrors = 0;
2482
2483	/* Only applies to raw mode -> 1 VPCU */
2484	Assert(pVM->cCPUs == 1);
2485	PVMCPU pVCpu = &pVM->aCpus[0];
2486
2487	/*
2488	* Check for mapping conflicts.
2489	*/
2490	for (PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
2491	pMapping;
2492	pMapping = pMapping->CTX_SUFF(pNext))
2493	{
2494	/** @todo This is slow and should be optimized, but since it's just assertions I don't care now. */
2495	for (RTGCPTR GCPtr = pMapping->GCPtr;
2496	GCPtr <= pMapping->GCPtrLast;
2497	GCPtr += PAGE_SIZE)
2498	{
2499	int rc = PGMGstGetPage(pVCpu, (RTGCPTR)GCPtr, NULL, NULL);
2500	if (rc != VERR_PAGE_TABLE_NOT_PRESENT)
2501	{
2502	AssertMsgFailed(("Conflict at %RGv with %s\n", GCPtr, R3STRING(pMapping->pszDesc)));
2503	cErrors++;
2504	break;
2505	}
2506	}
2507	}
2508
2509	return cErrors;
2510	}
2511
2512
2513	/**
2514	* Asserts that everything related to the guest CR3 is correctly shadowed.
2515	*
2516	* This will call PGMAssertNoMappingConflicts() and PGMAssertHandlerAndFlagsInSync(),
2517	* and assert the correctness of the guest CR3 mapping before asserting that the
2518	* shadow page tables is in sync with the guest page tables.
2519	*
2520	* @returns Number of conflicts.
2521	* @param pVM The VM Handle.
2522	* @param pVCpu VMCPU handle.
2523	* @param cr3 The current guest CR3 register value.
2524	* @param cr4 The current guest CR4 register value.
2525	*/
2526	VMMDECL(unsigned) PGMAssertCR3(PVM pVM, PVMCPU pVCpu, uint64_t cr3, uint64_t cr4)
2527	{
2528	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncCR3), a);
2529	unsigned cErrors = PGM_BTH_PFN(AssertCR3, pVCpu)(pVCpu, cr3, cr4, 0, ~(RTGCPTR)0);
2530	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncCR3), a);
2531	return cErrors;
2532	}
2533
2534	#endif /* VBOX_STRICT */

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAll.cpp@ 19979

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