PGMAll.cpp@ 2270

Last change on this file since 2270 was 2270, checked in by vboxsync, 18 years ago
Stricter pointer typechecking. (R0 vs R3)
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 55.5 KB

Line
1	/* $Id: PGMAll.cpp 2270 2007-04-20 12:58:15Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor - All context code.
4	*/
5
6	/*
7	* Copyright (C) 2006 InnoTek Systemberatung GmbH
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License as published by the Free Software Foundation,
13	* in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
14	* distribution. VirtualBox OSE is distributed in the hope that it will
15	* be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* If you received this file as part of a commercial VirtualBox
18	* distribution, then only the terms of your commercial VirtualBox
19	* license agreement apply instead of the previous paragraph.
20	*/
21
22	/*******************************************************************************
23	* Header Files *
24	*******************************************************************************/
25	#define LOG_GROUP LOG_GROUP_PGM
26	#include <VBox/pgm.h>
27	#include <VBox/cpum.h>
28	#include <VBox/selm.h>
29	#include <VBox/iom.h>
30	#include <VBox/sup.h>
31	#include <VBox/mm.h>
32	#include <VBox/stam.h>
33	#include <VBox/csam.h>
34	#include <VBox/patm.h>
35	#include <VBox/trpm.h>
36	#include <VBox/rem.h>
37	#include <VBox/em.h>
38	#include "PGMInternal.h"
39	#include <VBox/vm.h>
40	#include <iprt/assert.h>
41	#include <iprt/asm.h>
42	#include <iprt/string.h>
43	#include <VBox/log.h>
44	#include <VBox/param.h>
45	#include <VBox/err.h>
46
47
48	/*******************************************************************************
49	* Structures and Typedefs *
50	*******************************************************************************/
51	/**
52	* Stated structure for PGM_GST_NAME(HandlerVirtualUpdate) that's
53	* passed to PGM_GST_NAME(VirtHandlerUpdateOne) during enumeration.
54	*/
55	typedef struct PGMHVUSTATE
56	{
57	/** The VM handle. */
58	PVM pVM;
59	/** The todo flags. */
60	RTUINT fTodo;
61	/** The CR4 register value. */
62	uint32_t cr4;
63	} PGMHVUSTATE, *PPGMHVUSTATE;
64
65
66	/*******************************************************************************
67	* Internal Functions *
68	*******************************************************************************/
69	/** @def DUMP_PDE_BIG
70	* Debug routine for dumping a big PDE.
71	*/
72	#ifdef DEBUG_Sander
73	/** Debug routine for dumping a big PDE. */
74	static void pgmDumpPDEBig(const char *pszPrefix, int iPD, VBOXPDE Pde)
75	{
76	Log(("%s: BIG %d u10PageNo=%08X P=%d W=%d U=%d CACHE=%d ACC=%d DIR=%d GBL=%d\n", pszPrefix, iPD, Pde.b.u10PageNo, Pde.b.u1Present, Pde.b.u1Write, Pde.b.u1User, Pde.b.u1CacheDisable, Pde.b.u1Accessed, Pde.b.u1Dirty, Pde.b.u1Global));
77	Log(("%s: BIG %d WRT=%d AVAIL=%X RSV=%X PAT=%d\n", pszPrefix, iPD, Pde.b.u1WriteThru, Pde.b.u3Available, Pde.b.u8PageNoHigh, Pde.b.u1PAT));
78	}
79	#define DUMP_PDE_BIG(a, b, c) pgmDumpPDEBig(a, b, c)
80	#else
81	#define DUMP_PDE_BIG(a, b, c) do { } while (0)
82	#endif
83
84
85
86	#if 1///@todo ndef __AMD64__
87	/*
88	* Shadow - 32-bit mode
89	*/
90	#define PGM_SHW_TYPE PGM_TYPE_32BIT
91	#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
92	#include "PGMAllShw.h"
93
94	/* Guest - real mode */
95	#define PGM_GST_TYPE PGM_TYPE_REAL
96	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
97	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
98	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
99	#include "PGMAllGst.h"
100	#include "PGMAllBth.h"
101	#undef BTH_PGMPOOLKIND_PT_FOR_PT
102	#undef PGM_BTH_NAME
103	#undef PGM_GST_TYPE
104	#undef PGM_GST_NAME
105
106	/* Guest - protected mode */
107	#define PGM_GST_TYPE PGM_TYPE_PROT
108	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
109	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
110	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
111	#include "PGMAllGst.h"
112	#include "PGMAllBth.h"
113	#undef BTH_PGMPOOLKIND_PT_FOR_PT
114	#undef PGM_BTH_NAME
115	#undef PGM_GST_TYPE
116	#undef PGM_GST_NAME
117
118	/* Guest - 32-bit mode */
119	#define PGM_GST_TYPE PGM_TYPE_32BIT
120	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
121	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
122	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
123	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
124	#include "PGMAllGst.h"
125	#include "PGMAllBth.h"
126	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
127	#undef BTH_PGMPOOLKIND_PT_FOR_PT
128	#undef PGM_BTH_NAME
129	#undef PGM_GST_TYPE
130	#undef PGM_GST_NAME
131
132	#undef PGM_SHW_TYPE
133	#undef PGM_SHW_NAME
134	#endif /* !__AMD64__ */
135
136
137	/*
138	* Shadow - PAE mode
139	*/
140	#define PGM_SHW_TYPE PGM_TYPE_PAE
141	#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
142	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
143	#include "PGMAllShw.h"
144
145	/* Guest - real mode */
146	#define PGM_GST_TYPE PGM_TYPE_REAL
147	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
148	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
149	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
150	#include "PGMAllBth.h"
151	#undef BTH_PGMPOOLKIND_PT_FOR_PT
152	#undef PGM_BTH_NAME
153	#undef PGM_GST_TYPE
154	#undef PGM_GST_NAME
155
156	/* Guest - protected mode */
157	#define PGM_GST_TYPE PGM_TYPE_PROT
158	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
159	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
160	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
161	#include "PGMAllBth.h"
162	#undef BTH_PGMPOOLKIND_PT_FOR_PT
163	#undef PGM_BTH_NAME
164	#undef PGM_GST_TYPE
165	#undef PGM_GST_NAME
166
167	/* Guest - 32-bit mode */
168	#define PGM_GST_TYPE PGM_TYPE_32BIT
169	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
170	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
171	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
172	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
173	#include "PGMAllBth.h"
174	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
175	#undef BTH_PGMPOOLKIND_PT_FOR_PT
176	#undef PGM_BTH_NAME
177	#undef PGM_GST_TYPE
178	#undef PGM_GST_NAME
179
180
181	/* Guest - PAE mode */
182	#define PGM_GST_TYPE PGM_TYPE_PAE
183	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
184	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
185	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
186	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
187	#include "PGMAllGst.h"
188	#include "PGMAllBth.h"
189	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
190	#undef BTH_PGMPOOLKIND_PT_FOR_PT
191	#undef PGM_BTH_NAME
192	#undef PGM_GST_TYPE
193	#undef PGM_GST_NAME
194
195	#undef PGM_SHW_TYPE
196	#undef PGM_SHW_NAME
197
198
199	/*
200	* Shadow - AMD64 mode
201	*/
202	#define PGM_SHW_TYPE PGM_TYPE_AMD64
203	#define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
204	#include "PGMAllShw.h"
205
206	/* Guest - real mode */
207	#define PGM_GST_TYPE PGM_TYPE_REAL
208	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
209	#define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_REAL(name)
210	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
211	#include "PGMAllBth.h"
212	#undef BTH_PGMPOOLKIND_PT_FOR_PT
213	#undef PGM_BTH_NAME
214	#undef PGM_GST_NAME
215	#undef PGM_GST_TYPE
216
217	/* Guest - protected mode */
218	#define PGM_GST_TYPE PGM_TYPE_PROT
219	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
220	#define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_PROT(name)
221	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
222	#include "PGMAllBth.h"
223	#undef BTH_PGMPOOLKIND_PT_FOR_PT
224	#undef PGM_BTH_NAME
225	#undef PGM_GST_TYPE
226	#undef PGM_GST_NAME
227
228	/* Guest - AMD64 mode */
229	#define PGM_GST_TYPE PGM_TYPE_AMD64
230	#define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
231	#define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
232	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
233	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
234	#include "PGMAllGst.h"
235	#include "PGMAllBth.h"
236	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
237	#undef BTH_PGMPOOLKIND_PT_FOR_PT
238	#undef PGM_BTH_NAME
239	#undef PGM_GST_TYPE
240	#undef PGM_GST_NAME
241
242	#undef PGM_SHW_TYPE
243	#undef PGM_SHW_NAME
244
245
246
247	/**
248	* #PF Handler.
249	*
250	* @returns VBox status code (appropriate for trap handling and GC return).
251	* @param pVM VM Handle.
252	* @param uErr The trap error code.
253	* @param pRegFrame Trap register frame.
254	* @param pvFault The fault address.
255	*/
256	PGMDECL(int) PGMTrap0eHandler(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
257	{
258	LogFlow(("PGMTrap0eHandler: uErr=%#x pvFault=%VGv eip=%VGv\n", uErr, pvFault, pRegFrame->eip));
259	STAM_PROFILE_START(&pVM->pgm.s.StatGCTrap0e, a);
260	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = NULL; } );
261
262
263	#ifdef VBOX_WITH_STATISTICS
264	/*
265	* Error code stats.
266	*/
267	if (uErr & X86_TRAP_PF_US)
268	{
269	if (!(uErr & X86_TRAP_PF_P))
270	{
271	if (uErr & X86_TRAP_PF_RW)
272	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eUSNotPresentWrite);
273	else
274	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eUSNotPresentRead);
275	}
276	else if (uErr & X86_TRAP_PF_RW)
277	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eUSWrite);
278	else if (uErr & X86_TRAP_PF_RSVD)
279	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eUSReserved);
280	else
281	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eUSRead);
282	}
283	else
284	{ //supervisor
285	if (!(uErr & X86_TRAP_PF_P))
286	{
287	if (uErr & X86_TRAP_PF_RW)
288	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eSVNotPresentWrite);
289	else
290	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eSVNotPresentRead);
291	}
292	else if (uErr & X86_TRAP_PF_RW)
293	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eSVWrite);
294	else if (uErr & X86_TRAP_PF_RSVD)
295	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eSVReserved);
296	}
297	#endif
298
299	/*
300	* Call the worker.
301	*/
302	int rc = PGM_BTH_PFN(Trap0eHandler, pVM)(pVM, uErr, pRegFrame, pvFault);
303	if (rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
304	rc = VINF_SUCCESS;
305	STAM_STATS({ if (!pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution))
306	pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eMisc; });
307	STAM_PROFILE_STOP_EX(&pVM->pgm.s.StatGCTrap0e, pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution), a);
308	return rc;
309	}
310
311
312	/**
313	* Prefetch a page
314	*
315	* Typically used to sync commonly used pages before entering raw mode
316	* after a CR3 reload.
317	*
318	* @returns VBox status code suitable for scheduling.
319	* @retval VINF_SUCCESS on success.
320	* @retval VINF_PGM_SYNC_CR3 if we're out of shadow pages or something like that.
321	* @param pVM VM handle.
322	* @param GCPtrPage Page to invalidate.
323	*/
324	PGMDECL(int) PGMPrefetchPage(PVM pVM, RTGCPTR GCPtrPage)
325	{
326	STAM_PROFILE_START(&pVM->pgm.s.StatHCPrefetch, a);
327	int rc = PGM_BTH_PFN(PrefetchPage, pVM)(pVM, (RTGCUINTPTR)GCPtrPage);
328	STAM_PROFILE_STOP(&pVM->pgm.s.StatHCPrefetch, a);
329	AssertMsg(rc == VINF_SUCCESS \|\| rc == VINF_PGM_SYNC_CR3 \|\| VBOX_FAILURE(rc), ("rc=%Vrc\n", rc));
330	return rc;
331	}
332
333
334	/**
335	* Gets the mapping corresponding to the specified address (if any).
336	*
337	* @returns Pointer to the mapping.
338	* @returns NULL if not
339	*
340	* @param pVM The virtual machine.
341	* @param GCPtr The guest context pointer.
342	*/
343	PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr)
344	{
345	PPGMMAPPING pMapping = CTXALLSUFF(pVM->pgm.s.pMappings);
346	while (pMapping)
347	{
348	if ((uintptr_t)GCPtr < (uintptr_t)pMapping->GCPtr)
349	break;
350	if ((uintptr_t)GCPtr - (uintptr_t)pMapping->GCPtr < pMapping->cb)
351	{
352	STAM_COUNTER_INC(&pVM->pgm.s.StatGCSyncPTConflict);
353	return pMapping;
354	}
355	pMapping = CTXALLSUFF(pMapping->pNext);
356	}
357	return NULL;
358	}
359
360
361	/**
362	* Verifies a range of pages for read or write access
363	*
364	* Only checks the guest's page tables
365	*
366	* @returns VBox status code.
367	* @param pVM VM handle.
368	* @param Addr Guest virtual address to check
369	* @param cbSize Access size
370	* @param fAccess Access type (r/w, user/supervisor (X86_PTE_*))
371	*/
372	PGMDECL(int) PGMIsValidAccess(PVM pVM, RTGCUINTPTR Addr, uint32_t cbSize, uint32_t fAccess)
373	{
374	/*
375	* Validate input.
376	*/
377	if (fAccess & ~(X86_PTE_US \| X86_PTE_RW))
378	{
379	AssertMsgFailed(("PGMIsValidAccess: invalid access type %08x\n", fAccess));
380	return VERR_INVALID_PARAMETER;
381	}
382
383	uint64_t fPage;
384	int rc = PGMGstGetPage(pVM, (RTGCPTR)Addr, &fPage, NULL);
385	if (VBOX_FAILURE(rc))
386	{
387	Log(("PGMIsValidAccess: access violation for %VGv rc=%d\n", Addr, rc));
388	return VINF_EM_RAW_GUEST_TRAP;
389	}
390
391	/*
392	* Check if the access would cause a page fault
393	*
394	* Note that hypervisor page directories are not present in the guest's tables, so this check
395	* is sufficient.
396	*/
397	bool fWrite = !!(fAccess & X86_PTE_RW);
398	bool fUser = !!(fAccess & X86_PTE_US);
399	if ( !(fPage & X86_PTE_P)
400	\|\| (fWrite && !(fPage & X86_PTE_RW))
401	\|\| (fUser && !(fPage & X86_PTE_US)) )
402	{
403	Log(("PGMIsValidAccess: access violation for %VGv attr %#llx vs %d:%d\n", Addr, fPage, fWrite, fUser));
404	return VINF_EM_RAW_GUEST_TRAP;
405	}
406	if ( VBOX_SUCCESS(rc)
407	&& PAGE_ADDRESS(Addr) != PAGE_ADDRESS(Addr + cbSize))
408	return PGMIsValidAccess(pVM, Addr + PAGE_SIZE, (cbSize > PAGE_SIZE) ? cbSize - PAGE_SIZE : 1, fAccess);
409	return rc;
410	}
411
412
413	/**
414	* Verifies a range of pages for read or write access
415	*
416	* Supports handling of pages marked for dirty bit tracking and CSAM
417	*
418	* @returns VBox status code.
419	* @param pVM VM handle.
420	* @param Addr Guest virtual address to check
421	* @param cbSize Access size
422	* @param fAccess Access type (r/w, user/supervisor (X86_PTE_*))
423	*/
424	PGMDECL(int) PGMVerifyAccess(PVM pVM, RTGCUINTPTR Addr, uint32_t cbSize, uint32_t fAccess)
425	{
426	/*
427	* Validate input.
428	*/
429	if (fAccess & ~(X86_PTE_US \| X86_PTE_RW))
430	{
431	AssertMsgFailed(("PGMVerifyAccess: invalid access type %08x\n", fAccess));
432	return VERR_INVALID_PARAMETER;
433	}
434
435	uint64_t fPageGst;
436	int rc = PGMGstGetPage(pVM, (RTGCPTR)Addr, &fPageGst, NULL);
437	if (VBOX_FAILURE(rc))
438	{
439	Log(("PGMVerifyAccess: access violation for %VGv rc=%d\n", Addr, rc));
440	return VINF_EM_RAW_GUEST_TRAP;
441	}
442
443	/*
444	* Check if the access would cause a page fault
445	*
446	* Note that hypervisor page directories are not present in the guest's tables, so this check
447	* is sufficient.
448	*/
449	const bool fWrite = !!(fAccess & X86_PTE_RW);
450	const bool fUser = !!(fAccess & X86_PTE_US);
451	if ( !(fPageGst & X86_PTE_P)
452	\|\| (fWrite && !(fPageGst & X86_PTE_RW))
453	\|\| (fUser && !(fPageGst & X86_PTE_US)) )
454	{
455	Log(("PGMVerifyAccess: access violation for %VGv attr %#llx vs %d:%d\n", Addr, fPageGst, fWrite, fUser));
456	return VINF_EM_RAW_GUEST_TRAP;
457	}
458
459	/*
460	* Next step is to verify if we protected this page for dirty bit tracking or for CSAM scanning
461	*/
462	rc = PGMShwGetPage(pVM, (RTGCPTR)Addr, NULL, NULL);
463	if (rc == VERR_PAGE_NOT_PRESENT)
464	{
465	/*
466	* Page is not present in our page tables.
467	* Try to sync it!
468	*/
469	Assert(X86_TRAP_PF_RW == X86_PTE_RW && X86_TRAP_PF_US == X86_PTE_US);
470	uint32_t uErr = fAccess & (X86_TRAP_PF_RW \| X86_TRAP_PF_US);
471	rc = PGM_BTH_PFN(VerifyAccessSyncPage, pVM)(pVM, Addr, fPageGst, uErr);
472	if (rc != VINF_SUCCESS)
473	return rc;
474	}
475	else if (rc == VERR_PAGE_TABLE_NOT_PRESENT)
476	{
477	/*
478	* Page table is not present; can't do much here (?)
479	* We could of course try sync the page table.... (?)
480	*/
481	return VINF_EM_RAW_EMULATE_INSTR;
482	}
483	else
484	AssertMsg(rc == VINF_SUCCESS, ("PGMShwGetPage %VGv failed with %Vrc\n", Addr, rc));
485
486	#if 0 /* def VBOX_STRICT; triggers too often now */
487	/*
488	* This check is a bit paranoid, but useful.
489	*/
490	/** @note this will assert when writing to monitored pages (a bit annoying actually) */
491	uint64_t fPageShw;
492	rc = PGMShwGetPage(pVM, (RTGCPTR)Addr, &fPageShw, NULL);
493	if ( (rc == VERR_PAGE_NOT_PRESENT \|\| VBOX_FAILURE(rc))
494	\|\| (fWrite && !(fPageShw & X86_PTE_RW))
495	\|\| (fUser && !(fPageShw & X86_PTE_US)) )
496	{
497	AssertMsgFailed(("Unexpected access violation for %VGv! rc=%Vrc write=%d user=%d\n",
498	Addr, rc, fWrite && !(fPageShw & X86_PTE_RW), fUser && !(fPageShw & X86_PTE_US)));
499	return VINF_EM_RAW_GUEST_TRAP;
500	}
501	#endif
502
503	if ( VBOX_SUCCESS(rc)
504	&& ( PAGE_ADDRESS(Addr) != PAGE_ADDRESS(Addr + cbSize - 1)
505	\|\| Addr + cbSize < Addr))
506	return PGMVerifyAccess(pVM, Addr + PAGE_SIZE, cbSize > PAGE_SIZE ? cbSize - PAGE_SIZE : 1, fAccess);
507	return rc;
508	}
509
510	#ifndef IN_GC
511	/**
512	* Emulation of the invlpg instruction (HC only actually).
513	*
514	* @returns VBox status code.
515	* @param pVM VM handle.
516	* @param GCPtrPage Page to invalidate.
517	* @remark ASSUMES the page table entry or page directory is
518	* valid. Fairly safe, but there could be edge cases!
519	* @todo Flush page or page directory only if necessary!
520	*/
521	PGMDECL(int) PGMInvalidatePage(PVM pVM, RTGCPTR GCPtrPage)
522	{
523	LogFlow(("PGMInvalidatePage: GCPtrPage=%VGv\n", GCPtrPage));
524
525	STAM_PROFILE_START(&CTXMID(pVM->pgm.s.Stat,InvalidatePage), a);
526	int rc = PGM_BTH_PFN(InvalidatePage, pVM)(pVM, GCPtrPage);
527	STAM_PROFILE_STOP(&CTXMID(pVM->pgm.s.Stat,InvalidatePage), a);
528
529	#ifndef IN_RING0
530	/*
531	* Check if we have a pending update of the CR3 monitoring.
532	*/
533	if ( VBOX_SUCCESS(rc)
534	&& (pVM->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3))
535	{
536	pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
537	Assert(!pVM->pgm.s.fMappingsFixed);
538	Assert(pVM->pgm.s.GCPhysCR3 == pVM->pgm.s.GCPhysGstCR3Monitored);
539	rc = PGM_GST_PFN(MonitorCR3, pVM)(pVM, pVM->pgm.s.GCPhysCR3);
540	}
541	#endif
542
543	#ifdef IN_RING3
544	/*
545	* Inform CSAM about the flush
546	*/
547	/** @note this is to check if monitored pages have been changed; when we implement callbacks for virtual handlers, this is no longer required. */
548	CSAMR3FlushPage(pVM, GCPtrPage);
549	#endif
550	return rc;
551	}
552	#endif
553
554
555	/**
556	* Executes an instruction using the interpreter.
557	*
558	* @returns VBox status code (appropriate for trap handling and GC return).
559	* @param pVM VM handle.
560	* @param pRegFrame Register frame.
561	* @param pvFault Fault address.
562	*/
563	PGMDECL(int) PGMInterpretInstruction(PVM pVM, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
564	{
565	#ifdef IN_RING0
566	/** @todo */
567	int rc = VINF_EM_RAW_EMULATE_INSTR;
568	#else
569	uint32_t cb;
570	int rc = EMInterpretInstruction(pVM, pRegFrame, pvFault, &cb);
571	if (rc == VERR_EM_INTERPRETER)
572	rc = VINF_EM_RAW_EMULATE_INSTR;
573	if (rc != VINF_SUCCESS)
574	Log(("PGMInterpretInstruction: returns %Rrc (pvFault=%VGv)\n", rc, pvFault));
575	#endif
576	return rc;
577	}
578
579
580	/**
581	* Gets effective page information (from the VMM page directory).
582	*
583	* @returns VBox status.
584	* @param pVM VM Handle.
585	* @param GCPtr Guest Context virtual address of the page.
586	* @param pfFlags Where to store the flags. These are X86_PTE_*.
587	* @param pHCPhys Where to store the HC physical address of the page.
588	* This is page aligned.
589	* @remark You should use PGMMapGetPage() for pages in a mapping.
590	*/
591	PGMDECL(int) PGMShwGetPage(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys)
592	{
593	return PGM_SHW_PFN(GetPage,pVM)(pVM, (RTGCUINTPTR)GCPtr, pfFlags, pHCPhys);
594	}
595
596
597	/**
598	* Sets (replaces) the page flags for a range of pages in the shadow context.
599	*
600	* @returns VBox status.
601	* @param pVM VM handle.
602	* @param GCPtr The address of the first page.
603	* @param cb The size of the range in bytes.
604	* @param fFlags Page flags X86_PTE_*, excluding the page mask of course.
605	* @remark You must use PGMMapSetPage() for pages in a mapping.
606	*/
607	PGMDECL(int) PGMShwSetPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags)
608	{
609	return PGMShwModifyPage(pVM, GCPtr, cb, fFlags, 0);
610	}
611
612
613	/**
614	* Modify page flags for a range of pages in the shadow context.
615	*
616	* The existing flags are ANDed with the fMask and ORed with the fFlags.
617	*
618	* @returns VBox status code.
619	* @param pVM VM handle.
620	* @param GCPtr Virtual address of the first page in the range.
621	* @param cb Size (in bytes) of the range to apply the modification to.
622	* @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
623	* @param fMask The AND mask - page flags X86_PTE_*.
624	* Be very CAREFUL when ~'ing constants which could be 32-bit!
625	* @remark You must use PGMMapModifyPage() for pages in a mapping.
626	*/
627	PGMDECL(int) PGMShwModifyPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
628	{
629	/*
630	* Validate input.
631	*/
632	if (fFlags & X86_PTE_PAE_PG_MASK)
633	{
634	AssertMsgFailed(("fFlags=%#llx\n", fFlags));
635	return VERR_INVALID_PARAMETER;
636	}
637	if (!cb)
638	{
639	AssertFailed();
640	return VERR_INVALID_PARAMETER;
641	}
642
643	/*
644	* Align the input.
645	*/
646	cb += (RTGCUINTPTR)GCPtr & PAGE_OFFSET_MASK;
647	cb = RT_ALIGN_Z(cb, PAGE_SIZE);
648	GCPtr = (RTGCPTR)((RTGCUINTPTR)GCPtr & PAGE_BASE_GC_MASK); /** @todo this ain't necessary, right... */
649
650	/*
651	* Call worker.
652	*/
653	return PGM_SHW_PFN(ModifyPage, pVM)(pVM, (RTGCUINTPTR)GCPtr, cb, fFlags, fMask);
654	}
655
656
657	/**
658	* Gets effective Guest OS page information.
659	*
660	* When GCPtr is in a big page, the function will return as if it was a normal
661	* 4KB page. If the need for distinguishing between big and normal page becomes
662	* necessary at a later point, a PGMGstGetPage() will be created for that
663	* purpose.
664	*
665	* @returns VBox status.
666	* @param pVM VM Handle.
667	* @param GCPtr Guest Context virtual address of the page.
668	* @param pfFlags Where to store the flags. These are X86_PTE_*, even for big pages.
669	* @param pGCPhys Where to store the GC physical address of the page.
670	* This is page aligned. The fact that the
671	*/
672	PGMDECL(int) PGMGstGetPage(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys)
673	{
674	return PGM_GST_PFN(GetPage,pVM)(pVM, (RTGCUINTPTR)GCPtr, pfFlags, pGCPhys);
675	}
676
677
678	/**
679	* Checks if the page is present.
680	*
681	* @returns true if the page is present.
682	* @returns false if the page is not present.
683	* @param pVM The VM handle.
684	* @param GCPtr Address within the page.
685	*/
686	PGMDECL(bool) PGMGstIsPagePresent(PVM pVM, RTGCPTR GCPtr)
687	{
688	int rc = PGMGstGetPage(pVM, GCPtr, NULL, NULL);
689	return VBOX_SUCCESS(rc);
690	}
691
692
693	/**
694	* Sets (replaces) the page flags for a range of pages in the guest's tables.
695	*
696	* @returns VBox status.
697	* @param pVM VM handle.
698	* @param GCPtr The address of the first page.
699	* @param cb The size of the range in bytes.
700	* @param fFlags Page flags X86_PTE_*, excluding the page mask of course.
701	*/
702	PGMDECL(int) PGMGstSetPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags)
703	{
704	return PGMGstModifyPage(pVM, GCPtr, cb, fFlags, 0);
705	}
706
707
708	/**
709	* Modify page flags for a range of pages in the guest's tables
710	*
711	* The existing flags are ANDed with the fMask and ORed with the fFlags.
712	*
713	* @returns VBox status code.
714	* @param pVM VM handle.
715	* @param GCPtr Virtual address of the first page in the range.
716	* @param cb Size (in bytes) of the range to apply the modification to.
717	* @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
718	* @param fMask The AND mask - page flags X86_PTE_*, excluding the page mask of course.
719	* Be very CAREFUL when ~'ing constants which could be 32-bit!
720	*/
721	PGMDECL(int) PGMGstModifyPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
722	{
723	STAM_PROFILE_START(&CTXMID(pVM->pgm.s.Stat,GstModifyPage), a);
724
725	/*
726	* Validate input.
727	*/
728	if (fFlags & X86_PTE_PAE_PG_MASK)
729	{
730	AssertMsgFailed(("fFlags=%#llx\n", fFlags));
731	STAM_PROFILE_STOP(&CTXMID(pVM->pgm.s.Stat,GstModifyPage), a);
732	return VERR_INVALID_PARAMETER;
733	}
734
735	if (!cb)
736	{
737	AssertFailed();
738	STAM_PROFILE_STOP(&CTXMID(pVM->pgm.s.Stat,GstModifyPage), a);
739	return VERR_INVALID_PARAMETER;
740	}
741
742	LogFlow(("PGMGstModifyPage %VGv %d bytes fFlags=%08llx fMask=%08llx\n", GCPtr, cb, fFlags, fMask));
743
744	/*
745	* Adjust input.
746	*/
747	cb += (RTGCUINTPTR)GCPtr & PAGE_OFFSET_MASK;
748	cb = RT_ALIGN_Z(cb, PAGE_SIZE);
749	GCPtr = (RTGCPTR)((RTGCUINTPTR)GCPtr & PAGE_BASE_GC_MASK);
750
751	/*
752	* Call worker.
753	*/
754	int rc = PGM_GST_PFN(ModifyPage, pVM)(pVM, (RTGCUINTPTR)GCPtr, cb, fFlags, fMask);
755
756	STAM_PROFILE_STOP(&CTXMID(pVM->pgm.s.Stat,GstModifyPage), a);
757	return rc;
758	}
759
760
761	/**
762	* Temporarily turns off the access monitoring of a page within a monitored
763	* physical write/all page access handler region.
764	*
765	* Use this when no further \#PFs are required for that page. Be aware that
766	* a page directory sync might reset the flags, and turn on access monitoring
767	* for the page.
768	*
769	* The caller must do required page table modifications.
770	*
771	* @returns VBox status code.
772	* @param pVM VM Handle
773	* @param GCPhys Start physical address earlier passed to PGMR3HandlerPhysicalRegister().
774	* @param GCPhysPage Physical address of the page to turn off access monitoring for.
775	*/
776	PGMDECL(int) PGMHandlerPhysicalPageTempOff(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage)
777	{
778	/*
779	* Validate the range.
780	*/
781	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)RTAvlroGCPhysGet(&pVM->pgm.s.CTXSUFF(pTrees)->PhysHandlers, GCPhys);
782	if (pCur)
783	{
784	if ( GCPhysPage >= pCur->Core.Key
785	&& GCPhysPage <= pCur->Core.KeyLast)
786	{
787	/*
788	* Ok, check that the type is right and then clear the flag.
789	*/
790	unsigned fFlag;
791	switch (pCur->enmType)
792	{
793	case PGMPHYSHANDLERTYPE_PHYSICAL_WRITE:
794	fFlag = MM_RAM_FLAGS_PHYSICAL_WRITE;
795	break;
796
797	case PGMPHYSHANDLERTYPE_PHYSICAL_ALL:
798	fFlag = MM_RAM_FLAGS_PHYSICAL_ALL;
799	break;
800
801	case PGMPHYSHANDLERTYPE_MMIO:
802	case PGMPHYSHANDLERTYPE_PHYSICAL:
803	AssertMsgFailed(("Cannot disable an MMIO or natural PHYSICAL access handler! enmType=%d\n", pCur->enmType));
804	return VERR_ACCESS_DENIED;
805
806	default:
807	AssertMsgFailed(("Invalid mapping type %d\n", pCur->enmType));
808	return VERR_INTERNAL_ERROR;
809	}
810
811	/** @todo add a function which does both clear and set! */
812	/* clear and set */
813	PPGMRAMRANGE pHint = NULL;
814	int rc = PGMRamFlagsClearByGCPhysWithHint(&pVM->pgm.s, GCPhysPage, fFlag, &pHint);
815	if (VBOX_SUCCESS(rc))
816	rc = PGMRamFlagsSetByGCPhysWithHint(&pVM->pgm.s, GCPhysPage, MM_RAM_FLAGS_PHYSICAL_TEMP_OFF, &pHint);
817	return rc;
818	}
819	AssertMsgFailed(("The page %#x is outside the range %#x-%#x\n",
820	GCPhysPage, pCur->Core.Key, pCur->Core.KeyLast));
821	return VERR_INVALID_PARAMETER;
822	}
823
824	AssertMsgFailed(("Specified physical handler start address %#x is invalid.\n", GCPhys));
825	return VERR_PGM_HANDLER_NOT_FOUND;
826	}
827
828
829	/**
830	* Turns access monitoring of a page within a monitored
831	* physical write/all page access handler regio back on.
832	*
833	* The caller must do required page table modifications.
834	*
835	* @returns VBox status code.
836	* @param pVM VM Handle
837	* @param GCPhys Start physical address earlier passed to PGMR3HandlerPhysicalRegister().
838	* @param GCPhysPage Physical address of the page to turn on access monitoring for.
839	*/
840	PGMDECL(int) PGMHandlerPhysicalPageReset(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage)
841	{
842	/*
843	* Validate the range.
844	*/
845	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)RTAvlroGCPhysGet(&pVM->pgm.s.CTXSUFF(pTrees)->PhysHandlers, GCPhys);
846	if (pCur)
847	{
848	if ( GCPhysPage >= pCur->Core.Key
849	&& GCPhysPage <= pCur->Core.KeyLast)
850	{
851	/*
852	* Ok, check that the type is right and then clear the flag.
853	*/
854	unsigned fFlag;
855	switch (pCur->enmType)
856	{
857	case PGMPHYSHANDLERTYPE_PHYSICAL_WRITE:
858	fFlag = MM_RAM_FLAGS_PHYSICAL_WRITE;
859	break;
860
861	case PGMPHYSHANDLERTYPE_PHYSICAL_ALL:
862	fFlag = MM_RAM_FLAGS_PHYSICAL_ALL;
863	break;
864
865	case PGMPHYSHANDLERTYPE_MMIO:
866	case PGMPHYSHANDLERTYPE_PHYSICAL:
867	AssertMsgFailed(("Cannot enable an MMIO or natural PHYSICAL access handler! enmType=%d\n", pCur->enmType));
868	return VERR_ACCESS_DENIED;
869
870	default:
871	AssertMsgFailed(("Invalid mapping type %d\n", pCur->enmType));
872	return VERR_INTERNAL_ERROR;
873	}
874
875	/** @todo add a function which does both clear and set! */
876	/* set and clear */
877	PPGMRAMRANGE pHint = NULL;
878	int rc = PGMRamFlagsSetByGCPhysWithHint(&pVM->pgm.s, GCPhysPage, fFlag, &pHint);
879	if (VBOX_SUCCESS(rc))
880	rc = PGMRamFlagsClearByGCPhysWithHint(&pVM->pgm.s, GCPhysPage, MM_RAM_FLAGS_PHYSICAL_TEMP_OFF, &pHint);
881	return rc;
882
883	}
884	AssertMsgFailed(("The page %#x is outside the range %#x-%#x\n",
885	GCPhysPage, pCur->Core.Key, pCur->Core.KeyLast));
886	return VERR_INVALID_PARAMETER;
887	}
888
889	AssertMsgFailed(("Specified physical handler start address %#x is invalid.\n", GCPhys));
890	return VERR_PGM_HANDLER_NOT_FOUND;
891	}
892
893
894	/**
895	* Checks if a physical range is handled
896	*
897	* @returns boolean
898	* @param pVM VM Handle
899	* @param GCPhys Start physical address earlier passed to PGMR3HandlerPhysicalRegister().
900	*/
901	PGMDECL(bool) PGMHandlerPhysicalIsRegistered(PVM pVM, RTGCPHYS GCPhys)
902	{
903	/*
904	* Find the handler.
905	*/
906	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)RTAvlroGCPhysGet(&pVM->pgm.s.CTXSUFF(pTrees)->PhysHandlers, GCPhys);
907	if (pCur)
908	{
909	if ( GCPhys >= pCur->Core.Key
910	&& GCPhys <= pCur->Core.KeyLast)
911	{
912	/*
913	* Validate type.
914	*/
915	switch (pCur->enmType)
916	{
917	case PGMPHYSHANDLERTYPE_PHYSICAL_WRITE:
918	case PGMPHYSHANDLERTYPE_PHYSICAL_ALL:
919	case PGMPHYSHANDLERTYPE_PHYSICAL:
920	case PGMPHYSHANDLERTYPE_MMIO:
921	return true;
922
923	default:
924	AssertMsgFailed(("Invalid type %d! Corruption!\n", pCur->enmType));
925	return false;
926	}
927	}
928	}
929
930	return false;
931	}
932
933
934	#ifdef VBOX_STRICT
935	DECLCALLBACK(int) pgmVirtHandlerDumpPhysRange(PAVLROGCPHYSNODECORE pNode, void *pvUser)
936	{
937	PPGMPHYS2VIRTHANDLER pCur = (PPGMPHYS2VIRTHANDLER)pNode;
938	PPGMVIRTHANDLER pVirt = (PPGMVIRTHANDLER)((uintptr_t)pCur + pCur->offVirtHandler);
939	Log(("PHYS2VIRT: Range %VGp-%VGp for virtual handler: %s\n", pCur->Core.Key, pCur->Core.KeyLast, pVirt->pszDesc));
940	return 0;
941	}
942
943
944	void pgmHandlerVirtualDumpPhysPages(PVM pVM)
945	{
946	RTAvlroGCPhysDoWithAll(CTXSUFF(&pVM->pgm.s.pTrees)->PhysToVirtHandlers, true, pgmVirtHandlerDumpPhysRange, 0);
947	}
948	#endif /* VBOX_STRICT */
949
950
951	/**
952	* Gets the current CR3 register value for the shadow memory context.
953	* @returns CR3 value.
954	* @param pVM The VM handle.
955	*/
956	PGMDECL(uint32_t) PGMGetHyperCR3(PVM pVM)
957	{
958	switch (pVM->pgm.s.enmShadowMode)
959	{
960	case PGMMODE_32_BIT:
961	return pVM->pgm.s.HCPhys32BitPD;
962
963	case PGMMODE_PAE:
964	case PGMMODE_PAE_NX:
965	return pVM->pgm.s.HCPhysPaePDPTR;
966
967	case PGMMODE_AMD64:
968	case PGMMODE_AMD64_NX:
969	return pVM->pgm.s.HCPhysPaePML4;
970
971	default:
972	AssertMsgFailed(("enmShadowMode=%d\n", pVM->pgm.s.enmShadowMode));
973	return ~0;
974	}
975	}
976
977
978	/**
979	* Gets the CR3 register value for the 32-Bit shadow memory context.
980	* @returns CR3 value.
981	* @param pVM The VM handle.
982	*/
983	PGMDECL(uint32_t) PGMGetHyper32BitCR3(PVM pVM)
984	{
985	return pVM->pgm.s.HCPhys32BitPD;
986	}
987
988
989	/**
990	* Gets the CR3 register value for the PAE shadow memory context.
991	* @returns CR3 value.
992	* @param pVM The VM handle.
993	*/
994	PGMDECL(uint32_t) PGMGetHyperPaeCR3(PVM pVM)
995	{
996	return pVM->pgm.s.HCPhysPaePDPTR;
997	}
998
999
1000	/**
1001	* Gets the CR3 register value for the AMD64 shadow memory context.
1002	* @returns CR3 value.
1003	* @param pVM The VM handle.
1004	*/
1005	PGMDECL(uint32_t) PGMGetHyperAmd64CR3(PVM pVM)
1006	{
1007	return pVM->pgm.s.HCPhysPaePML4;
1008	}
1009
1010
1011	/**
1012	* Gets the current CR3 register value for the HC intermediate memory context.
1013	* @returns CR3 value.
1014	* @param pVM The VM handle.
1015	*/
1016	PGMDECL(uint32_t) PGMGetInterHCCR3(PVM pVM)
1017	{
1018	switch (pVM->pgm.s.enmHostMode)
1019	{
1020	case SUPPAGINGMODE_32_BIT:
1021	case SUPPAGINGMODE_32_BIT_GLOBAL:
1022	return pVM->pgm.s.HCPhysInterPD;
1023
1024	case SUPPAGINGMODE_PAE:
1025	case SUPPAGINGMODE_PAE_GLOBAL:
1026	case SUPPAGINGMODE_PAE_NX:
1027	case SUPPAGINGMODE_PAE_GLOBAL_NX:
1028	return pVM->pgm.s.HCPhysInterPaePDPTR;
1029
1030	case SUPPAGINGMODE_AMD64:
1031	case SUPPAGINGMODE_AMD64_GLOBAL:
1032	case SUPPAGINGMODE_AMD64_NX:
1033	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1034	return pVM->pgm.s.HCPhysInterPaePDPTR;
1035
1036	default:
1037	AssertMsgFailed(("enmHostMode=%d\n", pVM->pgm.s.enmHostMode));
1038	return ~0;
1039	}
1040	}
1041
1042
1043	/**
1044	* Gets the current CR3 register value for the GC intermediate memory context.
1045	* @returns CR3 value.
1046	* @param pVM The VM handle.
1047	*/
1048	PGMDECL(uint32_t) PGMGetInterGCCR3(PVM pVM)
1049	{
1050	switch (pVM->pgm.s.enmShadowMode)
1051	{
1052	case PGMMODE_32_BIT:
1053	return pVM->pgm.s.HCPhysInterPD;
1054
1055	case PGMMODE_PAE:
1056	case PGMMODE_PAE_NX:
1057	return pVM->pgm.s.HCPhysInterPaePDPTR;
1058
1059	case PGMMODE_AMD64:
1060	case PGMMODE_AMD64_NX:
1061	return pVM->pgm.s.HCPhysInterPaePML4;
1062
1063	default:
1064	AssertMsgFailed(("enmShadowMode=%d\n", pVM->pgm.s.enmShadowMode));
1065	return ~0;
1066	}
1067	}
1068
1069
1070	/**
1071	* Gets the CR3 register value for the 32-Bit intermediate memory context.
1072	* @returns CR3 value.
1073	* @param pVM The VM handle.
1074	*/
1075	PGMDECL(uint32_t) PGMGetInter32BitCR3(PVM pVM)
1076	{
1077	return pVM->pgm.s.HCPhysInterPD;
1078	}
1079
1080
1081	/**
1082	* Gets the CR3 register value for the PAE intermediate memory context.
1083	* @returns CR3 value.
1084	* @param pVM The VM handle.
1085	*/
1086	PGMDECL(uint32_t) PGMGetInterPaeCR3(PVM pVM)
1087	{
1088	return pVM->pgm.s.HCPhysInterPaePDPTR;
1089	}
1090
1091
1092	/**
1093	* Gets the CR3 register value for the AMD64 intermediate memory context.
1094	* @returns CR3 value.
1095	* @param pVM The VM handle.
1096	*/
1097	PGMDECL(uint32_t) PGMGetInterAmd64CR3(PVM pVM)
1098	{
1099	return pVM->pgm.s.HCPhysInterPaePML4;
1100	}
1101
1102
1103	/**
1104	* Performs and schedules necessary updates following a CR3 load or reload.
1105	*
1106	* This will normally involve mapping the guest PD or nPDPTR
1107	*
1108	* @returns VBox status code.
1109	* @retval VINF_PGM_SYNC_CR3 if monitoring requires a CR3 sync. This can
1110	* safely be ignored and overridden since the FF will be set too then.
1111	* @param pVM VM handle.
1112	* @param cr3 The new cr3.
1113	* @param fGlobal Indicates whether this is a global flush or not.
1114	*/
1115	PGMDECL(int) PGMFlushTLB(PVM pVM, uint32_t cr3, bool fGlobal)
1116	{
1117	/*
1118	* When in real or protected mode there is no TLB flushing, but
1119	* we may still be called because of REM not caring/knowing this.
1120	* REM is simple and we wish to keep it that way.
1121	*/
1122	if (pVM->pgm.s.enmGuestMode <= PGMMODE_PROTECTED)
1123	return VINF_SUCCESS;
1124	LogFlow(("PGMFlushTLB: cr3=%#x OldCr3=%#x fGlobal=%d\n", cr3, pVM->pgm.s.GCPhysCR3, fGlobal));
1125	STAM_PROFILE_START(&pVM->pgm.s.StatFlushTLB, a);
1126
1127	/*
1128	* Flag the necessary updates.
1129	*/
1130	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
1131	if (fGlobal)
1132	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
1133
1134	/*
1135	* Remap the CR3 content and adjust the monitoring if CR3 was actually changed.
1136	*/
1137	int rc = VINF_SUCCESS;
1138	RTGCPHYS GCPhysCR3;
1139	if ( pVM->pgm.s.enmGuestMode == PGMMODE_PAE
1140	\|\| pVM->pgm.s.enmGuestMode == PGMMODE_PAE_NX
1141	\|\| pVM->pgm.s.enmGuestMode == PGMMODE_AMD64
1142	\|\| pVM->pgm.s.enmGuestMode == PGMMODE_AMD64_NX)
1143	GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAE_PAGE_MASK);
1144	else
1145	GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAGE_MASK);
1146	if (pVM->pgm.s.GCPhysCR3 != GCPhysCR3)
1147	{
1148	pVM->pgm.s.GCPhysCR3 = GCPhysCR3;
1149	rc = PGM_GST_PFN(MapCR3, pVM)(pVM, GCPhysCR3);
1150	if (VBOX_SUCCESS(rc) && !pVM->pgm.s.fMappingsFixed)
1151	{
1152	pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
1153	rc = PGM_GST_PFN(MonitorCR3, pVM)(pVM, GCPhysCR3);
1154	}
1155	if (fGlobal)
1156	STAM_COUNTER_INC(&pVM->pgm.s.StatFlushTLBNewCR3Global);
1157	else
1158	STAM_COUNTER_INC(&pVM->pgm.s.StatFlushTLBNewCR3);
1159	}
1160	else
1161	{
1162	/*
1163	* Check if we have a pending update of the CR3 monitoring.
1164	*/
1165	if (pVM->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
1166	{
1167	pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
1168	Assert(!pVM->pgm.s.fMappingsFixed);
1169	rc = PGM_GST_PFN(MonitorCR3, pVM)(pVM, GCPhysCR3);
1170	}
1171	if (fGlobal)
1172	STAM_COUNTER_INC(&pVM->pgm.s.StatFlushTLBSameCR3Global);
1173	else
1174	STAM_COUNTER_INC(&pVM->pgm.s.StatFlushTLBSameCR3);
1175	}
1176
1177	STAM_PROFILE_STOP(&pVM->pgm.s.StatFlushTLB, a);
1178	return rc;
1179	}
1180
1181
1182	/**
1183	* Synchronize the paging structures.
1184	*
1185	* This function is called in response to the VM_FF_PGM_SYNC_CR3 and
1186	* VM_FF_PGM_SYNC_CR3_NONGLOBAL. Those two force action flags are set
1187	* in several places, most importantly whenever the CR3 is loaded.
1188	*
1189	* @returns VBox status code.
1190	* @param pVM The virtual machine.
1191	* @param cr0 Guest context CR0 register
1192	* @param cr3 Guest context CR3 register
1193	* @param cr4 Guest context CR4 register
1194	* @param fGlobal Including global page directories or not
1195	*/
1196	PGMDECL(int) PGMSyncCR3(PVM pVM, uint32_t cr0, uint32_t cr3, uint32_t cr4, bool fGlobal)
1197	{
1198	/*
1199	* We might be called when we shouldn't.
1200	*
1201	* The mode switching will ensure that the PD is resynced
1202	* after every mode switch. So, if we find ourselves here
1203	* when in protected or real mode we can safely disable the
1204	* FF and return immediately.
1205	*/
1206	if (pVM->pgm.s.enmGuestMode <= PGMMODE_PROTECTED)
1207	{
1208	Assert((cr0 & (X86_CR0_PG \| X86_CR0_PE)) != (X86_CR0_PG \| X86_CR0_PE));
1209	VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3);
1210	VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
1211	return VINF_SUCCESS;
1212	}
1213
1214	/* If global pages are not supported, then all flushes are global */
1215	if (!(cr4 & X86_CR4_PGE))
1216	fGlobal = true;
1217	LogFlow(("PGMSyncCR3: cr0=%08x cr3=%08x cr4=%08x fGlobal=%d[%d,%d]\n", cr0, cr3, cr4, fGlobal,
1218	VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3), VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL)));
1219
1220	/*
1221	* Let the 'Bth' function do the work and we'll just keep track of the flags.
1222	*/
1223	STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat,SyncCR3), a);
1224	int rc = PGM_BTH_PFN(SyncCR3, pVM)(pVM, cr0, cr3, cr4, fGlobal);
1225	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncCR3), a);
1226	AssertMsg(rc == VINF_SUCCESS \|\| rc == VINF_PGM_SYNC_CR3 \|\| VBOX_FAILURE(rc), ("rc=%VRc\n", rc));
1227	if (rc == VINF_SUCCESS)
1228	{
1229	if (!(pVM->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS))
1230	{
1231	VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3);
1232	VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
1233	}
1234
1235	/*
1236	* Check if we have a pending update of the CR3 monitoring.
1237	*/
1238	if (pVM->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
1239	{
1240	pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
1241	Assert(!pVM->pgm.s.fMappingsFixed);
1242	Assert(pVM->pgm.s.GCPhysCR3 == pVM->pgm.s.GCPhysGstCR3Monitored);
1243	rc = PGM_GST_PFN(MonitorCR3, pVM)(pVM, pVM->pgm.s.GCPhysCR3);
1244	}
1245	}
1246
1247	/*
1248	* Now flush the CR3 (guest context).
1249	*/
1250	if (rc == VINF_SUCCESS)
1251	PGM_INVL_GUEST_TLBS();
1252	return rc;
1253	}
1254
1255
1256	/**
1257	* Called whenever CR0 or CR4 in a way which may change
1258	* the paging mode.
1259	*
1260	* @returns VBox status code fit for scheduling in GC and R0.
1261	* @retval VINF_SUCCESS if the was no change, or it was successfully dealt with.
1262	* @retval VINF_PGM_CHANGE_MODE if we're in GC or R0 and the mode changes.
1263	* @param pVM VM handle.
1264	* @param cr0 The new cr0.
1265	* @param cr4 The new cr4.
1266	* @param efer The new extended feature enable register.
1267	*/
1268	PGMDECL(int) PGMChangeMode(PVM pVM, uint32_t cr0, uint32_t cr4, uint64_t efer)
1269	{
1270	PGMMODE enmGuestMode;
1271
1272	/*
1273	* Calc the new guest mode.
1274	*/
1275	if (!(cr0 & X86_CR0_PE))
1276	enmGuestMode = PGMMODE_REAL;
1277	else if (!(cr0 & X86_CR0_PG))
1278	enmGuestMode = PGMMODE_PROTECTED;
1279	else if (!(cr4 & X86_CR4_PAE))
1280	enmGuestMode = PGMMODE_32_BIT;
1281	else if (!(efer & MSR_K6_EFER_LME))
1282	{
1283	if (!(efer & MSR_K6_EFER_NXE))
1284	enmGuestMode = PGMMODE_PAE;
1285	else
1286	enmGuestMode = PGMMODE_PAE_NX;
1287	}
1288	else
1289	{
1290	if (!(efer & MSR_K6_EFER_NXE))
1291	enmGuestMode = PGMMODE_AMD64;
1292	else
1293	enmGuestMode = PGMMODE_AMD64_NX;
1294	}
1295
1296	/*
1297	* Did it change?
1298	*/
1299	if (pVM->pgm.s.enmGuestMode == enmGuestMode)
1300	return VINF_SUCCESS;
1301	#ifdef IN_RING3
1302	return pgmR3ChangeMode(pVM, enmGuestMode);
1303	#else
1304	Log(("PGMChangeMode: returns VINF_PGM_CHANGE_MODE.\n"));
1305	return VINF_PGM_CHANGE_MODE;
1306	#endif
1307	}
1308
1309
1310	/**
1311	* Gets the current guest paging mode.
1312	*
1313	* @returns The current paging mode.
1314	* @param pVM The VM handle.
1315	*/
1316	PGMDECL(PGMMODE) PGMGetGuestMode(PVM pVM)
1317	{
1318	return pVM->pgm.s.enmGuestMode;
1319	}
1320
1321
1322	/**
1323	* Gets the current shadow paging mode.
1324	*
1325	* @returns The current paging mode.
1326	* @param pVM The VM handle.
1327	*/
1328	PGMDECL(PGMMODE) PGMGetShadowMode(PVM pVM)
1329	{
1330	return pVM->pgm.s.enmShadowMode;
1331	}
1332
1333
1334	/**
1335	* Get mode name.
1336	*
1337	* @returns read-only name string.
1338	* @param enmMode The mode which name is desired.
1339	*/
1340	PGMDECL(const char *) PGMGetModeName(PGMMODE enmMode)
1341	{
1342	switch (enmMode)
1343	{
1344	case PGMMODE_REAL: return "real";
1345	case PGMMODE_PROTECTED: return "protected";
1346	case PGMMODE_32_BIT: return "32-bit";
1347	case PGMMODE_PAE: return "PAE";
1348	case PGMMODE_PAE_NX: return "PAE+NX";
1349	case PGMMODE_AMD64: return "AMD64";
1350	case PGMMODE_AMD64_NX: return "AMD64+NX";
1351	default: return "unknown mode value";
1352	}
1353	}
1354
1355
1356	/**
1357	* Acquire the PGM lock.
1358	*
1359	* @returns VBox status code
1360	* @param pVM The VM to operate on.
1361	*/
1362	int pgmLock(PVM pVM)
1363	{
1364	int rc = PDMCritSectEnter(&pVM->pgm.s.CritSect, VERR_SEM_BUSY);
1365	#ifdef IN_GC
1366	if (rc == VERR_SEM_BUSY)
1367	rc = VMMGCCallHost(pVM, VMMCALLHOST_PGM_LOCK, 0);
1368	#elif defined(IN_RING0)
1369	if (rc == VERR_SEM_BUSY)
1370	rc = VMMR0CallHost(pVM, VMMCALLHOST_PGM_LOCK, 0);
1371	#endif
1372	AssertRC(rc);
1373	return rc;
1374	}
1375
1376
1377	/**
1378	* Release the PGM lock.
1379	*
1380	* @returns VBox status code
1381	* @param pVM The VM to operate on.
1382	*/
1383	void pgmUnlock(PVM pVM)
1384	{
1385	PDMCritSectLeave(&pVM->pgm.s.CritSect);
1386	}
1387
1388
1389	#ifdef VBOX_STRICT
1390
1391	/**
1392	* State structure used by the PGMAssertHandlerAndFlagsInSync() function
1393	* and its AVL enumerators.
1394	*/
1395	typedef struct PGMAHAFIS
1396	{
1397	/** The VM handle. */
1398	PVM pVM;
1399	/** Number of errors. */
1400	unsigned cErrors;
1401	/** The flags we've found. */
1402	unsigned fFlagsFound;
1403	/** The flags we're matching up to.
1404	* This is also on the stack as a const, thus only valid during enumeration. */
1405	unsigned fFlags;
1406	/** The current physical address. */
1407	RTGCPHYS GCPhys;
1408	} PGMAHAFIS, *PPGMAHAFIS;
1409
1410	/**
1411	* Verify virtual handler by matching physical address.
1412	*
1413	* @returns 0
1414	* @param pNode Pointer to a PGMVIRTHANDLER.
1415	* @param pvUser Pointer to user parameter.
1416	*/
1417	static DECLCALLBACK(int) pgmVirtHandlerVerifyOneByPhysAddr(PAVLROGCPTRNODECORE pNode, void *pvUser)
1418	{
1419	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)pNode;
1420	PPGMAHAFIS pState = (PPGMAHAFIS)pvUser;
1421
1422	for (unsigned iPage = 0; iPage < pCur->cPages; iPage++)
1423	{
1424	if ((pCur->aPhysToVirt[iPage].Core.Key & X86_PTE_PAE_PG_MASK) == pState->GCPhys)
1425	{
1426	switch (pCur->enmType)
1427	{
1428	case PGMVIRTHANDLERTYPE_EIP:
1429	case PGMVIRTHANDLERTYPE_NORMAL: pState->fFlagsFound \|= MM_RAM_FLAGS_VIRTUAL_HANDLER; break;
1430	case PGMVIRTHANDLERTYPE_WRITE: pState->fFlagsFound \|= MM_RAM_FLAGS_VIRTUAL_HANDLER \| MM_RAM_FLAGS_VIRTUAL_WRITE; break;
1431	case PGMVIRTHANDLERTYPE_ALL: pState->fFlagsFound \|= MM_RAM_FLAGS_VIRTUAL_HANDLER \| MM_RAM_FLAGS_VIRTUAL_ALL; break;
1432	/* hypervisor handlers need no flags and wouldn't have nowhere to put them in any case. */
1433	case PGMVIRTHANDLERTYPE_HYPERVISOR:
1434	return 0;
1435	}
1436	if ( (pState->fFlags & (MM_RAM_FLAGS_VIRTUAL_HANDLER \| MM_RAM_FLAGS_VIRTUAL_WRITE \| MM_RAM_FLAGS_VIRTUAL_ALL))
1437	== pState->fFlagsFound)
1438	break;
1439	}
1440	}
1441	return 0;
1442	}
1443
1444
1445	/**
1446	* Verify a virtual handler.
1447	*
1448	* @returns 0
1449	* @param pNode Pointer to a PGMVIRTHANDLER.
1450	* @param pvUser Pointer to user parameter.
1451	*/
1452	static DECLCALLBACK(int) pgmVirtHandlerVerifyOne(PAVLROGCPTRNODECORE pNode, void *pvUser)
1453	{
1454	PPGMVIRTHANDLER pVirt = (PPGMVIRTHANDLER)pNode;
1455	PPGMAHAFIS pState = (PPGMAHAFIS)pvUser;
1456	PVM pVM = pState->pVM;
1457
1458	if ( pVirt->aPhysToVirt[0].Core.Key != NIL_RTGCPHYS
1459	&& (pVirt->aPhysToVirt[0].Core.Key & PAGE_OFFSET_MASK) != ((RTGCUINTPTR)pVirt->GCPtr & PAGE_OFFSET_MASK))
1460	{
1461	AssertMsgFailed(("virt handler phys out has incorrect key! %VGp %VGv %s\n",
1462	pVirt->aPhysToVirt[0].Core.Key, pVirt->GCPtr, HCSTRING(pVirt->pszDesc)));
1463	pState->cErrors++;
1464	}
1465
1466	/*
1467	* Calc flags.
1468	*/
1469	unsigned fFlags;
1470	switch (pVirt->enmType)
1471	{
1472	case PGMVIRTHANDLERTYPE_EIP:
1473	case PGMVIRTHANDLERTYPE_NORMAL: fFlags = MM_RAM_FLAGS_VIRTUAL_HANDLER; break;
1474	case PGMVIRTHANDLERTYPE_WRITE: fFlags = MM_RAM_FLAGS_VIRTUAL_HANDLER \| MM_RAM_FLAGS_VIRTUAL_WRITE; break;
1475	case PGMVIRTHANDLERTYPE_ALL: fFlags = MM_RAM_FLAGS_VIRTUAL_HANDLER \| MM_RAM_FLAGS_VIRTUAL_ALL; break;
1476	/* hypervisor handlers need no flags and wouldn't have nowhere to put them in any case. */
1477	case PGMVIRTHANDLERTYPE_HYPERVISOR:
1478	return 0;
1479	default:
1480	AssertMsgFailed(("unknown enmType=%d\n", pVirt->enmType));
1481	return 0;
1482	}
1483
1484	/*
1485	* Check pages against flags.
1486	*/
1487	RTGCUINTPTR GCPtr = (RTGCUINTPTR)pVirt->GCPtr;
1488	for (unsigned iPage = 0; iPage < pVirt->cPages; iPage++, GCPtr += PAGE_SIZE)
1489	{
1490	RTGCPHYS GCPhysGst;
1491	uint64_t fGst;
1492	int rc = PGMGstGetPage(pVM, (RTGCPTR)GCPtr, &fGst, &GCPhysGst);
1493	if (rc == VERR_PAGE_NOT_PRESENT)
1494	{
1495	if (pVirt->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
1496	{
1497	AssertMsgFailed(("virt handler phys out of sync. %VGp GCPhysNew=~0 iPage=%#x %VGv %s\n",
1498	pVirt->aPhysToVirt[iPage].Core.Key, iPage, GCPtr, HCSTRING(pVirt->pszDesc)));
1499	pState->cErrors++;
1500	}
1501	continue;
1502	}
1503
1504	AssertRCReturn(rc, 0);
1505	if ((pVirt->aPhysToVirt[iPage].Core.Key & X86_PTE_PAE_PG_MASK) != GCPhysGst)
1506	{
1507	AssertMsgFailed(("virt handler phys out of sync. %VGp GCPhysGst=%VGp iPage=%#x %VGv %s\n",
1508	pVirt->aPhysToVirt[iPage].Core.Key, GCPhysGst, iPage, GCPtr, HCSTRING(pVirt->pszDesc)));
1509	pState->cErrors++;
1510	continue;
1511	}
1512
1513	RTHCPHYS HCPhys;
1514	rc = PGMRamGCPhys2HCPhysWithFlags(&pVM->pgm.s, GCPhysGst, &HCPhys);
1515	if (VBOX_FAILURE(rc))
1516	{
1517	AssertMsgFailed(("virt handler getting ram flags rc=%Vrc. GCPhysGst=%VGp iPage=%#x %VGv %s\n",
1518	rc, GCPhysGst, iPage, GCPtr, HCSTRING(pVirt->pszDesc)));
1519	pState->cErrors++;
1520	continue;
1521	}
1522
1523	if ((HCPhys & fFlags) != fFlags)
1524	{
1525	AssertMsgFailed(("virt handler flags mismatch. HCPhys=%VHp fFlags=%#x GCPhysGst=%VGp iPage=%#x %VGv %s\n",
1526	HCPhys, fFlags, GCPhysGst, iPage, GCPtr, HCSTRING(pVirt->pszDesc)));
1527	pState->cErrors++;
1528	continue;
1529	}
1530	} /* for pages in virtual mapping. */
1531
1532	return 0;
1533	}
1534
1535
1536	/**
1537	* Asserts that the handlers+guest-page-tables == ramrange-flags and
1538	* that the physical addresses associated with virtual handlers are correct.
1539	*
1540	* @returns Number of mismatches.
1541	* @param pVM The VM handle.
1542	*/
1543	PGMDECL(unsigned) PGMAssertHandlerAndFlagsInSync(PVM pVM)
1544	{
1545	PPGM pPGM = &pVM->pgm.s;
1546	PGMAHAFIS State;
1547	State.cErrors = 0;
1548	State.pVM = pVM;
1549
1550	/*
1551	* Check the RAM flags against the handlers.
1552	*/
1553	for (PPGMRAMRANGE pRam = CTXSUFF(pPGM->pRamRanges); pRam; pRam = CTXSUFF(pRam->pNext))
1554	{
1555	const unsigned cPages = pRam->cb >> PAGE_SHIFT;
1556	for (unsigned iPage = 0; iPage < cPages; iPage++)
1557	{
1558	State.GCPhys = pRam->GCPhys + (iPage << PAGE_SHIFT);
1559	const unsigned fFlags = pRam->aHCPhys[iPage]
1560	& ( MM_RAM_FLAGS_VIRTUAL_HANDLER \| MM_RAM_FLAGS_VIRTUAL_WRITE \| MM_RAM_FLAGS_VIRTUAL_ALL
1561	\| MM_RAM_FLAGS_PHYSICAL_HANDLER \| MM_RAM_FLAGS_PHYSICAL_WRITE \| MM_RAM_FLAGS_PHYSICAL_ALL \| MM_RAM_FLAGS_PHYSICAL_TEMP_OFF);
1562	if (fFlags)
1563	{
1564	State.fFlagsFound = 0; /* build flags and compare. */
1565
1566	/* physical first. (simple because of page alignment) */
1567	if ( !(fFlags & MM_RAM_FLAGS_PHYSICAL_TEMP_OFF)
1568	&& (fFlags & (MM_RAM_FLAGS_PHYSICAL_HANDLER \| MM_RAM_FLAGS_PHYSICAL_WRITE \| MM_RAM_FLAGS_PHYSICAL_ALL)))
1569	{
1570	PPGMPHYSHANDLER pPhys = (PPGMPHYSHANDLER)RTAvlroGCPhysRangeGet(&pPGM->CTXSUFF(pTrees)->PhysHandlers, State.GCPhys);
1571	if (!pPhys)
1572	{
1573	pPhys = (PPGMPHYSHANDLER)RTAvlroGCPhysGetBestFit(&pPGM->CTXSUFF(pTrees)->PhysHandlers, State.GCPhys, true);
1574	if ( pPhys
1575	&& pPhys->Core.Key > (State.GCPhys + PAGE_SIZE - 1))
1576	pPhys = NULL;
1577	Assert(!pPhys \|\| pPhys->Core.Key >= State.GCPhys);
1578	}
1579	if (pPhys)
1580	{
1581	switch (pPhys->enmType)
1582	{
1583	case PGMPHYSHANDLERTYPE_PHYSICAL: State.fFlagsFound \|= MM_RAM_FLAGS_PHYSICAL_HANDLER; break;
1584	case PGMPHYSHANDLERTYPE_PHYSICAL_WRITE: State.fFlagsFound \|= MM_RAM_FLAGS_PHYSICAL_HANDLER \| MM_RAM_FLAGS_PHYSICAL_WRITE; break;
1585	case PGMPHYSHANDLERTYPE_MMIO:
1586	case PGMPHYSHANDLERTYPE_PHYSICAL_ALL: State.fFlagsFound \|= MM_RAM_FLAGS_PHYSICAL_HANDLER \| MM_RAM_FLAGS_PHYSICAL_ALL; break;
1587	default: AssertMsgFailed(("Invalid type phys type %d\n", pPhys->enmType)); State.cErrors++; break;
1588	}
1589	if ( (fFlags & (MM_RAM_FLAGS_PHYSICAL_HANDLER \| MM_RAM_FLAGS_PHYSICAL_WRITE \| MM_RAM_FLAGS_PHYSICAL_ALL))
1590	!= State.fFlagsFound)
1591	{
1592	AssertMsgFailed(("ram range vs phys handler flags mismatch. GCPhys=%#x fFlags=%#x fFlagsFound=%#x %s\n",
1593	State.GCPhys, fFlags, State.fFlagsFound, pPhys->pszDesc));
1594	State.cErrors++;
1595	}
1596
1597	#ifdef IN_RING3
1598	/* validate that REM is handling it. */
1599	if (!REMR3IsPageAccessHandled(pVM, State.GCPhys))
1600	{
1601	AssertMsgFailed(("ram range vs phys handler REM mismatch. GCPhys=%#x fFlags=%#x %s\n",
1602	State.GCPhys, fFlags, pPhys->pszDesc));
1603	State.cErrors++;
1604	}
1605	#endif
1606	}
1607	else
1608	{
1609	AssertMsgFailed(("ram range vs phys handler mismatch. no handler for GCPhys=%#x\n", State.GCPhys));
1610	State.cErrors++;
1611	}
1612	}
1613
1614	/* virtual flags. */
1615	if (fFlags & (MM_RAM_FLAGS_VIRTUAL_HANDLER \| MM_RAM_FLAGS_VIRTUAL_WRITE \| MM_RAM_FLAGS_VIRTUAL_ALL))
1616	{
1617	State.fFlags = fFlags;
1618	RTAvlroGCPtrDoWithAll(CTXSUFF(&pVM->pgm.s.pTrees)->VirtHandlers, true, pgmVirtHandlerVerifyOneByPhysAddr, &State);
1619	if ( (fFlags & (MM_RAM_FLAGS_VIRTUAL_HANDLER \| MM_RAM_FLAGS_VIRTUAL_WRITE \| MM_RAM_FLAGS_VIRTUAL_ALL))
1620	!= State.fFlagsFound)
1621	{
1622	AssertMsgFailed(("ram range vs virt handler flags mismatch. GCPhys=%#x fFlags=%#x fFlagsFound=%#x\n",
1623	State.GCPhys, fFlags, State.fFlagsFound));
1624	State.cErrors++;
1625	}
1626
1627	}
1628	}
1629	} /* foreach page in ram range. */
1630	} /* foreach ram range. */
1631
1632	/*
1633	* Check that the physical addresses of the virtual handlers matches up.
1634	*/
1635	RTAvlroGCPtrDoWithAll(CTXSUFF(&pVM->pgm.s.pTrees)->VirtHandlers, true, pgmVirtHandlerVerifyOne, &State);
1636
1637	return State.cErrors;
1638	}
1639
1640
1641	/**
1642	* Asserts that there are no mapping conflicts.
1643	*
1644	* @returns Number of conflicts.
1645	* @param pVM The VM Handle.
1646	*/
1647	PGMDECL(unsigned) PGMAssertNoMappingConflicts(PVM pVM)
1648	{
1649	unsigned cErrors = 0;
1650
1651	/*
1652	* Check for mapping conflicts.
1653	*/
1654	for (PPGMMAPPING pMapping = CTXALLSUFF(pVM->pgm.s.pMappings);
1655	pMapping;
1656	pMapping = CTXALLSUFF(pMapping->pNext))
1657	{
1658	/** @todo This is slow and should be optimized, but since it's just assertions I don't care now. */
1659	for (RTGCUINTPTR GCPtr = (RTGCUINTPTR)pMapping->GCPtr;
1660	GCPtr <= (RTGCUINTPTR)pMapping->GCPtrLast;
1661	GCPtr += PAGE_SIZE)
1662	{
1663	int rc = PGMGstGetPage(pVM, (RTGCPTR)GCPtr, NULL, NULL);
1664	if (rc != VERR_PAGE_TABLE_NOT_PRESENT)
1665	{
1666	AssertMsgFailed(("Conflict at %VGv with %s\n", GCPtr, HCSTRING(pMapping->pszDesc)));
1667	cErrors++;
1668	break;
1669	}
1670	}
1671	}
1672
1673	return cErrors;
1674	}
1675
1676
1677	/**
1678	* Asserts that everything related to the guest CR3 is correctly shadowed.
1679	*
1680	* This will call PGMAssertNoMappingConflicts() and PGMAssertHandlerAndFlagsInSync(),
1681	* and assert the correctness of the guest CR3 mapping before asserting that the
1682	* shadow page tables is in sync with the guest page tables.
1683	*
1684	* @returns Number of conflicts.
1685	* @param pVM The VM Handle.
1686	* @param cr3 The current guest CR3 register value.
1687	* @param cr4 The current guest CR4 register value.
1688	*/
1689	PGMDECL(unsigned) PGMAssertCR3(PVM pVM, uint32_t cr3, uint32_t cr4)
1690	{
1691	STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat,SyncCR3), a);
1692	unsigned cErrors = PGM_BTH_PFN(AssertCR3, pVM)(pVM, cr3, cr4, 0, ~(RTGCUINTPTR)0);
1693	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncCR3), a);
1694	return cErrors;
1695	}
1696
1697	#endif /* VBOX_STRICT */

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAll.cpp@ 2270

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