PGMAll.cpp@ 2299

Last change on this file since 2299 was 2298, checked in by vboxsync, 18 years ago
Don't update Addr unless we're going to loop.
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File size: 55.9 KB

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1	/* $Id: PGMAll.cpp 2298 2007-04-20 23:55:51Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor - All context code.
4	*/
5
6	/*
7	* Copyright (C) 2006 InnoTek Systemberatung GmbH
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License as published by the Free Software Foundation,
13	* in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
14	* distribution. VirtualBox OSE is distributed in the hope that it will
15	* be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* If you received this file as part of a commercial VirtualBox
18	* distribution, then only the terms of your commercial VirtualBox
19	* license agreement apply instead of the previous paragraph.
20	*/
21
22	/*******************************************************************************
23	* Header Files *
24	*******************************************************************************/
25	#define LOG_GROUP LOG_GROUP_PGM
26	#include <VBox/pgm.h>
27	#include <VBox/cpum.h>
28	#include <VBox/selm.h>
29	#include <VBox/iom.h>
30	#include <VBox/sup.h>
31	#include <VBox/mm.h>
32	#include <VBox/stam.h>
33	#include <VBox/csam.h>
34	#include <VBox/patm.h>
35	#include <VBox/trpm.h>
36	#include <VBox/rem.h>
37	#include <VBox/em.h>
38	#include "PGMInternal.h"
39	#include <VBox/vm.h>
40	#include <iprt/assert.h>
41	#include <iprt/asm.h>
42	#include <iprt/string.h>
43	#include <VBox/log.h>
44	#include <VBox/param.h>
45	#include <VBox/err.h>
46
47
48	/*******************************************************************************
49	* Structures and Typedefs *
50	*******************************************************************************/
51	/**
52	* Stated structure for PGM_GST_NAME(HandlerVirtualUpdate) that's
53	* passed to PGM_GST_NAME(VirtHandlerUpdateOne) during enumeration.
54	*/
55	typedef struct PGMHVUSTATE
56	{
57	/** The VM handle. */
58	PVM pVM;
59	/** The todo flags. */
60	RTUINT fTodo;
61	/** The CR4 register value. */
62	uint32_t cr4;
63	} PGMHVUSTATE, *PPGMHVUSTATE;
64
65
66	/*******************************************************************************
67	* Internal Functions *
68	*******************************************************************************/
69	/** @def DUMP_PDE_BIG
70	* Debug routine for dumping a big PDE.
71	*/
72	#ifdef DEBUG_Sander
73	/** Debug routine for dumping a big PDE. */
74	static void pgmDumpPDEBig(const char *pszPrefix, int iPD, VBOXPDE Pde)
75	{
76	Log(("%s: BIG %d u10PageNo=%08X P=%d W=%d U=%d CACHE=%d ACC=%d DIR=%d GBL=%d\n", pszPrefix, iPD, Pde.b.u10PageNo, Pde.b.u1Present, Pde.b.u1Write, Pde.b.u1User, Pde.b.u1CacheDisable, Pde.b.u1Accessed, Pde.b.u1Dirty, Pde.b.u1Global));
77	Log(("%s: BIG %d WRT=%d AVAIL=%X RSV=%X PAT=%d\n", pszPrefix, iPD, Pde.b.u1WriteThru, Pde.b.u3Available, Pde.b.u8PageNoHigh, Pde.b.u1PAT));
78	}
79	#define DUMP_PDE_BIG(a, b, c) pgmDumpPDEBig(a, b, c)
80	#else
81	#define DUMP_PDE_BIG(a, b, c) do { } while (0)
82	#endif
83
84
85
86	#if 1///@todo ndef __AMD64__
87	/*
88	* Shadow - 32-bit mode
89	*/
90	#define PGM_SHW_TYPE PGM_TYPE_32BIT
91	#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
92	#include "PGMAllShw.h"
93
94	/* Guest - real mode */
95	#define PGM_GST_TYPE PGM_TYPE_REAL
96	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
97	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
98	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
99	#include "PGMAllGst.h"
100	#include "PGMAllBth.h"
101	#undef BTH_PGMPOOLKIND_PT_FOR_PT
102	#undef PGM_BTH_NAME
103	#undef PGM_GST_TYPE
104	#undef PGM_GST_NAME
105
106	/* Guest - protected mode */
107	#define PGM_GST_TYPE PGM_TYPE_PROT
108	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
109	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
110	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
111	#include "PGMAllGst.h"
112	#include "PGMAllBth.h"
113	#undef BTH_PGMPOOLKIND_PT_FOR_PT
114	#undef PGM_BTH_NAME
115	#undef PGM_GST_TYPE
116	#undef PGM_GST_NAME
117
118	/* Guest - 32-bit mode */
119	#define PGM_GST_TYPE PGM_TYPE_32BIT
120	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
121	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
122	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
123	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
124	#include "PGMAllGst.h"
125	#include "PGMAllBth.h"
126	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
127	#undef BTH_PGMPOOLKIND_PT_FOR_PT
128	#undef PGM_BTH_NAME
129	#undef PGM_GST_TYPE
130	#undef PGM_GST_NAME
131
132	#undef PGM_SHW_TYPE
133	#undef PGM_SHW_NAME
134	#endif /* !__AMD64__ */
135
136
137	/*
138	* Shadow - PAE mode
139	*/
140	#define PGM_SHW_TYPE PGM_TYPE_PAE
141	#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
142	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
143	#include "PGMAllShw.h"
144
145	/* Guest - real mode */
146	#define PGM_GST_TYPE PGM_TYPE_REAL
147	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
148	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
149	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
150	#include "PGMAllBth.h"
151	#undef BTH_PGMPOOLKIND_PT_FOR_PT
152	#undef PGM_BTH_NAME
153	#undef PGM_GST_TYPE
154	#undef PGM_GST_NAME
155
156	/* Guest - protected mode */
157	#define PGM_GST_TYPE PGM_TYPE_PROT
158	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
159	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
160	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
161	#include "PGMAllBth.h"
162	#undef BTH_PGMPOOLKIND_PT_FOR_PT
163	#undef PGM_BTH_NAME
164	#undef PGM_GST_TYPE
165	#undef PGM_GST_NAME
166
167	/* Guest - 32-bit mode */
168	#define PGM_GST_TYPE PGM_TYPE_32BIT
169	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
170	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
171	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
172	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
173	#include "PGMAllBth.h"
174	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
175	#undef BTH_PGMPOOLKIND_PT_FOR_PT
176	#undef PGM_BTH_NAME
177	#undef PGM_GST_TYPE
178	#undef PGM_GST_NAME
179
180
181	/* Guest - PAE mode */
182	#define PGM_GST_TYPE PGM_TYPE_PAE
183	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
184	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
185	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
186	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
187	#include "PGMAllGst.h"
188	#include "PGMAllBth.h"
189	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
190	#undef BTH_PGMPOOLKIND_PT_FOR_PT
191	#undef PGM_BTH_NAME
192	#undef PGM_GST_TYPE
193	#undef PGM_GST_NAME
194
195	#undef PGM_SHW_TYPE
196	#undef PGM_SHW_NAME
197
198
199	/*
200	* Shadow - AMD64 mode
201	*/
202	#define PGM_SHW_TYPE PGM_TYPE_AMD64
203	#define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
204	#include "PGMAllShw.h"
205
206	/* Guest - real mode */
207	#define PGM_GST_TYPE PGM_TYPE_REAL
208	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
209	#define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_REAL(name)
210	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
211	#include "PGMAllBth.h"
212	#undef BTH_PGMPOOLKIND_PT_FOR_PT
213	#undef PGM_BTH_NAME
214	#undef PGM_GST_NAME
215	#undef PGM_GST_TYPE
216
217	/* Guest - protected mode */
218	#define PGM_GST_TYPE PGM_TYPE_PROT
219	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
220	#define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_PROT(name)
221	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
222	#include "PGMAllBth.h"
223	#undef BTH_PGMPOOLKIND_PT_FOR_PT
224	#undef PGM_BTH_NAME
225	#undef PGM_GST_TYPE
226	#undef PGM_GST_NAME
227
228	/* Guest - AMD64 mode */
229	#define PGM_GST_TYPE PGM_TYPE_AMD64
230	#define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
231	#define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
232	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
233	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
234	#include "PGMAllGst.h"
235	#include "PGMAllBth.h"
236	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
237	#undef BTH_PGMPOOLKIND_PT_FOR_PT
238	#undef PGM_BTH_NAME
239	#undef PGM_GST_TYPE
240	#undef PGM_GST_NAME
241
242	#undef PGM_SHW_TYPE
243	#undef PGM_SHW_NAME
244
245
246
247	/**
248	* #PF Handler.
249	*
250	* @returns VBox status code (appropriate for trap handling and GC return).
251	* @param pVM VM Handle.
252	* @param uErr The trap error code.
253	* @param pRegFrame Trap register frame.
254	* @param pvFault The fault address.
255	*/
256	PGMDECL(int) PGMTrap0eHandler(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
257	{
258	LogFlow(("PGMTrap0eHandler: uErr=%#x pvFault=%VGv eip=%VGv\n", uErr, pvFault, pRegFrame->eip));
259	STAM_PROFILE_START(&pVM->pgm.s.StatGCTrap0e, a);
260	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = NULL; } );
261
262
263	#ifdef VBOX_WITH_STATISTICS
264	/*
265	* Error code stats.
266	*/
267	if (uErr & X86_TRAP_PF_US)
268	{
269	if (!(uErr & X86_TRAP_PF_P))
270	{
271	if (uErr & X86_TRAP_PF_RW)
272	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eUSNotPresentWrite);
273	else
274	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eUSNotPresentRead);
275	}
276	else if (uErr & X86_TRAP_PF_RW)
277	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eUSWrite);
278	else if (uErr & X86_TRAP_PF_RSVD)
279	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eUSReserved);
280	else
281	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eUSRead);
282	}
283	else
284	{ //supervisor
285	if (!(uErr & X86_TRAP_PF_P))
286	{
287	if (uErr & X86_TRAP_PF_RW)
288	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eSVNotPresentWrite);
289	else
290	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eSVNotPresentRead);
291	}
292	else if (uErr & X86_TRAP_PF_RW)
293	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eSVWrite);
294	else if (uErr & X86_TRAP_PF_RSVD)
295	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eSVReserved);
296	}
297	#endif
298
299	/*
300	* Call the worker.
301	*/
302	int rc = PGM_BTH_PFN(Trap0eHandler, pVM)(pVM, uErr, pRegFrame, pvFault);
303	if (rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
304	rc = VINF_SUCCESS;
305	STAM_STATS({ if (!pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution))
306	pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eMisc; });
307	STAM_PROFILE_STOP_EX(&pVM->pgm.s.StatGCTrap0e, pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution), a);
308	return rc;
309	}
310
311
312	/**
313	* Prefetch a page
314	*
315	* Typically used to sync commonly used pages before entering raw mode
316	* after a CR3 reload.
317	*
318	* @returns VBox status code suitable for scheduling.
319	* @retval VINF_SUCCESS on success.
320	* @retval VINF_PGM_SYNC_CR3 if we're out of shadow pages or something like that.
321	* @param pVM VM handle.
322	* @param GCPtrPage Page to invalidate.
323	*/
324	PGMDECL(int) PGMPrefetchPage(PVM pVM, RTGCPTR GCPtrPage)
325	{
326	STAM_PROFILE_START(&pVM->pgm.s.StatHCPrefetch, a);
327	int rc = PGM_BTH_PFN(PrefetchPage, pVM)(pVM, (RTGCUINTPTR)GCPtrPage);
328	STAM_PROFILE_STOP(&pVM->pgm.s.StatHCPrefetch, a);
329	AssertMsg(rc == VINF_SUCCESS \|\| rc == VINF_PGM_SYNC_CR3 \|\| VBOX_FAILURE(rc), ("rc=%Vrc\n", rc));
330	return rc;
331	}
332
333
334	/**
335	* Gets the mapping corresponding to the specified address (if any).
336	*
337	* @returns Pointer to the mapping.
338	* @returns NULL if not
339	*
340	* @param pVM The virtual machine.
341	* @param GCPtr The guest context pointer.
342	*/
343	PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr)
344	{
345	PPGMMAPPING pMapping = CTXALLSUFF(pVM->pgm.s.pMappings);
346	while (pMapping)
347	{
348	if ((uintptr_t)GCPtr < (uintptr_t)pMapping->GCPtr)
349	break;
350	if ((uintptr_t)GCPtr - (uintptr_t)pMapping->GCPtr < pMapping->cb)
351	{
352	STAM_COUNTER_INC(&pVM->pgm.s.StatGCSyncPTConflict);
353	return pMapping;
354	}
355	pMapping = CTXALLSUFF(pMapping->pNext);
356	}
357	return NULL;
358	}
359
360
361	/**
362	* Verifies a range of pages for read or write access
363	*
364	* Only checks the guest's page tables
365	*
366	* @returns VBox status code.
367	* @param pVM VM handle.
368	* @param Addr Guest virtual address to check
369	* @param cbSize Access size
370	* @param fAccess Access type (r/w, user/supervisor (X86_PTE_*))
371	*/
372	PGMDECL(int) PGMIsValidAccess(PVM pVM, RTGCUINTPTR Addr, uint32_t cbSize, uint32_t fAccess)
373	{
374	/*
375	* Validate input.
376	*/
377	if (fAccess & ~(X86_PTE_US \| X86_PTE_RW))
378	{
379	AssertMsgFailed(("PGMIsValidAccess: invalid access type %08x\n", fAccess));
380	return VERR_INVALID_PARAMETER;
381	}
382
383	uint64_t fPage;
384	int rc = PGMGstGetPage(pVM, (RTGCPTR)Addr, &fPage, NULL);
385	if (VBOX_FAILURE(rc))
386	{
387	Log(("PGMIsValidAccess: access violation for %VGv rc=%d\n", Addr, rc));
388	return VINF_EM_RAW_GUEST_TRAP;
389	}
390
391	/*
392	* Check if the access would cause a page fault
393	*
394	* Note that hypervisor page directories are not present in the guest's tables, so this check
395	* is sufficient.
396	*/
397	bool fWrite = !!(fAccess & X86_PTE_RW);
398	bool fUser = !!(fAccess & X86_PTE_US);
399	if ( !(fPage & X86_PTE_P)
400	\|\| (fWrite && !(fPage & X86_PTE_RW))
401	\|\| (fUser && !(fPage & X86_PTE_US)) )
402	{
403	Log(("PGMIsValidAccess: access violation for %VGv attr %#llx vs %d:%d\n", Addr, fPage, fWrite, fUser));
404	return VINF_EM_RAW_GUEST_TRAP;
405	}
406	if ( VBOX_SUCCESS(rc)
407	&& PAGE_ADDRESS(Addr) != PAGE_ADDRESS(Addr + cbSize))
408	return PGMIsValidAccess(pVM, Addr + PAGE_SIZE, (cbSize > PAGE_SIZE) ? cbSize - PAGE_SIZE : 1, fAccess);
409	return rc;
410	}
411
412
413	/**
414	* Verifies a range of pages for read or write access
415	*
416	* Supports handling of pages marked for dirty bit tracking and CSAM
417	*
418	* @returns VBox status code.
419	* @param pVM VM handle.
420	* @param Addr Guest virtual address to check
421	* @param cbSize Access size
422	* @param fAccess Access type (r/w, user/supervisor (X86_PTE_*))
423	*/
424	PGMDECL(int) PGMVerifyAccess(PVM pVM, RTGCUINTPTR Addr, uint32_t cbSize, uint32_t fAccess)
425	{
426	/*
427	* Validate input.
428	*/
429	if (fAccess & ~(X86_PTE_US \| X86_PTE_RW))
430	{
431	AssertMsgFailed(("PGMVerifyAccess: invalid access type %08x\n", fAccess));
432	return VERR_INVALID_PARAMETER;
433	}
434
435	uint64_t fPageGst;
436	int rc = PGMGstGetPage(pVM, (RTGCPTR)Addr, &fPageGst, NULL);
437	if (VBOX_FAILURE(rc))
438	{
439	Log(("PGMVerifyAccess: access violation for %VGv rc=%d\n", Addr, rc));
440	return VINF_EM_RAW_GUEST_TRAP;
441	}
442
443	/*
444	* Check if the access would cause a page fault
445	*
446	* Note that hypervisor page directories are not present in the guest's tables, so this check
447	* is sufficient.
448	*/
449	const bool fWrite = !!(fAccess & X86_PTE_RW);
450	const bool fUser = !!(fAccess & X86_PTE_US);
451	if ( !(fPageGst & X86_PTE_P)
452	\|\| (fWrite && !(fPageGst & X86_PTE_RW))
453	\|\| (fUser && !(fPageGst & X86_PTE_US)) )
454	{
455	Log(("PGMVerifyAccess: access violation for %VGv attr %#llx vs %d:%d\n", Addr, fPageGst, fWrite, fUser));
456	return VINF_EM_RAW_GUEST_TRAP;
457	}
458
459	/*
460	* Next step is to verify if we protected this page for dirty bit tracking or for CSAM scanning
461	*/
462	rc = PGMShwGetPage(pVM, (RTGCPTR)Addr, NULL, NULL);
463	if (rc == VERR_PAGE_NOT_PRESENT)
464	{
465	/*
466	* Page is not present in our page tables.
467	* Try to sync it!
468	*/
469	Assert(X86_TRAP_PF_RW == X86_PTE_RW && X86_TRAP_PF_US == X86_PTE_US);
470	uint32_t uErr = fAccess & (X86_TRAP_PF_RW \| X86_TRAP_PF_US);
471	rc = PGM_BTH_PFN(VerifyAccessSyncPage, pVM)(pVM, Addr, fPageGst, uErr);
472	if (rc != VINF_SUCCESS)
473	return rc;
474	}
475	else if (rc == VERR_PAGE_TABLE_NOT_PRESENT)
476	{
477	/*
478	* Page table is not present; can't do much here (?)
479	* We could of course try sync the page table.... (?)
480	*/
481	return VINF_EM_RAW_EMULATE_INSTR;
482	}
483	else
484	AssertMsg(rc == VINF_SUCCESS, ("PGMShwGetPage %VGv failed with %Vrc\n", Addr, rc));
485
486	#if 0 /* def VBOX_STRICT; triggers too often now */
487	/*
488	* This check is a bit paranoid, but useful.
489	*/
490	/** @note this will assert when writing to monitored pages (a bit annoying actually) */
491	uint64_t fPageShw;
492	rc = PGMShwGetPage(pVM, (RTGCPTR)Addr, &fPageShw, NULL);
493	if ( (rc == VERR_PAGE_NOT_PRESENT \|\| VBOX_FAILURE(rc))
494	\|\| (fWrite && !(fPageShw & X86_PTE_RW))
495	\|\| (fUser && !(fPageShw & X86_PTE_US)) )
496	{
497	AssertMsgFailed(("Unexpected access violation for %VGv! rc=%Vrc write=%d user=%d\n",
498	Addr, rc, fWrite && !(fPageShw & X86_PTE_RW), fUser && !(fPageShw & X86_PTE_US)));
499	return VINF_EM_RAW_GUEST_TRAP;
500	}
501	#endif
502
503	if ( VBOX_SUCCESS(rc)
504	&& ( PAGE_ADDRESS(Addr) != PAGE_ADDRESS(Addr + cbSize - 1)
505	\|\| Addr + cbSize < Addr))
506	{
507	Addr += PAGE_SIZE;
508	if (cbSize > PAGE_SIZE)
509	cbSize =- PAGE_SIZE;
510	else
511	cbSize = 0;
512
513	/* Don't recursively call PGMVerifyAccess as we might run out of stack. */
514	for (;;)
515	{
516	rc = PGMVerifyAccess(pVM, Addr, 1, fAccess);
517	if (rc != VINF_SUCCESS)
518	break;
519
520	if (cbSize <= PAGE_SIZE)
521	break;
522	cbSize =- PAGE_SIZE;
523	Addr += PAGE_SIZE;
524	}
525	}
526	return rc;
527	}
528
529
530	#ifndef IN_GC
531	/**
532	* Emulation of the invlpg instruction (HC only actually).
533	*
534	* @returns VBox status code.
535	* @param pVM VM handle.
536	* @param GCPtrPage Page to invalidate.
537	* @remark ASSUMES the page table entry or page directory is
538	* valid. Fairly safe, but there could be edge cases!
539	* @todo Flush page or page directory only if necessary!
540	*/
541	PGMDECL(int) PGMInvalidatePage(PVM pVM, RTGCPTR GCPtrPage)
542	{
543	LogFlow(("PGMInvalidatePage: GCPtrPage=%VGv\n", GCPtrPage));
544
545	STAM_PROFILE_START(&CTXMID(pVM->pgm.s.Stat,InvalidatePage), a);
546	int rc = PGM_BTH_PFN(InvalidatePage, pVM)(pVM, GCPtrPage);
547	STAM_PROFILE_STOP(&CTXMID(pVM->pgm.s.Stat,InvalidatePage), a);
548
549	#ifndef IN_RING0
550	/*
551	* Check if we have a pending update of the CR3 monitoring.
552	*/
553	if ( VBOX_SUCCESS(rc)
554	&& (pVM->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3))
555	{
556	pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
557	Assert(!pVM->pgm.s.fMappingsFixed);
558	Assert(pVM->pgm.s.GCPhysCR3 == pVM->pgm.s.GCPhysGstCR3Monitored);
559	rc = PGM_GST_PFN(MonitorCR3, pVM)(pVM, pVM->pgm.s.GCPhysCR3);
560	}
561	#endif
562
563	#ifdef IN_RING3
564	/*
565	* Inform CSAM about the flush
566	*/
567	/** @note this is to check if monitored pages have been changed; when we implement callbacks for virtual handlers, this is no longer required. */
568	CSAMR3FlushPage(pVM, GCPtrPage);
569	#endif
570	return rc;
571	}
572	#endif
573
574
575	/**
576	* Executes an instruction using the interpreter.
577	*
578	* @returns VBox status code (appropriate for trap handling and GC return).
579	* @param pVM VM handle.
580	* @param pRegFrame Register frame.
581	* @param pvFault Fault address.
582	*/
583	PGMDECL(int) PGMInterpretInstruction(PVM pVM, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
584	{
585	#ifdef IN_RING0
586	/** @todo */
587	int rc = VINF_EM_RAW_EMULATE_INSTR;
588	#else
589	uint32_t cb;
590	int rc = EMInterpretInstruction(pVM, pRegFrame, pvFault, &cb);
591	if (rc == VERR_EM_INTERPRETER)
592	rc = VINF_EM_RAW_EMULATE_INSTR;
593	if (rc != VINF_SUCCESS)
594	Log(("PGMInterpretInstruction: returns %Rrc (pvFault=%VGv)\n", rc, pvFault));
595	#endif
596	return rc;
597	}
598
599
600	/**
601	* Gets effective page information (from the VMM page directory).
602	*
603	* @returns VBox status.
604	* @param pVM VM Handle.
605	* @param GCPtr Guest Context virtual address of the page.
606	* @param pfFlags Where to store the flags. These are X86_PTE_*.
607	* @param pHCPhys Where to store the HC physical address of the page.
608	* This is page aligned.
609	* @remark You should use PGMMapGetPage() for pages in a mapping.
610	*/
611	PGMDECL(int) PGMShwGetPage(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys)
612	{
613	return PGM_SHW_PFN(GetPage,pVM)(pVM, (RTGCUINTPTR)GCPtr, pfFlags, pHCPhys);
614	}
615
616
617	/**
618	* Sets (replaces) the page flags for a range of pages in the shadow context.
619	*
620	* @returns VBox status.
621	* @param pVM VM handle.
622	* @param GCPtr The address of the first page.
623	* @param cb The size of the range in bytes.
624	* @param fFlags Page flags X86_PTE_*, excluding the page mask of course.
625	* @remark You must use PGMMapSetPage() for pages in a mapping.
626	*/
627	PGMDECL(int) PGMShwSetPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags)
628	{
629	return PGMShwModifyPage(pVM, GCPtr, cb, fFlags, 0);
630	}
631
632
633	/**
634	* Modify page flags for a range of pages in the shadow context.
635	*
636	* The existing flags are ANDed with the fMask and ORed with the fFlags.
637	*
638	* @returns VBox status code.
639	* @param pVM VM handle.
640	* @param GCPtr Virtual address of the first page in the range.
641	* @param cb Size (in bytes) of the range to apply the modification to.
642	* @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
643	* @param fMask The AND mask - page flags X86_PTE_*.
644	* Be very CAREFUL when ~'ing constants which could be 32-bit!
645	* @remark You must use PGMMapModifyPage() for pages in a mapping.
646	*/
647	PGMDECL(int) PGMShwModifyPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
648	{
649	/*
650	* Validate input.
651	*/
652	if (fFlags & X86_PTE_PAE_PG_MASK)
653	{
654	AssertMsgFailed(("fFlags=%#llx\n", fFlags));
655	return VERR_INVALID_PARAMETER;
656	}
657	if (!cb)
658	{
659	AssertFailed();
660	return VERR_INVALID_PARAMETER;
661	}
662
663	/*
664	* Align the input.
665	*/
666	cb += (RTGCUINTPTR)GCPtr & PAGE_OFFSET_MASK;
667	cb = RT_ALIGN_Z(cb, PAGE_SIZE);
668	GCPtr = (RTGCPTR)((RTGCUINTPTR)GCPtr & PAGE_BASE_GC_MASK); /** @todo this ain't necessary, right... */
669
670	/*
671	* Call worker.
672	*/
673	return PGM_SHW_PFN(ModifyPage, pVM)(pVM, (RTGCUINTPTR)GCPtr, cb, fFlags, fMask);
674	}
675
676
677	/**
678	* Gets effective Guest OS page information.
679	*
680	* When GCPtr is in a big page, the function will return as if it was a normal
681	* 4KB page. If the need for distinguishing between big and normal page becomes
682	* necessary at a later point, a PGMGstGetPage() will be created for that
683	* purpose.
684	*
685	* @returns VBox status.
686	* @param pVM VM Handle.
687	* @param GCPtr Guest Context virtual address of the page.
688	* @param pfFlags Where to store the flags. These are X86_PTE_*, even for big pages.
689	* @param pGCPhys Where to store the GC physical address of the page.
690	* This is page aligned. The fact that the
691	*/
692	PGMDECL(int) PGMGstGetPage(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys)
693	{
694	return PGM_GST_PFN(GetPage,pVM)(pVM, (RTGCUINTPTR)GCPtr, pfFlags, pGCPhys);
695	}
696
697
698	/**
699	* Checks if the page is present.
700	*
701	* @returns true if the page is present.
702	* @returns false if the page is not present.
703	* @param pVM The VM handle.
704	* @param GCPtr Address within the page.
705	*/
706	PGMDECL(bool) PGMGstIsPagePresent(PVM pVM, RTGCPTR GCPtr)
707	{
708	int rc = PGMGstGetPage(pVM, GCPtr, NULL, NULL);
709	return VBOX_SUCCESS(rc);
710	}
711
712
713	/**
714	* Sets (replaces) the page flags for a range of pages in the guest's tables.
715	*
716	* @returns VBox status.
717	* @param pVM VM handle.
718	* @param GCPtr The address of the first page.
719	* @param cb The size of the range in bytes.
720	* @param fFlags Page flags X86_PTE_*, excluding the page mask of course.
721	*/
722	PGMDECL(int) PGMGstSetPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags)
723	{
724	return PGMGstModifyPage(pVM, GCPtr, cb, fFlags, 0);
725	}
726
727
728	/**
729	* Modify page flags for a range of pages in the guest's tables
730	*
731	* The existing flags are ANDed with the fMask and ORed with the fFlags.
732	*
733	* @returns VBox status code.
734	* @param pVM VM handle.
735	* @param GCPtr Virtual address of the first page in the range.
736	* @param cb Size (in bytes) of the range to apply the modification to.
737	* @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
738	* @param fMask The AND mask - page flags X86_PTE_*, excluding the page mask of course.
739	* Be very CAREFUL when ~'ing constants which could be 32-bit!
740	*/
741	PGMDECL(int) PGMGstModifyPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
742	{
743	STAM_PROFILE_START(&CTXMID(pVM->pgm.s.Stat,GstModifyPage), a);
744
745	/*
746	* Validate input.
747	*/
748	if (fFlags & X86_PTE_PAE_PG_MASK)
749	{
750	AssertMsgFailed(("fFlags=%#llx\n", fFlags));
751	STAM_PROFILE_STOP(&CTXMID(pVM->pgm.s.Stat,GstModifyPage), a);
752	return VERR_INVALID_PARAMETER;
753	}
754
755	if (!cb)
756	{
757	AssertFailed();
758	STAM_PROFILE_STOP(&CTXMID(pVM->pgm.s.Stat,GstModifyPage), a);
759	return VERR_INVALID_PARAMETER;
760	}
761
762	LogFlow(("PGMGstModifyPage %VGv %d bytes fFlags=%08llx fMask=%08llx\n", GCPtr, cb, fFlags, fMask));
763
764	/*
765	* Adjust input.
766	*/
767	cb += (RTGCUINTPTR)GCPtr & PAGE_OFFSET_MASK;
768	cb = RT_ALIGN_Z(cb, PAGE_SIZE);
769	GCPtr = (RTGCPTR)((RTGCUINTPTR)GCPtr & PAGE_BASE_GC_MASK);
770
771	/*
772	* Call worker.
773	*/
774	int rc = PGM_GST_PFN(ModifyPage, pVM)(pVM, (RTGCUINTPTR)GCPtr, cb, fFlags, fMask);
775
776	STAM_PROFILE_STOP(&CTXMID(pVM->pgm.s.Stat,GstModifyPage), a);
777	return rc;
778	}
779
780
781	/**
782	* Temporarily turns off the access monitoring of a page within a monitored
783	* physical write/all page access handler region.
784	*
785	* Use this when no further \#PFs are required for that page. Be aware that
786	* a page directory sync might reset the flags, and turn on access monitoring
787	* for the page.
788	*
789	* The caller must do required page table modifications.
790	*
791	* @returns VBox status code.
792	* @param pVM VM Handle
793	* @param GCPhys Start physical address earlier passed to PGMR3HandlerPhysicalRegister().
794	* @param GCPhysPage Physical address of the page to turn off access monitoring for.
795	*/
796	PGMDECL(int) PGMHandlerPhysicalPageTempOff(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage)
797	{
798	/*
799	* Validate the range.
800	*/
801	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)RTAvlroGCPhysGet(&pVM->pgm.s.CTXSUFF(pTrees)->PhysHandlers, GCPhys);
802	if (pCur)
803	{
804	if ( GCPhysPage >= pCur->Core.Key
805	&& GCPhysPage <= pCur->Core.KeyLast)
806	{
807	/*
808	* Ok, check that the type is right and then clear the flag.
809	*/
810	unsigned fFlag;
811	switch (pCur->enmType)
812	{
813	case PGMPHYSHANDLERTYPE_PHYSICAL_WRITE:
814	fFlag = MM_RAM_FLAGS_PHYSICAL_WRITE;
815	break;
816
817	case PGMPHYSHANDLERTYPE_PHYSICAL_ALL:
818	fFlag = MM_RAM_FLAGS_PHYSICAL_ALL;
819	break;
820
821	case PGMPHYSHANDLERTYPE_MMIO:
822	case PGMPHYSHANDLERTYPE_PHYSICAL:
823	AssertMsgFailed(("Cannot disable an MMIO or natural PHYSICAL access handler! enmType=%d\n", pCur->enmType));
824	return VERR_ACCESS_DENIED;
825
826	default:
827	AssertMsgFailed(("Invalid mapping type %d\n", pCur->enmType));
828	return VERR_INTERNAL_ERROR;
829	}
830
831	/** @todo add a function which does both clear and set! */
832	/* clear and set */
833	PPGMRAMRANGE pHint = NULL;
834	int rc = PGMRamFlagsClearByGCPhysWithHint(&pVM->pgm.s, GCPhysPage, fFlag, &pHint);
835	if (VBOX_SUCCESS(rc))
836	rc = PGMRamFlagsSetByGCPhysWithHint(&pVM->pgm.s, GCPhysPage, MM_RAM_FLAGS_PHYSICAL_TEMP_OFF, &pHint);
837	return rc;
838	}
839	AssertMsgFailed(("The page %#x is outside the range %#x-%#x\n",
840	GCPhysPage, pCur->Core.Key, pCur->Core.KeyLast));
841	return VERR_INVALID_PARAMETER;
842	}
843
844	AssertMsgFailed(("Specified physical handler start address %#x is invalid.\n", GCPhys));
845	return VERR_PGM_HANDLER_NOT_FOUND;
846	}
847
848
849	/**
850	* Turns access monitoring of a page within a monitored
851	* physical write/all page access handler regio back on.
852	*
853	* The caller must do required page table modifications.
854	*
855	* @returns VBox status code.
856	* @param pVM VM Handle
857	* @param GCPhys Start physical address earlier passed to PGMR3HandlerPhysicalRegister().
858	* @param GCPhysPage Physical address of the page to turn on access monitoring for.
859	*/
860	PGMDECL(int) PGMHandlerPhysicalPageReset(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage)
861	{
862	/*
863	* Validate the range.
864	*/
865	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)RTAvlroGCPhysGet(&pVM->pgm.s.CTXSUFF(pTrees)->PhysHandlers, GCPhys);
866	if (pCur)
867	{
868	if ( GCPhysPage >= pCur->Core.Key
869	&& GCPhysPage <= pCur->Core.KeyLast)
870	{
871	/*
872	* Ok, check that the type is right and then clear the flag.
873	*/
874	unsigned fFlag;
875	switch (pCur->enmType)
876	{
877	case PGMPHYSHANDLERTYPE_PHYSICAL_WRITE:
878	fFlag = MM_RAM_FLAGS_PHYSICAL_WRITE;
879	break;
880
881	case PGMPHYSHANDLERTYPE_PHYSICAL_ALL:
882	fFlag = MM_RAM_FLAGS_PHYSICAL_ALL;
883	break;
884
885	case PGMPHYSHANDLERTYPE_MMIO:
886	case PGMPHYSHANDLERTYPE_PHYSICAL:
887	AssertMsgFailed(("Cannot enable an MMIO or natural PHYSICAL access handler! enmType=%d\n", pCur->enmType));
888	return VERR_ACCESS_DENIED;
889
890	default:
891	AssertMsgFailed(("Invalid mapping type %d\n", pCur->enmType));
892	return VERR_INTERNAL_ERROR;
893	}
894
895	/** @todo add a function which does both clear and set! */
896	/* set and clear */
897	PPGMRAMRANGE pHint = NULL;
898	int rc = PGMRamFlagsSetByGCPhysWithHint(&pVM->pgm.s, GCPhysPage, fFlag, &pHint);
899	if (VBOX_SUCCESS(rc))
900	rc = PGMRamFlagsClearByGCPhysWithHint(&pVM->pgm.s, GCPhysPage, MM_RAM_FLAGS_PHYSICAL_TEMP_OFF, &pHint);
901	return rc;
902
903	}
904	AssertMsgFailed(("The page %#x is outside the range %#x-%#x\n",
905	GCPhysPage, pCur->Core.Key, pCur->Core.KeyLast));
906	return VERR_INVALID_PARAMETER;
907	}
908
909	AssertMsgFailed(("Specified physical handler start address %#x is invalid.\n", GCPhys));
910	return VERR_PGM_HANDLER_NOT_FOUND;
911	}
912
913
914	/**
915	* Checks if a physical range is handled
916	*
917	* @returns boolean
918	* @param pVM VM Handle
919	* @param GCPhys Start physical address earlier passed to PGMR3HandlerPhysicalRegister().
920	*/
921	PGMDECL(bool) PGMHandlerPhysicalIsRegistered(PVM pVM, RTGCPHYS GCPhys)
922	{
923	/*
924	* Find the handler.
925	*/
926	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)RTAvlroGCPhysGet(&pVM->pgm.s.CTXSUFF(pTrees)->PhysHandlers, GCPhys);
927	if (pCur)
928	{
929	if ( GCPhys >= pCur->Core.Key
930	&& GCPhys <= pCur->Core.KeyLast)
931	{
932	/*
933	* Validate type.
934	*/
935	switch (pCur->enmType)
936	{
937	case PGMPHYSHANDLERTYPE_PHYSICAL_WRITE:
938	case PGMPHYSHANDLERTYPE_PHYSICAL_ALL:
939	case PGMPHYSHANDLERTYPE_PHYSICAL:
940	case PGMPHYSHANDLERTYPE_MMIO:
941	return true;
942
943	default:
944	AssertMsgFailed(("Invalid type %d! Corruption!\n", pCur->enmType));
945	return false;
946	}
947	}
948	}
949
950	return false;
951	}
952
953
954	#ifdef VBOX_STRICT
955	DECLCALLBACK(int) pgmVirtHandlerDumpPhysRange(PAVLROGCPHYSNODECORE pNode, void *pvUser)
956	{
957	PPGMPHYS2VIRTHANDLER pCur = (PPGMPHYS2VIRTHANDLER)pNode;
958	PPGMVIRTHANDLER pVirt = (PPGMVIRTHANDLER)((uintptr_t)pCur + pCur->offVirtHandler);
959	Log(("PHYS2VIRT: Range %VGp-%VGp for virtual handler: %s\n", pCur->Core.Key, pCur->Core.KeyLast, pVirt->pszDesc));
960	return 0;
961	}
962
963
964	void pgmHandlerVirtualDumpPhysPages(PVM pVM)
965	{
966	RTAvlroGCPhysDoWithAll(CTXSUFF(&pVM->pgm.s.pTrees)->PhysToVirtHandlers, true, pgmVirtHandlerDumpPhysRange, 0);
967	}
968	#endif /* VBOX_STRICT */
969
970
971	/**
972	* Gets the current CR3 register value for the shadow memory context.
973	* @returns CR3 value.
974	* @param pVM The VM handle.
975	*/
976	PGMDECL(uint32_t) PGMGetHyperCR3(PVM pVM)
977	{
978	switch (pVM->pgm.s.enmShadowMode)
979	{
980	case PGMMODE_32_BIT:
981	return pVM->pgm.s.HCPhys32BitPD;
982
983	case PGMMODE_PAE:
984	case PGMMODE_PAE_NX:
985	return pVM->pgm.s.HCPhysPaePDPTR;
986
987	case PGMMODE_AMD64:
988	case PGMMODE_AMD64_NX:
989	return pVM->pgm.s.HCPhysPaePML4;
990
991	default:
992	AssertMsgFailed(("enmShadowMode=%d\n", pVM->pgm.s.enmShadowMode));
993	return ~0;
994	}
995	}
996
997
998	/**
999	* Gets the CR3 register value for the 32-Bit shadow memory context.
1000	* @returns CR3 value.
1001	* @param pVM The VM handle.
1002	*/
1003	PGMDECL(uint32_t) PGMGetHyper32BitCR3(PVM pVM)
1004	{
1005	return pVM->pgm.s.HCPhys32BitPD;
1006	}
1007
1008
1009	/**
1010	* Gets the CR3 register value for the PAE shadow memory context.
1011	* @returns CR3 value.
1012	* @param pVM The VM handle.
1013	*/
1014	PGMDECL(uint32_t) PGMGetHyperPaeCR3(PVM pVM)
1015	{
1016	return pVM->pgm.s.HCPhysPaePDPTR;
1017	}
1018
1019
1020	/**
1021	* Gets the CR3 register value for the AMD64 shadow memory context.
1022	* @returns CR3 value.
1023	* @param pVM The VM handle.
1024	*/
1025	PGMDECL(uint32_t) PGMGetHyperAmd64CR3(PVM pVM)
1026	{
1027	return pVM->pgm.s.HCPhysPaePML4;
1028	}
1029
1030
1031	/**
1032	* Gets the current CR3 register value for the HC intermediate memory context.
1033	* @returns CR3 value.
1034	* @param pVM The VM handle.
1035	*/
1036	PGMDECL(uint32_t) PGMGetInterHCCR3(PVM pVM)
1037	{
1038	switch (pVM->pgm.s.enmHostMode)
1039	{
1040	case SUPPAGINGMODE_32_BIT:
1041	case SUPPAGINGMODE_32_BIT_GLOBAL:
1042	return pVM->pgm.s.HCPhysInterPD;
1043
1044	case SUPPAGINGMODE_PAE:
1045	case SUPPAGINGMODE_PAE_GLOBAL:
1046	case SUPPAGINGMODE_PAE_NX:
1047	case SUPPAGINGMODE_PAE_GLOBAL_NX:
1048	return pVM->pgm.s.HCPhysInterPaePDPTR;
1049
1050	case SUPPAGINGMODE_AMD64:
1051	case SUPPAGINGMODE_AMD64_GLOBAL:
1052	case SUPPAGINGMODE_AMD64_NX:
1053	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1054	return pVM->pgm.s.HCPhysInterPaePDPTR;
1055
1056	default:
1057	AssertMsgFailed(("enmHostMode=%d\n", pVM->pgm.s.enmHostMode));
1058	return ~0;
1059	}
1060	}
1061
1062
1063	/**
1064	* Gets the current CR3 register value for the GC intermediate memory context.
1065	* @returns CR3 value.
1066	* @param pVM The VM handle.
1067	*/
1068	PGMDECL(uint32_t) PGMGetInterGCCR3(PVM pVM)
1069	{
1070	switch (pVM->pgm.s.enmShadowMode)
1071	{
1072	case PGMMODE_32_BIT:
1073	return pVM->pgm.s.HCPhysInterPD;
1074
1075	case PGMMODE_PAE:
1076	case PGMMODE_PAE_NX:
1077	return pVM->pgm.s.HCPhysInterPaePDPTR;
1078
1079	case PGMMODE_AMD64:
1080	case PGMMODE_AMD64_NX:
1081	return pVM->pgm.s.HCPhysInterPaePML4;
1082
1083	default:
1084	AssertMsgFailed(("enmShadowMode=%d\n", pVM->pgm.s.enmShadowMode));
1085	return ~0;
1086	}
1087	}
1088
1089
1090	/**
1091	* Gets the CR3 register value for the 32-Bit intermediate memory context.
1092	* @returns CR3 value.
1093	* @param pVM The VM handle.
1094	*/
1095	PGMDECL(uint32_t) PGMGetInter32BitCR3(PVM pVM)
1096	{
1097	return pVM->pgm.s.HCPhysInterPD;
1098	}
1099
1100
1101	/**
1102	* Gets the CR3 register value for the PAE intermediate memory context.
1103	* @returns CR3 value.
1104	* @param pVM The VM handle.
1105	*/
1106	PGMDECL(uint32_t) PGMGetInterPaeCR3(PVM pVM)
1107	{
1108	return pVM->pgm.s.HCPhysInterPaePDPTR;
1109	}
1110
1111
1112	/**
1113	* Gets the CR3 register value for the AMD64 intermediate memory context.
1114	* @returns CR3 value.
1115	* @param pVM The VM handle.
1116	*/
1117	PGMDECL(uint32_t) PGMGetInterAmd64CR3(PVM pVM)
1118	{
1119	return pVM->pgm.s.HCPhysInterPaePML4;
1120	}
1121
1122
1123	/**
1124	* Performs and schedules necessary updates following a CR3 load or reload.
1125	*
1126	* This will normally involve mapping the guest PD or nPDPTR
1127	*
1128	* @returns VBox status code.
1129	* @retval VINF_PGM_SYNC_CR3 if monitoring requires a CR3 sync. This can
1130	* safely be ignored and overridden since the FF will be set too then.
1131	* @param pVM VM handle.
1132	* @param cr3 The new cr3.
1133	* @param fGlobal Indicates whether this is a global flush or not.
1134	*/
1135	PGMDECL(int) PGMFlushTLB(PVM pVM, uint32_t cr3, bool fGlobal)
1136	{
1137	/*
1138	* When in real or protected mode there is no TLB flushing, but
1139	* we may still be called because of REM not caring/knowing this.
1140	* REM is simple and we wish to keep it that way.
1141	*/
1142	if (pVM->pgm.s.enmGuestMode <= PGMMODE_PROTECTED)
1143	return VINF_SUCCESS;
1144	LogFlow(("PGMFlushTLB: cr3=%#x OldCr3=%#x fGlobal=%d\n", cr3, pVM->pgm.s.GCPhysCR3, fGlobal));
1145	STAM_PROFILE_START(&pVM->pgm.s.StatFlushTLB, a);
1146
1147	/*
1148	* Flag the necessary updates.
1149	*/
1150	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
1151	if (fGlobal)
1152	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
1153
1154	/*
1155	* Remap the CR3 content and adjust the monitoring if CR3 was actually changed.
1156	*/
1157	int rc = VINF_SUCCESS;
1158	RTGCPHYS GCPhysCR3;
1159	if ( pVM->pgm.s.enmGuestMode == PGMMODE_PAE
1160	\|\| pVM->pgm.s.enmGuestMode == PGMMODE_PAE_NX
1161	\|\| pVM->pgm.s.enmGuestMode == PGMMODE_AMD64
1162	\|\| pVM->pgm.s.enmGuestMode == PGMMODE_AMD64_NX)
1163	GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAE_PAGE_MASK);
1164	else
1165	GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAGE_MASK);
1166	if (pVM->pgm.s.GCPhysCR3 != GCPhysCR3)
1167	{
1168	pVM->pgm.s.GCPhysCR3 = GCPhysCR3;
1169	rc = PGM_GST_PFN(MapCR3, pVM)(pVM, GCPhysCR3);
1170	if (VBOX_SUCCESS(rc) && !pVM->pgm.s.fMappingsFixed)
1171	{
1172	pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
1173	rc = PGM_GST_PFN(MonitorCR3, pVM)(pVM, GCPhysCR3);
1174	}
1175	if (fGlobal)
1176	STAM_COUNTER_INC(&pVM->pgm.s.StatFlushTLBNewCR3Global);
1177	else
1178	STAM_COUNTER_INC(&pVM->pgm.s.StatFlushTLBNewCR3);
1179	}
1180	else
1181	{
1182	/*
1183	* Check if we have a pending update of the CR3 monitoring.
1184	*/
1185	if (pVM->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
1186	{
1187	pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
1188	Assert(!pVM->pgm.s.fMappingsFixed);
1189	rc = PGM_GST_PFN(MonitorCR3, pVM)(pVM, GCPhysCR3);
1190	}
1191	if (fGlobal)
1192	STAM_COUNTER_INC(&pVM->pgm.s.StatFlushTLBSameCR3Global);
1193	else
1194	STAM_COUNTER_INC(&pVM->pgm.s.StatFlushTLBSameCR3);
1195	}
1196
1197	STAM_PROFILE_STOP(&pVM->pgm.s.StatFlushTLB, a);
1198	return rc;
1199	}
1200
1201
1202	/**
1203	* Synchronize the paging structures.
1204	*
1205	* This function is called in response to the VM_FF_PGM_SYNC_CR3 and
1206	* VM_FF_PGM_SYNC_CR3_NONGLOBAL. Those two force action flags are set
1207	* in several places, most importantly whenever the CR3 is loaded.
1208	*
1209	* @returns VBox status code.
1210	* @param pVM The virtual machine.
1211	* @param cr0 Guest context CR0 register
1212	* @param cr3 Guest context CR3 register
1213	* @param cr4 Guest context CR4 register
1214	* @param fGlobal Including global page directories or not
1215	*/
1216	PGMDECL(int) PGMSyncCR3(PVM pVM, uint32_t cr0, uint32_t cr3, uint32_t cr4, bool fGlobal)
1217	{
1218	/*
1219	* We might be called when we shouldn't.
1220	*
1221	* The mode switching will ensure that the PD is resynced
1222	* after every mode switch. So, if we find ourselves here
1223	* when in protected or real mode we can safely disable the
1224	* FF and return immediately.
1225	*/
1226	if (pVM->pgm.s.enmGuestMode <= PGMMODE_PROTECTED)
1227	{
1228	Assert((cr0 & (X86_CR0_PG \| X86_CR0_PE)) != (X86_CR0_PG \| X86_CR0_PE));
1229	VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3);
1230	VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
1231	return VINF_SUCCESS;
1232	}
1233
1234	/* If global pages are not supported, then all flushes are global */
1235	if (!(cr4 & X86_CR4_PGE))
1236	fGlobal = true;
1237	LogFlow(("PGMSyncCR3: cr0=%08x cr3=%08x cr4=%08x fGlobal=%d[%d,%d]\n", cr0, cr3, cr4, fGlobal,
1238	VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3), VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL)));
1239
1240	/*
1241	* Let the 'Bth' function do the work and we'll just keep track of the flags.
1242	*/
1243	STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat,SyncCR3), a);
1244	int rc = PGM_BTH_PFN(SyncCR3, pVM)(pVM, cr0, cr3, cr4, fGlobal);
1245	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncCR3), a);
1246	AssertMsg(rc == VINF_SUCCESS \|\| rc == VINF_PGM_SYNC_CR3 \|\| VBOX_FAILURE(rc), ("rc=%VRc\n", rc));
1247	if (rc == VINF_SUCCESS)
1248	{
1249	if (!(pVM->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS))
1250	{
1251	VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3);
1252	VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
1253	}
1254
1255	/*
1256	* Check if we have a pending update of the CR3 monitoring.
1257	*/
1258	if (pVM->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
1259	{
1260	pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
1261	Assert(!pVM->pgm.s.fMappingsFixed);
1262	Assert(pVM->pgm.s.GCPhysCR3 == pVM->pgm.s.GCPhysGstCR3Monitored);
1263	rc = PGM_GST_PFN(MonitorCR3, pVM)(pVM, pVM->pgm.s.GCPhysCR3);
1264	}
1265	}
1266
1267	/*
1268	* Now flush the CR3 (guest context).
1269	*/
1270	if (rc == VINF_SUCCESS)
1271	PGM_INVL_GUEST_TLBS();
1272	return rc;
1273	}
1274
1275
1276	/**
1277	* Called whenever CR0 or CR4 in a way which may change
1278	* the paging mode.
1279	*
1280	* @returns VBox status code fit for scheduling in GC and R0.
1281	* @retval VINF_SUCCESS if the was no change, or it was successfully dealt with.
1282	* @retval VINF_PGM_CHANGE_MODE if we're in GC or R0 and the mode changes.
1283	* @param pVM VM handle.
1284	* @param cr0 The new cr0.
1285	* @param cr4 The new cr4.
1286	* @param efer The new extended feature enable register.
1287	*/
1288	PGMDECL(int) PGMChangeMode(PVM pVM, uint32_t cr0, uint32_t cr4, uint64_t efer)
1289	{
1290	PGMMODE enmGuestMode;
1291
1292	/*
1293	* Calc the new guest mode.
1294	*/
1295	if (!(cr0 & X86_CR0_PE))
1296	enmGuestMode = PGMMODE_REAL;
1297	else if (!(cr0 & X86_CR0_PG))
1298	enmGuestMode = PGMMODE_PROTECTED;
1299	else if (!(cr4 & X86_CR4_PAE))
1300	enmGuestMode = PGMMODE_32_BIT;
1301	else if (!(efer & MSR_K6_EFER_LME))
1302	{
1303	if (!(efer & MSR_K6_EFER_NXE))
1304	enmGuestMode = PGMMODE_PAE;
1305	else
1306	enmGuestMode = PGMMODE_PAE_NX;
1307	}
1308	else
1309	{
1310	if (!(efer & MSR_K6_EFER_NXE))
1311	enmGuestMode = PGMMODE_AMD64;
1312	else
1313	enmGuestMode = PGMMODE_AMD64_NX;
1314	}
1315
1316	/*
1317	* Did it change?
1318	*/
1319	if (pVM->pgm.s.enmGuestMode == enmGuestMode)
1320	return VINF_SUCCESS;
1321	#ifdef IN_RING3
1322	return pgmR3ChangeMode(pVM, enmGuestMode);
1323	#else
1324	Log(("PGMChangeMode: returns VINF_PGM_CHANGE_MODE.\n"));
1325	return VINF_PGM_CHANGE_MODE;
1326	#endif
1327	}
1328
1329
1330	/**
1331	* Gets the current guest paging mode.
1332	*
1333	* @returns The current paging mode.
1334	* @param pVM The VM handle.
1335	*/
1336	PGMDECL(PGMMODE) PGMGetGuestMode(PVM pVM)
1337	{
1338	return pVM->pgm.s.enmGuestMode;
1339	}
1340
1341
1342	/**
1343	* Gets the current shadow paging mode.
1344	*
1345	* @returns The current paging mode.
1346	* @param pVM The VM handle.
1347	*/
1348	PGMDECL(PGMMODE) PGMGetShadowMode(PVM pVM)
1349	{
1350	return pVM->pgm.s.enmShadowMode;
1351	}
1352
1353
1354	/**
1355	* Get mode name.
1356	*
1357	* @returns read-only name string.
1358	* @param enmMode The mode which name is desired.
1359	*/
1360	PGMDECL(const char *) PGMGetModeName(PGMMODE enmMode)
1361	{
1362	switch (enmMode)
1363	{
1364	case PGMMODE_REAL: return "real";
1365	case PGMMODE_PROTECTED: return "protected";
1366	case PGMMODE_32_BIT: return "32-bit";
1367	case PGMMODE_PAE: return "PAE";
1368	case PGMMODE_PAE_NX: return "PAE+NX";
1369	case PGMMODE_AMD64: return "AMD64";
1370	case PGMMODE_AMD64_NX: return "AMD64+NX";
1371	default: return "unknown mode value";
1372	}
1373	}
1374
1375
1376	/**
1377	* Acquire the PGM lock.
1378	*
1379	* @returns VBox status code
1380	* @param pVM The VM to operate on.
1381	*/
1382	int pgmLock(PVM pVM)
1383	{
1384	int rc = PDMCritSectEnter(&pVM->pgm.s.CritSect, VERR_SEM_BUSY);
1385	#ifdef IN_GC
1386	if (rc == VERR_SEM_BUSY)
1387	rc = VMMGCCallHost(pVM, VMMCALLHOST_PGM_LOCK, 0);
1388	#elif defined(IN_RING0)
1389	if (rc == VERR_SEM_BUSY)
1390	rc = VMMR0CallHost(pVM, VMMCALLHOST_PGM_LOCK, 0);
1391	#endif
1392	AssertRC(rc);
1393	return rc;
1394	}
1395
1396
1397	/**
1398	* Release the PGM lock.
1399	*
1400	* @returns VBox status code
1401	* @param pVM The VM to operate on.
1402	*/
1403	void pgmUnlock(PVM pVM)
1404	{
1405	PDMCritSectLeave(&pVM->pgm.s.CritSect);
1406	}
1407
1408
1409	#ifdef VBOX_STRICT
1410
1411	/**
1412	* State structure used by the PGMAssertHandlerAndFlagsInSync() function
1413	* and its AVL enumerators.
1414	*/
1415	typedef struct PGMAHAFIS
1416	{
1417	/** The VM handle. */
1418	PVM pVM;
1419	/** Number of errors. */
1420	unsigned cErrors;
1421	/** The flags we've found. */
1422	unsigned fFlagsFound;
1423	/** The flags we're matching up to.
1424	* This is also on the stack as a const, thus only valid during enumeration. */
1425	unsigned fFlags;
1426	/** The current physical address. */
1427	RTGCPHYS GCPhys;
1428	} PGMAHAFIS, *PPGMAHAFIS;
1429
1430	/**
1431	* Verify virtual handler by matching physical address.
1432	*
1433	* @returns 0
1434	* @param pNode Pointer to a PGMVIRTHANDLER.
1435	* @param pvUser Pointer to user parameter.
1436	*/
1437	static DECLCALLBACK(int) pgmVirtHandlerVerifyOneByPhysAddr(PAVLROGCPTRNODECORE pNode, void *pvUser)
1438	{
1439	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)pNode;
1440	PPGMAHAFIS pState = (PPGMAHAFIS)pvUser;
1441
1442	for (unsigned iPage = 0; iPage < pCur->cPages; iPage++)
1443	{
1444	if ((pCur->aPhysToVirt[iPage].Core.Key & X86_PTE_PAE_PG_MASK) == pState->GCPhys)
1445	{
1446	switch (pCur->enmType)
1447	{
1448	case PGMVIRTHANDLERTYPE_EIP:
1449	case PGMVIRTHANDLERTYPE_NORMAL: pState->fFlagsFound \|= MM_RAM_FLAGS_VIRTUAL_HANDLER; break;
1450	case PGMVIRTHANDLERTYPE_WRITE: pState->fFlagsFound \|= MM_RAM_FLAGS_VIRTUAL_HANDLER \| MM_RAM_FLAGS_VIRTUAL_WRITE; break;
1451	case PGMVIRTHANDLERTYPE_ALL: pState->fFlagsFound \|= MM_RAM_FLAGS_VIRTUAL_HANDLER \| MM_RAM_FLAGS_VIRTUAL_ALL; break;
1452	/* hypervisor handlers need no flags and wouldn't have nowhere to put them in any case. */
1453	case PGMVIRTHANDLERTYPE_HYPERVISOR:
1454	return 0;
1455	}
1456	if ( (pState->fFlags & (MM_RAM_FLAGS_VIRTUAL_HANDLER \| MM_RAM_FLAGS_VIRTUAL_WRITE \| MM_RAM_FLAGS_VIRTUAL_ALL))
1457	== pState->fFlagsFound)
1458	break;
1459	}
1460	}
1461	return 0;
1462	}
1463
1464
1465	/**
1466	* Verify a virtual handler.
1467	*
1468	* @returns 0
1469	* @param pNode Pointer to a PGMVIRTHANDLER.
1470	* @param pvUser Pointer to user parameter.
1471	*/
1472	static DECLCALLBACK(int) pgmVirtHandlerVerifyOne(PAVLROGCPTRNODECORE pNode, void *pvUser)
1473	{
1474	PPGMVIRTHANDLER pVirt = (PPGMVIRTHANDLER)pNode;
1475	PPGMAHAFIS pState = (PPGMAHAFIS)pvUser;
1476	PVM pVM = pState->pVM;
1477
1478	if ( pVirt->aPhysToVirt[0].Core.Key != NIL_RTGCPHYS
1479	&& (pVirt->aPhysToVirt[0].Core.Key & PAGE_OFFSET_MASK) != ((RTGCUINTPTR)pVirt->GCPtr & PAGE_OFFSET_MASK))
1480	{
1481	AssertMsgFailed(("virt handler phys out has incorrect key! %VGp %VGv %s\n",
1482	pVirt->aPhysToVirt[0].Core.Key, pVirt->GCPtr, HCSTRING(pVirt->pszDesc)));
1483	pState->cErrors++;
1484	}
1485
1486	/*
1487	* Calc flags.
1488	*/
1489	unsigned fFlags;
1490	switch (pVirt->enmType)
1491	{
1492	case PGMVIRTHANDLERTYPE_EIP:
1493	case PGMVIRTHANDLERTYPE_NORMAL: fFlags = MM_RAM_FLAGS_VIRTUAL_HANDLER; break;
1494	case PGMVIRTHANDLERTYPE_WRITE: fFlags = MM_RAM_FLAGS_VIRTUAL_HANDLER \| MM_RAM_FLAGS_VIRTUAL_WRITE; break;
1495	case PGMVIRTHANDLERTYPE_ALL: fFlags = MM_RAM_FLAGS_VIRTUAL_HANDLER \| MM_RAM_FLAGS_VIRTUAL_ALL; break;
1496	/* hypervisor handlers need no flags and wouldn't have nowhere to put them in any case. */
1497	case PGMVIRTHANDLERTYPE_HYPERVISOR:
1498	return 0;
1499	default:
1500	AssertMsgFailed(("unknown enmType=%d\n", pVirt->enmType));
1501	return 0;
1502	}
1503
1504	/*
1505	* Check pages against flags.
1506	*/
1507	RTGCUINTPTR GCPtr = (RTGCUINTPTR)pVirt->GCPtr;
1508	for (unsigned iPage = 0; iPage < pVirt->cPages; iPage++, GCPtr += PAGE_SIZE)
1509	{
1510	RTGCPHYS GCPhysGst;
1511	uint64_t fGst;
1512	int rc = PGMGstGetPage(pVM, (RTGCPTR)GCPtr, &fGst, &GCPhysGst);
1513	if (rc == VERR_PAGE_NOT_PRESENT)
1514	{
1515	if (pVirt->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
1516	{
1517	AssertMsgFailed(("virt handler phys out of sync. %VGp GCPhysNew=~0 iPage=%#x %VGv %s\n",
1518	pVirt->aPhysToVirt[iPage].Core.Key, iPage, GCPtr, HCSTRING(pVirt->pszDesc)));
1519	pState->cErrors++;
1520	}
1521	continue;
1522	}
1523
1524	AssertRCReturn(rc, 0);
1525	if ((pVirt->aPhysToVirt[iPage].Core.Key & X86_PTE_PAE_PG_MASK) != GCPhysGst)
1526	{
1527	AssertMsgFailed(("virt handler phys out of sync. %VGp GCPhysGst=%VGp iPage=%#x %VGv %s\n",
1528	pVirt->aPhysToVirt[iPage].Core.Key, GCPhysGst, iPage, GCPtr, HCSTRING(pVirt->pszDesc)));
1529	pState->cErrors++;
1530	continue;
1531	}
1532
1533	RTHCPHYS HCPhys;
1534	rc = PGMRamGCPhys2HCPhysWithFlags(&pVM->pgm.s, GCPhysGst, &HCPhys);
1535	if (VBOX_FAILURE(rc))
1536	{
1537	AssertMsgFailed(("virt handler getting ram flags rc=%Vrc. GCPhysGst=%VGp iPage=%#x %VGv %s\n",
1538	rc, GCPhysGst, iPage, GCPtr, HCSTRING(pVirt->pszDesc)));
1539	pState->cErrors++;
1540	continue;
1541	}
1542
1543	if ((HCPhys & fFlags) != fFlags)
1544	{
1545	AssertMsgFailed(("virt handler flags mismatch. HCPhys=%VHp fFlags=%#x GCPhysGst=%VGp iPage=%#x %VGv %s\n",
1546	HCPhys, fFlags, GCPhysGst, iPage, GCPtr, HCSTRING(pVirt->pszDesc)));
1547	pState->cErrors++;
1548	continue;
1549	}
1550	} /* for pages in virtual mapping. */
1551
1552	return 0;
1553	}
1554
1555
1556	/**
1557	* Asserts that the handlers+guest-page-tables == ramrange-flags and
1558	* that the physical addresses associated with virtual handlers are correct.
1559	*
1560	* @returns Number of mismatches.
1561	* @param pVM The VM handle.
1562	*/
1563	PGMDECL(unsigned) PGMAssertHandlerAndFlagsInSync(PVM pVM)
1564	{
1565	PPGM pPGM = &pVM->pgm.s;
1566	PGMAHAFIS State;
1567	State.cErrors = 0;
1568	State.pVM = pVM;
1569
1570	/*
1571	* Check the RAM flags against the handlers.
1572	*/
1573	for (PPGMRAMRANGE pRam = CTXSUFF(pPGM->pRamRanges); pRam; pRam = CTXSUFF(pRam->pNext))
1574	{
1575	const unsigned cPages = pRam->cb >> PAGE_SHIFT;
1576	for (unsigned iPage = 0; iPage < cPages; iPage++)
1577	{
1578	State.GCPhys = pRam->GCPhys + (iPage << PAGE_SHIFT);
1579	const unsigned fFlags = pRam->aHCPhys[iPage]
1580	& ( MM_RAM_FLAGS_VIRTUAL_HANDLER \| MM_RAM_FLAGS_VIRTUAL_WRITE \| MM_RAM_FLAGS_VIRTUAL_ALL
1581	\| MM_RAM_FLAGS_PHYSICAL_HANDLER \| MM_RAM_FLAGS_PHYSICAL_WRITE \| MM_RAM_FLAGS_PHYSICAL_ALL \| MM_RAM_FLAGS_PHYSICAL_TEMP_OFF);
1582	if (fFlags)
1583	{
1584	State.fFlagsFound = 0; /* build flags and compare. */
1585
1586	/* physical first. (simple because of page alignment) */
1587	if ( !(fFlags & MM_RAM_FLAGS_PHYSICAL_TEMP_OFF)
1588	&& (fFlags & (MM_RAM_FLAGS_PHYSICAL_HANDLER \| MM_RAM_FLAGS_PHYSICAL_WRITE \| MM_RAM_FLAGS_PHYSICAL_ALL)))
1589	{
1590	PPGMPHYSHANDLER pPhys = (PPGMPHYSHANDLER)RTAvlroGCPhysRangeGet(&pPGM->CTXSUFF(pTrees)->PhysHandlers, State.GCPhys);
1591	if (!pPhys)
1592	{
1593	pPhys = (PPGMPHYSHANDLER)RTAvlroGCPhysGetBestFit(&pPGM->CTXSUFF(pTrees)->PhysHandlers, State.GCPhys, true);
1594	if ( pPhys
1595	&& pPhys->Core.Key > (State.GCPhys + PAGE_SIZE - 1))
1596	pPhys = NULL;
1597	Assert(!pPhys \|\| pPhys->Core.Key >= State.GCPhys);
1598	}
1599	if (pPhys)
1600	{
1601	switch (pPhys->enmType)
1602	{
1603	case PGMPHYSHANDLERTYPE_PHYSICAL: State.fFlagsFound \|= MM_RAM_FLAGS_PHYSICAL_HANDLER; break;
1604	case PGMPHYSHANDLERTYPE_PHYSICAL_WRITE: State.fFlagsFound \|= MM_RAM_FLAGS_PHYSICAL_HANDLER \| MM_RAM_FLAGS_PHYSICAL_WRITE; break;
1605	case PGMPHYSHANDLERTYPE_MMIO:
1606	case PGMPHYSHANDLERTYPE_PHYSICAL_ALL: State.fFlagsFound \|= MM_RAM_FLAGS_PHYSICAL_HANDLER \| MM_RAM_FLAGS_PHYSICAL_ALL; break;
1607	default: AssertMsgFailed(("Invalid type phys type %d\n", pPhys->enmType)); State.cErrors++; break;
1608	}
1609	if ( (fFlags & (MM_RAM_FLAGS_PHYSICAL_HANDLER \| MM_RAM_FLAGS_PHYSICAL_WRITE \| MM_RAM_FLAGS_PHYSICAL_ALL))
1610	!= State.fFlagsFound)
1611	{
1612	AssertMsgFailed(("ram range vs phys handler flags mismatch. GCPhys=%#x fFlags=%#x fFlagsFound=%#x %s\n",
1613	State.GCPhys, fFlags, State.fFlagsFound, pPhys->pszDesc));
1614	State.cErrors++;
1615	}
1616
1617	#ifdef IN_RING3
1618	/* validate that REM is handling it. */
1619	if (!REMR3IsPageAccessHandled(pVM, State.GCPhys))
1620	{
1621	AssertMsgFailed(("ram range vs phys handler REM mismatch. GCPhys=%#x fFlags=%#x %s\n",
1622	State.GCPhys, fFlags, pPhys->pszDesc));
1623	State.cErrors++;
1624	}
1625	#endif
1626	}
1627	else
1628	{
1629	AssertMsgFailed(("ram range vs phys handler mismatch. no handler for GCPhys=%#x\n", State.GCPhys));
1630	State.cErrors++;
1631	}
1632	}
1633
1634	/* virtual flags. */
1635	if (fFlags & (MM_RAM_FLAGS_VIRTUAL_HANDLER \| MM_RAM_FLAGS_VIRTUAL_WRITE \| MM_RAM_FLAGS_VIRTUAL_ALL))
1636	{
1637	State.fFlags = fFlags;
1638	RTAvlroGCPtrDoWithAll(CTXSUFF(&pVM->pgm.s.pTrees)->VirtHandlers, true, pgmVirtHandlerVerifyOneByPhysAddr, &State);
1639	if ( (fFlags & (MM_RAM_FLAGS_VIRTUAL_HANDLER \| MM_RAM_FLAGS_VIRTUAL_WRITE \| MM_RAM_FLAGS_VIRTUAL_ALL))
1640	!= State.fFlagsFound)
1641	{
1642	AssertMsgFailed(("ram range vs virt handler flags mismatch. GCPhys=%#x fFlags=%#x fFlagsFound=%#x\n",
1643	State.GCPhys, fFlags, State.fFlagsFound));
1644	State.cErrors++;
1645	}
1646
1647	}
1648	}
1649	} /* foreach page in ram range. */
1650	} /* foreach ram range. */
1651
1652	/*
1653	* Check that the physical addresses of the virtual handlers matches up.
1654	*/
1655	RTAvlroGCPtrDoWithAll(CTXSUFF(&pVM->pgm.s.pTrees)->VirtHandlers, true, pgmVirtHandlerVerifyOne, &State);
1656
1657	return State.cErrors;
1658	}
1659
1660
1661	/**
1662	* Asserts that there are no mapping conflicts.
1663	*
1664	* @returns Number of conflicts.
1665	* @param pVM The VM Handle.
1666	*/
1667	PGMDECL(unsigned) PGMAssertNoMappingConflicts(PVM pVM)
1668	{
1669	unsigned cErrors = 0;
1670
1671	/*
1672	* Check for mapping conflicts.
1673	*/
1674	for (PPGMMAPPING pMapping = CTXALLSUFF(pVM->pgm.s.pMappings);
1675	pMapping;
1676	pMapping = CTXALLSUFF(pMapping->pNext))
1677	{
1678	/** @todo This is slow and should be optimized, but since it's just assertions I don't care now. */
1679	for (RTGCUINTPTR GCPtr = (RTGCUINTPTR)pMapping->GCPtr;
1680	GCPtr <= (RTGCUINTPTR)pMapping->GCPtrLast;
1681	GCPtr += PAGE_SIZE)
1682	{
1683	int rc = PGMGstGetPage(pVM, (RTGCPTR)GCPtr, NULL, NULL);
1684	if (rc != VERR_PAGE_TABLE_NOT_PRESENT)
1685	{
1686	AssertMsgFailed(("Conflict at %VGv with %s\n", GCPtr, HCSTRING(pMapping->pszDesc)));
1687	cErrors++;
1688	break;
1689	}
1690	}
1691	}
1692
1693	return cErrors;
1694	}
1695
1696
1697	/**
1698	* Asserts that everything related to the guest CR3 is correctly shadowed.
1699	*
1700	* This will call PGMAssertNoMappingConflicts() and PGMAssertHandlerAndFlagsInSync(),
1701	* and assert the correctness of the guest CR3 mapping before asserting that the
1702	* shadow page tables is in sync with the guest page tables.
1703	*
1704	* @returns Number of conflicts.
1705	* @param pVM The VM Handle.
1706	* @param cr3 The current guest CR3 register value.
1707	* @param cr4 The current guest CR4 register value.
1708	*/
1709	PGMDECL(unsigned) PGMAssertCR3(PVM pVM, uint32_t cr3, uint32_t cr4)
1710	{
1711	STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat,SyncCR3), a);
1712	unsigned cErrors = PGM_BTH_PFN(AssertCR3, pVM)(pVM, cr3, cr4, 0, ~(RTGCUINTPTR)0);
1713	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncCR3), a);
1714	return cErrors;
1715	}
1716
1717	#endif /* VBOX_STRICT */

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAll.cpp@ 2299

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