VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAll.cpp@ 24764

Last change on this file since 24764 was 24764, checked in by vboxsync, 15 years ago

Handle missing page inconsistency with guest smp (instruction emulation)
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id
File size: 83.0 KB
Line 
1/* $Id: PGMAll.cpp 24764 2009-11-18 16:30:12Z vboxsync $ */
2/** @file
3 * PGM - Page Manager and Monitor - All context code.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22/*******************************************************************************
23* Header Files *
24*******************************************************************************/
25#define LOG_GROUP LOG_GROUP_PGM
26#include <VBox/pgm.h>
27#include <VBox/cpum.h>
28#include <VBox/selm.h>
29#include <VBox/iom.h>
30#include <VBox/sup.h>
31#include <VBox/mm.h>
32#include <VBox/stam.h>
33#include <VBox/csam.h>
34#include <VBox/patm.h>
35#include <VBox/trpm.h>
36#include <VBox/rem.h>
37#include <VBox/em.h>
38#include <VBox/hwaccm.h>
39#include <VBox/hwacc_vmx.h>
40#include "PGMInternal.h"
41#include <VBox/vm.h>
42#include <iprt/assert.h>
43#include <iprt/asm.h>
44#include <iprt/string.h>
45#include <VBox/log.h>
46#include <VBox/param.h>
47#include <VBox/err.h>
48
49
50/*******************************************************************************
51* Structures and Typedefs *
52*******************************************************************************/
53/**
54 * Stated structure for PGM_GST_NAME(HandlerVirtualUpdate) that's
55 * passed to PGM_GST_NAME(VirtHandlerUpdateOne) during enumeration.
56 */
57typedef struct PGMHVUSTATE
58{
59 /** The VM handle. */
60 PVM pVM;
61 /** The VMCPU handle. */
62 PVMCPU pVCpu;
63 /** The todo flags. */
64 RTUINT fTodo;
65 /** The CR4 register value. */
66 uint32_t cr4;
67} PGMHVUSTATE, *PPGMHVUSTATE;
68
69
70/*******************************************************************************
71* Internal Functions *
72*******************************************************************************/
73DECLINLINE(int) pgmShwGetLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPT *ppPdpt, PX86PDPAE *ppPD);
74DECLINLINE(int) pgmShwGetPaePoolPagePD(PPGMCPU pPGM, RTGCPTR GCPtr, PPGMPOOLPAGE *ppShwPde);
75
76/*
77 * Shadow - 32-bit mode
78 */
79#define PGM_SHW_TYPE PGM_TYPE_32BIT
80#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
81#include "PGMAllShw.h"
82
83/* Guest - real mode */
84#define PGM_GST_TYPE PGM_TYPE_REAL
85#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
86#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
87#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
88#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
89#include "PGMGstDefs.h"
90#include "PGMAllGst.h"
91#include "PGMAllBth.h"
92#undef BTH_PGMPOOLKIND_PT_FOR_PT
93#undef BTH_PGMPOOLKIND_ROOT
94#undef PGM_BTH_NAME
95#undef PGM_GST_TYPE
96#undef PGM_GST_NAME
97
98/* Guest - protected mode */
99#define PGM_GST_TYPE PGM_TYPE_PROT
100#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
101#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
102#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
103#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
104#include "PGMGstDefs.h"
105#include "PGMAllGst.h"
106#include "PGMAllBth.h"
107#undef BTH_PGMPOOLKIND_PT_FOR_PT
108#undef BTH_PGMPOOLKIND_ROOT
109#undef PGM_BTH_NAME
110#undef PGM_GST_TYPE
111#undef PGM_GST_NAME
112
113/* Guest - 32-bit mode */
114#define PGM_GST_TYPE PGM_TYPE_32BIT
115#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
116#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
117#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
118#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
119#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD
120#include "PGMGstDefs.h"
121#include "PGMAllGst.h"
122#include "PGMAllBth.h"
123#undef BTH_PGMPOOLKIND_PT_FOR_BIG
124#undef BTH_PGMPOOLKIND_PT_FOR_PT
125#undef BTH_PGMPOOLKIND_ROOT
126#undef PGM_BTH_NAME
127#undef PGM_GST_TYPE
128#undef PGM_GST_NAME
129
130#undef PGM_SHW_TYPE
131#undef PGM_SHW_NAME
132
133
134/*
135 * Shadow - PAE mode
136 */
137#define PGM_SHW_TYPE PGM_TYPE_PAE
138#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
139#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
140#include "PGMAllShw.h"
141
142/* Guest - real mode */
143#define PGM_GST_TYPE PGM_TYPE_REAL
144#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
145#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
146#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
147#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
148#include "PGMGstDefs.h"
149#include "PGMAllBth.h"
150#undef BTH_PGMPOOLKIND_PT_FOR_PT
151#undef BTH_PGMPOOLKIND_ROOT
152#undef PGM_BTH_NAME
153#undef PGM_GST_TYPE
154#undef PGM_GST_NAME
155
156/* Guest - protected mode */
157#define PGM_GST_TYPE PGM_TYPE_PROT
158#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
159#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
160#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
161#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
162#include "PGMGstDefs.h"
163#include "PGMAllBth.h"
164#undef BTH_PGMPOOLKIND_PT_FOR_PT
165#undef BTH_PGMPOOLKIND_ROOT
166#undef PGM_BTH_NAME
167#undef PGM_GST_TYPE
168#undef PGM_GST_NAME
169
170/* Guest - 32-bit mode */
171#define PGM_GST_TYPE PGM_TYPE_32BIT
172#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
173#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
174#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
175#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
176#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_FOR_32BIT
177#include "PGMGstDefs.h"
178#include "PGMAllBth.h"
179#undef BTH_PGMPOOLKIND_PT_FOR_BIG
180#undef BTH_PGMPOOLKIND_PT_FOR_PT
181#undef BTH_PGMPOOLKIND_ROOT
182#undef PGM_BTH_NAME
183#undef PGM_GST_TYPE
184#undef PGM_GST_NAME
185
186
187/* Guest - PAE mode */
188#define PGM_GST_TYPE PGM_TYPE_PAE
189#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
190#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
191#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
192#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
193#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT
194#include "PGMGstDefs.h"
195#include "PGMAllGst.h"
196#include "PGMAllBth.h"
197#undef BTH_PGMPOOLKIND_PT_FOR_BIG
198#undef BTH_PGMPOOLKIND_PT_FOR_PT
199#undef BTH_PGMPOOLKIND_ROOT
200#undef PGM_BTH_NAME
201#undef PGM_GST_TYPE
202#undef PGM_GST_NAME
203
204#undef PGM_SHW_TYPE
205#undef PGM_SHW_NAME
206
207
208#ifndef IN_RC /* AMD64 implies VT-x/AMD-V */
209/*
210 * Shadow - AMD64 mode
211 */
212# define PGM_SHW_TYPE PGM_TYPE_AMD64
213# define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
214# include "PGMAllShw.h"
215
216/* Guest - protected mode (only used for AMD-V nested paging in 64 bits mode) */
217# define PGM_GST_TYPE PGM_TYPE_PROT
218# define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
219# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_PROT(name)
220# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
221# define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PD_PHYS
222# include "PGMGstDefs.h"
223# include "PGMAllBth.h"
224# undef BTH_PGMPOOLKIND_PT_FOR_PT
225# undef BTH_PGMPOOLKIND_ROOT
226# undef PGM_BTH_NAME
227# undef PGM_GST_TYPE
228# undef PGM_GST_NAME
229
230# ifdef VBOX_WITH_64_BITS_GUESTS
231/* Guest - AMD64 mode */
232# define PGM_GST_TYPE PGM_TYPE_AMD64
233# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
234# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
235# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
236# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
237# define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_64BIT_PML4
238# include "PGMGstDefs.h"
239# include "PGMAllGst.h"
240# include "PGMAllBth.h"
241# undef BTH_PGMPOOLKIND_PT_FOR_BIG
242# undef BTH_PGMPOOLKIND_PT_FOR_PT
243# undef BTH_PGMPOOLKIND_ROOT
244# undef PGM_BTH_NAME
245# undef PGM_GST_TYPE
246# undef PGM_GST_NAME
247# endif /* VBOX_WITH_64_BITS_GUESTS */
248
249# undef PGM_SHW_TYPE
250# undef PGM_SHW_NAME
251
252
253/*
254 * Shadow - Nested paging mode
255 */
256# define PGM_SHW_TYPE PGM_TYPE_NESTED
257# define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED(name)
258# include "PGMAllShw.h"
259
260/* Guest - real mode */
261# define PGM_GST_TYPE PGM_TYPE_REAL
262# define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
263# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_REAL(name)
264# include "PGMGstDefs.h"
265# include "PGMAllBth.h"
266# undef PGM_BTH_NAME
267# undef PGM_GST_TYPE
268# undef PGM_GST_NAME
269
270/* Guest - protected mode */
271# define PGM_GST_TYPE PGM_TYPE_PROT
272# define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
273# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PROT(name)
274# include "PGMGstDefs.h"
275# include "PGMAllBth.h"
276# undef PGM_BTH_NAME
277# undef PGM_GST_TYPE
278# undef PGM_GST_NAME
279
280/* Guest - 32-bit mode */
281# define PGM_GST_TYPE PGM_TYPE_32BIT
282# define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
283# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT(name)
284# include "PGMGstDefs.h"
285# include "PGMAllBth.h"
286# undef PGM_BTH_NAME
287# undef PGM_GST_TYPE
288# undef PGM_GST_NAME
289
290/* Guest - PAE mode */
291# define PGM_GST_TYPE PGM_TYPE_PAE
292# define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
293# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE(name)
294# include "PGMGstDefs.h"
295# include "PGMAllBth.h"
296# undef PGM_BTH_NAME
297# undef PGM_GST_TYPE
298# undef PGM_GST_NAME
299
300# ifdef VBOX_WITH_64_BITS_GUESTS
301/* Guest - AMD64 mode */
302# define PGM_GST_TYPE PGM_TYPE_AMD64
303# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
304# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64(name)
305# include "PGMGstDefs.h"
306# include "PGMAllBth.h"
307# undef PGM_BTH_NAME
308# undef PGM_GST_TYPE
309# undef PGM_GST_NAME
310# endif /* VBOX_WITH_64_BITS_GUESTS */
311
312# undef PGM_SHW_TYPE
313# undef PGM_SHW_NAME
314
315
316/*
317 * Shadow - EPT
318 */
319# define PGM_SHW_TYPE PGM_TYPE_EPT
320# define PGM_SHW_NAME(name) PGM_SHW_NAME_EPT(name)
321# include "PGMAllShw.h"
322
323/* Guest - real mode */
324# define PGM_GST_TYPE PGM_TYPE_REAL
325# define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
326# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_REAL(name)
327# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
328# include "PGMGstDefs.h"
329# include "PGMAllBth.h"
330# undef BTH_PGMPOOLKIND_PT_FOR_PT
331# undef PGM_BTH_NAME
332# undef PGM_GST_TYPE
333# undef PGM_GST_NAME
334
335/* Guest - protected mode */
336# define PGM_GST_TYPE PGM_TYPE_PROT
337# define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
338# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PROT(name)
339# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
340# include "PGMGstDefs.h"
341# include "PGMAllBth.h"
342# undef BTH_PGMPOOLKIND_PT_FOR_PT
343# undef PGM_BTH_NAME
344# undef PGM_GST_TYPE
345# undef PGM_GST_NAME
346
347/* Guest - 32-bit mode */
348# define PGM_GST_TYPE PGM_TYPE_32BIT
349# define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
350# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_32BIT(name)
351# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
352# include "PGMGstDefs.h"
353# include "PGMAllBth.h"
354# undef BTH_PGMPOOLKIND_PT_FOR_PT
355# undef PGM_BTH_NAME
356# undef PGM_GST_TYPE
357# undef PGM_GST_NAME
358
359/* Guest - PAE mode */
360# define PGM_GST_TYPE PGM_TYPE_PAE
361# define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
362# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PAE(name)
363# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
364# include "PGMGstDefs.h"
365# include "PGMAllBth.h"
366# undef BTH_PGMPOOLKIND_PT_FOR_PT
367# undef PGM_BTH_NAME
368# undef PGM_GST_TYPE
369# undef PGM_GST_NAME
370
371# ifdef VBOX_WITH_64_BITS_GUESTS
372/* Guest - AMD64 mode */
373# define PGM_GST_TYPE PGM_TYPE_AMD64
374# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
375# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_AMD64(name)
376# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
377# include "PGMGstDefs.h"
378# include "PGMAllBth.h"
379# undef BTH_PGMPOOLKIND_PT_FOR_PT
380# undef PGM_BTH_NAME
381# undef PGM_GST_TYPE
382# undef PGM_GST_NAME
383# endif /* VBOX_WITH_64_BITS_GUESTS */
384
385# undef PGM_SHW_TYPE
386# undef PGM_SHW_NAME
387
388#endif /* !IN_RC */
389
390
391#ifndef IN_RING3
392/**
393 * #PF Handler.
394 *
395 * @returns VBox status code (appropriate for trap handling and GC return).
396 * @param pVCpu VMCPU handle.
397 * @param uErr The trap error code.
398 * @param pRegFrame Trap register frame.
399 * @param pvFault The fault address.
400 */
401VMMDECL(int) PGMTrap0eHandler(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
402{
403 PVM pVM = pVCpu->CTX_SUFF(pVM);
404
405 Log(("PGMTrap0eHandler: uErr=%RGu pvFault=%RGv eip=%04x:%RGv\n", uErr, pvFault, pRegFrame->cs, (RTGCPTR)pRegFrame->rip));
406 STAM_PROFILE_START(&pVCpu->pgm.s.StatRZTrap0e, a);
407 STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = NULL; } );
408
409
410#ifdef VBOX_WITH_STATISTICS
411 /*
412 * Error code stats.
413 */
414 if (uErr & X86_TRAP_PF_US)
415 {
416 if (!(uErr & X86_TRAP_PF_P))
417 {
418 if (uErr & X86_TRAP_PF_RW)
419 STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eUSNotPresentWrite);
420 else
421 STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eUSNotPresentRead);
422 }
423 else if (uErr & X86_TRAP_PF_RW)
424 STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eUSWrite);
425 else if (uErr & X86_TRAP_PF_RSVD)
426 STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eUSReserved);
427 else if (uErr & X86_TRAP_PF_ID)
428 STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eUSNXE);
429 else
430 STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eUSRead);
431 }
432 else
433 { /* Supervisor */
434 if (!(uErr & X86_TRAP_PF_P))
435 {
436 if (uErr & X86_TRAP_PF_RW)
437 STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eSVNotPresentWrite);
438 else
439 STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eSVNotPresentRead);
440 }
441 else if (uErr & X86_TRAP_PF_RW)
442 STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eSVWrite);
443 else if (uErr & X86_TRAP_PF_ID)
444 STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eSNXE);
445 else if (uErr & X86_TRAP_PF_RSVD)
446 STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eSVReserved);
447 }
448#endif /* VBOX_WITH_STATISTICS */
449
450 /*
451 * Call the worker.
452 */
453 pgmLock(pVM);
454 int rc = PGM_BTH_PFN(Trap0eHandler, pVCpu)(pVCpu, uErr, pRegFrame, pvFault);
455 Assert(PGMIsLockOwner(pVM));
456 pgmUnlock(pVM);
457 if (rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
458 rc = VINF_SUCCESS;
459
460# ifdef IN_RING0
461 /* Note: hack alert for difficult to reproduce problem. */
462 if ( rc == VERR_PAGE_NOT_PRESENT /* SMP only ; disassembly might fail. */
463 || rc == VERR_PAGE_TABLE_NOT_PRESENT /* seen with UNI & SMP */
464 || rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT /* seen with SMP */
465 || rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT) /* precaution */
466 {
467 Log(("WARNING: Unexpected VERR_PAGE_TABLE_NOT_PRESENT (%d) for page fault at %RGv error code %x (rip=%RGv)\n", rc, pvFault, uErr, pRegFrame->rip));
468 /* Some kind of inconsistency in the SMP case; it's safe to just execute the instruction again; not sure about single VCPU VMs though. */
469 rc = VINF_SUCCESS;
470 }
471# endif
472
473 STAM_STATS({ if (rc == VINF_EM_RAW_GUEST_TRAP) STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eGuestPF); });
474 STAM_STATS({ if (!pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution))
475 pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2Misc; });
476 STAM_PROFILE_STOP_EX(&pVCpu->pgm.s.StatRZTrap0e, pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution), a);
477 return rc;
478}
479#endif /* !IN_RING3 */
480
481
482/**
483 * Prefetch a page
484 *
485 * Typically used to sync commonly used pages before entering raw mode
486 * after a CR3 reload.
487 *
488 * @returns VBox status code suitable for scheduling.
489 * @retval VINF_SUCCESS on success.
490 * @retval VINF_PGM_SYNC_CR3 if we're out of shadow pages or something like that.
491 * @param pVCpu VMCPU handle.
492 * @param GCPtrPage Page to invalidate.
493 */
494VMMDECL(int) PGMPrefetchPage(PVMCPU pVCpu, RTGCPTR GCPtrPage)
495{
496 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_MID_Z(Stat,Prefetch), a);
497 int rc = PGM_BTH_PFN(PrefetchPage, pVCpu)(pVCpu, GCPtrPage);
498 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,Prefetch), a);
499 AssertMsg(rc == VINF_SUCCESS || rc == VINF_PGM_SYNC_CR3 || RT_FAILURE(rc), ("rc=%Rrc\n", rc));
500 return rc;
501}
502
503
504/**
505 * Gets the mapping corresponding to the specified address (if any).
506 *
507 * @returns Pointer to the mapping.
508 * @returns NULL if not
509 *
510 * @param pVM The virtual machine.
511 * @param GCPtr The guest context pointer.
512 */
513PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr)
514{
515 PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
516 while (pMapping)
517 {
518 if ((uintptr_t)GCPtr < (uintptr_t)pMapping->GCPtr)
519 break;
520 if ((uintptr_t)GCPtr - (uintptr_t)pMapping->GCPtr < pMapping->cb)
521 return pMapping;
522 pMapping = pMapping->CTX_SUFF(pNext);
523 }
524 return NULL;
525}
526
527
528/**
529 * Verifies a range of pages for read or write access
530 *
531 * Only checks the guest's page tables
532 *
533 * @returns VBox status code.
534 * @param pVCpu VMCPU handle.
535 * @param Addr Guest virtual address to check
536 * @param cbSize Access size
537 * @param fAccess Access type (r/w, user/supervisor (X86_PTE_*))
538 * @remarks Current not in use.
539 */
540VMMDECL(int) PGMIsValidAccess(PVMCPU pVCpu, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess)
541{
542 /*
543 * Validate input.
544 */
545 if (fAccess & ~(X86_PTE_US | X86_PTE_RW))
546 {
547 AssertMsgFailed(("PGMIsValidAccess: invalid access type %08x\n", fAccess));
548 return VERR_INVALID_PARAMETER;
549 }
550
551 uint64_t fPage;
552 int rc = PGMGstGetPage(pVCpu, (RTGCPTR)Addr, &fPage, NULL);
553 if (RT_FAILURE(rc))
554 {
555 Log(("PGMIsValidAccess: access violation for %RGv rc=%d\n", Addr, rc));
556 return VINF_EM_RAW_GUEST_TRAP;
557 }
558
559 /*
560 * Check if the access would cause a page fault
561 *
562 * Note that hypervisor page directories are not present in the guest's tables, so this check
563 * is sufficient.
564 */
565 bool fWrite = !!(fAccess & X86_PTE_RW);
566 bool fUser = !!(fAccess & X86_PTE_US);
567 if ( !(fPage & X86_PTE_P)
568 || (fWrite && !(fPage & X86_PTE_RW))
569 || (fUser && !(fPage & X86_PTE_US)) )
570 {
571 Log(("PGMIsValidAccess: access violation for %RGv attr %#llx vs %d:%d\n", Addr, fPage, fWrite, fUser));
572 return VINF_EM_RAW_GUEST_TRAP;
573 }
574 if ( RT_SUCCESS(rc)
575 && PAGE_ADDRESS(Addr) != PAGE_ADDRESS(Addr + cbSize))
576 return PGMIsValidAccess(pVCpu, Addr + PAGE_SIZE, (cbSize > PAGE_SIZE) ? cbSize - PAGE_SIZE : 1, fAccess);
577 return rc;
578}
579
580
581/**
582 * Verifies a range of pages for read or write access
583 *
584 * Supports handling of pages marked for dirty bit tracking and CSAM
585 *
586 * @returns VBox status code.
587 * @param pVCpu VMCPU handle.
588 * @param Addr Guest virtual address to check
589 * @param cbSize Access size
590 * @param fAccess Access type (r/w, user/supervisor (X86_PTE_*))
591 */
592VMMDECL(int) PGMVerifyAccess(PVMCPU pVCpu, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess)
593{
594 PVM pVM = pVCpu->CTX_SUFF(pVM);
595
596 AssertMsg(!(fAccess & ~(X86_PTE_US | X86_PTE_RW)), ("PGMVerifyAccess: invalid access type %08x\n", fAccess));
597
598 /*
599 * Get going.
600 */
601 uint64_t fPageGst;
602 int rc = PGMGstGetPage(pVCpu, (RTGCPTR)Addr, &fPageGst, NULL);
603 if (RT_FAILURE(rc))
604 {
605 Log(("PGMVerifyAccess: access violation for %RGv rc=%d\n", Addr, rc));
606 return VINF_EM_RAW_GUEST_TRAP;
607 }
608
609 /*
610 * Check if the access would cause a page fault
611 *
612 * Note that hypervisor page directories are not present in the guest's tables, so this check
613 * is sufficient.
614 */
615 const bool fWrite = !!(fAccess & X86_PTE_RW);
616 const bool fUser = !!(fAccess & X86_PTE_US);
617 if ( !(fPageGst & X86_PTE_P)
618 || (fWrite && !(fPageGst & X86_PTE_RW))
619 || (fUser && !(fPageGst & X86_PTE_US)) )
620 {
621 Log(("PGMVerifyAccess: access violation for %RGv attr %#llx vs %d:%d\n", Addr, fPageGst, fWrite, fUser));
622 return VINF_EM_RAW_GUEST_TRAP;
623 }
624
625 if (!HWACCMIsNestedPagingActive(pVM))
626 {
627 /*
628 * Next step is to verify if we protected this page for dirty bit tracking or for CSAM scanning
629 */
630 rc = PGMShwGetPage(pVCpu, (RTGCPTR)Addr, NULL, NULL);
631 if ( rc == VERR_PAGE_NOT_PRESENT
632 || rc == VERR_PAGE_TABLE_NOT_PRESENT)
633 {
634 /*
635 * Page is not present in our page tables.
636 * Try to sync it!
637 */
638 Assert(X86_TRAP_PF_RW == X86_PTE_RW && X86_TRAP_PF_US == X86_PTE_US);
639 uint32_t uErr = fAccess & (X86_TRAP_PF_RW | X86_TRAP_PF_US);
640 rc = PGM_BTH_PFN(VerifyAccessSyncPage, pVCpu)(pVCpu, Addr, fPageGst, uErr);
641 if (rc != VINF_SUCCESS)
642 return rc;
643 }
644 else
645 AssertMsg(rc == VINF_SUCCESS, ("PGMShwGetPage %RGv failed with %Rrc\n", Addr, rc));
646 }
647
648#if 0 /* def VBOX_STRICT; triggers too often now */
649 /*
650 * This check is a bit paranoid, but useful.
651 */
652 /** @note this will assert when writing to monitored pages (a bit annoying actually) */
653 uint64_t fPageShw;
654 rc = PGMShwGetPage(pVCpu, (RTGCPTR)Addr, &fPageShw, NULL);
655 if ( (rc == VERR_PAGE_NOT_PRESENT || RT_FAILURE(rc))
656 || (fWrite && !(fPageShw & X86_PTE_RW))
657 || (fUser && !(fPageShw & X86_PTE_US)) )
658 {
659 AssertMsgFailed(("Unexpected access violation for %RGv! rc=%Rrc write=%d user=%d\n",
660 Addr, rc, fWrite && !(fPageShw & X86_PTE_RW), fUser && !(fPageShw & X86_PTE_US)));
661 return VINF_EM_RAW_GUEST_TRAP;
662 }
663#endif
664
665 if ( RT_SUCCESS(rc)
666 && ( PAGE_ADDRESS(Addr) != PAGE_ADDRESS(Addr + cbSize - 1)
667 || Addr + cbSize < Addr))
668 {
669 /* Don't recursively call PGMVerifyAccess as we might run out of stack. */
670 for (;;)
671 {
672 Addr += PAGE_SIZE;
673 if (cbSize > PAGE_SIZE)
674 cbSize -= PAGE_SIZE;
675 else
676 cbSize = 1;
677 rc = PGMVerifyAccess(pVCpu, Addr, 1, fAccess);
678 if (rc != VINF_SUCCESS)
679 break;
680 if (PAGE_ADDRESS(Addr) == PAGE_ADDRESS(Addr + cbSize - 1))
681 break;
682 }
683 }
684 return rc;
685}
686
687
688/**
689 * Emulation of the invlpg instruction (HC only actually).
690 *
691 * @returns VBox status code, special care required.
692 * @retval VINF_PGM_SYNC_CR3 - handled.
693 * @retval VINF_EM_RAW_EMULATE_INSTR - not handled (RC only).
694 * @retval VERR_REM_FLUSHED_PAGES_OVERFLOW - not handled.
695 *
696 * @param pVCpu VMCPU handle.
697 * @param GCPtrPage Page to invalidate.
698 *
699 * @remark ASSUMES the page table entry or page directory is valid. Fairly
700 * safe, but there could be edge cases!
701 *
702 * @todo Flush page or page directory only if necessary!
703 */
704VMMDECL(int) PGMInvalidatePage(PVMCPU pVCpu, RTGCPTR GCPtrPage)
705{
706 PVM pVM = pVCpu->CTX_SUFF(pVM);
707 int rc;
708 Log3(("PGMInvalidatePage: GCPtrPage=%RGv\n", GCPtrPage));
709
710#ifndef IN_RING3
711 /*
712 * Notify the recompiler so it can record this instruction.
713 * Failure happens when it's out of space. We'll return to HC in that case.
714 */
715 rc = REMNotifyInvalidatePage(pVM, GCPtrPage);
716 if (rc != VINF_SUCCESS)
717 return rc;
718#endif /* !IN_RING3 */
719
720
721#ifdef IN_RC
722 /*
723 * Check for conflicts and pending CR3 monitoring updates.
724 */
725 if (!pVM->pgm.s.fMappingsFixed)
726 {
727 if ( pgmGetMapping(pVM, GCPtrPage)
728 && PGMGstGetPage(pVCpu, GCPtrPage, NULL, NULL) != VERR_PAGE_TABLE_NOT_PRESENT)
729 {
730 LogFlow(("PGMGCInvalidatePage: Conflict!\n"));
731 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
732 STAM_COUNTER_INC(&pVM->pgm.s.StatRCInvlPgConflict);
733 return VINF_PGM_SYNC_CR3;
734 }
735
736 if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
737 {
738 LogFlow(("PGMGCInvalidatePage: PGM_SYNC_MONITOR_CR3 -> reinterpret instruction in R3\n"));
739 STAM_COUNTER_INC(&pVM->pgm.s.StatRCInvlPgSyncMonCR3);
740 return VINF_EM_RAW_EMULATE_INSTR;
741 }
742 }
743#endif /* IN_RC */
744
745 /*
746 * Call paging mode specific worker.
747 */
748 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePage), a);
749 pgmLock(pVM);
750 rc = PGM_BTH_PFN(InvalidatePage, pVCpu)(pVCpu, GCPtrPage);
751 pgmUnlock(pVM);
752 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePage), a);
753
754#ifdef IN_RING3
755 /*
756 * Check if we have a pending update of the CR3 monitoring.
757 */
758 if ( RT_SUCCESS(rc)
759 && (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3))
760 {
761 pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
762 Assert(!pVM->pgm.s.fMappingsFixed);
763 }
764
765 /*
766 * Inform CSAM about the flush
767 *
768 * Note: This is to check if monitored pages have been changed; when we implement
769 * callbacks for virtual handlers, this is no longer required.
770 */
771 CSAMR3FlushPage(pVM, GCPtrPage);
772#endif /* IN_RING3 */
773 return rc;
774}
775
776
777/**
778 * Executes an instruction using the interpreter.
779 *
780 * @returns VBox status code (appropriate for trap handling and GC return).
781 * @param pVM VM handle.
782 * @param pVCpu VMCPU handle.
783 * @param pRegFrame Register frame.
784 * @param pvFault Fault address.
785 */
786VMMDECL(int) PGMInterpretInstruction(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
787{
788 uint32_t cb;
789 int rc = EMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault, &cb);
790 if (rc == VERR_EM_INTERPRETER)
791 rc = VINF_EM_RAW_EMULATE_INSTR;
792 if (rc != VINF_SUCCESS)
793 Log(("PGMInterpretInstruction: returns %Rrc (pvFault=%RGv)\n", rc, pvFault));
794 return rc;
795}
796
797
798/**
799 * Gets effective page information (from the VMM page directory).
800 *
801 * @returns VBox status.
802 * @param pVCpu VMCPU handle.
803 * @param GCPtr Guest Context virtual address of the page.
804 * @param pfFlags Where to store the flags. These are X86_PTE_*.
805 * @param pHCPhys Where to store the HC physical address of the page.
806 * This is page aligned.
807 * @remark You should use PGMMapGetPage() for pages in a mapping.
808 */
809VMMDECL(int) PGMShwGetPage(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys)
810{
811 pgmLock(pVCpu->CTX_SUFF(pVM));
812 int rc = PGM_SHW_PFN(GetPage, pVCpu)(pVCpu, GCPtr, pfFlags, pHCPhys);
813 pgmUnlock(pVCpu->CTX_SUFF(pVM));
814 return rc;
815}
816
817
818/**
819 * Sets (replaces) the page flags for a range of pages in the shadow context.
820 *
821 * @returns VBox status.
822 * @param pVCpu VMCPU handle.
823 * @param GCPtr The address of the first page.
824 * @param cb The size of the range in bytes.
825 * @param fFlags Page flags X86_PTE_*, excluding the page mask of course.
826 * @remark You must use PGMMapSetPage() for pages in a mapping.
827 */
828VMMDECL(int) PGMShwSetPage(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags)
829{
830 return PGMShwModifyPage(pVCpu, GCPtr, cb, fFlags, 0);
831}
832
833
834/**
835 * Modify page flags for a range of pages in the shadow context.
836 *
837 * The existing flags are ANDed with the fMask and ORed with the fFlags.
838 *
839 * @returns VBox status code.
840 * @param pVCpu VMCPU handle.
841 * @param GCPtr Virtual address of the first page in the range.
842 * @param cb Size (in bytes) of the range to apply the modification to.
843 * @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
844 * @param fMask The AND mask - page flags X86_PTE_*.
845 * Be very CAREFUL when ~'ing constants which could be 32-bit!
846 * @remark You must use PGMMapModifyPage() for pages in a mapping.
847 */
848VMMDECL(int) PGMShwModifyPage(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
849{
850 AssertMsg(!(fFlags & X86_PTE_PAE_PG_MASK), ("fFlags=%#llx\n", fFlags));
851 Assert(cb);
852
853 /*
854 * Align the input.
855 */
856 cb += GCPtr & PAGE_OFFSET_MASK;
857 cb = RT_ALIGN_Z(cb, PAGE_SIZE);
858 GCPtr = (GCPtr & PAGE_BASE_GC_MASK); /** @todo this ain't necessary, right... */
859
860 /*
861 * Call worker.
862 */
863 PVM pVM = pVCpu->CTX_SUFF(pVM);
864 pgmLock(pVM);
865 int rc = PGM_SHW_PFN(ModifyPage, pVCpu)(pVCpu, GCPtr, cb, fFlags, fMask);
866 pgmUnlock(pVM);
867 return rc;
868}
869
870/**
871 * Gets the shadow page directory for the specified address, PAE.
872 *
873 * @returns Pointer to the shadow PD.
874 * @param pVCpu The VMCPU handle.
875 * @param GCPtr The address.
876 * @param pGstPdpe Guest PDPT entry
877 * @param ppPD Receives address of page directory
878 */
879int pgmShwSyncPaePDPtr(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDPE pGstPdpe, PX86PDPAE *ppPD)
880{
881 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
882 PX86PDPT pPdpt = pgmShwGetPaePDPTPtr(&pVCpu->pgm.s);
883 PX86PDPE pPdpe = &pPdpt->a[iPdPt];
884 PVM pVM = pVCpu->CTX_SUFF(pVM);
885 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
886 PPGMPOOLPAGE pShwPage;
887 int rc;
888
889 Assert(PGMIsLockOwner(pVM));
890
891 /* Allocate page directory if not present. */
892 if ( !pPdpe->n.u1Present
893 && !(pPdpe->u & X86_PDPE_PG_MASK))
894 {
895 bool fNestedPaging = HWACCMIsNestedPagingActive(pVM);
896 bool fPaging = !!(CPUMGetGuestCR0(pVCpu) & X86_CR0_PG);
897 RTGCPTR64 GCPdPt;
898 PGMPOOLKIND enmKind;
899
900# if defined(IN_RC)
901 /* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
902 PGMDynLockHCPage(pVM, (uint8_t *)pPdpe);
903# endif
904
905 if (fNestedPaging || !fPaging)
906 {
907 /* AMD-V nested paging or real/protected mode without paging */
908 GCPdPt = (RTGCPTR64)iPdPt << X86_PDPT_SHIFT;
909 enmKind = PGMPOOLKIND_PAE_PD_PHYS;
910 }
911 else
912 {
913 Assert(pGstPdpe);
914
915 if (CPUMGetGuestCR4(pVCpu) & X86_CR4_PAE)
916 {
917 if (!pGstPdpe->n.u1Present)
918 {
919 /* PD not present; guest must reload CR3 to change it.
920 * No need to monitor anything in this case.
921 */
922 Assert(!HWACCMIsEnabled(pVM));
923
924 GCPdPt = pGstPdpe->u & X86_PDPE_PG_MASK;
925 enmKind = PGMPOOLKIND_PAE_PD_PHYS;
926 pGstPdpe->n.u1Present = 1;
927 }
928 else
929 {
930 GCPdPt = pGstPdpe->u & X86_PDPE_PG_MASK;
931 enmKind = PGMPOOLKIND_PAE_PD_FOR_PAE_PD;
932 }
933 }
934 else
935 {
936 GCPdPt = CPUMGetGuestCR3(pVCpu);
937 enmKind = (PGMPOOLKIND)(PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD + iPdPt);
938 }
939 }
940
941 /* Create a reference back to the PDPT by using the index in its shadow page. */
942 rc = pgmPoolAlloc(pVM, GCPdPt, enmKind, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPdPt, &pShwPage);
943 AssertRCReturn(rc, rc);
944
945 /* The PD was cached or created; hook it up now. */
946 pPdpe->u |= pShwPage->Core.Key
947 | (pGstPdpe->u & ~(X86_PDPE_PG_MASK | X86_PDPE_AVL_MASK | X86_PDPE_PCD | X86_PDPE_PWT));
948
949# if defined(IN_RC)
950 /* In 32 bits PAE mode we *must* invalidate the TLB when changing a PDPT entry; the CPU fetches them only during cr3 load, so any
951 * non-present PDPT will continue to cause page faults.
952 */
953 ASMReloadCR3();
954 PGMDynUnlockHCPage(pVM, (uint8_t *)pPdpe);
955# endif
956 }
957 else
958 {
959 pShwPage = pgmPoolGetPage(pPool, pPdpe->u & X86_PDPE_PG_MASK);
960 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
961 Assert((pPdpe->u & X86_PDPE_PG_MASK) == pShwPage->Core.Key);
962
963 pgmPoolCacheUsed(pPool, pShwPage);
964 }
965 *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
966 return VINF_SUCCESS;
967}
968
969
970/**
971 * Gets the pointer to the shadow page directory entry for an address, PAE.
972 *
973 * @returns Pointer to the PDE.
974 * @param pPGM Pointer to the PGMCPU instance data.
975 * @param GCPtr The address.
976 * @param ppShwPde Receives the address of the pgm pool page for the shadow page directory
977 */
978DECLINLINE(int) pgmShwGetPaePoolPagePD(PPGMCPU pPGM, RTGCPTR GCPtr, PPGMPOOLPAGE *ppShwPde)
979{
980 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
981 PX86PDPT pPdpt = pgmShwGetPaePDPTPtr(pPGM);
982
983 Assert(PGMIsLockOwner(PGMCPU2VM(pPGM)));
984
985 AssertReturn(pPdpt, VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT); /* can't happen */
986 if (!pPdpt->a[iPdPt].n.u1Present)
987 {
988 LogFlow(("pgmShwGetPaePoolPagePD: PD %d not present (%RX64)\n", iPdPt, pPdpt->a[iPdPt].u));
989 return VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT;
990 }
991 AssertMsg(pPdpt->a[iPdPt].u & X86_PDPE_PG_MASK, ("GCPtr=%RGv\n", GCPtr));
992
993 /* Fetch the pgm pool shadow descriptor. */
994 PPGMPOOLPAGE pShwPde = pgmPoolGetPage(PGMCPU2PGM(pPGM)->CTX_SUFF(pPool), pPdpt->a[iPdPt].u & X86_PDPE_PG_MASK);
995 AssertReturn(pShwPde, VERR_INTERNAL_ERROR);
996
997 *ppShwPde = pShwPde;
998 return VINF_SUCCESS;
999}
1000
1001#ifndef IN_RC
1002
1003/**
1004 * Syncs the SHADOW page directory pointer for the specified address.
1005 *
1006 * Allocates backing pages in case the PDPT or PML4 entry is missing.
1007 *
1008 * The caller is responsible for making sure the guest has a valid PD before
1009 * calling this function.
1010 *
1011 * @returns VBox status.
1012 * @param pVCpu VMCPU handle.
1013 * @param GCPtr The address.
1014 * @param pGstPml4e Guest PML4 entry
1015 * @param pGstPdpe Guest PDPT entry
1016 * @param ppPD Receives address of page directory
1017 */
1018int pgmShwSyncLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PX86PML4E pGstPml4e, PX86PDPE pGstPdpe, PX86PDPAE *ppPD)
1019{
1020 PPGMCPU pPGM = &pVCpu->pgm.s;
1021 PVM pVM = pVCpu->CTX_SUFF(pVM);
1022 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1023 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
1024 PX86PML4E pPml4e = pgmShwGetLongModePML4EPtr(pPGM, iPml4);
1025 bool fNestedPaging = HWACCMIsNestedPagingActive(pVM);
1026 bool fPaging = !!(CPUMGetGuestCR0(pVCpu) & X86_CR0_PG);
1027 PPGMPOOLPAGE pShwPage;
1028 int rc;
1029
1030 Assert(PGMIsLockOwner(pVM));
1031
1032 /* Allocate page directory pointer table if not present. */
1033 if ( !pPml4e->n.u1Present
1034 && !(pPml4e->u & X86_PML4E_PG_MASK))
1035 {
1036 RTGCPTR64 GCPml4;
1037 PGMPOOLKIND enmKind;
1038
1039 Assert(pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
1040
1041 if (fNestedPaging || !fPaging)
1042 {
1043 /* AMD-V nested paging or real/protected mode without paging */
1044 GCPml4 = (RTGCPTR64)iPml4 << X86_PML4_SHIFT;
1045 enmKind = PGMPOOLKIND_64BIT_PDPT_FOR_PHYS;
1046 }
1047 else
1048 {
1049 Assert(pGstPml4e && pGstPdpe);
1050
1051 GCPml4 = pGstPml4e->u & X86_PML4E_PG_MASK;
1052 enmKind = PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT;
1053 }
1054
1055 /* Create a reference back to the PDPT by using the index in its shadow page. */
1056 rc = pgmPoolAlloc(pVM, GCPml4, enmKind, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPml4, &pShwPage);
1057 AssertRCReturn(rc, rc);
1058 }
1059 else
1060 {
1061 pShwPage = pgmPoolGetPage(pPool, pPml4e->u & X86_PML4E_PG_MASK);
1062 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1063
1064 pgmPoolCacheUsed(pPool, pShwPage);
1065 }
1066 /* The PDPT was cached or created; hook it up now. */
1067 pPml4e->u |= pShwPage->Core.Key
1068 | (pGstPml4e->u & ~(X86_PML4E_PG_MASK | X86_PML4E_AVL_MASK | X86_PML4E_PCD | X86_PML4E_PWT));
1069
1070 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1071 PX86PDPT pPdpt = (PX86PDPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1072 PX86PDPE pPdpe = &pPdpt->a[iPdPt];
1073
1074 /* Allocate page directory if not present. */
1075 if ( !pPdpe->n.u1Present
1076 && !(pPdpe->u & X86_PDPE_PG_MASK))
1077 {
1078 RTGCPTR64 GCPdPt;
1079 PGMPOOLKIND enmKind;
1080
1081 if (fNestedPaging || !fPaging)
1082 {
1083 /* AMD-V nested paging or real/protected mode without paging */
1084 GCPdPt = (RTGCPTR64)iPdPt << X86_PDPT_SHIFT;
1085 enmKind = PGMPOOLKIND_64BIT_PD_FOR_PHYS;
1086 }
1087 else
1088 {
1089 Assert(pGstPdpe);
1090
1091 GCPdPt = pGstPdpe->u & X86_PDPE_PG_MASK;
1092 enmKind = PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD;
1093 }
1094
1095 /* Create a reference back to the PDPT by using the index in its shadow page. */
1096 rc = pgmPoolAlloc(pVM, GCPdPt, enmKind, pShwPage->idx, iPdPt, &pShwPage);
1097 AssertRCReturn(rc, rc);
1098 }
1099 else
1100 {
1101 pShwPage = pgmPoolGetPage(pPool, pPdpe->u & X86_PDPE_PG_MASK);
1102 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1103
1104 pgmPoolCacheUsed(pPool, pShwPage);
1105 }
1106 /* The PD was cached or created; hook it up now. */
1107 pPdpe->u |= pShwPage->Core.Key
1108 | (pGstPdpe->u & ~(X86_PDPE_PG_MASK | X86_PDPE_AVL_MASK | X86_PDPE_PCD | X86_PDPE_PWT));
1109
1110 *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1111 return VINF_SUCCESS;
1112}
1113
1114
1115/**
1116 * Gets the SHADOW page directory pointer for the specified address (long mode).
1117 *
1118 * @returns VBox status.
1119 * @param pVCpu VMCPU handle.
1120 * @param GCPtr The address.
1121 * @param ppPdpt Receives address of pdpt
1122 * @param ppPD Receives address of page directory
1123 */
1124DECLINLINE(int) pgmShwGetLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPT *ppPdpt, PX86PDPAE *ppPD)
1125{
1126 PPGMCPU pPGM = &pVCpu->pgm.s;
1127 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
1128 PCX86PML4E pPml4e = pgmShwGetLongModePML4EPtr(pPGM, iPml4);
1129
1130 Assert(PGMIsLockOwner(PGMCPU2VM(pPGM)));
1131
1132 AssertReturn(pPml4e, VERR_INTERNAL_ERROR);
1133 if (ppPml4e)
1134 *ppPml4e = (PX86PML4E)pPml4e;
1135
1136 Log4(("pgmShwGetLongModePDPtr %VGv (%VHv) %RX64\n", GCPtr, pPml4e, pPml4e->u));
1137
1138 if (!pPml4e->n.u1Present)
1139 return VERR_PAGE_MAP_LEVEL4_NOT_PRESENT;
1140
1141 PVM pVM = pVCpu->CTX_SUFF(pVM);
1142 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1143 PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPml4e->u & X86_PML4E_PG_MASK);
1144 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1145
1146 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1147 PCX86PDPT pPdpt = *ppPdpt = (PX86PDPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1148 if (!pPdpt->a[iPdPt].n.u1Present)
1149 return VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT;
1150
1151 pShwPage = pgmPoolGetPage(pPool, pPdpt->a[iPdPt].u & X86_PDPE_PG_MASK);
1152 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1153
1154 *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1155 return VINF_SUCCESS;
1156}
1157
1158
1159/**
1160 * Syncs the SHADOW EPT page directory pointer for the specified address. Allocates
1161 * backing pages in case the PDPT or PML4 entry is missing.
1162 *
1163 * @returns VBox status.
1164 * @param pVCpu VMCPU handle.
1165 * @param GCPtr The address.
1166 * @param ppPdpt Receives address of pdpt
1167 * @param ppPD Receives address of page directory
1168 */
1169int pgmShwGetEPTPDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PEPTPDPT *ppPdpt, PEPTPD *ppPD)
1170{
1171 PPGMCPU pPGM = &pVCpu->pgm.s;
1172 PVM pVM = pVCpu->CTX_SUFF(pVM);
1173 const unsigned iPml4 = (GCPtr >> EPT_PML4_SHIFT) & EPT_PML4_MASK;
1174 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1175 PEPTPML4 pPml4;
1176 PEPTPML4E pPml4e;
1177 PPGMPOOLPAGE pShwPage;
1178 int rc;
1179
1180 Assert(HWACCMIsNestedPagingActive(pVM));
1181 Assert(PGMIsLockOwner(pVM));
1182
1183 pPml4 = (PEPTPML4)PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
1184 Assert(pPml4);
1185
1186 /* Allocate page directory pointer table if not present. */
1187 pPml4e = &pPml4->a[iPml4];
1188 if ( !pPml4e->n.u1Present
1189 && !(pPml4e->u & EPT_PML4E_PG_MASK))
1190 {
1191 Assert(!(pPml4e->u & EPT_PML4E_PG_MASK));
1192 RTGCPTR64 GCPml4 = (RTGCPTR64)iPml4 << EPT_PML4_SHIFT;
1193
1194 rc = pgmPoolAlloc(pVM, GCPml4, PGMPOOLKIND_EPT_PDPT_FOR_PHYS, PGMPOOL_IDX_NESTED_ROOT, iPml4, &pShwPage);
1195 AssertRCReturn(rc, rc);
1196 }
1197 else
1198 {
1199 pShwPage = pgmPoolGetPage(pPool, pPml4e->u & EPT_PML4E_PG_MASK);
1200 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1201
1202 pgmPoolCacheUsed(pPool, pShwPage);
1203 }
1204 /* The PDPT was cached or created; hook it up now and fill with the default value. */
1205 pPml4e->u = pShwPage->Core.Key;
1206 pPml4e->n.u1Present = 1;
1207 pPml4e->n.u1Write = 1;
1208 pPml4e->n.u1Execute = 1;
1209
1210 const unsigned iPdPt = (GCPtr >> EPT_PDPT_SHIFT) & EPT_PDPT_MASK;
1211 PEPTPDPT pPdpt = (PEPTPDPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1212 PEPTPDPTE pPdpe = &pPdpt->a[iPdPt];
1213
1214 if (ppPdpt)
1215 *ppPdpt = pPdpt;
1216
1217 /* Allocate page directory if not present. */
1218 if ( !pPdpe->n.u1Present
1219 && !(pPdpe->u & EPT_PDPTE_PG_MASK))
1220 {
1221 RTGCPTR64 GCPdPt = (RTGCPTR64)iPdPt << EPT_PDPT_SHIFT;
1222
1223 rc = pgmPoolAlloc(pVM, GCPdPt, PGMPOOLKIND_64BIT_PD_FOR_PHYS, pShwPage->idx, iPdPt, &pShwPage);
1224 AssertRCReturn(rc, rc);
1225 }
1226 else
1227 {
1228 pShwPage = pgmPoolGetPage(pPool, pPdpe->u & EPT_PDPTE_PG_MASK);
1229 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1230
1231 pgmPoolCacheUsed(pPool, pShwPage);
1232 }
1233 /* The PD was cached or created; hook it up now and fill with the default value. */
1234 pPdpe->u = pShwPage->Core.Key;
1235 pPdpe->n.u1Present = 1;
1236 pPdpe->n.u1Write = 1;
1237 pPdpe->n.u1Execute = 1;
1238
1239 *ppPD = (PEPTPD)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1240 return VINF_SUCCESS;
1241}
1242
1243#endif /* IN_RC */
1244
1245/**
1246 * Gets effective Guest OS page information.
1247 *
1248 * When GCPtr is in a big page, the function will return as if it was a normal
1249 * 4KB page. If the need for distinguishing between big and normal page becomes
1250 * necessary at a later point, a PGMGstGetPage() will be created for that
1251 * purpose.
1252 *
1253 * @returns VBox status.
1254 * @param pVCpu VMCPU handle.
1255 * @param GCPtr Guest Context virtual address of the page.
1256 * @param pfFlags Where to store the flags. These are X86_PTE_*, even for big pages.
1257 * @param pGCPhys Where to store the GC physical address of the page.
1258 * This is page aligned. The fact that the
1259 */
1260VMMDECL(int) PGMGstGetPage(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys)
1261{
1262 return PGM_GST_PFN(GetPage, pVCpu)(pVCpu, GCPtr, pfFlags, pGCPhys);
1263}
1264
1265
1266/**
1267 * Checks if the page is present.
1268 *
1269 * @returns true if the page is present.
1270 * @returns false if the page is not present.
1271 * @param pVCpu VMCPU handle.
1272 * @param GCPtr Address within the page.
1273 */
1274VMMDECL(bool) PGMGstIsPagePresent(PVMCPU pVCpu, RTGCPTR GCPtr)
1275{
1276 int rc = PGMGstGetPage(pVCpu, GCPtr, NULL, NULL);
1277 return RT_SUCCESS(rc);
1278}
1279
1280
1281/**
1282 * Sets (replaces) the page flags for a range of pages in the guest's tables.
1283 *
1284 * @returns VBox status.
1285 * @param pVCpu VMCPU handle.
1286 * @param GCPtr The address of the first page.
1287 * @param cb The size of the range in bytes.
1288 * @param fFlags Page flags X86_PTE_*, excluding the page mask of course.
1289 */
1290VMMDECL(int) PGMGstSetPage(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags)
1291{
1292 return PGMGstModifyPage(pVCpu, GCPtr, cb, fFlags, 0);
1293}
1294
1295
1296/**
1297 * Modify page flags for a range of pages in the guest's tables
1298 *
1299 * The existing flags are ANDed with the fMask and ORed with the fFlags.
1300 *
1301 * @returns VBox status code.
1302 * @param pVCpu VMCPU handle.
1303 * @param GCPtr Virtual address of the first page in the range.
1304 * @param cb Size (in bytes) of the range to apply the modification to.
1305 * @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
1306 * @param fMask The AND mask - page flags X86_PTE_*, excluding the page mask of course.
1307 * Be very CAREFUL when ~'ing constants which could be 32-bit!
1308 */
1309VMMDECL(int) PGMGstModifyPage(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
1310{
1311 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_MID_Z(Stat,GstModifyPage), a);
1312
1313 /*
1314 * Validate input.
1315 */
1316 AssertMsg(!(fFlags & X86_PTE_PAE_PG_MASK), ("fFlags=%#llx\n", fFlags));
1317 Assert(cb);
1318
1319 LogFlow(("PGMGstModifyPage %RGv %d bytes fFlags=%08llx fMask=%08llx\n", GCPtr, cb, fFlags, fMask));
1320
1321 /*
1322 * Adjust input.
1323 */
1324 cb += GCPtr & PAGE_OFFSET_MASK;
1325 cb = RT_ALIGN_Z(cb, PAGE_SIZE);
1326 GCPtr = (GCPtr & PAGE_BASE_GC_MASK);
1327
1328 /*
1329 * Call worker.
1330 */
1331 int rc = PGM_GST_PFN(ModifyPage, pVCpu)(pVCpu, GCPtr, cb, fFlags, fMask);
1332
1333 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,GstModifyPage), a);
1334 return rc;
1335}
1336
1337#ifdef IN_RING3
1338
1339/**
1340 * Performs the lazy mapping of the 32-bit guest PD.
1341 *
1342 * @returns Pointer to the mapping.
1343 * @param pPGM The PGM instance data.
1344 */
1345PX86PD pgmGstLazyMap32BitPD(PPGMCPU pPGM)
1346{
1347 Assert(!pPGM->CTX_SUFF(pGst32BitPd));
1348 PVM pVM = PGMCPU2VM(pPGM);
1349 pgmLock(pVM);
1350
1351 PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, pPGM->GCPhysCR3);
1352 AssertReturn(pPage, NULL);
1353
1354 RTHCPTR HCPtrGuestCR3;
1355 int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, pPGM->GCPhysCR3 & X86_CR3_PAGE_MASK, (void **)&HCPtrGuestCR3);
1356 AssertRCReturn(rc, NULL);
1357
1358 pPGM->pGst32BitPdR3 = (R3PTRTYPE(PX86PD))HCPtrGuestCR3;
1359# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1360 pPGM->pGst32BitPdR0 = (R0PTRTYPE(PX86PD))HCPtrGuestCR3;
1361# endif
1362
1363 pgmUnlock(pVM);
1364 return pPGM->CTX_SUFF(pGst32BitPd);
1365}
1366
1367
1368/**
1369 * Performs the lazy mapping of the PAE guest PDPT.
1370 *
1371 * @returns Pointer to the mapping.
1372 * @param pPGM The PGM instance data.
1373 */
1374PX86PDPT pgmGstLazyMapPaePDPT(PPGMCPU pPGM)
1375{
1376 Assert(!pPGM->CTX_SUFF(pGstPaePdpt));
1377 PVM pVM = PGMCPU2VM(pPGM);
1378 pgmLock(pVM);
1379
1380 PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, pPGM->GCPhysCR3);
1381 AssertReturn(pPage, NULL);
1382
1383 RTHCPTR HCPtrGuestCR3;
1384 int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, pPGM->GCPhysCR3 & X86_CR3_PAE_PAGE_MASK, (void **)&HCPtrGuestCR3); /** @todo r=bird: This GCPhysR3 masking isn't necessary. */
1385 AssertRCReturn(rc, NULL);
1386
1387 pPGM->pGstPaePdptR3 = (R3PTRTYPE(PX86PDPT))HCPtrGuestCR3;
1388# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1389 pPGM->pGstPaePdptR0 = (R0PTRTYPE(PX86PDPT))HCPtrGuestCR3;
1390# endif
1391
1392 pgmUnlock(pVM);
1393 return pPGM->CTX_SUFF(pGstPaePdpt);
1394}
1395
1396#endif /* IN_RING3 */
1397
1398#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
1399/**
1400 * Performs the lazy mapping / updating of a PAE guest PD.
1401 *
1402 * @returns Pointer to the mapping.
1403 * @param pPGM The PGM instance data.
1404 * @param iPdpt Which PD entry to map (0..3).
1405 */
1406PX86PDPAE pgmGstLazyMapPaePD(PPGMCPU pPGM, uint32_t iPdpt)
1407{
1408 PVM pVM = PGMCPU2VM(pPGM);
1409 pgmLock(pVM);
1410
1411 PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
1412 Assert(pGuestPDPT);
1413 Assert(pGuestPDPT->a[iPdpt].n.u1Present);
1414 RTGCPHYS GCPhys = pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK;
1415 bool const fChanged = pPGM->aGCPhysGstPaePDs[iPdpt] != GCPhys;
1416
1417 PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, GCPhys);
1418 if (RT_LIKELY(pPage))
1419 {
1420 int rc = VINF_SUCCESS;
1421 RTRCPTR RCPtr = NIL_RTRCPTR;
1422 RTHCPTR HCPtr = NIL_RTHCPTR;
1423#if !defined(IN_RC) && !defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1424 rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, &HCPtr);
1425 AssertRC(rc);
1426#endif
1427 if (RT_SUCCESS(rc) && fChanged)
1428 {
1429 RCPtr = (RTRCPTR)(RTRCUINTPTR)(pVM->pgm.s.GCPtrCR3Mapping + (1 + iPdpt) * PAGE_SIZE);
1430 rc = PGMMap(pVM, (RTRCUINTPTR)RCPtr, PGM_PAGE_GET_HCPHYS(pPage), PAGE_SIZE, 0);
1431 }
1432 if (RT_SUCCESS(rc))
1433 {
1434 pPGM->apGstPaePDsR3[iPdpt] = (R3PTRTYPE(PX86PDPAE))HCPtr;
1435# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1436 pPGM->apGstPaePDsR0[iPdpt] = (R0PTRTYPE(PX86PDPAE))HCPtr;
1437# endif
1438 if (fChanged)
1439 {
1440 pPGM->aGCPhysGstPaePDs[iPdpt] = GCPhys;
1441 pPGM->apGstPaePDsRC[iPdpt] = (RCPTRTYPE(PX86PDPAE))RCPtr;
1442 }
1443
1444 pgmUnlock(pVM);
1445 return pPGM->CTX_SUFF(apGstPaePDs)[iPdpt];
1446 }
1447 }
1448
1449 /* Invalid page or some failure, invalidate the entry. */
1450 pPGM->aGCPhysGstPaePDs[iPdpt] = NIL_RTGCPHYS;
1451 pPGM->apGstPaePDsR3[iPdpt] = 0;
1452# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1453 pPGM->apGstPaePDsR0[iPdpt] = 0;
1454# endif
1455 pPGM->apGstPaePDsRC[iPdpt] = 0;
1456
1457 pgmUnlock(pVM);
1458 return NULL;
1459}
1460#endif /* !VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
1461
1462
1463#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R3
1464/**
1465 * Performs the lazy mapping of the 32-bit guest PD.
1466 *
1467 * @returns Pointer to the mapping.
1468 * @param pPGM The PGM instance data.
1469 */
1470PX86PML4 pgmGstLazyMapPml4(PPGMCPU pPGM)
1471{
1472 Assert(!pPGM->CTX_SUFF(pGstAmd64Pml4));
1473 PVM pVM = PGMCPU2VM(pPGM);
1474 pgmLock(pVM);
1475
1476 PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, pPGM->GCPhysCR3);
1477 AssertReturn(pPage, NULL);
1478
1479 RTHCPTR HCPtrGuestCR3;
1480 int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, pPGM->GCPhysCR3 & X86_CR3_AMD64_PAGE_MASK, (void **)&HCPtrGuestCR3); /** @todo r=bird: This GCPhysCR3 masking isn't necessary. */
1481 AssertRCReturn(rc, NULL);
1482
1483 pPGM->pGstAmd64Pml4R3 = (R3PTRTYPE(PX86PML4))HCPtrGuestCR3;
1484# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1485 pPGM->pGstAmd64Pml4R0 = (R0PTRTYPE(PX86PML4))HCPtrGuestCR3;
1486# endif
1487
1488 pgmUnlock(pVM);
1489 return pPGM->CTX_SUFF(pGstAmd64Pml4);
1490}
1491#endif /* VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R3 */
1492
1493
1494/**
1495 * Gets the specified page directory pointer table entry.
1496 *
1497 * @returns PDP entry
1498 * @param pVCpu VMCPU handle.
1499 * @param iPdpt PDPT index
1500 */
1501VMMDECL(X86PDPE) PGMGstGetPaePDPtr(PVMCPU pVCpu, unsigned iPdpt)
1502{
1503 Assert(iPdpt <= 3);
1504 return pgmGstGetPaePDPTPtr(&pVCpu->pgm.s)->a[iPdpt & 3];
1505}
1506
1507
1508/**
1509 * Gets the current CR3 register value for the shadow memory context.
1510 * @returns CR3 value.
1511 * @param pVCpu VMCPU handle.
1512 */
1513VMMDECL(RTHCPHYS) PGMGetHyperCR3(PVMCPU pVCpu)
1514{
1515 PPGMPOOLPAGE pPoolPage = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
1516 AssertPtrReturn(pPoolPage, 0);
1517 return pPoolPage->Core.Key;
1518}
1519
1520
1521/**
1522 * Gets the current CR3 register value for the nested memory context.
1523 * @returns CR3 value.
1524 * @param pVCpu VMCPU handle.
1525 */
1526VMMDECL(RTHCPHYS) PGMGetNestedCR3(PVMCPU pVCpu, PGMMODE enmShadowMode)
1527{
1528 Assert(pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
1529 return pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->Core.Key;
1530}
1531
1532
1533/**
1534 * Gets the current CR3 register value for the HC intermediate memory context.
1535 * @returns CR3 value.
1536 * @param pVM The VM handle.
1537 */
1538VMMDECL(RTHCPHYS) PGMGetInterHCCR3(PVM pVM)
1539{
1540 switch (pVM->pgm.s.enmHostMode)
1541 {
1542 case SUPPAGINGMODE_32_BIT:
1543 case SUPPAGINGMODE_32_BIT_GLOBAL:
1544 return pVM->pgm.s.HCPhysInterPD;
1545
1546 case SUPPAGINGMODE_PAE:
1547 case SUPPAGINGMODE_PAE_GLOBAL:
1548 case SUPPAGINGMODE_PAE_NX:
1549 case SUPPAGINGMODE_PAE_GLOBAL_NX:
1550 return pVM->pgm.s.HCPhysInterPaePDPT;
1551
1552 case SUPPAGINGMODE_AMD64:
1553 case SUPPAGINGMODE_AMD64_GLOBAL:
1554 case SUPPAGINGMODE_AMD64_NX:
1555 case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1556 return pVM->pgm.s.HCPhysInterPaePDPT;
1557
1558 default:
1559 AssertMsgFailed(("enmHostMode=%d\n", pVM->pgm.s.enmHostMode));
1560 return ~0;
1561 }
1562}
1563
1564
1565/**
1566 * Gets the current CR3 register value for the RC intermediate memory context.
1567 * @returns CR3 value.
1568 * @param pVM The VM handle.
1569 * @param pVCpu VMCPU handle.
1570 */
1571VMMDECL(RTHCPHYS) PGMGetInterRCCR3(PVM pVM, PVMCPU pVCpu)
1572{
1573 switch (pVCpu->pgm.s.enmShadowMode)
1574 {
1575 case PGMMODE_32_BIT:
1576 return pVM->pgm.s.HCPhysInterPD;
1577
1578 case PGMMODE_PAE:
1579 case PGMMODE_PAE_NX:
1580 return pVM->pgm.s.HCPhysInterPaePDPT;
1581
1582 case PGMMODE_AMD64:
1583 case PGMMODE_AMD64_NX:
1584 return pVM->pgm.s.HCPhysInterPaePML4;
1585
1586 case PGMMODE_EPT:
1587 case PGMMODE_NESTED:
1588 return 0; /* not relevant */
1589
1590 default:
1591 AssertMsgFailed(("enmShadowMode=%d\n", pVCpu->pgm.s.enmShadowMode));
1592 return ~0;
1593 }
1594}
1595
1596
1597/**
1598 * Gets the CR3 register value for the 32-Bit intermediate memory context.
1599 * @returns CR3 value.
1600 * @param pVM The VM handle.
1601 */
1602VMMDECL(RTHCPHYS) PGMGetInter32BitCR3(PVM pVM)
1603{
1604 return pVM->pgm.s.HCPhysInterPD;
1605}
1606
1607
1608/**
1609 * Gets the CR3 register value for the PAE intermediate memory context.
1610 * @returns CR3 value.
1611 * @param pVM The VM handle.
1612 */
1613VMMDECL(RTHCPHYS) PGMGetInterPaeCR3(PVM pVM)
1614{
1615 return pVM->pgm.s.HCPhysInterPaePDPT;
1616}
1617
1618
1619/**
1620 * Gets the CR3 register value for the AMD64 intermediate memory context.
1621 * @returns CR3 value.
1622 * @param pVM The VM handle.
1623 */
1624VMMDECL(RTHCPHYS) PGMGetInterAmd64CR3(PVM pVM)
1625{
1626 return pVM->pgm.s.HCPhysInterPaePML4;
1627}
1628
1629
1630/**
1631 * Performs and schedules necessary updates following a CR3 load or reload.
1632 *
1633 * This will normally involve mapping the guest PD or nPDPT
1634 *
1635 * @returns VBox status code.
1636 * @retval VINF_PGM_SYNC_CR3 if monitoring requires a CR3 sync. This can
1637 * safely be ignored and overridden since the FF will be set too then.
1638 * @param pVCpu VMCPU handle.
1639 * @param cr3 The new cr3.
1640 * @param fGlobal Indicates whether this is a global flush or not.
1641 */
1642VMMDECL(int) PGMFlushTLB(PVMCPU pVCpu, uint64_t cr3, bool fGlobal)
1643{
1644 PVM pVM = pVCpu->CTX_SUFF(pVM);
1645
1646 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_MID_Z(Stat,FlushTLB), a);
1647
1648 /*
1649 * Always flag the necessary updates; necessary for hardware acceleration
1650 */
1651 /** @todo optimize this, it shouldn't always be necessary. */
1652 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
1653 if (fGlobal)
1654 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
1655 LogFlow(("PGMFlushTLB: cr3=%RX64 OldCr3=%RX64 fGlobal=%d\n", cr3, pVCpu->pgm.s.GCPhysCR3, fGlobal));
1656
1657 /*
1658 * Remap the CR3 content and adjust the monitoring if CR3 was actually changed.
1659 */
1660 int rc = VINF_SUCCESS;
1661 RTGCPHYS GCPhysCR3;
1662 switch (pVCpu->pgm.s.enmGuestMode)
1663 {
1664 case PGMMODE_PAE:
1665 case PGMMODE_PAE_NX:
1666 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAE_PAGE_MASK);
1667 break;
1668 case PGMMODE_AMD64:
1669 case PGMMODE_AMD64_NX:
1670 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_AMD64_PAGE_MASK);
1671 break;
1672 default:
1673 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAGE_MASK);
1674 break;
1675 }
1676
1677 if (pVCpu->pgm.s.GCPhysCR3 != GCPhysCR3)
1678 {
1679 RTGCPHYS GCPhysOldCR3 = pVCpu->pgm.s.GCPhysCR3;
1680 pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3;
1681 rc = PGM_BTH_PFN(MapCR3, pVCpu)(pVCpu, GCPhysCR3);
1682 if (RT_LIKELY(rc == VINF_SUCCESS))
1683 {
1684 if (!pVM->pgm.s.fMappingsFixed)
1685 {
1686 pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
1687 }
1688 }
1689 else
1690 {
1691 AssertMsg(rc == VINF_PGM_SYNC_CR3, ("%Rrc\n", rc));
1692 Assert(VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL | VMCPU_FF_PGM_SYNC_CR3));
1693 pVCpu->pgm.s.GCPhysCR3 = GCPhysOldCR3;
1694 pVCpu->pgm.s.fSyncFlags |= PGM_SYNC_MAP_CR3;
1695 if (!pVM->pgm.s.fMappingsFixed)
1696 pVCpu->pgm.s.fSyncFlags |= PGM_SYNC_MONITOR_CR3;
1697 }
1698
1699 if (fGlobal)
1700 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,FlushTLBNewCR3Global));
1701 else
1702 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,FlushTLBNewCR3));
1703 }
1704 else
1705 {
1706# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
1707 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1708 if (pPool->cDirtyPages)
1709 {
1710 pgmLock(pVM);
1711 pgmPoolResetDirtyPages(pVM);
1712 pgmUnlock(pVM);
1713 }
1714# endif
1715 /*
1716 * Check if we have a pending update of the CR3 monitoring.
1717 */
1718 if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
1719 {
1720 pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
1721 Assert(!pVM->pgm.s.fMappingsFixed);
1722 }
1723 if (fGlobal)
1724 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,FlushTLBSameCR3Global));
1725 else
1726 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,FlushTLBSameCR3));
1727 }
1728
1729 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,FlushTLB), a);
1730 return rc;
1731}
1732
1733
1734/**
1735 * Performs and schedules necessary updates following a CR3 load or reload when
1736 * using nested or extended paging.
1737 *
1738 * This API is an alterantive to PDMFlushTLB that avoids actually flushing the
1739 * TLB and triggering a SyncCR3.
1740 *
1741 * This will normally involve mapping the guest PD or nPDPT
1742 *
1743 * @returns VBox status code.
1744 * @retval VINF_SUCCESS.
1745 * @retval (If applied when not in nested mode: VINF_PGM_SYNC_CR3 if monitoring
1746 * requires a CR3 sync. This can safely be ignored and overridden since
1747 * the FF will be set too then.)
1748 * @param pVCpu VMCPU handle.
1749 * @param cr3 The new cr3.
1750 */
1751VMMDECL(int) PGMUpdateCR3(PVMCPU pVCpu, uint64_t cr3)
1752{
1753 PVM pVM = pVCpu->CTX_SUFF(pVM);
1754
1755 LogFlow(("PGMUpdateCR3: cr3=%RX64 OldCr3=%RX64\n", cr3, pVCpu->pgm.s.GCPhysCR3));
1756
1757 /* We assume we're only called in nested paging mode. */
1758 Assert(pVM->pgm.s.fMappingsFixed);
1759 Assert(!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3));
1760 Assert(HWACCMIsNestedPagingActive(pVM) || pVCpu->pgm.s.enmShadowMode == PGMMODE_EPT);
1761
1762 /*
1763 * Remap the CR3 content and adjust the monitoring if CR3 was actually changed.
1764 */
1765 int rc = VINF_SUCCESS;
1766 RTGCPHYS GCPhysCR3;
1767 switch (pVCpu->pgm.s.enmGuestMode)
1768 {
1769 case PGMMODE_PAE:
1770 case PGMMODE_PAE_NX:
1771 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAE_PAGE_MASK);
1772 break;
1773 case PGMMODE_AMD64:
1774 case PGMMODE_AMD64_NX:
1775 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_AMD64_PAGE_MASK);
1776 break;
1777 default:
1778 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAGE_MASK);
1779 break;
1780 }
1781 if (pVCpu->pgm.s.GCPhysCR3 != GCPhysCR3)
1782 {
1783 pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3;
1784 rc = PGM_BTH_PFN(MapCR3, pVCpu)(pVCpu, GCPhysCR3);
1785 AssertRCSuccess(rc); /* Assumes VINF_PGM_SYNC_CR3 doesn't apply to nested paging. */ /** @todo this isn't true for the mac, but we need hw to test/fix this. */
1786 }
1787 return rc;
1788}
1789
1790
1791/**
1792 * Synchronize the paging structures.
1793 *
1794 * This function is called in response to the VM_FF_PGM_SYNC_CR3 and
1795 * VM_FF_PGM_SYNC_CR3_NONGLOBAL. Those two force action flags are set
1796 * in several places, most importantly whenever the CR3 is loaded.
1797 *
1798 * @returns VBox status code.
1799 * @param pVCpu VMCPU handle.
1800 * @param cr0 Guest context CR0 register
1801 * @param cr3 Guest context CR3 register
1802 * @param cr4 Guest context CR4 register
1803 * @param fGlobal Including global page directories or not
1804 */
1805VMMDECL(int) PGMSyncCR3(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
1806{
1807 PVM pVM = pVCpu->CTX_SUFF(pVM);
1808 int rc;
1809
1810#ifdef PGMPOOL_WITH_MONITORING
1811 /*
1812 * The pool may have pending stuff and even require a return to ring-3 to
1813 * clear the whole thing.
1814 */
1815 rc = pgmPoolSyncCR3(pVCpu);
1816 if (rc != VINF_SUCCESS)
1817 return rc;
1818#endif
1819
1820 /*
1821 * We might be called when we shouldn't.
1822 *
1823 * The mode switching will ensure that the PD is resynced
1824 * after every mode switch. So, if we find ourselves here
1825 * when in protected or real mode we can safely disable the
1826 * FF and return immediately.
1827 */
1828 if (pVCpu->pgm.s.enmGuestMode <= PGMMODE_PROTECTED)
1829 {
1830 Assert((cr0 & (X86_CR0_PG | X86_CR0_PE)) != (X86_CR0_PG | X86_CR0_PE));
1831 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
1832 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
1833 return VINF_SUCCESS;
1834 }
1835
1836 /* If global pages are not supported, then all flushes are global. */
1837 if (!(cr4 & X86_CR4_PGE))
1838 fGlobal = true;
1839 LogFlow(("PGMSyncCR3: cr0=%RX64 cr3=%RX64 cr4=%RX64 fGlobal=%d[%d,%d]\n", cr0, cr3, cr4, fGlobal,
1840 VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3), VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)));
1841
1842 /*
1843 * Check if we need to finish an aborted MapCR3 call (see PGMFlushTLB).
1844 * This should be done before SyncCR3.
1845 */
1846 if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MAP_CR3)
1847 {
1848 pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MAP_CR3;
1849
1850 RTGCPHYS GCPhysCR3Old = pVCpu->pgm.s.GCPhysCR3;
1851 RTGCPHYS GCPhysCR3;
1852 switch (pVCpu->pgm.s.enmGuestMode)
1853 {
1854 case PGMMODE_PAE:
1855 case PGMMODE_PAE_NX:
1856 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAE_PAGE_MASK);
1857 break;
1858 case PGMMODE_AMD64:
1859 case PGMMODE_AMD64_NX:
1860 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_AMD64_PAGE_MASK);
1861 break;
1862 default:
1863 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAGE_MASK);
1864 break;
1865 }
1866
1867 if (pVCpu->pgm.s.GCPhysCR3 != GCPhysCR3)
1868 {
1869 pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3;
1870 rc = PGM_BTH_PFN(MapCR3, pVCpu)(pVCpu, GCPhysCR3);
1871 }
1872#ifdef IN_RING3
1873 if (rc == VINF_PGM_SYNC_CR3)
1874 rc = pgmPoolSyncCR3(pVCpu);
1875#else
1876 if (rc == VINF_PGM_SYNC_CR3)
1877 {
1878 pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3Old;
1879 return rc;
1880 }
1881#endif
1882 AssertRCReturn(rc, rc);
1883 AssertRCSuccessReturn(rc, VERR_INTERNAL_ERROR);
1884 }
1885
1886 /*
1887 * Let the 'Bth' function do the work and we'll just keep track of the flags.
1888 */
1889 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncCR3), a);
1890 rc = PGM_BTH_PFN(SyncCR3, pVCpu)(pVCpu, cr0, cr3, cr4, fGlobal);
1891 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncCR3), a);
1892 AssertMsg(rc == VINF_SUCCESS || rc == VINF_PGM_SYNC_CR3 || RT_FAILURE(rc), ("rc=%Rrc\n", rc));
1893 if (rc == VINF_SUCCESS)
1894 {
1895 if (!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS))
1896 {
1897 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
1898 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
1899 }
1900
1901 /*
1902 * Check if we have a pending update of the CR3 monitoring.
1903 */
1904 if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
1905 {
1906 pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
1907 Assert(!pVM->pgm.s.fMappingsFixed);
1908 }
1909 }
1910
1911 /*
1912 * Now flush the CR3 (guest context).
1913 */
1914 if (rc == VINF_SUCCESS)
1915 PGM_INVL_VCPU_TLBS(pVCpu);
1916 return rc;
1917}
1918
1919
1920/**
1921 * Called whenever CR0 or CR4 in a way which may change
1922 * the paging mode.
1923 *
1924 * @returns VBox status code, with the following informational code for
1925 * VM scheduling.
1926 * @retval VINF_SUCCESS if the was no change, or it was successfully dealt with.
1927 * @retval VINF_PGM_CHANGE_MODE if we're in RC or R0 and the mode changes.
1928 * (I.e. not in R3.)
1929 * @retval VINF_EM_SUSPEND or VINF_EM_OFF on a fatal runtime error. (R3 only)
1930 *
1931 * @param pVCpu VMCPU handle.
1932 * @param cr0 The new cr0.
1933 * @param cr4 The new cr4.
1934 * @param efer The new extended feature enable register.
1935 */
1936VMMDECL(int) PGMChangeMode(PVMCPU pVCpu, uint64_t cr0, uint64_t cr4, uint64_t efer)
1937{
1938 PVM pVM = pVCpu->CTX_SUFF(pVM);
1939 PGMMODE enmGuestMode;
1940
1941 /*
1942 * Calc the new guest mode.
1943 */
1944 if (!(cr0 & X86_CR0_PE))
1945 enmGuestMode = PGMMODE_REAL;
1946 else if (!(cr0 & X86_CR0_PG))
1947 enmGuestMode = PGMMODE_PROTECTED;
1948 else if (!(cr4 & X86_CR4_PAE))
1949 enmGuestMode = PGMMODE_32_BIT;
1950 else if (!(efer & MSR_K6_EFER_LME))
1951 {
1952 if (!(efer & MSR_K6_EFER_NXE))
1953 enmGuestMode = PGMMODE_PAE;
1954 else
1955 enmGuestMode = PGMMODE_PAE_NX;
1956 }
1957 else
1958 {
1959 if (!(efer & MSR_K6_EFER_NXE))
1960 enmGuestMode = PGMMODE_AMD64;
1961 else
1962 enmGuestMode = PGMMODE_AMD64_NX;
1963 }
1964
1965 /*
1966 * Did it change?
1967 */
1968 if (pVCpu->pgm.s.enmGuestMode == enmGuestMode)
1969 return VINF_SUCCESS;
1970
1971 /* Flush the TLB */
1972 PGM_INVL_VCPU_TLBS(pVCpu);
1973
1974#ifdef IN_RING3
1975 return PGMR3ChangeMode(pVM, pVCpu, enmGuestMode);
1976#else
1977 LogFlow(("PGMChangeMode: returns VINF_PGM_CHANGE_MODE.\n"));
1978 return VINF_PGM_CHANGE_MODE;
1979#endif
1980}
1981
1982
1983/**
1984 * Gets the current guest paging mode.
1985 *
1986 * If you just need the CPU mode (real/protected/long), use CPUMGetGuestMode().
1987 *
1988 * @returns The current paging mode.
1989 * @param pVCpu VMCPU handle.
1990 */
1991VMMDECL(PGMMODE) PGMGetGuestMode(PVMCPU pVCpu)
1992{
1993 return pVCpu->pgm.s.enmGuestMode;
1994}
1995
1996
1997/**
1998 * Gets the current shadow paging mode.
1999 *
2000 * @returns The current paging mode.
2001 * @param pVCpu VMCPU handle.
2002 */
2003VMMDECL(PGMMODE) PGMGetShadowMode(PVMCPU pVCpu)
2004{
2005 return pVCpu->pgm.s.enmShadowMode;
2006}
2007
2008/**
2009 * Gets the current host paging mode.
2010 *
2011 * @returns The current paging mode.
2012 * @param pVM The VM handle.
2013 */
2014VMMDECL(PGMMODE) PGMGetHostMode(PVM pVM)
2015{
2016 switch (pVM->pgm.s.enmHostMode)
2017 {
2018 case SUPPAGINGMODE_32_BIT:
2019 case SUPPAGINGMODE_32_BIT_GLOBAL:
2020 return PGMMODE_32_BIT;
2021
2022 case SUPPAGINGMODE_PAE:
2023 case SUPPAGINGMODE_PAE_GLOBAL:
2024 return PGMMODE_PAE;
2025
2026 case SUPPAGINGMODE_PAE_NX:
2027 case SUPPAGINGMODE_PAE_GLOBAL_NX:
2028 return PGMMODE_PAE_NX;
2029
2030 case SUPPAGINGMODE_AMD64:
2031 case SUPPAGINGMODE_AMD64_GLOBAL:
2032 return PGMMODE_AMD64;
2033
2034 case SUPPAGINGMODE_AMD64_NX:
2035 case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2036 return PGMMODE_AMD64_NX;
2037
2038 default: AssertMsgFailed(("enmHostMode=%d\n", pVM->pgm.s.enmHostMode)); break;
2039 }
2040
2041 return PGMMODE_INVALID;
2042}
2043
2044
2045/**
2046 * Get mode name.
2047 *
2048 * @returns read-only name string.
2049 * @param enmMode The mode which name is desired.
2050 */
2051VMMDECL(const char *) PGMGetModeName(PGMMODE enmMode)
2052{
2053 switch (enmMode)
2054 {
2055 case PGMMODE_REAL: return "Real";
2056 case PGMMODE_PROTECTED: return "Protected";
2057 case PGMMODE_32_BIT: return "32-bit";
2058 case PGMMODE_PAE: return "PAE";
2059 case PGMMODE_PAE_NX: return "PAE+NX";
2060 case PGMMODE_AMD64: return "AMD64";
2061 case PGMMODE_AMD64_NX: return "AMD64+NX";
2062 case PGMMODE_NESTED: return "Nested";
2063 case PGMMODE_EPT: return "EPT";
2064 default: return "unknown mode value";
2065 }
2066}
2067
2068
2069/**
2070 * Check if any pgm pool pages are marked dirty (not monitored)
2071 *
2072 * @returns bool locked/not locked
2073 * @param pVM The VM to operate on.
2074 */
2075VMMDECL(bool) PGMHasDirtyPages(PVM pVM)
2076{
2077 return pVM->pgm.s.CTX_SUFF(pPool)->cDirtyPages != 0;
2078}
2079
2080/**
2081 * Check if the PGM lock is currently taken.
2082 *
2083 * @returns bool locked/not locked
2084 * @param pVM The VM to operate on.
2085 */
2086VMMDECL(bool) PGMIsLocked(PVM pVM)
2087{
2088 return PDMCritSectIsOwned(&pVM->pgm.s.CritSect);
2089}
2090
2091
2092/**
2093 * Check if this VCPU currently owns the PGM lock.
2094 *
2095 * @returns bool owner/not owner
2096 * @param pVM The VM to operate on.
2097 */
2098VMMDECL(bool) PGMIsLockOwner(PVM pVM)
2099{
2100 return PDMCritSectIsOwner(&pVM->pgm.s.CritSect);
2101}
2102
2103
2104/**
2105 * Acquire the PGM lock.
2106 *
2107 * @returns VBox status code
2108 * @param pVM The VM to operate on.
2109 */
2110int pgmLock(PVM pVM)
2111{
2112 int rc = PDMCritSectEnter(&pVM->pgm.s.CritSect, VERR_SEM_BUSY);
2113#if defined(IN_RC) || defined(IN_RING0)
2114 if (rc == VERR_SEM_BUSY)
2115 rc = VMMRZCallRing3NoCpu(pVM, VMMCALLRING3_PGM_LOCK, 0);
2116#endif
2117 AssertMsg(rc == VINF_SUCCESS, ("%Rrc\n", rc));
2118 return rc;
2119}
2120
2121
2122/**
2123 * Release the PGM lock.
2124 *
2125 * @returns VBox status code
2126 * @param pVM The VM to operate on.
2127 */
2128void pgmUnlock(PVM pVM)
2129{
2130 PDMCritSectLeave(&pVM->pgm.s.CritSect);
2131}
2132
2133#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2134
2135/**
2136 * Temporarily maps one guest page specified by GC physical address.
2137 * These pages must have a physical mapping in HC, i.e. they cannot be MMIO pages.
2138 *
2139 * Be WARNED that the dynamic page mapping area is small, 8 pages, thus the space is
2140 * reused after 8 mappings (or perhaps a few more if you score with the cache).
2141 *
2142 * @returns VBox status.
2143 * @param pVM VM handle.
2144 * @param GCPhys GC Physical address of the page.
2145 * @param ppv Where to store the address of the mapping.
2146 */
2147VMMDECL(int) PGMDynMapGCPage(PVM pVM, RTGCPHYS GCPhys, void **ppv)
2148{
2149 AssertMsg(!(GCPhys & PAGE_OFFSET_MASK), ("GCPhys=%RGp\n", GCPhys));
2150
2151 /*
2152 * Get the ram range.
2153 */
2154 PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
2155 while (pRam && GCPhys - pRam->GCPhys >= pRam->cb)
2156 pRam = pRam->CTX_SUFF(pNext);
2157 if (!pRam)
2158 {
2159 AssertMsgFailed(("Invalid physical address %RGp!\n", GCPhys));
2160 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2161 }
2162
2163 /*
2164 * Pass it on to PGMDynMapHCPage.
2165 */
2166 RTHCPHYS HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT]);
2167 //Log(("PGMDynMapGCPage: GCPhys=%RGp HCPhys=%RHp\n", GCPhys, HCPhys));
2168#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2169 pgmR0DynMapHCPageInlined(&pVM->pgm.s, HCPhys, ppv);
2170#else
2171 PGMDynMapHCPage(pVM, HCPhys, ppv);
2172#endif
2173 return VINF_SUCCESS;
2174}
2175
2176
2177/**
2178 * Temporarily maps one guest page specified by unaligned GC physical address.
2179 * These pages must have a physical mapping in HC, i.e. they cannot be MMIO pages.
2180 *
2181 * Be WARNED that the dynamic page mapping area is small, 8 pages, thus the space is
2182 * reused after 8 mappings (or perhaps a few more if you score with the cache).
2183 *
2184 * The caller is aware that only the speicifed page is mapped and that really bad things
2185 * will happen if writing beyond the page!
2186 *
2187 * @returns VBox status.
2188 * @param pVM VM handle.
2189 * @param GCPhys GC Physical address within the page to be mapped.
2190 * @param ppv Where to store the address of the mapping address corresponding to GCPhys.
2191 */
2192VMMDECL(int) PGMDynMapGCPageOff(PVM pVM, RTGCPHYS GCPhys, void **ppv)
2193{
2194 /*
2195 * Get the ram range.
2196 */
2197 PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
2198 while (pRam && GCPhys - pRam->GCPhys >= pRam->cb)
2199 pRam = pRam->CTX_SUFF(pNext);
2200 if (!pRam)
2201 {
2202 AssertMsgFailed(("Invalid physical address %RGp!\n", GCPhys));
2203 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2204 }
2205
2206 /*
2207 * Pass it on to PGMDynMapHCPage.
2208 */
2209 RTHCPHYS HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT]);
2210#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2211 pgmR0DynMapHCPageInlined(&pVM->pgm.s, HCPhys, ppv);
2212#else
2213 PGMDynMapHCPage(pVM, HCPhys, ppv);
2214#endif
2215 *ppv = (void *)((uintptr_t)*ppv | (GCPhys & PAGE_OFFSET_MASK));
2216 return VINF_SUCCESS;
2217}
2218
2219# ifdef IN_RC
2220
2221/**
2222 * Temporarily maps one host page specified by HC physical address.
2223 *
2224 * Be WARNED that the dynamic page mapping area is small, 16 pages, thus the space is
2225 * reused after 16 mappings (or perhaps a few more if you score with the cache).
2226 *
2227 * @returns VINF_SUCCESS, will bail out to ring-3 on failure.
2228 * @param pVM VM handle.
2229 * @param HCPhys HC Physical address of the page.
2230 * @param ppv Where to store the address of the mapping. This is the
2231 * address of the PAGE not the exact address corresponding
2232 * to HCPhys. Use PGMDynMapHCPageOff if you care for the
2233 * page offset.
2234 */
2235VMMDECL(int) PGMDynMapHCPage(PVM pVM, RTHCPHYS HCPhys, void **ppv)
2236{
2237 AssertMsg(!(HCPhys & PAGE_OFFSET_MASK), ("HCPhys=%RHp\n", HCPhys));
2238
2239 /*
2240 * Check the cache.
2241 */
2242 register unsigned iCache;
2243 for (iCache = 0;iCache < RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache);iCache++)
2244 {
2245 static const uint8_t au8Trans[MM_HYPER_DYNAMIC_SIZE >> PAGE_SHIFT][RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache)] =
2246 {
2247 { 0, 9, 10, 11, 12, 13, 14, 15},
2248 { 0, 1, 10, 11, 12, 13, 14, 15},
2249 { 0, 1, 2, 11, 12, 13, 14, 15},
2250 { 0, 1, 2, 3, 12, 13, 14, 15},
2251 { 0, 1, 2, 3, 4, 13, 14, 15},
2252 { 0, 1, 2, 3, 4, 5, 14, 15},
2253 { 0, 1, 2, 3, 4, 5, 6, 15},
2254 { 0, 1, 2, 3, 4, 5, 6, 7},
2255 { 8, 1, 2, 3, 4, 5, 6, 7},
2256 { 8, 9, 2, 3, 4, 5, 6, 7},
2257 { 8, 9, 10, 3, 4, 5, 6, 7},
2258 { 8, 9, 10, 11, 4, 5, 6, 7},
2259 { 8, 9, 10, 11, 12, 5, 6, 7},
2260 { 8, 9, 10, 11, 12, 13, 6, 7},
2261 { 8, 9, 10, 11, 12, 13, 14, 7},
2262 { 8, 9, 10, 11, 12, 13, 14, 15},
2263 };
2264 AssertCompile(RT_ELEMENTS(au8Trans) == 16);
2265 AssertCompile(RT_ELEMENTS(au8Trans[0]) == 8);
2266
2267 if (pVM->pgm.s.aHCPhysDynPageMapCache[iCache] == HCPhys)
2268 {
2269 int iPage = au8Trans[pVM->pgm.s.iDynPageMapLast][iCache];
2270
2271 /* The cache can get out of sync with locked entries. (10 locked, 2 overwrites its cache position, last = 11, lookup 2 -> page 10 instead of 2) */
2272 if ((pVM->pgm.s.paDynPageMap32BitPTEsGC[iPage].u & X86_PTE_PG_MASK) == HCPhys)
2273 {
2274 void *pv = pVM->pgm.s.pbDynPageMapBaseGC + (iPage << PAGE_SHIFT);
2275 *ppv = pv;
2276 STAM_COUNTER_INC(&pVM->pgm.s.StatRCDynMapCacheHits);
2277 Log4(("PGMGCDynMapHCPage: HCPhys=%RHp pv=%p iPage=%d iCache=%d\n", HCPhys, pv, iPage, iCache));
2278 return VINF_SUCCESS;
2279 }
2280 LogFlow(("Out of sync entry %d\n", iPage));
2281 }
2282 }
2283 AssertCompile(RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache) == 8);
2284 AssertCompile((MM_HYPER_DYNAMIC_SIZE >> PAGE_SHIFT) == 16);
2285 STAM_COUNTER_INC(&pVM->pgm.s.StatRCDynMapCacheMisses);
2286
2287 /*
2288 * Update the page tables.
2289 */
2290 unsigned iPage = pVM->pgm.s.iDynPageMapLast;
2291 unsigned i;
2292 for (i = 0; i < (MM_HYPER_DYNAMIC_SIZE >> PAGE_SHIFT); i++)
2293 {
2294 pVM->pgm.s.iDynPageMapLast = iPage = (iPage + 1) & ((MM_HYPER_DYNAMIC_SIZE >> PAGE_SHIFT) - 1);
2295 if (!pVM->pgm.s.aLockedDynPageMapCache[iPage])
2296 break;
2297 iPage++;
2298 }
2299 AssertRelease(i != (MM_HYPER_DYNAMIC_SIZE >> PAGE_SHIFT));
2300
2301 pVM->pgm.s.aHCPhysDynPageMapCache[iPage & (RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache) - 1)] = HCPhys;
2302 pVM->pgm.s.paDynPageMap32BitPTEsGC[iPage].u = (uint32_t)HCPhys | X86_PTE_P | X86_PTE_A | X86_PTE_D;
2303 pVM->pgm.s.paDynPageMapPaePTEsGC[iPage].u = HCPhys | X86_PTE_P | X86_PTE_A | X86_PTE_D;
2304 pVM->pgm.s.aLockedDynPageMapCache[iPage] = 0;
2305
2306 void *pv = pVM->pgm.s.pbDynPageMapBaseGC + (iPage << PAGE_SHIFT);
2307 *ppv = pv;
2308 ASMInvalidatePage(pv);
2309 Log4(("PGMGCDynMapHCPage: HCPhys=%RHp pv=%p iPage=%d\n", HCPhys, pv, iPage));
2310 return VINF_SUCCESS;
2311}
2312
2313
2314/**
2315 * Temporarily lock a dynamic page to prevent it from being reused.
2316 *
2317 * @param pVM VM handle.
2318 * @param GCPage GC address of page
2319 */
2320VMMDECL(void) PGMDynLockHCPage(PVM pVM, RCPTRTYPE(uint8_t *) GCPage)
2321{
2322 unsigned iPage;
2323
2324 Assert(GCPage >= pVM->pgm.s.pbDynPageMapBaseGC && GCPage < (pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE));
2325 iPage = ((uintptr_t)(GCPage - pVM->pgm.s.pbDynPageMapBaseGC)) >> PAGE_SHIFT;
2326 ASMAtomicIncU32(&pVM->pgm.s.aLockedDynPageMapCache[iPage]);
2327 Log4(("PGMDynLockHCPage %RRv iPage=%d\n", GCPage, iPage));
2328}
2329
2330
2331/**
2332 * Unlock a dynamic page
2333 *
2334 * @param pVM VM handle.
2335 * @param GCPage GC address of page
2336 */
2337VMMDECL(void) PGMDynUnlockHCPage(PVM pVM, RCPTRTYPE(uint8_t *) GCPage)
2338{
2339 unsigned iPage;
2340
2341 AssertCompile(RT_ELEMENTS(pVM->pgm.s.aLockedDynPageMapCache) == 2* RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache));
2342 AssertCompileMemberSize(VM, pgm.s.aLockedDynPageMapCache, sizeof(uint32_t) * (MM_HYPER_DYNAMIC_SIZE >> (PAGE_SHIFT)));
2343
2344 Assert(GCPage >= pVM->pgm.s.pbDynPageMapBaseGC && GCPage < (pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE));
2345 iPage = ((uintptr_t)(GCPage - pVM->pgm.s.pbDynPageMapBaseGC)) >> PAGE_SHIFT;
2346 Assert(pVM->pgm.s.aLockedDynPageMapCache[iPage]);
2347 ASMAtomicDecU32(&pVM->pgm.s.aLockedDynPageMapCache[iPage]);
2348 Log4(("PGMDynUnlockHCPage %RRv iPage=%d\n", GCPage, iPage));
2349}
2350
2351
2352# ifdef VBOX_STRICT
2353/**
2354 * Check for lock leaks.
2355 *
2356 * @param pVM VM handle.
2357 */
2358VMMDECL(void) PGMDynCheckLocks(PVM pVM)
2359{
2360 for (unsigned i=0;i<RT_ELEMENTS(pVM->pgm.s.aLockedDynPageMapCache);i++)
2361 Assert(!pVM->pgm.s.aLockedDynPageMapCache[i]);
2362}
2363# endif /* VBOX_STRICT */
2364
2365# endif /* IN_RC */
2366#endif /* IN_RC || VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
2367
2368#if !defined(IN_R0) || defined(LOG_ENABLED)
2369
2370/** Format handler for PGMPAGE.
2371 * @copydoc FNRTSTRFORMATTYPE */
2372static DECLCALLBACK(size_t) pgmFormatTypeHandlerPage(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
2373 const char *pszType, void const *pvValue,
2374 int cchWidth, int cchPrecision, unsigned fFlags,
2375 void *pvUser)
2376{
2377 size_t cch;
2378 PCPGMPAGE pPage = (PCPGMPAGE)pvValue;
2379 if (VALID_PTR(pPage))
2380 {
2381 char szTmp[64+80];
2382
2383 cch = 0;
2384
2385 /* The single char state stuff. */
2386 static const char s_achPageStates[4] = { 'Z', 'A', 'W', 'S' };
2387 szTmp[cch++] = s_achPageStates[PGM_PAGE_GET_STATE(pPage)];
2388
2389#define IS_PART_INCLUDED(lvl) ( !(fFlags & RTSTR_F_PRECISION) || cchPrecision == (lvl) || cchPrecision >= (lvl)+10 )
2390 if (IS_PART_INCLUDED(5))
2391 {
2392 static const char s_achHandlerStates[4] = { '-', 't', 'w', 'a' };
2393 szTmp[cch++] = s_achHandlerStates[PGM_PAGE_GET_HNDL_PHYS_STATE(pPage)];
2394 szTmp[cch++] = s_achHandlerStates[PGM_PAGE_GET_HNDL_VIRT_STATE(pPage)];
2395 }
2396
2397 /* The type. */
2398 if (IS_PART_INCLUDED(4))
2399 {
2400 szTmp[cch++] = ':';
2401 static const char s_achPageTypes[8][4] = { "INV", "RAM", "MI2", "M2A", "SHA", "ROM", "MIO", "BAD" };
2402 szTmp[cch++] = s_achPageTypes[PGM_PAGE_GET_TYPE(pPage)][0];
2403 szTmp[cch++] = s_achPageTypes[PGM_PAGE_GET_TYPE(pPage)][1];
2404 szTmp[cch++] = s_achPageTypes[PGM_PAGE_GET_TYPE(pPage)][2];
2405 }
2406
2407 /* The numbers. */
2408 if (IS_PART_INCLUDED(3))
2409 {
2410 szTmp[cch++] = ':';
2411 cch += RTStrFormatNumber(&szTmp[cch], PGM_PAGE_GET_HCPHYS(pPage), 16, 12, 0, RTSTR_F_ZEROPAD | RTSTR_F_64BIT);
2412 }
2413
2414 if (IS_PART_INCLUDED(2))
2415 {
2416 szTmp[cch++] = ':';
2417 cch += RTStrFormatNumber(&szTmp[cch], PGM_PAGE_GET_PAGEID(pPage), 16, 7, 0, RTSTR_F_ZEROPAD | RTSTR_F_32BIT);
2418 }
2419
2420 if (IS_PART_INCLUDED(6))
2421 {
2422 szTmp[cch++] = ':';
2423 static const char s_achRefs[4] = { '-', 'U', '!', 'L' };
2424 szTmp[cch++] = s_achRefs[PGM_PAGE_GET_TD_CREFS(pPage)];
2425 cch += RTStrFormatNumber(&szTmp[cch], PGM_PAGE_GET_TD_IDX(pPage), 16, 4, 0, RTSTR_F_ZEROPAD | RTSTR_F_16BIT);
2426 }
2427#undef IS_PART_INCLUDED
2428
2429 cch = pfnOutput(pvArgOutput, szTmp, cch);
2430 }
2431 else
2432 cch = pfnOutput(pvArgOutput, "<bad-pgmpage-ptr>", sizeof("<bad-pgmpage-ptr>") - 1);
2433 return cch;
2434}
2435
2436
2437/** Format handler for PGMRAMRANGE.
2438 * @copydoc FNRTSTRFORMATTYPE */
2439static DECLCALLBACK(size_t) pgmFormatTypeHandlerRamRange(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
2440 const char *pszType, void const *pvValue,
2441 int cchWidth, int cchPrecision, unsigned fFlags,
2442 void *pvUser)
2443{
2444 size_t cch;
2445 PGMRAMRANGE const *pRam = (PGMRAMRANGE const *)pvValue;
2446 if (VALID_PTR(pRam))
2447 {
2448 char szTmp[80];
2449 cch = RTStrPrintf(szTmp, sizeof(szTmp), "%RGp-%RGp", pRam->GCPhys, pRam->GCPhysLast);
2450 cch = pfnOutput(pvArgOutput, szTmp, cch);
2451 }
2452 else
2453 cch = pfnOutput(pvArgOutput, "<bad-pgmramrange-ptr>", sizeof("<bad-pgmramrange-ptr>") - 1);
2454 return cch;
2455}
2456
2457/** Format type andlers to be registered/deregistered. */
2458static const struct
2459{
2460 char szType[24];
2461 PFNRTSTRFORMATTYPE pfnHandler;
2462} g_aPgmFormatTypes[] =
2463{
2464 { "pgmpage", pgmFormatTypeHandlerPage },
2465 { "pgmramrange", pgmFormatTypeHandlerRamRange }
2466};
2467
2468#endif /* !IN_R0 || LOG_ENABLED */
2469
2470
2471/**
2472 * Registers the global string format types.
2473 *
2474 * This should be called at module load time or in some other manner that ensure
2475 * that it's called exactly one time.
2476 *
2477 * @returns IPRT status code on RTStrFormatTypeRegister failure.
2478 */
2479VMMDECL(int) PGMRegisterStringFormatTypes(void)
2480{
2481#if !defined(IN_R0) || defined(LOG_ENABLED)
2482 int rc = VINF_SUCCESS;
2483 unsigned i;
2484 for (i = 0; RT_SUCCESS(rc) && i < RT_ELEMENTS(g_aPgmFormatTypes); i++)
2485 {
2486 rc = RTStrFormatTypeRegister(g_aPgmFormatTypes[i].szType, g_aPgmFormatTypes[i].pfnHandler, NULL);
2487# ifdef IN_RING0
2488 if (rc == VERR_ALREADY_EXISTS)
2489 {
2490 /* in case of cleanup failure in ring-0 */
2491 RTStrFormatTypeDeregister(g_aPgmFormatTypes[i].szType);
2492 rc = RTStrFormatTypeRegister(g_aPgmFormatTypes[i].szType, g_aPgmFormatTypes[i].pfnHandler, NULL);
2493 }
2494# endif
2495 }
2496 if (RT_FAILURE(rc))
2497 while (i-- > 0)
2498 RTStrFormatTypeDeregister(g_aPgmFormatTypes[i].szType);
2499
2500 return rc;
2501#else
2502 return VINF_SUCCESS;
2503#endif
2504}
2505
2506
2507/**
2508 * Deregisters the global string format types.
2509 *
2510 * This should be called at module unload time or in some other manner that
2511 * ensure that it's called exactly one time.
2512 */
2513VMMDECL(void) PGMDeregisterStringFormatTypes(void)
2514{
2515#if !defined(IN_R0) || defined(LOG_ENABLED)
2516 for (unsigned i = 0; i < RT_ELEMENTS(g_aPgmFormatTypes); i++)
2517 RTStrFormatTypeDeregister(g_aPgmFormatTypes[i].szType);
2518#endif
2519}
2520
2521#ifdef VBOX_STRICT
2522
2523/**
2524 * Asserts that there are no mapping conflicts.
2525 *
2526 * @returns Number of conflicts.
2527 * @param pVM The VM Handle.
2528 */
2529VMMDECL(unsigned) PGMAssertNoMappingConflicts(PVM pVM)
2530{
2531 unsigned cErrors = 0;
2532
2533 /* Only applies to raw mode -> 1 VPCU */
2534 Assert(pVM->cCpus == 1);
2535 PVMCPU pVCpu = &pVM->aCpus[0];
2536
2537 /*
2538 * Check for mapping conflicts.
2539 */
2540 for (PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
2541 pMapping;
2542 pMapping = pMapping->CTX_SUFF(pNext))
2543 {
2544 /** @todo This is slow and should be optimized, but since it's just assertions I don't care now. */
2545 for (RTGCPTR GCPtr = pMapping->GCPtr;
2546 GCPtr <= pMapping->GCPtrLast;
2547 GCPtr += PAGE_SIZE)
2548 {
2549 int rc = PGMGstGetPage(pVCpu, (RTGCPTR)GCPtr, NULL, NULL);
2550 if (rc != VERR_PAGE_TABLE_NOT_PRESENT)
2551 {
2552 AssertMsgFailed(("Conflict at %RGv with %s\n", GCPtr, R3STRING(pMapping->pszDesc)));
2553 cErrors++;
2554 break;
2555 }
2556 }
2557 }
2558
2559 return cErrors;
2560}
2561
2562
2563/**
2564 * Asserts that everything related to the guest CR3 is correctly shadowed.
2565 *
2566 * This will call PGMAssertNoMappingConflicts() and PGMAssertHandlerAndFlagsInSync(),
2567 * and assert the correctness of the guest CR3 mapping before asserting that the
2568 * shadow page tables is in sync with the guest page tables.
2569 *
2570 * @returns Number of conflicts.
2571 * @param pVM The VM Handle.
2572 * @param pVCpu VMCPU handle.
2573 * @param cr3 The current guest CR3 register value.
2574 * @param cr4 The current guest CR4 register value.
2575 */
2576VMMDECL(unsigned) PGMAssertCR3(PVM pVM, PVMCPU pVCpu, uint64_t cr3, uint64_t cr4)
2577{
2578 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncCR3), a);
2579 pgmLock(pVM);
2580 unsigned cErrors = PGM_BTH_PFN(AssertCR3, pVCpu)(pVCpu, cr3, cr4, 0, ~(RTGCPTR)0);
2581 pgmUnlock(pVM);
2582 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncCR3), a);
2583 return cErrors;
2584}
2585
2586#endif /* VBOX_STRICT */
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette