VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAll.cpp@ 28800

Last change on this file since 28800 was 28800, checked in by vboxsync, 15 years ago

Automated rebranding to Oracle copyright/license strings via filemuncher
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id
File size: 84.0 KB
Line 
1/* $Id: PGMAll.cpp 28800 2010-04-27 08:22:32Z vboxsync $ */
2/** @file
3 * PGM - Page Manager and Monitor - All context code.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/*******************************************************************************
19* Header Files *
20*******************************************************************************/
21#define LOG_GROUP LOG_GROUP_PGM
22#include <VBox/pgm.h>
23#include <VBox/cpum.h>
24#include <VBox/selm.h>
25#include <VBox/iom.h>
26#include <VBox/sup.h>
27#include <VBox/mm.h>
28#include <VBox/stam.h>
29#include <VBox/csam.h>
30#include <VBox/patm.h>
31#include <VBox/trpm.h>
32#include <VBox/rem.h>
33#include <VBox/em.h>
34#include <VBox/hwaccm.h>
35#include <VBox/hwacc_vmx.h>
36#include "../PGMInternal.h"
37#include <VBox/vm.h>
38#include "../PGMInline.h"
39#include <iprt/assert.h>
40#include <iprt/asm.h>
41#include <iprt/string.h>
42#include <VBox/log.h>
43#include <VBox/param.h>
44#include <VBox/err.h>
45
46
47/*******************************************************************************
48* Structures and Typedefs *
49*******************************************************************************/
50/**
51 * Stated structure for PGM_GST_NAME(HandlerVirtualUpdate) that's
52 * passed to PGM_GST_NAME(VirtHandlerUpdateOne) during enumeration.
53 */
54typedef struct PGMHVUSTATE
55{
56 /** The VM handle. */
57 PVM pVM;
58 /** The VMCPU handle. */
59 PVMCPU pVCpu;
60 /** The todo flags. */
61 RTUINT fTodo;
62 /** The CR4 register value. */
63 uint32_t cr4;
64} PGMHVUSTATE, *PPGMHVUSTATE;
65
66
67/*******************************************************************************
68* Internal Functions *
69*******************************************************************************/
70DECLINLINE(int) pgmShwGetLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPT *ppPdpt, PX86PDPAE *ppPD);
71DECLINLINE(int) pgmShwGetPaePoolPagePD(PPGMCPU pPGM, RTGCPTR GCPtr, PPGMPOOLPAGE *ppShwPde);
72
73/*
74 * Shadow - 32-bit mode
75 */
76#define PGM_SHW_TYPE PGM_TYPE_32BIT
77#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
78#include "PGMAllShw.h"
79
80/* Guest - real mode */
81#define PGM_GST_TYPE PGM_TYPE_REAL
82#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
83#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
84#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
85#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
86#include "PGMGstDefs.h"
87#include "PGMAllGst.h"
88#include "PGMAllBth.h"
89#undef BTH_PGMPOOLKIND_PT_FOR_PT
90#undef BTH_PGMPOOLKIND_ROOT
91#undef PGM_BTH_NAME
92#undef PGM_GST_TYPE
93#undef PGM_GST_NAME
94
95/* Guest - protected mode */
96#define PGM_GST_TYPE PGM_TYPE_PROT
97#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
98#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
99#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
100#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
101#include "PGMGstDefs.h"
102#include "PGMAllGst.h"
103#include "PGMAllBth.h"
104#undef BTH_PGMPOOLKIND_PT_FOR_PT
105#undef BTH_PGMPOOLKIND_ROOT
106#undef PGM_BTH_NAME
107#undef PGM_GST_TYPE
108#undef PGM_GST_NAME
109
110/* Guest - 32-bit mode */
111#define PGM_GST_TYPE PGM_TYPE_32BIT
112#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
113#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
114#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
115#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
116#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD
117#include "PGMGstDefs.h"
118#include "PGMAllGst.h"
119#include "PGMAllBth.h"
120#undef BTH_PGMPOOLKIND_PT_FOR_BIG
121#undef BTH_PGMPOOLKIND_PT_FOR_PT
122#undef BTH_PGMPOOLKIND_ROOT
123#undef PGM_BTH_NAME
124#undef PGM_GST_TYPE
125#undef PGM_GST_NAME
126
127#undef PGM_SHW_TYPE
128#undef PGM_SHW_NAME
129
130
131/*
132 * Shadow - PAE mode
133 */
134#define PGM_SHW_TYPE PGM_TYPE_PAE
135#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
136#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
137#include "PGMAllShw.h"
138
139/* Guest - real mode */
140#define PGM_GST_TYPE PGM_TYPE_REAL
141#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
142#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
143#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
144#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
145#include "PGMGstDefs.h"
146#include "PGMAllBth.h"
147#undef BTH_PGMPOOLKIND_PT_FOR_PT
148#undef BTH_PGMPOOLKIND_ROOT
149#undef PGM_BTH_NAME
150#undef PGM_GST_TYPE
151#undef PGM_GST_NAME
152
153/* Guest - protected mode */
154#define PGM_GST_TYPE PGM_TYPE_PROT
155#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
156#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
157#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
158#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
159#include "PGMGstDefs.h"
160#include "PGMAllBth.h"
161#undef BTH_PGMPOOLKIND_PT_FOR_PT
162#undef BTH_PGMPOOLKIND_ROOT
163#undef PGM_BTH_NAME
164#undef PGM_GST_TYPE
165#undef PGM_GST_NAME
166
167/* Guest - 32-bit mode */
168#define PGM_GST_TYPE PGM_TYPE_32BIT
169#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
170#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
171#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
172#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
173#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_FOR_32BIT
174#include "PGMGstDefs.h"
175#include "PGMAllBth.h"
176#undef BTH_PGMPOOLKIND_PT_FOR_BIG
177#undef BTH_PGMPOOLKIND_PT_FOR_PT
178#undef BTH_PGMPOOLKIND_ROOT
179#undef PGM_BTH_NAME
180#undef PGM_GST_TYPE
181#undef PGM_GST_NAME
182
183
184/* Guest - PAE mode */
185#define PGM_GST_TYPE PGM_TYPE_PAE
186#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
187#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
188#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
189#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
190#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT
191#include "PGMGstDefs.h"
192#include "PGMAllGst.h"
193#include "PGMAllBth.h"
194#undef BTH_PGMPOOLKIND_PT_FOR_BIG
195#undef BTH_PGMPOOLKIND_PT_FOR_PT
196#undef BTH_PGMPOOLKIND_ROOT
197#undef PGM_BTH_NAME
198#undef PGM_GST_TYPE
199#undef PGM_GST_NAME
200
201#undef PGM_SHW_TYPE
202#undef PGM_SHW_NAME
203
204
205#ifndef IN_RC /* AMD64 implies VT-x/AMD-V */
206/*
207 * Shadow - AMD64 mode
208 */
209# define PGM_SHW_TYPE PGM_TYPE_AMD64
210# define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
211# include "PGMAllShw.h"
212
213/* Guest - protected mode (only used for AMD-V nested paging in 64 bits mode) */
214# define PGM_GST_TYPE PGM_TYPE_PROT
215# define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
216# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_PROT(name)
217# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
218# define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PD_PHYS
219# include "PGMGstDefs.h"
220# include "PGMAllBth.h"
221# undef BTH_PGMPOOLKIND_PT_FOR_PT
222# undef BTH_PGMPOOLKIND_ROOT
223# undef PGM_BTH_NAME
224# undef PGM_GST_TYPE
225# undef PGM_GST_NAME
226
227# ifdef VBOX_WITH_64_BITS_GUESTS
228/* Guest - AMD64 mode */
229# define PGM_GST_TYPE PGM_TYPE_AMD64
230# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
231# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
232# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
233# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
234# define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_64BIT_PML4
235# include "PGMGstDefs.h"
236# include "PGMAllGst.h"
237# include "PGMAllBth.h"
238# undef BTH_PGMPOOLKIND_PT_FOR_BIG
239# undef BTH_PGMPOOLKIND_PT_FOR_PT
240# undef BTH_PGMPOOLKIND_ROOT
241# undef PGM_BTH_NAME
242# undef PGM_GST_TYPE
243# undef PGM_GST_NAME
244# endif /* VBOX_WITH_64_BITS_GUESTS */
245
246# undef PGM_SHW_TYPE
247# undef PGM_SHW_NAME
248
249
250/*
251 * Shadow - Nested paging mode
252 */
253# define PGM_SHW_TYPE PGM_TYPE_NESTED
254# define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED(name)
255# include "PGMAllShw.h"
256
257/* Guest - real mode */
258# define PGM_GST_TYPE PGM_TYPE_REAL
259# define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
260# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_REAL(name)
261# include "PGMGstDefs.h"
262# include "PGMAllBth.h"
263# undef PGM_BTH_NAME
264# undef PGM_GST_TYPE
265# undef PGM_GST_NAME
266
267/* Guest - protected mode */
268# define PGM_GST_TYPE PGM_TYPE_PROT
269# define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
270# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PROT(name)
271# include "PGMGstDefs.h"
272# include "PGMAllBth.h"
273# undef PGM_BTH_NAME
274# undef PGM_GST_TYPE
275# undef PGM_GST_NAME
276
277/* Guest - 32-bit mode */
278# define PGM_GST_TYPE PGM_TYPE_32BIT
279# define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
280# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT(name)
281# include "PGMGstDefs.h"
282# include "PGMAllBth.h"
283# undef PGM_BTH_NAME
284# undef PGM_GST_TYPE
285# undef PGM_GST_NAME
286
287/* Guest - PAE mode */
288# define PGM_GST_TYPE PGM_TYPE_PAE
289# define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
290# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE(name)
291# include "PGMGstDefs.h"
292# include "PGMAllBth.h"
293# undef PGM_BTH_NAME
294# undef PGM_GST_TYPE
295# undef PGM_GST_NAME
296
297# ifdef VBOX_WITH_64_BITS_GUESTS
298/* Guest - AMD64 mode */
299# define PGM_GST_TYPE PGM_TYPE_AMD64
300# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
301# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64(name)
302# include "PGMGstDefs.h"
303# include "PGMAllBth.h"
304# undef PGM_BTH_NAME
305# undef PGM_GST_TYPE
306# undef PGM_GST_NAME
307# endif /* VBOX_WITH_64_BITS_GUESTS */
308
309# undef PGM_SHW_TYPE
310# undef PGM_SHW_NAME
311
312
313/*
314 * Shadow - EPT
315 */
316# define PGM_SHW_TYPE PGM_TYPE_EPT
317# define PGM_SHW_NAME(name) PGM_SHW_NAME_EPT(name)
318# include "PGMAllShw.h"
319
320/* Guest - real mode */
321# define PGM_GST_TYPE PGM_TYPE_REAL
322# define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
323# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_REAL(name)
324# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
325# include "PGMGstDefs.h"
326# include "PGMAllBth.h"
327# undef BTH_PGMPOOLKIND_PT_FOR_PT
328# undef PGM_BTH_NAME
329# undef PGM_GST_TYPE
330# undef PGM_GST_NAME
331
332/* Guest - protected mode */
333# define PGM_GST_TYPE PGM_TYPE_PROT
334# define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
335# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PROT(name)
336# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
337# include "PGMGstDefs.h"
338# include "PGMAllBth.h"
339# undef BTH_PGMPOOLKIND_PT_FOR_PT
340# undef PGM_BTH_NAME
341# undef PGM_GST_TYPE
342# undef PGM_GST_NAME
343
344/* Guest - 32-bit mode */
345# define PGM_GST_TYPE PGM_TYPE_32BIT
346# define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
347# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_32BIT(name)
348# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
349# include "PGMGstDefs.h"
350# include "PGMAllBth.h"
351# undef BTH_PGMPOOLKIND_PT_FOR_PT
352# undef PGM_BTH_NAME
353# undef PGM_GST_TYPE
354# undef PGM_GST_NAME
355
356/* Guest - PAE mode */
357# define PGM_GST_TYPE PGM_TYPE_PAE
358# define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
359# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PAE(name)
360# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
361# include "PGMGstDefs.h"
362# include "PGMAllBth.h"
363# undef BTH_PGMPOOLKIND_PT_FOR_PT
364# undef PGM_BTH_NAME
365# undef PGM_GST_TYPE
366# undef PGM_GST_NAME
367
368# ifdef VBOX_WITH_64_BITS_GUESTS
369/* Guest - AMD64 mode */
370# define PGM_GST_TYPE PGM_TYPE_AMD64
371# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
372# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_AMD64(name)
373# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
374# include "PGMGstDefs.h"
375# include "PGMAllBth.h"
376# undef BTH_PGMPOOLKIND_PT_FOR_PT
377# undef PGM_BTH_NAME
378# undef PGM_GST_TYPE
379# undef PGM_GST_NAME
380# endif /* VBOX_WITH_64_BITS_GUESTS */
381
382# undef PGM_SHW_TYPE
383# undef PGM_SHW_NAME
384
385#endif /* !IN_RC */
386
387
388#ifndef IN_RING3
389/**
390 * #PF Handler.
391 *
392 * @returns VBox status code (appropriate for trap handling and GC return).
393 * @param pVCpu VMCPU handle.
394 * @param uErr The trap error code.
395 * @param pRegFrame Trap register frame.
396 * @param pvFault The fault address.
397 */
398VMMDECL(int) PGMTrap0eHandler(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
399{
400 PVM pVM = pVCpu->CTX_SUFF(pVM);
401
402 Log(("PGMTrap0eHandler: uErr=%RGx pvFault=%RGv eip=%04x:%RGv\n", uErr, pvFault, pRegFrame->cs, (RTGCPTR)pRegFrame->rip));
403 STAM_PROFILE_START(&pVCpu->pgm.s.StatRZTrap0e, a);
404 STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = NULL; } );
405
406
407#ifdef VBOX_WITH_STATISTICS
408 /*
409 * Error code stats.
410 */
411 if (uErr & X86_TRAP_PF_US)
412 {
413 if (!(uErr & X86_TRAP_PF_P))
414 {
415 if (uErr & X86_TRAP_PF_RW)
416 STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eUSNotPresentWrite);
417 else
418 STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eUSNotPresentRead);
419 }
420 else if (uErr & X86_TRAP_PF_RW)
421 STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eUSWrite);
422 else if (uErr & X86_TRAP_PF_RSVD)
423 STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eUSReserved);
424 else if (uErr & X86_TRAP_PF_ID)
425 STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eUSNXE);
426 else
427 STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eUSRead);
428 }
429 else
430 { /* Supervisor */
431 if (!(uErr & X86_TRAP_PF_P))
432 {
433 if (uErr & X86_TRAP_PF_RW)
434 STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eSVNotPresentWrite);
435 else
436 STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eSVNotPresentRead);
437 }
438 else if (uErr & X86_TRAP_PF_RW)
439 STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eSVWrite);
440 else if (uErr & X86_TRAP_PF_ID)
441 STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eSNXE);
442 else if (uErr & X86_TRAP_PF_RSVD)
443 STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eSVReserved);
444 }
445#endif /* VBOX_WITH_STATISTICS */
446
447 /*
448 * Call the worker.
449 */
450 bool fLockTaken = false;
451 int rc = PGM_BTH_PFN(Trap0eHandler, pVCpu)(pVCpu, uErr, pRegFrame, pvFault, &fLockTaken);
452 if (fLockTaken)
453 {
454 Assert(PGMIsLockOwner(pVM));
455 pgmUnlock(pVM);
456 }
457 if (rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
458 rc = VINF_SUCCESS;
459
460# ifdef IN_RING0
461 /* Note: hack alert for difficult to reproduce problem. */
462 if ( rc == VERR_PAGE_NOT_PRESENT /* SMP only ; disassembly might fail. */
463 || rc == VERR_PAGE_TABLE_NOT_PRESENT /* seen with UNI & SMP */
464 || rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT /* seen with SMP */
465 || rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT) /* precaution */
466 {
467 Log(("WARNING: Unexpected VERR_PAGE_TABLE_NOT_PRESENT (%d) for page fault at %RGv error code %x (rip=%RGv)\n", rc, pvFault, uErr, pRegFrame->rip));
468 /* Some kind of inconsistency in the SMP case; it's safe to just execute the instruction again; not sure about single VCPU VMs though. */
469 rc = VINF_SUCCESS;
470 }
471# endif
472
473 STAM_STATS({ if (rc == VINF_EM_RAW_GUEST_TRAP) STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eGuestPF); });
474 STAM_STATS({ if (!pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution))
475 pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2Misc; });
476 STAM_PROFILE_STOP_EX(&pVCpu->pgm.s.StatRZTrap0e, pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution), a);
477 return rc;
478}
479#endif /* !IN_RING3 */
480
481
482/**
483 * Prefetch a page
484 *
485 * Typically used to sync commonly used pages before entering raw mode
486 * after a CR3 reload.
487 *
488 * @returns VBox status code suitable for scheduling.
489 * @retval VINF_SUCCESS on success.
490 * @retval VINF_PGM_SYNC_CR3 if we're out of shadow pages or something like that.
491 * @param pVCpu VMCPU handle.
492 * @param GCPtrPage Page to invalidate.
493 */
494VMMDECL(int) PGMPrefetchPage(PVMCPU pVCpu, RTGCPTR GCPtrPage)
495{
496 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_MID_Z(Stat,Prefetch), a);
497 int rc = PGM_BTH_PFN(PrefetchPage, pVCpu)(pVCpu, GCPtrPage);
498 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,Prefetch), a);
499 AssertMsg(rc == VINF_SUCCESS || rc == VINF_PGM_SYNC_CR3 || RT_FAILURE(rc), ("rc=%Rrc\n", rc));
500 return rc;
501}
502
503
504/**
505 * Gets the mapping corresponding to the specified address (if any).
506 *
507 * @returns Pointer to the mapping.
508 * @returns NULL if not
509 *
510 * @param pVM The virtual machine.
511 * @param GCPtr The guest context pointer.
512 */
513PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr)
514{
515 PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
516 while (pMapping)
517 {
518 if ((uintptr_t)GCPtr < (uintptr_t)pMapping->GCPtr)
519 break;
520 if ((uintptr_t)GCPtr - (uintptr_t)pMapping->GCPtr < pMapping->cb)
521 return pMapping;
522 pMapping = pMapping->CTX_SUFF(pNext);
523 }
524 return NULL;
525}
526
527
528/**
529 * Verifies a range of pages for read or write access
530 *
531 * Only checks the guest's page tables
532 *
533 * @returns VBox status code.
534 * @param pVCpu VMCPU handle.
535 * @param Addr Guest virtual address to check
536 * @param cbSize Access size
537 * @param fAccess Access type (r/w, user/supervisor (X86_PTE_*))
538 * @remarks Current not in use.
539 */
540VMMDECL(int) PGMIsValidAccess(PVMCPU pVCpu, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess)
541{
542 /*
543 * Validate input.
544 */
545 if (fAccess & ~(X86_PTE_US | X86_PTE_RW))
546 {
547 AssertMsgFailed(("PGMIsValidAccess: invalid access type %08x\n", fAccess));
548 return VERR_INVALID_PARAMETER;
549 }
550
551 uint64_t fPage;
552 int rc = PGMGstGetPage(pVCpu, (RTGCPTR)Addr, &fPage, NULL);
553 if (RT_FAILURE(rc))
554 {
555 Log(("PGMIsValidAccess: access violation for %RGv rc=%d\n", Addr, rc));
556 return VINF_EM_RAW_GUEST_TRAP;
557 }
558
559 /*
560 * Check if the access would cause a page fault
561 *
562 * Note that hypervisor page directories are not present in the guest's tables, so this check
563 * is sufficient.
564 */
565 bool fWrite = !!(fAccess & X86_PTE_RW);
566 bool fUser = !!(fAccess & X86_PTE_US);
567 if ( !(fPage & X86_PTE_P)
568 || (fWrite && !(fPage & X86_PTE_RW))
569 || (fUser && !(fPage & X86_PTE_US)) )
570 {
571 Log(("PGMIsValidAccess: access violation for %RGv attr %#llx vs %d:%d\n", Addr, fPage, fWrite, fUser));
572 return VINF_EM_RAW_GUEST_TRAP;
573 }
574 if ( RT_SUCCESS(rc)
575 && PAGE_ADDRESS(Addr) != PAGE_ADDRESS(Addr + cbSize))
576 return PGMIsValidAccess(pVCpu, Addr + PAGE_SIZE, (cbSize > PAGE_SIZE) ? cbSize - PAGE_SIZE : 1, fAccess);
577 return rc;
578}
579
580
581/**
582 * Verifies a range of pages for read or write access
583 *
584 * Supports handling of pages marked for dirty bit tracking and CSAM
585 *
586 * @returns VBox status code.
587 * @param pVCpu VMCPU handle.
588 * @param Addr Guest virtual address to check
589 * @param cbSize Access size
590 * @param fAccess Access type (r/w, user/supervisor (X86_PTE_*))
591 */
592VMMDECL(int) PGMVerifyAccess(PVMCPU pVCpu, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess)
593{
594 PVM pVM = pVCpu->CTX_SUFF(pVM);
595
596 AssertMsg(!(fAccess & ~(X86_PTE_US | X86_PTE_RW)), ("PGMVerifyAccess: invalid access type %08x\n", fAccess));
597
598 /*
599 * Get going.
600 */
601 uint64_t fPageGst;
602 int rc = PGMGstGetPage(pVCpu, (RTGCPTR)Addr, &fPageGst, NULL);
603 if (RT_FAILURE(rc))
604 {
605 Log(("PGMVerifyAccess: access violation for %RGv rc=%d\n", Addr, rc));
606 return VINF_EM_RAW_GUEST_TRAP;
607 }
608
609 /*
610 * Check if the access would cause a page fault
611 *
612 * Note that hypervisor page directories are not present in the guest's tables, so this check
613 * is sufficient.
614 */
615 const bool fWrite = !!(fAccess & X86_PTE_RW);
616 const bool fUser = !!(fAccess & X86_PTE_US);
617 if ( !(fPageGst & X86_PTE_P)
618 || (fWrite && !(fPageGst & X86_PTE_RW))
619 || (fUser && !(fPageGst & X86_PTE_US)) )
620 {
621 Log(("PGMVerifyAccess: access violation for %RGv attr %#llx vs %d:%d\n", Addr, fPageGst, fWrite, fUser));
622 return VINF_EM_RAW_GUEST_TRAP;
623 }
624
625 if (!HWACCMIsNestedPagingActive(pVM))
626 {
627 /*
628 * Next step is to verify if we protected this page for dirty bit tracking or for CSAM scanning
629 */
630 rc = PGMShwGetPage(pVCpu, (RTGCPTR)Addr, NULL, NULL);
631 if ( rc == VERR_PAGE_NOT_PRESENT
632 || rc == VERR_PAGE_TABLE_NOT_PRESENT)
633 {
634 /*
635 * Page is not present in our page tables.
636 * Try to sync it!
637 */
638 Assert(X86_TRAP_PF_RW == X86_PTE_RW && X86_TRAP_PF_US == X86_PTE_US);
639 uint32_t uErr = fAccess & (X86_TRAP_PF_RW | X86_TRAP_PF_US);
640 rc = PGM_BTH_PFN(VerifyAccessSyncPage, pVCpu)(pVCpu, Addr, fPageGst, uErr);
641 if (rc != VINF_SUCCESS)
642 return rc;
643 }
644 else
645 AssertMsg(rc == VINF_SUCCESS, ("PGMShwGetPage %RGv failed with %Rrc\n", Addr, rc));
646 }
647
648#if 0 /* def VBOX_STRICT; triggers too often now */
649 /*
650 * This check is a bit paranoid, but useful.
651 */
652 /** @note this will assert when writing to monitored pages (a bit annoying actually) */
653 uint64_t fPageShw;
654 rc = PGMShwGetPage(pVCpu, (RTGCPTR)Addr, &fPageShw, NULL);
655 if ( (rc == VERR_PAGE_NOT_PRESENT || RT_FAILURE(rc))
656 || (fWrite && !(fPageShw & X86_PTE_RW))
657 || (fUser && !(fPageShw & X86_PTE_US)) )
658 {
659 AssertMsgFailed(("Unexpected access violation for %RGv! rc=%Rrc write=%d user=%d\n",
660 Addr, rc, fWrite && !(fPageShw & X86_PTE_RW), fUser && !(fPageShw & X86_PTE_US)));
661 return VINF_EM_RAW_GUEST_TRAP;
662 }
663#endif
664
665 if ( RT_SUCCESS(rc)
666 && ( PAGE_ADDRESS(Addr) != PAGE_ADDRESS(Addr + cbSize - 1)
667 || Addr + cbSize < Addr))
668 {
669 /* Don't recursively call PGMVerifyAccess as we might run out of stack. */
670 for (;;)
671 {
672 Addr += PAGE_SIZE;
673 if (cbSize > PAGE_SIZE)
674 cbSize -= PAGE_SIZE;
675 else
676 cbSize = 1;
677 rc = PGMVerifyAccess(pVCpu, Addr, 1, fAccess);
678 if (rc != VINF_SUCCESS)
679 break;
680 if (PAGE_ADDRESS(Addr) == PAGE_ADDRESS(Addr + cbSize - 1))
681 break;
682 }
683 }
684 return rc;
685}
686
687
688/**
689 * Emulation of the invlpg instruction (HC only actually).
690 *
691 * @returns VBox status code, special care required.
692 * @retval VINF_PGM_SYNC_CR3 - handled.
693 * @retval VINF_EM_RAW_EMULATE_INSTR - not handled (RC only).
694 * @retval VERR_REM_FLUSHED_PAGES_OVERFLOW - not handled.
695 *
696 * @param pVCpu VMCPU handle.
697 * @param GCPtrPage Page to invalidate.
698 *
699 * @remark ASSUMES the page table entry or page directory is valid. Fairly
700 * safe, but there could be edge cases!
701 *
702 * @todo Flush page or page directory only if necessary!
703 */
704VMMDECL(int) PGMInvalidatePage(PVMCPU pVCpu, RTGCPTR GCPtrPage)
705{
706 PVM pVM = pVCpu->CTX_SUFF(pVM);
707 int rc;
708 Log3(("PGMInvalidatePage: GCPtrPage=%RGv\n", GCPtrPage));
709
710#ifndef IN_RING3
711 /*
712 * Notify the recompiler so it can record this instruction.
713 */
714 REMNotifyInvalidatePage(pVM, GCPtrPage);
715#endif /* !IN_RING3 */
716
717
718#ifdef IN_RC
719 /*
720 * Check for conflicts and pending CR3 monitoring updates.
721 */
722 if (pgmMapAreMappingsFloating(&pVM->pgm.s))
723 {
724 if ( pgmGetMapping(pVM, GCPtrPage)
725 && PGMGstGetPage(pVCpu, GCPtrPage, NULL, NULL) != VERR_PAGE_TABLE_NOT_PRESENT)
726 {
727 LogFlow(("PGMGCInvalidatePage: Conflict!\n"));
728 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
729 STAM_COUNTER_INC(&pVM->pgm.s.StatRCInvlPgConflict);
730 return VINF_PGM_SYNC_CR3;
731 }
732
733 if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
734 {
735 LogFlow(("PGMGCInvalidatePage: PGM_SYNC_MONITOR_CR3 -> reinterpret instruction in R3\n"));
736 STAM_COUNTER_INC(&pVM->pgm.s.StatRCInvlPgSyncMonCR3);
737 return VINF_EM_RAW_EMULATE_INSTR;
738 }
739 }
740#endif /* IN_RC */
741
742 /*
743 * Call paging mode specific worker.
744 */
745 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePage), a);
746 pgmLock(pVM);
747 rc = PGM_BTH_PFN(InvalidatePage, pVCpu)(pVCpu, GCPtrPage);
748 pgmUnlock(pVM);
749 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePage), a);
750
751 /* Invalidate the TLB entry; might already be done by InvalidatePage (@todo) */
752 PGM_INVL_PG(pVCpu, GCPtrPage);
753
754#ifdef IN_RING3
755 /*
756 * Check if we have a pending update of the CR3 monitoring.
757 */
758 if ( RT_SUCCESS(rc)
759 && (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3))
760 {
761 pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
762 Assert(!pVM->pgm.s.fMappingsFixed); Assert(!pVM->pgm.s.fMappingsDisabled);
763 }
764
765 /*
766 * Inform CSAM about the flush
767 *
768 * Note: This is to check if monitored pages have been changed; when we implement
769 * callbacks for virtual handlers, this is no longer required.
770 */
771 CSAMR3FlushPage(pVM, GCPtrPage);
772#endif /* IN_RING3 */
773
774 /* Ignore all irrelevant error codes. */
775 if ( rc == VERR_PAGE_NOT_PRESENT
776 || rc == VERR_PAGE_TABLE_NOT_PRESENT
777 || rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT
778 || rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT)
779 rc = VINF_SUCCESS;
780
781 return rc;
782}
783
784
785/**
786 * Executes an instruction using the interpreter.
787 *
788 * @returns VBox status code (appropriate for trap handling and GC return).
789 * @param pVM VM handle.
790 * @param pVCpu VMCPU handle.
791 * @param pRegFrame Register frame.
792 * @param pvFault Fault address.
793 */
794VMMDECL(int) PGMInterpretInstruction(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
795{
796 uint32_t cb;
797 int rc = EMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault, &cb);
798 if (rc == VERR_EM_INTERPRETER)
799 rc = VINF_EM_RAW_EMULATE_INSTR;
800 if (rc != VINF_SUCCESS)
801 Log(("PGMInterpretInstruction: returns %Rrc (pvFault=%RGv)\n", rc, pvFault));
802 return rc;
803}
804
805
806/**
807 * Gets effective page information (from the VMM page directory).
808 *
809 * @returns VBox status.
810 * @param pVCpu VMCPU handle.
811 * @param GCPtr Guest Context virtual address of the page.
812 * @param pfFlags Where to store the flags. These are X86_PTE_*.
813 * @param pHCPhys Where to store the HC physical address of the page.
814 * This is page aligned.
815 * @remark You should use PGMMapGetPage() for pages in a mapping.
816 */
817VMMDECL(int) PGMShwGetPage(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys)
818{
819 pgmLock(pVCpu->CTX_SUFF(pVM));
820 int rc = PGM_SHW_PFN(GetPage, pVCpu)(pVCpu, GCPtr, pfFlags, pHCPhys);
821 pgmUnlock(pVCpu->CTX_SUFF(pVM));
822 return rc;
823}
824
825
826/**
827 * Sets (replaces) the page flags for a range of pages in the shadow context.
828 *
829 * @returns VBox status.
830 * @param pVCpu VMCPU handle.
831 * @param GCPtr The address of the first page.
832 * @param cb The size of the range in bytes.
833 * @param fFlags Page flags X86_PTE_*, excluding the page mask of course.
834 * @remark You must use PGMMapSetPage() for pages in a mapping.
835 */
836VMMDECL(int) PGMShwSetPage(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags)
837{
838 return PGMShwModifyPage(pVCpu, GCPtr, cb, fFlags, 0);
839}
840
841
842/**
843 * Modify page flags for a range of pages in the shadow context.
844 *
845 * The existing flags are ANDed with the fMask and ORed with the fFlags.
846 *
847 * @returns VBox status code.
848 * @param pVCpu VMCPU handle.
849 * @param GCPtr Virtual address of the first page in the range.
850 * @param cb Size (in bytes) of the range to apply the modification to.
851 * @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
852 * @param fMask The AND mask - page flags X86_PTE_*.
853 * Be very CAREFUL when ~'ing constants which could be 32-bit!
854 * @remark You must use PGMMapModifyPage() for pages in a mapping.
855 */
856VMMDECL(int) PGMShwModifyPage(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
857{
858 AssertMsg(!(fFlags & X86_PTE_PAE_PG_MASK), ("fFlags=%#llx\n", fFlags));
859 Assert(cb);
860
861 /*
862 * Align the input.
863 */
864 cb += GCPtr & PAGE_OFFSET_MASK;
865 cb = RT_ALIGN_Z(cb, PAGE_SIZE);
866 GCPtr = (GCPtr & PAGE_BASE_GC_MASK); /** @todo this ain't necessary, right... */
867
868 /*
869 * Call worker.
870 */
871 PVM pVM = pVCpu->CTX_SUFF(pVM);
872 pgmLock(pVM);
873 int rc = PGM_SHW_PFN(ModifyPage, pVCpu)(pVCpu, GCPtr, cb, fFlags, fMask);
874 pgmUnlock(pVM);
875 return rc;
876}
877
878/**
879 * Gets the shadow page directory for the specified address, PAE.
880 *
881 * @returns Pointer to the shadow PD.
882 * @param pVCpu The VMCPU handle.
883 * @param GCPtr The address.
884 * @param pGstPdpe Guest PDPT entry
885 * @param ppPD Receives address of page directory
886 */
887int pgmShwSyncPaePDPtr(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDPE pGstPdpe, PX86PDPAE *ppPD)
888{
889 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
890 PX86PDPT pPdpt = pgmShwGetPaePDPTPtr(&pVCpu->pgm.s);
891 PX86PDPE pPdpe = &pPdpt->a[iPdPt];
892 PVM pVM = pVCpu->CTX_SUFF(pVM);
893 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
894 PPGMPOOLPAGE pShwPage;
895 int rc;
896
897 Assert(PGMIsLockOwner(pVM));
898
899 /* Allocate page directory if not present. */
900 if ( !pPdpe->n.u1Present
901 && !(pPdpe->u & X86_PDPE_PG_MASK))
902 {
903 RTGCPTR64 GCPdPt;
904 PGMPOOLKIND enmKind;
905
906# if defined(IN_RC)
907 /* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
908 PGMDynLockHCPage(pVM, (uint8_t *)pPdpe);
909# endif
910
911 if (HWACCMIsNestedPagingActive(pVM) || !CPUMIsGuestPagingEnabled(pVCpu))
912 {
913 /* AMD-V nested paging or real/protected mode without paging */
914 GCPdPt = (RTGCPTR64)iPdPt << X86_PDPT_SHIFT;
915 enmKind = PGMPOOLKIND_PAE_PD_PHYS;
916 }
917 else
918 {
919 Assert(pGstPdpe);
920
921 if (CPUMGetGuestCR4(pVCpu) & X86_CR4_PAE)
922 {
923 if (!pGstPdpe->n.u1Present)
924 {
925 /* PD not present; guest must reload CR3 to change it.
926 * No need to monitor anything in this case.
927 */
928 Assert(!HWACCMIsEnabled(pVM));
929
930 GCPdPt = pGstPdpe->u & X86_PDPE_PG_MASK;
931 enmKind = PGMPOOLKIND_PAE_PD_PHYS;
932 pGstPdpe->n.u1Present = 1;
933 }
934 else
935 {
936 GCPdPt = pGstPdpe->u & X86_PDPE_PG_MASK;
937 enmKind = PGMPOOLKIND_PAE_PD_FOR_PAE_PD;
938 }
939 }
940 else
941 {
942 GCPdPt = CPUMGetGuestCR3(pVCpu);
943 enmKind = (PGMPOOLKIND)(PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD + iPdPt);
944 }
945 }
946
947 /* Create a reference back to the PDPT by using the index in its shadow page. */
948 rc = pgmPoolAlloc(pVM, GCPdPt, enmKind, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPdPt, &pShwPage);
949 AssertRCReturn(rc, rc);
950
951 /* The PD was cached or created; hook it up now. */
952 pPdpe->u |= pShwPage->Core.Key
953 | (pGstPdpe->u & ~(X86_PDPE_PG_MASK | X86_PDPE_AVL_MASK | X86_PDPE_PCD | X86_PDPE_PWT));
954
955# if defined(IN_RC)
956 /* In 32 bits PAE mode we *must* invalidate the TLB when changing a PDPT entry; the CPU fetches them only during cr3 load, so any
957 * non-present PDPT will continue to cause page faults.
958 */
959 ASMReloadCR3();
960 PGMDynUnlockHCPage(pVM, (uint8_t *)pPdpe);
961# endif
962 }
963 else
964 {
965 pShwPage = pgmPoolGetPage(pPool, pPdpe->u & X86_PDPE_PG_MASK);
966 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
967 Assert((pPdpe->u & X86_PDPE_PG_MASK) == pShwPage->Core.Key);
968
969 pgmPoolCacheUsed(pPool, pShwPage);
970 }
971 *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
972 return VINF_SUCCESS;
973}
974
975
976/**
977 * Gets the pointer to the shadow page directory entry for an address, PAE.
978 *
979 * @returns Pointer to the PDE.
980 * @param pPGM Pointer to the PGMCPU instance data.
981 * @param GCPtr The address.
982 * @param ppShwPde Receives the address of the pgm pool page for the shadow page directory
983 */
984DECLINLINE(int) pgmShwGetPaePoolPagePD(PPGMCPU pPGM, RTGCPTR GCPtr, PPGMPOOLPAGE *ppShwPde)
985{
986 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
987 PX86PDPT pPdpt = pgmShwGetPaePDPTPtr(pPGM);
988
989 Assert(PGMIsLockOwner(PGMCPU2VM(pPGM)));
990
991 AssertReturn(pPdpt, VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT); /* can't happen */
992 if (!pPdpt->a[iPdPt].n.u1Present)
993 {
994 LogFlow(("pgmShwGetPaePoolPagePD: PD %d not present (%RX64)\n", iPdPt, pPdpt->a[iPdPt].u));
995 return VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT;
996 }
997 AssertMsg(pPdpt->a[iPdPt].u & X86_PDPE_PG_MASK, ("GCPtr=%RGv\n", GCPtr));
998
999 /* Fetch the pgm pool shadow descriptor. */
1000 PPGMPOOLPAGE pShwPde = pgmPoolGetPage(PGMCPU2PGM(pPGM)->CTX_SUFF(pPool), pPdpt->a[iPdPt].u & X86_PDPE_PG_MASK);
1001 AssertReturn(pShwPde, VERR_INTERNAL_ERROR);
1002
1003 *ppShwPde = pShwPde;
1004 return VINF_SUCCESS;
1005}
1006
1007#ifndef IN_RC
1008
1009/**
1010 * Syncs the SHADOW page directory pointer for the specified address.
1011 *
1012 * Allocates backing pages in case the PDPT or PML4 entry is missing.
1013 *
1014 * The caller is responsible for making sure the guest has a valid PD before
1015 * calling this function.
1016 *
1017 * @returns VBox status.
1018 * @param pVCpu VMCPU handle.
1019 * @param GCPtr The address.
1020 * @param pGstPml4e Guest PML4 entry
1021 * @param pGstPdpe Guest PDPT entry
1022 * @param ppPD Receives address of page directory
1023 */
1024int pgmShwSyncLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PX86PML4E pGstPml4e, PX86PDPE pGstPdpe, PX86PDPAE *ppPD)
1025{
1026 PPGMCPU pPGM = &pVCpu->pgm.s;
1027 PVM pVM = pVCpu->CTX_SUFF(pVM);
1028 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1029 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
1030 PX86PML4E pPml4e = pgmShwGetLongModePML4EPtr(pPGM, iPml4);
1031 bool fNestedPagingOrNoGstPaging = HWACCMIsNestedPagingActive(pVM) || !CPUMIsGuestPagingEnabled(pVCpu);
1032 PPGMPOOLPAGE pShwPage;
1033 int rc;
1034
1035 Assert(PGMIsLockOwner(pVM));
1036
1037 /* Allocate page directory pointer table if not present. */
1038 if ( !pPml4e->n.u1Present
1039 && !(pPml4e->u & X86_PML4E_PG_MASK))
1040 {
1041 RTGCPTR64 GCPml4;
1042 PGMPOOLKIND enmKind;
1043
1044 Assert(pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
1045
1046 if (fNestedPagingOrNoGstPaging)
1047 {
1048 /* AMD-V nested paging or real/protected mode without paging */
1049 GCPml4 = (RTGCPTR64)iPml4 << X86_PML4_SHIFT;
1050 enmKind = PGMPOOLKIND_64BIT_PDPT_FOR_PHYS;
1051 }
1052 else
1053 {
1054 Assert(pGstPml4e && pGstPdpe);
1055
1056 GCPml4 = pGstPml4e->u & X86_PML4E_PG_MASK;
1057 enmKind = PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT;
1058 }
1059
1060 /* Create a reference back to the PDPT by using the index in its shadow page. */
1061 rc = pgmPoolAlloc(pVM, GCPml4, enmKind, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPml4, &pShwPage);
1062 AssertRCReturn(rc, rc);
1063 }
1064 else
1065 {
1066 pShwPage = pgmPoolGetPage(pPool, pPml4e->u & X86_PML4E_PG_MASK);
1067 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1068
1069 pgmPoolCacheUsed(pPool, pShwPage);
1070 }
1071 /* The PDPT was cached or created; hook it up now. */
1072 pPml4e->u |= pShwPage->Core.Key
1073 | (pGstPml4e->u & ~(X86_PML4E_PG_MASK | X86_PML4E_AVL_MASK | X86_PML4E_PCD | X86_PML4E_PWT));
1074
1075 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1076 PX86PDPT pPdpt = (PX86PDPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1077 PX86PDPE pPdpe = &pPdpt->a[iPdPt];
1078
1079 /* Allocate page directory if not present. */
1080 if ( !pPdpe->n.u1Present
1081 && !(pPdpe->u & X86_PDPE_PG_MASK))
1082 {
1083 RTGCPTR64 GCPdPt;
1084 PGMPOOLKIND enmKind;
1085
1086 if (fNestedPagingOrNoGstPaging)
1087 {
1088 /* AMD-V nested paging or real/protected mode without paging */
1089 GCPdPt = (RTGCPTR64)iPdPt << X86_PDPT_SHIFT;
1090 enmKind = PGMPOOLKIND_64BIT_PD_FOR_PHYS;
1091 }
1092 else
1093 {
1094 Assert(pGstPdpe);
1095
1096 GCPdPt = pGstPdpe->u & X86_PDPE_PG_MASK;
1097 enmKind = PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD;
1098 }
1099
1100 /* Create a reference back to the PDPT by using the index in its shadow page. */
1101 rc = pgmPoolAlloc(pVM, GCPdPt, enmKind, pShwPage->idx, iPdPt, &pShwPage);
1102 AssertRCReturn(rc, rc);
1103 }
1104 else
1105 {
1106 pShwPage = pgmPoolGetPage(pPool, pPdpe->u & X86_PDPE_PG_MASK);
1107 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1108
1109 pgmPoolCacheUsed(pPool, pShwPage);
1110 }
1111 /* The PD was cached or created; hook it up now. */
1112 pPdpe->u |= pShwPage->Core.Key
1113 | (pGstPdpe->u & ~(X86_PDPE_PG_MASK | X86_PDPE_AVL_MASK | X86_PDPE_PCD | X86_PDPE_PWT));
1114
1115 *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1116 return VINF_SUCCESS;
1117}
1118
1119
1120/**
1121 * Gets the SHADOW page directory pointer for the specified address (long mode).
1122 *
1123 * @returns VBox status.
1124 * @param pVCpu VMCPU handle.
1125 * @param GCPtr The address.
1126 * @param ppPdpt Receives address of pdpt
1127 * @param ppPD Receives address of page directory
1128 */
1129DECLINLINE(int) pgmShwGetLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPT *ppPdpt, PX86PDPAE *ppPD)
1130{
1131 PPGMCPU pPGM = &pVCpu->pgm.s;
1132 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
1133 PCX86PML4E pPml4e = pgmShwGetLongModePML4EPtr(pPGM, iPml4);
1134
1135 Assert(PGMIsLockOwner(PGMCPU2VM(pPGM)));
1136
1137 AssertReturn(pPml4e, VERR_INTERNAL_ERROR);
1138 if (ppPml4e)
1139 *ppPml4e = (PX86PML4E)pPml4e;
1140
1141 Log4(("pgmShwGetLongModePDPtr %RGv (%RHv) %RX64\n", GCPtr, pPml4e, pPml4e->u));
1142
1143 if (!pPml4e->n.u1Present)
1144 return VERR_PAGE_MAP_LEVEL4_NOT_PRESENT;
1145
1146 PVM pVM = pVCpu->CTX_SUFF(pVM);
1147 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1148 PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPml4e->u & X86_PML4E_PG_MASK);
1149 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1150
1151 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1152 PCX86PDPT pPdpt = *ppPdpt = (PX86PDPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1153 if (!pPdpt->a[iPdPt].n.u1Present)
1154 return VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT;
1155
1156 pShwPage = pgmPoolGetPage(pPool, pPdpt->a[iPdPt].u & X86_PDPE_PG_MASK);
1157 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1158
1159 *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1160 return VINF_SUCCESS;
1161}
1162
1163
1164/**
1165 * Syncs the SHADOW EPT page directory pointer for the specified address. Allocates
1166 * backing pages in case the PDPT or PML4 entry is missing.
1167 *
1168 * @returns VBox status.
1169 * @param pVCpu VMCPU handle.
1170 * @param GCPtr The address.
1171 * @param ppPdpt Receives address of pdpt
1172 * @param ppPD Receives address of page directory
1173 */
1174int pgmShwGetEPTPDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PEPTPDPT *ppPdpt, PEPTPD *ppPD)
1175{
1176 PPGMCPU pPGM = &pVCpu->pgm.s;
1177 PVM pVM = pVCpu->CTX_SUFF(pVM);
1178 const unsigned iPml4 = (GCPtr >> EPT_PML4_SHIFT) & EPT_PML4_MASK;
1179 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1180 PEPTPML4 pPml4;
1181 PEPTPML4E pPml4e;
1182 PPGMPOOLPAGE pShwPage;
1183 int rc;
1184
1185 Assert(HWACCMIsNestedPagingActive(pVM));
1186 Assert(PGMIsLockOwner(pVM));
1187
1188 pPml4 = (PEPTPML4)PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
1189 Assert(pPml4);
1190
1191 /* Allocate page directory pointer table if not present. */
1192 pPml4e = &pPml4->a[iPml4];
1193 if ( !pPml4e->n.u1Present
1194 && !(pPml4e->u & EPT_PML4E_PG_MASK))
1195 {
1196 Assert(!(pPml4e->u & EPT_PML4E_PG_MASK));
1197 RTGCPTR64 GCPml4 = (RTGCPTR64)iPml4 << EPT_PML4_SHIFT;
1198
1199 rc = pgmPoolAlloc(pVM, GCPml4, PGMPOOLKIND_EPT_PDPT_FOR_PHYS, PGMPOOL_IDX_NESTED_ROOT, iPml4, &pShwPage);
1200 AssertRCReturn(rc, rc);
1201 }
1202 else
1203 {
1204 pShwPage = pgmPoolGetPage(pPool, pPml4e->u & EPT_PML4E_PG_MASK);
1205 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1206
1207 pgmPoolCacheUsed(pPool, pShwPage);
1208 }
1209 /* The PDPT was cached or created; hook it up now and fill with the default value. */
1210 pPml4e->u = pShwPage->Core.Key;
1211 pPml4e->n.u1Present = 1;
1212 pPml4e->n.u1Write = 1;
1213 pPml4e->n.u1Execute = 1;
1214
1215 const unsigned iPdPt = (GCPtr >> EPT_PDPT_SHIFT) & EPT_PDPT_MASK;
1216 PEPTPDPT pPdpt = (PEPTPDPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1217 PEPTPDPTE pPdpe = &pPdpt->a[iPdPt];
1218
1219 if (ppPdpt)
1220 *ppPdpt = pPdpt;
1221
1222 /* Allocate page directory if not present. */
1223 if ( !pPdpe->n.u1Present
1224 && !(pPdpe->u & EPT_PDPTE_PG_MASK))
1225 {
1226 RTGCPTR64 GCPdPt = (RTGCPTR64)iPdPt << EPT_PDPT_SHIFT;
1227
1228 rc = pgmPoolAlloc(pVM, GCPdPt, PGMPOOLKIND_64BIT_PD_FOR_PHYS, pShwPage->idx, iPdPt, &pShwPage);
1229 AssertRCReturn(rc, rc);
1230 }
1231 else
1232 {
1233 pShwPage = pgmPoolGetPage(pPool, pPdpe->u & EPT_PDPTE_PG_MASK);
1234 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1235
1236 pgmPoolCacheUsed(pPool, pShwPage);
1237 }
1238 /* The PD was cached or created; hook it up now and fill with the default value. */
1239 pPdpe->u = pShwPage->Core.Key;
1240 pPdpe->n.u1Present = 1;
1241 pPdpe->n.u1Write = 1;
1242 pPdpe->n.u1Execute = 1;
1243
1244 *ppPD = (PEPTPD)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1245 return VINF_SUCCESS;
1246}
1247
1248#endif /* IN_RC */
1249
1250/**
1251 * Gets effective Guest OS page information.
1252 *
1253 * When GCPtr is in a big page, the function will return as if it was a normal
1254 * 4KB page. If the need for distinguishing between big and normal page becomes
1255 * necessary at a later point, a PGMGstGetPage() will be created for that
1256 * purpose.
1257 *
1258 * @returns VBox status.
1259 * @param pVCpu VMCPU handle.
1260 * @param GCPtr Guest Context virtual address of the page.
1261 * @param pfFlags Where to store the flags. These are X86_PTE_*, even for big pages.
1262 * @param pGCPhys Where to store the GC physical address of the page.
1263 * This is page aligned. The fact that the
1264 */
1265VMMDECL(int) PGMGstGetPage(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys)
1266{
1267 return PGM_GST_PFN(GetPage, pVCpu)(pVCpu, GCPtr, pfFlags, pGCPhys);
1268}
1269
1270
1271/**
1272 * Checks if the page is present.
1273 *
1274 * @returns true if the page is present.
1275 * @returns false if the page is not present.
1276 * @param pVCpu VMCPU handle.
1277 * @param GCPtr Address within the page.
1278 */
1279VMMDECL(bool) PGMGstIsPagePresent(PVMCPU pVCpu, RTGCPTR GCPtr)
1280{
1281 int rc = PGMGstGetPage(pVCpu, GCPtr, NULL, NULL);
1282 return RT_SUCCESS(rc);
1283}
1284
1285
1286/**
1287 * Sets (replaces) the page flags for a range of pages in the guest's tables.
1288 *
1289 * @returns VBox status.
1290 * @param pVCpu VMCPU handle.
1291 * @param GCPtr The address of the first page.
1292 * @param cb The size of the range in bytes.
1293 * @param fFlags Page flags X86_PTE_*, excluding the page mask of course.
1294 */
1295VMMDECL(int) PGMGstSetPage(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags)
1296{
1297 return PGMGstModifyPage(pVCpu, GCPtr, cb, fFlags, 0);
1298}
1299
1300
1301/**
1302 * Modify page flags for a range of pages in the guest's tables
1303 *
1304 * The existing flags are ANDed with the fMask and ORed with the fFlags.
1305 *
1306 * @returns VBox status code.
1307 * @param pVCpu VMCPU handle.
1308 * @param GCPtr Virtual address of the first page in the range.
1309 * @param cb Size (in bytes) of the range to apply the modification to.
1310 * @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
1311 * @param fMask The AND mask - page flags X86_PTE_*, excluding the page mask of course.
1312 * Be very CAREFUL when ~'ing constants which could be 32-bit!
1313 */
1314VMMDECL(int) PGMGstModifyPage(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
1315{
1316 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_MID_Z(Stat,GstModifyPage), a);
1317
1318 /*
1319 * Validate input.
1320 */
1321 AssertMsg(!(fFlags & X86_PTE_PAE_PG_MASK), ("fFlags=%#llx\n", fFlags));
1322 Assert(cb);
1323
1324 LogFlow(("PGMGstModifyPage %RGv %d bytes fFlags=%08llx fMask=%08llx\n", GCPtr, cb, fFlags, fMask));
1325
1326 /*
1327 * Adjust input.
1328 */
1329 cb += GCPtr & PAGE_OFFSET_MASK;
1330 cb = RT_ALIGN_Z(cb, PAGE_SIZE);
1331 GCPtr = (GCPtr & PAGE_BASE_GC_MASK);
1332
1333 /*
1334 * Call worker.
1335 */
1336 int rc = PGM_GST_PFN(ModifyPage, pVCpu)(pVCpu, GCPtr, cb, fFlags, fMask);
1337
1338 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,GstModifyPage), a);
1339 return rc;
1340}
1341
1342#ifdef IN_RING3
1343
1344/**
1345 * Performs the lazy mapping of the 32-bit guest PD.
1346 *
1347 * @returns Pointer to the mapping.
1348 * @param pPGM The PGM instance data.
1349 */
1350PX86PD pgmGstLazyMap32BitPD(PPGMCPU pPGM)
1351{
1352 Assert(!pPGM->CTX_SUFF(pGst32BitPd));
1353 PVM pVM = PGMCPU2VM(pPGM);
1354 pgmLock(pVM);
1355
1356 PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, pPGM->GCPhysCR3);
1357 AssertReturn(pPage, NULL);
1358
1359 RTHCPTR HCPtrGuestCR3;
1360 int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, pPGM->GCPhysCR3 & X86_CR3_PAGE_MASK, (void **)&HCPtrGuestCR3);
1361 AssertRCReturn(rc, NULL);
1362
1363 pPGM->pGst32BitPdR3 = (R3PTRTYPE(PX86PD))HCPtrGuestCR3;
1364# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1365 pPGM->pGst32BitPdR0 = (R0PTRTYPE(PX86PD))HCPtrGuestCR3;
1366# endif
1367
1368 pgmUnlock(pVM);
1369 return pPGM->CTX_SUFF(pGst32BitPd);
1370}
1371
1372
1373/**
1374 * Performs the lazy mapping of the PAE guest PDPT.
1375 *
1376 * @returns Pointer to the mapping.
1377 * @param pPGM The PGM instance data.
1378 */
1379PX86PDPT pgmGstLazyMapPaePDPT(PPGMCPU pPGM)
1380{
1381 Assert(!pPGM->CTX_SUFF(pGstPaePdpt));
1382 PVM pVM = PGMCPU2VM(pPGM);
1383 pgmLock(pVM);
1384
1385 PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, pPGM->GCPhysCR3);
1386 AssertReturn(pPage, NULL);
1387
1388 RTHCPTR HCPtrGuestCR3;
1389 int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, pPGM->GCPhysCR3 & X86_CR3_PAE_PAGE_MASK, (void **)&HCPtrGuestCR3); /** @todo r=bird: This GCPhysR3 masking isn't necessary. */
1390 AssertRCReturn(rc, NULL);
1391
1392 pPGM->pGstPaePdptR3 = (R3PTRTYPE(PX86PDPT))HCPtrGuestCR3;
1393# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1394 pPGM->pGstPaePdptR0 = (R0PTRTYPE(PX86PDPT))HCPtrGuestCR3;
1395# endif
1396
1397 pgmUnlock(pVM);
1398 return pPGM->CTX_SUFF(pGstPaePdpt);
1399}
1400
1401#endif /* IN_RING3 */
1402
1403#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
1404/**
1405 * Performs the lazy mapping / updating of a PAE guest PD.
1406 *
1407 * @returns Pointer to the mapping.
1408 * @param pPGM The PGM instance data.
1409 * @param iPdpt Which PD entry to map (0..3).
1410 */
1411PX86PDPAE pgmGstLazyMapPaePD(PPGMCPU pPGM, uint32_t iPdpt)
1412{
1413 PVM pVM = PGMCPU2VM(pPGM);
1414 pgmLock(pVM);
1415
1416 PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
1417 Assert(pGuestPDPT);
1418 Assert(pGuestPDPT->a[iPdpt].n.u1Present);
1419 RTGCPHYS GCPhys = pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK;
1420 bool const fChanged = pPGM->aGCPhysGstPaePDs[iPdpt] != GCPhys;
1421
1422 PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, GCPhys);
1423 if (RT_LIKELY(pPage))
1424 {
1425 int rc = VINF_SUCCESS;
1426 RTRCPTR RCPtr = NIL_RTRCPTR;
1427 RTHCPTR HCPtr = NIL_RTHCPTR;
1428#if !defined(IN_RC) && !defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1429 rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, &HCPtr);
1430 AssertRC(rc);
1431#endif
1432 if (RT_SUCCESS(rc) && fChanged)
1433 {
1434 RCPtr = (RTRCPTR)(RTRCUINTPTR)(pVM->pgm.s.GCPtrCR3Mapping + (1 + iPdpt) * PAGE_SIZE);
1435 rc = PGMMap(pVM, (RTRCUINTPTR)RCPtr, PGM_PAGE_GET_HCPHYS(pPage), PAGE_SIZE, 0);
1436 }
1437 if (RT_SUCCESS(rc))
1438 {
1439 pPGM->apGstPaePDsR3[iPdpt] = (R3PTRTYPE(PX86PDPAE))HCPtr;
1440# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1441 pPGM->apGstPaePDsR0[iPdpt] = (R0PTRTYPE(PX86PDPAE))HCPtr;
1442# endif
1443 if (fChanged)
1444 {
1445 pPGM->aGCPhysGstPaePDs[iPdpt] = GCPhys;
1446 pPGM->apGstPaePDsRC[iPdpt] = (RCPTRTYPE(PX86PDPAE))RCPtr;
1447 }
1448
1449 pgmUnlock(pVM);
1450 return pPGM->CTX_SUFF(apGstPaePDs)[iPdpt];
1451 }
1452 }
1453
1454 /* Invalid page or some failure, invalidate the entry. */
1455 pPGM->aGCPhysGstPaePDs[iPdpt] = NIL_RTGCPHYS;
1456 pPGM->apGstPaePDsR3[iPdpt] = 0;
1457# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1458 pPGM->apGstPaePDsR0[iPdpt] = 0;
1459# endif
1460 pPGM->apGstPaePDsRC[iPdpt] = 0;
1461
1462 pgmUnlock(pVM);
1463 return NULL;
1464}
1465#endif /* !VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
1466
1467
1468#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R3
1469/**
1470 * Performs the lazy mapping of the 32-bit guest PD.
1471 *
1472 * @returns Pointer to the mapping.
1473 * @param pPGM The PGM instance data.
1474 */
1475PX86PML4 pgmGstLazyMapPml4(PPGMCPU pPGM)
1476{
1477 Assert(!pPGM->CTX_SUFF(pGstAmd64Pml4));
1478 PVM pVM = PGMCPU2VM(pPGM);
1479 pgmLock(pVM);
1480
1481 PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, pPGM->GCPhysCR3);
1482 AssertReturn(pPage, NULL);
1483
1484 RTHCPTR HCPtrGuestCR3;
1485 int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, pPGM->GCPhysCR3 & X86_CR3_AMD64_PAGE_MASK, (void **)&HCPtrGuestCR3); /** @todo r=bird: This GCPhysCR3 masking isn't necessary. */
1486 AssertRCReturn(rc, NULL);
1487
1488 pPGM->pGstAmd64Pml4R3 = (R3PTRTYPE(PX86PML4))HCPtrGuestCR3;
1489# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1490 pPGM->pGstAmd64Pml4R0 = (R0PTRTYPE(PX86PML4))HCPtrGuestCR3;
1491# endif
1492
1493 pgmUnlock(pVM);
1494 return pPGM->CTX_SUFF(pGstAmd64Pml4);
1495}
1496#endif /* VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R3 */
1497
1498
1499/**
1500 * Gets the specified page directory pointer table entry.
1501 *
1502 * @returns PDP entry
1503 * @param pVCpu VMCPU handle.
1504 * @param iPdpt PDPT index
1505 */
1506VMMDECL(X86PDPE) PGMGstGetPaePDPtr(PVMCPU pVCpu, unsigned iPdpt)
1507{
1508 Assert(iPdpt <= 3);
1509 return pgmGstGetPaePDPTPtr(&pVCpu->pgm.s)->a[iPdpt & 3];
1510}
1511
1512
1513/**
1514 * Gets the current CR3 register value for the shadow memory context.
1515 * @returns CR3 value.
1516 * @param pVCpu VMCPU handle.
1517 */
1518VMMDECL(RTHCPHYS) PGMGetHyperCR3(PVMCPU pVCpu)
1519{
1520 PPGMPOOLPAGE pPoolPage = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
1521 AssertPtrReturn(pPoolPage, 0);
1522 return pPoolPage->Core.Key;
1523}
1524
1525
1526/**
1527 * Gets the current CR3 register value for the nested memory context.
1528 * @returns CR3 value.
1529 * @param pVCpu VMCPU handle.
1530 */
1531VMMDECL(RTHCPHYS) PGMGetNestedCR3(PVMCPU pVCpu, PGMMODE enmShadowMode)
1532{
1533 Assert(pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
1534 return pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->Core.Key;
1535}
1536
1537
1538/**
1539 * Gets the current CR3 register value for the HC intermediate memory context.
1540 * @returns CR3 value.
1541 * @param pVM The VM handle.
1542 */
1543VMMDECL(RTHCPHYS) PGMGetInterHCCR3(PVM pVM)
1544{
1545 switch (pVM->pgm.s.enmHostMode)
1546 {
1547 case SUPPAGINGMODE_32_BIT:
1548 case SUPPAGINGMODE_32_BIT_GLOBAL:
1549 return pVM->pgm.s.HCPhysInterPD;
1550
1551 case SUPPAGINGMODE_PAE:
1552 case SUPPAGINGMODE_PAE_GLOBAL:
1553 case SUPPAGINGMODE_PAE_NX:
1554 case SUPPAGINGMODE_PAE_GLOBAL_NX:
1555 return pVM->pgm.s.HCPhysInterPaePDPT;
1556
1557 case SUPPAGINGMODE_AMD64:
1558 case SUPPAGINGMODE_AMD64_GLOBAL:
1559 case SUPPAGINGMODE_AMD64_NX:
1560 case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1561 return pVM->pgm.s.HCPhysInterPaePDPT;
1562
1563 default:
1564 AssertMsgFailed(("enmHostMode=%d\n", pVM->pgm.s.enmHostMode));
1565 return ~0;
1566 }
1567}
1568
1569
1570/**
1571 * Gets the current CR3 register value for the RC intermediate memory context.
1572 * @returns CR3 value.
1573 * @param pVM The VM handle.
1574 * @param pVCpu VMCPU handle.
1575 */
1576VMMDECL(RTHCPHYS) PGMGetInterRCCR3(PVM pVM, PVMCPU pVCpu)
1577{
1578 switch (pVCpu->pgm.s.enmShadowMode)
1579 {
1580 case PGMMODE_32_BIT:
1581 return pVM->pgm.s.HCPhysInterPD;
1582
1583 case PGMMODE_PAE:
1584 case PGMMODE_PAE_NX:
1585 return pVM->pgm.s.HCPhysInterPaePDPT;
1586
1587 case PGMMODE_AMD64:
1588 case PGMMODE_AMD64_NX:
1589 return pVM->pgm.s.HCPhysInterPaePML4;
1590
1591 case PGMMODE_EPT:
1592 case PGMMODE_NESTED:
1593 return 0; /* not relevant */
1594
1595 default:
1596 AssertMsgFailed(("enmShadowMode=%d\n", pVCpu->pgm.s.enmShadowMode));
1597 return ~0;
1598 }
1599}
1600
1601
1602/**
1603 * Gets the CR3 register value for the 32-Bit intermediate memory context.
1604 * @returns CR3 value.
1605 * @param pVM The VM handle.
1606 */
1607VMMDECL(RTHCPHYS) PGMGetInter32BitCR3(PVM pVM)
1608{
1609 return pVM->pgm.s.HCPhysInterPD;
1610}
1611
1612
1613/**
1614 * Gets the CR3 register value for the PAE intermediate memory context.
1615 * @returns CR3 value.
1616 * @param pVM The VM handle.
1617 */
1618VMMDECL(RTHCPHYS) PGMGetInterPaeCR3(PVM pVM)
1619{
1620 return pVM->pgm.s.HCPhysInterPaePDPT;
1621}
1622
1623
1624/**
1625 * Gets the CR3 register value for the AMD64 intermediate memory context.
1626 * @returns CR3 value.
1627 * @param pVM The VM handle.
1628 */
1629VMMDECL(RTHCPHYS) PGMGetInterAmd64CR3(PVM pVM)
1630{
1631 return pVM->pgm.s.HCPhysInterPaePML4;
1632}
1633
1634
1635/**
1636 * Performs and schedules necessary updates following a CR3 load or reload.
1637 *
1638 * This will normally involve mapping the guest PD or nPDPT
1639 *
1640 * @returns VBox status code.
1641 * @retval VINF_PGM_SYNC_CR3 if monitoring requires a CR3 sync. This can
1642 * safely be ignored and overridden since the FF will be set too then.
1643 * @param pVCpu VMCPU handle.
1644 * @param cr3 The new cr3.
1645 * @param fGlobal Indicates whether this is a global flush or not.
1646 */
1647VMMDECL(int) PGMFlushTLB(PVMCPU pVCpu, uint64_t cr3, bool fGlobal)
1648{
1649 PVM pVM = pVCpu->CTX_SUFF(pVM);
1650
1651 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_MID_Z(Stat,FlushTLB), a);
1652
1653 /*
1654 * Always flag the necessary updates; necessary for hardware acceleration
1655 */
1656 /** @todo optimize this, it shouldn't always be necessary. */
1657 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
1658 if (fGlobal)
1659 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
1660 LogFlow(("PGMFlushTLB: cr3=%RX64 OldCr3=%RX64 fGlobal=%d\n", cr3, pVCpu->pgm.s.GCPhysCR3, fGlobal));
1661
1662 /*
1663 * Remap the CR3 content and adjust the monitoring if CR3 was actually changed.
1664 */
1665 int rc = VINF_SUCCESS;
1666 RTGCPHYS GCPhysCR3;
1667 switch (pVCpu->pgm.s.enmGuestMode)
1668 {
1669 case PGMMODE_PAE:
1670 case PGMMODE_PAE_NX:
1671 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAE_PAGE_MASK);
1672 break;
1673 case PGMMODE_AMD64:
1674 case PGMMODE_AMD64_NX:
1675 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_AMD64_PAGE_MASK);
1676 break;
1677 default:
1678 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAGE_MASK);
1679 break;
1680 }
1681
1682 if (pVCpu->pgm.s.GCPhysCR3 != GCPhysCR3)
1683 {
1684 RTGCPHYS GCPhysOldCR3 = pVCpu->pgm.s.GCPhysCR3;
1685 pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3;
1686 rc = PGM_BTH_PFN(MapCR3, pVCpu)(pVCpu, GCPhysCR3);
1687 if (RT_LIKELY(rc == VINF_SUCCESS))
1688 {
1689 if (pgmMapAreMappingsFloating(&pVM->pgm.s))
1690 pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
1691 }
1692 else
1693 {
1694 AssertMsg(rc == VINF_PGM_SYNC_CR3, ("%Rrc\n", rc));
1695 Assert(VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL | VMCPU_FF_PGM_SYNC_CR3));
1696 pVCpu->pgm.s.GCPhysCR3 = GCPhysOldCR3;
1697 pVCpu->pgm.s.fSyncFlags |= PGM_SYNC_MAP_CR3;
1698 if (pgmMapAreMappingsFloating(&pVM->pgm.s))
1699 pVCpu->pgm.s.fSyncFlags |= PGM_SYNC_MONITOR_CR3;
1700 }
1701
1702 if (fGlobal)
1703 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,FlushTLBNewCR3Global));
1704 else
1705 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,FlushTLBNewCR3));
1706 }
1707 else
1708 {
1709# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
1710 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1711 if (pPool->cDirtyPages)
1712 {
1713 pgmLock(pVM);
1714 pgmPoolResetDirtyPages(pVM);
1715 pgmUnlock(pVM);
1716 }
1717# endif
1718 /*
1719 * Check if we have a pending update of the CR3 monitoring.
1720 */
1721 if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
1722 {
1723 pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
1724 Assert(!pVM->pgm.s.fMappingsFixed); Assert(!pVM->pgm.s.fMappingsDisabled);
1725 }
1726 if (fGlobal)
1727 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,FlushTLBSameCR3Global));
1728 else
1729 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,FlushTLBSameCR3));
1730 }
1731
1732 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,FlushTLB), a);
1733 return rc;
1734}
1735
1736
1737/**
1738 * Performs and schedules necessary updates following a CR3 load or reload when
1739 * using nested or extended paging.
1740 *
1741 * This API is an alterantive to PDMFlushTLB that avoids actually flushing the
1742 * TLB and triggering a SyncCR3.
1743 *
1744 * This will normally involve mapping the guest PD or nPDPT
1745 *
1746 * @returns VBox status code.
1747 * @retval VINF_SUCCESS.
1748 * @retval (If applied when not in nested mode: VINF_PGM_SYNC_CR3 if monitoring
1749 * requires a CR3 sync. This can safely be ignored and overridden since
1750 * the FF will be set too then.)
1751 * @param pVCpu VMCPU handle.
1752 * @param cr3 The new cr3.
1753 */
1754VMMDECL(int) PGMUpdateCR3(PVMCPU pVCpu, uint64_t cr3)
1755{
1756 PVM pVM = pVCpu->CTX_SUFF(pVM);
1757
1758 LogFlow(("PGMUpdateCR3: cr3=%RX64 OldCr3=%RX64\n", cr3, pVCpu->pgm.s.GCPhysCR3));
1759
1760 /* We assume we're only called in nested paging mode. */
1761 Assert(HWACCMIsNestedPagingActive(pVM) || pVCpu->pgm.s.enmShadowMode == PGMMODE_EPT);
1762 Assert(pVM->pgm.s.fMappingsDisabled);
1763 Assert(!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3));
1764
1765 /*
1766 * Remap the CR3 content and adjust the monitoring if CR3 was actually changed.
1767 */
1768 int rc = VINF_SUCCESS;
1769 RTGCPHYS GCPhysCR3;
1770 switch (pVCpu->pgm.s.enmGuestMode)
1771 {
1772 case PGMMODE_PAE:
1773 case PGMMODE_PAE_NX:
1774 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAE_PAGE_MASK);
1775 break;
1776 case PGMMODE_AMD64:
1777 case PGMMODE_AMD64_NX:
1778 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_AMD64_PAGE_MASK);
1779 break;
1780 default:
1781 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAGE_MASK);
1782 break;
1783 }
1784 if (pVCpu->pgm.s.GCPhysCR3 != GCPhysCR3)
1785 {
1786 pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3;
1787 rc = PGM_BTH_PFN(MapCR3, pVCpu)(pVCpu, GCPhysCR3);
1788 AssertRCSuccess(rc); /* Assumes VINF_PGM_SYNC_CR3 doesn't apply to nested paging. */ /** @todo this isn't true for the mac, but we need hw to test/fix this. */
1789 }
1790 return rc;
1791}
1792
1793
1794/**
1795 * Synchronize the paging structures.
1796 *
1797 * This function is called in response to the VM_FF_PGM_SYNC_CR3 and
1798 * VM_FF_PGM_SYNC_CR3_NONGLOBAL. Those two force action flags are set
1799 * in several places, most importantly whenever the CR3 is loaded.
1800 *
1801 * @returns VBox status code.
1802 * @param pVCpu VMCPU handle.
1803 * @param cr0 Guest context CR0 register
1804 * @param cr3 Guest context CR3 register
1805 * @param cr4 Guest context CR4 register
1806 * @param fGlobal Including global page directories or not
1807 */
1808VMMDECL(int) PGMSyncCR3(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
1809{
1810 PVM pVM = pVCpu->CTX_SUFF(pVM);
1811 int rc;
1812
1813 /*
1814 * The pool may have pending stuff and even require a return to ring-3 to
1815 * clear the whole thing.
1816 */
1817 rc = pgmPoolSyncCR3(pVCpu);
1818 if (rc != VINF_SUCCESS)
1819 return rc;
1820
1821 /*
1822 * We might be called when we shouldn't.
1823 *
1824 * The mode switching will ensure that the PD is resynced
1825 * after every mode switch. So, if we find ourselves here
1826 * when in protected or real mode we can safely disable the
1827 * FF and return immediately.
1828 */
1829 if (pVCpu->pgm.s.enmGuestMode <= PGMMODE_PROTECTED)
1830 {
1831 Assert((cr0 & (X86_CR0_PG | X86_CR0_PE)) != (X86_CR0_PG | X86_CR0_PE));
1832 Assert(!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL));
1833 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
1834 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
1835 return VINF_SUCCESS;
1836 }
1837
1838 /* If global pages are not supported, then all flushes are global. */
1839 if (!(cr4 & X86_CR4_PGE))
1840 fGlobal = true;
1841 LogFlow(("PGMSyncCR3: cr0=%RX64 cr3=%RX64 cr4=%RX64 fGlobal=%d[%d,%d]\n", cr0, cr3, cr4, fGlobal,
1842 VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3), VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)));
1843
1844 /*
1845 * Check if we need to finish an aborted MapCR3 call (see PGMFlushTLB).
1846 * This should be done before SyncCR3.
1847 */
1848 if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MAP_CR3)
1849 {
1850 pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MAP_CR3;
1851
1852 RTGCPHYS GCPhysCR3Old = pVCpu->pgm.s.GCPhysCR3;
1853 RTGCPHYS GCPhysCR3;
1854 switch (pVCpu->pgm.s.enmGuestMode)
1855 {
1856 case PGMMODE_PAE:
1857 case PGMMODE_PAE_NX:
1858 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAE_PAGE_MASK);
1859 break;
1860 case PGMMODE_AMD64:
1861 case PGMMODE_AMD64_NX:
1862 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_AMD64_PAGE_MASK);
1863 break;
1864 default:
1865 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAGE_MASK);
1866 break;
1867 }
1868
1869 if (pVCpu->pgm.s.GCPhysCR3 != GCPhysCR3)
1870 {
1871 pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3;
1872 rc = PGM_BTH_PFN(MapCR3, pVCpu)(pVCpu, GCPhysCR3);
1873 }
1874 /* Make sure we check for pending pgm pool syncs as we clear VMCPU_FF_PGM_SYNC_CR3 later on! */
1875 if ( rc == VINF_PGM_SYNC_CR3
1876 || (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL))
1877 {
1878 Log(("PGMSyncCR3: pending pgm pool sync after MapCR3!\n"));
1879#ifdef IN_RING3
1880 rc = pgmPoolSyncCR3(pVCpu);
1881#else
1882 if (rc == VINF_PGM_SYNC_CR3)
1883 pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3Old;
1884 return VINF_PGM_SYNC_CR3;
1885#endif
1886 }
1887 AssertRCReturn(rc, rc);
1888 AssertRCSuccessReturn(rc, VERR_INTERNAL_ERROR);
1889 }
1890
1891 /*
1892 * Let the 'Bth' function do the work and we'll just keep track of the flags.
1893 */
1894 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncCR3), a);
1895 rc = PGM_BTH_PFN(SyncCR3, pVCpu)(pVCpu, cr0, cr3, cr4, fGlobal);
1896 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncCR3), a);
1897 AssertMsg(rc == VINF_SUCCESS || rc == VINF_PGM_SYNC_CR3 || RT_FAILURE(rc), ("rc=%Rrc\n", rc));
1898 if (rc == VINF_SUCCESS)
1899 {
1900 if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL)
1901 {
1902 /* Go back to ring 3 if a pgm pool sync is again pending. */
1903 return VINF_PGM_SYNC_CR3;
1904 }
1905
1906 if (!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS))
1907 {
1908 Assert(!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL));
1909 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
1910 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
1911 }
1912
1913 /*
1914 * Check if we have a pending update of the CR3 monitoring.
1915 */
1916 if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
1917 {
1918 pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
1919 Assert(!pVM->pgm.s.fMappingsFixed); Assert(!pVM->pgm.s.fMappingsDisabled);
1920 }
1921 }
1922
1923 /*
1924 * Now flush the CR3 (guest context).
1925 */
1926 if (rc == VINF_SUCCESS)
1927 PGM_INVL_VCPU_TLBS(pVCpu);
1928 return rc;
1929}
1930
1931
1932/**
1933 * Called whenever CR0 or CR4 in a way which may change
1934 * the paging mode.
1935 *
1936 * @returns VBox status code, with the following informational code for
1937 * VM scheduling.
1938 * @retval VINF_SUCCESS if the was no change, or it was successfully dealt with.
1939 * @retval VINF_PGM_CHANGE_MODE if we're in RC or R0 and the mode changes.
1940 * (I.e. not in R3.)
1941 * @retval VINF_EM_SUSPEND or VINF_EM_OFF on a fatal runtime error. (R3 only)
1942 *
1943 * @param pVCpu VMCPU handle.
1944 * @param cr0 The new cr0.
1945 * @param cr4 The new cr4.
1946 * @param efer The new extended feature enable register.
1947 */
1948VMMDECL(int) PGMChangeMode(PVMCPU pVCpu, uint64_t cr0, uint64_t cr4, uint64_t efer)
1949{
1950 PVM pVM = pVCpu->CTX_SUFF(pVM);
1951 PGMMODE enmGuestMode;
1952
1953 /*
1954 * Calc the new guest mode.
1955 */
1956 if (!(cr0 & X86_CR0_PE))
1957 enmGuestMode = PGMMODE_REAL;
1958 else if (!(cr0 & X86_CR0_PG))
1959 enmGuestMode = PGMMODE_PROTECTED;
1960 else if (!(cr4 & X86_CR4_PAE))
1961 enmGuestMode = PGMMODE_32_BIT;
1962 else if (!(efer & MSR_K6_EFER_LME))
1963 {
1964 if (!(efer & MSR_K6_EFER_NXE))
1965 enmGuestMode = PGMMODE_PAE;
1966 else
1967 enmGuestMode = PGMMODE_PAE_NX;
1968 }
1969 else
1970 {
1971 if (!(efer & MSR_K6_EFER_NXE))
1972 enmGuestMode = PGMMODE_AMD64;
1973 else
1974 enmGuestMode = PGMMODE_AMD64_NX;
1975 }
1976
1977 /*
1978 * Did it change?
1979 */
1980 if (pVCpu->pgm.s.enmGuestMode == enmGuestMode)
1981 return VINF_SUCCESS;
1982
1983 /* Flush the TLB */
1984 PGM_INVL_VCPU_TLBS(pVCpu);
1985
1986#ifdef IN_RING3
1987 return PGMR3ChangeMode(pVM, pVCpu, enmGuestMode);
1988#else
1989 LogFlow(("PGMChangeMode: returns VINF_PGM_CHANGE_MODE.\n"));
1990 return VINF_PGM_CHANGE_MODE;
1991#endif
1992}
1993
1994
1995/**
1996 * Gets the current guest paging mode.
1997 *
1998 * If you just need the CPU mode (real/protected/long), use CPUMGetGuestMode().
1999 *
2000 * @returns The current paging mode.
2001 * @param pVCpu VMCPU handle.
2002 */
2003VMMDECL(PGMMODE) PGMGetGuestMode(PVMCPU pVCpu)
2004{
2005 return pVCpu->pgm.s.enmGuestMode;
2006}
2007
2008
2009/**
2010 * Gets the current shadow paging mode.
2011 *
2012 * @returns The current paging mode.
2013 * @param pVCpu VMCPU handle.
2014 */
2015VMMDECL(PGMMODE) PGMGetShadowMode(PVMCPU pVCpu)
2016{
2017 return pVCpu->pgm.s.enmShadowMode;
2018}
2019
2020/**
2021 * Gets the current host paging mode.
2022 *
2023 * @returns The current paging mode.
2024 * @param pVM The VM handle.
2025 */
2026VMMDECL(PGMMODE) PGMGetHostMode(PVM pVM)
2027{
2028 switch (pVM->pgm.s.enmHostMode)
2029 {
2030 case SUPPAGINGMODE_32_BIT:
2031 case SUPPAGINGMODE_32_BIT_GLOBAL:
2032 return PGMMODE_32_BIT;
2033
2034 case SUPPAGINGMODE_PAE:
2035 case SUPPAGINGMODE_PAE_GLOBAL:
2036 return PGMMODE_PAE;
2037
2038 case SUPPAGINGMODE_PAE_NX:
2039 case SUPPAGINGMODE_PAE_GLOBAL_NX:
2040 return PGMMODE_PAE_NX;
2041
2042 case SUPPAGINGMODE_AMD64:
2043 case SUPPAGINGMODE_AMD64_GLOBAL:
2044 return PGMMODE_AMD64;
2045
2046 case SUPPAGINGMODE_AMD64_NX:
2047 case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2048 return PGMMODE_AMD64_NX;
2049
2050 default: AssertMsgFailed(("enmHostMode=%d\n", pVM->pgm.s.enmHostMode)); break;
2051 }
2052
2053 return PGMMODE_INVALID;
2054}
2055
2056
2057/**
2058 * Get mode name.
2059 *
2060 * @returns read-only name string.
2061 * @param enmMode The mode which name is desired.
2062 */
2063VMMDECL(const char *) PGMGetModeName(PGMMODE enmMode)
2064{
2065 switch (enmMode)
2066 {
2067 case PGMMODE_REAL: return "Real";
2068 case PGMMODE_PROTECTED: return "Protected";
2069 case PGMMODE_32_BIT: return "32-bit";
2070 case PGMMODE_PAE: return "PAE";
2071 case PGMMODE_PAE_NX: return "PAE+NX";
2072 case PGMMODE_AMD64: return "AMD64";
2073 case PGMMODE_AMD64_NX: return "AMD64+NX";
2074 case PGMMODE_NESTED: return "Nested";
2075 case PGMMODE_EPT: return "EPT";
2076 default: return "unknown mode value";
2077 }
2078}
2079
2080
2081/**
2082 * Check if any pgm pool pages are marked dirty (not monitored)
2083 *
2084 * @returns bool locked/not locked
2085 * @param pVM The VM to operate on.
2086 */
2087VMMDECL(bool) PGMHasDirtyPages(PVM pVM)
2088{
2089 return pVM->pgm.s.CTX_SUFF(pPool)->cDirtyPages != 0;
2090}
2091
2092/**
2093 * Check if the PGM lock is currently taken.
2094 *
2095 * @returns bool locked/not locked
2096 * @param pVM The VM to operate on.
2097 */
2098VMMDECL(bool) PGMIsLocked(PVM pVM)
2099{
2100 return PDMCritSectIsOwned(&pVM->pgm.s.CritSect);
2101}
2102
2103
2104/**
2105 * Check if this VCPU currently owns the PGM lock.
2106 *
2107 * @returns bool owner/not owner
2108 * @param pVM The VM to operate on.
2109 */
2110VMMDECL(bool) PGMIsLockOwner(PVM pVM)
2111{
2112 return PDMCritSectIsOwner(&pVM->pgm.s.CritSect);
2113}
2114
2115
2116/**
2117 * Enable or disable large page usage
2118 *
2119 * @param pVM The VM to operate on.
2120 * @param fUseLargePages Use/not use large pages
2121 */
2122VMMDECL(void) PGMSetLargePageUsage(PVM pVM, bool fUseLargePages)
2123{
2124 pVM->fUseLargePages = fUseLargePages;
2125}
2126
2127/**
2128 * Acquire the PGM lock.
2129 *
2130 * @returns VBox status code
2131 * @param pVM The VM to operate on.
2132 */
2133int pgmLock(PVM pVM)
2134{
2135 int rc = PDMCritSectEnter(&pVM->pgm.s.CritSect, VERR_SEM_BUSY);
2136#if defined(IN_RC) || defined(IN_RING0)
2137 if (rc == VERR_SEM_BUSY)
2138 rc = VMMRZCallRing3NoCpu(pVM, VMMCALLRING3_PGM_LOCK, 0);
2139#endif
2140 AssertMsg(rc == VINF_SUCCESS, ("%Rrc\n", rc));
2141 return rc;
2142}
2143
2144
2145/**
2146 * Release the PGM lock.
2147 *
2148 * @returns VBox status code
2149 * @param pVM The VM to operate on.
2150 */
2151void pgmUnlock(PVM pVM)
2152{
2153 PDMCritSectLeave(&pVM->pgm.s.CritSect);
2154}
2155
2156#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2157
2158/**
2159 * Temporarily maps one guest page specified by GC physical address.
2160 * These pages must have a physical mapping in HC, i.e. they cannot be MMIO pages.
2161 *
2162 * Be WARNED that the dynamic page mapping area is small, 8 pages, thus the space is
2163 * reused after 8 mappings (or perhaps a few more if you score with the cache).
2164 *
2165 * @returns VBox status.
2166 * @param pVM VM handle.
2167 * @param GCPhys GC Physical address of the page.
2168 * @param ppv Where to store the address of the mapping.
2169 */
2170VMMDECL(int) PGMDynMapGCPage(PVM pVM, RTGCPHYS GCPhys, void **ppv)
2171{
2172 AssertMsg(!(GCPhys & PAGE_OFFSET_MASK), ("GCPhys=%RGp\n", GCPhys));
2173
2174 /*
2175 * Get the ram range.
2176 */
2177 PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
2178 while (pRam && GCPhys - pRam->GCPhys >= pRam->cb)
2179 pRam = pRam->CTX_SUFF(pNext);
2180 if (!pRam)
2181 {
2182 AssertMsgFailed(("Invalid physical address %RGp!\n", GCPhys));
2183 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2184 }
2185
2186 /*
2187 * Pass it on to PGMDynMapHCPage.
2188 */
2189 RTHCPHYS HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT]);
2190 //Log(("PGMDynMapGCPage: GCPhys=%RGp HCPhys=%RHp\n", GCPhys, HCPhys));
2191#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2192 pgmR0DynMapHCPageInlined(&pVM->pgm.s, HCPhys, ppv);
2193#else
2194 PGMDynMapHCPage(pVM, HCPhys, ppv);
2195#endif
2196 return VINF_SUCCESS;
2197}
2198
2199
2200/**
2201 * Temporarily maps one guest page specified by unaligned GC physical address.
2202 * These pages must have a physical mapping in HC, i.e. they cannot be MMIO pages.
2203 *
2204 * Be WARNED that the dynamic page mapping area is small, 8 pages, thus the space is
2205 * reused after 8 mappings (or perhaps a few more if you score with the cache).
2206 *
2207 * The caller is aware that only the speicifed page is mapped and that really bad things
2208 * will happen if writing beyond the page!
2209 *
2210 * @returns VBox status.
2211 * @param pVM VM handle.
2212 * @param GCPhys GC Physical address within the page to be mapped.
2213 * @param ppv Where to store the address of the mapping address corresponding to GCPhys.
2214 */
2215VMMDECL(int) PGMDynMapGCPageOff(PVM pVM, RTGCPHYS GCPhys, void **ppv)
2216{
2217 /*
2218 * Get the ram range.
2219 */
2220 PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
2221 while (pRam && GCPhys - pRam->GCPhys >= pRam->cb)
2222 pRam = pRam->CTX_SUFF(pNext);
2223 if (!pRam)
2224 {
2225 AssertMsgFailed(("Invalid physical address %RGp!\n", GCPhys));
2226 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2227 }
2228
2229 /*
2230 * Pass it on to PGMDynMapHCPage.
2231 */
2232 RTHCPHYS HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT]);
2233#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2234 pgmR0DynMapHCPageInlined(&pVM->pgm.s, HCPhys, ppv);
2235#else
2236 PGMDynMapHCPage(pVM, HCPhys, ppv);
2237#endif
2238 *ppv = (void *)((uintptr_t)*ppv | (uintptr_t)(GCPhys & PAGE_OFFSET_MASK));
2239 return VINF_SUCCESS;
2240}
2241
2242# ifdef IN_RC
2243
2244/**
2245 * Temporarily maps one host page specified by HC physical address.
2246 *
2247 * Be WARNED that the dynamic page mapping area is small, 16 pages, thus the space is
2248 * reused after 16 mappings (or perhaps a few more if you score with the cache).
2249 *
2250 * @returns VINF_SUCCESS, will bail out to ring-3 on failure.
2251 * @param pVM VM handle.
2252 * @param HCPhys HC Physical address of the page.
2253 * @param ppv Where to store the address of the mapping. This is the
2254 * address of the PAGE not the exact address corresponding
2255 * to HCPhys. Use PGMDynMapHCPageOff if you care for the
2256 * page offset.
2257 */
2258VMMDECL(int) PGMDynMapHCPage(PVM pVM, RTHCPHYS HCPhys, void **ppv)
2259{
2260 AssertMsg(!(HCPhys & PAGE_OFFSET_MASK), ("HCPhys=%RHp\n", HCPhys));
2261
2262 /*
2263 * Check the cache.
2264 */
2265 register unsigned iCache;
2266 for (iCache = 0;iCache < RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache);iCache++)
2267 {
2268 static const uint8_t au8Trans[MM_HYPER_DYNAMIC_SIZE >> PAGE_SHIFT][RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache)] =
2269 {
2270 { 0, 9, 10, 11, 12, 13, 14, 15},
2271 { 0, 1, 10, 11, 12, 13, 14, 15},
2272 { 0, 1, 2, 11, 12, 13, 14, 15},
2273 { 0, 1, 2, 3, 12, 13, 14, 15},
2274 { 0, 1, 2, 3, 4, 13, 14, 15},
2275 { 0, 1, 2, 3, 4, 5, 14, 15},
2276 { 0, 1, 2, 3, 4, 5, 6, 15},
2277 { 0, 1, 2, 3, 4, 5, 6, 7},
2278 { 8, 1, 2, 3, 4, 5, 6, 7},
2279 { 8, 9, 2, 3, 4, 5, 6, 7},
2280 { 8, 9, 10, 3, 4, 5, 6, 7},
2281 { 8, 9, 10, 11, 4, 5, 6, 7},
2282 { 8, 9, 10, 11, 12, 5, 6, 7},
2283 { 8, 9, 10, 11, 12, 13, 6, 7},
2284 { 8, 9, 10, 11, 12, 13, 14, 7},
2285 { 8, 9, 10, 11, 12, 13, 14, 15},
2286 };
2287 AssertCompile(RT_ELEMENTS(au8Trans) == 16);
2288 AssertCompile(RT_ELEMENTS(au8Trans[0]) == 8);
2289
2290 if (pVM->pgm.s.aHCPhysDynPageMapCache[iCache] == HCPhys)
2291 {
2292 int iPage = au8Trans[pVM->pgm.s.iDynPageMapLast][iCache];
2293
2294 /* The cache can get out of sync with locked entries. (10 locked, 2 overwrites its cache position, last = 11, lookup 2 -> page 10 instead of 2) */
2295 if ((pVM->pgm.s.paDynPageMap32BitPTEsGC[iPage].u & X86_PTE_PG_MASK) == HCPhys)
2296 {
2297 void *pv = pVM->pgm.s.pbDynPageMapBaseGC + (iPage << PAGE_SHIFT);
2298 *ppv = pv;
2299 STAM_COUNTER_INC(&pVM->pgm.s.StatRCDynMapCacheHits);
2300 Log4(("PGMGCDynMapHCPage: HCPhys=%RHp pv=%p iPage=%d iCache=%d\n", HCPhys, pv, iPage, iCache));
2301 return VINF_SUCCESS;
2302 }
2303 LogFlow(("Out of sync entry %d\n", iPage));
2304 }
2305 }
2306 AssertCompile(RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache) == 8);
2307 AssertCompile((MM_HYPER_DYNAMIC_SIZE >> PAGE_SHIFT) == 16);
2308 STAM_COUNTER_INC(&pVM->pgm.s.StatRCDynMapCacheMisses);
2309
2310 /*
2311 * Update the page tables.
2312 */
2313 unsigned iPage = pVM->pgm.s.iDynPageMapLast;
2314 unsigned i;
2315 for (i = 0; i < (MM_HYPER_DYNAMIC_SIZE >> PAGE_SHIFT); i++)
2316 {
2317 pVM->pgm.s.iDynPageMapLast = iPage = (iPage + 1) & ((MM_HYPER_DYNAMIC_SIZE >> PAGE_SHIFT) - 1);
2318 if (!pVM->pgm.s.aLockedDynPageMapCache[iPage])
2319 break;
2320 iPage++;
2321 }
2322 AssertRelease(i != (MM_HYPER_DYNAMIC_SIZE >> PAGE_SHIFT));
2323
2324 pVM->pgm.s.aHCPhysDynPageMapCache[iPage & (RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache) - 1)] = HCPhys;
2325 pVM->pgm.s.paDynPageMap32BitPTEsGC[iPage].u = (uint32_t)HCPhys | X86_PTE_P | X86_PTE_A | X86_PTE_D;
2326 pVM->pgm.s.paDynPageMapPaePTEsGC[iPage].u = HCPhys | X86_PTE_P | X86_PTE_A | X86_PTE_D;
2327 pVM->pgm.s.aLockedDynPageMapCache[iPage] = 0;
2328
2329 void *pv = pVM->pgm.s.pbDynPageMapBaseGC + (iPage << PAGE_SHIFT);
2330 *ppv = pv;
2331 ASMInvalidatePage(pv);
2332 Log4(("PGMGCDynMapHCPage: HCPhys=%RHp pv=%p iPage=%d\n", HCPhys, pv, iPage));
2333 return VINF_SUCCESS;
2334}
2335
2336
2337/**
2338 * Temporarily lock a dynamic page to prevent it from being reused.
2339 *
2340 * @param pVM VM handle.
2341 * @param GCPage GC address of page
2342 */
2343VMMDECL(void) PGMDynLockHCPage(PVM pVM, RCPTRTYPE(uint8_t *) GCPage)
2344{
2345 unsigned iPage;
2346
2347 Assert(GCPage >= pVM->pgm.s.pbDynPageMapBaseGC && GCPage < (pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE));
2348 iPage = ((uintptr_t)(GCPage - pVM->pgm.s.pbDynPageMapBaseGC)) >> PAGE_SHIFT;
2349 ASMAtomicIncU32(&pVM->pgm.s.aLockedDynPageMapCache[iPage]);
2350 Log4(("PGMDynLockHCPage %RRv iPage=%d\n", GCPage, iPage));
2351}
2352
2353
2354/**
2355 * Unlock a dynamic page
2356 *
2357 * @param pVM VM handle.
2358 * @param GCPage GC address of page
2359 */
2360VMMDECL(void) PGMDynUnlockHCPage(PVM pVM, RCPTRTYPE(uint8_t *) GCPage)
2361{
2362 unsigned iPage;
2363
2364 AssertCompile(RT_ELEMENTS(pVM->pgm.s.aLockedDynPageMapCache) == 2* RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache));
2365 AssertCompileMemberSize(VM, pgm.s.aLockedDynPageMapCache, sizeof(uint32_t) * (MM_HYPER_DYNAMIC_SIZE >> (PAGE_SHIFT)));
2366
2367 Assert(GCPage >= pVM->pgm.s.pbDynPageMapBaseGC && GCPage < (pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE));
2368 iPage = ((uintptr_t)(GCPage - pVM->pgm.s.pbDynPageMapBaseGC)) >> PAGE_SHIFT;
2369 Assert(pVM->pgm.s.aLockedDynPageMapCache[iPage]);
2370 ASMAtomicDecU32(&pVM->pgm.s.aLockedDynPageMapCache[iPage]);
2371 Log4(("PGMDynUnlockHCPage %RRv iPage=%d\n", GCPage, iPage));
2372}
2373
2374
2375# ifdef VBOX_STRICT
2376/**
2377 * Check for lock leaks.
2378 *
2379 * @param pVM VM handle.
2380 */
2381VMMDECL(void) PGMDynCheckLocks(PVM pVM)
2382{
2383 for (unsigned i=0;i<RT_ELEMENTS(pVM->pgm.s.aLockedDynPageMapCache);i++)
2384 Assert(!pVM->pgm.s.aLockedDynPageMapCache[i]);
2385}
2386# endif /* VBOX_STRICT */
2387
2388# endif /* IN_RC */
2389#endif /* IN_RC || VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
2390
2391#if !defined(IN_R0) || defined(LOG_ENABLED)
2392
2393/** Format handler for PGMPAGE.
2394 * @copydoc FNRTSTRFORMATTYPE */
2395static DECLCALLBACK(size_t) pgmFormatTypeHandlerPage(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
2396 const char *pszType, void const *pvValue,
2397 int cchWidth, int cchPrecision, unsigned fFlags,
2398 void *pvUser)
2399{
2400 size_t cch;
2401 PCPGMPAGE pPage = (PCPGMPAGE)pvValue;
2402 if (VALID_PTR(pPage))
2403 {
2404 char szTmp[64+80];
2405
2406 cch = 0;
2407
2408 /* The single char state stuff. */
2409 static const char s_achPageStates[4] = { 'Z', 'A', 'W', 'S' };
2410 szTmp[cch++] = s_achPageStates[PGM_PAGE_GET_STATE(pPage)];
2411
2412#define IS_PART_INCLUDED(lvl) ( !(fFlags & RTSTR_F_PRECISION) || cchPrecision == (lvl) || cchPrecision >= (lvl)+10 )
2413 if (IS_PART_INCLUDED(5))
2414 {
2415 static const char s_achHandlerStates[4] = { '-', 't', 'w', 'a' };
2416 szTmp[cch++] = s_achHandlerStates[PGM_PAGE_GET_HNDL_PHYS_STATE(pPage)];
2417 szTmp[cch++] = s_achHandlerStates[PGM_PAGE_GET_HNDL_VIRT_STATE(pPage)];
2418 }
2419
2420 /* The type. */
2421 if (IS_PART_INCLUDED(4))
2422 {
2423 szTmp[cch++] = ':';
2424 static const char s_achPageTypes[8][4] = { "INV", "RAM", "MI2", "M2A", "SHA", "ROM", "MIO", "BAD" };
2425 szTmp[cch++] = s_achPageTypes[PGM_PAGE_GET_TYPE(pPage)][0];
2426 szTmp[cch++] = s_achPageTypes[PGM_PAGE_GET_TYPE(pPage)][1];
2427 szTmp[cch++] = s_achPageTypes[PGM_PAGE_GET_TYPE(pPage)][2];
2428 }
2429
2430 /* The numbers. */
2431 if (IS_PART_INCLUDED(3))
2432 {
2433 szTmp[cch++] = ':';
2434 cch += RTStrFormatNumber(&szTmp[cch], PGM_PAGE_GET_HCPHYS(pPage), 16, 12, 0, RTSTR_F_ZEROPAD | RTSTR_F_64BIT);
2435 }
2436
2437 if (IS_PART_INCLUDED(2))
2438 {
2439 szTmp[cch++] = ':';
2440 cch += RTStrFormatNumber(&szTmp[cch], PGM_PAGE_GET_PAGEID(pPage), 16, 7, 0, RTSTR_F_ZEROPAD | RTSTR_F_32BIT);
2441 }
2442
2443 if (IS_PART_INCLUDED(6))
2444 {
2445 szTmp[cch++] = ':';
2446 static const char s_achRefs[4] = { '-', 'U', '!', 'L' };
2447 szTmp[cch++] = s_achRefs[PGM_PAGE_GET_TD_CREFS(pPage)];
2448 cch += RTStrFormatNumber(&szTmp[cch], PGM_PAGE_GET_TD_IDX(pPage), 16, 4, 0, RTSTR_F_ZEROPAD | RTSTR_F_16BIT);
2449 }
2450#undef IS_PART_INCLUDED
2451
2452 cch = pfnOutput(pvArgOutput, szTmp, cch);
2453 }
2454 else
2455 cch = pfnOutput(pvArgOutput, "<bad-pgmpage-ptr>", sizeof("<bad-pgmpage-ptr>") - 1);
2456 return cch;
2457}
2458
2459
2460/** Format handler for PGMRAMRANGE.
2461 * @copydoc FNRTSTRFORMATTYPE */
2462static DECLCALLBACK(size_t) pgmFormatTypeHandlerRamRange(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
2463 const char *pszType, void const *pvValue,
2464 int cchWidth, int cchPrecision, unsigned fFlags,
2465 void *pvUser)
2466{
2467 size_t cch;
2468 PGMRAMRANGE const *pRam = (PGMRAMRANGE const *)pvValue;
2469 if (VALID_PTR(pRam))
2470 {
2471 char szTmp[80];
2472 cch = RTStrPrintf(szTmp, sizeof(szTmp), "%RGp-%RGp", pRam->GCPhys, pRam->GCPhysLast);
2473 cch = pfnOutput(pvArgOutput, szTmp, cch);
2474 }
2475 else
2476 cch = pfnOutput(pvArgOutput, "<bad-pgmramrange-ptr>", sizeof("<bad-pgmramrange-ptr>") - 1);
2477 return cch;
2478}
2479
2480/** Format type andlers to be registered/deregistered. */
2481static const struct
2482{
2483 char szType[24];
2484 PFNRTSTRFORMATTYPE pfnHandler;
2485} g_aPgmFormatTypes[] =
2486{
2487 { "pgmpage", pgmFormatTypeHandlerPage },
2488 { "pgmramrange", pgmFormatTypeHandlerRamRange }
2489};
2490
2491#endif /* !IN_R0 || LOG_ENABLED */
2492
2493
2494/**
2495 * Registers the global string format types.
2496 *
2497 * This should be called at module load time or in some other manner that ensure
2498 * that it's called exactly one time.
2499 *
2500 * @returns IPRT status code on RTStrFormatTypeRegister failure.
2501 */
2502VMMDECL(int) PGMRegisterStringFormatTypes(void)
2503{
2504#if !defined(IN_R0) || defined(LOG_ENABLED)
2505 int rc = VINF_SUCCESS;
2506 unsigned i;
2507 for (i = 0; RT_SUCCESS(rc) && i < RT_ELEMENTS(g_aPgmFormatTypes); i++)
2508 {
2509 rc = RTStrFormatTypeRegister(g_aPgmFormatTypes[i].szType, g_aPgmFormatTypes[i].pfnHandler, NULL);
2510# ifdef IN_RING0
2511 if (rc == VERR_ALREADY_EXISTS)
2512 {
2513 /* in case of cleanup failure in ring-0 */
2514 RTStrFormatTypeDeregister(g_aPgmFormatTypes[i].szType);
2515 rc = RTStrFormatTypeRegister(g_aPgmFormatTypes[i].szType, g_aPgmFormatTypes[i].pfnHandler, NULL);
2516 }
2517# endif
2518 }
2519 if (RT_FAILURE(rc))
2520 while (i-- > 0)
2521 RTStrFormatTypeDeregister(g_aPgmFormatTypes[i].szType);
2522
2523 return rc;
2524#else
2525 return VINF_SUCCESS;
2526#endif
2527}
2528
2529
2530/**
2531 * Deregisters the global string format types.
2532 *
2533 * This should be called at module unload time or in some other manner that
2534 * ensure that it's called exactly one time.
2535 */
2536VMMDECL(void) PGMDeregisterStringFormatTypes(void)
2537{
2538#if !defined(IN_R0) || defined(LOG_ENABLED)
2539 for (unsigned i = 0; i < RT_ELEMENTS(g_aPgmFormatTypes); i++)
2540 RTStrFormatTypeDeregister(g_aPgmFormatTypes[i].szType);
2541#endif
2542}
2543
2544#ifdef VBOX_STRICT
2545
2546/**
2547 * Asserts that there are no mapping conflicts.
2548 *
2549 * @returns Number of conflicts.
2550 * @param pVM The VM Handle.
2551 */
2552VMMDECL(unsigned) PGMAssertNoMappingConflicts(PVM pVM)
2553{
2554 unsigned cErrors = 0;
2555
2556 /* Only applies to raw mode -> 1 VPCU */
2557 Assert(pVM->cCpus == 1);
2558 PVMCPU pVCpu = &pVM->aCpus[0];
2559
2560 /*
2561 * Check for mapping conflicts.
2562 */
2563 for (PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
2564 pMapping;
2565 pMapping = pMapping->CTX_SUFF(pNext))
2566 {
2567 /** @todo This is slow and should be optimized, but since it's just assertions I don't care now. */
2568 for (RTGCPTR GCPtr = pMapping->GCPtr;
2569 GCPtr <= pMapping->GCPtrLast;
2570 GCPtr += PAGE_SIZE)
2571 {
2572 int rc = PGMGstGetPage(pVCpu, (RTGCPTR)GCPtr, NULL, NULL);
2573 if (rc != VERR_PAGE_TABLE_NOT_PRESENT)
2574 {
2575 AssertMsgFailed(("Conflict at %RGv with %s\n", GCPtr, R3STRING(pMapping->pszDesc)));
2576 cErrors++;
2577 break;
2578 }
2579 }
2580 }
2581
2582 return cErrors;
2583}
2584
2585
2586/**
2587 * Asserts that everything related to the guest CR3 is correctly shadowed.
2588 *
2589 * This will call PGMAssertNoMappingConflicts() and PGMAssertHandlerAndFlagsInSync(),
2590 * and assert the correctness of the guest CR3 mapping before asserting that the
2591 * shadow page tables is in sync with the guest page tables.
2592 *
2593 * @returns Number of conflicts.
2594 * @param pVM The VM Handle.
2595 * @param pVCpu VMCPU handle.
2596 * @param cr3 The current guest CR3 register value.
2597 * @param cr4 The current guest CR4 register value.
2598 */
2599VMMDECL(unsigned) PGMAssertCR3(PVM pVM, PVMCPU pVCpu, uint64_t cr3, uint64_t cr4)
2600{
2601 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncCR3), a);
2602 pgmLock(pVM);
2603 unsigned cErrors = PGM_BTH_PFN(AssertCR3, pVCpu)(pVCpu, cr3, cr4, 0, ~(RTGCPTR)0);
2604 pgmUnlock(pVM);
2605 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncCR3), a);
2606 return cErrors;
2607}
2608
2609#endif /* VBOX_STRICT */
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette