VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAll.cpp@ 30824

Last change on this file since 30824 was 30824, checked in by vboxsync, 14 years ago

Must also deal with zero cr3 translation ptrs in ring 0.
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File size: 84.7 KB
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1/* $Id: PGMAll.cpp 30824 2010-07-14 12:25:12Z vboxsync $ */
2/** @file
3 * PGM - Page Manager and Monitor - All context code.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/*******************************************************************************
19* Header Files *
20*******************************************************************************/
21#define LOG_GROUP LOG_GROUP_PGM
22#include <VBox/pgm.h>
23#include <VBox/cpum.h>
24#include <VBox/selm.h>
25#include <VBox/iom.h>
26#include <VBox/sup.h>
27#include <VBox/mm.h>
28#include <VBox/stam.h>
29#include <VBox/csam.h>
30#include <VBox/patm.h>
31#include <VBox/trpm.h>
32#include <VBox/rem.h>
33#include <VBox/em.h>
34#include <VBox/hwaccm.h>
35#include <VBox/hwacc_vmx.h>
36#include "../PGMInternal.h"
37#include <VBox/vm.h>
38#include "../PGMInline.h"
39#include <iprt/assert.h>
40#include <iprt/asm-amd64-x86.h>
41#include <iprt/string.h>
42#include <VBox/log.h>
43#include <VBox/param.h>
44#include <VBox/err.h>
45
46
47/*******************************************************************************
48* Structures and Typedefs *
49*******************************************************************************/
50/**
51 * Stated structure for PGM_GST_NAME(HandlerVirtualUpdate) that's
52 * passed to PGM_GST_NAME(VirtHandlerUpdateOne) during enumeration.
53 */
54typedef struct PGMHVUSTATE
55{
56 /** The VM handle. */
57 PVM pVM;
58 /** The VMCPU handle. */
59 PVMCPU pVCpu;
60 /** The todo flags. */
61 RTUINT fTodo;
62 /** The CR4 register value. */
63 uint32_t cr4;
64} PGMHVUSTATE, *PPGMHVUSTATE;
65
66
67/*******************************************************************************
68* Internal Functions *
69*******************************************************************************/
70DECLINLINE(int) pgmShwGetLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPT *ppPdpt, PX86PDPAE *ppPD);
71DECLINLINE(int) pgmShwGetPaePoolPagePD(PPGMCPU pPGM, RTGCPTR GCPtr, PPGMPOOLPAGE *ppShwPde);
72
73/*
74 * Shadow - 32-bit mode
75 */
76#define PGM_SHW_TYPE PGM_TYPE_32BIT
77#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
78#include "PGMAllShw.h"
79
80/* Guest - real mode */
81#define PGM_GST_TYPE PGM_TYPE_REAL
82#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
83#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
84#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
85#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
86#include "PGMGstDefs.h"
87#include "PGMAllGst.h"
88#include "PGMAllBth.h"
89#undef BTH_PGMPOOLKIND_PT_FOR_PT
90#undef BTH_PGMPOOLKIND_ROOT
91#undef PGM_BTH_NAME
92#undef PGM_GST_TYPE
93#undef PGM_GST_NAME
94
95/* Guest - protected mode */
96#define PGM_GST_TYPE PGM_TYPE_PROT
97#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
98#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
99#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
100#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
101#include "PGMGstDefs.h"
102#include "PGMAllGst.h"
103#include "PGMAllBth.h"
104#undef BTH_PGMPOOLKIND_PT_FOR_PT
105#undef BTH_PGMPOOLKIND_ROOT
106#undef PGM_BTH_NAME
107#undef PGM_GST_TYPE
108#undef PGM_GST_NAME
109
110/* Guest - 32-bit mode */
111#define PGM_GST_TYPE PGM_TYPE_32BIT
112#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
113#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
114#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
115#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
116#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD
117#include "PGMGstDefs.h"
118#include "PGMAllGst.h"
119#include "PGMAllBth.h"
120#undef BTH_PGMPOOLKIND_PT_FOR_BIG
121#undef BTH_PGMPOOLKIND_PT_FOR_PT
122#undef BTH_PGMPOOLKIND_ROOT
123#undef PGM_BTH_NAME
124#undef PGM_GST_TYPE
125#undef PGM_GST_NAME
126
127#undef PGM_SHW_TYPE
128#undef PGM_SHW_NAME
129
130
131/*
132 * Shadow - PAE mode
133 */
134#define PGM_SHW_TYPE PGM_TYPE_PAE
135#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
136#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
137#include "PGMAllShw.h"
138
139/* Guest - real mode */
140#define PGM_GST_TYPE PGM_TYPE_REAL
141#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
142#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
143#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
144#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
145#include "PGMGstDefs.h"
146#include "PGMAllBth.h"
147#undef BTH_PGMPOOLKIND_PT_FOR_PT
148#undef BTH_PGMPOOLKIND_ROOT
149#undef PGM_BTH_NAME
150#undef PGM_GST_TYPE
151#undef PGM_GST_NAME
152
153/* Guest - protected mode */
154#define PGM_GST_TYPE PGM_TYPE_PROT
155#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
156#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
157#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
158#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
159#include "PGMGstDefs.h"
160#include "PGMAllBth.h"
161#undef BTH_PGMPOOLKIND_PT_FOR_PT
162#undef BTH_PGMPOOLKIND_ROOT
163#undef PGM_BTH_NAME
164#undef PGM_GST_TYPE
165#undef PGM_GST_NAME
166
167/* Guest - 32-bit mode */
168#define PGM_GST_TYPE PGM_TYPE_32BIT
169#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
170#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
171#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
172#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
173#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_FOR_32BIT
174#include "PGMGstDefs.h"
175#include "PGMAllBth.h"
176#undef BTH_PGMPOOLKIND_PT_FOR_BIG
177#undef BTH_PGMPOOLKIND_PT_FOR_PT
178#undef BTH_PGMPOOLKIND_ROOT
179#undef PGM_BTH_NAME
180#undef PGM_GST_TYPE
181#undef PGM_GST_NAME
182
183
184/* Guest - PAE mode */
185#define PGM_GST_TYPE PGM_TYPE_PAE
186#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
187#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
188#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
189#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
190#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT
191#include "PGMGstDefs.h"
192#include "PGMAllGst.h"
193#include "PGMAllBth.h"
194#undef BTH_PGMPOOLKIND_PT_FOR_BIG
195#undef BTH_PGMPOOLKIND_PT_FOR_PT
196#undef BTH_PGMPOOLKIND_ROOT
197#undef PGM_BTH_NAME
198#undef PGM_GST_TYPE
199#undef PGM_GST_NAME
200
201#undef PGM_SHW_TYPE
202#undef PGM_SHW_NAME
203
204
205#ifndef IN_RC /* AMD64 implies VT-x/AMD-V */
206/*
207 * Shadow - AMD64 mode
208 */
209# define PGM_SHW_TYPE PGM_TYPE_AMD64
210# define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
211# include "PGMAllShw.h"
212
213/* Guest - protected mode (only used for AMD-V nested paging in 64 bits mode) */
214# define PGM_GST_TYPE PGM_TYPE_PROT
215# define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
216# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_PROT(name)
217# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
218# define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PD_PHYS
219# include "PGMGstDefs.h"
220# include "PGMAllBth.h"
221# undef BTH_PGMPOOLKIND_PT_FOR_PT
222# undef BTH_PGMPOOLKIND_ROOT
223# undef PGM_BTH_NAME
224# undef PGM_GST_TYPE
225# undef PGM_GST_NAME
226
227# ifdef VBOX_WITH_64_BITS_GUESTS
228/* Guest - AMD64 mode */
229# define PGM_GST_TYPE PGM_TYPE_AMD64
230# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
231# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
232# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
233# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
234# define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_64BIT_PML4
235# include "PGMGstDefs.h"
236# include "PGMAllGst.h"
237# include "PGMAllBth.h"
238# undef BTH_PGMPOOLKIND_PT_FOR_BIG
239# undef BTH_PGMPOOLKIND_PT_FOR_PT
240# undef BTH_PGMPOOLKIND_ROOT
241# undef PGM_BTH_NAME
242# undef PGM_GST_TYPE
243# undef PGM_GST_NAME
244# endif /* VBOX_WITH_64_BITS_GUESTS */
245
246# undef PGM_SHW_TYPE
247# undef PGM_SHW_NAME
248
249
250/*
251 * Shadow - Nested paging mode
252 */
253# define PGM_SHW_TYPE PGM_TYPE_NESTED
254# define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED(name)
255# include "PGMAllShw.h"
256
257/* Guest - real mode */
258# define PGM_GST_TYPE PGM_TYPE_REAL
259# define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
260# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_REAL(name)
261# include "PGMGstDefs.h"
262# include "PGMAllBth.h"
263# undef PGM_BTH_NAME
264# undef PGM_GST_TYPE
265# undef PGM_GST_NAME
266
267/* Guest - protected mode */
268# define PGM_GST_TYPE PGM_TYPE_PROT
269# define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
270# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PROT(name)
271# include "PGMGstDefs.h"
272# include "PGMAllBth.h"
273# undef PGM_BTH_NAME
274# undef PGM_GST_TYPE
275# undef PGM_GST_NAME
276
277/* Guest - 32-bit mode */
278# define PGM_GST_TYPE PGM_TYPE_32BIT
279# define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
280# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT(name)
281# include "PGMGstDefs.h"
282# include "PGMAllBth.h"
283# undef PGM_BTH_NAME
284# undef PGM_GST_TYPE
285# undef PGM_GST_NAME
286
287/* Guest - PAE mode */
288# define PGM_GST_TYPE PGM_TYPE_PAE
289# define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
290# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE(name)
291# include "PGMGstDefs.h"
292# include "PGMAllBth.h"
293# undef PGM_BTH_NAME
294# undef PGM_GST_TYPE
295# undef PGM_GST_NAME
296
297# ifdef VBOX_WITH_64_BITS_GUESTS
298/* Guest - AMD64 mode */
299# define PGM_GST_TYPE PGM_TYPE_AMD64
300# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
301# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64(name)
302# include "PGMGstDefs.h"
303# include "PGMAllBth.h"
304# undef PGM_BTH_NAME
305# undef PGM_GST_TYPE
306# undef PGM_GST_NAME
307# endif /* VBOX_WITH_64_BITS_GUESTS */
308
309# undef PGM_SHW_TYPE
310# undef PGM_SHW_NAME
311
312
313/*
314 * Shadow - EPT
315 */
316# define PGM_SHW_TYPE PGM_TYPE_EPT
317# define PGM_SHW_NAME(name) PGM_SHW_NAME_EPT(name)
318# include "PGMAllShw.h"
319
320/* Guest - real mode */
321# define PGM_GST_TYPE PGM_TYPE_REAL
322# define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
323# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_REAL(name)
324# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
325# include "PGMGstDefs.h"
326# include "PGMAllBth.h"
327# undef BTH_PGMPOOLKIND_PT_FOR_PT
328# undef PGM_BTH_NAME
329# undef PGM_GST_TYPE
330# undef PGM_GST_NAME
331
332/* Guest - protected mode */
333# define PGM_GST_TYPE PGM_TYPE_PROT
334# define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
335# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PROT(name)
336# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
337# include "PGMGstDefs.h"
338# include "PGMAllBth.h"
339# undef BTH_PGMPOOLKIND_PT_FOR_PT
340# undef PGM_BTH_NAME
341# undef PGM_GST_TYPE
342# undef PGM_GST_NAME
343
344/* Guest - 32-bit mode */
345# define PGM_GST_TYPE PGM_TYPE_32BIT
346# define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
347# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_32BIT(name)
348# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
349# include "PGMGstDefs.h"
350# include "PGMAllBth.h"
351# undef BTH_PGMPOOLKIND_PT_FOR_PT
352# undef PGM_BTH_NAME
353# undef PGM_GST_TYPE
354# undef PGM_GST_NAME
355
356/* Guest - PAE mode */
357# define PGM_GST_TYPE PGM_TYPE_PAE
358# define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
359# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PAE(name)
360# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
361# include "PGMGstDefs.h"
362# include "PGMAllBth.h"
363# undef BTH_PGMPOOLKIND_PT_FOR_PT
364# undef PGM_BTH_NAME
365# undef PGM_GST_TYPE
366# undef PGM_GST_NAME
367
368# ifdef VBOX_WITH_64_BITS_GUESTS
369/* Guest - AMD64 mode */
370# define PGM_GST_TYPE PGM_TYPE_AMD64
371# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
372# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_AMD64(name)
373# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
374# include "PGMGstDefs.h"
375# include "PGMAllBth.h"
376# undef BTH_PGMPOOLKIND_PT_FOR_PT
377# undef PGM_BTH_NAME
378# undef PGM_GST_TYPE
379# undef PGM_GST_NAME
380# endif /* VBOX_WITH_64_BITS_GUESTS */
381
382# undef PGM_SHW_TYPE
383# undef PGM_SHW_NAME
384
385#endif /* !IN_RC */
386
387
388#ifndef IN_RING3
389/**
390 * #PF Handler.
391 *
392 * @returns VBox status code (appropriate for trap handling and GC return).
393 * @param pVCpu VMCPU handle.
394 * @param uErr The trap error code.
395 * @param pRegFrame Trap register frame.
396 * @param pvFault The fault address.
397 */
398VMMDECL(int) PGMTrap0eHandler(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
399{
400 PVM pVM = pVCpu->CTX_SUFF(pVM);
401
402 Log(("PGMTrap0eHandler: uErr=%RGx pvFault=%RGv eip=%04x:%RGv\n", uErr, pvFault, pRegFrame->cs, (RTGCPTR)pRegFrame->rip));
403 STAM_PROFILE_START(&pVCpu->pgm.s.StatRZTrap0e, a);
404 STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = NULL; } );
405
406
407#ifdef VBOX_WITH_STATISTICS
408 /*
409 * Error code stats.
410 */
411 if (uErr & X86_TRAP_PF_US)
412 {
413 if (!(uErr & X86_TRAP_PF_P))
414 {
415 if (uErr & X86_TRAP_PF_RW)
416 STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eUSNotPresentWrite);
417 else
418 STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eUSNotPresentRead);
419 }
420 else if (uErr & X86_TRAP_PF_RW)
421 STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eUSWrite);
422 else if (uErr & X86_TRAP_PF_RSVD)
423 STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eUSReserved);
424 else if (uErr & X86_TRAP_PF_ID)
425 STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eUSNXE);
426 else
427 STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eUSRead);
428 }
429 else
430 { /* Supervisor */
431 if (!(uErr & X86_TRAP_PF_P))
432 {
433 if (uErr & X86_TRAP_PF_RW)
434 STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eSVNotPresentWrite);
435 else
436 STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eSVNotPresentRead);
437 }
438 else if (uErr & X86_TRAP_PF_RW)
439 STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eSVWrite);
440 else if (uErr & X86_TRAP_PF_ID)
441 STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eSNXE);
442 else if (uErr & X86_TRAP_PF_RSVD)
443 STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eSVReserved);
444 }
445#endif /* VBOX_WITH_STATISTICS */
446
447 /*
448 * Call the worker.
449 */
450 bool fLockTaken = false;
451 int rc = PGM_BTH_PFN(Trap0eHandler, pVCpu)(pVCpu, uErr, pRegFrame, pvFault, &fLockTaken);
452 if (fLockTaken)
453 {
454 Assert(PGMIsLockOwner(pVM));
455 pgmUnlock(pVM);
456 }
457 if (rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
458 rc = VINF_SUCCESS;
459
460# ifdef IN_RING0
461 /* Note: hack alert for difficult to reproduce problem. */
462 if ( rc == VERR_PAGE_NOT_PRESENT /* SMP only ; disassembly might fail. */
463 || rc == VERR_PAGE_TABLE_NOT_PRESENT /* seen with UNI & SMP */
464 || rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT /* seen with SMP */
465 || rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT) /* precaution */
466 {
467 Log(("WARNING: Unexpected VERR_PAGE_TABLE_NOT_PRESENT (%d) for page fault at %RGv error code %x (rip=%RGv)\n", rc, pvFault, uErr, pRegFrame->rip));
468 /* Some kind of inconsistency in the SMP case; it's safe to just execute the instruction again; not sure about single VCPU VMs though. */
469 rc = VINF_SUCCESS;
470 }
471# endif
472
473 STAM_STATS({ if (rc == VINF_EM_RAW_GUEST_TRAP) STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eGuestPF); });
474 STAM_STATS({ if (!pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution))
475 pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2Misc; });
476 STAM_PROFILE_STOP_EX(&pVCpu->pgm.s.StatRZTrap0e, pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution), a);
477 return rc;
478}
479#endif /* !IN_RING3 */
480
481
482/**
483 * Prefetch a page
484 *
485 * Typically used to sync commonly used pages before entering raw mode
486 * after a CR3 reload.
487 *
488 * @returns VBox status code suitable for scheduling.
489 * @retval VINF_SUCCESS on success.
490 * @retval VINF_PGM_SYNC_CR3 if we're out of shadow pages or something like that.
491 * @param pVCpu VMCPU handle.
492 * @param GCPtrPage Page to invalidate.
493 */
494VMMDECL(int) PGMPrefetchPage(PVMCPU pVCpu, RTGCPTR GCPtrPage)
495{
496 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_MID_Z(Stat,Prefetch), a);
497 int rc = PGM_BTH_PFN(PrefetchPage, pVCpu)(pVCpu, GCPtrPage);
498 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,Prefetch), a);
499 AssertMsg(rc == VINF_SUCCESS || rc == VINF_PGM_SYNC_CR3 || RT_FAILURE(rc), ("rc=%Rrc\n", rc));
500 return rc;
501}
502
503
504/**
505 * Gets the mapping corresponding to the specified address (if any).
506 *
507 * @returns Pointer to the mapping.
508 * @returns NULL if not
509 *
510 * @param pVM The virtual machine.
511 * @param GCPtr The guest context pointer.
512 */
513PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr)
514{
515 PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
516 while (pMapping)
517 {
518 if ((uintptr_t)GCPtr < (uintptr_t)pMapping->GCPtr)
519 break;
520 if ((uintptr_t)GCPtr - (uintptr_t)pMapping->GCPtr < pMapping->cb)
521 return pMapping;
522 pMapping = pMapping->CTX_SUFF(pNext);
523 }
524 return NULL;
525}
526
527
528/**
529 * Verifies a range of pages for read or write access
530 *
531 * Only checks the guest's page tables
532 *
533 * @returns VBox status code.
534 * @param pVCpu VMCPU handle.
535 * @param Addr Guest virtual address to check
536 * @param cbSize Access size
537 * @param fAccess Access type (r/w, user/supervisor (X86_PTE_*))
538 * @remarks Current not in use.
539 */
540VMMDECL(int) PGMIsValidAccess(PVMCPU pVCpu, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess)
541{
542 /*
543 * Validate input.
544 */
545 if (fAccess & ~(X86_PTE_US | X86_PTE_RW))
546 {
547 AssertMsgFailed(("PGMIsValidAccess: invalid access type %08x\n", fAccess));
548 return VERR_INVALID_PARAMETER;
549 }
550
551 uint64_t fPage;
552 int rc = PGMGstGetPage(pVCpu, (RTGCPTR)Addr, &fPage, NULL);
553 if (RT_FAILURE(rc))
554 {
555 Log(("PGMIsValidAccess: access violation for %RGv rc=%d\n", Addr, rc));
556 return VINF_EM_RAW_GUEST_TRAP;
557 }
558
559 /*
560 * Check if the access would cause a page fault
561 *
562 * Note that hypervisor page directories are not present in the guest's tables, so this check
563 * is sufficient.
564 */
565 bool fWrite = !!(fAccess & X86_PTE_RW);
566 bool fUser = !!(fAccess & X86_PTE_US);
567 if ( !(fPage & X86_PTE_P)
568 || (fWrite && !(fPage & X86_PTE_RW))
569 || (fUser && !(fPage & X86_PTE_US)) )
570 {
571 Log(("PGMIsValidAccess: access violation for %RGv attr %#llx vs %d:%d\n", Addr, fPage, fWrite, fUser));
572 return VINF_EM_RAW_GUEST_TRAP;
573 }
574 if ( RT_SUCCESS(rc)
575 && PAGE_ADDRESS(Addr) != PAGE_ADDRESS(Addr + cbSize))
576 return PGMIsValidAccess(pVCpu, Addr + PAGE_SIZE, (cbSize > PAGE_SIZE) ? cbSize - PAGE_SIZE : 1, fAccess);
577 return rc;
578}
579
580
581/**
582 * Verifies a range of pages for read or write access
583 *
584 * Supports handling of pages marked for dirty bit tracking and CSAM
585 *
586 * @returns VBox status code.
587 * @param pVCpu VMCPU handle.
588 * @param Addr Guest virtual address to check
589 * @param cbSize Access size
590 * @param fAccess Access type (r/w, user/supervisor (X86_PTE_*))
591 */
592VMMDECL(int) PGMVerifyAccess(PVMCPU pVCpu, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess)
593{
594 PVM pVM = pVCpu->CTX_SUFF(pVM);
595
596 AssertMsg(!(fAccess & ~(X86_PTE_US | X86_PTE_RW)), ("PGMVerifyAccess: invalid access type %08x\n", fAccess));
597
598 /*
599 * Get going.
600 */
601 uint64_t fPageGst;
602 int rc = PGMGstGetPage(pVCpu, (RTGCPTR)Addr, &fPageGst, NULL);
603 if (RT_FAILURE(rc))
604 {
605 Log(("PGMVerifyAccess: access violation for %RGv rc=%d\n", Addr, rc));
606 return VINF_EM_RAW_GUEST_TRAP;
607 }
608
609 /*
610 * Check if the access would cause a page fault
611 *
612 * Note that hypervisor page directories are not present in the guest's tables, so this check
613 * is sufficient.
614 */
615 const bool fWrite = !!(fAccess & X86_PTE_RW);
616 const bool fUser = !!(fAccess & X86_PTE_US);
617 if ( !(fPageGst & X86_PTE_P)
618 || (fWrite && !(fPageGst & X86_PTE_RW))
619 || (fUser && !(fPageGst & X86_PTE_US)) )
620 {
621 Log(("PGMVerifyAccess: access violation for %RGv attr %#llx vs %d:%d\n", Addr, fPageGst, fWrite, fUser));
622 return VINF_EM_RAW_GUEST_TRAP;
623 }
624
625 if (!HWACCMIsNestedPagingActive(pVM))
626 {
627 /*
628 * Next step is to verify if we protected this page for dirty bit tracking or for CSAM scanning
629 */
630 rc = PGMShwGetPage(pVCpu, (RTGCPTR)Addr, NULL, NULL);
631 if ( rc == VERR_PAGE_NOT_PRESENT
632 || rc == VERR_PAGE_TABLE_NOT_PRESENT)
633 {
634 /*
635 * Page is not present in our page tables.
636 * Try to sync it!
637 */
638 Assert(X86_TRAP_PF_RW == X86_PTE_RW && X86_TRAP_PF_US == X86_PTE_US);
639 uint32_t uErr = fAccess & (X86_TRAP_PF_RW | X86_TRAP_PF_US);
640 rc = PGM_BTH_PFN(VerifyAccessSyncPage, pVCpu)(pVCpu, Addr, fPageGst, uErr);
641 if (rc != VINF_SUCCESS)
642 return rc;
643 }
644 else
645 AssertMsg(rc == VINF_SUCCESS, ("PGMShwGetPage %RGv failed with %Rrc\n", Addr, rc));
646 }
647
648#if 0 /* def VBOX_STRICT; triggers too often now */
649 /*
650 * This check is a bit paranoid, but useful.
651 */
652 /** @note this will assert when writing to monitored pages (a bit annoying actually) */
653 uint64_t fPageShw;
654 rc = PGMShwGetPage(pVCpu, (RTGCPTR)Addr, &fPageShw, NULL);
655 if ( (rc == VERR_PAGE_NOT_PRESENT || RT_FAILURE(rc))
656 || (fWrite && !(fPageShw & X86_PTE_RW))
657 || (fUser && !(fPageShw & X86_PTE_US)) )
658 {
659 AssertMsgFailed(("Unexpected access violation for %RGv! rc=%Rrc write=%d user=%d\n",
660 Addr, rc, fWrite && !(fPageShw & X86_PTE_RW), fUser && !(fPageShw & X86_PTE_US)));
661 return VINF_EM_RAW_GUEST_TRAP;
662 }
663#endif
664
665 if ( RT_SUCCESS(rc)
666 && ( PAGE_ADDRESS(Addr) != PAGE_ADDRESS(Addr + cbSize - 1)
667 || Addr + cbSize < Addr))
668 {
669 /* Don't recursively call PGMVerifyAccess as we might run out of stack. */
670 for (;;)
671 {
672 Addr += PAGE_SIZE;
673 if (cbSize > PAGE_SIZE)
674 cbSize -= PAGE_SIZE;
675 else
676 cbSize = 1;
677 rc = PGMVerifyAccess(pVCpu, Addr, 1, fAccess);
678 if (rc != VINF_SUCCESS)
679 break;
680 if (PAGE_ADDRESS(Addr) == PAGE_ADDRESS(Addr + cbSize - 1))
681 break;
682 }
683 }
684 return rc;
685}
686
687
688/**
689 * Emulation of the invlpg instruction (HC only actually).
690 *
691 * @returns VBox status code, special care required.
692 * @retval VINF_PGM_SYNC_CR3 - handled.
693 * @retval VINF_EM_RAW_EMULATE_INSTR - not handled (RC only).
694 * @retval VERR_REM_FLUSHED_PAGES_OVERFLOW - not handled.
695 *
696 * @param pVCpu VMCPU handle.
697 * @param GCPtrPage Page to invalidate.
698 *
699 * @remark ASSUMES the page table entry or page directory is valid. Fairly
700 * safe, but there could be edge cases!
701 *
702 * @todo Flush page or page directory only if necessary!
703 */
704VMMDECL(int) PGMInvalidatePage(PVMCPU pVCpu, RTGCPTR GCPtrPage)
705{
706 PVM pVM = pVCpu->CTX_SUFF(pVM);
707 int rc;
708 Log3(("PGMInvalidatePage: GCPtrPage=%RGv\n", GCPtrPage));
709
710#ifndef IN_RING3
711 /*
712 * Notify the recompiler so it can record this instruction.
713 */
714 REMNotifyInvalidatePage(pVM, GCPtrPage);
715#endif /* !IN_RING3 */
716
717
718#ifdef IN_RC
719 /*
720 * Check for conflicts and pending CR3 monitoring updates.
721 */
722 if (pgmMapAreMappingsFloating(&pVM->pgm.s))
723 {
724 if ( pgmGetMapping(pVM, GCPtrPage)
725 && PGMGstGetPage(pVCpu, GCPtrPage, NULL, NULL) != VERR_PAGE_TABLE_NOT_PRESENT)
726 {
727 LogFlow(("PGMGCInvalidatePage: Conflict!\n"));
728 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
729 STAM_COUNTER_INC(&pVM->pgm.s.StatRCInvlPgConflict);
730 return VINF_PGM_SYNC_CR3;
731 }
732
733 if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
734 {
735 LogFlow(("PGMGCInvalidatePage: PGM_SYNC_MONITOR_CR3 -> reinterpret instruction in R3\n"));
736 STAM_COUNTER_INC(&pVM->pgm.s.StatRCInvlPgSyncMonCR3);
737 return VINF_EM_RAW_EMULATE_INSTR;
738 }
739 }
740#endif /* IN_RC */
741
742 /*
743 * Call paging mode specific worker.
744 */
745 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePage), a);
746 pgmLock(pVM);
747 rc = PGM_BTH_PFN(InvalidatePage, pVCpu)(pVCpu, GCPtrPage);
748 pgmUnlock(pVM);
749 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePage), a);
750
751 /* Invalidate the TLB entry; might already be done by InvalidatePage (@todo) */
752 PGM_INVL_PG(pVCpu, GCPtrPage);
753
754#ifdef IN_RING3
755 /*
756 * Check if we have a pending update of the CR3 monitoring.
757 */
758 if ( RT_SUCCESS(rc)
759 && (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3))
760 {
761 pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
762 Assert(!pVM->pgm.s.fMappingsFixed); Assert(!pVM->pgm.s.fMappingsDisabled);
763 }
764
765 /*
766 * Inform CSAM about the flush
767 *
768 * Note: This is to check if monitored pages have been changed; when we implement
769 * callbacks for virtual handlers, this is no longer required.
770 */
771 CSAMR3FlushPage(pVM, GCPtrPage);
772#endif /* IN_RING3 */
773
774 /* Ignore all irrelevant error codes. */
775 if ( rc == VERR_PAGE_NOT_PRESENT
776 || rc == VERR_PAGE_TABLE_NOT_PRESENT
777 || rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT
778 || rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT)
779 rc = VINF_SUCCESS;
780
781 return rc;
782}
783
784
785/**
786 * Executes an instruction using the interpreter.
787 *
788 * @returns VBox status code (appropriate for trap handling and GC return).
789 * @param pVM VM handle.
790 * @param pVCpu VMCPU handle.
791 * @param pRegFrame Register frame.
792 * @param pvFault Fault address.
793 */
794VMMDECL(int) PGMInterpretInstruction(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
795{
796 uint32_t cb;
797 int rc = EMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault, &cb);
798 if (rc == VERR_EM_INTERPRETER)
799 rc = VINF_EM_RAW_EMULATE_INSTR;
800 if (rc != VINF_SUCCESS)
801 Log(("PGMInterpretInstruction: returns %Rrc (pvFault=%RGv)\n", rc, pvFault));
802 return rc;
803}
804
805
806/**
807 * Gets effective page information (from the VMM page directory).
808 *
809 * @returns VBox status.
810 * @param pVCpu VMCPU handle.
811 * @param GCPtr Guest Context virtual address of the page.
812 * @param pfFlags Where to store the flags. These are X86_PTE_*.
813 * @param pHCPhys Where to store the HC physical address of the page.
814 * This is page aligned.
815 * @remark You should use PGMMapGetPage() for pages in a mapping.
816 */
817VMMDECL(int) PGMShwGetPage(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys)
818{
819 pgmLock(pVCpu->CTX_SUFF(pVM));
820 int rc = PGM_SHW_PFN(GetPage, pVCpu)(pVCpu, GCPtr, pfFlags, pHCPhys);
821 pgmUnlock(pVCpu->CTX_SUFF(pVM));
822 return rc;
823}
824
825
826/**
827 * Modify page flags for a range of pages in the shadow context.
828 *
829 * The existing flags are ANDed with the fMask and ORed with the fFlags.
830 *
831 * @returns VBox status code.
832 * @param pVCpu VMCPU handle.
833 * @param GCPtr Virtual address of the first page in the range.
834 * @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
835 * @param fMask The AND mask - page flags X86_PTE_*.
836 * Be very CAREFUL when ~'ing constants which could be 32-bit!
837 * @param fOpFlags A combination of the PGM_MK_PK_XXX flags.
838 * @remark You must use PGMMapModifyPage() for pages in a mapping.
839 */
840DECLINLINE(int) pdmShwModifyPage(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags)
841{
842 AssertMsg(!(fFlags & X86_PTE_PAE_PG_MASK), ("fFlags=%#llx\n", fFlags));
843 Assert(!(fOpFlags & ~(PGM_MK_PG_IS_MMIO2 | PGM_MK_PG_IS_WRITE_FAULT)));
844
845 GCPtr &= PAGE_BASE_GC_MASK; /** @todo this ain't necessary, right... */
846
847 PVM pVM = pVCpu->CTX_SUFF(pVM);
848 pgmLock(pVM);
849 int rc = PGM_SHW_PFN(ModifyPage, pVCpu)(pVCpu, GCPtr, PAGE_SIZE, fFlags, fMask, fOpFlags);
850 pgmUnlock(pVM);
851 return rc;
852}
853
854
855/**
856 * Changing the page flags for a single page in the shadow page tables so as to
857 * make it read-only.
858 *
859 * @returns VBox status code.
860 * @param pVCpu VMCPU handle.
861 * @param GCPtr Virtual address of the first page in the range.
862 * @param fOpFlags A combination of the PGM_MK_PK_XXX flags.
863 */
864VMMDECL(int) PGMShwMakePageReadonly(PVMCPU pVCpu, RTGCPTR GCPtr, uint32_t fOpFlags)
865{
866 return pdmShwModifyPage(pVCpu, GCPtr, 0, ~(uint64_t)X86_PTE_RW, fOpFlags);
867}
868
869
870/**
871 * Changing the page flags for a single page in the shadow page tables so as to
872 * make it writable.
873 *
874 * The call must know with 101% certainty that the guest page tables maps this
875 * as writable too. This function will deal shared, zero and write monitored
876 * pages.
877 *
878 * @returns VBox status code.
879 * @param pVCpu VMCPU handle.
880 * @param GCPtr Virtual address of the first page in the range.
881 * @param fMmio2 Set if it is an MMIO2 page.
882 * @param fOpFlags A combination of the PGM_MK_PK_XXX flags.
883 */
884VMMDECL(int) PGMShwMakePageWritable(PVMCPU pVCpu, RTGCPTR GCPtr, uint32_t fOpFlags)
885{
886 return pdmShwModifyPage(pVCpu, GCPtr, X86_PTE_RW, ~(uint64_t)0, fOpFlags);
887}
888
889
890/**
891 * Changing the page flags for a single page in the shadow page tables so as to
892 * make it not present.
893 *
894 * @returns VBox status code.
895 * @param pVCpu VMCPU handle.
896 * @param GCPtr Virtual address of the first page in the range.
897 * @param fOpFlags A combination of the PGM_MK_PG_XXX flags.
898 */
899VMMDECL(int) PGMShwMakePageNotPresent(PVMCPU pVCpu, RTGCPTR GCPtr, uint32_t fOpFlags)
900{
901 return pdmShwModifyPage(pVCpu, GCPtr, 0, 0, fOpFlags);
902}
903
904
905/**
906 * Gets the shadow page directory for the specified address, PAE.
907 *
908 * @returns Pointer to the shadow PD.
909 * @param pVCpu The VMCPU handle.
910 * @param GCPtr The address.
911 * @param pGstPdpe Guest PDPT entry
912 * @param ppPD Receives address of page directory
913 */
914int pgmShwSyncPaePDPtr(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDPE pGstPdpe, PX86PDPAE *ppPD)
915{
916 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
917 PX86PDPT pPdpt = pgmShwGetPaePDPTPtr(&pVCpu->pgm.s);
918 PX86PDPE pPdpe = &pPdpt->a[iPdPt];
919 PVM pVM = pVCpu->CTX_SUFF(pVM);
920 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
921 PPGMPOOLPAGE pShwPage;
922 int rc;
923
924 Assert(PGMIsLockOwner(pVM));
925
926 /* Allocate page directory if not present. */
927 if ( !pPdpe->n.u1Present
928 && !(pPdpe->u & X86_PDPE_PG_MASK))
929 {
930 RTGCPTR64 GCPdPt;
931 PGMPOOLKIND enmKind;
932
933# if defined(IN_RC)
934 /* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
935 PGMDynLockHCPage(pVM, (uint8_t *)pPdpe);
936# endif
937
938 if (HWACCMIsNestedPagingActive(pVM) || !CPUMIsGuestPagingEnabled(pVCpu))
939 {
940 /* AMD-V nested paging or real/protected mode without paging */
941 GCPdPt = (RTGCPTR64)iPdPt << X86_PDPT_SHIFT;
942 enmKind = PGMPOOLKIND_PAE_PD_PHYS;
943 }
944 else
945 {
946 Assert(pGstPdpe);
947
948 if (CPUMGetGuestCR4(pVCpu) & X86_CR4_PAE)
949 {
950 if (!pGstPdpe->n.u1Present)
951 {
952 /* PD not present; guest must reload CR3 to change it.
953 * No need to monitor anything in this case.
954 */
955 Assert(!HWACCMIsEnabled(pVM));
956
957 GCPdPt = pGstPdpe->u & X86_PDPE_PG_MASK;
958 enmKind = PGMPOOLKIND_PAE_PD_PHYS;
959 pGstPdpe->n.u1Present = 1;
960 }
961 else
962 {
963 GCPdPt = pGstPdpe->u & X86_PDPE_PG_MASK;
964 enmKind = PGMPOOLKIND_PAE_PD_FOR_PAE_PD;
965 }
966 }
967 else
968 {
969 GCPdPt = CPUMGetGuestCR3(pVCpu);
970 enmKind = (PGMPOOLKIND)(PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD + iPdPt);
971 }
972 }
973
974 /* Create a reference back to the PDPT by using the index in its shadow page. */
975 rc = pgmPoolAlloc(pVM, GCPdPt, enmKind, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPdPt, &pShwPage);
976 AssertRCReturn(rc, rc);
977
978 /* The PD was cached or created; hook it up now. */
979 pPdpe->u |= pShwPage->Core.Key
980 | (pGstPdpe->u & ~(X86_PDPE_PG_MASK | X86_PDPE_AVL_MASK | X86_PDPE_PCD | X86_PDPE_PWT));
981
982# if defined(IN_RC)
983 /* In 32 bits PAE mode we *must* invalidate the TLB when changing a PDPT entry; the CPU fetches them only during cr3 load, so any
984 * non-present PDPT will continue to cause page faults.
985 */
986 ASMReloadCR3();
987 PGMDynUnlockHCPage(pVM, (uint8_t *)pPdpe);
988# endif
989 }
990 else
991 {
992 pShwPage = pgmPoolGetPage(pPool, pPdpe->u & X86_PDPE_PG_MASK);
993 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
994 Assert((pPdpe->u & X86_PDPE_PG_MASK) == pShwPage->Core.Key);
995
996 pgmPoolCacheUsed(pPool, pShwPage);
997 }
998 *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
999 return VINF_SUCCESS;
1000}
1001
1002
1003/**
1004 * Gets the pointer to the shadow page directory entry for an address, PAE.
1005 *
1006 * @returns Pointer to the PDE.
1007 * @param pPGM Pointer to the PGMCPU instance data.
1008 * @param GCPtr The address.
1009 * @param ppShwPde Receives the address of the pgm pool page for the shadow page directory
1010 */
1011DECLINLINE(int) pgmShwGetPaePoolPagePD(PPGMCPU pPGM, RTGCPTR GCPtr, PPGMPOOLPAGE *ppShwPde)
1012{
1013 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
1014 PX86PDPT pPdpt = pgmShwGetPaePDPTPtr(pPGM);
1015
1016 Assert(PGMIsLockOwner(PGMCPU2VM(pPGM)));
1017
1018 AssertReturn(pPdpt, VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT); /* can't happen */
1019 if (!pPdpt->a[iPdPt].n.u1Present)
1020 {
1021 LogFlow(("pgmShwGetPaePoolPagePD: PD %d not present (%RX64)\n", iPdPt, pPdpt->a[iPdPt].u));
1022 return VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT;
1023 }
1024 AssertMsg(pPdpt->a[iPdPt].u & X86_PDPE_PG_MASK, ("GCPtr=%RGv\n", GCPtr));
1025
1026 /* Fetch the pgm pool shadow descriptor. */
1027 PPGMPOOLPAGE pShwPde = pgmPoolGetPage(PGMCPU2PGM(pPGM)->CTX_SUFF(pPool), pPdpt->a[iPdPt].u & X86_PDPE_PG_MASK);
1028 AssertReturn(pShwPde, VERR_INTERNAL_ERROR);
1029
1030 *ppShwPde = pShwPde;
1031 return VINF_SUCCESS;
1032}
1033
1034#ifndef IN_RC
1035
1036/**
1037 * Syncs the SHADOW page directory pointer for the specified address.
1038 *
1039 * Allocates backing pages in case the PDPT or PML4 entry is missing.
1040 *
1041 * The caller is responsible for making sure the guest has a valid PD before
1042 * calling this function.
1043 *
1044 * @returns VBox status.
1045 * @param pVCpu VMCPU handle.
1046 * @param GCPtr The address.
1047 * @param pGstPml4e Guest PML4 entry
1048 * @param pGstPdpe Guest PDPT entry
1049 * @param ppPD Receives address of page directory
1050 */
1051int pgmShwSyncLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PX86PML4E pGstPml4e, PX86PDPE pGstPdpe, PX86PDPAE *ppPD)
1052{
1053 PPGMCPU pPGM = &pVCpu->pgm.s;
1054 PVM pVM = pVCpu->CTX_SUFF(pVM);
1055 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1056 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
1057 PX86PML4E pPml4e = pgmShwGetLongModePML4EPtr(pPGM, iPml4);
1058 bool fNestedPagingOrNoGstPaging = HWACCMIsNestedPagingActive(pVM) || !CPUMIsGuestPagingEnabled(pVCpu);
1059 PPGMPOOLPAGE pShwPage;
1060 int rc;
1061
1062 Assert(PGMIsLockOwner(pVM));
1063
1064 /* Allocate page directory pointer table if not present. */
1065 if ( !pPml4e->n.u1Present
1066 && !(pPml4e->u & X86_PML4E_PG_MASK))
1067 {
1068 RTGCPTR64 GCPml4;
1069 PGMPOOLKIND enmKind;
1070
1071 Assert(pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
1072
1073 if (fNestedPagingOrNoGstPaging)
1074 {
1075 /* AMD-V nested paging or real/protected mode without paging */
1076 GCPml4 = (RTGCPTR64)iPml4 << X86_PML4_SHIFT;
1077 enmKind = PGMPOOLKIND_64BIT_PDPT_FOR_PHYS;
1078 }
1079 else
1080 {
1081 Assert(pGstPml4e && pGstPdpe);
1082
1083 GCPml4 = pGstPml4e->u & X86_PML4E_PG_MASK;
1084 enmKind = PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT;
1085 }
1086
1087 /* Create a reference back to the PDPT by using the index in its shadow page. */
1088 rc = pgmPoolAlloc(pVM, GCPml4, enmKind, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPml4, &pShwPage);
1089 AssertRCReturn(rc, rc);
1090 }
1091 else
1092 {
1093 pShwPage = pgmPoolGetPage(pPool, pPml4e->u & X86_PML4E_PG_MASK);
1094 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1095
1096 pgmPoolCacheUsed(pPool, pShwPage);
1097 }
1098 /* The PDPT was cached or created; hook it up now. */
1099 pPml4e->u |= pShwPage->Core.Key
1100 | (pGstPml4e->u & ~(X86_PML4E_PG_MASK | X86_PML4E_AVL_MASK | X86_PML4E_PCD | X86_PML4E_PWT));
1101
1102 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1103 PX86PDPT pPdpt = (PX86PDPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1104 PX86PDPE pPdpe = &pPdpt->a[iPdPt];
1105
1106 /* Allocate page directory if not present. */
1107 if ( !pPdpe->n.u1Present
1108 && !(pPdpe->u & X86_PDPE_PG_MASK))
1109 {
1110 RTGCPTR64 GCPdPt;
1111 PGMPOOLKIND enmKind;
1112
1113 if (fNestedPagingOrNoGstPaging)
1114 {
1115 /* AMD-V nested paging or real/protected mode without paging */
1116 GCPdPt = (RTGCPTR64)iPdPt << X86_PDPT_SHIFT;
1117 enmKind = PGMPOOLKIND_64BIT_PD_FOR_PHYS;
1118 }
1119 else
1120 {
1121 Assert(pGstPdpe);
1122
1123 GCPdPt = pGstPdpe->u & X86_PDPE_PG_MASK;
1124 enmKind = PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD;
1125 }
1126
1127 /* Create a reference back to the PDPT by using the index in its shadow page. */
1128 rc = pgmPoolAlloc(pVM, GCPdPt, enmKind, pShwPage->idx, iPdPt, &pShwPage);
1129 AssertRCReturn(rc, rc);
1130 }
1131 else
1132 {
1133 pShwPage = pgmPoolGetPage(pPool, pPdpe->u & X86_PDPE_PG_MASK);
1134 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1135
1136 pgmPoolCacheUsed(pPool, pShwPage);
1137 }
1138 /* The PD was cached or created; hook it up now. */
1139 pPdpe->u |= pShwPage->Core.Key
1140 | (pGstPdpe->u & ~(X86_PDPE_PG_MASK | X86_PDPE_AVL_MASK | X86_PDPE_PCD | X86_PDPE_PWT));
1141
1142 *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1143 return VINF_SUCCESS;
1144}
1145
1146
1147/**
1148 * Gets the SHADOW page directory pointer for the specified address (long mode).
1149 *
1150 * @returns VBox status.
1151 * @param pVCpu VMCPU handle.
1152 * @param GCPtr The address.
1153 * @param ppPdpt Receives address of pdpt
1154 * @param ppPD Receives address of page directory
1155 */
1156DECLINLINE(int) pgmShwGetLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPT *ppPdpt, PX86PDPAE *ppPD)
1157{
1158 PPGMCPU pPGM = &pVCpu->pgm.s;
1159 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
1160 PCX86PML4E pPml4e = pgmShwGetLongModePML4EPtr(pPGM, iPml4);
1161
1162 Assert(PGMIsLockOwner(PGMCPU2VM(pPGM)));
1163
1164 AssertReturn(pPml4e, VERR_INTERNAL_ERROR);
1165 if (ppPml4e)
1166 *ppPml4e = (PX86PML4E)pPml4e;
1167
1168 Log4(("pgmShwGetLongModePDPtr %RGv (%RHv) %RX64\n", GCPtr, pPml4e, pPml4e->u));
1169
1170 if (!pPml4e->n.u1Present)
1171 return VERR_PAGE_MAP_LEVEL4_NOT_PRESENT;
1172
1173 PVM pVM = pVCpu->CTX_SUFF(pVM);
1174 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1175 PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPml4e->u & X86_PML4E_PG_MASK);
1176 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1177
1178 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1179 PCX86PDPT pPdpt = *ppPdpt = (PX86PDPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1180 if (!pPdpt->a[iPdPt].n.u1Present)
1181 return VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT;
1182
1183 pShwPage = pgmPoolGetPage(pPool, pPdpt->a[iPdPt].u & X86_PDPE_PG_MASK);
1184 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1185
1186 *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1187 return VINF_SUCCESS;
1188}
1189
1190
1191/**
1192 * Syncs the SHADOW EPT page directory pointer for the specified address. Allocates
1193 * backing pages in case the PDPT or PML4 entry is missing.
1194 *
1195 * @returns VBox status.
1196 * @param pVCpu VMCPU handle.
1197 * @param GCPtr The address.
1198 * @param ppPdpt Receives address of pdpt
1199 * @param ppPD Receives address of page directory
1200 */
1201int pgmShwGetEPTPDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PEPTPDPT *ppPdpt, PEPTPD *ppPD)
1202{
1203 PPGMCPU pPGM = &pVCpu->pgm.s;
1204 PVM pVM = pVCpu->CTX_SUFF(pVM);
1205 const unsigned iPml4 = (GCPtr >> EPT_PML4_SHIFT) & EPT_PML4_MASK;
1206 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1207 PEPTPML4 pPml4;
1208 PEPTPML4E pPml4e;
1209 PPGMPOOLPAGE pShwPage;
1210 int rc;
1211
1212 Assert(HWACCMIsNestedPagingActive(pVM));
1213 Assert(PGMIsLockOwner(pVM));
1214
1215 pPml4 = (PEPTPML4)PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
1216 Assert(pPml4);
1217
1218 /* Allocate page directory pointer table if not present. */
1219 pPml4e = &pPml4->a[iPml4];
1220 if ( !pPml4e->n.u1Present
1221 && !(pPml4e->u & EPT_PML4E_PG_MASK))
1222 {
1223 Assert(!(pPml4e->u & EPT_PML4E_PG_MASK));
1224 RTGCPTR64 GCPml4 = (RTGCPTR64)iPml4 << EPT_PML4_SHIFT;
1225
1226 rc = pgmPoolAlloc(pVM, GCPml4, PGMPOOLKIND_EPT_PDPT_FOR_PHYS, PGMPOOL_IDX_NESTED_ROOT, iPml4, &pShwPage);
1227 AssertRCReturn(rc, rc);
1228 }
1229 else
1230 {
1231 pShwPage = pgmPoolGetPage(pPool, pPml4e->u & EPT_PML4E_PG_MASK);
1232 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1233
1234 pgmPoolCacheUsed(pPool, pShwPage);
1235 }
1236 /* The PDPT was cached or created; hook it up now and fill with the default value. */
1237 pPml4e->u = pShwPage->Core.Key;
1238 pPml4e->n.u1Present = 1;
1239 pPml4e->n.u1Write = 1;
1240 pPml4e->n.u1Execute = 1;
1241
1242 const unsigned iPdPt = (GCPtr >> EPT_PDPT_SHIFT) & EPT_PDPT_MASK;
1243 PEPTPDPT pPdpt = (PEPTPDPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1244 PEPTPDPTE pPdpe = &pPdpt->a[iPdPt];
1245
1246 if (ppPdpt)
1247 *ppPdpt = pPdpt;
1248
1249 /* Allocate page directory if not present. */
1250 if ( !pPdpe->n.u1Present
1251 && !(pPdpe->u & EPT_PDPTE_PG_MASK))
1252 {
1253 RTGCPTR64 GCPdPt = (RTGCPTR64)iPdPt << EPT_PDPT_SHIFT;
1254
1255 rc = pgmPoolAlloc(pVM, GCPdPt, PGMPOOLKIND_64BIT_PD_FOR_PHYS, pShwPage->idx, iPdPt, &pShwPage);
1256 AssertRCReturn(rc, rc);
1257 }
1258 else
1259 {
1260 pShwPage = pgmPoolGetPage(pPool, pPdpe->u & EPT_PDPTE_PG_MASK);
1261 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1262
1263 pgmPoolCacheUsed(pPool, pShwPage);
1264 }
1265 /* The PD was cached or created; hook it up now and fill with the default value. */
1266 pPdpe->u = pShwPage->Core.Key;
1267 pPdpe->n.u1Present = 1;
1268 pPdpe->n.u1Write = 1;
1269 pPdpe->n.u1Execute = 1;
1270
1271 *ppPD = (PEPTPD)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1272 return VINF_SUCCESS;
1273}
1274
1275#endif /* IN_RC */
1276
1277/**
1278 * Gets effective Guest OS page information.
1279 *
1280 * When GCPtr is in a big page, the function will return as if it was a normal
1281 * 4KB page. If the need for distinguishing between big and normal page becomes
1282 * necessary at a later point, a PGMGstGetPage() will be created for that
1283 * purpose.
1284 *
1285 * @returns VBox status.
1286 * @param pVCpu VMCPU handle.
1287 * @param GCPtr Guest Context virtual address of the page.
1288 * @param pfFlags Where to store the flags. These are X86_PTE_*, even for big pages.
1289 * @param pGCPhys Where to store the GC physical address of the page.
1290 * This is page aligned. The fact that the
1291 */
1292VMMDECL(int) PGMGstGetPage(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys)
1293{
1294 return PGM_GST_PFN(GetPage, pVCpu)(pVCpu, GCPtr, pfFlags, pGCPhys);
1295}
1296
1297
1298/**
1299 * Checks if the page is present.
1300 *
1301 * @returns true if the page is present.
1302 * @returns false if the page is not present.
1303 * @param pVCpu VMCPU handle.
1304 * @param GCPtr Address within the page.
1305 */
1306VMMDECL(bool) PGMGstIsPagePresent(PVMCPU pVCpu, RTGCPTR GCPtr)
1307{
1308 int rc = PGMGstGetPage(pVCpu, GCPtr, NULL, NULL);
1309 return RT_SUCCESS(rc);
1310}
1311
1312
1313/**
1314 * Sets (replaces) the page flags for a range of pages in the guest's tables.
1315 *
1316 * @returns VBox status.
1317 * @param pVCpu VMCPU handle.
1318 * @param GCPtr The address of the first page.
1319 * @param cb The size of the range in bytes.
1320 * @param fFlags Page flags X86_PTE_*, excluding the page mask of course.
1321 */
1322VMMDECL(int) PGMGstSetPage(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags)
1323{
1324 return PGMGstModifyPage(pVCpu, GCPtr, cb, fFlags, 0);
1325}
1326
1327
1328/**
1329 * Modify page flags for a range of pages in the guest's tables
1330 *
1331 * The existing flags are ANDed with the fMask and ORed with the fFlags.
1332 *
1333 * @returns VBox status code.
1334 * @param pVCpu VMCPU handle.
1335 * @param GCPtr Virtual address of the first page in the range.
1336 * @param cb Size (in bytes) of the range to apply the modification to.
1337 * @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
1338 * @param fMask The AND mask - page flags X86_PTE_*, excluding the page mask of course.
1339 * Be very CAREFUL when ~'ing constants which could be 32-bit!
1340 */
1341VMMDECL(int) PGMGstModifyPage(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
1342{
1343 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_MID_Z(Stat,GstModifyPage), a);
1344
1345 /*
1346 * Validate input.
1347 */
1348 AssertMsg(!(fFlags & X86_PTE_PAE_PG_MASK), ("fFlags=%#llx\n", fFlags));
1349 Assert(cb);
1350
1351 LogFlow(("PGMGstModifyPage %RGv %d bytes fFlags=%08llx fMask=%08llx\n", GCPtr, cb, fFlags, fMask));
1352
1353 /*
1354 * Adjust input.
1355 */
1356 cb += GCPtr & PAGE_OFFSET_MASK;
1357 cb = RT_ALIGN_Z(cb, PAGE_SIZE);
1358 GCPtr = (GCPtr & PAGE_BASE_GC_MASK);
1359
1360 /*
1361 * Call worker.
1362 */
1363 int rc = PGM_GST_PFN(ModifyPage, pVCpu)(pVCpu, GCPtr, cb, fFlags, fMask);
1364
1365 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,GstModifyPage), a);
1366 return rc;
1367}
1368
1369
1370/**
1371 * Performs the lazy mapping of the 32-bit guest PD.
1372 *
1373 * @returns Pointer to the mapping.
1374 * @param pPGM The PGM instance data.
1375 */
1376PX86PD pgmGstLazyMap32BitPD(PPGMCPU pPGM)
1377{
1378 Assert(!pPGM->CTX_SUFF(pGst32BitPd));
1379 PVM pVM = PGMCPU2VM(pPGM);
1380 pgmLock(pVM);
1381
1382 PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, pPGM->GCPhysCR3);
1383 AssertReturn(pPage, NULL);
1384
1385 RTHCPTR HCPtrGuestCR3;
1386 int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, pPGM->GCPhysCR3 & X86_CR3_PAGE_MASK, (void **)&HCPtrGuestCR3);
1387 AssertRCReturn(rc, NULL);
1388
1389 pPGM->pGst32BitPdR3 = (R3PTRTYPE(PX86PD))HCPtrGuestCR3;
1390# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1391 pPGM->pGst32BitPdR0 = (R0PTRTYPE(PX86PD))HCPtrGuestCR3;
1392# endif
1393
1394 pgmUnlock(pVM);
1395 return pPGM->CTX_SUFF(pGst32BitPd);
1396}
1397
1398
1399/**
1400 * Performs the lazy mapping of the PAE guest PDPT.
1401 *
1402 * @returns Pointer to the mapping.
1403 * @param pPGM The PGM instance data.
1404 */
1405PX86PDPT pgmGstLazyMapPaePDPT(PPGMCPU pPGM)
1406{
1407 Assert(!pPGM->CTX_SUFF(pGstPaePdpt));
1408 PVM pVM = PGMCPU2VM(pPGM);
1409 pgmLock(pVM);
1410
1411 PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, pPGM->GCPhysCR3);
1412 AssertReturn(pPage, NULL);
1413
1414 RTHCPTR HCPtrGuestCR3;
1415 int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, pPGM->GCPhysCR3 & X86_CR3_PAE_PAGE_MASK, (void **)&HCPtrGuestCR3); /** @todo r=bird: This GCPhysR3 masking isn't necessary. */
1416 AssertRCReturn(rc, NULL);
1417
1418 pPGM->pGstPaePdptR3 = (R3PTRTYPE(PX86PDPT))HCPtrGuestCR3;
1419# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1420 pPGM->pGstPaePdptR0 = (R0PTRTYPE(PX86PDPT))HCPtrGuestCR3;
1421# endif
1422
1423 pgmUnlock(pVM);
1424 return pPGM->CTX_SUFF(pGstPaePdpt);
1425}
1426
1427
1428#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
1429/**
1430 * Performs the lazy mapping / updating of a PAE guest PD.
1431 *
1432 * @returns Pointer to the mapping.
1433 * @param pPGM The PGM instance data.
1434 * @param iPdpt Which PD entry to map (0..3).
1435 */
1436PX86PDPAE pgmGstLazyMapPaePD(PPGMCPU pPGM, uint32_t iPdpt)
1437{
1438 PVM pVM = PGMCPU2VM(pPGM);
1439 pgmLock(pVM);
1440
1441 PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
1442 Assert(pGuestPDPT);
1443 Assert(pGuestPDPT->a[iPdpt].n.u1Present);
1444 RTGCPHYS GCPhys = pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK;
1445 bool const fChanged = pPGM->aGCPhysGstPaePDs[iPdpt] != GCPhys;
1446
1447 PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, GCPhys);
1448 if (RT_LIKELY(pPage))
1449 {
1450 int rc = VINF_SUCCESS;
1451 RTRCPTR RCPtr = NIL_RTRCPTR;
1452 RTHCPTR HCPtr = NIL_RTHCPTR;
1453#if !defined(IN_RC) && !defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1454 rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, &HCPtr);
1455 AssertRC(rc);
1456#endif
1457 if (RT_SUCCESS(rc) && fChanged)
1458 {
1459 RCPtr = (RTRCPTR)(RTRCUINTPTR)(pVM->pgm.s.GCPtrCR3Mapping + (1 + iPdpt) * PAGE_SIZE);
1460 rc = PGMMap(pVM, (RTRCUINTPTR)RCPtr, PGM_PAGE_GET_HCPHYS(pPage), PAGE_SIZE, 0);
1461 }
1462 if (RT_SUCCESS(rc))
1463 {
1464 pPGM->apGstPaePDsR3[iPdpt] = (R3PTRTYPE(PX86PDPAE))HCPtr;
1465# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1466 pPGM->apGstPaePDsR0[iPdpt] = (R0PTRTYPE(PX86PDPAE))HCPtr;
1467# endif
1468 if (fChanged)
1469 {
1470 pPGM->aGCPhysGstPaePDs[iPdpt] = GCPhys;
1471 pPGM->apGstPaePDsRC[iPdpt] = (RCPTRTYPE(PX86PDPAE))RCPtr;
1472 }
1473
1474 pgmUnlock(pVM);
1475 return pPGM->CTX_SUFF(apGstPaePDs)[iPdpt];
1476 }
1477 }
1478
1479 /* Invalid page or some failure, invalidate the entry. */
1480 pPGM->aGCPhysGstPaePDs[iPdpt] = NIL_RTGCPHYS;
1481 pPGM->apGstPaePDsR3[iPdpt] = 0;
1482# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1483 pPGM->apGstPaePDsR0[iPdpt] = 0;
1484# endif
1485 pPGM->apGstPaePDsRC[iPdpt] = 0;
1486
1487 pgmUnlock(pVM);
1488 return NULL;
1489}
1490#endif /* !VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
1491
1492#ifndef IN_RC
1493/**
1494 * Performs the lazy mapping of the 32-bit guest PD.
1495 *
1496 * @returns Pointer to the mapping.
1497 * @param pPGM The PGM instance data.
1498 */
1499PX86PML4 pgmGstLazyMapPml4(PPGMCPU pPGM)
1500{
1501 Assert(!pPGM->CTX_SUFF(pGstAmd64Pml4));
1502 PVM pVM = PGMCPU2VM(pPGM);
1503 pgmLock(pVM);
1504
1505 PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, pPGM->GCPhysCR3);
1506 AssertReturn(pPage, NULL);
1507
1508 RTHCPTR HCPtrGuestCR3;
1509 int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, pPGM->GCPhysCR3 & X86_CR3_AMD64_PAGE_MASK, (void **)&HCPtrGuestCR3); /** @todo r=bird: This GCPhysCR3 masking isn't necessary. */
1510 AssertRCReturn(rc, NULL);
1511
1512 pPGM->pGstAmd64Pml4R3 = (R3PTRTYPE(PX86PML4))HCPtrGuestCR3;
1513# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1514 pPGM->pGstAmd64Pml4R0 = (R0PTRTYPE(PX86PML4))HCPtrGuestCR3;
1515# endif
1516
1517 pgmUnlock(pVM);
1518 return pPGM->CTX_SUFF(pGstAmd64Pml4);
1519}
1520#endif
1521
1522/**
1523 * Gets the specified page directory pointer table entry.
1524 *
1525 * @returns PDP entry
1526 * @param pVCpu VMCPU handle.
1527 * @param iPdpt PDPT index
1528 */
1529VMMDECL(X86PDPE) PGMGstGetPaePDPtr(PVMCPU pVCpu, unsigned iPdpt)
1530{
1531 Assert(iPdpt <= 3);
1532 return pgmGstGetPaePDPTPtr(&pVCpu->pgm.s)->a[iPdpt & 3];
1533}
1534
1535
1536/**
1537 * Gets the current CR3 register value for the shadow memory context.
1538 * @returns CR3 value.
1539 * @param pVCpu VMCPU handle.
1540 */
1541VMMDECL(RTHCPHYS) PGMGetHyperCR3(PVMCPU pVCpu)
1542{
1543 PPGMPOOLPAGE pPoolPage = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
1544 AssertPtrReturn(pPoolPage, 0);
1545 return pPoolPage->Core.Key;
1546}
1547
1548
1549/**
1550 * Gets the current CR3 register value for the nested memory context.
1551 * @returns CR3 value.
1552 * @param pVCpu VMCPU handle.
1553 */
1554VMMDECL(RTHCPHYS) PGMGetNestedCR3(PVMCPU pVCpu, PGMMODE enmShadowMode)
1555{
1556 Assert(pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
1557 return pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->Core.Key;
1558}
1559
1560
1561/**
1562 * Gets the current CR3 register value for the HC intermediate memory context.
1563 * @returns CR3 value.
1564 * @param pVM The VM handle.
1565 */
1566VMMDECL(RTHCPHYS) PGMGetInterHCCR3(PVM pVM)
1567{
1568 switch (pVM->pgm.s.enmHostMode)
1569 {
1570 case SUPPAGINGMODE_32_BIT:
1571 case SUPPAGINGMODE_32_BIT_GLOBAL:
1572 return pVM->pgm.s.HCPhysInterPD;
1573
1574 case SUPPAGINGMODE_PAE:
1575 case SUPPAGINGMODE_PAE_GLOBAL:
1576 case SUPPAGINGMODE_PAE_NX:
1577 case SUPPAGINGMODE_PAE_GLOBAL_NX:
1578 return pVM->pgm.s.HCPhysInterPaePDPT;
1579
1580 case SUPPAGINGMODE_AMD64:
1581 case SUPPAGINGMODE_AMD64_GLOBAL:
1582 case SUPPAGINGMODE_AMD64_NX:
1583 case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1584 return pVM->pgm.s.HCPhysInterPaePDPT;
1585
1586 default:
1587 AssertMsgFailed(("enmHostMode=%d\n", pVM->pgm.s.enmHostMode));
1588 return ~0;
1589 }
1590}
1591
1592
1593/**
1594 * Gets the current CR3 register value for the RC intermediate memory context.
1595 * @returns CR3 value.
1596 * @param pVM The VM handle.
1597 * @param pVCpu VMCPU handle.
1598 */
1599VMMDECL(RTHCPHYS) PGMGetInterRCCR3(PVM pVM, PVMCPU pVCpu)
1600{
1601 switch (pVCpu->pgm.s.enmShadowMode)
1602 {
1603 case PGMMODE_32_BIT:
1604 return pVM->pgm.s.HCPhysInterPD;
1605
1606 case PGMMODE_PAE:
1607 case PGMMODE_PAE_NX:
1608 return pVM->pgm.s.HCPhysInterPaePDPT;
1609
1610 case PGMMODE_AMD64:
1611 case PGMMODE_AMD64_NX:
1612 return pVM->pgm.s.HCPhysInterPaePML4;
1613
1614 case PGMMODE_EPT:
1615 case PGMMODE_NESTED:
1616 return 0; /* not relevant */
1617
1618 default:
1619 AssertMsgFailed(("enmShadowMode=%d\n", pVCpu->pgm.s.enmShadowMode));
1620 return ~0;
1621 }
1622}
1623
1624
1625/**
1626 * Gets the CR3 register value for the 32-Bit intermediate memory context.
1627 * @returns CR3 value.
1628 * @param pVM The VM handle.
1629 */
1630VMMDECL(RTHCPHYS) PGMGetInter32BitCR3(PVM pVM)
1631{
1632 return pVM->pgm.s.HCPhysInterPD;
1633}
1634
1635
1636/**
1637 * Gets the CR3 register value for the PAE intermediate memory context.
1638 * @returns CR3 value.
1639 * @param pVM The VM handle.
1640 */
1641VMMDECL(RTHCPHYS) PGMGetInterPaeCR3(PVM pVM)
1642{
1643 return pVM->pgm.s.HCPhysInterPaePDPT;
1644}
1645
1646
1647/**
1648 * Gets the CR3 register value for the AMD64 intermediate memory context.
1649 * @returns CR3 value.
1650 * @param pVM The VM handle.
1651 */
1652VMMDECL(RTHCPHYS) PGMGetInterAmd64CR3(PVM pVM)
1653{
1654 return pVM->pgm.s.HCPhysInterPaePML4;
1655}
1656
1657
1658/**
1659 * Performs and schedules necessary updates following a CR3 load or reload.
1660 *
1661 * This will normally involve mapping the guest PD or nPDPT
1662 *
1663 * @returns VBox status code.
1664 * @retval VINF_PGM_SYNC_CR3 if monitoring requires a CR3 sync. This can
1665 * safely be ignored and overridden since the FF will be set too then.
1666 * @param pVCpu VMCPU handle.
1667 * @param cr3 The new cr3.
1668 * @param fGlobal Indicates whether this is a global flush or not.
1669 */
1670VMMDECL(int) PGMFlushTLB(PVMCPU pVCpu, uint64_t cr3, bool fGlobal)
1671{
1672 PVM pVM = pVCpu->CTX_SUFF(pVM);
1673
1674 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_MID_Z(Stat,FlushTLB), a);
1675
1676 /*
1677 * Always flag the necessary updates; necessary for hardware acceleration
1678 */
1679 /** @todo optimize this, it shouldn't always be necessary. */
1680 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
1681 if (fGlobal)
1682 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
1683 LogFlow(("PGMFlushTLB: cr3=%RX64 OldCr3=%RX64 fGlobal=%d\n", cr3, pVCpu->pgm.s.GCPhysCR3, fGlobal));
1684
1685 /*
1686 * Remap the CR3 content and adjust the monitoring if CR3 was actually changed.
1687 */
1688 int rc = VINF_SUCCESS;
1689 RTGCPHYS GCPhysCR3;
1690 switch (pVCpu->pgm.s.enmGuestMode)
1691 {
1692 case PGMMODE_PAE:
1693 case PGMMODE_PAE_NX:
1694 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAE_PAGE_MASK);
1695 break;
1696 case PGMMODE_AMD64:
1697 case PGMMODE_AMD64_NX:
1698 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_AMD64_PAGE_MASK);
1699 break;
1700 default:
1701 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAGE_MASK);
1702 break;
1703 }
1704
1705 if (pVCpu->pgm.s.GCPhysCR3 != GCPhysCR3)
1706 {
1707 RTGCPHYS GCPhysOldCR3 = pVCpu->pgm.s.GCPhysCR3;
1708 pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3;
1709 rc = PGM_BTH_PFN(MapCR3, pVCpu)(pVCpu, GCPhysCR3);
1710 if (RT_LIKELY(rc == VINF_SUCCESS))
1711 {
1712 if (pgmMapAreMappingsFloating(&pVM->pgm.s))
1713 pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
1714 }
1715 else
1716 {
1717 AssertMsg(rc == VINF_PGM_SYNC_CR3, ("%Rrc\n", rc));
1718 Assert(VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL | VMCPU_FF_PGM_SYNC_CR3));
1719 pVCpu->pgm.s.GCPhysCR3 = GCPhysOldCR3;
1720 pVCpu->pgm.s.fSyncFlags |= PGM_SYNC_MAP_CR3;
1721 if (pgmMapAreMappingsFloating(&pVM->pgm.s))
1722 pVCpu->pgm.s.fSyncFlags |= PGM_SYNC_MONITOR_CR3;
1723 }
1724
1725 if (fGlobal)
1726 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,FlushTLBNewCR3Global));
1727 else
1728 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,FlushTLBNewCR3));
1729 }
1730 else
1731 {
1732# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
1733 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1734 if (pPool->cDirtyPages)
1735 {
1736 pgmLock(pVM);
1737 pgmPoolResetDirtyPages(pVM);
1738 pgmUnlock(pVM);
1739 }
1740# endif
1741 /*
1742 * Check if we have a pending update of the CR3 monitoring.
1743 */
1744 if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
1745 {
1746 pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
1747 Assert(!pVM->pgm.s.fMappingsFixed); Assert(!pVM->pgm.s.fMappingsDisabled);
1748 }
1749 if (fGlobal)
1750 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,FlushTLBSameCR3Global));
1751 else
1752 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,FlushTLBSameCR3));
1753 }
1754
1755 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,FlushTLB), a);
1756 return rc;
1757}
1758
1759
1760/**
1761 * Performs and schedules necessary updates following a CR3 load or reload when
1762 * using nested or extended paging.
1763 *
1764 * This API is an alterantive to PDMFlushTLB that avoids actually flushing the
1765 * TLB and triggering a SyncCR3.
1766 *
1767 * This will normally involve mapping the guest PD or nPDPT
1768 *
1769 * @returns VBox status code.
1770 * @retval VINF_SUCCESS.
1771 * @retval (If applied when not in nested mode: VINF_PGM_SYNC_CR3 if monitoring
1772 * requires a CR3 sync. This can safely be ignored and overridden since
1773 * the FF will be set too then.)
1774 * @param pVCpu VMCPU handle.
1775 * @param cr3 The new cr3.
1776 */
1777VMMDECL(int) PGMUpdateCR3(PVMCPU pVCpu, uint64_t cr3)
1778{
1779 PVM pVM = pVCpu->CTX_SUFF(pVM);
1780
1781 LogFlow(("PGMUpdateCR3: cr3=%RX64 OldCr3=%RX64\n", cr3, pVCpu->pgm.s.GCPhysCR3));
1782
1783 /* We assume we're only called in nested paging mode. */
1784 Assert(HWACCMIsNestedPagingActive(pVM) || pVCpu->pgm.s.enmShadowMode == PGMMODE_EPT);
1785 Assert(pVM->pgm.s.fMappingsDisabled);
1786 Assert(!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3));
1787
1788 /*
1789 * Remap the CR3 content and adjust the monitoring if CR3 was actually changed.
1790 */
1791 int rc = VINF_SUCCESS;
1792 RTGCPHYS GCPhysCR3;
1793 switch (pVCpu->pgm.s.enmGuestMode)
1794 {
1795 case PGMMODE_PAE:
1796 case PGMMODE_PAE_NX:
1797 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAE_PAGE_MASK);
1798 break;
1799 case PGMMODE_AMD64:
1800 case PGMMODE_AMD64_NX:
1801 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_AMD64_PAGE_MASK);
1802 break;
1803 default:
1804 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAGE_MASK);
1805 break;
1806 }
1807 if (pVCpu->pgm.s.GCPhysCR3 != GCPhysCR3)
1808 {
1809 pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3;
1810 rc = PGM_BTH_PFN(MapCR3, pVCpu)(pVCpu, GCPhysCR3);
1811 AssertRCSuccess(rc); /* Assumes VINF_PGM_SYNC_CR3 doesn't apply to nested paging. */ /** @todo this isn't true for the mac, but we need hw to test/fix this. */
1812 }
1813 return rc;
1814}
1815
1816
1817/**
1818 * Synchronize the paging structures.
1819 *
1820 * This function is called in response to the VM_FF_PGM_SYNC_CR3 and
1821 * VM_FF_PGM_SYNC_CR3_NONGLOBAL. Those two force action flags are set
1822 * in several places, most importantly whenever the CR3 is loaded.
1823 *
1824 * @returns VBox status code.
1825 * @param pVCpu VMCPU handle.
1826 * @param cr0 Guest context CR0 register
1827 * @param cr3 Guest context CR3 register
1828 * @param cr4 Guest context CR4 register
1829 * @param fGlobal Including global page directories or not
1830 */
1831VMMDECL(int) PGMSyncCR3(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
1832{
1833 PVM pVM = pVCpu->CTX_SUFF(pVM);
1834 int rc;
1835
1836 /*
1837 * The pool may have pending stuff and even require a return to ring-3 to
1838 * clear the whole thing.
1839 */
1840 rc = pgmPoolSyncCR3(pVCpu);
1841 if (rc != VINF_SUCCESS)
1842 return rc;
1843
1844 /*
1845 * We might be called when we shouldn't.
1846 *
1847 * The mode switching will ensure that the PD is resynced
1848 * after every mode switch. So, if we find ourselves here
1849 * when in protected or real mode we can safely disable the
1850 * FF and return immediately.
1851 */
1852 if (pVCpu->pgm.s.enmGuestMode <= PGMMODE_PROTECTED)
1853 {
1854 Assert((cr0 & (X86_CR0_PG | X86_CR0_PE)) != (X86_CR0_PG | X86_CR0_PE));
1855 Assert(!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL));
1856 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
1857 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
1858 return VINF_SUCCESS;
1859 }
1860
1861 /* If global pages are not supported, then all flushes are global. */
1862 if (!(cr4 & X86_CR4_PGE))
1863 fGlobal = true;
1864 LogFlow(("PGMSyncCR3: cr0=%RX64 cr3=%RX64 cr4=%RX64 fGlobal=%d[%d,%d]\n", cr0, cr3, cr4, fGlobal,
1865 VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3), VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)));
1866
1867 /*
1868 * Check if we need to finish an aborted MapCR3 call (see PGMFlushTLB).
1869 * This should be done before SyncCR3.
1870 */
1871 if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MAP_CR3)
1872 {
1873 pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MAP_CR3;
1874
1875 RTGCPHYS GCPhysCR3Old = pVCpu->pgm.s.GCPhysCR3;
1876 RTGCPHYS GCPhysCR3;
1877 switch (pVCpu->pgm.s.enmGuestMode)
1878 {
1879 case PGMMODE_PAE:
1880 case PGMMODE_PAE_NX:
1881 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAE_PAGE_MASK);
1882 break;
1883 case PGMMODE_AMD64:
1884 case PGMMODE_AMD64_NX:
1885 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_AMD64_PAGE_MASK);
1886 break;
1887 default:
1888 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAGE_MASK);
1889 break;
1890 }
1891
1892 if (pVCpu->pgm.s.GCPhysCR3 != GCPhysCR3)
1893 {
1894 pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3;
1895 rc = PGM_BTH_PFN(MapCR3, pVCpu)(pVCpu, GCPhysCR3);
1896 }
1897 /* Make sure we check for pending pgm pool syncs as we clear VMCPU_FF_PGM_SYNC_CR3 later on! */
1898 if ( rc == VINF_PGM_SYNC_CR3
1899 || (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL))
1900 {
1901 Log(("PGMSyncCR3: pending pgm pool sync after MapCR3!\n"));
1902#ifdef IN_RING3
1903 rc = pgmPoolSyncCR3(pVCpu);
1904#else
1905 if (rc == VINF_PGM_SYNC_CR3)
1906 pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3Old;
1907 return VINF_PGM_SYNC_CR3;
1908#endif
1909 }
1910 AssertRCReturn(rc, rc);
1911 AssertRCSuccessReturn(rc, VERR_INTERNAL_ERROR);
1912 }
1913
1914 /*
1915 * Let the 'Bth' function do the work and we'll just keep track of the flags.
1916 */
1917 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncCR3), a);
1918 rc = PGM_BTH_PFN(SyncCR3, pVCpu)(pVCpu, cr0, cr3, cr4, fGlobal);
1919 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncCR3), a);
1920 AssertMsg(rc == VINF_SUCCESS || rc == VINF_PGM_SYNC_CR3 || RT_FAILURE(rc), ("rc=%Rrc\n", rc));
1921 if (rc == VINF_SUCCESS)
1922 {
1923 if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL)
1924 {
1925 /* Go back to ring 3 if a pgm pool sync is again pending. */
1926 return VINF_PGM_SYNC_CR3;
1927 }
1928
1929 if (!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS))
1930 {
1931 Assert(!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL));
1932 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
1933 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
1934 }
1935
1936 /*
1937 * Check if we have a pending update of the CR3 monitoring.
1938 */
1939 if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
1940 {
1941 pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
1942 Assert(!pVM->pgm.s.fMappingsFixed); Assert(!pVM->pgm.s.fMappingsDisabled);
1943 }
1944 }
1945
1946 /*
1947 * Now flush the CR3 (guest context).
1948 */
1949 if (rc == VINF_SUCCESS)
1950 PGM_INVL_VCPU_TLBS(pVCpu);
1951 return rc;
1952}
1953
1954
1955/**
1956 * Called whenever CR0 or CR4 in a way which may change
1957 * the paging mode.
1958 *
1959 * @returns VBox status code, with the following informational code for
1960 * VM scheduling.
1961 * @retval VINF_SUCCESS if the was no change, or it was successfully dealt with.
1962 * @retval VINF_PGM_CHANGE_MODE if we're in RC or R0 and the mode changes.
1963 * (I.e. not in R3.)
1964 * @retval VINF_EM_SUSPEND or VINF_EM_OFF on a fatal runtime error. (R3 only)
1965 *
1966 * @param pVCpu VMCPU handle.
1967 * @param cr0 The new cr0.
1968 * @param cr4 The new cr4.
1969 * @param efer The new extended feature enable register.
1970 */
1971VMMDECL(int) PGMChangeMode(PVMCPU pVCpu, uint64_t cr0, uint64_t cr4, uint64_t efer)
1972{
1973 PVM pVM = pVCpu->CTX_SUFF(pVM);
1974 PGMMODE enmGuestMode;
1975
1976 /*
1977 * Calc the new guest mode.
1978 */
1979 if (!(cr0 & X86_CR0_PE))
1980 enmGuestMode = PGMMODE_REAL;
1981 else if (!(cr0 & X86_CR0_PG))
1982 enmGuestMode = PGMMODE_PROTECTED;
1983 else if (!(cr4 & X86_CR4_PAE))
1984 enmGuestMode = PGMMODE_32_BIT;
1985 else if (!(efer & MSR_K6_EFER_LME))
1986 {
1987 if (!(efer & MSR_K6_EFER_NXE))
1988 enmGuestMode = PGMMODE_PAE;
1989 else
1990 enmGuestMode = PGMMODE_PAE_NX;
1991 }
1992 else
1993 {
1994 if (!(efer & MSR_K6_EFER_NXE))
1995 enmGuestMode = PGMMODE_AMD64;
1996 else
1997 enmGuestMode = PGMMODE_AMD64_NX;
1998 }
1999
2000 /*
2001 * Did it change?
2002 */
2003 if (pVCpu->pgm.s.enmGuestMode == enmGuestMode)
2004 return VINF_SUCCESS;
2005
2006 /* Flush the TLB */
2007 PGM_INVL_VCPU_TLBS(pVCpu);
2008
2009#ifdef IN_RING3
2010 return PGMR3ChangeMode(pVM, pVCpu, enmGuestMode);
2011#else
2012 LogFlow(("PGMChangeMode: returns VINF_PGM_CHANGE_MODE.\n"));
2013 return VINF_PGM_CHANGE_MODE;
2014#endif
2015}
2016
2017
2018/**
2019 * Gets the current guest paging mode.
2020 *
2021 * If you just need the CPU mode (real/protected/long), use CPUMGetGuestMode().
2022 *
2023 * @returns The current paging mode.
2024 * @param pVCpu VMCPU handle.
2025 */
2026VMMDECL(PGMMODE) PGMGetGuestMode(PVMCPU pVCpu)
2027{
2028 return pVCpu->pgm.s.enmGuestMode;
2029}
2030
2031
2032/**
2033 * Gets the current shadow paging mode.
2034 *
2035 * @returns The current paging mode.
2036 * @param pVCpu VMCPU handle.
2037 */
2038VMMDECL(PGMMODE) PGMGetShadowMode(PVMCPU pVCpu)
2039{
2040 return pVCpu->pgm.s.enmShadowMode;
2041}
2042
2043/**
2044 * Gets the current host paging mode.
2045 *
2046 * @returns The current paging mode.
2047 * @param pVM The VM handle.
2048 */
2049VMMDECL(PGMMODE) PGMGetHostMode(PVM pVM)
2050{
2051 switch (pVM->pgm.s.enmHostMode)
2052 {
2053 case SUPPAGINGMODE_32_BIT:
2054 case SUPPAGINGMODE_32_BIT_GLOBAL:
2055 return PGMMODE_32_BIT;
2056
2057 case SUPPAGINGMODE_PAE:
2058 case SUPPAGINGMODE_PAE_GLOBAL:
2059 return PGMMODE_PAE;
2060
2061 case SUPPAGINGMODE_PAE_NX:
2062 case SUPPAGINGMODE_PAE_GLOBAL_NX:
2063 return PGMMODE_PAE_NX;
2064
2065 case SUPPAGINGMODE_AMD64:
2066 case SUPPAGINGMODE_AMD64_GLOBAL:
2067 return PGMMODE_AMD64;
2068
2069 case SUPPAGINGMODE_AMD64_NX:
2070 case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2071 return PGMMODE_AMD64_NX;
2072
2073 default: AssertMsgFailed(("enmHostMode=%d\n", pVM->pgm.s.enmHostMode)); break;
2074 }
2075
2076 return PGMMODE_INVALID;
2077}
2078
2079
2080/**
2081 * Get mode name.
2082 *
2083 * @returns read-only name string.
2084 * @param enmMode The mode which name is desired.
2085 */
2086VMMDECL(const char *) PGMGetModeName(PGMMODE enmMode)
2087{
2088 switch (enmMode)
2089 {
2090 case PGMMODE_REAL: return "Real";
2091 case PGMMODE_PROTECTED: return "Protected";
2092 case PGMMODE_32_BIT: return "32-bit";
2093 case PGMMODE_PAE: return "PAE";
2094 case PGMMODE_PAE_NX: return "PAE+NX";
2095 case PGMMODE_AMD64: return "AMD64";
2096 case PGMMODE_AMD64_NX: return "AMD64+NX";
2097 case PGMMODE_NESTED: return "Nested";
2098 case PGMMODE_EPT: return "EPT";
2099 default: return "unknown mode value";
2100 }
2101}
2102
2103
2104/**
2105 * Check if any pgm pool pages are marked dirty (not monitored)
2106 *
2107 * @returns bool locked/not locked
2108 * @param pVM The VM to operate on.
2109 */
2110VMMDECL(bool) PGMHasDirtyPages(PVM pVM)
2111{
2112 return pVM->pgm.s.CTX_SUFF(pPool)->cDirtyPages != 0;
2113}
2114
2115/**
2116 * Check if the PGM lock is currently taken.
2117 *
2118 * @returns bool locked/not locked
2119 * @param pVM The VM to operate on.
2120 */
2121VMMDECL(bool) PGMIsLocked(PVM pVM)
2122{
2123 return PDMCritSectIsOwned(&pVM->pgm.s.CritSect);
2124}
2125
2126
2127/**
2128 * Check if this VCPU currently owns the PGM lock.
2129 *
2130 * @returns bool owner/not owner
2131 * @param pVM The VM to operate on.
2132 */
2133VMMDECL(bool) PGMIsLockOwner(PVM pVM)
2134{
2135 return PDMCritSectIsOwner(&pVM->pgm.s.CritSect);
2136}
2137
2138
2139/**
2140 * Enable or disable large page usage
2141 *
2142 * @param pVM The VM to operate on.
2143 * @param fUseLargePages Use/not use large pages
2144 */
2145VMMDECL(void) PGMSetLargePageUsage(PVM pVM, bool fUseLargePages)
2146{
2147 pVM->fUseLargePages = fUseLargePages;
2148}
2149
2150/**
2151 * Acquire the PGM lock.
2152 *
2153 * @returns VBox status code
2154 * @param pVM The VM to operate on.
2155 */
2156int pgmLock(PVM pVM)
2157{
2158 int rc = PDMCritSectEnter(&pVM->pgm.s.CritSect, VERR_SEM_BUSY);
2159#if defined(IN_RC) || defined(IN_RING0)
2160 if (rc == VERR_SEM_BUSY)
2161 rc = VMMRZCallRing3NoCpu(pVM, VMMCALLRING3_PGM_LOCK, 0);
2162#endif
2163 AssertMsg(rc == VINF_SUCCESS, ("%Rrc\n", rc));
2164 return rc;
2165}
2166
2167
2168/**
2169 * Release the PGM lock.
2170 *
2171 * @returns VBox status code
2172 * @param pVM The VM to operate on.
2173 */
2174void pgmUnlock(PVM pVM)
2175{
2176 PDMCritSectLeave(&pVM->pgm.s.CritSect);
2177}
2178
2179#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2180
2181/** Common worker for PGMDynMapGCPage and PGMDynMapGCPageOff. */
2182DECLINLINE(int) pgmDynMapGCPageInternal(PVM pVM, RTGCPHYS GCPhys, void **ppv)
2183{
2184 pgmLock(pVM);
2185
2186 /*
2187 * Convert it to a writable page and it on to PGMDynMapHCPage.
2188 */
2189 int rc;
2190 PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, GCPhys);
2191 if (RT_LIKELY(pPage))
2192 {
2193 rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
2194 if (RT_SUCCESS(rc))
2195 {
2196 //Log(("PGMDynMapGCPage: GCPhys=%RGp pPage=%R[pgmpage]\n", GCPhys, pPage));
2197#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2198 rc = pgmR0DynMapHCPageInlined(&pVM->pgm.s, PGM_PAGE_GET_HCPHYS(pPage), ppv);
2199#else
2200 rc = PGMDynMapHCPage(pVM, PGM_PAGE_GET_HCPHYS(pPage), ppv);
2201#endif
2202 }
2203 else
2204 AssertRC(rc);
2205 }
2206 else
2207 {
2208 AssertMsgFailed(("Invalid physical address %RGp!\n", GCPhys));
2209 rc = VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2210 }
2211
2212 pgmUnlock(pVM);
2213 return rc;
2214}
2215
2216/**
2217 * Temporarily maps one guest page specified by GC physical address.
2218 * These pages must have a physical mapping in HC, i.e. they cannot be MMIO pages.
2219 *
2220 * Be WARNED that the dynamic page mapping area is small, 8 pages, thus the space is
2221 * reused after 8 mappings (or perhaps a few more if you score with the cache).
2222 *
2223 * @returns VBox status.
2224 * @param pVM VM handle.
2225 * @param GCPhys GC Physical address of the page.
2226 * @param ppv Where to store the address of the mapping.
2227 */
2228VMMDECL(int) PGMDynMapGCPage(PVM pVM, RTGCPHYS GCPhys, void **ppv)
2229{
2230 AssertMsg(!(GCPhys & PAGE_OFFSET_MASK), ("GCPhys=%RGp\n", GCPhys));
2231 return pgmDynMapGCPageInternal(pVM, GCPhys, ppv);
2232}
2233
2234
2235/**
2236 * Temporarily maps one guest page specified by unaligned GC physical address.
2237 * These pages must have a physical mapping in HC, i.e. they cannot be MMIO pages.
2238 *
2239 * Be WARNED that the dynamic page mapping area is small, 8 pages, thus the space is
2240 * reused after 8 mappings (or perhaps a few more if you score with the cache).
2241 *
2242 * The caller is aware that only the speicifed page is mapped and that really bad things
2243 * will happen if writing beyond the page!
2244 *
2245 * @returns VBox status.
2246 * @param pVM VM handle.
2247 * @param GCPhys GC Physical address within the page to be mapped.
2248 * @param ppv Where to store the address of the mapping address corresponding to GCPhys.
2249 */
2250VMMDECL(int) PGMDynMapGCPageOff(PVM pVM, RTGCPHYS GCPhys, void **ppv)
2251{
2252 void *pv;
2253 int rc = pgmDynMapGCPageInternal(pVM, GCPhys, &pv);
2254 if (RT_SUCCESS(rc))
2255 {
2256 *ppv = (void *)((uintptr_t)pv | (uintptr_t)(GCPhys & PAGE_OFFSET_MASK));
2257 return VINF_SUCCESS;
2258 }
2259 return rc;
2260}
2261
2262# ifdef IN_RC
2263
2264/**
2265 * Temporarily maps one host page specified by HC physical address.
2266 *
2267 * Be WARNED that the dynamic page mapping area is small, 16 pages, thus the space is
2268 * reused after 16 mappings (or perhaps a few more if you score with the cache).
2269 *
2270 * @returns VINF_SUCCESS, will bail out to ring-3 on failure.
2271 * @param pVM VM handle.
2272 * @param HCPhys HC Physical address of the page.
2273 * @param ppv Where to store the address of the mapping. This is the
2274 * address of the PAGE not the exact address corresponding
2275 * to HCPhys. Use PGMDynMapHCPageOff if you care for the
2276 * page offset.
2277 */
2278VMMDECL(int) PGMDynMapHCPage(PVM pVM, RTHCPHYS HCPhys, void **ppv)
2279{
2280 AssertMsg(!(HCPhys & PAGE_OFFSET_MASK), ("HCPhys=%RHp\n", HCPhys));
2281
2282 /*
2283 * Check the cache.
2284 */
2285 register unsigned iCache;
2286 for (iCache = 0;iCache < RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache);iCache++)
2287 {
2288 static const uint8_t au8Trans[MM_HYPER_DYNAMIC_SIZE >> PAGE_SHIFT][RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache)] =
2289 {
2290 { 0, 9, 10, 11, 12, 13, 14, 15},
2291 { 0, 1, 10, 11, 12, 13, 14, 15},
2292 { 0, 1, 2, 11, 12, 13, 14, 15},
2293 { 0, 1, 2, 3, 12, 13, 14, 15},
2294 { 0, 1, 2, 3, 4, 13, 14, 15},
2295 { 0, 1, 2, 3, 4, 5, 14, 15},
2296 { 0, 1, 2, 3, 4, 5, 6, 15},
2297 { 0, 1, 2, 3, 4, 5, 6, 7},
2298 { 8, 1, 2, 3, 4, 5, 6, 7},
2299 { 8, 9, 2, 3, 4, 5, 6, 7},
2300 { 8, 9, 10, 3, 4, 5, 6, 7},
2301 { 8, 9, 10, 11, 4, 5, 6, 7},
2302 { 8, 9, 10, 11, 12, 5, 6, 7},
2303 { 8, 9, 10, 11, 12, 13, 6, 7},
2304 { 8, 9, 10, 11, 12, 13, 14, 7},
2305 { 8, 9, 10, 11, 12, 13, 14, 15},
2306 };
2307 AssertCompile(RT_ELEMENTS(au8Trans) == 16);
2308 AssertCompile(RT_ELEMENTS(au8Trans[0]) == 8);
2309
2310 if (pVM->pgm.s.aHCPhysDynPageMapCache[iCache] == HCPhys)
2311 {
2312 int iPage = au8Trans[pVM->pgm.s.iDynPageMapLast][iCache];
2313
2314 /* The cache can get out of sync with locked entries. (10 locked, 2 overwrites its cache position, last = 11, lookup 2 -> page 10 instead of 2) */
2315 if ((pVM->pgm.s.paDynPageMap32BitPTEsGC[iPage].u & X86_PTE_PG_MASK) == HCPhys)
2316 {
2317 void *pv = pVM->pgm.s.pbDynPageMapBaseGC + (iPage << PAGE_SHIFT);
2318 *ppv = pv;
2319 STAM_COUNTER_INC(&pVM->pgm.s.StatRCDynMapCacheHits);
2320 Log4(("PGMGCDynMapHCPage: HCPhys=%RHp pv=%p iPage=%d iCache=%d\n", HCPhys, pv, iPage, iCache));
2321 return VINF_SUCCESS;
2322 }
2323 LogFlow(("Out of sync entry %d\n", iPage));
2324 }
2325 }
2326 AssertCompile(RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache) == 8);
2327 AssertCompile((MM_HYPER_DYNAMIC_SIZE >> PAGE_SHIFT) == 16);
2328 STAM_COUNTER_INC(&pVM->pgm.s.StatRCDynMapCacheMisses);
2329
2330 /*
2331 * Update the page tables.
2332 */
2333 unsigned iPage = pVM->pgm.s.iDynPageMapLast;
2334 unsigned i;
2335 for (i = 0; i < (MM_HYPER_DYNAMIC_SIZE >> PAGE_SHIFT); i++)
2336 {
2337 pVM->pgm.s.iDynPageMapLast = iPage = (iPage + 1) & ((MM_HYPER_DYNAMIC_SIZE >> PAGE_SHIFT) - 1);
2338 if (!pVM->pgm.s.aLockedDynPageMapCache[iPage])
2339 break;
2340 iPage++;
2341 }
2342 AssertRelease(i != (MM_HYPER_DYNAMIC_SIZE >> PAGE_SHIFT));
2343
2344 pVM->pgm.s.aHCPhysDynPageMapCache[iPage & (RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache) - 1)] = HCPhys;
2345 pVM->pgm.s.paDynPageMap32BitPTEsGC[iPage].u = (uint32_t)HCPhys | X86_PTE_P | X86_PTE_A | X86_PTE_D;
2346 pVM->pgm.s.paDynPageMapPaePTEsGC[iPage].u = HCPhys | X86_PTE_P | X86_PTE_A | X86_PTE_D;
2347 pVM->pgm.s.aLockedDynPageMapCache[iPage] = 0;
2348
2349 void *pv = pVM->pgm.s.pbDynPageMapBaseGC + (iPage << PAGE_SHIFT);
2350 *ppv = pv;
2351 ASMInvalidatePage(pv);
2352 Log4(("PGMGCDynMapHCPage: HCPhys=%RHp pv=%p iPage=%d\n", HCPhys, pv, iPage));
2353 return VINF_SUCCESS;
2354}
2355
2356
2357/**
2358 * Temporarily lock a dynamic page to prevent it from being reused.
2359 *
2360 * @param pVM VM handle.
2361 * @param GCPage GC address of page
2362 */
2363VMMDECL(void) PGMDynLockHCPage(PVM pVM, RCPTRTYPE(uint8_t *) GCPage)
2364{
2365 unsigned iPage;
2366
2367 Assert(GCPage >= pVM->pgm.s.pbDynPageMapBaseGC && GCPage < (pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE));
2368 iPage = ((uintptr_t)(GCPage - pVM->pgm.s.pbDynPageMapBaseGC)) >> PAGE_SHIFT;
2369 ASMAtomicIncU32(&pVM->pgm.s.aLockedDynPageMapCache[iPage]);
2370 Log4(("PGMDynLockHCPage %RRv iPage=%d\n", GCPage, iPage));
2371}
2372
2373
2374/**
2375 * Unlock a dynamic page
2376 *
2377 * @param pVM VM handle.
2378 * @param GCPage GC address of page
2379 */
2380VMMDECL(void) PGMDynUnlockHCPage(PVM pVM, RCPTRTYPE(uint8_t *) GCPage)
2381{
2382 unsigned iPage;
2383
2384 AssertCompile(RT_ELEMENTS(pVM->pgm.s.aLockedDynPageMapCache) == 2* RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache));
2385 AssertCompileMemberSize(VM, pgm.s.aLockedDynPageMapCache, sizeof(uint32_t) * (MM_HYPER_DYNAMIC_SIZE >> (PAGE_SHIFT)));
2386
2387 Assert(GCPage >= pVM->pgm.s.pbDynPageMapBaseGC && GCPage < (pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE));
2388 iPage = ((uintptr_t)(GCPage - pVM->pgm.s.pbDynPageMapBaseGC)) >> PAGE_SHIFT;
2389 Assert(pVM->pgm.s.aLockedDynPageMapCache[iPage]);
2390 ASMAtomicDecU32(&pVM->pgm.s.aLockedDynPageMapCache[iPage]);
2391 Log4(("PGMDynUnlockHCPage %RRv iPage=%d\n", GCPage, iPage));
2392}
2393
2394
2395# ifdef VBOX_STRICT
2396/**
2397 * Check for lock leaks.
2398 *
2399 * @param pVM VM handle.
2400 */
2401VMMDECL(void) PGMDynCheckLocks(PVM pVM)
2402{
2403 for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.aLockedDynPageMapCache); i++)
2404 Assert(!pVM->pgm.s.aLockedDynPageMapCache[i]);
2405}
2406# endif /* VBOX_STRICT */
2407
2408# endif /* IN_RC */
2409#endif /* IN_RC || VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
2410
2411#if !defined(IN_R0) || defined(LOG_ENABLED)
2412
2413/** Format handler for PGMPAGE.
2414 * @copydoc FNRTSTRFORMATTYPE */
2415static DECLCALLBACK(size_t) pgmFormatTypeHandlerPage(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
2416 const char *pszType, void const *pvValue,
2417 int cchWidth, int cchPrecision, unsigned fFlags,
2418 void *pvUser)
2419{
2420 size_t cch;
2421 PCPGMPAGE pPage = (PCPGMPAGE)pvValue;
2422 if (VALID_PTR(pPage))
2423 {
2424 char szTmp[64+80];
2425
2426 cch = 0;
2427
2428 /* The single char state stuff. */
2429 static const char s_achPageStates[4] = { 'Z', 'A', 'W', 'S' };
2430 szTmp[cch++] = s_achPageStates[PGM_PAGE_GET_STATE(pPage)];
2431
2432#define IS_PART_INCLUDED(lvl) ( !(fFlags & RTSTR_F_PRECISION) || cchPrecision == (lvl) || cchPrecision >= (lvl)+10 )
2433 if (IS_PART_INCLUDED(5))
2434 {
2435 static const char s_achHandlerStates[4] = { '-', 't', 'w', 'a' };
2436 szTmp[cch++] = s_achHandlerStates[PGM_PAGE_GET_HNDL_PHYS_STATE(pPage)];
2437 szTmp[cch++] = s_achHandlerStates[PGM_PAGE_GET_HNDL_VIRT_STATE(pPage)];
2438 }
2439
2440 /* The type. */
2441 if (IS_PART_INCLUDED(4))
2442 {
2443 szTmp[cch++] = ':';
2444 static const char s_achPageTypes[8][4] = { "INV", "RAM", "MI2", "M2A", "SHA", "ROM", "MIO", "BAD" };
2445 szTmp[cch++] = s_achPageTypes[PGM_PAGE_GET_TYPE(pPage)][0];
2446 szTmp[cch++] = s_achPageTypes[PGM_PAGE_GET_TYPE(pPage)][1];
2447 szTmp[cch++] = s_achPageTypes[PGM_PAGE_GET_TYPE(pPage)][2];
2448 }
2449
2450 /* The numbers. */
2451 if (IS_PART_INCLUDED(3))
2452 {
2453 szTmp[cch++] = ':';
2454 cch += RTStrFormatNumber(&szTmp[cch], PGM_PAGE_GET_HCPHYS(pPage), 16, 12, 0, RTSTR_F_ZEROPAD | RTSTR_F_64BIT);
2455 }
2456
2457 if (IS_PART_INCLUDED(2))
2458 {
2459 szTmp[cch++] = ':';
2460 cch += RTStrFormatNumber(&szTmp[cch], PGM_PAGE_GET_PAGEID(pPage), 16, 7, 0, RTSTR_F_ZEROPAD | RTSTR_F_32BIT);
2461 }
2462
2463 if (IS_PART_INCLUDED(6))
2464 {
2465 szTmp[cch++] = ':';
2466 static const char s_achRefs[4] = { '-', 'U', '!', 'L' };
2467 szTmp[cch++] = s_achRefs[PGM_PAGE_GET_TD_CREFS(pPage)];
2468 cch += RTStrFormatNumber(&szTmp[cch], PGM_PAGE_GET_TD_IDX(pPage), 16, 4, 0, RTSTR_F_ZEROPAD | RTSTR_F_16BIT);
2469 }
2470#undef IS_PART_INCLUDED
2471
2472 cch = pfnOutput(pvArgOutput, szTmp, cch);
2473 }
2474 else
2475 cch = pfnOutput(pvArgOutput, "<bad-pgmpage-ptr>", sizeof("<bad-pgmpage-ptr>") - 1);
2476 return cch;
2477}
2478
2479
2480/** Format handler for PGMRAMRANGE.
2481 * @copydoc FNRTSTRFORMATTYPE */
2482static DECLCALLBACK(size_t) pgmFormatTypeHandlerRamRange(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
2483 const char *pszType, void const *pvValue,
2484 int cchWidth, int cchPrecision, unsigned fFlags,
2485 void *pvUser)
2486{
2487 size_t cch;
2488 PGMRAMRANGE const *pRam = (PGMRAMRANGE const *)pvValue;
2489 if (VALID_PTR(pRam))
2490 {
2491 char szTmp[80];
2492 cch = RTStrPrintf(szTmp, sizeof(szTmp), "%RGp-%RGp", pRam->GCPhys, pRam->GCPhysLast);
2493 cch = pfnOutput(pvArgOutput, szTmp, cch);
2494 }
2495 else
2496 cch = pfnOutput(pvArgOutput, "<bad-pgmramrange-ptr>", sizeof("<bad-pgmramrange-ptr>") - 1);
2497 return cch;
2498}
2499
2500/** Format type andlers to be registered/deregistered. */
2501static const struct
2502{
2503 char szType[24];
2504 PFNRTSTRFORMATTYPE pfnHandler;
2505} g_aPgmFormatTypes[] =
2506{
2507 { "pgmpage", pgmFormatTypeHandlerPage },
2508 { "pgmramrange", pgmFormatTypeHandlerRamRange }
2509};
2510
2511#endif /* !IN_R0 || LOG_ENABLED */
2512
2513/**
2514 * Registers the global string format types.
2515 *
2516 * This should be called at module load time or in some other manner that ensure
2517 * that it's called exactly one time.
2518 *
2519 * @returns IPRT status code on RTStrFormatTypeRegister failure.
2520 */
2521VMMDECL(int) PGMRegisterStringFormatTypes(void)
2522{
2523#if !defined(IN_R0) || defined(LOG_ENABLED)
2524 int rc = VINF_SUCCESS;
2525 unsigned i;
2526 for (i = 0; RT_SUCCESS(rc) && i < RT_ELEMENTS(g_aPgmFormatTypes); i++)
2527 {
2528 rc = RTStrFormatTypeRegister(g_aPgmFormatTypes[i].szType, g_aPgmFormatTypes[i].pfnHandler, NULL);
2529# ifdef IN_RING0
2530 if (rc == VERR_ALREADY_EXISTS)
2531 {
2532 /* in case of cleanup failure in ring-0 */
2533 RTStrFormatTypeDeregister(g_aPgmFormatTypes[i].szType);
2534 rc = RTStrFormatTypeRegister(g_aPgmFormatTypes[i].szType, g_aPgmFormatTypes[i].pfnHandler, NULL);
2535 }
2536# endif
2537 }
2538 if (RT_FAILURE(rc))
2539 while (i-- > 0)
2540 RTStrFormatTypeDeregister(g_aPgmFormatTypes[i].szType);
2541
2542 return rc;
2543#else
2544 return VINF_SUCCESS;
2545#endif
2546}
2547
2548
2549/**
2550 * Deregisters the global string format types.
2551 *
2552 * This should be called at module unload time or in some other manner that
2553 * ensure that it's called exactly one time.
2554 */
2555VMMDECL(void) PGMDeregisterStringFormatTypes(void)
2556{
2557#if !defined(IN_R0) || defined(LOG_ENABLED)
2558 for (unsigned i = 0; i < RT_ELEMENTS(g_aPgmFormatTypes); i++)
2559 RTStrFormatTypeDeregister(g_aPgmFormatTypes[i].szType);
2560#endif
2561}
2562
2563#ifdef VBOX_STRICT
2564
2565/**
2566 * Asserts that there are no mapping conflicts.
2567 *
2568 * @returns Number of conflicts.
2569 * @param pVM The VM Handle.
2570 */
2571VMMDECL(unsigned) PGMAssertNoMappingConflicts(PVM pVM)
2572{
2573 unsigned cErrors = 0;
2574
2575 /* Only applies to raw mode -> 1 VPCU */
2576 Assert(pVM->cCpus == 1);
2577 PVMCPU pVCpu = &pVM->aCpus[0];
2578
2579 /*
2580 * Check for mapping conflicts.
2581 */
2582 for (PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
2583 pMapping;
2584 pMapping = pMapping->CTX_SUFF(pNext))
2585 {
2586 /** @todo This is slow and should be optimized, but since it's just assertions I don't care now. */
2587 for (RTGCPTR GCPtr = pMapping->GCPtr;
2588 GCPtr <= pMapping->GCPtrLast;
2589 GCPtr += PAGE_SIZE)
2590 {
2591 int rc = PGMGstGetPage(pVCpu, (RTGCPTR)GCPtr, NULL, NULL);
2592 if (rc != VERR_PAGE_TABLE_NOT_PRESENT)
2593 {
2594 AssertMsgFailed(("Conflict at %RGv with %s\n", GCPtr, R3STRING(pMapping->pszDesc)));
2595 cErrors++;
2596 break;
2597 }
2598 }
2599 }
2600
2601 return cErrors;
2602}
2603
2604
2605/**
2606 * Asserts that everything related to the guest CR3 is correctly shadowed.
2607 *
2608 * This will call PGMAssertNoMappingConflicts() and PGMAssertHandlerAndFlagsInSync(),
2609 * and assert the correctness of the guest CR3 mapping before asserting that the
2610 * shadow page tables is in sync with the guest page tables.
2611 *
2612 * @returns Number of conflicts.
2613 * @param pVM The VM Handle.
2614 * @param pVCpu VMCPU handle.
2615 * @param cr3 The current guest CR3 register value.
2616 * @param cr4 The current guest CR4 register value.
2617 */
2618VMMDECL(unsigned) PGMAssertCR3(PVM pVM, PVMCPU pVCpu, uint64_t cr3, uint64_t cr4)
2619{
2620 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncCR3), a);
2621 pgmLock(pVM);
2622 unsigned cErrors = PGM_BTH_PFN(AssertCR3, pVCpu)(pVCpu, cr3, cr4, 0, ~(RTGCPTR)0);
2623 pgmUnlock(pVM);
2624 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncCR3), a);
2625 return cErrors;
2626}
2627
2628#endif /* VBOX_STRICT */
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