VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAll.cpp@ 31565

Last change on this file since 31565 was 31565, checked in by vboxsync, 14 years ago

PGM,HWACCM: MMIO optimizations - coding in progress.
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1/* $Id: PGMAll.cpp 31565 2010-08-11 12:47:07Z vboxsync $ */
2/** @file
3 * PGM - Page Manager and Monitor - All context code.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/*******************************************************************************
19* Header Files *
20*******************************************************************************/
21#define LOG_GROUP LOG_GROUP_PGM
22#include <VBox/pgm.h>
23#include <VBox/cpum.h>
24#include <VBox/selm.h>
25#include <VBox/iom.h>
26#include <VBox/sup.h>
27#include <VBox/mm.h>
28#include <VBox/stam.h>
29#include <VBox/csam.h>
30#include <VBox/patm.h>
31#include <VBox/trpm.h>
32#include <VBox/rem.h>
33#include <VBox/em.h>
34#include <VBox/hwaccm.h>
35#include <VBox/hwacc_vmx.h>
36#include "../PGMInternal.h"
37#include <VBox/vm.h>
38#include "../PGMInline.h"
39#include <iprt/assert.h>
40#include <iprt/asm-amd64-x86.h>
41#include <iprt/string.h>
42#include <VBox/log.h>
43#include <VBox/param.h>
44#include <VBox/err.h>
45
46
47/*******************************************************************************
48* Structures and Typedefs *
49*******************************************************************************/
50/**
51 * Stated structure for PGM_GST_NAME(HandlerVirtualUpdate) that's
52 * passed to PGM_GST_NAME(VirtHandlerUpdateOne) during enumeration.
53 */
54typedef struct PGMHVUSTATE
55{
56 /** The VM handle. */
57 PVM pVM;
58 /** The VMCPU handle. */
59 PVMCPU pVCpu;
60 /** The todo flags. */
61 RTUINT fTodo;
62 /** The CR4 register value. */
63 uint32_t cr4;
64} PGMHVUSTATE, *PPGMHVUSTATE;
65
66
67/*******************************************************************************
68* Internal Functions *
69*******************************************************************************/
70DECLINLINE(int) pgmShwGetLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPT *ppPdpt, PX86PDPAE *ppPD);
71DECLINLINE(int) pgmShwGetPaePoolPagePD(PVMCPU pVCpu, RTGCPTR GCPtr, PPGMPOOLPAGE *ppShwPde);
72#ifndef IN_RC
73static int pgmShwSyncLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, X86PGPAEUINT uGstPml4e, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD);
74static int pgmShwGetEPTPDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PEPTPDPT *ppPdpt, PEPTPD *ppPD);
75#endif
76
77
78/*
79 * Shadow - 32-bit mode
80 */
81#define PGM_SHW_TYPE PGM_TYPE_32BIT
82#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
83#include "PGMAllShw.h"
84
85/* Guest - real mode */
86#define PGM_GST_TYPE PGM_TYPE_REAL
87#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
88#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
89#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
90#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
91#include "PGMGstDefs.h"
92#include "PGMAllGst.h"
93#include "PGMAllBth.h"
94#undef BTH_PGMPOOLKIND_PT_FOR_PT
95#undef BTH_PGMPOOLKIND_ROOT
96#undef PGM_BTH_NAME
97#undef PGM_GST_TYPE
98#undef PGM_GST_NAME
99
100/* Guest - protected mode */
101#define PGM_GST_TYPE PGM_TYPE_PROT
102#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
103#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
104#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
105#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
106#include "PGMGstDefs.h"
107#include "PGMAllGst.h"
108#include "PGMAllBth.h"
109#undef BTH_PGMPOOLKIND_PT_FOR_PT
110#undef BTH_PGMPOOLKIND_ROOT
111#undef PGM_BTH_NAME
112#undef PGM_GST_TYPE
113#undef PGM_GST_NAME
114
115/* Guest - 32-bit mode */
116#define PGM_GST_TYPE PGM_TYPE_32BIT
117#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
118#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
119#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
120#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
121#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD
122#include "PGMGstDefs.h"
123#include "PGMAllGst.h"
124#include "PGMAllBth.h"
125#undef BTH_PGMPOOLKIND_PT_FOR_BIG
126#undef BTH_PGMPOOLKIND_PT_FOR_PT
127#undef BTH_PGMPOOLKIND_ROOT
128#undef PGM_BTH_NAME
129#undef PGM_GST_TYPE
130#undef PGM_GST_NAME
131
132#undef PGM_SHW_TYPE
133#undef PGM_SHW_NAME
134
135
136/*
137 * Shadow - PAE mode
138 */
139#define PGM_SHW_TYPE PGM_TYPE_PAE
140#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
141#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
142#include "PGMAllShw.h"
143
144/* Guest - real mode */
145#define PGM_GST_TYPE PGM_TYPE_REAL
146#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
147#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
148#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
149#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
150#include "PGMGstDefs.h"
151#include "PGMAllBth.h"
152#undef BTH_PGMPOOLKIND_PT_FOR_PT
153#undef BTH_PGMPOOLKIND_ROOT
154#undef PGM_BTH_NAME
155#undef PGM_GST_TYPE
156#undef PGM_GST_NAME
157
158/* Guest - protected mode */
159#define PGM_GST_TYPE PGM_TYPE_PROT
160#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
161#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
162#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
163#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
164#include "PGMGstDefs.h"
165#include "PGMAllBth.h"
166#undef BTH_PGMPOOLKIND_PT_FOR_PT
167#undef BTH_PGMPOOLKIND_ROOT
168#undef PGM_BTH_NAME
169#undef PGM_GST_TYPE
170#undef PGM_GST_NAME
171
172/* Guest - 32-bit mode */
173#define PGM_GST_TYPE PGM_TYPE_32BIT
174#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
175#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
176#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
177#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
178#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_FOR_32BIT
179#include "PGMGstDefs.h"
180#include "PGMAllBth.h"
181#undef BTH_PGMPOOLKIND_PT_FOR_BIG
182#undef BTH_PGMPOOLKIND_PT_FOR_PT
183#undef BTH_PGMPOOLKIND_ROOT
184#undef PGM_BTH_NAME
185#undef PGM_GST_TYPE
186#undef PGM_GST_NAME
187
188
189/* Guest - PAE mode */
190#define PGM_GST_TYPE PGM_TYPE_PAE
191#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
192#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
193#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
194#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
195#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT
196#include "PGMGstDefs.h"
197#include "PGMAllGst.h"
198#include "PGMAllBth.h"
199#undef BTH_PGMPOOLKIND_PT_FOR_BIG
200#undef BTH_PGMPOOLKIND_PT_FOR_PT
201#undef BTH_PGMPOOLKIND_ROOT
202#undef PGM_BTH_NAME
203#undef PGM_GST_TYPE
204#undef PGM_GST_NAME
205
206#undef PGM_SHW_TYPE
207#undef PGM_SHW_NAME
208
209
210#ifndef IN_RC /* AMD64 implies VT-x/AMD-V */
211/*
212 * Shadow - AMD64 mode
213 */
214# define PGM_SHW_TYPE PGM_TYPE_AMD64
215# define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
216# include "PGMAllShw.h"
217
218/* Guest - protected mode (only used for AMD-V nested paging in 64 bits mode) */
219# define PGM_GST_TYPE PGM_TYPE_PROT
220# define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
221# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_PROT(name)
222# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
223# define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PD_PHYS
224# include "PGMGstDefs.h"
225# include "PGMAllBth.h"
226# undef BTH_PGMPOOLKIND_PT_FOR_PT
227# undef BTH_PGMPOOLKIND_ROOT
228# undef PGM_BTH_NAME
229# undef PGM_GST_TYPE
230# undef PGM_GST_NAME
231
232# ifdef VBOX_WITH_64_BITS_GUESTS
233/* Guest - AMD64 mode */
234# define PGM_GST_TYPE PGM_TYPE_AMD64
235# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
236# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
237# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
238# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
239# define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_64BIT_PML4
240# include "PGMGstDefs.h"
241# include "PGMAllGst.h"
242# include "PGMAllBth.h"
243# undef BTH_PGMPOOLKIND_PT_FOR_BIG
244# undef BTH_PGMPOOLKIND_PT_FOR_PT
245# undef BTH_PGMPOOLKIND_ROOT
246# undef PGM_BTH_NAME
247# undef PGM_GST_TYPE
248# undef PGM_GST_NAME
249# endif /* VBOX_WITH_64_BITS_GUESTS */
250
251# undef PGM_SHW_TYPE
252# undef PGM_SHW_NAME
253
254
255/*
256 * Shadow - Nested paging mode
257 */
258# define PGM_SHW_TYPE PGM_TYPE_NESTED
259# define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED(name)
260# include "PGMAllShw.h"
261
262/* Guest - real mode */
263# define PGM_GST_TYPE PGM_TYPE_REAL
264# define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
265# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_REAL(name)
266# include "PGMGstDefs.h"
267# include "PGMAllBth.h"
268# undef PGM_BTH_NAME
269# undef PGM_GST_TYPE
270# undef PGM_GST_NAME
271
272/* Guest - protected mode */
273# define PGM_GST_TYPE PGM_TYPE_PROT
274# define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
275# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PROT(name)
276# include "PGMGstDefs.h"
277# include "PGMAllBth.h"
278# undef PGM_BTH_NAME
279# undef PGM_GST_TYPE
280# undef PGM_GST_NAME
281
282/* Guest - 32-bit mode */
283# define PGM_GST_TYPE PGM_TYPE_32BIT
284# define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
285# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT(name)
286# include "PGMGstDefs.h"
287# include "PGMAllBth.h"
288# undef PGM_BTH_NAME
289# undef PGM_GST_TYPE
290# undef PGM_GST_NAME
291
292/* Guest - PAE mode */
293# define PGM_GST_TYPE PGM_TYPE_PAE
294# define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
295# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE(name)
296# include "PGMGstDefs.h"
297# include "PGMAllBth.h"
298# undef PGM_BTH_NAME
299# undef PGM_GST_TYPE
300# undef PGM_GST_NAME
301
302# ifdef VBOX_WITH_64_BITS_GUESTS
303/* Guest - AMD64 mode */
304# define PGM_GST_TYPE PGM_TYPE_AMD64
305# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
306# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64(name)
307# include "PGMGstDefs.h"
308# include "PGMAllBth.h"
309# undef PGM_BTH_NAME
310# undef PGM_GST_TYPE
311# undef PGM_GST_NAME
312# endif /* VBOX_WITH_64_BITS_GUESTS */
313
314# undef PGM_SHW_TYPE
315# undef PGM_SHW_NAME
316
317
318/*
319 * Shadow - EPT
320 */
321# define PGM_SHW_TYPE PGM_TYPE_EPT
322# define PGM_SHW_NAME(name) PGM_SHW_NAME_EPT(name)
323# include "PGMAllShw.h"
324
325/* Guest - real mode */
326# define PGM_GST_TYPE PGM_TYPE_REAL
327# define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
328# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_REAL(name)
329# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
330# include "PGMGstDefs.h"
331# include "PGMAllBth.h"
332# undef BTH_PGMPOOLKIND_PT_FOR_PT
333# undef PGM_BTH_NAME
334# undef PGM_GST_TYPE
335# undef PGM_GST_NAME
336
337/* Guest - protected mode */
338# define PGM_GST_TYPE PGM_TYPE_PROT
339# define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
340# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PROT(name)
341# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
342# include "PGMGstDefs.h"
343# include "PGMAllBth.h"
344# undef BTH_PGMPOOLKIND_PT_FOR_PT
345# undef PGM_BTH_NAME
346# undef PGM_GST_TYPE
347# undef PGM_GST_NAME
348
349/* Guest - 32-bit mode */
350# define PGM_GST_TYPE PGM_TYPE_32BIT
351# define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
352# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_32BIT(name)
353# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
354# include "PGMGstDefs.h"
355# include "PGMAllBth.h"
356# undef BTH_PGMPOOLKIND_PT_FOR_PT
357# undef PGM_BTH_NAME
358# undef PGM_GST_TYPE
359# undef PGM_GST_NAME
360
361/* Guest - PAE mode */
362# define PGM_GST_TYPE PGM_TYPE_PAE
363# define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
364# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PAE(name)
365# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
366# include "PGMGstDefs.h"
367# include "PGMAllBth.h"
368# undef BTH_PGMPOOLKIND_PT_FOR_PT
369# undef PGM_BTH_NAME
370# undef PGM_GST_TYPE
371# undef PGM_GST_NAME
372
373# ifdef VBOX_WITH_64_BITS_GUESTS
374/* Guest - AMD64 mode */
375# define PGM_GST_TYPE PGM_TYPE_AMD64
376# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
377# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_AMD64(name)
378# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
379# include "PGMGstDefs.h"
380# include "PGMAllBth.h"
381# undef BTH_PGMPOOLKIND_PT_FOR_PT
382# undef PGM_BTH_NAME
383# undef PGM_GST_TYPE
384# undef PGM_GST_NAME
385# endif /* VBOX_WITH_64_BITS_GUESTS */
386
387# undef PGM_SHW_TYPE
388# undef PGM_SHW_NAME
389
390#endif /* !IN_RC */
391
392
393#ifndef IN_RING3
394/**
395 * #PF Handler.
396 *
397 * @returns VBox status code (appropriate for trap handling and GC return).
398 * @param pVCpu VMCPU handle.
399 * @param uErr The trap error code.
400 * @param pRegFrame Trap register frame.
401 * @param pvFault The fault address.
402 */
403VMMDECL(int) PGMTrap0eHandler(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
404{
405 PVM pVM = pVCpu->CTX_SUFF(pVM);
406
407 Log(("PGMTrap0eHandler: uErr=%RGx pvFault=%RGv eip=%04x:%RGv\n", uErr, pvFault, pRegFrame->cs, (RTGCPTR)pRegFrame->rip));
408 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0e, a);
409 STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = NULL; } );
410
411
412#ifdef VBOX_WITH_STATISTICS
413 /*
414 * Error code stats.
415 */
416 if (uErr & X86_TRAP_PF_US)
417 {
418 if (!(uErr & X86_TRAP_PF_P))
419 {
420 if (uErr & X86_TRAP_PF_RW)
421 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eUSNotPresentWrite);
422 else
423 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eUSNotPresentRead);
424 }
425 else if (uErr & X86_TRAP_PF_RW)
426 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eUSWrite);
427 else if (uErr & X86_TRAP_PF_RSVD)
428 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eUSReserved);
429 else if (uErr & X86_TRAP_PF_ID)
430 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eUSNXE);
431 else
432 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eUSRead);
433 }
434 else
435 { /* Supervisor */
436 if (!(uErr & X86_TRAP_PF_P))
437 {
438 if (uErr & X86_TRAP_PF_RW)
439 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eSVNotPresentWrite);
440 else
441 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eSVNotPresentRead);
442 }
443 else if (uErr & X86_TRAP_PF_RW)
444 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eSVWrite);
445 else if (uErr & X86_TRAP_PF_ID)
446 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eSNXE);
447 else if (uErr & X86_TRAP_PF_RSVD)
448 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eSVReserved);
449 }
450#endif /* VBOX_WITH_STATISTICS */
451
452 /*
453 * Call the worker.
454 */
455 bool fLockTaken = false;
456 int rc = PGM_BTH_PFN(Trap0eHandler, pVCpu)(pVCpu, uErr, pRegFrame, pvFault, &fLockTaken);
457 if (fLockTaken)
458 {
459 Assert(PGMIsLockOwner(pVM));
460 pgmUnlock(pVM);
461 }
462 if (rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
463 rc = VINF_SUCCESS;
464
465# ifdef IN_RING0
466 /* Note: hack alert for difficult to reproduce problem. */
467 if ( rc == VERR_PAGE_NOT_PRESENT /* SMP only ; disassembly might fail. */
468 || rc == VERR_PAGE_TABLE_NOT_PRESENT /* seen with UNI & SMP */
469 || rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT /* seen with SMP */
470 || rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT) /* precaution */
471 {
472 Log(("WARNING: Unexpected VERR_PAGE_TABLE_NOT_PRESENT (%d) for page fault at %RGv error code %x (rip=%RGv)\n", rc, pvFault, uErr, pRegFrame->rip));
473 /* Some kind of inconsistency in the SMP case; it's safe to just execute the instruction again; not sure about single VCPU VMs though. */
474 rc = VINF_SUCCESS;
475 }
476# endif
477
478 STAM_STATS({ if (rc == VINF_EM_RAW_GUEST_TRAP) STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eGuestPF); });
479 STAM_STATS({ if (!pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution))
480 pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Misc; });
481 STAM_PROFILE_STOP_EX(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0e, pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution), a);
482 return rc;
483}
484#endif /* !IN_RING3 */
485
486
487/**
488 * Prefetch a page
489 *
490 * Typically used to sync commonly used pages before entering raw mode
491 * after a CR3 reload.
492 *
493 * @returns VBox status code suitable for scheduling.
494 * @retval VINF_SUCCESS on success.
495 * @retval VINF_PGM_SYNC_CR3 if we're out of shadow pages or something like that.
496 * @param pVCpu VMCPU handle.
497 * @param GCPtrPage Page to invalidate.
498 */
499VMMDECL(int) PGMPrefetchPage(PVMCPU pVCpu, RTGCPTR GCPtrPage)
500{
501 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Prefetch), a);
502 int rc = PGM_BTH_PFN(PrefetchPage, pVCpu)(pVCpu, GCPtrPage);
503 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Prefetch), a);
504 AssertMsg(rc == VINF_SUCCESS || rc == VINF_PGM_SYNC_CR3 || RT_FAILURE(rc), ("rc=%Rrc\n", rc));
505 return rc;
506}
507
508
509/**
510 * Gets the mapping corresponding to the specified address (if any).
511 *
512 * @returns Pointer to the mapping.
513 * @returns NULL if not
514 *
515 * @param pVM The virtual machine.
516 * @param GCPtr The guest context pointer.
517 */
518PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr)
519{
520 PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
521 while (pMapping)
522 {
523 if ((uintptr_t)GCPtr < (uintptr_t)pMapping->GCPtr)
524 break;
525 if ((uintptr_t)GCPtr - (uintptr_t)pMapping->GCPtr < pMapping->cb)
526 return pMapping;
527 pMapping = pMapping->CTX_SUFF(pNext);
528 }
529 return NULL;
530}
531
532
533/**
534 * Verifies a range of pages for read or write access
535 *
536 * Only checks the guest's page tables
537 *
538 * @returns VBox status code.
539 * @param pVCpu VMCPU handle.
540 * @param Addr Guest virtual address to check
541 * @param cbSize Access size
542 * @param fAccess Access type (r/w, user/supervisor (X86_PTE_*))
543 * @remarks Current not in use.
544 */
545VMMDECL(int) PGMIsValidAccess(PVMCPU pVCpu, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess)
546{
547 /*
548 * Validate input.
549 */
550 if (fAccess & ~(X86_PTE_US | X86_PTE_RW))
551 {
552 AssertMsgFailed(("PGMIsValidAccess: invalid access type %08x\n", fAccess));
553 return VERR_INVALID_PARAMETER;
554 }
555
556 uint64_t fPage;
557 int rc = PGMGstGetPage(pVCpu, (RTGCPTR)Addr, &fPage, NULL);
558 if (RT_FAILURE(rc))
559 {
560 Log(("PGMIsValidAccess: access violation for %RGv rc=%d\n", Addr, rc));
561 return VINF_EM_RAW_GUEST_TRAP;
562 }
563
564 /*
565 * Check if the access would cause a page fault
566 *
567 * Note that hypervisor page directories are not present in the guest's tables, so this check
568 * is sufficient.
569 */
570 bool fWrite = !!(fAccess & X86_PTE_RW);
571 bool fUser = !!(fAccess & X86_PTE_US);
572 if ( !(fPage & X86_PTE_P)
573 || (fWrite && !(fPage & X86_PTE_RW))
574 || (fUser && !(fPage & X86_PTE_US)) )
575 {
576 Log(("PGMIsValidAccess: access violation for %RGv attr %#llx vs %d:%d\n", Addr, fPage, fWrite, fUser));
577 return VINF_EM_RAW_GUEST_TRAP;
578 }
579 if ( RT_SUCCESS(rc)
580 && PAGE_ADDRESS(Addr) != PAGE_ADDRESS(Addr + cbSize))
581 return PGMIsValidAccess(pVCpu, Addr + PAGE_SIZE, (cbSize > PAGE_SIZE) ? cbSize - PAGE_SIZE : 1, fAccess);
582 return rc;
583}
584
585
586/**
587 * Verifies a range of pages for read or write access
588 *
589 * Supports handling of pages marked for dirty bit tracking and CSAM
590 *
591 * @returns VBox status code.
592 * @param pVCpu VMCPU handle.
593 * @param Addr Guest virtual address to check
594 * @param cbSize Access size
595 * @param fAccess Access type (r/w, user/supervisor (X86_PTE_*))
596 */
597VMMDECL(int) PGMVerifyAccess(PVMCPU pVCpu, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess)
598{
599 PVM pVM = pVCpu->CTX_SUFF(pVM);
600
601 AssertMsg(!(fAccess & ~(X86_PTE_US | X86_PTE_RW)), ("PGMVerifyAccess: invalid access type %08x\n", fAccess));
602
603 /*
604 * Get going.
605 */
606 uint64_t fPageGst;
607 int rc = PGMGstGetPage(pVCpu, (RTGCPTR)Addr, &fPageGst, NULL);
608 if (RT_FAILURE(rc))
609 {
610 Log(("PGMVerifyAccess: access violation for %RGv rc=%d\n", Addr, rc));
611 return VINF_EM_RAW_GUEST_TRAP;
612 }
613
614 /*
615 * Check if the access would cause a page fault
616 *
617 * Note that hypervisor page directories are not present in the guest's tables, so this check
618 * is sufficient.
619 */
620 const bool fWrite = !!(fAccess & X86_PTE_RW);
621 const bool fUser = !!(fAccess & X86_PTE_US);
622 if ( !(fPageGst & X86_PTE_P)
623 || (fWrite && !(fPageGst & X86_PTE_RW))
624 || (fUser && !(fPageGst & X86_PTE_US)) )
625 {
626 Log(("PGMVerifyAccess: access violation for %RGv attr %#llx vs %d:%d\n", Addr, fPageGst, fWrite, fUser));
627 return VINF_EM_RAW_GUEST_TRAP;
628 }
629
630 if (!pVM->pgm.s.fNestedPaging)
631 {
632 /*
633 * Next step is to verify if we protected this page for dirty bit tracking or for CSAM scanning
634 */
635 rc = PGMShwGetPage(pVCpu, (RTGCPTR)Addr, NULL, NULL);
636 if ( rc == VERR_PAGE_NOT_PRESENT
637 || rc == VERR_PAGE_TABLE_NOT_PRESENT)
638 {
639 /*
640 * Page is not present in our page tables.
641 * Try to sync it!
642 */
643 Assert(X86_TRAP_PF_RW == X86_PTE_RW && X86_TRAP_PF_US == X86_PTE_US);
644 uint32_t uErr = fAccess & (X86_TRAP_PF_RW | X86_TRAP_PF_US);
645 rc = PGM_BTH_PFN(VerifyAccessSyncPage, pVCpu)(pVCpu, Addr, fPageGst, uErr);
646 if (rc != VINF_SUCCESS)
647 return rc;
648 }
649 else
650 AssertMsg(rc == VINF_SUCCESS, ("PGMShwGetPage %RGv failed with %Rrc\n", Addr, rc));
651 }
652
653#if 0 /* def VBOX_STRICT; triggers too often now */
654 /*
655 * This check is a bit paranoid, but useful.
656 */
657 /* Note! This will assert when writing to monitored pages (a bit annoying actually). */
658 uint64_t fPageShw;
659 rc = PGMShwGetPage(pVCpu, (RTGCPTR)Addr, &fPageShw, NULL);
660 if ( (rc == VERR_PAGE_NOT_PRESENT || RT_FAILURE(rc))
661 || (fWrite && !(fPageShw & X86_PTE_RW))
662 || (fUser && !(fPageShw & X86_PTE_US)) )
663 {
664 AssertMsgFailed(("Unexpected access violation for %RGv! rc=%Rrc write=%d user=%d\n",
665 Addr, rc, fWrite && !(fPageShw & X86_PTE_RW), fUser && !(fPageShw & X86_PTE_US)));
666 return VINF_EM_RAW_GUEST_TRAP;
667 }
668#endif
669
670 if ( RT_SUCCESS(rc)
671 && ( PAGE_ADDRESS(Addr) != PAGE_ADDRESS(Addr + cbSize - 1)
672 || Addr + cbSize < Addr))
673 {
674 /* Don't recursively call PGMVerifyAccess as we might run out of stack. */
675 for (;;)
676 {
677 Addr += PAGE_SIZE;
678 if (cbSize > PAGE_SIZE)
679 cbSize -= PAGE_SIZE;
680 else
681 cbSize = 1;
682 rc = PGMVerifyAccess(pVCpu, Addr, 1, fAccess);
683 if (rc != VINF_SUCCESS)
684 break;
685 if (PAGE_ADDRESS(Addr) == PAGE_ADDRESS(Addr + cbSize - 1))
686 break;
687 }
688 }
689 return rc;
690}
691
692
693/**
694 * Emulation of the invlpg instruction (HC only actually).
695 *
696 * @returns VBox status code, special care required.
697 * @retval VINF_PGM_SYNC_CR3 - handled.
698 * @retval VINF_EM_RAW_EMULATE_INSTR - not handled (RC only).
699 * @retval VERR_REM_FLUSHED_PAGES_OVERFLOW - not handled.
700 *
701 * @param pVCpu VMCPU handle.
702 * @param GCPtrPage Page to invalidate.
703 *
704 * @remark ASSUMES the page table entry or page directory is valid. Fairly
705 * safe, but there could be edge cases!
706 *
707 * @todo Flush page or page directory only if necessary!
708 */
709VMMDECL(int) PGMInvalidatePage(PVMCPU pVCpu, RTGCPTR GCPtrPage)
710{
711 PVM pVM = pVCpu->CTX_SUFF(pVM);
712 int rc;
713 Log3(("PGMInvalidatePage: GCPtrPage=%RGv\n", GCPtrPage));
714
715#ifndef IN_RING3
716 /*
717 * Notify the recompiler so it can record this instruction.
718 */
719 REMNotifyInvalidatePage(pVM, GCPtrPage);
720#endif /* !IN_RING3 */
721
722
723#ifdef IN_RC
724 /*
725 * Check for conflicts and pending CR3 monitoring updates.
726 */
727 if (pgmMapAreMappingsFloating(&pVM->pgm.s))
728 {
729 if ( pgmGetMapping(pVM, GCPtrPage)
730 && PGMGstGetPage(pVCpu, GCPtrPage, NULL, NULL) != VERR_PAGE_TABLE_NOT_PRESENT)
731 {
732 LogFlow(("PGMGCInvalidatePage: Conflict!\n"));
733 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
734 STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatRCInvlPgConflict);
735 return VINF_PGM_SYNC_CR3;
736 }
737
738 if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
739 {
740 LogFlow(("PGMGCInvalidatePage: PGM_SYNC_MONITOR_CR3 -> reinterpret instruction in R3\n"));
741 STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatRCInvlPgSyncMonCR3);
742 return VINF_EM_RAW_EMULATE_INSTR;
743 }
744 }
745#endif /* IN_RC */
746
747 /*
748 * Call paging mode specific worker.
749 */
750 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePage), a);
751 pgmLock(pVM);
752 rc = PGM_BTH_PFN(InvalidatePage, pVCpu)(pVCpu, GCPtrPage);
753 pgmUnlock(pVM);
754 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePage), a);
755
756 /* Invalidate the TLB entry; might already be done by InvalidatePage (@todo) */
757 PGM_INVL_PG(pVCpu, GCPtrPage);
758
759#ifdef IN_RING3
760 /*
761 * Check if we have a pending update of the CR3 monitoring.
762 */
763 if ( RT_SUCCESS(rc)
764 && (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3))
765 {
766 pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
767 Assert(!pVM->pgm.s.fMappingsFixed); Assert(!pVM->pgm.s.fMappingsDisabled);
768 }
769
770 /*
771 * Inform CSAM about the flush
772 *
773 * Note: This is to check if monitored pages have been changed; when we implement
774 * callbacks for virtual handlers, this is no longer required.
775 */
776 CSAMR3FlushPage(pVM, GCPtrPage);
777#endif /* IN_RING3 */
778
779 /* Ignore all irrelevant error codes. */
780 if ( rc == VERR_PAGE_NOT_PRESENT
781 || rc == VERR_PAGE_TABLE_NOT_PRESENT
782 || rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT
783 || rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT)
784 rc = VINF_SUCCESS;
785
786 return rc;
787}
788
789
790/**
791 * Executes an instruction using the interpreter.
792 *
793 * @returns VBox status code (appropriate for trap handling and GC return).
794 * @param pVM VM handle.
795 * @param pVCpu VMCPU handle.
796 * @param pRegFrame Register frame.
797 * @param pvFault Fault address.
798 */
799VMMDECL(int) PGMInterpretInstruction(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
800{
801 uint32_t cb;
802 int rc = EMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault, &cb);
803 if (rc == VERR_EM_INTERPRETER)
804 rc = VINF_EM_RAW_EMULATE_INSTR;
805 if (rc != VINF_SUCCESS)
806 Log(("PGMInterpretInstruction: returns %Rrc (pvFault=%RGv)\n", rc, pvFault));
807 return rc;
808}
809
810
811/**
812 * Gets effective page information (from the VMM page directory).
813 *
814 * @returns VBox status.
815 * @param pVCpu VMCPU handle.
816 * @param GCPtr Guest Context virtual address of the page.
817 * @param pfFlags Where to store the flags. These are X86_PTE_*.
818 * @param pHCPhys Where to store the HC physical address of the page.
819 * This is page aligned.
820 * @remark You should use PGMMapGetPage() for pages in a mapping.
821 */
822VMMDECL(int) PGMShwGetPage(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys)
823{
824 pgmLock(pVCpu->CTX_SUFF(pVM));
825 int rc = PGM_SHW_PFN(GetPage, pVCpu)(pVCpu, GCPtr, pfFlags, pHCPhys);
826 pgmUnlock(pVCpu->CTX_SUFF(pVM));
827 return rc;
828}
829
830
831/**
832 * Modify page flags for a range of pages in the shadow context.
833 *
834 * The existing flags are ANDed with the fMask and ORed with the fFlags.
835 *
836 * @returns VBox status code.
837 * @param pVCpu VMCPU handle.
838 * @param GCPtr Virtual address of the first page in the range.
839 * @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
840 * @param fMask The AND mask - page flags X86_PTE_*.
841 * Be very CAREFUL when ~'ing constants which could be 32-bit!
842 * @param fOpFlags A combination of the PGM_MK_PK_XXX flags.
843 * @remark You must use PGMMapModifyPage() for pages in a mapping.
844 */
845DECLINLINE(int) pdmShwModifyPage(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags)
846{
847 AssertMsg(!(fFlags & X86_PTE_PAE_PG_MASK), ("fFlags=%#llx\n", fFlags));
848 Assert(!(fOpFlags & ~(PGM_MK_PG_IS_MMIO2 | PGM_MK_PG_IS_WRITE_FAULT)));
849
850 GCPtr &= PAGE_BASE_GC_MASK; /** @todo this ain't necessary, right... */
851
852 PVM pVM = pVCpu->CTX_SUFF(pVM);
853 pgmLock(pVM);
854 int rc = PGM_SHW_PFN(ModifyPage, pVCpu)(pVCpu, GCPtr, PAGE_SIZE, fFlags, fMask, fOpFlags);
855 pgmUnlock(pVM);
856 return rc;
857}
858
859
860/**
861 * Changing the page flags for a single page in the shadow page tables so as to
862 * make it read-only.
863 *
864 * @returns VBox status code.
865 * @param pVCpu VMCPU handle.
866 * @param GCPtr Virtual address of the first page in the range.
867 * @param fOpFlags A combination of the PGM_MK_PK_XXX flags.
868 */
869VMMDECL(int) PGMShwMakePageReadonly(PVMCPU pVCpu, RTGCPTR GCPtr, uint32_t fOpFlags)
870{
871 return pdmShwModifyPage(pVCpu, GCPtr, 0, ~(uint64_t)X86_PTE_RW, fOpFlags);
872}
873
874
875/**
876 * Changing the page flags for a single page in the shadow page tables so as to
877 * make it writable.
878 *
879 * The call must know with 101% certainty that the guest page tables maps this
880 * as writable too. This function will deal shared, zero and write monitored
881 * pages.
882 *
883 * @returns VBox status code.
884 * @param pVCpu VMCPU handle.
885 * @param GCPtr Virtual address of the first page in the range.
886 * @param fMmio2 Set if it is an MMIO2 page.
887 * @param fOpFlags A combination of the PGM_MK_PK_XXX flags.
888 */
889VMMDECL(int) PGMShwMakePageWritable(PVMCPU pVCpu, RTGCPTR GCPtr, uint32_t fOpFlags)
890{
891 return pdmShwModifyPage(pVCpu, GCPtr, X86_PTE_RW, ~(uint64_t)0, fOpFlags);
892}
893
894
895/**
896 * Changing the page flags for a single page in the shadow page tables so as to
897 * make it not present.
898 *
899 * @returns VBox status code.
900 * @param pVCpu VMCPU handle.
901 * @param GCPtr Virtual address of the first page in the range.
902 * @param fOpFlags A combination of the PGM_MK_PG_XXX flags.
903 */
904VMMDECL(int) PGMShwMakePageNotPresent(PVMCPU pVCpu, RTGCPTR GCPtr, uint32_t fOpFlags)
905{
906 return pdmShwModifyPage(pVCpu, GCPtr, 0, 0, fOpFlags);
907}
908
909
910/**
911 * Gets the shadow page directory for the specified address, PAE.
912 *
913 * @returns Pointer to the shadow PD.
914 * @param pVCpu The VMCPU handle.
915 * @param GCPtr The address.
916 * @param uGstPdpe Guest PDPT entry.
917 * @param ppPD Receives address of page directory
918 */
919int pgmShwSyncPaePDPtr(PVMCPU pVCpu, RTGCPTR GCPtr, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD)
920{
921 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
922 PX86PDPT pPdpt = pgmShwGetPaePDPTPtr(pVCpu);
923 PX86PDPE pPdpe = &pPdpt->a[iPdPt];
924 PVM pVM = pVCpu->CTX_SUFF(pVM);
925 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
926 PPGMPOOLPAGE pShwPage;
927 int rc;
928
929 Assert(PGMIsLockOwner(pVM));
930
931 /* Allocate page directory if not present. */
932 if ( !pPdpe->n.u1Present
933 && !(pPdpe->u & X86_PDPE_PG_MASK))
934 {
935 RTGCPTR64 GCPdPt;
936 PGMPOOLKIND enmKind;
937
938 if (pVM->pgm.s.fNestedPaging || !CPUMIsGuestPagingEnabled(pVCpu))
939 {
940 /* AMD-V nested paging or real/protected mode without paging. */
941 GCPdPt = (RTGCPTR64)iPdPt << X86_PDPT_SHIFT;
942 enmKind = PGMPOOLKIND_PAE_PD_PHYS;
943 }
944 else
945 {
946 if (CPUMGetGuestCR4(pVCpu) & X86_CR4_PAE)
947 {
948 if (!(uGstPdpe & X86_PDPE_P))
949 {
950 /* PD not present; guest must reload CR3 to change it.
951 * No need to monitor anything in this case.
952 */
953 Assert(!HWACCMIsEnabled(pVM));
954
955 GCPdPt = uGstPdpe & X86_PDPE_PG_MASK;
956 enmKind = PGMPOOLKIND_PAE_PD_PHYS;
957 uGstPdpe |= X86_PDPE_P;
958 }
959 else
960 {
961 GCPdPt = uGstPdpe & X86_PDPE_PG_MASK;
962 enmKind = PGMPOOLKIND_PAE_PD_FOR_PAE_PD;
963 }
964 }
965 else
966 {
967 GCPdPt = CPUMGetGuestCR3(pVCpu);
968 enmKind = (PGMPOOLKIND)(PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD + iPdPt);
969 }
970 }
971
972 /* Create a reference back to the PDPT by using the index in its shadow page. */
973 rc = pgmPoolAlloc(pVM, GCPdPt, enmKind, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPdPt, &pShwPage);
974 AssertRCReturn(rc, rc);
975
976 /* The PD was cached or created; hook it up now. */
977 pPdpe->u |= pShwPage->Core.Key
978 | (uGstPdpe & ~(X86_PDPE_PG_MASK | X86_PDPE_AVL_MASK | X86_PDPE_PCD | X86_PDPE_PWT));
979
980# if defined(IN_RC)
981 /*
982 * In 32 bits PAE mode we *must* invalidate the TLB when changing a
983 * PDPT entry; the CPU fetches them only during cr3 load, so any
984 * non-present PDPT will continue to cause page faults.
985 */
986 ASMReloadCR3();
987# endif
988 PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdpe);
989 }
990 else
991 {
992 pShwPage = pgmPoolGetPage(pPool, pPdpe->u & X86_PDPE_PG_MASK);
993 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
994 Assert((pPdpe->u & X86_PDPE_PG_MASK) == pShwPage->Core.Key);
995
996 pgmPoolCacheUsed(pPool, pShwPage);
997 }
998 *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
999 return VINF_SUCCESS;
1000}
1001
1002
1003/**
1004 * Gets the pointer to the shadow page directory entry for an address, PAE.
1005 *
1006 * @returns Pointer to the PDE.
1007 * @param pVCpu The current CPU.
1008 * @param GCPtr The address.
1009 * @param ppShwPde Receives the address of the pgm pool page for the shadow page directory
1010 */
1011DECLINLINE(int) pgmShwGetPaePoolPagePD(PVMCPU pVCpu, RTGCPTR GCPtr, PPGMPOOLPAGE *ppShwPde)
1012{
1013 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
1014 PX86PDPT pPdpt = pgmShwGetPaePDPTPtr(pVCpu);
1015 PVM pVM = pVCpu->CTX_SUFF(pVM);
1016
1017 Assert(PGMIsLockOwner(pVM));
1018
1019 AssertReturn(pPdpt, VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT); /* can't happen */
1020 if (!pPdpt->a[iPdPt].n.u1Present)
1021 {
1022 LogFlow(("pgmShwGetPaePoolPagePD: PD %d not present (%RX64)\n", iPdPt, pPdpt->a[iPdPt].u));
1023 return VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT;
1024 }
1025 AssertMsg(pPdpt->a[iPdPt].u & X86_PDPE_PG_MASK, ("GCPtr=%RGv\n", GCPtr));
1026
1027 /* Fetch the pgm pool shadow descriptor. */
1028 PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pVM->pgm.s.CTX_SUFF(pPool), pPdpt->a[iPdPt].u & X86_PDPE_PG_MASK);
1029 AssertReturn(pShwPde, VERR_INTERNAL_ERROR);
1030
1031 *ppShwPde = pShwPde;
1032 return VINF_SUCCESS;
1033}
1034
1035#ifndef IN_RC
1036
1037/**
1038 * Syncs the SHADOW page directory pointer for the specified address.
1039 *
1040 * Allocates backing pages in case the PDPT or PML4 entry is missing.
1041 *
1042 * The caller is responsible for making sure the guest has a valid PD before
1043 * calling this function.
1044 *
1045 * @returns VBox status.
1046 * @param pVCpu VMCPU handle.
1047 * @param GCPtr The address.
1048 * @param uGstPml4e Guest PML4 entry
1049 * @param uGstPdpe Guest PDPT entry
1050 * @param ppPD Receives address of page directory
1051 */
1052static int pgmShwSyncLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, X86PGPAEUINT uGstPml4e, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD)
1053{
1054 PPGMCPU pPGM = &pVCpu->pgm.s;
1055 PVM pVM = pVCpu->CTX_SUFF(pVM);
1056 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1057 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
1058 PX86PML4E pPml4e = pgmShwGetLongModePML4EPtr(pVCpu, iPml4);
1059 bool fNestedPagingOrNoGstPaging = pVM->pgm.s.fNestedPaging || !CPUMIsGuestPagingEnabled(pVCpu);
1060 PPGMPOOLPAGE pShwPage;
1061 int rc;
1062
1063 Assert(PGMIsLockOwner(pVM));
1064
1065 /* Allocate page directory pointer table if not present. */
1066 if ( !pPml4e->n.u1Present
1067 && !(pPml4e->u & X86_PML4E_PG_MASK))
1068 {
1069 RTGCPTR64 GCPml4;
1070 PGMPOOLKIND enmKind;
1071
1072 Assert(pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
1073
1074 if (fNestedPagingOrNoGstPaging)
1075 {
1076 /* AMD-V nested paging or real/protected mode without paging */
1077 GCPml4 = (RTGCPTR64)iPml4 << X86_PML4_SHIFT;
1078 enmKind = PGMPOOLKIND_64BIT_PDPT_FOR_PHYS;
1079 }
1080 else
1081 {
1082 GCPml4 = uGstPml4e & X86_PML4E_PG_MASK;
1083 enmKind = PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT;
1084 }
1085
1086 /* Create a reference back to the PDPT by using the index in its shadow page. */
1087 rc = pgmPoolAlloc(pVM, GCPml4, enmKind, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPml4, &pShwPage);
1088 AssertRCReturn(rc, rc);
1089 }
1090 else
1091 {
1092 pShwPage = pgmPoolGetPage(pPool, pPml4e->u & X86_PML4E_PG_MASK);
1093 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1094
1095 pgmPoolCacheUsed(pPool, pShwPage);
1096 }
1097 /* The PDPT was cached or created; hook it up now. */
1098 pPml4e->u |= pShwPage->Core.Key
1099 | (uGstPml4e & ~(X86_PML4E_PG_MASK | X86_PML4E_AVL_MASK | X86_PML4E_PCD | X86_PML4E_PWT));
1100
1101 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1102 PX86PDPT pPdpt = (PX86PDPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1103 PX86PDPE pPdpe = &pPdpt->a[iPdPt];
1104
1105 /* Allocate page directory if not present. */
1106 if ( !pPdpe->n.u1Present
1107 && !(pPdpe->u & X86_PDPE_PG_MASK))
1108 {
1109 RTGCPTR64 GCPdPt;
1110 PGMPOOLKIND enmKind;
1111
1112 if (fNestedPagingOrNoGstPaging)
1113 {
1114 /* AMD-V nested paging or real/protected mode without paging */
1115 GCPdPt = (RTGCPTR64)iPdPt << X86_PDPT_SHIFT;
1116 enmKind = PGMPOOLKIND_64BIT_PD_FOR_PHYS;
1117 }
1118 else
1119 {
1120 GCPdPt = uGstPdpe & X86_PDPE_PG_MASK;
1121 enmKind = PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD;
1122 }
1123
1124 /* Create a reference back to the PDPT by using the index in its shadow page. */
1125 rc = pgmPoolAlloc(pVM, GCPdPt, enmKind, pShwPage->idx, iPdPt, &pShwPage);
1126 AssertRCReturn(rc, rc);
1127 }
1128 else
1129 {
1130 pShwPage = pgmPoolGetPage(pPool, pPdpe->u & X86_PDPE_PG_MASK);
1131 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1132
1133 pgmPoolCacheUsed(pPool, pShwPage);
1134 }
1135 /* The PD was cached or created; hook it up now. */
1136 pPdpe->u |= pShwPage->Core.Key
1137 | (uGstPdpe & ~(X86_PDPE_PG_MASK | X86_PDPE_AVL_MASK | X86_PDPE_PCD | X86_PDPE_PWT));
1138
1139 *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1140 return VINF_SUCCESS;
1141}
1142
1143
1144/**
1145 * Gets the SHADOW page directory pointer for the specified address (long mode).
1146 *
1147 * @returns VBox status.
1148 * @param pVCpu VMCPU handle.
1149 * @param GCPtr The address.
1150 * @param ppPdpt Receives address of pdpt
1151 * @param ppPD Receives address of page directory
1152 */
1153DECLINLINE(int) pgmShwGetLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPT *ppPdpt, PX86PDPAE *ppPD)
1154{
1155 PPGMCPU pPGM = &pVCpu->pgm.s;
1156 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
1157 PCX86PML4E pPml4e = pgmShwGetLongModePML4EPtr(pVCpu, iPml4);
1158
1159 Assert(PGMIsLockOwner(PGMCPU2VM(pPGM)));
1160
1161 AssertReturn(pPml4e, VERR_INTERNAL_ERROR);
1162 if (ppPml4e)
1163 *ppPml4e = (PX86PML4E)pPml4e;
1164
1165 Log4(("pgmShwGetLongModePDPtr %RGv (%RHv) %RX64\n", GCPtr, pPml4e, pPml4e->u));
1166
1167 if (!pPml4e->n.u1Present)
1168 return VERR_PAGE_MAP_LEVEL4_NOT_PRESENT;
1169
1170 PVM pVM = pVCpu->CTX_SUFF(pVM);
1171 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1172 PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPml4e->u & X86_PML4E_PG_MASK);
1173 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1174
1175 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1176 PCX86PDPT pPdpt = *ppPdpt = (PX86PDPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1177 if (!pPdpt->a[iPdPt].n.u1Present)
1178 return VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT;
1179
1180 pShwPage = pgmPoolGetPage(pPool, pPdpt->a[iPdPt].u & X86_PDPE_PG_MASK);
1181 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1182
1183 *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1184 return VINF_SUCCESS;
1185}
1186
1187
1188/**
1189 * Syncs the SHADOW EPT page directory pointer for the specified address. Allocates
1190 * backing pages in case the PDPT or PML4 entry is missing.
1191 *
1192 * @returns VBox status.
1193 * @param pVCpu VMCPU handle.
1194 * @param GCPtr The address.
1195 * @param ppPdpt Receives address of pdpt
1196 * @param ppPD Receives address of page directory
1197 */
1198static int pgmShwGetEPTPDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PEPTPDPT *ppPdpt, PEPTPD *ppPD)
1199{
1200 PVM pVM = pVCpu->CTX_SUFF(pVM);
1201 const unsigned iPml4 = (GCPtr >> EPT_PML4_SHIFT) & EPT_PML4_MASK;
1202 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1203 PEPTPML4 pPml4;
1204 PEPTPML4E pPml4e;
1205 PPGMPOOLPAGE pShwPage;
1206 int rc;
1207
1208 Assert(pVM->pgm.s.fNestedPaging);
1209 Assert(PGMIsLockOwner(pVM));
1210
1211 pPml4 = (PEPTPML4)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
1212 Assert(pPml4);
1213
1214 /* Allocate page directory pointer table if not present. */
1215 pPml4e = &pPml4->a[iPml4];
1216 if ( !pPml4e->n.u1Present
1217 && !(pPml4e->u & EPT_PML4E_PG_MASK))
1218 {
1219 Assert(!(pPml4e->u & EPT_PML4E_PG_MASK));
1220 RTGCPTR64 GCPml4 = (RTGCPTR64)iPml4 << EPT_PML4_SHIFT;
1221
1222 rc = pgmPoolAlloc(pVM, GCPml4, PGMPOOLKIND_EPT_PDPT_FOR_PHYS, PGMPOOL_IDX_NESTED_ROOT, iPml4, &pShwPage);
1223 AssertRCReturn(rc, rc);
1224 }
1225 else
1226 {
1227 pShwPage = pgmPoolGetPage(pPool, pPml4e->u & EPT_PML4E_PG_MASK);
1228 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1229
1230 pgmPoolCacheUsed(pPool, pShwPage);
1231 }
1232 /* The PDPT was cached or created; hook it up now and fill with the default value. */
1233 pPml4e->u = pShwPage->Core.Key;
1234 pPml4e->n.u1Present = 1;
1235 pPml4e->n.u1Write = 1;
1236 pPml4e->n.u1Execute = 1;
1237
1238 const unsigned iPdPt = (GCPtr >> EPT_PDPT_SHIFT) & EPT_PDPT_MASK;
1239 PEPTPDPT pPdpt = (PEPTPDPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1240 PEPTPDPTE pPdpe = &pPdpt->a[iPdPt];
1241
1242 if (ppPdpt)
1243 *ppPdpt = pPdpt;
1244
1245 /* Allocate page directory if not present. */
1246 if ( !pPdpe->n.u1Present
1247 && !(pPdpe->u & EPT_PDPTE_PG_MASK))
1248 {
1249 RTGCPTR64 GCPdPt = (RTGCPTR64)iPdPt << EPT_PDPT_SHIFT;
1250
1251 rc = pgmPoolAlloc(pVM, GCPdPt, PGMPOOLKIND_64BIT_PD_FOR_PHYS, pShwPage->idx, iPdPt, &pShwPage);
1252 AssertRCReturn(rc, rc);
1253 }
1254 else
1255 {
1256 pShwPage = pgmPoolGetPage(pPool, pPdpe->u & EPT_PDPTE_PG_MASK);
1257 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1258
1259 pgmPoolCacheUsed(pPool, pShwPage);
1260 }
1261 /* The PD was cached or created; hook it up now and fill with the default value. */
1262 pPdpe->u = pShwPage->Core.Key;
1263 pPdpe->n.u1Present = 1;
1264 pPdpe->n.u1Write = 1;
1265 pPdpe->n.u1Execute = 1;
1266
1267 *ppPD = (PEPTPD)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1268 return VINF_SUCCESS;
1269}
1270
1271#endif /* IN_RC */
1272
1273#ifdef IN_RING0
1274/**
1275 * Synchronizes a range of nested page table entries.
1276 *
1277 * The caller must own the PGM lock.
1278 *
1279 * @param pVCpu The current CPU.
1280 * @param GCPhys Where to start.
1281 * @param cPages How many pages which entries should be synced.
1282 * @param enmShwPagingMode The shadow paging mode (PGMMODE_EPT for VT-x,
1283 * host paging mode for AMD-V).
1284 */
1285int pgmShwSyncNestedPageLocked(PVMCPU pVCpu, RTGCPHYS GCPhysFault, uint32_t cPages, PGMMODE enmShwPagingMode)
1286{
1287 Assert(PGMIsLockOwner(pVCpu->CTX_SUFF(pVM)));
1288
1289 int rc;
1290 switch (enmShwPagingMode)
1291 {
1292 case PGMMODE_32_BIT:
1293 {
1294 X86PDE PdeDummy = { X86_PDE_P | X86_PDE_US | X86_PDE_RW | X86_PDE_A };
1295 rc = PGM_BTH_NAME_32BIT_PROT(SyncPage)(pVCpu, PdeDummy, GCPhysFault, cPages, ~0U /*uErr*/);
1296 break;
1297 }
1298
1299 case PGMMODE_PAE:
1300 case PGMMODE_PAE_NX:
1301 {
1302 X86PDEPAE PdeDummy = { X86_PDE_P | X86_PDE_US | X86_PDE_RW | X86_PDE_A };
1303 rc = PGM_BTH_NAME_PAE_PROT(SyncPage)(pVCpu, PdeDummy, GCPhysFault, cPages, ~0U /*uErr*/);
1304 break;
1305 }
1306
1307 case PGMMODE_AMD64:
1308 case PGMMODE_AMD64_NX:
1309 {
1310 X86PDEPAE PdeDummy = { X86_PDE_P | X86_PDE_US | X86_PDE_RW | X86_PDE_A };
1311 rc = PGM_BTH_NAME_AMD64_PROT(SyncPage)(pVCpu, PdeDummy, GCPhysFault, cPages, ~0U /*uErr*/);
1312 break;
1313 }
1314
1315 case PGMMODE_EPT:
1316 {
1317 X86PDEPAE PdeDummy = { X86_PDE_P | X86_PDE_US | X86_PDE_RW | X86_PDE_A };
1318 rc = PGM_BTH_NAME_EPT_PROT(SyncPage)(pVCpu, PdeDummy, GCPhysFault, cPages, ~0U /*uErr*/);
1319 break;
1320 }
1321
1322 default:
1323 AssertMsgFailedReturn(("%d\n", enmShwPagingMode), VERR_INTERNAL_ERROR_5);
1324 }
1325 return rc;
1326}
1327#endif /* IN_RING0 */
1328
1329
1330/**
1331 * Gets effective Guest OS page information.
1332 *
1333 * When GCPtr is in a big page, the function will return as if it was a normal
1334 * 4KB page. If the need for distinguishing between big and normal page becomes
1335 * necessary at a later point, a PGMGstGetPage() will be created for that
1336 * purpose.
1337 *
1338 * @returns VBox status.
1339 * @param pVCpu VMCPU handle.
1340 * @param GCPtr Guest Context virtual address of the page.
1341 * @param pfFlags Where to store the flags. These are X86_PTE_*, even for big pages.
1342 * @param pGCPhys Where to store the GC physical address of the page.
1343 * This is page aligned. The fact that the
1344 */
1345VMMDECL(int) PGMGstGetPage(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys)
1346{
1347 return PGM_GST_PFN(GetPage, pVCpu)(pVCpu, GCPtr, pfFlags, pGCPhys);
1348}
1349
1350
1351/**
1352 * Checks if the page is present.
1353 *
1354 * @returns true if the page is present.
1355 * @returns false if the page is not present.
1356 * @param pVCpu VMCPU handle.
1357 * @param GCPtr Address within the page.
1358 */
1359VMMDECL(bool) PGMGstIsPagePresent(PVMCPU pVCpu, RTGCPTR GCPtr)
1360{
1361 int rc = PGMGstGetPage(pVCpu, GCPtr, NULL, NULL);
1362 return RT_SUCCESS(rc);
1363}
1364
1365
1366/**
1367 * Sets (replaces) the page flags for a range of pages in the guest's tables.
1368 *
1369 * @returns VBox status.
1370 * @param pVCpu VMCPU handle.
1371 * @param GCPtr The address of the first page.
1372 * @param cb The size of the range in bytes.
1373 * @param fFlags Page flags X86_PTE_*, excluding the page mask of course.
1374 */
1375VMMDECL(int) PGMGstSetPage(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags)
1376{
1377 return PGMGstModifyPage(pVCpu, GCPtr, cb, fFlags, 0);
1378}
1379
1380
1381/**
1382 * Modify page flags for a range of pages in the guest's tables
1383 *
1384 * The existing flags are ANDed with the fMask and ORed with the fFlags.
1385 *
1386 * @returns VBox status code.
1387 * @param pVCpu VMCPU handle.
1388 * @param GCPtr Virtual address of the first page in the range.
1389 * @param cb Size (in bytes) of the range to apply the modification to.
1390 * @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
1391 * @param fMask The AND mask - page flags X86_PTE_*, excluding the page mask of course.
1392 * Be very CAREFUL when ~'ing constants which could be 32-bit!
1393 */
1394VMMDECL(int) PGMGstModifyPage(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
1395{
1396 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,GstModifyPage), a);
1397
1398 /*
1399 * Validate input.
1400 */
1401 AssertMsg(!(fFlags & X86_PTE_PAE_PG_MASK), ("fFlags=%#llx\n", fFlags));
1402 Assert(cb);
1403
1404 LogFlow(("PGMGstModifyPage %RGv %d bytes fFlags=%08llx fMask=%08llx\n", GCPtr, cb, fFlags, fMask));
1405
1406 /*
1407 * Adjust input.
1408 */
1409 cb += GCPtr & PAGE_OFFSET_MASK;
1410 cb = RT_ALIGN_Z(cb, PAGE_SIZE);
1411 GCPtr = (GCPtr & PAGE_BASE_GC_MASK);
1412
1413 /*
1414 * Call worker.
1415 */
1416 int rc = PGM_GST_PFN(ModifyPage, pVCpu)(pVCpu, GCPtr, cb, fFlags, fMask);
1417
1418 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,GstModifyPage), a);
1419 return rc;
1420}
1421
1422
1423#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
1424
1425/**
1426 * Performs the lazy mapping of the 32-bit guest PD.
1427 *
1428 * @returns VBox status code.
1429 * @param pVCpu The current CPU.
1430 * @param ppPd Where to return the pointer to the mapping. This is
1431 * always set.
1432 */
1433int pgmGstLazyMap32BitPD(PVMCPU pVCpu, PX86PD *ppPd)
1434{
1435 PVM pVM = pVCpu->CTX_SUFF(pVM);
1436 pgmLock(pVM);
1437
1438 Assert(!pVCpu->pgm.s.CTX_SUFF(pGst32BitPd));
1439
1440 RTGCPHYS GCPhysCR3 = pVCpu->pgm.s.GCPhysCR3 & X86_CR3_PAGE_MASK;
1441 PPGMPAGE pPage;
1442 int rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhysCR3, &pPage);
1443 if (RT_SUCCESS(rc))
1444 {
1445 RTHCPTR HCPtrGuestCR3;
1446 rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhysCR3, (void **)&HCPtrGuestCR3);
1447 if (RT_SUCCESS(rc))
1448 {
1449 pVCpu->pgm.s.pGst32BitPdR3 = (R3PTRTYPE(PX86PD))HCPtrGuestCR3;
1450# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1451 pVCpu->pgm.s.pGst32BitPdR0 = (R0PTRTYPE(PX86PD))HCPtrGuestCR3;
1452# endif
1453 *ppPd = (PX86PD)HCPtrGuestCR3;
1454
1455 pgmUnlock(pVM);
1456 return VINF_SUCCESS;
1457 }
1458
1459 AssertRC(rc);
1460 }
1461 pgmUnlock(pVM);
1462
1463 *ppPd = NULL;
1464 return rc;
1465}
1466
1467
1468/**
1469 * Performs the lazy mapping of the PAE guest PDPT.
1470 *
1471 * @returns VBox status code.
1472 * @param pVCpu The current CPU.
1473 * @param ppPdpt Where to return the pointer to the mapping. This is
1474 * always set.
1475 */
1476int pgmGstLazyMapPaePDPT(PVMCPU pVCpu, PX86PDPT *ppPdpt)
1477{
1478 Assert(!pVCpu->pgm.s.CTX_SUFF(pGstPaePdpt));
1479 PVM pVM = pVCpu->CTX_SUFF(pVM);
1480 pgmLock(pVM);
1481
1482 RTGCPHYS GCPhysCR3 = pVCpu->pgm.s.GCPhysCR3 & X86_CR3_PAE_PAGE_MASK;
1483 PPGMPAGE pPage;
1484 int rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhysCR3, &pPage);
1485 if (RT_SUCCESS(rc))
1486 {
1487 RTHCPTR HCPtrGuestCR3;
1488 rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhysCR3, (void **)&HCPtrGuestCR3);
1489 if (RT_SUCCESS(rc))
1490 {
1491 pVCpu->pgm.s.pGstPaePdptR3 = (R3PTRTYPE(PX86PDPT))HCPtrGuestCR3;
1492# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1493 pVCpu->pgm.s.pGstPaePdptR0 = (R0PTRTYPE(PX86PDPT))HCPtrGuestCR3;
1494# endif
1495 *ppPdpt = (PX86PDPT)HCPtrGuestCR3;
1496
1497 pgmUnlock(pVM);
1498 return VINF_SUCCESS;
1499 }
1500
1501 AssertRC(rc);
1502 }
1503
1504 pgmUnlock(pVM);
1505 *ppPdpt = NULL;
1506 return rc;
1507}
1508
1509
1510/**
1511 * Performs the lazy mapping / updating of a PAE guest PD.
1512 *
1513 * @returns Pointer to the mapping.
1514 * @returns VBox status code.
1515 * @param pVCpu The current CPU.
1516 * @param iPdpt Which PD entry to map (0..3).
1517 * @param ppPd Where to return the pointer to the mapping. This is
1518 * always set.
1519 */
1520int pgmGstLazyMapPaePD(PVMCPU pVCpu, uint32_t iPdpt, PX86PDPAE *ppPd)
1521{
1522 PVM pVM = pVCpu->CTX_SUFF(pVM);
1523 pgmLock(pVM);
1524
1525 PX86PDPT pGuestPDPT = pVCpu->pgm.s.CTX_SUFF(pGstPaePdpt);
1526 Assert(pGuestPDPT);
1527 Assert(pGuestPDPT->a[iPdpt].n.u1Present);
1528 RTGCPHYS GCPhys = pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK_FULL;
1529 bool const fChanged = pVCpu->pgm.s.aGCPhysGstPaePDs[iPdpt] != GCPhys;
1530
1531 PPGMPAGE pPage;
1532 int rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
1533 if (RT_SUCCESS(rc))
1534 {
1535 RTRCPTR RCPtr = NIL_RTRCPTR;
1536 RTHCPTR HCPtr = NIL_RTHCPTR;
1537#if !defined(IN_RC) && !defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1538 rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, &HCPtr);
1539 AssertRC(rc);
1540#endif
1541 if (RT_SUCCESS(rc) && fChanged)
1542 {
1543 RCPtr = (RTRCPTR)(RTRCUINTPTR)(pVM->pgm.s.GCPtrCR3Mapping + (1 + iPdpt) * PAGE_SIZE);
1544 rc = PGMMap(pVM, (RTRCUINTPTR)RCPtr, PGM_PAGE_GET_HCPHYS(pPage), PAGE_SIZE, 0);
1545 }
1546 if (RT_SUCCESS(rc))
1547 {
1548 pVCpu->pgm.s.apGstPaePDsR3[iPdpt] = (R3PTRTYPE(PX86PDPAE))HCPtr;
1549# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1550 pVCpu->pgm.s.apGstPaePDsR0[iPdpt] = (R0PTRTYPE(PX86PDPAE))HCPtr;
1551# endif
1552 if (fChanged)
1553 {
1554 pVCpu->pgm.s.aGCPhysGstPaePDs[iPdpt] = GCPhys;
1555 pVCpu->pgm.s.apGstPaePDsRC[iPdpt] = (RCPTRTYPE(PX86PDPAE))RCPtr;
1556 }
1557
1558 *ppPd = pVCpu->pgm.s.CTX_SUFF(apGstPaePDs)[iPdpt];
1559 pgmUnlock(pVM);
1560 return VINF_SUCCESS;
1561 }
1562 }
1563
1564 /* Invalid page or some failure, invalidate the entry. */
1565 pVCpu->pgm.s.aGCPhysGstPaePDs[iPdpt] = NIL_RTGCPHYS;
1566 pVCpu->pgm.s.apGstPaePDsR3[iPdpt] = 0;
1567# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1568 pVCpu->pgm.s.apGstPaePDsR0[iPdpt] = 0;
1569# endif
1570 pVCpu->pgm.s.apGstPaePDsRC[iPdpt] = 0;
1571
1572 pgmUnlock(pVM);
1573 return rc;
1574}
1575
1576#endif /* !VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
1577#if !defined(IN_RC) && !defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1578/**
1579 * Performs the lazy mapping of the 32-bit guest PD.
1580 *
1581 * @returns VBox status code.
1582 * @param pVCpu The current CPU.
1583 * @param ppPml4 Where to return the pointer to the mapping. This will
1584 * always be set.
1585 */
1586int pgmGstLazyMapPml4(PVMCPU pVCpu, PX86PML4 *ppPml4)
1587{
1588 Assert(!pVCpu->pgm.s.CTX_SUFF(pGstAmd64Pml4));
1589 PVM pVM = pVCpu->CTX_SUFF(pVM);
1590 pgmLock(pVM);
1591
1592 RTGCPHYS GCPhysCR3 = pVCpu->pgm.s.GCPhysCR3 & X86_CR3_AMD64_PAGE_MASK;
1593 PPGMPAGE pPage;
1594 int rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhysCR3, &pPage);
1595 if (RT_SUCCESS(rc))
1596 {
1597 RTHCPTR HCPtrGuestCR3;
1598 rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhysCR3, (void **)&HCPtrGuestCR3);
1599 if (RT_SUCCESS(rc))
1600 {
1601 pVCpu->pgm.s.pGstAmd64Pml4R3 = (R3PTRTYPE(PX86PML4))HCPtrGuestCR3;
1602# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1603 pVCpu->pgm.s.pGstAmd64Pml4R0 = (R0PTRTYPE(PX86PML4))HCPtrGuestCR3;
1604# endif
1605 *ppPml4 = (PX86PML4)HCPtrGuestCR3;
1606
1607 pgmUnlock(pVM);
1608 return VINF_SUCCESS;
1609 }
1610 }
1611
1612 pgmUnlock(pVM);
1613 *ppPml4 = NULL;
1614 return rc;
1615}
1616#endif
1617
1618/**
1619 * Gets the specified page directory pointer table entry.
1620 *
1621 * @returns PDP entry
1622 * @param pVCpu VMCPU handle.
1623 * @param iPdpt PDPT index
1624 */
1625VMMDECL(X86PDPE) PGMGstGetPaePDPtr(PVMCPU pVCpu, unsigned iPdpt)
1626{
1627 Assert(iPdpt <= 3);
1628 return pgmGstGetPaePDPTPtr(pVCpu)->a[iPdpt & 3];
1629}
1630
1631
1632/**
1633 * Gets the current CR3 register value for the shadow memory context.
1634 * @returns CR3 value.
1635 * @param pVCpu VMCPU handle.
1636 */
1637VMMDECL(RTHCPHYS) PGMGetHyperCR3(PVMCPU pVCpu)
1638{
1639 PPGMPOOLPAGE pPoolPage = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
1640 AssertPtrReturn(pPoolPage, 0);
1641 return pPoolPage->Core.Key;
1642}
1643
1644
1645/**
1646 * Gets the current CR3 register value for the nested memory context.
1647 * @returns CR3 value.
1648 * @param pVCpu VMCPU handle.
1649 */
1650VMMDECL(RTHCPHYS) PGMGetNestedCR3(PVMCPU pVCpu, PGMMODE enmShadowMode)
1651{
1652 Assert(pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
1653 return pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->Core.Key;
1654}
1655
1656
1657/**
1658 * Gets the current CR3 register value for the HC intermediate memory context.
1659 * @returns CR3 value.
1660 * @param pVM The VM handle.
1661 */
1662VMMDECL(RTHCPHYS) PGMGetInterHCCR3(PVM pVM)
1663{
1664 switch (pVM->pgm.s.enmHostMode)
1665 {
1666 case SUPPAGINGMODE_32_BIT:
1667 case SUPPAGINGMODE_32_BIT_GLOBAL:
1668 return pVM->pgm.s.HCPhysInterPD;
1669
1670 case SUPPAGINGMODE_PAE:
1671 case SUPPAGINGMODE_PAE_GLOBAL:
1672 case SUPPAGINGMODE_PAE_NX:
1673 case SUPPAGINGMODE_PAE_GLOBAL_NX:
1674 return pVM->pgm.s.HCPhysInterPaePDPT;
1675
1676 case SUPPAGINGMODE_AMD64:
1677 case SUPPAGINGMODE_AMD64_GLOBAL:
1678 case SUPPAGINGMODE_AMD64_NX:
1679 case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1680 return pVM->pgm.s.HCPhysInterPaePDPT;
1681
1682 default:
1683 AssertMsgFailed(("enmHostMode=%d\n", pVM->pgm.s.enmHostMode));
1684 return ~0;
1685 }
1686}
1687
1688
1689/**
1690 * Gets the current CR3 register value for the RC intermediate memory context.
1691 * @returns CR3 value.
1692 * @param pVM The VM handle.
1693 * @param pVCpu VMCPU handle.
1694 */
1695VMMDECL(RTHCPHYS) PGMGetInterRCCR3(PVM pVM, PVMCPU pVCpu)
1696{
1697 switch (pVCpu->pgm.s.enmShadowMode)
1698 {
1699 case PGMMODE_32_BIT:
1700 return pVM->pgm.s.HCPhysInterPD;
1701
1702 case PGMMODE_PAE:
1703 case PGMMODE_PAE_NX:
1704 return pVM->pgm.s.HCPhysInterPaePDPT;
1705
1706 case PGMMODE_AMD64:
1707 case PGMMODE_AMD64_NX:
1708 return pVM->pgm.s.HCPhysInterPaePML4;
1709
1710 case PGMMODE_EPT:
1711 case PGMMODE_NESTED:
1712 return 0; /* not relevant */
1713
1714 default:
1715 AssertMsgFailed(("enmShadowMode=%d\n", pVCpu->pgm.s.enmShadowMode));
1716 return ~0;
1717 }
1718}
1719
1720
1721/**
1722 * Gets the CR3 register value for the 32-Bit intermediate memory context.
1723 * @returns CR3 value.
1724 * @param pVM The VM handle.
1725 */
1726VMMDECL(RTHCPHYS) PGMGetInter32BitCR3(PVM pVM)
1727{
1728 return pVM->pgm.s.HCPhysInterPD;
1729}
1730
1731
1732/**
1733 * Gets the CR3 register value for the PAE intermediate memory context.
1734 * @returns CR3 value.
1735 * @param pVM The VM handle.
1736 */
1737VMMDECL(RTHCPHYS) PGMGetInterPaeCR3(PVM pVM)
1738{
1739 return pVM->pgm.s.HCPhysInterPaePDPT;
1740}
1741
1742
1743/**
1744 * Gets the CR3 register value for the AMD64 intermediate memory context.
1745 * @returns CR3 value.
1746 * @param pVM The VM handle.
1747 */
1748VMMDECL(RTHCPHYS) PGMGetInterAmd64CR3(PVM pVM)
1749{
1750 return pVM->pgm.s.HCPhysInterPaePML4;
1751}
1752
1753
1754/**
1755 * Performs and schedules necessary updates following a CR3 load or reload.
1756 *
1757 * This will normally involve mapping the guest PD or nPDPT
1758 *
1759 * @returns VBox status code.
1760 * @retval VINF_PGM_SYNC_CR3 if monitoring requires a CR3 sync. This can
1761 * safely be ignored and overridden since the FF will be set too then.
1762 * @param pVCpu VMCPU handle.
1763 * @param cr3 The new cr3.
1764 * @param fGlobal Indicates whether this is a global flush or not.
1765 */
1766VMMDECL(int) PGMFlushTLB(PVMCPU pVCpu, uint64_t cr3, bool fGlobal)
1767{
1768 PVM pVM = pVCpu->CTX_SUFF(pVM);
1769
1770 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FlushTLB), a);
1771
1772 /*
1773 * Always flag the necessary updates; necessary for hardware acceleration
1774 */
1775 /** @todo optimize this, it shouldn't always be necessary. */
1776 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
1777 if (fGlobal)
1778 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
1779 LogFlow(("PGMFlushTLB: cr3=%RX64 OldCr3=%RX64 fGlobal=%d\n", cr3, pVCpu->pgm.s.GCPhysCR3, fGlobal));
1780
1781 /*
1782 * Remap the CR3 content and adjust the monitoring if CR3 was actually changed.
1783 */
1784 int rc = VINF_SUCCESS;
1785 RTGCPHYS GCPhysCR3;
1786 switch (pVCpu->pgm.s.enmGuestMode)
1787 {
1788 case PGMMODE_PAE:
1789 case PGMMODE_PAE_NX:
1790 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAE_PAGE_MASK);
1791 break;
1792 case PGMMODE_AMD64:
1793 case PGMMODE_AMD64_NX:
1794 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_AMD64_PAGE_MASK);
1795 break;
1796 default:
1797 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAGE_MASK);
1798 break;
1799 }
1800
1801 if (pVCpu->pgm.s.GCPhysCR3 != GCPhysCR3)
1802 {
1803 RTGCPHYS GCPhysOldCR3 = pVCpu->pgm.s.GCPhysCR3;
1804 pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3;
1805 rc = PGM_BTH_PFN(MapCR3, pVCpu)(pVCpu, GCPhysCR3);
1806 if (RT_LIKELY(rc == VINF_SUCCESS))
1807 {
1808 if (pgmMapAreMappingsFloating(&pVM->pgm.s))
1809 pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
1810 }
1811 else
1812 {
1813 AssertMsg(rc == VINF_PGM_SYNC_CR3, ("%Rrc\n", rc));
1814 Assert(VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL | VMCPU_FF_PGM_SYNC_CR3));
1815 pVCpu->pgm.s.GCPhysCR3 = GCPhysOldCR3;
1816 pVCpu->pgm.s.fSyncFlags |= PGM_SYNC_MAP_CR3;
1817 if (pgmMapAreMappingsFloating(&pVM->pgm.s))
1818 pVCpu->pgm.s.fSyncFlags |= PGM_SYNC_MONITOR_CR3;
1819 }
1820
1821 if (fGlobal)
1822 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FlushTLBNewCR3Global));
1823 else
1824 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FlushTLBNewCR3));
1825 }
1826 else
1827 {
1828# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
1829 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1830 if (pPool->cDirtyPages)
1831 {
1832 pgmLock(pVM);
1833 pgmPoolResetDirtyPages(pVM);
1834 pgmUnlock(pVM);
1835 }
1836# endif
1837 /*
1838 * Check if we have a pending update of the CR3 monitoring.
1839 */
1840 if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
1841 {
1842 pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
1843 Assert(!pVM->pgm.s.fMappingsFixed); Assert(!pVM->pgm.s.fMappingsDisabled);
1844 }
1845 if (fGlobal)
1846 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FlushTLBSameCR3Global));
1847 else
1848 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FlushTLBSameCR3));
1849 }
1850
1851 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FlushTLB), a);
1852 return rc;
1853}
1854
1855
1856/**
1857 * Performs and schedules necessary updates following a CR3 load or reload when
1858 * using nested or extended paging.
1859 *
1860 * This API is an alterantive to PDMFlushTLB that avoids actually flushing the
1861 * TLB and triggering a SyncCR3.
1862 *
1863 * This will normally involve mapping the guest PD or nPDPT
1864 *
1865 * @returns VBox status code.
1866 * @retval VINF_SUCCESS.
1867 * @retval (If applied when not in nested mode: VINF_PGM_SYNC_CR3 if monitoring
1868 * requires a CR3 sync. This can safely be ignored and overridden since
1869 * the FF will be set too then.)
1870 * @param pVCpu VMCPU handle.
1871 * @param cr3 The new cr3.
1872 */
1873VMMDECL(int) PGMUpdateCR3(PVMCPU pVCpu, uint64_t cr3)
1874{
1875 PVM pVM = pVCpu->CTX_SUFF(pVM);
1876
1877 LogFlow(("PGMUpdateCR3: cr3=%RX64 OldCr3=%RX64\n", cr3, pVCpu->pgm.s.GCPhysCR3));
1878
1879 /* We assume we're only called in nested paging mode. */
1880 Assert(pVM->pgm.s.fNestedPaging || pVCpu->pgm.s.enmShadowMode == PGMMODE_EPT);
1881 Assert(pVM->pgm.s.fMappingsDisabled);
1882 Assert(!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3));
1883
1884 /*
1885 * Remap the CR3 content and adjust the monitoring if CR3 was actually changed.
1886 */
1887 int rc = VINF_SUCCESS;
1888 RTGCPHYS GCPhysCR3;
1889 switch (pVCpu->pgm.s.enmGuestMode)
1890 {
1891 case PGMMODE_PAE:
1892 case PGMMODE_PAE_NX:
1893 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAE_PAGE_MASK);
1894 break;
1895 case PGMMODE_AMD64:
1896 case PGMMODE_AMD64_NX:
1897 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_AMD64_PAGE_MASK);
1898 break;
1899 default:
1900 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAGE_MASK);
1901 break;
1902 }
1903 if (pVCpu->pgm.s.GCPhysCR3 != GCPhysCR3)
1904 {
1905 pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3;
1906 rc = PGM_BTH_PFN(MapCR3, pVCpu)(pVCpu, GCPhysCR3);
1907 AssertRCSuccess(rc); /* Assumes VINF_PGM_SYNC_CR3 doesn't apply to nested paging. */ /** @todo this isn't true for the mac, but we need hw to test/fix this. */
1908 }
1909 return rc;
1910}
1911
1912
1913/**
1914 * Synchronize the paging structures.
1915 *
1916 * This function is called in response to the VM_FF_PGM_SYNC_CR3 and
1917 * VM_FF_PGM_SYNC_CR3_NONGLOBAL. Those two force action flags are set
1918 * in several places, most importantly whenever the CR3 is loaded.
1919 *
1920 * @returns VBox status code.
1921 * @param pVCpu VMCPU handle.
1922 * @param cr0 Guest context CR0 register
1923 * @param cr3 Guest context CR3 register
1924 * @param cr4 Guest context CR4 register
1925 * @param fGlobal Including global page directories or not
1926 */
1927VMMDECL(int) PGMSyncCR3(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
1928{
1929 PVM pVM = pVCpu->CTX_SUFF(pVM);
1930 int rc;
1931
1932 /*
1933 * The pool may have pending stuff and even require a return to ring-3 to
1934 * clear the whole thing.
1935 */
1936 rc = pgmPoolSyncCR3(pVCpu);
1937 if (rc != VINF_SUCCESS)
1938 return rc;
1939
1940 /*
1941 * We might be called when we shouldn't.
1942 *
1943 * The mode switching will ensure that the PD is resynced
1944 * after every mode switch. So, if we find ourselves here
1945 * when in protected or real mode we can safely disable the
1946 * FF and return immediately.
1947 */
1948 if (pVCpu->pgm.s.enmGuestMode <= PGMMODE_PROTECTED)
1949 {
1950 Assert((cr0 & (X86_CR0_PG | X86_CR0_PE)) != (X86_CR0_PG | X86_CR0_PE));
1951 Assert(!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL));
1952 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
1953 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
1954 return VINF_SUCCESS;
1955 }
1956
1957 /* If global pages are not supported, then all flushes are global. */
1958 if (!(cr4 & X86_CR4_PGE))
1959 fGlobal = true;
1960 LogFlow(("PGMSyncCR3: cr0=%RX64 cr3=%RX64 cr4=%RX64 fGlobal=%d[%d,%d]\n", cr0, cr3, cr4, fGlobal,
1961 VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3), VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)));
1962
1963 /*
1964 * Check if we need to finish an aborted MapCR3 call (see PGMFlushTLB).
1965 * This should be done before SyncCR3.
1966 */
1967 if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MAP_CR3)
1968 {
1969 pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MAP_CR3;
1970
1971 RTGCPHYS GCPhysCR3Old = pVCpu->pgm.s.GCPhysCR3;
1972 RTGCPHYS GCPhysCR3;
1973 switch (pVCpu->pgm.s.enmGuestMode)
1974 {
1975 case PGMMODE_PAE:
1976 case PGMMODE_PAE_NX:
1977 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAE_PAGE_MASK);
1978 break;
1979 case PGMMODE_AMD64:
1980 case PGMMODE_AMD64_NX:
1981 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_AMD64_PAGE_MASK);
1982 break;
1983 default:
1984 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAGE_MASK);
1985 break;
1986 }
1987
1988 if (pVCpu->pgm.s.GCPhysCR3 != GCPhysCR3)
1989 {
1990 pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3;
1991 rc = PGM_BTH_PFN(MapCR3, pVCpu)(pVCpu, GCPhysCR3);
1992 }
1993 /* Make sure we check for pending pgm pool syncs as we clear VMCPU_FF_PGM_SYNC_CR3 later on! */
1994 if ( rc == VINF_PGM_SYNC_CR3
1995 || (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL))
1996 {
1997 Log(("PGMSyncCR3: pending pgm pool sync after MapCR3!\n"));
1998#ifdef IN_RING3
1999 rc = pgmPoolSyncCR3(pVCpu);
2000#else
2001 if (rc == VINF_PGM_SYNC_CR3)
2002 pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3Old;
2003 return VINF_PGM_SYNC_CR3;
2004#endif
2005 }
2006 AssertRCReturn(rc, rc);
2007 AssertRCSuccessReturn(rc, VERR_INTERNAL_ERROR);
2008 }
2009
2010 /*
2011 * Let the 'Bth' function do the work and we'll just keep track of the flags.
2012 */
2013 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3), a);
2014 rc = PGM_BTH_PFN(SyncCR3, pVCpu)(pVCpu, cr0, cr3, cr4, fGlobal);
2015 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3), a);
2016 AssertMsg(rc == VINF_SUCCESS || rc == VINF_PGM_SYNC_CR3 || RT_FAILURE(rc), ("rc=%Rrc\n", rc));
2017 if (rc == VINF_SUCCESS)
2018 {
2019 if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL)
2020 {
2021 /* Go back to ring 3 if a pgm pool sync is again pending. */
2022 return VINF_PGM_SYNC_CR3;
2023 }
2024
2025 if (!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS))
2026 {
2027 Assert(!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL));
2028 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2029 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
2030 }
2031
2032 /*
2033 * Check if we have a pending update of the CR3 monitoring.
2034 */
2035 if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
2036 {
2037 pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
2038 Assert(!pVM->pgm.s.fMappingsFixed); Assert(!pVM->pgm.s.fMappingsDisabled);
2039 }
2040 }
2041
2042 /*
2043 * Now flush the CR3 (guest context).
2044 */
2045 if (rc == VINF_SUCCESS)
2046 PGM_INVL_VCPU_TLBS(pVCpu);
2047 return rc;
2048}
2049
2050
2051/**
2052 * Called whenever CR0 or CR4 in a way which may affect the paging mode.
2053 *
2054 * @returns VBox status code, with the following informational code for
2055 * VM scheduling.
2056 * @retval VINF_SUCCESS if the was no change, or it was successfully dealt with.
2057 * @retval VINF_PGM_CHANGE_MODE if we're in RC or R0 and the mode changes.
2058 * (I.e. not in R3.)
2059 * @retval VINF_EM_SUSPEND or VINF_EM_OFF on a fatal runtime error. (R3 only)
2060 *
2061 * @param pVCpu VMCPU handle.
2062 * @param cr0 The new cr0.
2063 * @param cr4 The new cr4.
2064 * @param efer The new extended feature enable register.
2065 */
2066VMMDECL(int) PGMChangeMode(PVMCPU pVCpu, uint64_t cr0, uint64_t cr4, uint64_t efer)
2067{
2068 PVM pVM = pVCpu->CTX_SUFF(pVM);
2069 PGMMODE enmGuestMode;
2070
2071 /*
2072 * Calc the new guest mode.
2073 */
2074 if (!(cr0 & X86_CR0_PE))
2075 enmGuestMode = PGMMODE_REAL;
2076 else if (!(cr0 & X86_CR0_PG))
2077 enmGuestMode = PGMMODE_PROTECTED;
2078 else if (!(cr4 & X86_CR4_PAE))
2079 {
2080 bool const fPse = !!(cr4 & X86_CR4_PSE);
2081 if (pVCpu->pgm.s.fGst32BitPageSizeExtension != fPse)
2082 Log(("PGMChangeMode: CR4.PSE %d -> %d\n", pVCpu->pgm.s.fGst32BitPageSizeExtension, fPse));
2083 pVCpu->pgm.s.fGst32BitPageSizeExtension = fPse;
2084 enmGuestMode = PGMMODE_32_BIT;
2085 }
2086 else if (!(efer & MSR_K6_EFER_LME))
2087 {
2088 if (!(efer & MSR_K6_EFER_NXE))
2089 enmGuestMode = PGMMODE_PAE;
2090 else
2091 enmGuestMode = PGMMODE_PAE_NX;
2092 }
2093 else
2094 {
2095 if (!(efer & MSR_K6_EFER_NXE))
2096 enmGuestMode = PGMMODE_AMD64;
2097 else
2098 enmGuestMode = PGMMODE_AMD64_NX;
2099 }
2100
2101 /*
2102 * Did it change?
2103 */
2104 if (pVCpu->pgm.s.enmGuestMode == enmGuestMode)
2105 return VINF_SUCCESS;
2106
2107 /* Flush the TLB */
2108 PGM_INVL_VCPU_TLBS(pVCpu);
2109
2110#ifdef IN_RING3
2111 return PGMR3ChangeMode(pVM, pVCpu, enmGuestMode);
2112#else
2113 LogFlow(("PGMChangeMode: returns VINF_PGM_CHANGE_MODE.\n"));
2114 return VINF_PGM_CHANGE_MODE;
2115#endif
2116}
2117
2118
2119/**
2120 * Gets the current guest paging mode.
2121 *
2122 * If you just need the CPU mode (real/protected/long), use CPUMGetGuestMode().
2123 *
2124 * @returns The current paging mode.
2125 * @param pVCpu VMCPU handle.
2126 */
2127VMMDECL(PGMMODE) PGMGetGuestMode(PVMCPU pVCpu)
2128{
2129 return pVCpu->pgm.s.enmGuestMode;
2130}
2131
2132
2133/**
2134 * Gets the current shadow paging mode.
2135 *
2136 * @returns The current paging mode.
2137 * @param pVCpu VMCPU handle.
2138 */
2139VMMDECL(PGMMODE) PGMGetShadowMode(PVMCPU pVCpu)
2140{
2141 return pVCpu->pgm.s.enmShadowMode;
2142}
2143
2144/**
2145 * Gets the current host paging mode.
2146 *
2147 * @returns The current paging mode.
2148 * @param pVM The VM handle.
2149 */
2150VMMDECL(PGMMODE) PGMGetHostMode(PVM pVM)
2151{
2152 switch (pVM->pgm.s.enmHostMode)
2153 {
2154 case SUPPAGINGMODE_32_BIT:
2155 case SUPPAGINGMODE_32_BIT_GLOBAL:
2156 return PGMMODE_32_BIT;
2157
2158 case SUPPAGINGMODE_PAE:
2159 case SUPPAGINGMODE_PAE_GLOBAL:
2160 return PGMMODE_PAE;
2161
2162 case SUPPAGINGMODE_PAE_NX:
2163 case SUPPAGINGMODE_PAE_GLOBAL_NX:
2164 return PGMMODE_PAE_NX;
2165
2166 case SUPPAGINGMODE_AMD64:
2167 case SUPPAGINGMODE_AMD64_GLOBAL:
2168 return PGMMODE_AMD64;
2169
2170 case SUPPAGINGMODE_AMD64_NX:
2171 case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2172 return PGMMODE_AMD64_NX;
2173
2174 default: AssertMsgFailed(("enmHostMode=%d\n", pVM->pgm.s.enmHostMode)); break;
2175 }
2176
2177 return PGMMODE_INVALID;
2178}
2179
2180
2181/**
2182 * Get mode name.
2183 *
2184 * @returns read-only name string.
2185 * @param enmMode The mode which name is desired.
2186 */
2187VMMDECL(const char *) PGMGetModeName(PGMMODE enmMode)
2188{
2189 switch (enmMode)
2190 {
2191 case PGMMODE_REAL: return "Real";
2192 case PGMMODE_PROTECTED: return "Protected";
2193 case PGMMODE_32_BIT: return "32-bit";
2194 case PGMMODE_PAE: return "PAE";
2195 case PGMMODE_PAE_NX: return "PAE+NX";
2196 case PGMMODE_AMD64: return "AMD64";
2197 case PGMMODE_AMD64_NX: return "AMD64+NX";
2198 case PGMMODE_NESTED: return "Nested";
2199 case PGMMODE_EPT: return "EPT";
2200 default: return "unknown mode value";
2201 }
2202}
2203
2204
2205
2206/**
2207 * Notification from CPUM that the EFER.NXE bit has changed.
2208 *
2209 * @param pVCpu The virtual CPU for which EFER changed.
2210 * @param fNxe The new NXE state.
2211 */
2212VMM_INT_DECL(void) PGMNotifyNxeChanged(PVMCPU pVCpu, bool fNxe)
2213{
2214 Log(("PGMNotifyNxeChanged: fNxe=%RTbool\n", fNxe));
2215 pVCpu->pgm.s.fNoExecuteEnabled = fNxe;
2216 if (fNxe)
2217 {
2218 /*pVCpu->pgm.s.fGst32BitMbzBigPdeMask - N/A */
2219 pVCpu->pgm.s.fGstPaeMbzPteMask &= ~X86_PTE_PAE_NX;
2220 pVCpu->pgm.s.fGstPaeMbzPdeMask &= ~X86_PDE_PAE_NX;
2221 pVCpu->pgm.s.fGstPaeMbzBigPdeMask &= ~X86_PDE2M_PAE_NX;
2222 /*pVCpu->pgm.s.fGstPaeMbzPdpeMask - N/A */
2223 pVCpu->pgm.s.fGstAmd64MbzPteMask &= ~X86_PTE_PAE_NX;
2224 pVCpu->pgm.s.fGstAmd64MbzPdeMask &= ~X86_PDE_PAE_NX;
2225 pVCpu->pgm.s.fGstAmd64MbzBigPdeMask &= ~X86_PDE2M_PAE_NX;
2226 pVCpu->pgm.s.fGstAmd64MbzPdpeMask &= ~X86_PDPE_LM_NX;
2227 pVCpu->pgm.s.fGstAmd64MbzBigPdpeMask &= ~X86_PDPE_LM_NX;
2228 pVCpu->pgm.s.fGstAmd64MbzPml4eMask &= ~X86_PML4E_NX;
2229 }
2230 else
2231 {
2232 /*pVCpu->pgm.s.fGst32BitMbzBigPdeMask - N/A */
2233 pVCpu->pgm.s.fGstPaeMbzPteMask |= X86_PTE_PAE_NX;
2234 pVCpu->pgm.s.fGstPaeMbzPdeMask |= X86_PDE_PAE_NX;
2235 pVCpu->pgm.s.fGstPaeMbzBigPdeMask |= X86_PDE2M_PAE_NX;
2236 /*pVCpu->pgm.s.fGstPaeMbzPdpeMask - N/A */
2237 pVCpu->pgm.s.fGstAmd64MbzPteMask |= X86_PTE_PAE_NX;
2238 pVCpu->pgm.s.fGstAmd64MbzPdeMask |= X86_PDE_PAE_NX;
2239 pVCpu->pgm.s.fGstAmd64MbzBigPdeMask |= X86_PDE2M_PAE_NX;
2240 pVCpu->pgm.s.fGstAmd64MbzPdpeMask |= X86_PDPE_LM_NX;
2241 pVCpu->pgm.s.fGstAmd64MbzBigPdpeMask |= X86_PDPE_LM_NX;
2242 pVCpu->pgm.s.fGstAmd64MbzPml4eMask |= X86_PML4E_NX;
2243 }
2244}
2245
2246
2247/**
2248 * Check if any pgm pool pages are marked dirty (not monitored)
2249 *
2250 * @returns bool locked/not locked
2251 * @param pVM The VM to operate on.
2252 */
2253VMMDECL(bool) PGMHasDirtyPages(PVM pVM)
2254{
2255 return pVM->pgm.s.CTX_SUFF(pPool)->cDirtyPages != 0;
2256}
2257
2258/**
2259 * Check if the PGM lock is currently taken.
2260 *
2261 * @returns bool locked/not locked
2262 * @param pVM The VM to operate on.
2263 */
2264VMMDECL(bool) PGMIsLocked(PVM pVM)
2265{
2266 return PDMCritSectIsOwned(&pVM->pgm.s.CritSect);
2267}
2268
2269
2270/**
2271 * Check if this VCPU currently owns the PGM lock.
2272 *
2273 * @returns bool owner/not owner
2274 * @param pVM The VM to operate on.
2275 */
2276VMMDECL(bool) PGMIsLockOwner(PVM pVM)
2277{
2278 return PDMCritSectIsOwner(&pVM->pgm.s.CritSect);
2279}
2280
2281
2282/**
2283 * Enable or disable large page usage
2284 *
2285 * @param pVM The VM to operate on.
2286 * @param fUseLargePages Use/not use large pages
2287 */
2288VMMDECL(void) PGMSetLargePageUsage(PVM pVM, bool fUseLargePages)
2289{
2290 pVM->fUseLargePages = fUseLargePages;
2291}
2292
2293/**
2294 * Acquire the PGM lock.
2295 *
2296 * @returns VBox status code
2297 * @param pVM The VM to operate on.
2298 */
2299int pgmLock(PVM pVM)
2300{
2301 int rc = PDMCritSectEnter(&pVM->pgm.s.CritSect, VERR_SEM_BUSY);
2302#if defined(IN_RC) || defined(IN_RING0)
2303 if (rc == VERR_SEM_BUSY)
2304 rc = VMMRZCallRing3NoCpu(pVM, VMMCALLRING3_PGM_LOCK, 0);
2305#endif
2306 AssertMsg(rc == VINF_SUCCESS, ("%Rrc\n", rc));
2307 return rc;
2308}
2309
2310
2311/**
2312 * Release the PGM lock.
2313 *
2314 * @returns VBox status code
2315 * @param pVM The VM to operate on.
2316 */
2317void pgmUnlock(PVM pVM)
2318{
2319 PDMCritSectLeave(&pVM->pgm.s.CritSect);
2320}
2321
2322#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2323
2324/**
2325 * Common worker for pgmRZDynMapGCPageOffInlined and pgmRZDynMapGCPageV2Inlined.
2326 *
2327 * @returns VBox status code.
2328 * @param pVM The VM handle.
2329 * @param pVCpu The current CPU.
2330 * @param GCPhys The guest physical address of the page to map. The
2331 * offset bits are not ignored.
2332 * @param ppv Where to return the address corresponding to @a GCPhys.
2333 */
2334int pgmRZDynMapGCPageCommon(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void **ppv RTLOG_COMMA_SRC_POS_DECL)
2335{
2336 pgmLock(pVM);
2337
2338 /*
2339 * Convert it to a writable page and it on to the dynamic mapper.
2340 */
2341 int rc;
2342 PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, GCPhys);
2343 if (RT_LIKELY(pPage))
2344 {
2345 rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
2346 if (RT_SUCCESS(rc))
2347 {
2348 void *pv;
2349 rc = pgmRZDynMapHCPageInlined(pVCpu, PGM_PAGE_GET_HCPHYS(pPage), &pv RTLOG_COMMA_SRC_POS_ARGS);
2350 if (RT_SUCCESS(rc))
2351 *ppv = (void *)((uintptr_t)pv | ((uintptr_t)GCPhys & PAGE_OFFSET_MASK));
2352 }
2353 else
2354 AssertRC(rc);
2355 }
2356 else
2357 {
2358 AssertMsgFailed(("Invalid physical address %RGp!\n", GCPhys));
2359 rc = VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2360 }
2361
2362 pgmUnlock(pVM);
2363 return rc;
2364}
2365
2366#endif /* IN_RC || VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
2367#if !defined(IN_R0) || defined(LOG_ENABLED)
2368
2369/** Format handler for PGMPAGE.
2370 * @copydoc FNRTSTRFORMATTYPE */
2371static DECLCALLBACK(size_t) pgmFormatTypeHandlerPage(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
2372 const char *pszType, void const *pvValue,
2373 int cchWidth, int cchPrecision, unsigned fFlags,
2374 void *pvUser)
2375{
2376 size_t cch;
2377 PCPGMPAGE pPage = (PCPGMPAGE)pvValue;
2378 if (VALID_PTR(pPage))
2379 {
2380 char szTmp[64+80];
2381
2382 cch = 0;
2383
2384 /* The single char state stuff. */
2385 static const char s_achPageStates[4] = { 'Z', 'A', 'W', 'S' };
2386 szTmp[cch++] = s_achPageStates[PGM_PAGE_GET_STATE(pPage)];
2387
2388#define IS_PART_INCLUDED(lvl) ( !(fFlags & RTSTR_F_PRECISION) || cchPrecision == (lvl) || cchPrecision >= (lvl)+10 )
2389 if (IS_PART_INCLUDED(5))
2390 {
2391 static const char s_achHandlerStates[4] = { '-', 't', 'w', 'a' };
2392 szTmp[cch++] = s_achHandlerStates[PGM_PAGE_GET_HNDL_PHYS_STATE(pPage)];
2393 szTmp[cch++] = s_achHandlerStates[PGM_PAGE_GET_HNDL_VIRT_STATE(pPage)];
2394 }
2395
2396 /* The type. */
2397 if (IS_PART_INCLUDED(4))
2398 {
2399 szTmp[cch++] = ':';
2400 static const char s_achPageTypes[8][4] = { "INV", "RAM", "MI2", "M2A", "SHA", "ROM", "MIO", "BAD" };
2401 szTmp[cch++] = s_achPageTypes[PGM_PAGE_GET_TYPE(pPage)][0];
2402 szTmp[cch++] = s_achPageTypes[PGM_PAGE_GET_TYPE(pPage)][1];
2403 szTmp[cch++] = s_achPageTypes[PGM_PAGE_GET_TYPE(pPage)][2];
2404 }
2405
2406 /* The numbers. */
2407 if (IS_PART_INCLUDED(3))
2408 {
2409 szTmp[cch++] = ':';
2410 cch += RTStrFormatNumber(&szTmp[cch], PGM_PAGE_GET_HCPHYS(pPage), 16, 12, 0, RTSTR_F_ZEROPAD | RTSTR_F_64BIT);
2411 }
2412
2413 if (IS_PART_INCLUDED(2))
2414 {
2415 szTmp[cch++] = ':';
2416 cch += RTStrFormatNumber(&szTmp[cch], PGM_PAGE_GET_PAGEID(pPage), 16, 7, 0, RTSTR_F_ZEROPAD | RTSTR_F_32BIT);
2417 }
2418
2419 if (IS_PART_INCLUDED(6))
2420 {
2421 szTmp[cch++] = ':';
2422 static const char s_achRefs[4] = { '-', 'U', '!', 'L' };
2423 szTmp[cch++] = s_achRefs[PGM_PAGE_GET_TD_CREFS(pPage)];
2424 cch += RTStrFormatNumber(&szTmp[cch], PGM_PAGE_GET_TD_IDX(pPage), 16, 4, 0, RTSTR_F_ZEROPAD | RTSTR_F_16BIT);
2425 }
2426#undef IS_PART_INCLUDED
2427
2428 cch = pfnOutput(pvArgOutput, szTmp, cch);
2429 }
2430 else
2431 cch = pfnOutput(pvArgOutput, "<bad-pgmpage-ptr>", sizeof("<bad-pgmpage-ptr>") - 1);
2432 return cch;
2433}
2434
2435
2436/** Format handler for PGMRAMRANGE.
2437 * @copydoc FNRTSTRFORMATTYPE */
2438static DECLCALLBACK(size_t) pgmFormatTypeHandlerRamRange(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
2439 const char *pszType, void const *pvValue,
2440 int cchWidth, int cchPrecision, unsigned fFlags,
2441 void *pvUser)
2442{
2443 size_t cch;
2444 PGMRAMRANGE const *pRam = (PGMRAMRANGE const *)pvValue;
2445 if (VALID_PTR(pRam))
2446 {
2447 char szTmp[80];
2448 cch = RTStrPrintf(szTmp, sizeof(szTmp), "%RGp-%RGp", pRam->GCPhys, pRam->GCPhysLast);
2449 cch = pfnOutput(pvArgOutput, szTmp, cch);
2450 }
2451 else
2452 cch = pfnOutput(pvArgOutput, "<bad-pgmramrange-ptr>", sizeof("<bad-pgmramrange-ptr>") - 1);
2453 return cch;
2454}
2455
2456/** Format type andlers to be registered/deregistered. */
2457static const struct
2458{
2459 char szType[24];
2460 PFNRTSTRFORMATTYPE pfnHandler;
2461} g_aPgmFormatTypes[] =
2462{
2463 { "pgmpage", pgmFormatTypeHandlerPage },
2464 { "pgmramrange", pgmFormatTypeHandlerRamRange }
2465};
2466
2467#endif /* !IN_R0 || LOG_ENABLED */
2468
2469/**
2470 * Registers the global string format types.
2471 *
2472 * This should be called at module load time or in some other manner that ensure
2473 * that it's called exactly one time.
2474 *
2475 * @returns IPRT status code on RTStrFormatTypeRegister failure.
2476 */
2477VMMDECL(int) PGMRegisterStringFormatTypes(void)
2478{
2479#if !defined(IN_R0) || defined(LOG_ENABLED)
2480 int rc = VINF_SUCCESS;
2481 unsigned i;
2482 for (i = 0; RT_SUCCESS(rc) && i < RT_ELEMENTS(g_aPgmFormatTypes); i++)
2483 {
2484 rc = RTStrFormatTypeRegister(g_aPgmFormatTypes[i].szType, g_aPgmFormatTypes[i].pfnHandler, NULL);
2485# ifdef IN_RING0
2486 if (rc == VERR_ALREADY_EXISTS)
2487 {
2488 /* in case of cleanup failure in ring-0 */
2489 RTStrFormatTypeDeregister(g_aPgmFormatTypes[i].szType);
2490 rc = RTStrFormatTypeRegister(g_aPgmFormatTypes[i].szType, g_aPgmFormatTypes[i].pfnHandler, NULL);
2491 }
2492# endif
2493 }
2494 if (RT_FAILURE(rc))
2495 while (i-- > 0)
2496 RTStrFormatTypeDeregister(g_aPgmFormatTypes[i].szType);
2497
2498 return rc;
2499#else
2500 return VINF_SUCCESS;
2501#endif
2502}
2503
2504
2505/**
2506 * Deregisters the global string format types.
2507 *
2508 * This should be called at module unload time or in some other manner that
2509 * ensure that it's called exactly one time.
2510 */
2511VMMDECL(void) PGMDeregisterStringFormatTypes(void)
2512{
2513#if !defined(IN_R0) || defined(LOG_ENABLED)
2514 for (unsigned i = 0; i < RT_ELEMENTS(g_aPgmFormatTypes); i++)
2515 RTStrFormatTypeDeregister(g_aPgmFormatTypes[i].szType);
2516#endif
2517}
2518
2519#ifdef VBOX_STRICT
2520
2521/**
2522 * Asserts that there are no mapping conflicts.
2523 *
2524 * @returns Number of conflicts.
2525 * @param pVM The VM Handle.
2526 */
2527VMMDECL(unsigned) PGMAssertNoMappingConflicts(PVM pVM)
2528{
2529 unsigned cErrors = 0;
2530
2531 /* Only applies to raw mode -> 1 VPCU */
2532 Assert(pVM->cCpus == 1);
2533 PVMCPU pVCpu = &pVM->aCpus[0];
2534
2535 /*
2536 * Check for mapping conflicts.
2537 */
2538 for (PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
2539 pMapping;
2540 pMapping = pMapping->CTX_SUFF(pNext))
2541 {
2542 /** @todo This is slow and should be optimized, but since it's just assertions I don't care now. */
2543 for (RTGCPTR GCPtr = pMapping->GCPtr;
2544 GCPtr <= pMapping->GCPtrLast;
2545 GCPtr += PAGE_SIZE)
2546 {
2547 int rc = PGMGstGetPage(pVCpu, (RTGCPTR)GCPtr, NULL, NULL);
2548 if (rc != VERR_PAGE_TABLE_NOT_PRESENT)
2549 {
2550 AssertMsgFailed(("Conflict at %RGv with %s\n", GCPtr, R3STRING(pMapping->pszDesc)));
2551 cErrors++;
2552 break;
2553 }
2554 }
2555 }
2556
2557 return cErrors;
2558}
2559
2560
2561/**
2562 * Asserts that everything related to the guest CR3 is correctly shadowed.
2563 *
2564 * This will call PGMAssertNoMappingConflicts() and PGMAssertHandlerAndFlagsInSync(),
2565 * and assert the correctness of the guest CR3 mapping before asserting that the
2566 * shadow page tables is in sync with the guest page tables.
2567 *
2568 * @returns Number of conflicts.
2569 * @param pVM The VM Handle.
2570 * @param pVCpu VMCPU handle.
2571 * @param cr3 The current guest CR3 register value.
2572 * @param cr4 The current guest CR4 register value.
2573 */
2574VMMDECL(unsigned) PGMAssertCR3(PVM pVM, PVMCPU pVCpu, uint64_t cr3, uint64_t cr4)
2575{
2576 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3), a);
2577 pgmLock(pVM);
2578 unsigned cErrors = PGM_BTH_PFN(AssertCR3, pVCpu)(pVCpu, cr3, cr4, 0, ~(RTGCPTR)0);
2579 pgmUnlock(pVM);
2580 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3), a);
2581 return cErrors;
2582}
2583
2584#endif /* VBOX_STRICT */
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