VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAll.cpp@ 31997

Last change on this file since 31997 was 31997, checked in by vboxsync, 15 years ago

PGM: Don't shadow any extra bits in long mode PDPEs and PML4Es.
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File size: 84.7 KB
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1/* $Id: PGMAll.cpp 31997 2010-08-26 13:59:06Z vboxsync $ */
2/** @file
3 * PGM - Page Manager and Monitor - All context code.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/*******************************************************************************
19* Header Files *
20*******************************************************************************/
21#define LOG_GROUP LOG_GROUP_PGM
22#include <VBox/pgm.h>
23#include <VBox/cpum.h>
24#include <VBox/selm.h>
25#include <VBox/iom.h>
26#include <VBox/sup.h>
27#include <VBox/mm.h>
28#include <VBox/stam.h>
29#include <VBox/csam.h>
30#include <VBox/patm.h>
31#include <VBox/trpm.h>
32#include <VBox/rem.h>
33#include <VBox/em.h>
34#include <VBox/hwaccm.h>
35#include <VBox/hwacc_vmx.h>
36#include "../PGMInternal.h"
37#include <VBox/vm.h>
38#include "../PGMInline.h"
39#include <iprt/assert.h>
40#include <iprt/asm-amd64-x86.h>
41#include <iprt/string.h>
42#include <VBox/log.h>
43#include <VBox/param.h>
44#include <VBox/err.h>
45
46
47/*******************************************************************************
48* Structures and Typedefs *
49*******************************************************************************/
50/**
51 * Stated structure for PGM_GST_NAME(HandlerVirtualUpdate) that's
52 * passed to PGM_GST_NAME(VirtHandlerUpdateOne) during enumeration.
53 */
54typedef struct PGMHVUSTATE
55{
56 /** The VM handle. */
57 PVM pVM;
58 /** The VMCPU handle. */
59 PVMCPU pVCpu;
60 /** The todo flags. */
61 RTUINT fTodo;
62 /** The CR4 register value. */
63 uint32_t cr4;
64} PGMHVUSTATE, *PPGMHVUSTATE;
65
66
67/*******************************************************************************
68* Internal Functions *
69*******************************************************************************/
70DECLINLINE(int) pgmShwGetLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPT *ppPdpt, PX86PDPAE *ppPD);
71DECLINLINE(int) pgmShwGetPaePoolPagePD(PVMCPU pVCpu, RTGCPTR GCPtr, PPGMPOOLPAGE *ppShwPde);
72#ifndef IN_RC
73static int pgmShwSyncLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, X86PGPAEUINT uGstPml4e, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD);
74static int pgmShwGetEPTPDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PEPTPDPT *ppPdpt, PEPTPD *ppPD);
75#endif
76
77
78/*
79 * Shadow - 32-bit mode
80 */
81#define PGM_SHW_TYPE PGM_TYPE_32BIT
82#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
83#include "PGMAllShw.h"
84
85/* Guest - real mode */
86#define PGM_GST_TYPE PGM_TYPE_REAL
87#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
88#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
89#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
90#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
91#include "PGMGstDefs.h"
92#include "PGMAllGst.h"
93#include "PGMAllBth.h"
94#undef BTH_PGMPOOLKIND_PT_FOR_PT
95#undef BTH_PGMPOOLKIND_ROOT
96#undef PGM_BTH_NAME
97#undef PGM_GST_TYPE
98#undef PGM_GST_NAME
99
100/* Guest - protected mode */
101#define PGM_GST_TYPE PGM_TYPE_PROT
102#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
103#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
104#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
105#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
106#include "PGMGstDefs.h"
107#include "PGMAllGst.h"
108#include "PGMAllBth.h"
109#undef BTH_PGMPOOLKIND_PT_FOR_PT
110#undef BTH_PGMPOOLKIND_ROOT
111#undef PGM_BTH_NAME
112#undef PGM_GST_TYPE
113#undef PGM_GST_NAME
114
115/* Guest - 32-bit mode */
116#define PGM_GST_TYPE PGM_TYPE_32BIT
117#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
118#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
119#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
120#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
121#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD
122#include "PGMGstDefs.h"
123#include "PGMAllGst.h"
124#include "PGMAllBth.h"
125#undef BTH_PGMPOOLKIND_PT_FOR_BIG
126#undef BTH_PGMPOOLKIND_PT_FOR_PT
127#undef BTH_PGMPOOLKIND_ROOT
128#undef PGM_BTH_NAME
129#undef PGM_GST_TYPE
130#undef PGM_GST_NAME
131
132#undef PGM_SHW_TYPE
133#undef PGM_SHW_NAME
134
135
136/*
137 * Shadow - PAE mode
138 */
139#define PGM_SHW_TYPE PGM_TYPE_PAE
140#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
141#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
142#include "PGMAllShw.h"
143
144/* Guest - real mode */
145#define PGM_GST_TYPE PGM_TYPE_REAL
146#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
147#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
148#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
149#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
150#include "PGMGstDefs.h"
151#include "PGMAllBth.h"
152#undef BTH_PGMPOOLKIND_PT_FOR_PT
153#undef BTH_PGMPOOLKIND_ROOT
154#undef PGM_BTH_NAME
155#undef PGM_GST_TYPE
156#undef PGM_GST_NAME
157
158/* Guest - protected mode */
159#define PGM_GST_TYPE PGM_TYPE_PROT
160#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
161#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
162#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
163#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
164#include "PGMGstDefs.h"
165#include "PGMAllBth.h"
166#undef BTH_PGMPOOLKIND_PT_FOR_PT
167#undef BTH_PGMPOOLKIND_ROOT
168#undef PGM_BTH_NAME
169#undef PGM_GST_TYPE
170#undef PGM_GST_NAME
171
172/* Guest - 32-bit mode */
173#define PGM_GST_TYPE PGM_TYPE_32BIT
174#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
175#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
176#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
177#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
178#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_FOR_32BIT
179#include "PGMGstDefs.h"
180#include "PGMAllBth.h"
181#undef BTH_PGMPOOLKIND_PT_FOR_BIG
182#undef BTH_PGMPOOLKIND_PT_FOR_PT
183#undef BTH_PGMPOOLKIND_ROOT
184#undef PGM_BTH_NAME
185#undef PGM_GST_TYPE
186#undef PGM_GST_NAME
187
188
189/* Guest - PAE mode */
190#define PGM_GST_TYPE PGM_TYPE_PAE
191#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
192#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
193#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
194#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
195#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT
196#include "PGMGstDefs.h"
197#include "PGMAllGst.h"
198#include "PGMAllBth.h"
199#undef BTH_PGMPOOLKIND_PT_FOR_BIG
200#undef BTH_PGMPOOLKIND_PT_FOR_PT
201#undef BTH_PGMPOOLKIND_ROOT
202#undef PGM_BTH_NAME
203#undef PGM_GST_TYPE
204#undef PGM_GST_NAME
205
206#undef PGM_SHW_TYPE
207#undef PGM_SHW_NAME
208
209
210#ifndef IN_RC /* AMD64 implies VT-x/AMD-V */
211/*
212 * Shadow - AMD64 mode
213 */
214# define PGM_SHW_TYPE PGM_TYPE_AMD64
215# define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
216# include "PGMAllShw.h"
217
218/* Guest - protected mode (only used for AMD-V nested paging in 64 bits mode) */
219# define PGM_GST_TYPE PGM_TYPE_PROT
220# define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
221# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_PROT(name)
222# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
223# define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PD_PHYS
224# include "PGMGstDefs.h"
225# include "PGMAllBth.h"
226# undef BTH_PGMPOOLKIND_PT_FOR_PT
227# undef BTH_PGMPOOLKIND_ROOT
228# undef PGM_BTH_NAME
229# undef PGM_GST_TYPE
230# undef PGM_GST_NAME
231
232# ifdef VBOX_WITH_64_BITS_GUESTS
233/* Guest - AMD64 mode */
234# define PGM_GST_TYPE PGM_TYPE_AMD64
235# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
236# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
237# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
238# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
239# define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_64BIT_PML4
240# include "PGMGstDefs.h"
241# include "PGMAllGst.h"
242# include "PGMAllBth.h"
243# undef BTH_PGMPOOLKIND_PT_FOR_BIG
244# undef BTH_PGMPOOLKIND_PT_FOR_PT
245# undef BTH_PGMPOOLKIND_ROOT
246# undef PGM_BTH_NAME
247# undef PGM_GST_TYPE
248# undef PGM_GST_NAME
249# endif /* VBOX_WITH_64_BITS_GUESTS */
250
251# undef PGM_SHW_TYPE
252# undef PGM_SHW_NAME
253
254
255/*
256 * Shadow - Nested paging mode
257 */
258# define PGM_SHW_TYPE PGM_TYPE_NESTED
259# define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED(name)
260# include "PGMAllShw.h"
261
262/* Guest - real mode */
263# define PGM_GST_TYPE PGM_TYPE_REAL
264# define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
265# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_REAL(name)
266# include "PGMGstDefs.h"
267# include "PGMAllBth.h"
268# undef PGM_BTH_NAME
269# undef PGM_GST_TYPE
270# undef PGM_GST_NAME
271
272/* Guest - protected mode */
273# define PGM_GST_TYPE PGM_TYPE_PROT
274# define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
275# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PROT(name)
276# include "PGMGstDefs.h"
277# include "PGMAllBth.h"
278# undef PGM_BTH_NAME
279# undef PGM_GST_TYPE
280# undef PGM_GST_NAME
281
282/* Guest - 32-bit mode */
283# define PGM_GST_TYPE PGM_TYPE_32BIT
284# define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
285# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT(name)
286# include "PGMGstDefs.h"
287# include "PGMAllBth.h"
288# undef PGM_BTH_NAME
289# undef PGM_GST_TYPE
290# undef PGM_GST_NAME
291
292/* Guest - PAE mode */
293# define PGM_GST_TYPE PGM_TYPE_PAE
294# define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
295# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE(name)
296# include "PGMGstDefs.h"
297# include "PGMAllBth.h"
298# undef PGM_BTH_NAME
299# undef PGM_GST_TYPE
300# undef PGM_GST_NAME
301
302# ifdef VBOX_WITH_64_BITS_GUESTS
303/* Guest - AMD64 mode */
304# define PGM_GST_TYPE PGM_TYPE_AMD64
305# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
306# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64(name)
307# include "PGMGstDefs.h"
308# include "PGMAllBth.h"
309# undef PGM_BTH_NAME
310# undef PGM_GST_TYPE
311# undef PGM_GST_NAME
312# endif /* VBOX_WITH_64_BITS_GUESTS */
313
314# undef PGM_SHW_TYPE
315# undef PGM_SHW_NAME
316
317
318/*
319 * Shadow - EPT
320 */
321# define PGM_SHW_TYPE PGM_TYPE_EPT
322# define PGM_SHW_NAME(name) PGM_SHW_NAME_EPT(name)
323# include "PGMAllShw.h"
324
325/* Guest - real mode */
326# define PGM_GST_TYPE PGM_TYPE_REAL
327# define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
328# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_REAL(name)
329# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
330# include "PGMGstDefs.h"
331# include "PGMAllBth.h"
332# undef BTH_PGMPOOLKIND_PT_FOR_PT
333# undef PGM_BTH_NAME
334# undef PGM_GST_TYPE
335# undef PGM_GST_NAME
336
337/* Guest - protected mode */
338# define PGM_GST_TYPE PGM_TYPE_PROT
339# define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
340# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PROT(name)
341# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
342# include "PGMGstDefs.h"
343# include "PGMAllBth.h"
344# undef BTH_PGMPOOLKIND_PT_FOR_PT
345# undef PGM_BTH_NAME
346# undef PGM_GST_TYPE
347# undef PGM_GST_NAME
348
349/* Guest - 32-bit mode */
350# define PGM_GST_TYPE PGM_TYPE_32BIT
351# define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
352# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_32BIT(name)
353# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
354# include "PGMGstDefs.h"
355# include "PGMAllBth.h"
356# undef BTH_PGMPOOLKIND_PT_FOR_PT
357# undef PGM_BTH_NAME
358# undef PGM_GST_TYPE
359# undef PGM_GST_NAME
360
361/* Guest - PAE mode */
362# define PGM_GST_TYPE PGM_TYPE_PAE
363# define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
364# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PAE(name)
365# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
366# include "PGMGstDefs.h"
367# include "PGMAllBth.h"
368# undef BTH_PGMPOOLKIND_PT_FOR_PT
369# undef PGM_BTH_NAME
370# undef PGM_GST_TYPE
371# undef PGM_GST_NAME
372
373# ifdef VBOX_WITH_64_BITS_GUESTS
374/* Guest - AMD64 mode */
375# define PGM_GST_TYPE PGM_TYPE_AMD64
376# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
377# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_AMD64(name)
378# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
379# include "PGMGstDefs.h"
380# include "PGMAllBth.h"
381# undef BTH_PGMPOOLKIND_PT_FOR_PT
382# undef PGM_BTH_NAME
383# undef PGM_GST_TYPE
384# undef PGM_GST_NAME
385# endif /* VBOX_WITH_64_BITS_GUESTS */
386
387# undef PGM_SHW_TYPE
388# undef PGM_SHW_NAME
389
390#endif /* !IN_RC */
391
392
393#ifndef IN_RING3
394/**
395 * #PF Handler.
396 *
397 * @returns VBox status code (appropriate for trap handling and GC return).
398 * @param pVCpu VMCPU handle.
399 * @param uErr The trap error code.
400 * @param pRegFrame Trap register frame.
401 * @param pvFault The fault address.
402 */
403VMMDECL(int) PGMTrap0eHandler(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
404{
405 PVM pVM = pVCpu->CTX_SUFF(pVM);
406
407 Log(("PGMTrap0eHandler: uErr=%RGx pvFault=%RGv eip=%04x:%RGv cr3=%RGp\n", uErr, pvFault, pRegFrame->cs, (RTGCPTR)pRegFrame->rip, (RTGCPHYS)CPUMGetGuestCR3(pVCpu)));
408 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0e, a);
409 STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = NULL; } );
410
411
412#ifdef VBOX_WITH_STATISTICS
413 /*
414 * Error code stats.
415 */
416 if (uErr & X86_TRAP_PF_US)
417 {
418 if (!(uErr & X86_TRAP_PF_P))
419 {
420 if (uErr & X86_TRAP_PF_RW)
421 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eUSNotPresentWrite);
422 else
423 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eUSNotPresentRead);
424 }
425 else if (uErr & X86_TRAP_PF_RW)
426 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eUSWrite);
427 else if (uErr & X86_TRAP_PF_RSVD)
428 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eUSReserved);
429 else if (uErr & X86_TRAP_PF_ID)
430 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eUSNXE);
431 else
432 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eUSRead);
433 }
434 else
435 { /* Supervisor */
436 if (!(uErr & X86_TRAP_PF_P))
437 {
438 if (uErr & X86_TRAP_PF_RW)
439 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eSVNotPresentWrite);
440 else
441 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eSVNotPresentRead);
442 }
443 else if (uErr & X86_TRAP_PF_RW)
444 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eSVWrite);
445 else if (uErr & X86_TRAP_PF_ID)
446 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eSNXE);
447 else if (uErr & X86_TRAP_PF_RSVD)
448 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eSVReserved);
449 }
450#endif /* VBOX_WITH_STATISTICS */
451
452 /*
453 * Call the worker.
454 */
455 bool fLockTaken = false;
456 int rc = PGM_BTH_PFN(Trap0eHandler, pVCpu)(pVCpu, uErr, pRegFrame, pvFault, &fLockTaken);
457 if (fLockTaken)
458 {
459 Assert(PGMIsLockOwner(pVM));
460 pgmUnlock(pVM);
461 }
462 LogFlow(("PGMTrap0eHandler: uErr=%RGx pvFault=%RGv rc=%Rrc\n", uErr, pvFault, rc));
463
464 /*
465 * Return code tweaks.
466 */
467 if (rc != VINF_SUCCESS)
468 {
469 if (rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
470 rc = VINF_SUCCESS;
471
472# ifdef IN_RING0
473 /* Note: hack alert for difficult to reproduce problem. */
474 if ( rc == VERR_PAGE_NOT_PRESENT /* SMP only ; disassembly might fail. */
475 || rc == VERR_PAGE_TABLE_NOT_PRESENT /* seen with UNI & SMP */
476 || rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT /* seen with SMP */
477 || rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT) /* precaution */
478 {
479 Log(("WARNING: Unexpected VERR_PAGE_TABLE_NOT_PRESENT (%d) for page fault at %RGv error code %x (rip=%RGv)\n", rc, pvFault, uErr, pRegFrame->rip));
480 /* Some kind of inconsistency in the SMP case; it's safe to just execute the instruction again; not sure about single VCPU VMs though. */
481 rc = VINF_SUCCESS;
482 }
483# endif
484 }
485
486 STAM_STATS({ if (rc == VINF_EM_RAW_GUEST_TRAP) STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eGuestPF); });
487 STAM_STATS({ if (!pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution))
488 pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Misc; });
489 STAM_PROFILE_STOP_EX(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0e, pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution), a);
490 return rc;
491}
492#endif /* !IN_RING3 */
493
494
495/**
496 * Prefetch a page
497 *
498 * Typically used to sync commonly used pages before entering raw mode
499 * after a CR3 reload.
500 *
501 * @returns VBox status code suitable for scheduling.
502 * @retval VINF_SUCCESS on success.
503 * @retval VINF_PGM_SYNC_CR3 if we're out of shadow pages or something like that.
504 * @param pVCpu VMCPU handle.
505 * @param GCPtrPage Page to invalidate.
506 */
507VMMDECL(int) PGMPrefetchPage(PVMCPU pVCpu, RTGCPTR GCPtrPage)
508{
509 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Prefetch), a);
510 int rc = PGM_BTH_PFN(PrefetchPage, pVCpu)(pVCpu, GCPtrPage);
511 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Prefetch), a);
512 AssertMsg(rc == VINF_SUCCESS || rc == VINF_PGM_SYNC_CR3 || RT_FAILURE(rc), ("rc=%Rrc\n", rc));
513 return rc;
514}
515
516
517/**
518 * Gets the mapping corresponding to the specified address (if any).
519 *
520 * @returns Pointer to the mapping.
521 * @returns NULL if not
522 *
523 * @param pVM The virtual machine.
524 * @param GCPtr The guest context pointer.
525 */
526PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr)
527{
528 PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
529 while (pMapping)
530 {
531 if ((uintptr_t)GCPtr < (uintptr_t)pMapping->GCPtr)
532 break;
533 if ((uintptr_t)GCPtr - (uintptr_t)pMapping->GCPtr < pMapping->cb)
534 return pMapping;
535 pMapping = pMapping->CTX_SUFF(pNext);
536 }
537 return NULL;
538}
539
540
541/**
542 * Verifies a range of pages for read or write access
543 *
544 * Only checks the guest's page tables
545 *
546 * @returns VBox status code.
547 * @param pVCpu VMCPU handle.
548 * @param Addr Guest virtual address to check
549 * @param cbSize Access size
550 * @param fAccess Access type (r/w, user/supervisor (X86_PTE_*))
551 * @remarks Current not in use.
552 */
553VMMDECL(int) PGMIsValidAccess(PVMCPU pVCpu, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess)
554{
555 /*
556 * Validate input.
557 */
558 if (fAccess & ~(X86_PTE_US | X86_PTE_RW))
559 {
560 AssertMsgFailed(("PGMIsValidAccess: invalid access type %08x\n", fAccess));
561 return VERR_INVALID_PARAMETER;
562 }
563
564 uint64_t fPage;
565 int rc = PGMGstGetPage(pVCpu, (RTGCPTR)Addr, &fPage, NULL);
566 if (RT_FAILURE(rc))
567 {
568 Log(("PGMIsValidAccess: access violation for %RGv rc=%d\n", Addr, rc));
569 return VINF_EM_RAW_GUEST_TRAP;
570 }
571
572 /*
573 * Check if the access would cause a page fault
574 *
575 * Note that hypervisor page directories are not present in the guest's tables, so this check
576 * is sufficient.
577 */
578 bool fWrite = !!(fAccess & X86_PTE_RW);
579 bool fUser = !!(fAccess & X86_PTE_US);
580 if ( !(fPage & X86_PTE_P)
581 || (fWrite && !(fPage & X86_PTE_RW))
582 || (fUser && !(fPage & X86_PTE_US)) )
583 {
584 Log(("PGMIsValidAccess: access violation for %RGv attr %#llx vs %d:%d\n", Addr, fPage, fWrite, fUser));
585 return VINF_EM_RAW_GUEST_TRAP;
586 }
587 if ( RT_SUCCESS(rc)
588 && PAGE_ADDRESS(Addr) != PAGE_ADDRESS(Addr + cbSize))
589 return PGMIsValidAccess(pVCpu, Addr + PAGE_SIZE, (cbSize > PAGE_SIZE) ? cbSize - PAGE_SIZE : 1, fAccess);
590 return rc;
591}
592
593
594/**
595 * Verifies a range of pages for read or write access
596 *
597 * Supports handling of pages marked for dirty bit tracking and CSAM
598 *
599 * @returns VBox status code.
600 * @param pVCpu VMCPU handle.
601 * @param Addr Guest virtual address to check
602 * @param cbSize Access size
603 * @param fAccess Access type (r/w, user/supervisor (X86_PTE_*))
604 */
605VMMDECL(int) PGMVerifyAccess(PVMCPU pVCpu, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess)
606{
607 PVM pVM = pVCpu->CTX_SUFF(pVM);
608
609 AssertMsg(!(fAccess & ~(X86_PTE_US | X86_PTE_RW)), ("PGMVerifyAccess: invalid access type %08x\n", fAccess));
610
611 /*
612 * Get going.
613 */
614 uint64_t fPageGst;
615 int rc = PGMGstGetPage(pVCpu, (RTGCPTR)Addr, &fPageGst, NULL);
616 if (RT_FAILURE(rc))
617 {
618 Log(("PGMVerifyAccess: access violation for %RGv rc=%d\n", Addr, rc));
619 return VINF_EM_RAW_GUEST_TRAP;
620 }
621
622 /*
623 * Check if the access would cause a page fault
624 *
625 * Note that hypervisor page directories are not present in the guest's tables, so this check
626 * is sufficient.
627 */
628 const bool fWrite = !!(fAccess & X86_PTE_RW);
629 const bool fUser = !!(fAccess & X86_PTE_US);
630 if ( !(fPageGst & X86_PTE_P)
631 || (fWrite && !(fPageGst & X86_PTE_RW))
632 || (fUser && !(fPageGst & X86_PTE_US)) )
633 {
634 Log(("PGMVerifyAccess: access violation for %RGv attr %#llx vs %d:%d\n", Addr, fPageGst, fWrite, fUser));
635 return VINF_EM_RAW_GUEST_TRAP;
636 }
637
638 if (!pVM->pgm.s.fNestedPaging)
639 {
640 /*
641 * Next step is to verify if we protected this page for dirty bit tracking or for CSAM scanning
642 */
643 rc = PGMShwGetPage(pVCpu, (RTGCPTR)Addr, NULL, NULL);
644 if ( rc == VERR_PAGE_NOT_PRESENT
645 || rc == VERR_PAGE_TABLE_NOT_PRESENT)
646 {
647 /*
648 * Page is not present in our page tables.
649 * Try to sync it!
650 */
651 Assert(X86_TRAP_PF_RW == X86_PTE_RW && X86_TRAP_PF_US == X86_PTE_US);
652 uint32_t uErr = fAccess & (X86_TRAP_PF_RW | X86_TRAP_PF_US);
653 rc = PGM_BTH_PFN(VerifyAccessSyncPage, pVCpu)(pVCpu, Addr, fPageGst, uErr);
654 if (rc != VINF_SUCCESS)
655 return rc;
656 }
657 else
658 AssertMsg(rc == VINF_SUCCESS, ("PGMShwGetPage %RGv failed with %Rrc\n", Addr, rc));
659 }
660
661#if 0 /* def VBOX_STRICT; triggers too often now */
662 /*
663 * This check is a bit paranoid, but useful.
664 */
665 /* Note! This will assert when writing to monitored pages (a bit annoying actually). */
666 uint64_t fPageShw;
667 rc = PGMShwGetPage(pVCpu, (RTGCPTR)Addr, &fPageShw, NULL);
668 if ( (rc == VERR_PAGE_NOT_PRESENT || RT_FAILURE(rc))
669 || (fWrite && !(fPageShw & X86_PTE_RW))
670 || (fUser && !(fPageShw & X86_PTE_US)) )
671 {
672 AssertMsgFailed(("Unexpected access violation for %RGv! rc=%Rrc write=%d user=%d\n",
673 Addr, rc, fWrite && !(fPageShw & X86_PTE_RW), fUser && !(fPageShw & X86_PTE_US)));
674 return VINF_EM_RAW_GUEST_TRAP;
675 }
676#endif
677
678 if ( RT_SUCCESS(rc)
679 && ( PAGE_ADDRESS(Addr) != PAGE_ADDRESS(Addr + cbSize - 1)
680 || Addr + cbSize < Addr))
681 {
682 /* Don't recursively call PGMVerifyAccess as we might run out of stack. */
683 for (;;)
684 {
685 Addr += PAGE_SIZE;
686 if (cbSize > PAGE_SIZE)
687 cbSize -= PAGE_SIZE;
688 else
689 cbSize = 1;
690 rc = PGMVerifyAccess(pVCpu, Addr, 1, fAccess);
691 if (rc != VINF_SUCCESS)
692 break;
693 if (PAGE_ADDRESS(Addr) == PAGE_ADDRESS(Addr + cbSize - 1))
694 break;
695 }
696 }
697 return rc;
698}
699
700
701/**
702 * Emulation of the invlpg instruction (HC only actually).
703 *
704 * @returns Strict VBox status code, special care required.
705 * @retval VINF_PGM_SYNC_CR3 - handled.
706 * @retval VINF_EM_RAW_EMULATE_INSTR - not handled (RC only).
707 * @retval VERR_REM_FLUSHED_PAGES_OVERFLOW - not handled.
708 *
709 * @param pVCpu VMCPU handle.
710 * @param GCPtrPage Page to invalidate.
711 *
712 * @remark ASSUMES the page table entry or page directory is valid. Fairly
713 * safe, but there could be edge cases!
714 *
715 * @todo Flush page or page directory only if necessary!
716 * @todo VBOXSTRICTRC
717 */
718VMMDECL(int) PGMInvalidatePage(PVMCPU pVCpu, RTGCPTR GCPtrPage)
719{
720 PVM pVM = pVCpu->CTX_SUFF(pVM);
721 int rc;
722 Log3(("PGMInvalidatePage: GCPtrPage=%RGv\n", GCPtrPage));
723
724#ifndef IN_RING3
725 /*
726 * Notify the recompiler so it can record this instruction.
727 */
728 REMNotifyInvalidatePage(pVM, GCPtrPage);
729#endif /* !IN_RING3 */
730
731
732#ifdef IN_RC
733 /*
734 * Check for conflicts and pending CR3 monitoring updates.
735 */
736 if (pgmMapAreMappingsFloating(&pVM->pgm.s))
737 {
738 if ( pgmGetMapping(pVM, GCPtrPage)
739 && PGMGstGetPage(pVCpu, GCPtrPage, NULL, NULL) != VERR_PAGE_TABLE_NOT_PRESENT)
740 {
741 LogFlow(("PGMGCInvalidatePage: Conflict!\n"));
742 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
743 STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatRCInvlPgConflict);
744 return VINF_PGM_SYNC_CR3;
745 }
746
747 if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
748 {
749 LogFlow(("PGMGCInvalidatePage: PGM_SYNC_MONITOR_CR3 -> reinterpret instruction in R3\n"));
750 STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatRCInvlPgSyncMonCR3);
751 return VINF_EM_RAW_EMULATE_INSTR;
752 }
753 }
754#endif /* IN_RC */
755
756 /*
757 * Call paging mode specific worker.
758 */
759 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePage), a);
760 pgmLock(pVM);
761 rc = PGM_BTH_PFN(InvalidatePage, pVCpu)(pVCpu, GCPtrPage);
762 pgmUnlock(pVM);
763 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePage), a);
764
765 /* Invalidate the TLB entry; might already be done by InvalidatePage (@todo) */
766 PGM_INVL_PG(pVCpu, GCPtrPage);
767
768#ifdef IN_RING3
769 /*
770 * Check if we have a pending update of the CR3 monitoring.
771 */
772 if ( RT_SUCCESS(rc)
773 && (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3))
774 {
775 pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
776 Assert(!pVM->pgm.s.fMappingsFixed); Assert(!pVM->pgm.s.fMappingsDisabled);
777 }
778
779 /*
780 * Inform CSAM about the flush
781 *
782 * Note: This is to check if monitored pages have been changed; when we implement
783 * callbacks for virtual handlers, this is no longer required.
784 */
785 CSAMR3FlushPage(pVM, GCPtrPage);
786#endif /* IN_RING3 */
787
788 /* Ignore all irrelevant error codes. */
789 if ( rc == VERR_PAGE_NOT_PRESENT
790 || rc == VERR_PAGE_TABLE_NOT_PRESENT
791 || rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT
792 || rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT)
793 rc = VINF_SUCCESS;
794
795 return rc;
796}
797
798
799/**
800 * Executes an instruction using the interpreter.
801 *
802 * @returns VBox status code (appropriate for trap handling and GC return).
803 * @param pVM VM handle.
804 * @param pVCpu VMCPU handle.
805 * @param pRegFrame Register frame.
806 * @param pvFault Fault address.
807 */
808VMMDECL(VBOXSTRICTRC) PGMInterpretInstruction(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
809{
810 uint32_t cb;
811 VBOXSTRICTRC rc = EMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault, &cb);
812 if (rc == VERR_EM_INTERPRETER)
813 rc = VINF_EM_RAW_EMULATE_INSTR;
814 if (rc != VINF_SUCCESS)
815 Log(("PGMInterpretInstruction: returns %Rrc (pvFault=%RGv)\n", VBOXSTRICTRC_VAL(rc), pvFault));
816 return rc;
817}
818
819
820/**
821 * Gets effective page information (from the VMM page directory).
822 *
823 * @returns VBox status.
824 * @param pVCpu VMCPU handle.
825 * @param GCPtr Guest Context virtual address of the page.
826 * @param pfFlags Where to store the flags. These are X86_PTE_*.
827 * @param pHCPhys Where to store the HC physical address of the page.
828 * This is page aligned.
829 * @remark You should use PGMMapGetPage() for pages in a mapping.
830 */
831VMMDECL(int) PGMShwGetPage(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys)
832{
833 pgmLock(pVCpu->CTX_SUFF(pVM));
834 int rc = PGM_SHW_PFN(GetPage, pVCpu)(pVCpu, GCPtr, pfFlags, pHCPhys);
835 pgmUnlock(pVCpu->CTX_SUFF(pVM));
836 return rc;
837}
838
839
840/**
841 * Modify page flags for a range of pages in the shadow context.
842 *
843 * The existing flags are ANDed with the fMask and ORed with the fFlags.
844 *
845 * @returns VBox status code.
846 * @param pVCpu VMCPU handle.
847 * @param GCPtr Virtual address of the first page in the range.
848 * @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
849 * @param fMask The AND mask - page flags X86_PTE_*.
850 * Be very CAREFUL when ~'ing constants which could be 32-bit!
851 * @param fOpFlags A combination of the PGM_MK_PK_XXX flags.
852 * @remark You must use PGMMapModifyPage() for pages in a mapping.
853 */
854DECLINLINE(int) pdmShwModifyPage(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags)
855{
856 AssertMsg(!(fFlags & X86_PTE_PAE_PG_MASK_FULL), ("fFlags=%#llx\n", fFlags));
857 Assert(!(fOpFlags & ~(PGM_MK_PG_IS_MMIO2 | PGM_MK_PG_IS_WRITE_FAULT)));
858
859 GCPtr &= PAGE_BASE_GC_MASK; /** @todo this ain't necessary, right... */
860
861 PVM pVM = pVCpu->CTX_SUFF(pVM);
862 pgmLock(pVM);
863 int rc = PGM_SHW_PFN(ModifyPage, pVCpu)(pVCpu, GCPtr, PAGE_SIZE, fFlags, fMask, fOpFlags);
864 pgmUnlock(pVM);
865 return rc;
866}
867
868
869/**
870 * Changing the page flags for a single page in the shadow page tables so as to
871 * make it read-only.
872 *
873 * @returns VBox status code.
874 * @param pVCpu VMCPU handle.
875 * @param GCPtr Virtual address of the first page in the range.
876 * @param fOpFlags A combination of the PGM_MK_PK_XXX flags.
877 */
878VMMDECL(int) PGMShwMakePageReadonly(PVMCPU pVCpu, RTGCPTR GCPtr, uint32_t fOpFlags)
879{
880 return pdmShwModifyPage(pVCpu, GCPtr, 0, ~(uint64_t)X86_PTE_RW, fOpFlags);
881}
882
883
884/**
885 * Changing the page flags for a single page in the shadow page tables so as to
886 * make it writable.
887 *
888 * The call must know with 101% certainty that the guest page tables maps this
889 * as writable too. This function will deal shared, zero and write monitored
890 * pages.
891 *
892 * @returns VBox status code.
893 * @param pVCpu VMCPU handle.
894 * @param GCPtr Virtual address of the first page in the range.
895 * @param fMmio2 Set if it is an MMIO2 page.
896 * @param fOpFlags A combination of the PGM_MK_PK_XXX flags.
897 */
898VMMDECL(int) PGMShwMakePageWritable(PVMCPU pVCpu, RTGCPTR GCPtr, uint32_t fOpFlags)
899{
900 return pdmShwModifyPage(pVCpu, GCPtr, X86_PTE_RW, ~(uint64_t)0, fOpFlags);
901}
902
903
904/**
905 * Changing the page flags for a single page in the shadow page tables so as to
906 * make it not present.
907 *
908 * @returns VBox status code.
909 * @param pVCpu VMCPU handle.
910 * @param GCPtr Virtual address of the first page in the range.
911 * @param fOpFlags A combination of the PGM_MK_PG_XXX flags.
912 */
913VMMDECL(int) PGMShwMakePageNotPresent(PVMCPU pVCpu, RTGCPTR GCPtr, uint32_t fOpFlags)
914{
915 return pdmShwModifyPage(pVCpu, GCPtr, 0, 0, fOpFlags);
916}
917
918
919/**
920 * Gets the shadow page directory for the specified address, PAE.
921 *
922 * @returns Pointer to the shadow PD.
923 * @param pVCpu The VMCPU handle.
924 * @param GCPtr The address.
925 * @param uGstPdpe Guest PDPT entry.
926 * @param ppPD Receives address of page directory
927 */
928int pgmShwSyncPaePDPtr(PVMCPU pVCpu, RTGCPTR GCPtr, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD)
929{
930 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
931 PX86PDPT pPdpt = pgmShwGetPaePDPTPtr(pVCpu);
932 PX86PDPE pPdpe = &pPdpt->a[iPdPt];
933 PVM pVM = pVCpu->CTX_SUFF(pVM);
934 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
935 PPGMPOOLPAGE pShwPage;
936 int rc;
937
938 Assert(PGMIsLockOwner(pVM));
939
940 /* Allocate page directory if not present. */
941 if ( !pPdpe->n.u1Present
942 && !(pPdpe->u & X86_PDPE_PG_MASK))
943 {
944 RTGCPTR64 GCPdPt;
945 PGMPOOLKIND enmKind;
946
947 if (pVM->pgm.s.fNestedPaging || !CPUMIsGuestPagingEnabled(pVCpu))
948 {
949 /* AMD-V nested paging or real/protected mode without paging. */
950 GCPdPt = (RTGCPTR64)iPdPt << X86_PDPT_SHIFT;
951 enmKind = PGMPOOLKIND_PAE_PD_PHYS;
952 }
953 else
954 {
955 if (CPUMGetGuestCR4(pVCpu) & X86_CR4_PAE)
956 {
957 if (!(uGstPdpe & X86_PDPE_P))
958 {
959 /* PD not present; guest must reload CR3 to change it.
960 * No need to monitor anything in this case.
961 */
962 Assert(!HWACCMIsEnabled(pVM));
963
964 GCPdPt = uGstPdpe & X86_PDPE_PG_MASK_FULL;
965 enmKind = PGMPOOLKIND_PAE_PD_PHYS;
966 uGstPdpe |= X86_PDPE_P;
967 }
968 else
969 {
970 GCPdPt = uGstPdpe & X86_PDPE_PG_MASK_FULL;
971 enmKind = PGMPOOLKIND_PAE_PD_FOR_PAE_PD;
972 }
973 }
974 else
975 {
976 GCPdPt = CPUMGetGuestCR3(pVCpu);
977 enmKind = (PGMPOOLKIND)(PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD + iPdPt);
978 }
979 }
980
981 /* Create a reference back to the PDPT by using the index in its shadow page. */
982 rc = pgmPoolAlloc(pVM, GCPdPt, enmKind, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPdPt, &pShwPage);
983 AssertRCReturn(rc, rc);
984
985 /* The PD was cached or created; hook it up now. */
986 pPdpe->u |= pShwPage->Core.Key
987 | (uGstPdpe & ~(X86_PDPE_PG_MASK_FULL | X86_PDPE_AVL_MASK | X86_PDPE_PCD | X86_PDPE_PWT));
988
989# if defined(IN_RC)
990 /*
991 * In 32 bits PAE mode we *must* invalidate the TLB when changing a
992 * PDPT entry; the CPU fetches them only during cr3 load, so any
993 * non-present PDPT will continue to cause page faults.
994 */
995 ASMReloadCR3();
996# endif
997 PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdpe);
998 }
999 else
1000 {
1001 pShwPage = pgmPoolGetPage(pPool, pPdpe->u & X86_PDPE_PG_MASK);
1002 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1003 Assert((pPdpe->u & X86_PDPE_PG_MASK) == pShwPage->Core.Key);
1004
1005 pgmPoolCacheUsed(pPool, pShwPage);
1006 }
1007 *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1008 return VINF_SUCCESS;
1009}
1010
1011
1012/**
1013 * Gets the pointer to the shadow page directory entry for an address, PAE.
1014 *
1015 * @returns Pointer to the PDE.
1016 * @param pVCpu The current CPU.
1017 * @param GCPtr The address.
1018 * @param ppShwPde Receives the address of the pgm pool page for the shadow page directory
1019 */
1020DECLINLINE(int) pgmShwGetPaePoolPagePD(PVMCPU pVCpu, RTGCPTR GCPtr, PPGMPOOLPAGE *ppShwPde)
1021{
1022 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
1023 PX86PDPT pPdpt = pgmShwGetPaePDPTPtr(pVCpu);
1024 PVM pVM = pVCpu->CTX_SUFF(pVM);
1025
1026 Assert(PGMIsLockOwner(pVM));
1027
1028 AssertReturn(pPdpt, VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT); /* can't happen */
1029 if (!pPdpt->a[iPdPt].n.u1Present)
1030 {
1031 LogFlow(("pgmShwGetPaePoolPagePD: PD %d not present (%RX64)\n", iPdPt, pPdpt->a[iPdPt].u));
1032 return VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT;
1033 }
1034 AssertMsg(pPdpt->a[iPdPt].u & X86_PDPE_PG_MASK, ("GCPtr=%RGv\n", GCPtr));
1035
1036 /* Fetch the pgm pool shadow descriptor. */
1037 PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pVM->pgm.s.CTX_SUFF(pPool), pPdpt->a[iPdPt].u & X86_PDPE_PG_MASK);
1038 AssertReturn(pShwPde, VERR_INTERNAL_ERROR);
1039
1040 *ppShwPde = pShwPde;
1041 return VINF_SUCCESS;
1042}
1043
1044#ifndef IN_RC
1045
1046/**
1047 * Syncs the SHADOW page directory pointer for the specified address.
1048 *
1049 * Allocates backing pages in case the PDPT or PML4 entry is missing.
1050 *
1051 * The caller is responsible for making sure the guest has a valid PD before
1052 * calling this function.
1053 *
1054 * @returns VBox status.
1055 * @param pVCpu VMCPU handle.
1056 * @param GCPtr The address.
1057 * @param uGstPml4e Guest PML4 entry (valid).
1058 * @param uGstPdpe Guest PDPT entry (valid).
1059 * @param ppPD Receives address of page directory
1060 */
1061static int pgmShwSyncLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, X86PGPAEUINT uGstPml4e, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD)
1062{
1063 PPGMCPU pPGM = &pVCpu->pgm.s;
1064 PVM pVM = pVCpu->CTX_SUFF(pVM);
1065 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1066 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
1067 PX86PML4E pPml4e = pgmShwGetLongModePML4EPtr(pVCpu, iPml4);
1068 bool fNestedPagingOrNoGstPaging = pVM->pgm.s.fNestedPaging || !CPUMIsGuestPagingEnabled(pVCpu);
1069 PPGMPOOLPAGE pShwPage;
1070 int rc;
1071
1072 Assert(PGMIsLockOwner(pVM));
1073
1074 /* Allocate page directory pointer table if not present. */
1075 if ( !pPml4e->n.u1Present
1076 && !(pPml4e->u & X86_PML4E_PG_MASK))
1077 {
1078 RTGCPTR64 GCPml4;
1079 PGMPOOLKIND enmKind;
1080
1081 Assert(pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
1082
1083 if (fNestedPagingOrNoGstPaging)
1084 {
1085 /* AMD-V nested paging or real/protected mode without paging */
1086 GCPml4 = (RTGCPTR64)iPml4 << X86_PML4_SHIFT;
1087 enmKind = PGMPOOLKIND_64BIT_PDPT_FOR_PHYS;
1088 }
1089 else
1090 {
1091 GCPml4 = uGstPml4e & X86_PML4E_PG_MASK_FULL;
1092 enmKind = PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT;
1093 }
1094
1095 /* Create a reference back to the PDPT by using the index in its shadow page. */
1096 rc = pgmPoolAlloc(pVM, GCPml4, enmKind, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPml4, &pShwPage);
1097 AssertRCReturn(rc, rc);
1098 }
1099 else
1100 {
1101 pShwPage = pgmPoolGetPage(pPool, pPml4e->u & X86_PML4E_PG_MASK);
1102 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1103
1104 pgmPoolCacheUsed(pPool, pShwPage);
1105 }
1106 /* The PDPT was cached or created; hook it up now. */
1107 pPml4e->u |= pShwPage->Core.Key | (uGstPml4e & pVCpu->pgm.s.fGstAmd64ShadowedPml4eMask);
1108
1109 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1110 PX86PDPT pPdpt = (PX86PDPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1111 PX86PDPE pPdpe = &pPdpt->a[iPdPt];
1112
1113 /* Allocate page directory if not present. */
1114 if ( !pPdpe->n.u1Present
1115 && !(pPdpe->u & X86_PDPE_PG_MASK))
1116 {
1117 RTGCPTR64 GCPdPt;
1118 PGMPOOLKIND enmKind;
1119
1120 if (fNestedPagingOrNoGstPaging)
1121 {
1122 /* AMD-V nested paging or real/protected mode without paging */
1123 GCPdPt = (RTGCPTR64)iPdPt << X86_PDPT_SHIFT;
1124 enmKind = PGMPOOLKIND_64BIT_PD_FOR_PHYS;
1125 }
1126 else
1127 {
1128 GCPdPt = uGstPdpe & X86_PDPE_PG_MASK_FULL;
1129 enmKind = PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD;
1130 }
1131
1132 /* Create a reference back to the PDPT by using the index in its shadow page. */
1133 rc = pgmPoolAlloc(pVM, GCPdPt, enmKind, pShwPage->idx, iPdPt, &pShwPage);
1134 AssertRCReturn(rc, rc);
1135 }
1136 else
1137 {
1138 pShwPage = pgmPoolGetPage(pPool, pPdpe->u & X86_PDPE_PG_MASK);
1139 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1140
1141 pgmPoolCacheUsed(pPool, pShwPage);
1142 }
1143 /* The PD was cached or created; hook it up now. */
1144 pPdpe->u |= pShwPage->Core.Key | (uGstPdpe & pVCpu->pgm.s.fGstAmd64ShadowedPdpeMask);
1145
1146 *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1147 return VINF_SUCCESS;
1148}
1149
1150
1151/**
1152 * Gets the SHADOW page directory pointer for the specified address (long mode).
1153 *
1154 * @returns VBox status.
1155 * @param pVCpu VMCPU handle.
1156 * @param GCPtr The address.
1157 * @param ppPdpt Receives address of pdpt
1158 * @param ppPD Receives address of page directory
1159 */
1160DECLINLINE(int) pgmShwGetLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPT *ppPdpt, PX86PDPAE *ppPD)
1161{
1162 PPGMCPU pPGM = &pVCpu->pgm.s;
1163 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
1164 PCX86PML4E pPml4e = pgmShwGetLongModePML4EPtr(pVCpu, iPml4);
1165
1166 Assert(PGMIsLockOwner(PGMCPU2VM(pPGM)));
1167
1168 AssertReturn(pPml4e, VERR_INTERNAL_ERROR);
1169 if (ppPml4e)
1170 *ppPml4e = (PX86PML4E)pPml4e;
1171
1172 Log4(("pgmShwGetLongModePDPtr %RGv (%RHv) %RX64\n", GCPtr, pPml4e, pPml4e->u));
1173
1174 if (!pPml4e->n.u1Present)
1175 return VERR_PAGE_MAP_LEVEL4_NOT_PRESENT;
1176
1177 PVM pVM = pVCpu->CTX_SUFF(pVM);
1178 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1179 PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPml4e->u & X86_PML4E_PG_MASK);
1180 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1181
1182 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1183 PCX86PDPT pPdpt = *ppPdpt = (PX86PDPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1184 if (!pPdpt->a[iPdPt].n.u1Present)
1185 return VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT;
1186
1187 pShwPage = pgmPoolGetPage(pPool, pPdpt->a[iPdPt].u & X86_PDPE_PG_MASK);
1188 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1189
1190 *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1191 Log4(("pgmShwGetLongModePDPtr %RGv -> *ppPD=%p PDE=%p/%RX64\n", GCPtr, *ppPD, &(*ppPD)->a[(GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK], (*ppPD)->a[(GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK].u));
1192 return VINF_SUCCESS;
1193}
1194
1195
1196/**
1197 * Syncs the SHADOW EPT page directory pointer for the specified address. Allocates
1198 * backing pages in case the PDPT or PML4 entry is missing.
1199 *
1200 * @returns VBox status.
1201 * @param pVCpu VMCPU handle.
1202 * @param GCPtr The address.
1203 * @param ppPdpt Receives address of pdpt
1204 * @param ppPD Receives address of page directory
1205 */
1206static int pgmShwGetEPTPDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PEPTPDPT *ppPdpt, PEPTPD *ppPD)
1207{
1208 PVM pVM = pVCpu->CTX_SUFF(pVM);
1209 const unsigned iPml4 = (GCPtr >> EPT_PML4_SHIFT) & EPT_PML4_MASK;
1210 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1211 PEPTPML4 pPml4;
1212 PEPTPML4E pPml4e;
1213 PPGMPOOLPAGE pShwPage;
1214 int rc;
1215
1216 Assert(pVM->pgm.s.fNestedPaging);
1217 Assert(PGMIsLockOwner(pVM));
1218
1219 pPml4 = (PEPTPML4)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
1220 Assert(pPml4);
1221
1222 /* Allocate page directory pointer table if not present. */
1223 pPml4e = &pPml4->a[iPml4];
1224 if ( !pPml4e->n.u1Present
1225 && !(pPml4e->u & EPT_PML4E_PG_MASK))
1226 {
1227 Assert(!(pPml4e->u & EPT_PML4E_PG_MASK));
1228 RTGCPTR64 GCPml4 = (RTGCPTR64)iPml4 << EPT_PML4_SHIFT;
1229
1230 rc = pgmPoolAlloc(pVM, GCPml4, PGMPOOLKIND_EPT_PDPT_FOR_PHYS, PGMPOOL_IDX_NESTED_ROOT, iPml4, &pShwPage);
1231 AssertRCReturn(rc, rc);
1232 }
1233 else
1234 {
1235 pShwPage = pgmPoolGetPage(pPool, pPml4e->u & EPT_PML4E_PG_MASK);
1236 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1237
1238 pgmPoolCacheUsed(pPool, pShwPage);
1239 }
1240 /* The PDPT was cached or created; hook it up now and fill with the default value. */
1241 pPml4e->u = pShwPage->Core.Key;
1242 pPml4e->n.u1Present = 1;
1243 pPml4e->n.u1Write = 1;
1244 pPml4e->n.u1Execute = 1;
1245
1246 const unsigned iPdPt = (GCPtr >> EPT_PDPT_SHIFT) & EPT_PDPT_MASK;
1247 PEPTPDPT pPdpt = (PEPTPDPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1248 PEPTPDPTE pPdpe = &pPdpt->a[iPdPt];
1249
1250 if (ppPdpt)
1251 *ppPdpt = pPdpt;
1252
1253 /* Allocate page directory if not present. */
1254 if ( !pPdpe->n.u1Present
1255 && !(pPdpe->u & EPT_PDPTE_PG_MASK))
1256 {
1257 RTGCPTR64 GCPdPt = (RTGCPTR64)iPdPt << EPT_PDPT_SHIFT;
1258
1259 rc = pgmPoolAlloc(pVM, GCPdPt, PGMPOOLKIND_64BIT_PD_FOR_PHYS, pShwPage->idx, iPdPt, &pShwPage);
1260 AssertRCReturn(rc, rc);
1261 }
1262 else
1263 {
1264 pShwPage = pgmPoolGetPage(pPool, pPdpe->u & EPT_PDPTE_PG_MASK);
1265 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1266
1267 pgmPoolCacheUsed(pPool, pShwPage);
1268 }
1269 /* The PD was cached or created; hook it up now and fill with the default value. */
1270 pPdpe->u = pShwPage->Core.Key;
1271 pPdpe->n.u1Present = 1;
1272 pPdpe->n.u1Write = 1;
1273 pPdpe->n.u1Execute = 1;
1274
1275 *ppPD = (PEPTPD)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1276 return VINF_SUCCESS;
1277}
1278
1279#endif /* IN_RC */
1280
1281#ifdef IN_RING0
1282/**
1283 * Synchronizes a range of nested page table entries.
1284 *
1285 * The caller must own the PGM lock.
1286 *
1287 * @param pVCpu The current CPU.
1288 * @param GCPhys Where to start.
1289 * @param cPages How many pages which entries should be synced.
1290 * @param enmShwPagingMode The shadow paging mode (PGMMODE_EPT for VT-x,
1291 * host paging mode for AMD-V).
1292 */
1293int pgmShwSyncNestedPageLocked(PVMCPU pVCpu, RTGCPHYS GCPhysFault, uint32_t cPages, PGMMODE enmShwPagingMode)
1294{
1295 Assert(PGMIsLockOwner(pVCpu->CTX_SUFF(pVM)));
1296
1297 int rc;
1298 switch (enmShwPagingMode)
1299 {
1300 case PGMMODE_32_BIT:
1301 {
1302 X86PDE PdeDummy = { X86_PDE_P | X86_PDE_US | X86_PDE_RW | X86_PDE_A };
1303 rc = PGM_BTH_NAME_32BIT_PROT(SyncPage)(pVCpu, PdeDummy, GCPhysFault, cPages, ~0U /*uErr*/);
1304 break;
1305 }
1306
1307 case PGMMODE_PAE:
1308 case PGMMODE_PAE_NX:
1309 {
1310 X86PDEPAE PdeDummy = { X86_PDE_P | X86_PDE_US | X86_PDE_RW | X86_PDE_A };
1311 rc = PGM_BTH_NAME_PAE_PROT(SyncPage)(pVCpu, PdeDummy, GCPhysFault, cPages, ~0U /*uErr*/);
1312 break;
1313 }
1314
1315 case PGMMODE_AMD64:
1316 case PGMMODE_AMD64_NX:
1317 {
1318 X86PDEPAE PdeDummy = { X86_PDE_P | X86_PDE_US | X86_PDE_RW | X86_PDE_A };
1319 rc = PGM_BTH_NAME_AMD64_PROT(SyncPage)(pVCpu, PdeDummy, GCPhysFault, cPages, ~0U /*uErr*/);
1320 break;
1321 }
1322
1323 case PGMMODE_EPT:
1324 {
1325 X86PDEPAE PdeDummy = { X86_PDE_P | X86_PDE_US | X86_PDE_RW | X86_PDE_A };
1326 rc = PGM_BTH_NAME_EPT_PROT(SyncPage)(pVCpu, PdeDummy, GCPhysFault, cPages, ~0U /*uErr*/);
1327 break;
1328 }
1329
1330 default:
1331 AssertMsgFailedReturn(("%d\n", enmShwPagingMode), VERR_INTERNAL_ERROR_5);
1332 }
1333 return rc;
1334}
1335#endif /* IN_RING0 */
1336
1337
1338/**
1339 * Gets effective Guest OS page information.
1340 *
1341 * When GCPtr is in a big page, the function will return as if it was a normal
1342 * 4KB page. If the need for distinguishing between big and normal page becomes
1343 * necessary at a later point, a PGMGstGetPage() will be created for that
1344 * purpose.
1345 *
1346 * @returns VBox status.
1347 * @param pVCpu VMCPU handle.
1348 * @param GCPtr Guest Context virtual address of the page.
1349 * @param pfFlags Where to store the flags. These are X86_PTE_*, even for big pages.
1350 * @param pGCPhys Where to store the GC physical address of the page.
1351 * This is page aligned. The fact that the
1352 */
1353VMMDECL(int) PGMGstGetPage(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys)
1354{
1355 return PGM_GST_PFN(GetPage, pVCpu)(pVCpu, GCPtr, pfFlags, pGCPhys);
1356}
1357
1358
1359/**
1360 * Checks if the page is present.
1361 *
1362 * @returns true if the page is present.
1363 * @returns false if the page is not present.
1364 * @param pVCpu VMCPU handle.
1365 * @param GCPtr Address within the page.
1366 */
1367VMMDECL(bool) PGMGstIsPagePresent(PVMCPU pVCpu, RTGCPTR GCPtr)
1368{
1369 int rc = PGMGstGetPage(pVCpu, GCPtr, NULL, NULL);
1370 return RT_SUCCESS(rc);
1371}
1372
1373
1374/**
1375 * Sets (replaces) the page flags for a range of pages in the guest's tables.
1376 *
1377 * @returns VBox status.
1378 * @param pVCpu VMCPU handle.
1379 * @param GCPtr The address of the first page.
1380 * @param cb The size of the range in bytes.
1381 * @param fFlags Page flags X86_PTE_*, excluding the page mask of course.
1382 */
1383VMMDECL(int) PGMGstSetPage(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags)
1384{
1385 return PGMGstModifyPage(pVCpu, GCPtr, cb, fFlags, 0);
1386}
1387
1388
1389/**
1390 * Modify page flags for a range of pages in the guest's tables
1391 *
1392 * The existing flags are ANDed with the fMask and ORed with the fFlags.
1393 *
1394 * @returns VBox status code.
1395 * @param pVCpu VMCPU handle.
1396 * @param GCPtr Virtual address of the first page in the range.
1397 * @param cb Size (in bytes) of the range to apply the modification to.
1398 * @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
1399 * @param fMask The AND mask - page flags X86_PTE_*, excluding the page mask of course.
1400 * Be very CAREFUL when ~'ing constants which could be 32-bit!
1401 */
1402VMMDECL(int) PGMGstModifyPage(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
1403{
1404 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,GstModifyPage), a);
1405
1406 /*
1407 * Validate input.
1408 */
1409 AssertMsg(!(fFlags & X86_PTE_PAE_PG_MASK_FULL), ("fFlags=%#llx\n", fFlags));
1410 Assert(cb);
1411
1412 LogFlow(("PGMGstModifyPage %RGv %d bytes fFlags=%08llx fMask=%08llx\n", GCPtr, cb, fFlags, fMask));
1413
1414 /*
1415 * Adjust input.
1416 */
1417 cb += GCPtr & PAGE_OFFSET_MASK;
1418 cb = RT_ALIGN_Z(cb, PAGE_SIZE);
1419 GCPtr = (GCPtr & PAGE_BASE_GC_MASK);
1420
1421 /*
1422 * Call worker.
1423 */
1424 int rc = PGM_GST_PFN(ModifyPage, pVCpu)(pVCpu, GCPtr, cb, fFlags, fMask);
1425
1426 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,GstModifyPage), a);
1427 return rc;
1428}
1429
1430
1431#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
1432
1433/**
1434 * Performs the lazy mapping of the 32-bit guest PD.
1435 *
1436 * @returns VBox status code.
1437 * @param pVCpu The current CPU.
1438 * @param ppPd Where to return the pointer to the mapping. This is
1439 * always set.
1440 */
1441int pgmGstLazyMap32BitPD(PVMCPU pVCpu, PX86PD *ppPd)
1442{
1443 PVM pVM = pVCpu->CTX_SUFF(pVM);
1444 pgmLock(pVM);
1445
1446 Assert(!pVCpu->pgm.s.CTX_SUFF(pGst32BitPd));
1447
1448 RTGCPHYS GCPhysCR3 = pVCpu->pgm.s.GCPhysCR3 & X86_CR3_PAGE_MASK;
1449 PPGMPAGE pPage;
1450 int rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhysCR3, &pPage);
1451 if (RT_SUCCESS(rc))
1452 {
1453 RTHCPTR HCPtrGuestCR3;
1454 rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhysCR3, (void **)&HCPtrGuestCR3);
1455 if (RT_SUCCESS(rc))
1456 {
1457 pVCpu->pgm.s.pGst32BitPdR3 = (R3PTRTYPE(PX86PD))HCPtrGuestCR3;
1458# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1459 pVCpu->pgm.s.pGst32BitPdR0 = (R0PTRTYPE(PX86PD))HCPtrGuestCR3;
1460# endif
1461 *ppPd = (PX86PD)HCPtrGuestCR3;
1462
1463 pgmUnlock(pVM);
1464 return VINF_SUCCESS;
1465 }
1466
1467 AssertRC(rc);
1468 }
1469 pgmUnlock(pVM);
1470
1471 *ppPd = NULL;
1472 return rc;
1473}
1474
1475
1476/**
1477 * Performs the lazy mapping of the PAE guest PDPT.
1478 *
1479 * @returns VBox status code.
1480 * @param pVCpu The current CPU.
1481 * @param ppPdpt Where to return the pointer to the mapping. This is
1482 * always set.
1483 */
1484int pgmGstLazyMapPaePDPT(PVMCPU pVCpu, PX86PDPT *ppPdpt)
1485{
1486 Assert(!pVCpu->pgm.s.CTX_SUFF(pGstPaePdpt));
1487 PVM pVM = pVCpu->CTX_SUFF(pVM);
1488 pgmLock(pVM);
1489
1490 RTGCPHYS GCPhysCR3 = pVCpu->pgm.s.GCPhysCR3 & X86_CR3_PAE_PAGE_MASK;
1491 PPGMPAGE pPage;
1492 int rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhysCR3, &pPage);
1493 if (RT_SUCCESS(rc))
1494 {
1495 RTHCPTR HCPtrGuestCR3;
1496 rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhysCR3, (void **)&HCPtrGuestCR3);
1497 if (RT_SUCCESS(rc))
1498 {
1499 pVCpu->pgm.s.pGstPaePdptR3 = (R3PTRTYPE(PX86PDPT))HCPtrGuestCR3;
1500# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1501 pVCpu->pgm.s.pGstPaePdptR0 = (R0PTRTYPE(PX86PDPT))HCPtrGuestCR3;
1502# endif
1503 *ppPdpt = (PX86PDPT)HCPtrGuestCR3;
1504
1505 pgmUnlock(pVM);
1506 return VINF_SUCCESS;
1507 }
1508
1509 AssertRC(rc);
1510 }
1511
1512 pgmUnlock(pVM);
1513 *ppPdpt = NULL;
1514 return rc;
1515}
1516
1517
1518/**
1519 * Performs the lazy mapping / updating of a PAE guest PD.
1520 *
1521 * @returns Pointer to the mapping.
1522 * @returns VBox status code.
1523 * @param pVCpu The current CPU.
1524 * @param iPdpt Which PD entry to map (0..3).
1525 * @param ppPd Where to return the pointer to the mapping. This is
1526 * always set.
1527 */
1528int pgmGstLazyMapPaePD(PVMCPU pVCpu, uint32_t iPdpt, PX86PDPAE *ppPd)
1529{
1530 PVM pVM = pVCpu->CTX_SUFF(pVM);
1531 pgmLock(pVM);
1532
1533 PX86PDPT pGuestPDPT = pVCpu->pgm.s.CTX_SUFF(pGstPaePdpt);
1534 Assert(pGuestPDPT);
1535 Assert(pGuestPDPT->a[iPdpt].n.u1Present);
1536 RTGCPHYS GCPhys = pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK_FULL;
1537 bool const fChanged = pVCpu->pgm.s.aGCPhysGstPaePDs[iPdpt] != GCPhys;
1538
1539 PPGMPAGE pPage;
1540 int rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
1541 if (RT_SUCCESS(rc))
1542 {
1543 RTRCPTR RCPtr = NIL_RTRCPTR;
1544 RTHCPTR HCPtr = NIL_RTHCPTR;
1545#if !defined(IN_RC) && !defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1546 rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, &HCPtr);
1547 AssertRC(rc);
1548#endif
1549 if (RT_SUCCESS(rc) && fChanged)
1550 {
1551 RCPtr = (RTRCPTR)(RTRCUINTPTR)(pVM->pgm.s.GCPtrCR3Mapping + (1 + iPdpt) * PAGE_SIZE);
1552 rc = PGMMap(pVM, (RTRCUINTPTR)RCPtr, PGM_PAGE_GET_HCPHYS(pPage), PAGE_SIZE, 0);
1553 }
1554 if (RT_SUCCESS(rc))
1555 {
1556 pVCpu->pgm.s.apGstPaePDsR3[iPdpt] = (R3PTRTYPE(PX86PDPAE))HCPtr;
1557# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1558 pVCpu->pgm.s.apGstPaePDsR0[iPdpt] = (R0PTRTYPE(PX86PDPAE))HCPtr;
1559# endif
1560 if (fChanged)
1561 {
1562 pVCpu->pgm.s.aGCPhysGstPaePDs[iPdpt] = GCPhys;
1563 pVCpu->pgm.s.apGstPaePDsRC[iPdpt] = (RCPTRTYPE(PX86PDPAE))RCPtr;
1564 }
1565
1566 *ppPd = pVCpu->pgm.s.CTX_SUFF(apGstPaePDs)[iPdpt];
1567 pgmUnlock(pVM);
1568 return VINF_SUCCESS;
1569 }
1570 }
1571
1572 /* Invalid page or some failure, invalidate the entry. */
1573 pVCpu->pgm.s.aGCPhysGstPaePDs[iPdpt] = NIL_RTGCPHYS;
1574 pVCpu->pgm.s.apGstPaePDsR3[iPdpt] = 0;
1575# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1576 pVCpu->pgm.s.apGstPaePDsR0[iPdpt] = 0;
1577# endif
1578 pVCpu->pgm.s.apGstPaePDsRC[iPdpt] = 0;
1579
1580 pgmUnlock(pVM);
1581 return rc;
1582}
1583
1584#endif /* !VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
1585#if !defined(IN_RC) && !defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1586/**
1587 * Performs the lazy mapping of the 32-bit guest PD.
1588 *
1589 * @returns VBox status code.
1590 * @param pVCpu The current CPU.
1591 * @param ppPml4 Where to return the pointer to the mapping. This will
1592 * always be set.
1593 */
1594int pgmGstLazyMapPml4(PVMCPU pVCpu, PX86PML4 *ppPml4)
1595{
1596 Assert(!pVCpu->pgm.s.CTX_SUFF(pGstAmd64Pml4));
1597 PVM pVM = pVCpu->CTX_SUFF(pVM);
1598 pgmLock(pVM);
1599
1600 RTGCPHYS GCPhysCR3 = pVCpu->pgm.s.GCPhysCR3 & X86_CR3_AMD64_PAGE_MASK;
1601 PPGMPAGE pPage;
1602 int rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhysCR3, &pPage);
1603 if (RT_SUCCESS(rc))
1604 {
1605 RTHCPTR HCPtrGuestCR3;
1606 rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhysCR3, (void **)&HCPtrGuestCR3);
1607 if (RT_SUCCESS(rc))
1608 {
1609 pVCpu->pgm.s.pGstAmd64Pml4R3 = (R3PTRTYPE(PX86PML4))HCPtrGuestCR3;
1610# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1611 pVCpu->pgm.s.pGstAmd64Pml4R0 = (R0PTRTYPE(PX86PML4))HCPtrGuestCR3;
1612# endif
1613 *ppPml4 = (PX86PML4)HCPtrGuestCR3;
1614
1615 pgmUnlock(pVM);
1616 return VINF_SUCCESS;
1617 }
1618 }
1619
1620 pgmUnlock(pVM);
1621 *ppPml4 = NULL;
1622 return rc;
1623}
1624#endif
1625
1626/**
1627 * Gets the specified page directory pointer table entry.
1628 *
1629 * @returns PDP entry
1630 * @param pVCpu VMCPU handle.
1631 * @param iPdpt PDPT index
1632 */
1633VMMDECL(X86PDPE) PGMGstGetPaePDPtr(PVMCPU pVCpu, unsigned iPdpt)
1634{
1635 Assert(iPdpt <= 3);
1636 return pgmGstGetPaePDPTPtr(pVCpu)->a[iPdpt & 3];
1637}
1638
1639
1640/**
1641 * Gets the current CR3 register value for the shadow memory context.
1642 * @returns CR3 value.
1643 * @param pVCpu VMCPU handle.
1644 */
1645VMMDECL(RTHCPHYS) PGMGetHyperCR3(PVMCPU pVCpu)
1646{
1647 PPGMPOOLPAGE pPoolPage = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
1648 AssertPtrReturn(pPoolPage, 0);
1649 return pPoolPage->Core.Key;
1650}
1651
1652
1653/**
1654 * Gets the current CR3 register value for the nested memory context.
1655 * @returns CR3 value.
1656 * @param pVCpu VMCPU handle.
1657 */
1658VMMDECL(RTHCPHYS) PGMGetNestedCR3(PVMCPU pVCpu, PGMMODE enmShadowMode)
1659{
1660 Assert(pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
1661 return pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->Core.Key;
1662}
1663
1664
1665/**
1666 * Gets the current CR3 register value for the HC intermediate memory context.
1667 * @returns CR3 value.
1668 * @param pVM The VM handle.
1669 */
1670VMMDECL(RTHCPHYS) PGMGetInterHCCR3(PVM pVM)
1671{
1672 switch (pVM->pgm.s.enmHostMode)
1673 {
1674 case SUPPAGINGMODE_32_BIT:
1675 case SUPPAGINGMODE_32_BIT_GLOBAL:
1676 return pVM->pgm.s.HCPhysInterPD;
1677
1678 case SUPPAGINGMODE_PAE:
1679 case SUPPAGINGMODE_PAE_GLOBAL:
1680 case SUPPAGINGMODE_PAE_NX:
1681 case SUPPAGINGMODE_PAE_GLOBAL_NX:
1682 return pVM->pgm.s.HCPhysInterPaePDPT;
1683
1684 case SUPPAGINGMODE_AMD64:
1685 case SUPPAGINGMODE_AMD64_GLOBAL:
1686 case SUPPAGINGMODE_AMD64_NX:
1687 case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1688 return pVM->pgm.s.HCPhysInterPaePDPT;
1689
1690 default:
1691 AssertMsgFailed(("enmHostMode=%d\n", pVM->pgm.s.enmHostMode));
1692 return ~0;
1693 }
1694}
1695
1696
1697/**
1698 * Gets the current CR3 register value for the RC intermediate memory context.
1699 * @returns CR3 value.
1700 * @param pVM The VM handle.
1701 * @param pVCpu VMCPU handle.
1702 */
1703VMMDECL(RTHCPHYS) PGMGetInterRCCR3(PVM pVM, PVMCPU pVCpu)
1704{
1705 switch (pVCpu->pgm.s.enmShadowMode)
1706 {
1707 case PGMMODE_32_BIT:
1708 return pVM->pgm.s.HCPhysInterPD;
1709
1710 case PGMMODE_PAE:
1711 case PGMMODE_PAE_NX:
1712 return pVM->pgm.s.HCPhysInterPaePDPT;
1713
1714 case PGMMODE_AMD64:
1715 case PGMMODE_AMD64_NX:
1716 return pVM->pgm.s.HCPhysInterPaePML4;
1717
1718 case PGMMODE_EPT:
1719 case PGMMODE_NESTED:
1720 return 0; /* not relevant */
1721
1722 default:
1723 AssertMsgFailed(("enmShadowMode=%d\n", pVCpu->pgm.s.enmShadowMode));
1724 return ~0;
1725 }
1726}
1727
1728
1729/**
1730 * Gets the CR3 register value for the 32-Bit intermediate memory context.
1731 * @returns CR3 value.
1732 * @param pVM The VM handle.
1733 */
1734VMMDECL(RTHCPHYS) PGMGetInter32BitCR3(PVM pVM)
1735{
1736 return pVM->pgm.s.HCPhysInterPD;
1737}
1738
1739
1740/**
1741 * Gets the CR3 register value for the PAE intermediate memory context.
1742 * @returns CR3 value.
1743 * @param pVM The VM handle.
1744 */
1745VMMDECL(RTHCPHYS) PGMGetInterPaeCR3(PVM pVM)
1746{
1747 return pVM->pgm.s.HCPhysInterPaePDPT;
1748}
1749
1750
1751/**
1752 * Gets the CR3 register value for the AMD64 intermediate memory context.
1753 * @returns CR3 value.
1754 * @param pVM The VM handle.
1755 */
1756VMMDECL(RTHCPHYS) PGMGetInterAmd64CR3(PVM pVM)
1757{
1758 return pVM->pgm.s.HCPhysInterPaePML4;
1759}
1760
1761
1762/**
1763 * Performs and schedules necessary updates following a CR3 load or reload.
1764 *
1765 * This will normally involve mapping the guest PD or nPDPT
1766 *
1767 * @returns VBox status code.
1768 * @retval VINF_PGM_SYNC_CR3 if monitoring requires a CR3 sync. This can
1769 * safely be ignored and overridden since the FF will be set too then.
1770 * @param pVCpu VMCPU handle.
1771 * @param cr3 The new cr3.
1772 * @param fGlobal Indicates whether this is a global flush or not.
1773 */
1774VMMDECL(int) PGMFlushTLB(PVMCPU pVCpu, uint64_t cr3, bool fGlobal)
1775{
1776 PVM pVM = pVCpu->CTX_SUFF(pVM);
1777
1778 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FlushTLB), a);
1779
1780 /*
1781 * Always flag the necessary updates; necessary for hardware acceleration
1782 */
1783 /** @todo optimize this, it shouldn't always be necessary. */
1784 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
1785 if (fGlobal)
1786 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
1787 LogFlow(("PGMFlushTLB: cr3=%RX64 OldCr3=%RX64 fGlobal=%d\n", cr3, pVCpu->pgm.s.GCPhysCR3, fGlobal));
1788
1789 /*
1790 * Remap the CR3 content and adjust the monitoring if CR3 was actually changed.
1791 */
1792 int rc = VINF_SUCCESS;
1793 RTGCPHYS GCPhysCR3;
1794 switch (pVCpu->pgm.s.enmGuestMode)
1795 {
1796 case PGMMODE_PAE:
1797 case PGMMODE_PAE_NX:
1798 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAE_PAGE_MASK);
1799 break;
1800 case PGMMODE_AMD64:
1801 case PGMMODE_AMD64_NX:
1802 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_AMD64_PAGE_MASK);
1803 break;
1804 default:
1805 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAGE_MASK);
1806 break;
1807 }
1808
1809 if (pVCpu->pgm.s.GCPhysCR3 != GCPhysCR3)
1810 {
1811 RTGCPHYS GCPhysOldCR3 = pVCpu->pgm.s.GCPhysCR3;
1812 pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3;
1813 rc = PGM_BTH_PFN(MapCR3, pVCpu)(pVCpu, GCPhysCR3);
1814 if (RT_LIKELY(rc == VINF_SUCCESS))
1815 {
1816 if (pgmMapAreMappingsFloating(&pVM->pgm.s))
1817 pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
1818 }
1819 else
1820 {
1821 AssertMsg(rc == VINF_PGM_SYNC_CR3, ("%Rrc\n", rc));
1822 Assert(VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL | VMCPU_FF_PGM_SYNC_CR3));
1823 pVCpu->pgm.s.GCPhysCR3 = GCPhysOldCR3;
1824 pVCpu->pgm.s.fSyncFlags |= PGM_SYNC_MAP_CR3;
1825 if (pgmMapAreMappingsFloating(&pVM->pgm.s))
1826 pVCpu->pgm.s.fSyncFlags |= PGM_SYNC_MONITOR_CR3;
1827 }
1828
1829 if (fGlobal)
1830 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FlushTLBNewCR3Global));
1831 else
1832 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FlushTLBNewCR3));
1833 }
1834 else
1835 {
1836# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
1837 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1838 if (pPool->cDirtyPages)
1839 {
1840 pgmLock(pVM);
1841 pgmPoolResetDirtyPages(pVM);
1842 pgmUnlock(pVM);
1843 }
1844# endif
1845 /*
1846 * Check if we have a pending update of the CR3 monitoring.
1847 */
1848 if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
1849 {
1850 pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
1851 Assert(!pVM->pgm.s.fMappingsFixed); Assert(!pVM->pgm.s.fMappingsDisabled);
1852 }
1853 if (fGlobal)
1854 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FlushTLBSameCR3Global));
1855 else
1856 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FlushTLBSameCR3));
1857 }
1858
1859 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FlushTLB), a);
1860 return rc;
1861}
1862
1863
1864/**
1865 * Performs and schedules necessary updates following a CR3 load or reload when
1866 * using nested or extended paging.
1867 *
1868 * This API is an alterantive to PDMFlushTLB that avoids actually flushing the
1869 * TLB and triggering a SyncCR3.
1870 *
1871 * This will normally involve mapping the guest PD or nPDPT
1872 *
1873 * @returns VBox status code.
1874 * @retval VINF_SUCCESS.
1875 * @retval (If applied when not in nested mode: VINF_PGM_SYNC_CR3 if monitoring
1876 * requires a CR3 sync. This can safely be ignored and overridden since
1877 * the FF will be set too then.)
1878 * @param pVCpu VMCPU handle.
1879 * @param cr3 The new cr3.
1880 */
1881VMMDECL(int) PGMUpdateCR3(PVMCPU pVCpu, uint64_t cr3)
1882{
1883 PVM pVM = pVCpu->CTX_SUFF(pVM);
1884
1885 LogFlow(("PGMUpdateCR3: cr3=%RX64 OldCr3=%RX64\n", cr3, pVCpu->pgm.s.GCPhysCR3));
1886
1887 /* We assume we're only called in nested paging mode. */
1888 Assert(pVM->pgm.s.fNestedPaging || pVCpu->pgm.s.enmShadowMode == PGMMODE_EPT);
1889 Assert(pVM->pgm.s.fMappingsDisabled);
1890 Assert(!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3));
1891
1892 /*
1893 * Remap the CR3 content and adjust the monitoring if CR3 was actually changed.
1894 */
1895 int rc = VINF_SUCCESS;
1896 RTGCPHYS GCPhysCR3;
1897 switch (pVCpu->pgm.s.enmGuestMode)
1898 {
1899 case PGMMODE_PAE:
1900 case PGMMODE_PAE_NX:
1901 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAE_PAGE_MASK);
1902 break;
1903 case PGMMODE_AMD64:
1904 case PGMMODE_AMD64_NX:
1905 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_AMD64_PAGE_MASK);
1906 break;
1907 default:
1908 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAGE_MASK);
1909 break;
1910 }
1911 if (pVCpu->pgm.s.GCPhysCR3 != GCPhysCR3)
1912 {
1913 pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3;
1914 rc = PGM_BTH_PFN(MapCR3, pVCpu)(pVCpu, GCPhysCR3);
1915 AssertRCSuccess(rc); /* Assumes VINF_PGM_SYNC_CR3 doesn't apply to nested paging. */ /** @todo this isn't true for the mac, but we need hw to test/fix this. */
1916 }
1917 return rc;
1918}
1919
1920
1921/**
1922 * Synchronize the paging structures.
1923 *
1924 * This function is called in response to the VM_FF_PGM_SYNC_CR3 and
1925 * VM_FF_PGM_SYNC_CR3_NONGLOBAL. Those two force action flags are set
1926 * in several places, most importantly whenever the CR3 is loaded.
1927 *
1928 * @returns VBox status code.
1929 * @param pVCpu VMCPU handle.
1930 * @param cr0 Guest context CR0 register
1931 * @param cr3 Guest context CR3 register
1932 * @param cr4 Guest context CR4 register
1933 * @param fGlobal Including global page directories or not
1934 */
1935VMMDECL(int) PGMSyncCR3(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
1936{
1937 PVM pVM = pVCpu->CTX_SUFF(pVM);
1938 int rc;
1939
1940 /*
1941 * The pool may have pending stuff and even require a return to ring-3 to
1942 * clear the whole thing.
1943 */
1944 rc = pgmPoolSyncCR3(pVCpu);
1945 if (rc != VINF_SUCCESS)
1946 return rc;
1947
1948 /*
1949 * We might be called when we shouldn't.
1950 *
1951 * The mode switching will ensure that the PD is resynced
1952 * after every mode switch. So, if we find ourselves here
1953 * when in protected or real mode we can safely disable the
1954 * FF and return immediately.
1955 */
1956 if (pVCpu->pgm.s.enmGuestMode <= PGMMODE_PROTECTED)
1957 {
1958 Assert((cr0 & (X86_CR0_PG | X86_CR0_PE)) != (X86_CR0_PG | X86_CR0_PE));
1959 Assert(!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL));
1960 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
1961 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
1962 return VINF_SUCCESS;
1963 }
1964
1965 /* If global pages are not supported, then all flushes are global. */
1966 if (!(cr4 & X86_CR4_PGE))
1967 fGlobal = true;
1968 LogFlow(("PGMSyncCR3: cr0=%RX64 cr3=%RX64 cr4=%RX64 fGlobal=%d[%d,%d]\n", cr0, cr3, cr4, fGlobal,
1969 VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3), VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)));
1970
1971 /*
1972 * Check if we need to finish an aborted MapCR3 call (see PGMFlushTLB).
1973 * This should be done before SyncCR3.
1974 */
1975 if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MAP_CR3)
1976 {
1977 pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MAP_CR3;
1978
1979 RTGCPHYS GCPhysCR3Old = pVCpu->pgm.s.GCPhysCR3;
1980 RTGCPHYS GCPhysCR3;
1981 switch (pVCpu->pgm.s.enmGuestMode)
1982 {
1983 case PGMMODE_PAE:
1984 case PGMMODE_PAE_NX:
1985 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAE_PAGE_MASK);
1986 break;
1987 case PGMMODE_AMD64:
1988 case PGMMODE_AMD64_NX:
1989 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_AMD64_PAGE_MASK);
1990 break;
1991 default:
1992 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAGE_MASK);
1993 break;
1994 }
1995
1996 if (pVCpu->pgm.s.GCPhysCR3 != GCPhysCR3)
1997 {
1998 pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3;
1999 rc = PGM_BTH_PFN(MapCR3, pVCpu)(pVCpu, GCPhysCR3);
2000 }
2001 /* Make sure we check for pending pgm pool syncs as we clear VMCPU_FF_PGM_SYNC_CR3 later on! */
2002 if ( rc == VINF_PGM_SYNC_CR3
2003 || (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL))
2004 {
2005 Log(("PGMSyncCR3: pending pgm pool sync after MapCR3!\n"));
2006#ifdef IN_RING3
2007 rc = pgmPoolSyncCR3(pVCpu);
2008#else
2009 if (rc == VINF_PGM_SYNC_CR3)
2010 pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3Old;
2011 return VINF_PGM_SYNC_CR3;
2012#endif
2013 }
2014 AssertRCReturn(rc, rc);
2015 AssertRCSuccessReturn(rc, VERR_INTERNAL_ERROR);
2016 }
2017
2018 /*
2019 * Let the 'Bth' function do the work and we'll just keep track of the flags.
2020 */
2021 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3), a);
2022 rc = PGM_BTH_PFN(SyncCR3, pVCpu)(pVCpu, cr0, cr3, cr4, fGlobal);
2023 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3), a);
2024 AssertMsg(rc == VINF_SUCCESS || rc == VINF_PGM_SYNC_CR3 || RT_FAILURE(rc), ("rc=%Rrc\n", rc));
2025 if (rc == VINF_SUCCESS)
2026 {
2027 if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL)
2028 {
2029 /* Go back to ring 3 if a pgm pool sync is again pending. */
2030 return VINF_PGM_SYNC_CR3;
2031 }
2032
2033 if (!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS))
2034 {
2035 Assert(!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL));
2036 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2037 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
2038 }
2039
2040 /*
2041 * Check if we have a pending update of the CR3 monitoring.
2042 */
2043 if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
2044 {
2045 pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
2046 Assert(!pVM->pgm.s.fMappingsFixed); Assert(!pVM->pgm.s.fMappingsDisabled);
2047 }
2048 }
2049
2050 /*
2051 * Now flush the CR3 (guest context).
2052 */
2053 if (rc == VINF_SUCCESS)
2054 PGM_INVL_VCPU_TLBS(pVCpu);
2055 return rc;
2056}
2057
2058
2059/**
2060 * Called whenever CR0 or CR4 in a way which may affect the paging mode.
2061 *
2062 * @returns VBox status code, with the following informational code for
2063 * VM scheduling.
2064 * @retval VINF_SUCCESS if the was no change, or it was successfully dealt with.
2065 * @retval VINF_PGM_CHANGE_MODE if we're in RC or R0 and the mode changes.
2066 * (I.e. not in R3.)
2067 * @retval VINF_EM_SUSPEND or VINF_EM_OFF on a fatal runtime error. (R3 only)
2068 *
2069 * @param pVCpu VMCPU handle.
2070 * @param cr0 The new cr0.
2071 * @param cr4 The new cr4.
2072 * @param efer The new extended feature enable register.
2073 */
2074VMMDECL(int) PGMChangeMode(PVMCPU pVCpu, uint64_t cr0, uint64_t cr4, uint64_t efer)
2075{
2076 PVM pVM = pVCpu->CTX_SUFF(pVM);
2077 PGMMODE enmGuestMode;
2078
2079 /*
2080 * Calc the new guest mode.
2081 */
2082 if (!(cr0 & X86_CR0_PE))
2083 enmGuestMode = PGMMODE_REAL;
2084 else if (!(cr0 & X86_CR0_PG))
2085 enmGuestMode = PGMMODE_PROTECTED;
2086 else if (!(cr4 & X86_CR4_PAE))
2087 {
2088 bool const fPse = !!(cr4 & X86_CR4_PSE);
2089 if (pVCpu->pgm.s.fGst32BitPageSizeExtension != fPse)
2090 Log(("PGMChangeMode: CR4.PSE %d -> %d\n", pVCpu->pgm.s.fGst32BitPageSizeExtension, fPse));
2091 pVCpu->pgm.s.fGst32BitPageSizeExtension = fPse;
2092 enmGuestMode = PGMMODE_32_BIT;
2093 }
2094 else if (!(efer & MSR_K6_EFER_LME))
2095 {
2096 if (!(efer & MSR_K6_EFER_NXE))
2097 enmGuestMode = PGMMODE_PAE;
2098 else
2099 enmGuestMode = PGMMODE_PAE_NX;
2100 }
2101 else
2102 {
2103 if (!(efer & MSR_K6_EFER_NXE))
2104 enmGuestMode = PGMMODE_AMD64;
2105 else
2106 enmGuestMode = PGMMODE_AMD64_NX;
2107 }
2108
2109 /*
2110 * Did it change?
2111 */
2112 if (pVCpu->pgm.s.enmGuestMode == enmGuestMode)
2113 return VINF_SUCCESS;
2114
2115 /* Flush the TLB */
2116 PGM_INVL_VCPU_TLBS(pVCpu);
2117
2118#ifdef IN_RING3
2119 return PGMR3ChangeMode(pVM, pVCpu, enmGuestMode);
2120#else
2121 LogFlow(("PGMChangeMode: returns VINF_PGM_CHANGE_MODE.\n"));
2122 return VINF_PGM_CHANGE_MODE;
2123#endif
2124}
2125
2126
2127/**
2128 * Gets the current guest paging mode.
2129 *
2130 * If you just need the CPU mode (real/protected/long), use CPUMGetGuestMode().
2131 *
2132 * @returns The current paging mode.
2133 * @param pVCpu VMCPU handle.
2134 */
2135VMMDECL(PGMMODE) PGMGetGuestMode(PVMCPU pVCpu)
2136{
2137 return pVCpu->pgm.s.enmGuestMode;
2138}
2139
2140
2141/**
2142 * Gets the current shadow paging mode.
2143 *
2144 * @returns The current paging mode.
2145 * @param pVCpu VMCPU handle.
2146 */
2147VMMDECL(PGMMODE) PGMGetShadowMode(PVMCPU pVCpu)
2148{
2149 return pVCpu->pgm.s.enmShadowMode;
2150}
2151
2152/**
2153 * Gets the current host paging mode.
2154 *
2155 * @returns The current paging mode.
2156 * @param pVM The VM handle.
2157 */
2158VMMDECL(PGMMODE) PGMGetHostMode(PVM pVM)
2159{
2160 switch (pVM->pgm.s.enmHostMode)
2161 {
2162 case SUPPAGINGMODE_32_BIT:
2163 case SUPPAGINGMODE_32_BIT_GLOBAL:
2164 return PGMMODE_32_BIT;
2165
2166 case SUPPAGINGMODE_PAE:
2167 case SUPPAGINGMODE_PAE_GLOBAL:
2168 return PGMMODE_PAE;
2169
2170 case SUPPAGINGMODE_PAE_NX:
2171 case SUPPAGINGMODE_PAE_GLOBAL_NX:
2172 return PGMMODE_PAE_NX;
2173
2174 case SUPPAGINGMODE_AMD64:
2175 case SUPPAGINGMODE_AMD64_GLOBAL:
2176 return PGMMODE_AMD64;
2177
2178 case SUPPAGINGMODE_AMD64_NX:
2179 case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2180 return PGMMODE_AMD64_NX;
2181
2182 default: AssertMsgFailed(("enmHostMode=%d\n", pVM->pgm.s.enmHostMode)); break;
2183 }
2184
2185 return PGMMODE_INVALID;
2186}
2187
2188
2189/**
2190 * Get mode name.
2191 *
2192 * @returns read-only name string.
2193 * @param enmMode The mode which name is desired.
2194 */
2195VMMDECL(const char *) PGMGetModeName(PGMMODE enmMode)
2196{
2197 switch (enmMode)
2198 {
2199 case PGMMODE_REAL: return "Real";
2200 case PGMMODE_PROTECTED: return "Protected";
2201 case PGMMODE_32_BIT: return "32-bit";
2202 case PGMMODE_PAE: return "PAE";
2203 case PGMMODE_PAE_NX: return "PAE+NX";
2204 case PGMMODE_AMD64: return "AMD64";
2205 case PGMMODE_AMD64_NX: return "AMD64+NX";
2206 case PGMMODE_NESTED: return "Nested";
2207 case PGMMODE_EPT: return "EPT";
2208 default: return "unknown mode value";
2209 }
2210}
2211
2212
2213
2214/**
2215 * Notification from CPUM that the EFER.NXE bit has changed.
2216 *
2217 * @param pVCpu The virtual CPU for which EFER changed.
2218 * @param fNxe The new NXE state.
2219 */
2220VMM_INT_DECL(void) PGMNotifyNxeChanged(PVMCPU pVCpu, bool fNxe)
2221{
2222 Log(("PGMNotifyNxeChanged: fNxe=%RTbool\n", fNxe));
2223 pVCpu->pgm.s.fNoExecuteEnabled = fNxe;
2224 if (fNxe)
2225 {
2226 /*pVCpu->pgm.s.fGst32BitMbzBigPdeMask - N/A */
2227 pVCpu->pgm.s.fGstPaeMbzPteMask &= ~X86_PTE_PAE_NX;
2228 pVCpu->pgm.s.fGstPaeMbzPdeMask &= ~X86_PDE_PAE_NX;
2229 pVCpu->pgm.s.fGstPaeMbzBigPdeMask &= ~X86_PDE2M_PAE_NX;
2230 /*pVCpu->pgm.s.fGstPaeMbzPdpeMask - N/A */
2231 pVCpu->pgm.s.fGstAmd64MbzPteMask &= ~X86_PTE_PAE_NX;
2232 pVCpu->pgm.s.fGstAmd64MbzPdeMask &= ~X86_PDE_PAE_NX;
2233 pVCpu->pgm.s.fGstAmd64MbzBigPdeMask &= ~X86_PDE2M_PAE_NX;
2234 pVCpu->pgm.s.fGstAmd64MbzPdpeMask &= ~X86_PDPE_LM_NX;
2235 pVCpu->pgm.s.fGstAmd64MbzBigPdpeMask &= ~X86_PDPE_LM_NX;
2236 pVCpu->pgm.s.fGstAmd64MbzPml4eMask &= ~X86_PML4E_NX;
2237
2238 pVCpu->pgm.s.fGst64ShadowedPteMask |= X86_PTE_PAE_NX;
2239 pVCpu->pgm.s.fGst64ShadowedPdeMask |= X86_PDE_PAE_NX;
2240 pVCpu->pgm.s.fGst64ShadowedBigPdeMask |= X86_PDE2M_PAE_NX;
2241 pVCpu->pgm.s.fGst64ShadowedBigPde4PteMask |= X86_PDE2M_PAE_NX;
2242 pVCpu->pgm.s.fGstAmd64ShadowedPdpeMask |= X86_PDPE_LM_NX;
2243 pVCpu->pgm.s.fGstAmd64ShadowedPml4eMask |= X86_PML4E_NX;
2244 }
2245 else
2246 {
2247 /*pVCpu->pgm.s.fGst32BitMbzBigPdeMask - N/A */
2248 pVCpu->pgm.s.fGstPaeMbzPteMask |= X86_PTE_PAE_NX;
2249 pVCpu->pgm.s.fGstPaeMbzPdeMask |= X86_PDE_PAE_NX;
2250 pVCpu->pgm.s.fGstPaeMbzBigPdeMask |= X86_PDE2M_PAE_NX;
2251 /*pVCpu->pgm.s.fGstPaeMbzPdpeMask -N/A */
2252 pVCpu->pgm.s.fGstAmd64MbzPteMask |= X86_PTE_PAE_NX;
2253 pVCpu->pgm.s.fGstAmd64MbzPdeMask |= X86_PDE_PAE_NX;
2254 pVCpu->pgm.s.fGstAmd64MbzBigPdeMask |= X86_PDE2M_PAE_NX;
2255 pVCpu->pgm.s.fGstAmd64MbzPdpeMask |= X86_PDPE_LM_NX;
2256 pVCpu->pgm.s.fGstAmd64MbzBigPdpeMask |= X86_PDPE_LM_NX;
2257 pVCpu->pgm.s.fGstAmd64MbzPml4eMask |= X86_PML4E_NX;
2258
2259 pVCpu->pgm.s.fGst64ShadowedPteMask &= ~X86_PTE_PAE_NX;
2260 pVCpu->pgm.s.fGst64ShadowedPdeMask &= ~X86_PDE_PAE_NX;
2261 pVCpu->pgm.s.fGst64ShadowedBigPdeMask &= ~X86_PDE2M_PAE_NX;
2262 pVCpu->pgm.s.fGst64ShadowedBigPde4PteMask &= ~X86_PDE2M_PAE_NX;
2263 pVCpu->pgm.s.fGstAmd64ShadowedPdpeMask &= ~X86_PDPE_LM_NX;
2264 pVCpu->pgm.s.fGstAmd64ShadowedPml4eMask &= ~X86_PML4E_NX;
2265 }
2266}
2267
2268
2269/**
2270 * Check if any pgm pool pages are marked dirty (not monitored)
2271 *
2272 * @returns bool locked/not locked
2273 * @param pVM The VM to operate on.
2274 */
2275VMMDECL(bool) PGMHasDirtyPages(PVM pVM)
2276{
2277 return pVM->pgm.s.CTX_SUFF(pPool)->cDirtyPages != 0;
2278}
2279
2280/**
2281 * Check if the PGM lock is currently taken.
2282 *
2283 * @returns bool locked/not locked
2284 * @param pVM The VM to operate on.
2285 */
2286VMMDECL(bool) PGMIsLocked(PVM pVM)
2287{
2288 return PDMCritSectIsOwned(&pVM->pgm.s.CritSect);
2289}
2290
2291
2292/**
2293 * Check if this VCPU currently owns the PGM lock.
2294 *
2295 * @returns bool owner/not owner
2296 * @param pVM The VM to operate on.
2297 */
2298VMMDECL(bool) PGMIsLockOwner(PVM pVM)
2299{
2300 return PDMCritSectIsOwner(&pVM->pgm.s.CritSect);
2301}
2302
2303
2304/**
2305 * Enable or disable large page usage
2306 *
2307 * @param pVM The VM to operate on.
2308 * @param fUseLargePages Use/not use large pages
2309 */
2310VMMDECL(void) PGMSetLargePageUsage(PVM pVM, bool fUseLargePages)
2311{
2312 pVM->fUseLargePages = fUseLargePages;
2313}
2314
2315/**
2316 * Acquire the PGM lock.
2317 *
2318 * @returns VBox status code
2319 * @param pVM The VM to operate on.
2320 */
2321int pgmLock(PVM pVM)
2322{
2323 int rc = PDMCritSectEnter(&pVM->pgm.s.CritSect, VERR_SEM_BUSY);
2324#if defined(IN_RC) || defined(IN_RING0)
2325 if (rc == VERR_SEM_BUSY)
2326 rc = VMMRZCallRing3NoCpu(pVM, VMMCALLRING3_PGM_LOCK, 0);
2327#endif
2328 AssertMsg(rc == VINF_SUCCESS, ("%Rrc\n", rc));
2329 return rc;
2330}
2331
2332
2333/**
2334 * Release the PGM lock.
2335 *
2336 * @returns VBox status code
2337 * @param pVM The VM to operate on.
2338 */
2339void pgmUnlock(PVM pVM)
2340{
2341 PDMCritSectLeave(&pVM->pgm.s.CritSect);
2342}
2343
2344#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2345
2346/**
2347 * Common worker for pgmRZDynMapGCPageOffInlined and pgmRZDynMapGCPageV2Inlined.
2348 *
2349 * @returns VBox status code.
2350 * @param pVM The VM handle.
2351 * @param pVCpu The current CPU.
2352 * @param GCPhys The guest physical address of the page to map. The
2353 * offset bits are not ignored.
2354 * @param ppv Where to return the address corresponding to @a GCPhys.
2355 */
2356int pgmRZDynMapGCPageCommon(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void **ppv RTLOG_COMMA_SRC_POS_DECL)
2357{
2358 pgmLock(pVM);
2359
2360 /*
2361 * Convert it to a writable page and it on to the dynamic mapper.
2362 */
2363 int rc;
2364 PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, GCPhys);
2365 if (RT_LIKELY(pPage))
2366 {
2367 rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
2368 if (RT_SUCCESS(rc))
2369 {
2370 void *pv;
2371 rc = pgmRZDynMapHCPageInlined(pVCpu, PGM_PAGE_GET_HCPHYS(pPage), &pv RTLOG_COMMA_SRC_POS_ARGS);
2372 if (RT_SUCCESS(rc))
2373 *ppv = (void *)((uintptr_t)pv | ((uintptr_t)GCPhys & PAGE_OFFSET_MASK));
2374 }
2375 else
2376 AssertRC(rc);
2377 }
2378 else
2379 {
2380 AssertMsgFailed(("Invalid physical address %RGp!\n", GCPhys));
2381 rc = VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2382 }
2383
2384 pgmUnlock(pVM);
2385 return rc;
2386}
2387
2388#endif /* IN_RC || VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
2389#if !defined(IN_R0) || defined(LOG_ENABLED)
2390
2391/** Format handler for PGMPAGE.
2392 * @copydoc FNRTSTRFORMATTYPE */
2393static DECLCALLBACK(size_t) pgmFormatTypeHandlerPage(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
2394 const char *pszType, void const *pvValue,
2395 int cchWidth, int cchPrecision, unsigned fFlags,
2396 void *pvUser)
2397{
2398 size_t cch;
2399 PCPGMPAGE pPage = (PCPGMPAGE)pvValue;
2400 if (VALID_PTR(pPage))
2401 {
2402 char szTmp[64+80];
2403
2404 cch = 0;
2405
2406 /* The single char state stuff. */
2407 static const char s_achPageStates[4] = { 'Z', 'A', 'W', 'S' };
2408 szTmp[cch++] = s_achPageStates[PGM_PAGE_GET_STATE(pPage)];
2409
2410#define IS_PART_INCLUDED(lvl) ( !(fFlags & RTSTR_F_PRECISION) || cchPrecision == (lvl) || cchPrecision >= (lvl)+10 )
2411 if (IS_PART_INCLUDED(5))
2412 {
2413 static const char s_achHandlerStates[4] = { '-', 't', 'w', 'a' };
2414 szTmp[cch++] = s_achHandlerStates[PGM_PAGE_GET_HNDL_PHYS_STATE(pPage)];
2415 szTmp[cch++] = s_achHandlerStates[PGM_PAGE_GET_HNDL_VIRT_STATE(pPage)];
2416 }
2417
2418 /* The type. */
2419 if (IS_PART_INCLUDED(4))
2420 {
2421 szTmp[cch++] = ':';
2422 static const char s_achPageTypes[8][4] = { "INV", "RAM", "MI2", "M2A", "SHA", "ROM", "MIO", "BAD" };
2423 szTmp[cch++] = s_achPageTypes[PGM_PAGE_GET_TYPE(pPage)][0];
2424 szTmp[cch++] = s_achPageTypes[PGM_PAGE_GET_TYPE(pPage)][1];
2425 szTmp[cch++] = s_achPageTypes[PGM_PAGE_GET_TYPE(pPage)][2];
2426 }
2427
2428 /* The numbers. */
2429 if (IS_PART_INCLUDED(3))
2430 {
2431 szTmp[cch++] = ':';
2432 cch += RTStrFormatNumber(&szTmp[cch], PGM_PAGE_GET_HCPHYS(pPage), 16, 12, 0, RTSTR_F_ZEROPAD | RTSTR_F_64BIT);
2433 }
2434
2435 if (IS_PART_INCLUDED(2))
2436 {
2437 szTmp[cch++] = ':';
2438 cch += RTStrFormatNumber(&szTmp[cch], PGM_PAGE_GET_PAGEID(pPage), 16, 7, 0, RTSTR_F_ZEROPAD | RTSTR_F_32BIT);
2439 }
2440
2441 if (IS_PART_INCLUDED(6))
2442 {
2443 szTmp[cch++] = ':';
2444 static const char s_achRefs[4] = { '-', 'U', '!', 'L' };
2445 szTmp[cch++] = s_achRefs[PGM_PAGE_GET_TD_CREFS(pPage)];
2446 cch += RTStrFormatNumber(&szTmp[cch], PGM_PAGE_GET_TD_IDX(pPage), 16, 4, 0, RTSTR_F_ZEROPAD | RTSTR_F_16BIT);
2447 }
2448#undef IS_PART_INCLUDED
2449
2450 cch = pfnOutput(pvArgOutput, szTmp, cch);
2451 }
2452 else
2453 cch = pfnOutput(pvArgOutput, "<bad-pgmpage-ptr>", sizeof("<bad-pgmpage-ptr>") - 1);
2454 return cch;
2455}
2456
2457
2458/** Format handler for PGMRAMRANGE.
2459 * @copydoc FNRTSTRFORMATTYPE */
2460static DECLCALLBACK(size_t) pgmFormatTypeHandlerRamRange(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
2461 const char *pszType, void const *pvValue,
2462 int cchWidth, int cchPrecision, unsigned fFlags,
2463 void *pvUser)
2464{
2465 size_t cch;
2466 PGMRAMRANGE const *pRam = (PGMRAMRANGE const *)pvValue;
2467 if (VALID_PTR(pRam))
2468 {
2469 char szTmp[80];
2470 cch = RTStrPrintf(szTmp, sizeof(szTmp), "%RGp-%RGp", pRam->GCPhys, pRam->GCPhysLast);
2471 cch = pfnOutput(pvArgOutput, szTmp, cch);
2472 }
2473 else
2474 cch = pfnOutput(pvArgOutput, "<bad-pgmramrange-ptr>", sizeof("<bad-pgmramrange-ptr>") - 1);
2475 return cch;
2476}
2477
2478/** Format type andlers to be registered/deregistered. */
2479static const struct
2480{
2481 char szType[24];
2482 PFNRTSTRFORMATTYPE pfnHandler;
2483} g_aPgmFormatTypes[] =
2484{
2485 { "pgmpage", pgmFormatTypeHandlerPage },
2486 { "pgmramrange", pgmFormatTypeHandlerRamRange }
2487};
2488
2489#endif /* !IN_R0 || LOG_ENABLED */
2490
2491/**
2492 * Registers the global string format types.
2493 *
2494 * This should be called at module load time or in some other manner that ensure
2495 * that it's called exactly one time.
2496 *
2497 * @returns IPRT status code on RTStrFormatTypeRegister failure.
2498 */
2499VMMDECL(int) PGMRegisterStringFormatTypes(void)
2500{
2501#if !defined(IN_R0) || defined(LOG_ENABLED)
2502 int rc = VINF_SUCCESS;
2503 unsigned i;
2504 for (i = 0; RT_SUCCESS(rc) && i < RT_ELEMENTS(g_aPgmFormatTypes); i++)
2505 {
2506 rc = RTStrFormatTypeRegister(g_aPgmFormatTypes[i].szType, g_aPgmFormatTypes[i].pfnHandler, NULL);
2507# ifdef IN_RING0
2508 if (rc == VERR_ALREADY_EXISTS)
2509 {
2510 /* in case of cleanup failure in ring-0 */
2511 RTStrFormatTypeDeregister(g_aPgmFormatTypes[i].szType);
2512 rc = RTStrFormatTypeRegister(g_aPgmFormatTypes[i].szType, g_aPgmFormatTypes[i].pfnHandler, NULL);
2513 }
2514# endif
2515 }
2516 if (RT_FAILURE(rc))
2517 while (i-- > 0)
2518 RTStrFormatTypeDeregister(g_aPgmFormatTypes[i].szType);
2519
2520 return rc;
2521#else
2522 return VINF_SUCCESS;
2523#endif
2524}
2525
2526
2527/**
2528 * Deregisters the global string format types.
2529 *
2530 * This should be called at module unload time or in some other manner that
2531 * ensure that it's called exactly one time.
2532 */
2533VMMDECL(void) PGMDeregisterStringFormatTypes(void)
2534{
2535#if !defined(IN_R0) || defined(LOG_ENABLED)
2536 for (unsigned i = 0; i < RT_ELEMENTS(g_aPgmFormatTypes); i++)
2537 RTStrFormatTypeDeregister(g_aPgmFormatTypes[i].szType);
2538#endif
2539}
2540
2541#ifdef VBOX_STRICT
2542
2543/**
2544 * Asserts that there are no mapping conflicts.
2545 *
2546 * @returns Number of conflicts.
2547 * @param pVM The VM Handle.
2548 */
2549VMMDECL(unsigned) PGMAssertNoMappingConflicts(PVM pVM)
2550{
2551 unsigned cErrors = 0;
2552
2553 /* Only applies to raw mode -> 1 VPCU */
2554 Assert(pVM->cCpus == 1);
2555 PVMCPU pVCpu = &pVM->aCpus[0];
2556
2557 /*
2558 * Check for mapping conflicts.
2559 */
2560 for (PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
2561 pMapping;
2562 pMapping = pMapping->CTX_SUFF(pNext))
2563 {
2564 /** @todo This is slow and should be optimized, but since it's just assertions I don't care now. */
2565 for (RTGCPTR GCPtr = pMapping->GCPtr;
2566 GCPtr <= pMapping->GCPtrLast;
2567 GCPtr += PAGE_SIZE)
2568 {
2569 int rc = PGMGstGetPage(pVCpu, (RTGCPTR)GCPtr, NULL, NULL);
2570 if (rc != VERR_PAGE_TABLE_NOT_PRESENT)
2571 {
2572 AssertMsgFailed(("Conflict at %RGv with %s\n", GCPtr, R3STRING(pMapping->pszDesc)));
2573 cErrors++;
2574 break;
2575 }
2576 }
2577 }
2578
2579 return cErrors;
2580}
2581
2582
2583/**
2584 * Asserts that everything related to the guest CR3 is correctly shadowed.
2585 *
2586 * This will call PGMAssertNoMappingConflicts() and PGMAssertHandlerAndFlagsInSync(),
2587 * and assert the correctness of the guest CR3 mapping before asserting that the
2588 * shadow page tables is in sync with the guest page tables.
2589 *
2590 * @returns Number of conflicts.
2591 * @param pVM The VM Handle.
2592 * @param pVCpu VMCPU handle.
2593 * @param cr3 The current guest CR3 register value.
2594 * @param cr4 The current guest CR4 register value.
2595 */
2596VMMDECL(unsigned) PGMAssertCR3(PVM pVM, PVMCPU pVCpu, uint64_t cr3, uint64_t cr4)
2597{
2598 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3), a);
2599 pgmLock(pVM);
2600 unsigned cErrors = PGM_BTH_PFN(AssertCR3, pVCpu)(pVCpu, cr3, cr4, 0, ~(RTGCPTR)0);
2601 pgmUnlock(pVM);
2602 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3), a);
2603 return cErrors;
2604}
2605
2606#endif /* VBOX_STRICT */
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