VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAll.cpp@ 45528

Last change on this file since 45528 was 45528, checked in by vboxsync, 12 years ago

VBOX_WITH_RAW_MODE changes.
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1/* $Id: PGMAll.cpp 45528 2013-04-12 17:32:57Z vboxsync $ */
2/** @file
3 * PGM - Page Manager and Monitor - All context code.
4 */
5
6/*
7 * Copyright (C) 2006-2012 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/*******************************************************************************
19* Header Files *
20*******************************************************************************/
21#define LOG_GROUP LOG_GROUP_PGM
22#include <VBox/vmm/pgm.h>
23#include <VBox/vmm/cpum.h>
24#include <VBox/vmm/selm.h>
25#include <VBox/vmm/iom.h>
26#include <VBox/sup.h>
27#include <VBox/vmm/mm.h>
28#include <VBox/vmm/stam.h>
29#include <VBox/vmm/csam.h>
30#include <VBox/vmm/patm.h>
31#include <VBox/vmm/trpm.h>
32#ifdef VBOX_WITH_REM
33# include <VBox/vmm/rem.h>
34#endif
35#include <VBox/vmm/em.h>
36#include <VBox/vmm/hm.h>
37#include <VBox/vmm/hm_vmx.h>
38#include "PGMInternal.h"
39#include <VBox/vmm/vm.h>
40#include "PGMInline.h"
41#include <iprt/assert.h>
42#include <iprt/asm-amd64-x86.h>
43#include <iprt/string.h>
44#include <VBox/log.h>
45#include <VBox/param.h>
46#include <VBox/err.h>
47
48
49/*******************************************************************************
50* Structures and Typedefs *
51*******************************************************************************/
52/**
53 * Stated structure for PGM_GST_NAME(HandlerVirtualUpdate) that's
54 * passed to PGM_GST_NAME(VirtHandlerUpdateOne) during enumeration.
55 */
56typedef struct PGMHVUSTATE
57{
58 /** Pointer to the VM. */
59 PVM pVM;
60 /** Pointer to the VMCPU. */
61 PVMCPU pVCpu;
62 /** The todo flags. */
63 RTUINT fTodo;
64 /** The CR4 register value. */
65 uint32_t cr4;
66} PGMHVUSTATE, *PPGMHVUSTATE;
67
68
69/*******************************************************************************
70* Internal Functions *
71*******************************************************************************/
72DECLINLINE(int) pgmShwGetLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPT *ppPdpt, PX86PDPAE *ppPD);
73DECLINLINE(int) pgmShwGetPaePoolPagePD(PVMCPU pVCpu, RTGCPTR GCPtr, PPGMPOOLPAGE *ppShwPde);
74#ifndef IN_RC
75static int pgmShwSyncLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, X86PGPAEUINT uGstPml4e, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD);
76static int pgmShwGetEPTPDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PEPTPDPT *ppPdpt, PEPTPD *ppPD);
77#endif
78
79
80/*
81 * Shadow - 32-bit mode
82 */
83#define PGM_SHW_TYPE PGM_TYPE_32BIT
84#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
85#include "PGMAllShw.h"
86
87/* Guest - real mode */
88#define PGM_GST_TYPE PGM_TYPE_REAL
89#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
90#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
91#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
92#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
93#include "PGMGstDefs.h"
94#include "PGMAllGst.h"
95#include "PGMAllBth.h"
96#undef BTH_PGMPOOLKIND_PT_FOR_PT
97#undef BTH_PGMPOOLKIND_ROOT
98#undef PGM_BTH_NAME
99#undef PGM_GST_TYPE
100#undef PGM_GST_NAME
101
102/* Guest - protected mode */
103#define PGM_GST_TYPE PGM_TYPE_PROT
104#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
105#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
106#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
107#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
108#include "PGMGstDefs.h"
109#include "PGMAllGst.h"
110#include "PGMAllBth.h"
111#undef BTH_PGMPOOLKIND_PT_FOR_PT
112#undef BTH_PGMPOOLKIND_ROOT
113#undef PGM_BTH_NAME
114#undef PGM_GST_TYPE
115#undef PGM_GST_NAME
116
117/* Guest - 32-bit mode */
118#define PGM_GST_TYPE PGM_TYPE_32BIT
119#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
120#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
121#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
122#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
123#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD
124#include "PGMGstDefs.h"
125#include "PGMAllGst.h"
126#include "PGMAllBth.h"
127#undef BTH_PGMPOOLKIND_PT_FOR_BIG
128#undef BTH_PGMPOOLKIND_PT_FOR_PT
129#undef BTH_PGMPOOLKIND_ROOT
130#undef PGM_BTH_NAME
131#undef PGM_GST_TYPE
132#undef PGM_GST_NAME
133
134#undef PGM_SHW_TYPE
135#undef PGM_SHW_NAME
136
137
138/*
139 * Shadow - PAE mode
140 */
141#define PGM_SHW_TYPE PGM_TYPE_PAE
142#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
143#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
144#include "PGMAllShw.h"
145
146/* Guest - real mode */
147#define PGM_GST_TYPE PGM_TYPE_REAL
148#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
149#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
150#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
151#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
152#include "PGMGstDefs.h"
153#include "PGMAllBth.h"
154#undef BTH_PGMPOOLKIND_PT_FOR_PT
155#undef BTH_PGMPOOLKIND_ROOT
156#undef PGM_BTH_NAME
157#undef PGM_GST_TYPE
158#undef PGM_GST_NAME
159
160/* Guest - protected mode */
161#define PGM_GST_TYPE PGM_TYPE_PROT
162#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
163#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
164#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
165#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
166#include "PGMGstDefs.h"
167#include "PGMAllBth.h"
168#undef BTH_PGMPOOLKIND_PT_FOR_PT
169#undef BTH_PGMPOOLKIND_ROOT
170#undef PGM_BTH_NAME
171#undef PGM_GST_TYPE
172#undef PGM_GST_NAME
173
174/* Guest - 32-bit mode */
175#define PGM_GST_TYPE PGM_TYPE_32BIT
176#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
177#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
178#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
179#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
180#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_FOR_32BIT
181#include "PGMGstDefs.h"
182#include "PGMAllBth.h"
183#undef BTH_PGMPOOLKIND_PT_FOR_BIG
184#undef BTH_PGMPOOLKIND_PT_FOR_PT
185#undef BTH_PGMPOOLKIND_ROOT
186#undef PGM_BTH_NAME
187#undef PGM_GST_TYPE
188#undef PGM_GST_NAME
189
190
191/* Guest - PAE mode */
192#define PGM_GST_TYPE PGM_TYPE_PAE
193#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
194#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
195#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
196#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
197#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT
198#include "PGMGstDefs.h"
199#include "PGMAllGst.h"
200#include "PGMAllBth.h"
201#undef BTH_PGMPOOLKIND_PT_FOR_BIG
202#undef BTH_PGMPOOLKIND_PT_FOR_PT
203#undef BTH_PGMPOOLKIND_ROOT
204#undef PGM_BTH_NAME
205#undef PGM_GST_TYPE
206#undef PGM_GST_NAME
207
208#undef PGM_SHW_TYPE
209#undef PGM_SHW_NAME
210
211
212#ifndef IN_RC /* AMD64 implies VT-x/AMD-V */
213/*
214 * Shadow - AMD64 mode
215 */
216# define PGM_SHW_TYPE PGM_TYPE_AMD64
217# define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
218# include "PGMAllShw.h"
219
220/* Guest - protected mode (only used for AMD-V nested paging in 64 bits mode) */
221# define PGM_GST_TYPE PGM_TYPE_PROT
222# define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
223# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_PROT(name)
224# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
225# define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PD_PHYS
226# include "PGMGstDefs.h"
227# include "PGMAllBth.h"
228# undef BTH_PGMPOOLKIND_PT_FOR_PT
229# undef BTH_PGMPOOLKIND_ROOT
230# undef PGM_BTH_NAME
231# undef PGM_GST_TYPE
232# undef PGM_GST_NAME
233
234# ifdef VBOX_WITH_64_BITS_GUESTS
235/* Guest - AMD64 mode */
236# define PGM_GST_TYPE PGM_TYPE_AMD64
237# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
238# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
239# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
240# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
241# define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_64BIT_PML4
242# include "PGMGstDefs.h"
243# include "PGMAllGst.h"
244# include "PGMAllBth.h"
245# undef BTH_PGMPOOLKIND_PT_FOR_BIG
246# undef BTH_PGMPOOLKIND_PT_FOR_PT
247# undef BTH_PGMPOOLKIND_ROOT
248# undef PGM_BTH_NAME
249# undef PGM_GST_TYPE
250# undef PGM_GST_NAME
251# endif /* VBOX_WITH_64_BITS_GUESTS */
252
253# undef PGM_SHW_TYPE
254# undef PGM_SHW_NAME
255
256
257/*
258 * Shadow - Nested paging mode
259 */
260# define PGM_SHW_TYPE PGM_TYPE_NESTED
261# define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED(name)
262# include "PGMAllShw.h"
263
264/* Guest - real mode */
265# define PGM_GST_TYPE PGM_TYPE_REAL
266# define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
267# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_REAL(name)
268# include "PGMGstDefs.h"
269# include "PGMAllBth.h"
270# undef PGM_BTH_NAME
271# undef PGM_GST_TYPE
272# undef PGM_GST_NAME
273
274/* Guest - protected mode */
275# define PGM_GST_TYPE PGM_TYPE_PROT
276# define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
277# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PROT(name)
278# include "PGMGstDefs.h"
279# include "PGMAllBth.h"
280# undef PGM_BTH_NAME
281# undef PGM_GST_TYPE
282# undef PGM_GST_NAME
283
284/* Guest - 32-bit mode */
285# define PGM_GST_TYPE PGM_TYPE_32BIT
286# define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
287# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT(name)
288# include "PGMGstDefs.h"
289# include "PGMAllBth.h"
290# undef PGM_BTH_NAME
291# undef PGM_GST_TYPE
292# undef PGM_GST_NAME
293
294/* Guest - PAE mode */
295# define PGM_GST_TYPE PGM_TYPE_PAE
296# define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
297# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE(name)
298# include "PGMGstDefs.h"
299# include "PGMAllBth.h"
300# undef PGM_BTH_NAME
301# undef PGM_GST_TYPE
302# undef PGM_GST_NAME
303
304# ifdef VBOX_WITH_64_BITS_GUESTS
305/* Guest - AMD64 mode */
306# define PGM_GST_TYPE PGM_TYPE_AMD64
307# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
308# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64(name)
309# include "PGMGstDefs.h"
310# include "PGMAllBth.h"
311# undef PGM_BTH_NAME
312# undef PGM_GST_TYPE
313# undef PGM_GST_NAME
314# endif /* VBOX_WITH_64_BITS_GUESTS */
315
316# undef PGM_SHW_TYPE
317# undef PGM_SHW_NAME
318
319
320/*
321 * Shadow - EPT
322 */
323# define PGM_SHW_TYPE PGM_TYPE_EPT
324# define PGM_SHW_NAME(name) PGM_SHW_NAME_EPT(name)
325# include "PGMAllShw.h"
326
327/* Guest - real mode */
328# define PGM_GST_TYPE PGM_TYPE_REAL
329# define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
330# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_REAL(name)
331# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
332# include "PGMGstDefs.h"
333# include "PGMAllBth.h"
334# undef BTH_PGMPOOLKIND_PT_FOR_PT
335# undef PGM_BTH_NAME
336# undef PGM_GST_TYPE
337# undef PGM_GST_NAME
338
339/* Guest - protected mode */
340# define PGM_GST_TYPE PGM_TYPE_PROT
341# define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
342# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PROT(name)
343# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
344# include "PGMGstDefs.h"
345# include "PGMAllBth.h"
346# undef BTH_PGMPOOLKIND_PT_FOR_PT
347# undef PGM_BTH_NAME
348# undef PGM_GST_TYPE
349# undef PGM_GST_NAME
350
351/* Guest - 32-bit mode */
352# define PGM_GST_TYPE PGM_TYPE_32BIT
353# define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
354# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_32BIT(name)
355# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
356# include "PGMGstDefs.h"
357# include "PGMAllBth.h"
358# undef BTH_PGMPOOLKIND_PT_FOR_PT
359# undef PGM_BTH_NAME
360# undef PGM_GST_TYPE
361# undef PGM_GST_NAME
362
363/* Guest - PAE mode */
364# define PGM_GST_TYPE PGM_TYPE_PAE
365# define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
366# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PAE(name)
367# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
368# include "PGMGstDefs.h"
369# include "PGMAllBth.h"
370# undef BTH_PGMPOOLKIND_PT_FOR_PT
371# undef PGM_BTH_NAME
372# undef PGM_GST_TYPE
373# undef PGM_GST_NAME
374
375# ifdef VBOX_WITH_64_BITS_GUESTS
376/* Guest - AMD64 mode */
377# define PGM_GST_TYPE PGM_TYPE_AMD64
378# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
379# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_AMD64(name)
380# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
381# include "PGMGstDefs.h"
382# include "PGMAllBth.h"
383# undef BTH_PGMPOOLKIND_PT_FOR_PT
384# undef PGM_BTH_NAME
385# undef PGM_GST_TYPE
386# undef PGM_GST_NAME
387# endif /* VBOX_WITH_64_BITS_GUESTS */
388
389# undef PGM_SHW_TYPE
390# undef PGM_SHW_NAME
391
392#endif /* !IN_RC */
393
394
395#ifndef IN_RING3
396/**
397 * #PF Handler.
398 *
399 * @returns VBox status code (appropriate for trap handling and GC return).
400 * @param pVCpu Pointer to the VMCPU.
401 * @param uErr The trap error code.
402 * @param pRegFrame Trap register frame.
403 * @param pvFault The fault address.
404 */
405VMMDECL(int) PGMTrap0eHandler(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
406{
407 PVM pVM = pVCpu->CTX_SUFF(pVM);
408
409 Log(("PGMTrap0eHandler: uErr=%RGx pvFault=%RGv eip=%04x:%RGv cr3=%RGp\n", uErr, pvFault, pRegFrame->cs.Sel, (RTGCPTR)pRegFrame->rip, (RTGCPHYS)CPUMGetGuestCR3(pVCpu)));
410 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0e, a);
411 STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = NULL; } );
412
413
414#ifdef VBOX_WITH_STATISTICS
415 /*
416 * Error code stats.
417 */
418 if (uErr & X86_TRAP_PF_US)
419 {
420 if (!(uErr & X86_TRAP_PF_P))
421 {
422 if (uErr & X86_TRAP_PF_RW)
423 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eUSNotPresentWrite);
424 else
425 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eUSNotPresentRead);
426 }
427 else if (uErr & X86_TRAP_PF_RW)
428 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eUSWrite);
429 else if (uErr & X86_TRAP_PF_RSVD)
430 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eUSReserved);
431 else if (uErr & X86_TRAP_PF_ID)
432 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eUSNXE);
433 else
434 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eUSRead);
435 }
436 else
437 { /* Supervisor */
438 if (!(uErr & X86_TRAP_PF_P))
439 {
440 if (uErr & X86_TRAP_PF_RW)
441 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eSVNotPresentWrite);
442 else
443 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eSVNotPresentRead);
444 }
445 else if (uErr & X86_TRAP_PF_RW)
446 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eSVWrite);
447 else if (uErr & X86_TRAP_PF_ID)
448 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eSNXE);
449 else if (uErr & X86_TRAP_PF_RSVD)
450 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eSVReserved);
451 }
452#endif /* VBOX_WITH_STATISTICS */
453
454 /*
455 * Call the worker.
456 */
457 bool fLockTaken = false;
458 int rc = PGM_BTH_PFN(Trap0eHandler, pVCpu)(pVCpu, uErr, pRegFrame, pvFault, &fLockTaken);
459 if (fLockTaken)
460 {
461 PGM_LOCK_ASSERT_OWNER(pVM);
462 pgmUnlock(pVM);
463 }
464 LogFlow(("PGMTrap0eHandler: uErr=%RGx pvFault=%RGv rc=%Rrc\n", uErr, pvFault, rc));
465
466 /*
467 * Return code tweaks.
468 */
469 if (rc != VINF_SUCCESS)
470 {
471 if (rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
472 rc = VINF_SUCCESS;
473
474# ifdef IN_RING0
475 /* Note: hack alert for difficult to reproduce problem. */
476 if ( rc == VERR_PAGE_NOT_PRESENT /* SMP only ; disassembly might fail. */
477 || rc == VERR_PAGE_TABLE_NOT_PRESENT /* seen with UNI & SMP */
478 || rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT /* seen with SMP */
479 || rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT) /* precaution */
480 {
481 Log(("WARNING: Unexpected VERR_PAGE_TABLE_NOT_PRESENT (%d) for page fault at %RGv error code %x (rip=%RGv)\n", rc, pvFault, uErr, pRegFrame->rip));
482 /* Some kind of inconsistency in the SMP case; it's safe to just execute the instruction again; not sure about single VCPU VMs though. */
483 rc = VINF_SUCCESS;
484 }
485# endif
486 }
487
488 STAM_STATS({ if (rc == VINF_EM_RAW_GUEST_TRAP) STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eGuestPF); });
489 STAM_STATS({ if (!pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution))
490 pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Misc; });
491 STAM_PROFILE_STOP_EX(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0e, pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution), a);
492 return rc;
493}
494#endif /* !IN_RING3 */
495
496
497/**
498 * Prefetch a page
499 *
500 * Typically used to sync commonly used pages before entering raw mode
501 * after a CR3 reload.
502 *
503 * @returns VBox status code suitable for scheduling.
504 * @retval VINF_SUCCESS on success.
505 * @retval VINF_PGM_SYNC_CR3 if we're out of shadow pages or something like that.
506 * @param pVCpu Pointer to the VMCPU.
507 * @param GCPtrPage Page to invalidate.
508 */
509VMMDECL(int) PGMPrefetchPage(PVMCPU pVCpu, RTGCPTR GCPtrPage)
510{
511 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Prefetch), a);
512 int rc = PGM_BTH_PFN(PrefetchPage, pVCpu)(pVCpu, GCPtrPage);
513 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Prefetch), a);
514 AssertMsg(rc == VINF_SUCCESS || rc == VINF_PGM_SYNC_CR3 || RT_FAILURE(rc), ("rc=%Rrc\n", rc));
515 return rc;
516}
517
518
519/**
520 * Gets the mapping corresponding to the specified address (if any).
521 *
522 * @returns Pointer to the mapping.
523 * @returns NULL if not
524 *
525 * @param pVM Pointer to the VM.
526 * @param GCPtr The guest context pointer.
527 */
528PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr)
529{
530 PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
531 while (pMapping)
532 {
533 if ((uintptr_t)GCPtr < (uintptr_t)pMapping->GCPtr)
534 break;
535 if ((uintptr_t)GCPtr - (uintptr_t)pMapping->GCPtr < pMapping->cb)
536 return pMapping;
537 pMapping = pMapping->CTX_SUFF(pNext);
538 }
539 return NULL;
540}
541
542
543/**
544 * Verifies a range of pages for read or write access
545 *
546 * Only checks the guest's page tables
547 *
548 * @returns VBox status code.
549 * @param pVCpu Pointer to the VMCPU.
550 * @param Addr Guest virtual address to check
551 * @param cbSize Access size
552 * @param fAccess Access type (r/w, user/supervisor (X86_PTE_*))
553 * @remarks Current not in use.
554 */
555VMMDECL(int) PGMIsValidAccess(PVMCPU pVCpu, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess)
556{
557 /*
558 * Validate input.
559 */
560 if (fAccess & ~(X86_PTE_US | X86_PTE_RW))
561 {
562 AssertMsgFailed(("PGMIsValidAccess: invalid access type %08x\n", fAccess));
563 return VERR_INVALID_PARAMETER;
564 }
565
566 uint64_t fPage;
567 int rc = PGMGstGetPage(pVCpu, (RTGCPTR)Addr, &fPage, NULL);
568 if (RT_FAILURE(rc))
569 {
570 Log(("PGMIsValidAccess: access violation for %RGv rc=%d\n", Addr, rc));
571 return VINF_EM_RAW_GUEST_TRAP;
572 }
573
574 /*
575 * Check if the access would cause a page fault
576 *
577 * Note that hypervisor page directories are not present in the guest's tables, so this check
578 * is sufficient.
579 */
580 bool fWrite = !!(fAccess & X86_PTE_RW);
581 bool fUser = !!(fAccess & X86_PTE_US);
582 if ( !(fPage & X86_PTE_P)
583 || (fWrite && !(fPage & X86_PTE_RW))
584 || (fUser && !(fPage & X86_PTE_US)) )
585 {
586 Log(("PGMIsValidAccess: access violation for %RGv attr %#llx vs %d:%d\n", Addr, fPage, fWrite, fUser));
587 return VINF_EM_RAW_GUEST_TRAP;
588 }
589 if ( RT_SUCCESS(rc)
590 && PAGE_ADDRESS(Addr) != PAGE_ADDRESS(Addr + cbSize))
591 return PGMIsValidAccess(pVCpu, Addr + PAGE_SIZE, (cbSize > PAGE_SIZE) ? cbSize - PAGE_SIZE : 1, fAccess);
592 return rc;
593}
594
595
596/**
597 * Verifies a range of pages for read or write access
598 *
599 * Supports handling of pages marked for dirty bit tracking and CSAM
600 *
601 * @returns VBox status code.
602 * @param pVCpu Pointer to the VMCPU.
603 * @param Addr Guest virtual address to check
604 * @param cbSize Access size
605 * @param fAccess Access type (r/w, user/supervisor (X86_PTE_*))
606 */
607VMMDECL(int) PGMVerifyAccess(PVMCPU pVCpu, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess)
608{
609 PVM pVM = pVCpu->CTX_SUFF(pVM);
610
611 AssertMsg(!(fAccess & ~(X86_PTE_US | X86_PTE_RW)), ("PGMVerifyAccess: invalid access type %08x\n", fAccess));
612
613 /*
614 * Get going.
615 */
616 uint64_t fPageGst;
617 int rc = PGMGstGetPage(pVCpu, (RTGCPTR)Addr, &fPageGst, NULL);
618 if (RT_FAILURE(rc))
619 {
620 Log(("PGMVerifyAccess: access violation for %RGv rc=%d\n", Addr, rc));
621 return VINF_EM_RAW_GUEST_TRAP;
622 }
623
624 /*
625 * Check if the access would cause a page fault
626 *
627 * Note that hypervisor page directories are not present in the guest's tables, so this check
628 * is sufficient.
629 */
630 const bool fWrite = !!(fAccess & X86_PTE_RW);
631 const bool fUser = !!(fAccess & X86_PTE_US);
632 if ( !(fPageGst & X86_PTE_P)
633 || (fWrite && !(fPageGst & X86_PTE_RW))
634 || (fUser && !(fPageGst & X86_PTE_US)) )
635 {
636 Log(("PGMVerifyAccess: access violation for %RGv attr %#llx vs %d:%d\n", Addr, fPageGst, fWrite, fUser));
637 return VINF_EM_RAW_GUEST_TRAP;
638 }
639
640 if (!pVM->pgm.s.fNestedPaging)
641 {
642 /*
643 * Next step is to verify if we protected this page for dirty bit tracking or for CSAM scanning
644 */
645 rc = PGMShwGetPage(pVCpu, (RTGCPTR)Addr, NULL, NULL);
646 if ( rc == VERR_PAGE_NOT_PRESENT
647 || rc == VERR_PAGE_TABLE_NOT_PRESENT)
648 {
649 /*
650 * Page is not present in our page tables.
651 * Try to sync it!
652 */
653 Assert(X86_TRAP_PF_RW == X86_PTE_RW && X86_TRAP_PF_US == X86_PTE_US);
654 uint32_t uErr = fAccess & (X86_TRAP_PF_RW | X86_TRAP_PF_US);
655 rc = PGM_BTH_PFN(VerifyAccessSyncPage, pVCpu)(pVCpu, Addr, fPageGst, uErr);
656 if (rc != VINF_SUCCESS)
657 return rc;
658 }
659 else
660 AssertMsg(rc == VINF_SUCCESS, ("PGMShwGetPage %RGv failed with %Rrc\n", Addr, rc));
661 }
662
663#if 0 /* def VBOX_STRICT; triggers too often now */
664 /*
665 * This check is a bit paranoid, but useful.
666 */
667 /* Note! This will assert when writing to monitored pages (a bit annoying actually). */
668 uint64_t fPageShw;
669 rc = PGMShwGetPage(pVCpu, (RTGCPTR)Addr, &fPageShw, NULL);
670 if ( (rc == VERR_PAGE_NOT_PRESENT || RT_FAILURE(rc))
671 || (fWrite && !(fPageShw & X86_PTE_RW))
672 || (fUser && !(fPageShw & X86_PTE_US)) )
673 {
674 AssertMsgFailed(("Unexpected access violation for %RGv! rc=%Rrc write=%d user=%d\n",
675 Addr, rc, fWrite && !(fPageShw & X86_PTE_RW), fUser && !(fPageShw & X86_PTE_US)));
676 return VINF_EM_RAW_GUEST_TRAP;
677 }
678#endif
679
680 if ( RT_SUCCESS(rc)
681 && ( PAGE_ADDRESS(Addr) != PAGE_ADDRESS(Addr + cbSize - 1)
682 || Addr + cbSize < Addr))
683 {
684 /* Don't recursively call PGMVerifyAccess as we might run out of stack. */
685 for (;;)
686 {
687 Addr += PAGE_SIZE;
688 if (cbSize > PAGE_SIZE)
689 cbSize -= PAGE_SIZE;
690 else
691 cbSize = 1;
692 rc = PGMVerifyAccess(pVCpu, Addr, 1, fAccess);
693 if (rc != VINF_SUCCESS)
694 break;
695 if (PAGE_ADDRESS(Addr) == PAGE_ADDRESS(Addr + cbSize - 1))
696 break;
697 }
698 }
699 return rc;
700}
701
702
703/**
704 * Emulation of the invlpg instruction (HC only actually).
705 *
706 * @returns Strict VBox status code, special care required.
707 * @retval VINF_PGM_SYNC_CR3 - handled.
708 * @retval VINF_EM_RAW_EMULATE_INSTR - not handled (RC only).
709 * @retval VERR_REM_FLUSHED_PAGES_OVERFLOW - not handled.
710 *
711 * @param pVCpu Pointer to the VMCPU.
712 * @param GCPtrPage Page to invalidate.
713 *
714 * @remark ASSUMES the page table entry or page directory is valid. Fairly
715 * safe, but there could be edge cases!
716 *
717 * @todo Flush page or page directory only if necessary!
718 * @todo VBOXSTRICTRC
719 */
720VMMDECL(int) PGMInvalidatePage(PVMCPU pVCpu, RTGCPTR GCPtrPage)
721{
722 PVM pVM = pVCpu->CTX_SUFF(pVM);
723 int rc;
724 Log3(("PGMInvalidatePage: GCPtrPage=%RGv\n", GCPtrPage));
725
726#if !defined(IN_RING3) && defined(VBOX_WITH_REM)
727 /*
728 * Notify the recompiler so it can record this instruction.
729 */
730 REMNotifyInvalidatePage(pVM, GCPtrPage);
731#endif /* !IN_RING3 */
732
733
734#ifdef IN_RC
735 /*
736 * Check for conflicts and pending CR3 monitoring updates.
737 */
738 if (pgmMapAreMappingsFloating(pVM))
739 {
740 if ( pgmGetMapping(pVM, GCPtrPage)
741 && PGMGstGetPage(pVCpu, GCPtrPage, NULL, NULL) != VERR_PAGE_TABLE_NOT_PRESENT)
742 {
743 LogFlow(("PGMGCInvalidatePage: Conflict!\n"));
744 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
745 STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatRCInvlPgConflict);
746 return VINF_PGM_SYNC_CR3;
747 }
748
749 if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
750 {
751 LogFlow(("PGMGCInvalidatePage: PGM_SYNC_MONITOR_CR3 -> reinterpret instruction in R3\n"));
752 STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatRCInvlPgSyncMonCR3);
753 return VINF_EM_RAW_EMULATE_INSTR;
754 }
755 }
756#endif /* IN_RC */
757
758 /*
759 * Call paging mode specific worker.
760 */
761 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePage), a);
762 pgmLock(pVM);
763 rc = PGM_BTH_PFN(InvalidatePage, pVCpu)(pVCpu, GCPtrPage);
764 pgmUnlock(pVM);
765 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePage), a);
766
767#ifdef IN_RING3
768 /*
769 * Check if we have a pending update of the CR3 monitoring.
770 */
771 if ( RT_SUCCESS(rc)
772 && (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3))
773 {
774 pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
775 Assert(!pVM->pgm.s.fMappingsFixed); Assert(!pVM->pgm.s.fMappingsDisabled);
776 }
777
778# ifdef VBOX_WITH_RAW_MODE
779 /*
780 * Inform CSAM about the flush
781 *
782 * Note: This is to check if monitored pages have been changed; when we implement
783 * callbacks for virtual handlers, this is no longer required.
784 */
785 CSAMR3FlushPage(pVM, GCPtrPage);
786# endif
787#endif /* IN_RING3 */
788
789 /* Ignore all irrelevant error codes. */
790 if ( rc == VERR_PAGE_NOT_PRESENT
791 || rc == VERR_PAGE_TABLE_NOT_PRESENT
792 || rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT
793 || rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT)
794 rc = VINF_SUCCESS;
795
796 return rc;
797}
798
799
800/**
801 * Executes an instruction using the interpreter.
802 *
803 * @returns VBox status code (appropriate for trap handling and GC return).
804 * @param pVM Pointer to the VM.
805 * @param pVCpu Pointer to the VMCPU.
806 * @param pRegFrame Register frame.
807 * @param pvFault Fault address.
808 */
809VMMDECL(VBOXSTRICTRC) PGMInterpretInstruction(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
810{
811 VBOXSTRICTRC rc = EMInterpretInstruction(pVCpu, pRegFrame, pvFault);
812 if (rc == VERR_EM_INTERPRETER)
813 rc = VINF_EM_RAW_EMULATE_INSTR;
814 if (rc != VINF_SUCCESS)
815 Log(("PGMInterpretInstruction: returns %Rrc (pvFault=%RGv)\n", VBOXSTRICTRC_VAL(rc), pvFault));
816 return rc;
817}
818
819
820/**
821 * Gets effective page information (from the VMM page directory).
822 *
823 * @returns VBox status.
824 * @param pVCpu Pointer to the VMCPU.
825 * @param GCPtr Guest Context virtual address of the page.
826 * @param pfFlags Where to store the flags. These are X86_PTE_*.
827 * @param pHCPhys Where to store the HC physical address of the page.
828 * This is page aligned.
829 * @remark You should use PGMMapGetPage() for pages in a mapping.
830 */
831VMMDECL(int) PGMShwGetPage(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys)
832{
833 pgmLock(pVCpu->CTX_SUFF(pVM));
834 int rc = PGM_SHW_PFN(GetPage, pVCpu)(pVCpu, GCPtr, pfFlags, pHCPhys);
835 pgmUnlock(pVCpu->CTX_SUFF(pVM));
836 return rc;
837}
838
839
840/**
841 * Modify page flags for a range of pages in the shadow context.
842 *
843 * The existing flags are ANDed with the fMask and ORed with the fFlags.
844 *
845 * @returns VBox status code.
846 * @param pVCpu Pointer to the VMCPU.
847 * @param GCPtr Virtual address of the first page in the range.
848 * @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
849 * @param fMask The AND mask - page flags X86_PTE_*.
850 * Be very CAREFUL when ~'ing constants which could be 32-bit!
851 * @param fOpFlags A combination of the PGM_MK_PK_XXX flags.
852 * @remark You must use PGMMapModifyPage() for pages in a mapping.
853 */
854DECLINLINE(int) pdmShwModifyPage(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags)
855{
856 AssertMsg(!(fFlags & X86_PTE_PAE_PG_MASK), ("fFlags=%#llx\n", fFlags));
857 Assert(!(fOpFlags & ~(PGM_MK_PG_IS_MMIO2 | PGM_MK_PG_IS_WRITE_FAULT)));
858
859 GCPtr &= PAGE_BASE_GC_MASK; /** @todo this ain't necessary, right... */
860
861 PVM pVM = pVCpu->CTX_SUFF(pVM);
862 pgmLock(pVM);
863 int rc = PGM_SHW_PFN(ModifyPage, pVCpu)(pVCpu, GCPtr, PAGE_SIZE, fFlags, fMask, fOpFlags);
864 pgmUnlock(pVM);
865 return rc;
866}
867
868
869/**
870 * Changing the page flags for a single page in the shadow page tables so as to
871 * make it read-only.
872 *
873 * @returns VBox status code.
874 * @param pVCpu Pointer to the VMCPU.
875 * @param GCPtr Virtual address of the first page in the range.
876 * @param fOpFlags A combination of the PGM_MK_PK_XXX flags.
877 */
878VMMDECL(int) PGMShwMakePageReadonly(PVMCPU pVCpu, RTGCPTR GCPtr, uint32_t fOpFlags)
879{
880 return pdmShwModifyPage(pVCpu, GCPtr, 0, ~(uint64_t)X86_PTE_RW, fOpFlags);
881}
882
883
884/**
885 * Changing the page flags for a single page in the shadow page tables so as to
886 * make it writable.
887 *
888 * The call must know with 101% certainty that the guest page tables maps this
889 * as writable too. This function will deal shared, zero and write monitored
890 * pages.
891 *
892 * @returns VBox status code.
893 * @param pVCpu Pointer to the VMCPU.
894 * @param GCPtr Virtual address of the first page in the range.
895 * @param fMmio2 Set if it is an MMIO2 page.
896 * @param fOpFlags A combination of the PGM_MK_PK_XXX flags.
897 */
898VMMDECL(int) PGMShwMakePageWritable(PVMCPU pVCpu, RTGCPTR GCPtr, uint32_t fOpFlags)
899{
900 return pdmShwModifyPage(pVCpu, GCPtr, X86_PTE_RW, ~(uint64_t)0, fOpFlags);
901}
902
903
904/**
905 * Changing the page flags for a single page in the shadow page tables so as to
906 * make it not present.
907 *
908 * @returns VBox status code.
909 * @param pVCpu Pointer to the VMCPU.
910 * @param GCPtr Virtual address of the first page in the range.
911 * @param fOpFlags A combination of the PGM_MK_PG_XXX flags.
912 */
913VMMDECL(int) PGMShwMakePageNotPresent(PVMCPU pVCpu, RTGCPTR GCPtr, uint32_t fOpFlags)
914{
915 return pdmShwModifyPage(pVCpu, GCPtr, 0, 0, fOpFlags);
916}
917
918
919/**
920 * Gets the shadow page directory for the specified address, PAE.
921 *
922 * @returns Pointer to the shadow PD.
923 * @param pVCpu Pointer to the VMCPU.
924 * @param GCPtr The address.
925 * @param uGstPdpe Guest PDPT entry. Valid.
926 * @param ppPD Receives address of page directory
927 */
928int pgmShwSyncPaePDPtr(PVMCPU pVCpu, RTGCPTR GCPtr, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD)
929{
930 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
931 PX86PDPT pPdpt = pgmShwGetPaePDPTPtr(pVCpu);
932 PX86PDPE pPdpe = &pPdpt->a[iPdPt];
933 PVM pVM = pVCpu->CTX_SUFF(pVM);
934 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
935 PPGMPOOLPAGE pShwPage;
936 int rc;
937
938 PGM_LOCK_ASSERT_OWNER(pVM);
939
940 /* Allocate page directory if not present. */
941 if ( !pPdpe->n.u1Present
942 && !(pPdpe->u & X86_PDPE_PG_MASK))
943 {
944 RTGCPTR64 GCPdPt;
945 PGMPOOLKIND enmKind;
946
947 if (pVM->pgm.s.fNestedPaging || !CPUMIsGuestPagingEnabled(pVCpu))
948 {
949 /* AMD-V nested paging or real/protected mode without paging. */
950 GCPdPt = (RTGCPTR64)iPdPt << X86_PDPT_SHIFT;
951 enmKind = PGMPOOLKIND_PAE_PD_PHYS;
952 }
953 else
954 {
955 if (CPUMGetGuestCR4(pVCpu) & X86_CR4_PAE)
956 {
957 if (!(uGstPdpe & X86_PDPE_P))
958 {
959 /* PD not present; guest must reload CR3 to change it.
960 * No need to monitor anything in this case.
961 */
962 Assert(!HMIsEnabled(pVM));
963
964 GCPdPt = uGstPdpe & X86_PDPE_PG_MASK;
965 enmKind = PGMPOOLKIND_PAE_PD_PHYS;
966 uGstPdpe |= X86_PDPE_P;
967 }
968 else
969 {
970 GCPdPt = uGstPdpe & X86_PDPE_PG_MASK;
971 enmKind = PGMPOOLKIND_PAE_PD_FOR_PAE_PD;
972 }
973 }
974 else
975 {
976 GCPdPt = CPUMGetGuestCR3(pVCpu);
977 enmKind = (PGMPOOLKIND)(PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD + iPdPt);
978 }
979 }
980
981 /* Create a reference back to the PDPT by using the index in its shadow page. */
982 rc = pgmPoolAlloc(pVM, GCPdPt, enmKind, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
983 pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPdPt, false /*fLockPage*/,
984 &pShwPage);
985 AssertRCReturn(rc, rc);
986
987 /* The PD was cached or created; hook it up now. */
988 pPdpe->u |= pShwPage->Core.Key | (uGstPdpe & (X86_PDPE_P | X86_PDPE_A));
989
990# if defined(IN_RC)
991 /*
992 * In 32 bits PAE mode we *must* invalidate the TLB when changing a
993 * PDPT entry; the CPU fetches them only during cr3 load, so any
994 * non-present PDPT will continue to cause page faults.
995 */
996 ASMReloadCR3();
997# endif
998 PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdpe);
999 }
1000 else
1001 {
1002 pShwPage = pgmPoolGetPage(pPool, pPdpe->u & X86_PDPE_PG_MASK);
1003 AssertReturn(pShwPage, VERR_PGM_POOL_GET_PAGE_FAILED);
1004 Assert((pPdpe->u & X86_PDPE_PG_MASK) == pShwPage->Core.Key);
1005
1006 pgmPoolCacheUsed(pPool, pShwPage);
1007 }
1008 *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1009 return VINF_SUCCESS;
1010}
1011
1012
1013/**
1014 * Gets the pointer to the shadow page directory entry for an address, PAE.
1015 *
1016 * @returns Pointer to the PDE.
1017 * @param pVCpu The current CPU.
1018 * @param GCPtr The address.
1019 * @param ppShwPde Receives the address of the pgm pool page for the shadow page directory
1020 */
1021DECLINLINE(int) pgmShwGetPaePoolPagePD(PVMCPU pVCpu, RTGCPTR GCPtr, PPGMPOOLPAGE *ppShwPde)
1022{
1023 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
1024 PX86PDPT pPdpt = pgmShwGetPaePDPTPtr(pVCpu);
1025 PVM pVM = pVCpu->CTX_SUFF(pVM);
1026
1027 PGM_LOCK_ASSERT_OWNER(pVM);
1028
1029 AssertReturn(pPdpt, VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT); /* can't happen */
1030 if (!pPdpt->a[iPdPt].n.u1Present)
1031 {
1032 LogFlow(("pgmShwGetPaePoolPagePD: PD %d not present (%RX64)\n", iPdPt, pPdpt->a[iPdPt].u));
1033 return VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT;
1034 }
1035 AssertMsg(pPdpt->a[iPdPt].u & X86_PDPE_PG_MASK, ("GCPtr=%RGv\n", GCPtr));
1036
1037 /* Fetch the pgm pool shadow descriptor. */
1038 PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pVM->pgm.s.CTX_SUFF(pPool), pPdpt->a[iPdPt].u & X86_PDPE_PG_MASK);
1039 AssertReturn(pShwPde, VERR_PGM_POOL_GET_PAGE_FAILED);
1040
1041 *ppShwPde = pShwPde;
1042 return VINF_SUCCESS;
1043}
1044
1045#ifndef IN_RC
1046
1047/**
1048 * Syncs the SHADOW page directory pointer for the specified address.
1049 *
1050 * Allocates backing pages in case the PDPT or PML4 entry is missing.
1051 *
1052 * The caller is responsible for making sure the guest has a valid PD before
1053 * calling this function.
1054 *
1055 * @returns VBox status.
1056 * @param pVCpu Pointer to the VMCPU.
1057 * @param GCPtr The address.
1058 * @param uGstPml4e Guest PML4 entry (valid).
1059 * @param uGstPdpe Guest PDPT entry (valid).
1060 * @param ppPD Receives address of page directory
1061 */
1062static int pgmShwSyncLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, X86PGPAEUINT uGstPml4e, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD)
1063{
1064 PVM pVM = pVCpu->CTX_SUFF(pVM);
1065 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1066 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
1067 PX86PML4E pPml4e = pgmShwGetLongModePML4EPtr(pVCpu, iPml4);
1068 bool fNestedPagingOrNoGstPaging = pVM->pgm.s.fNestedPaging || !CPUMIsGuestPagingEnabled(pVCpu);
1069 PPGMPOOLPAGE pShwPage;
1070 int rc;
1071
1072 PGM_LOCK_ASSERT_OWNER(pVM);
1073
1074 /* Allocate page directory pointer table if not present. */
1075 if ( !pPml4e->n.u1Present
1076 && !(pPml4e->u & X86_PML4E_PG_MASK))
1077 {
1078 RTGCPTR64 GCPml4;
1079 PGMPOOLKIND enmKind;
1080
1081 Assert(pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
1082
1083 if (fNestedPagingOrNoGstPaging)
1084 {
1085 /* AMD-V nested paging or real/protected mode without paging */
1086 GCPml4 = (RTGCPTR64)iPml4 << X86_PML4_SHIFT;
1087 enmKind = PGMPOOLKIND_64BIT_PDPT_FOR_PHYS;
1088 }
1089 else
1090 {
1091 GCPml4 = uGstPml4e & X86_PML4E_PG_MASK;
1092 enmKind = PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT;
1093 }
1094
1095 /* Create a reference back to the PDPT by using the index in its shadow page. */
1096 rc = pgmPoolAlloc(pVM, GCPml4, enmKind, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
1097 pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPml4, false /*fLockPage*/,
1098 &pShwPage);
1099 AssertRCReturn(rc, rc);
1100 }
1101 else
1102 {
1103 pShwPage = pgmPoolGetPage(pPool, pPml4e->u & X86_PML4E_PG_MASK);
1104 AssertReturn(pShwPage, VERR_PGM_POOL_GET_PAGE_FAILED);
1105
1106 pgmPoolCacheUsed(pPool, pShwPage);
1107 }
1108 /* The PDPT was cached or created; hook it up now. */
1109 pPml4e->u |= pShwPage->Core.Key | (uGstPml4e & pVCpu->pgm.s.fGstAmd64ShadowedPml4eMask);
1110
1111 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1112 PX86PDPT pPdpt = (PX86PDPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1113 PX86PDPE pPdpe = &pPdpt->a[iPdPt];
1114
1115 /* Allocate page directory if not present. */
1116 if ( !pPdpe->n.u1Present
1117 && !(pPdpe->u & X86_PDPE_PG_MASK))
1118 {
1119 RTGCPTR64 GCPdPt;
1120 PGMPOOLKIND enmKind;
1121
1122 if (fNestedPagingOrNoGstPaging)
1123 {
1124 /* AMD-V nested paging or real/protected mode without paging */
1125 GCPdPt = (RTGCPTR64)iPdPt << X86_PDPT_SHIFT;
1126 enmKind = PGMPOOLKIND_64BIT_PD_FOR_PHYS;
1127 }
1128 else
1129 {
1130 GCPdPt = uGstPdpe & X86_PDPE_PG_MASK;
1131 enmKind = PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD;
1132 }
1133
1134 /* Create a reference back to the PDPT by using the index in its shadow page. */
1135 rc = pgmPoolAlloc(pVM, GCPdPt, enmKind, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
1136 pShwPage->idx, iPdPt, false /*fLockPage*/,
1137 &pShwPage);
1138 AssertRCReturn(rc, rc);
1139 }
1140 else
1141 {
1142 pShwPage = pgmPoolGetPage(pPool, pPdpe->u & X86_PDPE_PG_MASK);
1143 AssertReturn(pShwPage, VERR_PGM_POOL_GET_PAGE_FAILED);
1144
1145 pgmPoolCacheUsed(pPool, pShwPage);
1146 }
1147 /* The PD was cached or created; hook it up now. */
1148 pPdpe->u |= pShwPage->Core.Key | (uGstPdpe & pVCpu->pgm.s.fGstAmd64ShadowedPdpeMask);
1149
1150 *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1151 return VINF_SUCCESS;
1152}
1153
1154
1155/**
1156 * Gets the SHADOW page directory pointer for the specified address (long mode).
1157 *
1158 * @returns VBox status.
1159 * @param pVCpu Pointer to the VMCPU.
1160 * @param GCPtr The address.
1161 * @param ppPdpt Receives address of pdpt
1162 * @param ppPD Receives address of page directory
1163 */
1164DECLINLINE(int) pgmShwGetLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPT *ppPdpt, PX86PDPAE *ppPD)
1165{
1166 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
1167 PCX86PML4E pPml4e = pgmShwGetLongModePML4EPtr(pVCpu, iPml4);
1168
1169 PGM_LOCK_ASSERT_OWNER(pVCpu->CTX_SUFF(pVM));
1170
1171 AssertReturn(pPml4e, VERR_PGM_PML4_MAPPING);
1172 if (ppPml4e)
1173 *ppPml4e = (PX86PML4E)pPml4e;
1174
1175 Log4(("pgmShwGetLongModePDPtr %RGv (%RHv) %RX64\n", GCPtr, pPml4e, pPml4e->u));
1176
1177 if (!pPml4e->n.u1Present)
1178 return VERR_PAGE_MAP_LEVEL4_NOT_PRESENT;
1179
1180 PVM pVM = pVCpu->CTX_SUFF(pVM);
1181 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1182 PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPml4e->u & X86_PML4E_PG_MASK);
1183 AssertReturn(pShwPage, VERR_PGM_POOL_GET_PAGE_FAILED);
1184
1185 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1186 PCX86PDPT pPdpt = *ppPdpt = (PX86PDPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1187 if (!pPdpt->a[iPdPt].n.u1Present)
1188 return VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT;
1189
1190 pShwPage = pgmPoolGetPage(pPool, pPdpt->a[iPdPt].u & X86_PDPE_PG_MASK);
1191 AssertReturn(pShwPage, VERR_PGM_POOL_GET_PAGE_FAILED);
1192
1193 *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1194 Log4(("pgmShwGetLongModePDPtr %RGv -> *ppPD=%p PDE=%p/%RX64\n", GCPtr, *ppPD, &(*ppPD)->a[(GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK], (*ppPD)->a[(GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK].u));
1195 return VINF_SUCCESS;
1196}
1197
1198
1199/**
1200 * Syncs the SHADOW EPT page directory pointer for the specified address. Allocates
1201 * backing pages in case the PDPT or PML4 entry is missing.
1202 *
1203 * @returns VBox status.
1204 * @param pVCpu Pointer to the VMCPU.
1205 * @param GCPtr The address.
1206 * @param ppPdpt Receives address of pdpt
1207 * @param ppPD Receives address of page directory
1208 */
1209static int pgmShwGetEPTPDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PEPTPDPT *ppPdpt, PEPTPD *ppPD)
1210{
1211 PVM pVM = pVCpu->CTX_SUFF(pVM);
1212 const unsigned iPml4 = (GCPtr >> EPT_PML4_SHIFT) & EPT_PML4_MASK;
1213 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1214 PEPTPML4 pPml4;
1215 PEPTPML4E pPml4e;
1216 PPGMPOOLPAGE pShwPage;
1217 int rc;
1218
1219 Assert(pVM->pgm.s.fNestedPaging);
1220 PGM_LOCK_ASSERT_OWNER(pVM);
1221
1222 pPml4 = (PEPTPML4)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
1223 Assert(pPml4);
1224
1225 /* Allocate page directory pointer table if not present. */
1226 pPml4e = &pPml4->a[iPml4];
1227 if ( !pPml4e->n.u1Present
1228 && !(pPml4e->u & EPT_PML4E_PG_MASK))
1229 {
1230 Assert(!(pPml4e->u & EPT_PML4E_PG_MASK));
1231 RTGCPTR64 GCPml4 = (RTGCPTR64)iPml4 << EPT_PML4_SHIFT;
1232
1233 rc = pgmPoolAlloc(pVM, GCPml4, PGMPOOLKIND_EPT_PDPT_FOR_PHYS, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
1234 pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPml4, false /*fLockPage*/,
1235 &pShwPage);
1236 AssertRCReturn(rc, rc);
1237 }
1238 else
1239 {
1240 pShwPage = pgmPoolGetPage(pPool, pPml4e->u & EPT_PML4E_PG_MASK);
1241 AssertReturn(pShwPage, VERR_PGM_POOL_GET_PAGE_FAILED);
1242
1243 pgmPoolCacheUsed(pPool, pShwPage);
1244 }
1245 /* The PDPT was cached or created; hook it up now and fill with the default value. */
1246 pPml4e->u = pShwPage->Core.Key;
1247 pPml4e->n.u1Present = 1;
1248 pPml4e->n.u1Write = 1;
1249 pPml4e->n.u1Execute = 1;
1250
1251 const unsigned iPdPt = (GCPtr >> EPT_PDPT_SHIFT) & EPT_PDPT_MASK;
1252 PEPTPDPT pPdpt = (PEPTPDPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1253 PEPTPDPTE pPdpe = &pPdpt->a[iPdPt];
1254
1255 if (ppPdpt)
1256 *ppPdpt = pPdpt;
1257
1258 /* Allocate page directory if not present. */
1259 if ( !pPdpe->n.u1Present
1260 && !(pPdpe->u & EPT_PDPTE_PG_MASK))
1261 {
1262 RTGCPTR64 GCPdPt = (RTGCPTR64)iPdPt << EPT_PDPT_SHIFT;
1263 rc = pgmPoolAlloc(pVM, GCPdPt, PGMPOOLKIND_EPT_PD_FOR_PHYS, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
1264 pShwPage->idx, iPdPt, false /*fLockPage*/,
1265 &pShwPage);
1266 AssertRCReturn(rc, rc);
1267 }
1268 else
1269 {
1270 pShwPage = pgmPoolGetPage(pPool, pPdpe->u & EPT_PDPTE_PG_MASK);
1271 AssertReturn(pShwPage, VERR_PGM_POOL_GET_PAGE_FAILED);
1272
1273 pgmPoolCacheUsed(pPool, pShwPage);
1274 }
1275 /* The PD was cached or created; hook it up now and fill with the default value. */
1276 pPdpe->u = pShwPage->Core.Key;
1277 pPdpe->n.u1Present = 1;
1278 pPdpe->n.u1Write = 1;
1279 pPdpe->n.u1Execute = 1;
1280
1281 *ppPD = (PEPTPD)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1282 return VINF_SUCCESS;
1283}
1284
1285#endif /* IN_RC */
1286
1287#ifdef IN_RING0
1288/**
1289 * Synchronizes a range of nested page table entries.
1290 *
1291 * The caller must own the PGM lock.
1292 *
1293 * @param pVCpu The current CPU.
1294 * @param GCPhys Where to start.
1295 * @param cPages How many pages which entries should be synced.
1296 * @param enmShwPagingMode The shadow paging mode (PGMMODE_EPT for VT-x,
1297 * host paging mode for AMD-V).
1298 */
1299int pgmShwSyncNestedPageLocked(PVMCPU pVCpu, RTGCPHYS GCPhysFault, uint32_t cPages, PGMMODE enmShwPagingMode)
1300{
1301 PGM_LOCK_ASSERT_OWNER(pVCpu->CTX_SUFF(pVM));
1302
1303 int rc;
1304 switch (enmShwPagingMode)
1305 {
1306 case PGMMODE_32_BIT:
1307 {
1308 X86PDE PdeDummy = { X86_PDE_P | X86_PDE_US | X86_PDE_RW | X86_PDE_A };
1309 rc = PGM_BTH_NAME_32BIT_PROT(SyncPage)(pVCpu, PdeDummy, GCPhysFault, cPages, ~0U /*uErr*/);
1310 break;
1311 }
1312
1313 case PGMMODE_PAE:
1314 case PGMMODE_PAE_NX:
1315 {
1316 X86PDEPAE PdeDummy = { X86_PDE_P | X86_PDE_US | X86_PDE_RW | X86_PDE_A };
1317 rc = PGM_BTH_NAME_PAE_PROT(SyncPage)(pVCpu, PdeDummy, GCPhysFault, cPages, ~0U /*uErr*/);
1318 break;
1319 }
1320
1321 case PGMMODE_AMD64:
1322 case PGMMODE_AMD64_NX:
1323 {
1324 X86PDEPAE PdeDummy = { X86_PDE_P | X86_PDE_US | X86_PDE_RW | X86_PDE_A };
1325 rc = PGM_BTH_NAME_AMD64_PROT(SyncPage)(pVCpu, PdeDummy, GCPhysFault, cPages, ~0U /*uErr*/);
1326 break;
1327 }
1328
1329 case PGMMODE_EPT:
1330 {
1331 X86PDEPAE PdeDummy = { X86_PDE_P | X86_PDE_US | X86_PDE_RW | X86_PDE_A };
1332 rc = PGM_BTH_NAME_EPT_PROT(SyncPage)(pVCpu, PdeDummy, GCPhysFault, cPages, ~0U /*uErr*/);
1333 break;
1334 }
1335
1336 default:
1337 AssertMsgFailedReturn(("%d\n", enmShwPagingMode), VERR_IPE_NOT_REACHED_DEFAULT_CASE);
1338 }
1339 return rc;
1340}
1341#endif /* IN_RING0 */
1342
1343
1344/**
1345 * Gets effective Guest OS page information.
1346 *
1347 * When GCPtr is in a big page, the function will return as if it was a normal
1348 * 4KB page. If the need for distinguishing between big and normal page becomes
1349 * necessary at a later point, a PGMGstGetPage() will be created for that
1350 * purpose.
1351 *
1352 * @returns VBox status.
1353 * @param pVCpu The current CPU.
1354 * @param GCPtr Guest Context virtual address of the page.
1355 * @param pfFlags Where to store the flags. These are X86_PTE_*, even for big pages.
1356 * @param pGCPhys Where to store the GC physical address of the page.
1357 * This is page aligned. The fact that the
1358 */
1359VMMDECL(int) PGMGstGetPage(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys)
1360{
1361 VMCPU_ASSERT_EMT(pVCpu);
1362 return PGM_GST_PFN(GetPage, pVCpu)(pVCpu, GCPtr, pfFlags, pGCPhys);
1363}
1364
1365
1366/**
1367 * Checks if the page is present.
1368 *
1369 * @returns true if the page is present.
1370 * @returns false if the page is not present.
1371 * @param pVCpu Pointer to the VMCPU.
1372 * @param GCPtr Address within the page.
1373 */
1374VMMDECL(bool) PGMGstIsPagePresent(PVMCPU pVCpu, RTGCPTR GCPtr)
1375{
1376 VMCPU_ASSERT_EMT(pVCpu);
1377 int rc = PGMGstGetPage(pVCpu, GCPtr, NULL, NULL);
1378 return RT_SUCCESS(rc);
1379}
1380
1381
1382/**
1383 * Sets (replaces) the page flags for a range of pages in the guest's tables.
1384 *
1385 * @returns VBox status.
1386 * @param pVCpu Pointer to the VMCPU.
1387 * @param GCPtr The address of the first page.
1388 * @param cb The size of the range in bytes.
1389 * @param fFlags Page flags X86_PTE_*, excluding the page mask of course.
1390 */
1391VMMDECL(int) PGMGstSetPage(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags)
1392{
1393 VMCPU_ASSERT_EMT(pVCpu);
1394 return PGMGstModifyPage(pVCpu, GCPtr, cb, fFlags, 0);
1395}
1396
1397
1398/**
1399 * Modify page flags for a range of pages in the guest's tables
1400 *
1401 * The existing flags are ANDed with the fMask and ORed with the fFlags.
1402 *
1403 * @returns VBox status code.
1404 * @param pVCpu Pointer to the VMCPU.
1405 * @param GCPtr Virtual address of the first page in the range.
1406 * @param cb Size (in bytes) of the range to apply the modification to.
1407 * @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
1408 * @param fMask The AND mask - page flags X86_PTE_*, excluding the page mask of course.
1409 * Be very CAREFUL when ~'ing constants which could be 32-bit!
1410 */
1411VMMDECL(int) PGMGstModifyPage(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
1412{
1413 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,GstModifyPage), a);
1414 VMCPU_ASSERT_EMT(pVCpu);
1415
1416 /*
1417 * Validate input.
1418 */
1419 AssertMsg(!(fFlags & X86_PTE_PAE_PG_MASK), ("fFlags=%#llx\n", fFlags));
1420 Assert(cb);
1421
1422 LogFlow(("PGMGstModifyPage %RGv %d bytes fFlags=%08llx fMask=%08llx\n", GCPtr, cb, fFlags, fMask));
1423
1424 /*
1425 * Adjust input.
1426 */
1427 cb += GCPtr & PAGE_OFFSET_MASK;
1428 cb = RT_ALIGN_Z(cb, PAGE_SIZE);
1429 GCPtr = (GCPtr & PAGE_BASE_GC_MASK);
1430
1431 /*
1432 * Call worker.
1433 */
1434 int rc = PGM_GST_PFN(ModifyPage, pVCpu)(pVCpu, GCPtr, cb, fFlags, fMask);
1435
1436 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,GstModifyPage), a);
1437 return rc;
1438}
1439
1440
1441#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
1442
1443/**
1444 * Performs the lazy mapping of the 32-bit guest PD.
1445 *
1446 * @returns VBox status code.
1447 * @param pVCpu The current CPU.
1448 * @param ppPd Where to return the pointer to the mapping. This is
1449 * always set.
1450 */
1451int pgmGstLazyMap32BitPD(PVMCPU pVCpu, PX86PD *ppPd)
1452{
1453 PVM pVM = pVCpu->CTX_SUFF(pVM);
1454 pgmLock(pVM);
1455
1456 Assert(!pVCpu->pgm.s.CTX_SUFF(pGst32BitPd));
1457
1458 RTGCPHYS GCPhysCR3 = pVCpu->pgm.s.GCPhysCR3 & X86_CR3_PAGE_MASK;
1459 PPGMPAGE pPage;
1460 int rc = pgmPhysGetPageEx(pVM, GCPhysCR3, &pPage);
1461 if (RT_SUCCESS(rc))
1462 {
1463 RTHCPTR HCPtrGuestCR3;
1464 rc = pgmPhysGCPhys2CCPtrInternalDepr(pVM, pPage, GCPhysCR3, (void **)&HCPtrGuestCR3);
1465 if (RT_SUCCESS(rc))
1466 {
1467 pVCpu->pgm.s.pGst32BitPdR3 = (R3PTRTYPE(PX86PD))HCPtrGuestCR3;
1468# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1469 pVCpu->pgm.s.pGst32BitPdR0 = (R0PTRTYPE(PX86PD))HCPtrGuestCR3;
1470# endif
1471 *ppPd = (PX86PD)HCPtrGuestCR3;
1472
1473 pgmUnlock(pVM);
1474 return VINF_SUCCESS;
1475 }
1476
1477 AssertRC(rc);
1478 }
1479 pgmUnlock(pVM);
1480
1481 *ppPd = NULL;
1482 return rc;
1483}
1484
1485
1486/**
1487 * Performs the lazy mapping of the PAE guest PDPT.
1488 *
1489 * @returns VBox status code.
1490 * @param pVCpu The current CPU.
1491 * @param ppPdpt Where to return the pointer to the mapping. This is
1492 * always set.
1493 */
1494int pgmGstLazyMapPaePDPT(PVMCPU pVCpu, PX86PDPT *ppPdpt)
1495{
1496 Assert(!pVCpu->pgm.s.CTX_SUFF(pGstPaePdpt));
1497 PVM pVM = pVCpu->CTX_SUFF(pVM);
1498 pgmLock(pVM);
1499
1500 RTGCPHYS GCPhysCR3 = pVCpu->pgm.s.GCPhysCR3 & X86_CR3_PAE_PAGE_MASK;
1501 PPGMPAGE pPage;
1502 int rc = pgmPhysGetPageEx(pVM, GCPhysCR3, &pPage);
1503 if (RT_SUCCESS(rc))
1504 {
1505 RTHCPTR HCPtrGuestCR3;
1506 rc = pgmPhysGCPhys2CCPtrInternalDepr(pVM, pPage, GCPhysCR3, (void **)&HCPtrGuestCR3);
1507 if (RT_SUCCESS(rc))
1508 {
1509 pVCpu->pgm.s.pGstPaePdptR3 = (R3PTRTYPE(PX86PDPT))HCPtrGuestCR3;
1510# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1511 pVCpu->pgm.s.pGstPaePdptR0 = (R0PTRTYPE(PX86PDPT))HCPtrGuestCR3;
1512# endif
1513 *ppPdpt = (PX86PDPT)HCPtrGuestCR3;
1514
1515 pgmUnlock(pVM);
1516 return VINF_SUCCESS;
1517 }
1518
1519 AssertRC(rc);
1520 }
1521
1522 pgmUnlock(pVM);
1523 *ppPdpt = NULL;
1524 return rc;
1525}
1526
1527
1528/**
1529 * Performs the lazy mapping / updating of a PAE guest PD.
1530 *
1531 * @returns Pointer to the mapping.
1532 * @returns VBox status code.
1533 * @param pVCpu The current CPU.
1534 * @param iPdpt Which PD entry to map (0..3).
1535 * @param ppPd Where to return the pointer to the mapping. This is
1536 * always set.
1537 */
1538int pgmGstLazyMapPaePD(PVMCPU pVCpu, uint32_t iPdpt, PX86PDPAE *ppPd)
1539{
1540 PVM pVM = pVCpu->CTX_SUFF(pVM);
1541 pgmLock(pVM);
1542
1543 PX86PDPT pGuestPDPT = pVCpu->pgm.s.CTX_SUFF(pGstPaePdpt);
1544 Assert(pGuestPDPT);
1545 Assert(pGuestPDPT->a[iPdpt].n.u1Present);
1546 RTGCPHYS GCPhys = pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK;
1547 bool const fChanged = pVCpu->pgm.s.aGCPhysGstPaePDs[iPdpt] != GCPhys;
1548
1549 PPGMPAGE pPage;
1550 int rc = pgmPhysGetPageEx(pVM, GCPhys, &pPage);
1551 if (RT_SUCCESS(rc))
1552 {
1553 RTRCPTR RCPtr = NIL_RTRCPTR;
1554 RTHCPTR HCPtr = NIL_RTHCPTR;
1555#if !defined(IN_RC) && !defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1556 rc = pgmPhysGCPhys2CCPtrInternalDepr(pVM, pPage, GCPhys, &HCPtr);
1557 AssertRC(rc);
1558#endif
1559 if (RT_SUCCESS(rc) && fChanged)
1560 {
1561 RCPtr = (RTRCPTR)(RTRCUINTPTR)(pVM->pgm.s.GCPtrCR3Mapping + (1 + iPdpt) * PAGE_SIZE);
1562 rc = PGMMap(pVM, (RTRCUINTPTR)RCPtr, PGM_PAGE_GET_HCPHYS(pPage), PAGE_SIZE, 0);
1563 }
1564 if (RT_SUCCESS(rc))
1565 {
1566 pVCpu->pgm.s.apGstPaePDsR3[iPdpt] = (R3PTRTYPE(PX86PDPAE))HCPtr;
1567# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1568 pVCpu->pgm.s.apGstPaePDsR0[iPdpt] = (R0PTRTYPE(PX86PDPAE))HCPtr;
1569# endif
1570 if (fChanged)
1571 {
1572 pVCpu->pgm.s.aGCPhysGstPaePDs[iPdpt] = GCPhys;
1573 pVCpu->pgm.s.apGstPaePDsRC[iPdpt] = (RCPTRTYPE(PX86PDPAE))RCPtr;
1574 }
1575
1576 *ppPd = pVCpu->pgm.s.CTX_SUFF(apGstPaePDs)[iPdpt];
1577 pgmUnlock(pVM);
1578 return VINF_SUCCESS;
1579 }
1580 }
1581
1582 /* Invalid page or some failure, invalidate the entry. */
1583 pVCpu->pgm.s.aGCPhysGstPaePDs[iPdpt] = NIL_RTGCPHYS;
1584 pVCpu->pgm.s.apGstPaePDsR3[iPdpt] = 0;
1585# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1586 pVCpu->pgm.s.apGstPaePDsR0[iPdpt] = 0;
1587# endif
1588 pVCpu->pgm.s.apGstPaePDsRC[iPdpt] = 0;
1589
1590 pgmUnlock(pVM);
1591 return rc;
1592}
1593
1594#endif /* !VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
1595#if !defined(IN_RC) && !defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1596/**
1597 * Performs the lazy mapping of the 32-bit guest PD.
1598 *
1599 * @returns VBox status code.
1600 * @param pVCpu The current CPU.
1601 * @param ppPml4 Where to return the pointer to the mapping. This will
1602 * always be set.
1603 */
1604int pgmGstLazyMapPml4(PVMCPU pVCpu, PX86PML4 *ppPml4)
1605{
1606 Assert(!pVCpu->pgm.s.CTX_SUFF(pGstAmd64Pml4));
1607 PVM pVM = pVCpu->CTX_SUFF(pVM);
1608 pgmLock(pVM);
1609
1610 RTGCPHYS GCPhysCR3 = pVCpu->pgm.s.GCPhysCR3 & X86_CR3_AMD64_PAGE_MASK;
1611 PPGMPAGE pPage;
1612 int rc = pgmPhysGetPageEx(pVM, GCPhysCR3, &pPage);
1613 if (RT_SUCCESS(rc))
1614 {
1615 RTHCPTR HCPtrGuestCR3;
1616 rc = pgmPhysGCPhys2CCPtrInternalDepr(pVM, pPage, GCPhysCR3, (void **)&HCPtrGuestCR3);
1617 if (RT_SUCCESS(rc))
1618 {
1619 pVCpu->pgm.s.pGstAmd64Pml4R3 = (R3PTRTYPE(PX86PML4))HCPtrGuestCR3;
1620# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1621 pVCpu->pgm.s.pGstAmd64Pml4R0 = (R0PTRTYPE(PX86PML4))HCPtrGuestCR3;
1622# endif
1623 *ppPml4 = (PX86PML4)HCPtrGuestCR3;
1624
1625 pgmUnlock(pVM);
1626 return VINF_SUCCESS;
1627 }
1628 }
1629
1630 pgmUnlock(pVM);
1631 *ppPml4 = NULL;
1632 return rc;
1633}
1634#endif
1635
1636
1637/**
1638 * Gets the PAE PDPEs values cached by the CPU.
1639 *
1640 * @returns VBox status code.
1641 * @param pVCpu Pointer to the VMCPU.
1642 * @param paPdpes Where to return the four PDPEs. The array
1643 * pointed to must have 4 entries.
1644 */
1645VMM_INT_DECL(int) PGMGstGetPaePdpes(PVMCPU pVCpu, PX86PDPE paPdpes)
1646{
1647 Assert(pVCpu->pgm.s.enmShadowMode == PGMMODE_EPT);
1648
1649 paPdpes[0] = pVCpu->pgm.s.aGstPaePdpeRegs[0];
1650 paPdpes[1] = pVCpu->pgm.s.aGstPaePdpeRegs[1];
1651 paPdpes[2] = pVCpu->pgm.s.aGstPaePdpeRegs[2];
1652 paPdpes[3] = pVCpu->pgm.s.aGstPaePdpeRegs[3];
1653 return VINF_SUCCESS;
1654}
1655
1656
1657/**
1658 * Sets the PAE PDPEs values cached by the CPU.
1659 *
1660 * @remarks This must be called *AFTER* PGMUpdateCR3.
1661 *
1662 * @returns VBox status code.
1663 * @param pVCpu Pointer to the VMCPU.
1664 * @param paPdpes The four PDPE values. The array pointed to must
1665 * have exactly 4 entries.
1666 *
1667 * @remarks No-long-jump zone!!!
1668 */
1669VMM_INT_DECL(int) PGMGstUpdatePaePdpes(PVMCPU pVCpu, PCX86PDPE paPdpes)
1670{
1671 Assert(pVCpu->pgm.s.enmShadowMode == PGMMODE_EPT);
1672
1673 for (unsigned i = 0; i < RT_ELEMENTS(pVCpu->pgm.s.aGstPaePdpeRegs); i++)
1674 {
1675 if (pVCpu->pgm.s.aGstPaePdpeRegs[i].u != paPdpes[i].u)
1676 {
1677 pVCpu->pgm.s.aGstPaePdpeRegs[i] = paPdpes[i];
1678
1679 /* Force lazy remapping if it changed in any way. */
1680 pVCpu->pgm.s.apGstPaePDsR3[i] = 0;
1681# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1682 pVCpu->pgm.s.apGstPaePDsR0[i] = 0;
1683# endif
1684 pVCpu->pgm.s.apGstPaePDsRC[i] = 0;
1685 pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
1686 }
1687 }
1688
1689 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES);
1690 return VINF_SUCCESS;
1691}
1692
1693
1694/**
1695 * Gets the current CR3 register value for the shadow memory context.
1696 * @returns CR3 value.
1697 * @param pVCpu Pointer to the VMCPU.
1698 */
1699VMMDECL(RTHCPHYS) PGMGetHyperCR3(PVMCPU pVCpu)
1700{
1701 PPGMPOOLPAGE pPoolPage = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
1702 AssertPtrReturn(pPoolPage, 0);
1703 return pPoolPage->Core.Key;
1704}
1705
1706
1707/**
1708 * Gets the current CR3 register value for the nested memory context.
1709 * @returns CR3 value.
1710 * @param pVCpu Pointer to the VMCPU.
1711 */
1712VMMDECL(RTHCPHYS) PGMGetNestedCR3(PVMCPU pVCpu, PGMMODE enmShadowMode)
1713{
1714 NOREF(enmShadowMode);
1715 Assert(pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
1716 return pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->Core.Key;
1717}
1718
1719
1720/**
1721 * Gets the current CR3 register value for the HC intermediate memory context.
1722 * @returns CR3 value.
1723 * @param pVM Pointer to the VM.
1724 */
1725VMMDECL(RTHCPHYS) PGMGetInterHCCR3(PVM pVM)
1726{
1727 switch (pVM->pgm.s.enmHostMode)
1728 {
1729 case SUPPAGINGMODE_32_BIT:
1730 case SUPPAGINGMODE_32_BIT_GLOBAL:
1731 return pVM->pgm.s.HCPhysInterPD;
1732
1733 case SUPPAGINGMODE_PAE:
1734 case SUPPAGINGMODE_PAE_GLOBAL:
1735 case SUPPAGINGMODE_PAE_NX:
1736 case SUPPAGINGMODE_PAE_GLOBAL_NX:
1737 return pVM->pgm.s.HCPhysInterPaePDPT;
1738
1739 case SUPPAGINGMODE_AMD64:
1740 case SUPPAGINGMODE_AMD64_GLOBAL:
1741 case SUPPAGINGMODE_AMD64_NX:
1742 case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1743 return pVM->pgm.s.HCPhysInterPaePDPT;
1744
1745 default:
1746 AssertMsgFailed(("enmHostMode=%d\n", pVM->pgm.s.enmHostMode));
1747 return NIL_RTHCPHYS;
1748 }
1749}
1750
1751
1752/**
1753 * Gets the current CR3 register value for the RC intermediate memory context.
1754 * @returns CR3 value.
1755 * @param pVM Pointer to the VM.
1756 * @param pVCpu Pointer to the VMCPU.
1757 */
1758VMMDECL(RTHCPHYS) PGMGetInterRCCR3(PVM pVM, PVMCPU pVCpu)
1759{
1760 switch (pVCpu->pgm.s.enmShadowMode)
1761 {
1762 case PGMMODE_32_BIT:
1763 return pVM->pgm.s.HCPhysInterPD;
1764
1765 case PGMMODE_PAE:
1766 case PGMMODE_PAE_NX:
1767 return pVM->pgm.s.HCPhysInterPaePDPT;
1768
1769 case PGMMODE_AMD64:
1770 case PGMMODE_AMD64_NX:
1771 return pVM->pgm.s.HCPhysInterPaePML4;
1772
1773 case PGMMODE_EPT:
1774 case PGMMODE_NESTED:
1775 return 0; /* not relevant */
1776
1777 default:
1778 AssertMsgFailed(("enmShadowMode=%d\n", pVCpu->pgm.s.enmShadowMode));
1779 return NIL_RTHCPHYS;
1780 }
1781}
1782
1783
1784/**
1785 * Gets the CR3 register value for the 32-Bit intermediate memory context.
1786 * @returns CR3 value.
1787 * @param pVM Pointer to the VM.
1788 */
1789VMMDECL(RTHCPHYS) PGMGetInter32BitCR3(PVM pVM)
1790{
1791 return pVM->pgm.s.HCPhysInterPD;
1792}
1793
1794
1795/**
1796 * Gets the CR3 register value for the PAE intermediate memory context.
1797 * @returns CR3 value.
1798 * @param pVM Pointer to the VM.
1799 */
1800VMMDECL(RTHCPHYS) PGMGetInterPaeCR3(PVM pVM)
1801{
1802 return pVM->pgm.s.HCPhysInterPaePDPT;
1803}
1804
1805
1806/**
1807 * Gets the CR3 register value for the AMD64 intermediate memory context.
1808 * @returns CR3 value.
1809 * @param pVM Pointer to the VM.
1810 */
1811VMMDECL(RTHCPHYS) PGMGetInterAmd64CR3(PVM pVM)
1812{
1813 return pVM->pgm.s.HCPhysInterPaePML4;
1814}
1815
1816
1817/**
1818 * Performs and schedules necessary updates following a CR3 load or reload.
1819 *
1820 * This will normally involve mapping the guest PD or nPDPT
1821 *
1822 * @returns VBox status code.
1823 * @retval VINF_PGM_SYNC_CR3 if monitoring requires a CR3 sync. This can
1824 * safely be ignored and overridden since the FF will be set too then.
1825 * @param pVCpu Pointer to the VMCPU.
1826 * @param cr3 The new cr3.
1827 * @param fGlobal Indicates whether this is a global flush or not.
1828 */
1829VMMDECL(int) PGMFlushTLB(PVMCPU pVCpu, uint64_t cr3, bool fGlobal)
1830{
1831 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FlushTLB), a);
1832 PVM pVM = pVCpu->CTX_SUFF(pVM);
1833
1834 VMCPU_ASSERT_EMT(pVCpu);
1835
1836 /*
1837 * Always flag the necessary updates; necessary for hardware acceleration
1838 */
1839 /** @todo optimize this, it shouldn't always be necessary. */
1840 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
1841 if (fGlobal)
1842 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
1843 LogFlow(("PGMFlushTLB: cr3=%RX64 OldCr3=%RX64 fGlobal=%d\n", cr3, pVCpu->pgm.s.GCPhysCR3, fGlobal));
1844
1845 /*
1846 * Remap the CR3 content and adjust the monitoring if CR3 was actually changed.
1847 */
1848 int rc = VINF_SUCCESS;
1849 RTGCPHYS GCPhysCR3;
1850 switch (pVCpu->pgm.s.enmGuestMode)
1851 {
1852 case PGMMODE_PAE:
1853 case PGMMODE_PAE_NX:
1854 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAE_PAGE_MASK);
1855 break;
1856 case PGMMODE_AMD64:
1857 case PGMMODE_AMD64_NX:
1858 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_AMD64_PAGE_MASK);
1859 break;
1860 default:
1861 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAGE_MASK);
1862 break;
1863 }
1864 PGM_A20_APPLY_TO_VAR(pVCpu, GCPhysCR3);
1865
1866 if (pVCpu->pgm.s.GCPhysCR3 != GCPhysCR3)
1867 {
1868 RTGCPHYS GCPhysOldCR3 = pVCpu->pgm.s.GCPhysCR3;
1869 pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3;
1870 rc = PGM_BTH_PFN(MapCR3, pVCpu)(pVCpu, GCPhysCR3);
1871 if (RT_LIKELY(rc == VINF_SUCCESS))
1872 {
1873 if (pgmMapAreMappingsFloating(pVM))
1874 pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
1875 }
1876 else
1877 {
1878 AssertMsg(rc == VINF_PGM_SYNC_CR3, ("%Rrc\n", rc));
1879 Assert(VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL | VMCPU_FF_PGM_SYNC_CR3));
1880 pVCpu->pgm.s.GCPhysCR3 = GCPhysOldCR3;
1881 pVCpu->pgm.s.fSyncFlags |= PGM_SYNC_MAP_CR3;
1882 if (pgmMapAreMappingsFloating(pVM))
1883 pVCpu->pgm.s.fSyncFlags |= PGM_SYNC_MONITOR_CR3;
1884 }
1885
1886 if (fGlobal)
1887 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FlushTLBNewCR3Global));
1888 else
1889 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FlushTLBNewCR3));
1890 }
1891 else
1892 {
1893# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
1894 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1895 if (pPool->cDirtyPages)
1896 {
1897 pgmLock(pVM);
1898 pgmPoolResetDirtyPages(pVM);
1899 pgmUnlock(pVM);
1900 }
1901# endif
1902 /*
1903 * Check if we have a pending update of the CR3 monitoring.
1904 */
1905 if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
1906 {
1907 pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
1908 Assert(!pVM->pgm.s.fMappingsFixed); Assert(!pVM->pgm.s.fMappingsDisabled);
1909 }
1910 if (fGlobal)
1911 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FlushTLBSameCR3Global));
1912 else
1913 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FlushTLBSameCR3));
1914 }
1915
1916 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FlushTLB), a);
1917 return rc;
1918}
1919
1920
1921/**
1922 * Performs and schedules necessary updates following a CR3 load or reload when
1923 * using nested or extended paging.
1924 *
1925 * This API is an alternative to PDMFlushTLB that avoids actually flushing the
1926 * TLB and triggering a SyncCR3.
1927 *
1928 * This will normally involve mapping the guest PD or nPDPT
1929 *
1930 * @returns VBox status code.
1931 * @retval VINF_SUCCESS.
1932 * @retval (If applied when not in nested mode: VINF_PGM_SYNC_CR3 if monitoring
1933 * requires a CR3 sync. This can safely be ignored and overridden since
1934 * the FF will be set too then.)
1935 * @param pVCpu Pointer to the VMCPU.
1936 * @param cr3 The new cr3.
1937 */
1938VMMDECL(int) PGMUpdateCR3(PVMCPU pVCpu, uint64_t cr3)
1939{
1940 VMCPU_ASSERT_EMT(pVCpu);
1941 LogFlow(("PGMUpdateCR3: cr3=%RX64 OldCr3=%RX64\n", cr3, pVCpu->pgm.s.GCPhysCR3));
1942
1943 /* We assume we're only called in nested paging mode. */
1944 Assert(pVCpu->CTX_SUFF(pVM)->pgm.s.fNestedPaging || pVCpu->pgm.s.enmShadowMode == PGMMODE_EPT);
1945 Assert(pVCpu->CTX_SUFF(pVM)->pgm.s.fMappingsDisabled);
1946 Assert(!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3));
1947
1948 /*
1949 * Remap the CR3 content and adjust the monitoring if CR3 was actually changed.
1950 */
1951 int rc = VINF_SUCCESS;
1952 RTGCPHYS GCPhysCR3;
1953 switch (pVCpu->pgm.s.enmGuestMode)
1954 {
1955 case PGMMODE_PAE:
1956 case PGMMODE_PAE_NX:
1957 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAE_PAGE_MASK);
1958 break;
1959 case PGMMODE_AMD64:
1960 case PGMMODE_AMD64_NX:
1961 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_AMD64_PAGE_MASK);
1962 break;
1963 default:
1964 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAGE_MASK);
1965 break;
1966 }
1967 PGM_A20_APPLY_TO_VAR(pVCpu, GCPhysCR3);
1968
1969 if (pVCpu->pgm.s.GCPhysCR3 != GCPhysCR3)
1970 {
1971 pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3;
1972 rc = PGM_BTH_PFN(MapCR3, pVCpu)(pVCpu, GCPhysCR3);
1973 AssertRCSuccess(rc); /* Assumes VINF_PGM_SYNC_CR3 doesn't apply to nested paging. */ /** @todo this isn't true for the mac, but we need hw to test/fix this. */
1974 }
1975
1976 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_HM_UPDATE_CR3);
1977 return rc;
1978}
1979
1980
1981/**
1982 * Synchronize the paging structures.
1983 *
1984 * This function is called in response to the VM_FF_PGM_SYNC_CR3 and
1985 * VM_FF_PGM_SYNC_CR3_NONGLOBAL. Those two force action flags are set
1986 * in several places, most importantly whenever the CR3 is loaded.
1987 *
1988 * @returns VBox status code.
1989 * @param pVCpu Pointer to the VMCPU.
1990 * @param cr0 Guest context CR0 register
1991 * @param cr3 Guest context CR3 register
1992 * @param cr4 Guest context CR4 register
1993 * @param fGlobal Including global page directories or not
1994 */
1995VMMDECL(int) PGMSyncCR3(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
1996{
1997 int rc;
1998
1999 VMCPU_ASSERT_EMT(pVCpu);
2000
2001 /*
2002 * The pool may have pending stuff and even require a return to ring-3 to
2003 * clear the whole thing.
2004 */
2005 rc = pgmPoolSyncCR3(pVCpu);
2006 if (rc != VINF_SUCCESS)
2007 return rc;
2008
2009 /*
2010 * We might be called when we shouldn't.
2011 *
2012 * The mode switching will ensure that the PD is resynced after every mode
2013 * switch. So, if we find ourselves here when in protected or real mode
2014 * we can safely clear the FF and return immediately.
2015 */
2016 if (pVCpu->pgm.s.enmGuestMode <= PGMMODE_PROTECTED)
2017 {
2018 Assert((cr0 & (X86_CR0_PG | X86_CR0_PE)) != (X86_CR0_PG | X86_CR0_PE));
2019 Assert(!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL));
2020 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2021 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
2022 return VINF_SUCCESS;
2023 }
2024
2025 /* If global pages are not supported, then all flushes are global. */
2026 if (!(cr4 & X86_CR4_PGE))
2027 fGlobal = true;
2028 LogFlow(("PGMSyncCR3: cr0=%RX64 cr3=%RX64 cr4=%RX64 fGlobal=%d[%d,%d]\n", cr0, cr3, cr4, fGlobal,
2029 VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3), VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)));
2030
2031 /*
2032 * Check if we need to finish an aborted MapCR3 call (see PGMFlushTLB).
2033 * This should be done before SyncCR3.
2034 */
2035 if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MAP_CR3)
2036 {
2037 pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MAP_CR3;
2038
2039 RTGCPHYS GCPhysCR3Old = pVCpu->pgm.s.GCPhysCR3; NOREF(GCPhysCR3Old);
2040 RTGCPHYS GCPhysCR3;
2041 switch (pVCpu->pgm.s.enmGuestMode)
2042 {
2043 case PGMMODE_PAE:
2044 case PGMMODE_PAE_NX:
2045 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAE_PAGE_MASK);
2046 break;
2047 case PGMMODE_AMD64:
2048 case PGMMODE_AMD64_NX:
2049 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_AMD64_PAGE_MASK);
2050 break;
2051 default:
2052 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAGE_MASK);
2053 break;
2054 }
2055 PGM_A20_APPLY_TO_VAR(pVCpu, GCPhysCR3);
2056
2057 if (pVCpu->pgm.s.GCPhysCR3 != GCPhysCR3)
2058 {
2059 pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3;
2060 rc = PGM_BTH_PFN(MapCR3, pVCpu)(pVCpu, GCPhysCR3);
2061 }
2062
2063 /* Make sure we check for pending pgm pool syncs as we clear VMCPU_FF_PGM_SYNC_CR3 later on! */
2064 if ( rc == VINF_PGM_SYNC_CR3
2065 || (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL))
2066 {
2067 Log(("PGMSyncCR3: pending pgm pool sync after MapCR3!\n"));
2068#ifdef IN_RING3
2069 rc = pgmPoolSyncCR3(pVCpu);
2070#else
2071 if (rc == VINF_PGM_SYNC_CR3)
2072 pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3Old;
2073 return VINF_PGM_SYNC_CR3;
2074#endif
2075 }
2076 AssertRCReturn(rc, rc);
2077 AssertRCSuccessReturn(rc, VERR_IPE_UNEXPECTED_INFO_STATUS);
2078 }
2079
2080 /*
2081 * Let the 'Bth' function do the work and we'll just keep track of the flags.
2082 */
2083 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3), a);
2084 rc = PGM_BTH_PFN(SyncCR3, pVCpu)(pVCpu, cr0, cr3, cr4, fGlobal);
2085 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3), a);
2086 AssertMsg(rc == VINF_SUCCESS || rc == VINF_PGM_SYNC_CR3 || RT_FAILURE(rc), ("rc=%Rrc\n", rc));
2087 if (rc == VINF_SUCCESS)
2088 {
2089 if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL)
2090 {
2091 /* Go back to ring 3 if a pgm pool sync is again pending. */
2092 return VINF_PGM_SYNC_CR3;
2093 }
2094
2095 if (!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS))
2096 {
2097 Assert(!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL));
2098 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2099 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
2100 }
2101
2102 /*
2103 * Check if we have a pending update of the CR3 monitoring.
2104 */
2105 if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
2106 {
2107 pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
2108 Assert(!pVCpu->CTX_SUFF(pVM)->pgm.s.fMappingsFixed);
2109 Assert(!pVCpu->CTX_SUFF(pVM)->pgm.s.fMappingsDisabled);
2110 }
2111 }
2112
2113 /*
2114 * Now flush the CR3 (guest context).
2115 */
2116 if (rc == VINF_SUCCESS)
2117 PGM_INVL_VCPU_TLBS(pVCpu);
2118 return rc;
2119}
2120
2121
2122/**
2123 * Called whenever CR0 or CR4 in a way which may affect the paging mode.
2124 *
2125 * @returns VBox status code, with the following informational code for
2126 * VM scheduling.
2127 * @retval VINF_SUCCESS if the was no change, or it was successfully dealt with.
2128 * @retval VINF_PGM_CHANGE_MODE if we're in RC or R0 and the mode changes.
2129 * (I.e. not in R3.)
2130 * @retval VINF_EM_SUSPEND or VINF_EM_OFF on a fatal runtime error. (R3 only)
2131 *
2132 * @param pVCpu Pointer to the VMCPU.
2133 * @param cr0 The new cr0.
2134 * @param cr4 The new cr4.
2135 * @param efer The new extended feature enable register.
2136 */
2137VMMDECL(int) PGMChangeMode(PVMCPU pVCpu, uint64_t cr0, uint64_t cr4, uint64_t efer)
2138{
2139 PGMMODE enmGuestMode;
2140
2141 VMCPU_ASSERT_EMT(pVCpu);
2142
2143 /*
2144 * Calc the new guest mode.
2145 */
2146 if (!(cr0 & X86_CR0_PE))
2147 enmGuestMode = PGMMODE_REAL;
2148 else if (!(cr0 & X86_CR0_PG))
2149 enmGuestMode = PGMMODE_PROTECTED;
2150 else if (!(cr4 & X86_CR4_PAE))
2151 {
2152 bool const fPse = !!(cr4 & X86_CR4_PSE);
2153 if (pVCpu->pgm.s.fGst32BitPageSizeExtension != fPse)
2154 Log(("PGMChangeMode: CR4.PSE %d -> %d\n", pVCpu->pgm.s.fGst32BitPageSizeExtension, fPse));
2155 pVCpu->pgm.s.fGst32BitPageSizeExtension = fPse;
2156 enmGuestMode = PGMMODE_32_BIT;
2157 }
2158 else if (!(efer & MSR_K6_EFER_LME))
2159 {
2160 if (!(efer & MSR_K6_EFER_NXE))
2161 enmGuestMode = PGMMODE_PAE;
2162 else
2163 enmGuestMode = PGMMODE_PAE_NX;
2164 }
2165 else
2166 {
2167 if (!(efer & MSR_K6_EFER_NXE))
2168 enmGuestMode = PGMMODE_AMD64;
2169 else
2170 enmGuestMode = PGMMODE_AMD64_NX;
2171 }
2172
2173 /*
2174 * Did it change?
2175 */
2176 if (pVCpu->pgm.s.enmGuestMode == enmGuestMode)
2177 return VINF_SUCCESS;
2178
2179 /* Flush the TLB */
2180 PGM_INVL_VCPU_TLBS(pVCpu);
2181
2182#ifdef IN_RING3
2183 return PGMR3ChangeMode(pVCpu->CTX_SUFF(pVM), pVCpu, enmGuestMode);
2184#else
2185 LogFlow(("PGMChangeMode: returns VINF_PGM_CHANGE_MODE.\n"));
2186 return VINF_PGM_CHANGE_MODE;
2187#endif
2188}
2189
2190
2191/**
2192 * Gets the current guest paging mode.
2193 *
2194 * If you just need the CPU mode (real/protected/long), use CPUMGetGuestMode().
2195 *
2196 * @returns The current paging mode.
2197 * @param pVCpu Pointer to the VMCPU.
2198 */
2199VMMDECL(PGMMODE) PGMGetGuestMode(PVMCPU pVCpu)
2200{
2201 return pVCpu->pgm.s.enmGuestMode;
2202}
2203
2204
2205/**
2206 * Gets the current shadow paging mode.
2207 *
2208 * @returns The current paging mode.
2209 * @param pVCpu Pointer to the VMCPU.
2210 */
2211VMMDECL(PGMMODE) PGMGetShadowMode(PVMCPU pVCpu)
2212{
2213 return pVCpu->pgm.s.enmShadowMode;
2214}
2215
2216
2217/**
2218 * Gets the current host paging mode.
2219 *
2220 * @returns The current paging mode.
2221 * @param pVM Pointer to the VM.
2222 */
2223VMMDECL(PGMMODE) PGMGetHostMode(PVM pVM)
2224{
2225 switch (pVM->pgm.s.enmHostMode)
2226 {
2227 case SUPPAGINGMODE_32_BIT:
2228 case SUPPAGINGMODE_32_BIT_GLOBAL:
2229 return PGMMODE_32_BIT;
2230
2231 case SUPPAGINGMODE_PAE:
2232 case SUPPAGINGMODE_PAE_GLOBAL:
2233 return PGMMODE_PAE;
2234
2235 case SUPPAGINGMODE_PAE_NX:
2236 case SUPPAGINGMODE_PAE_GLOBAL_NX:
2237 return PGMMODE_PAE_NX;
2238
2239 case SUPPAGINGMODE_AMD64:
2240 case SUPPAGINGMODE_AMD64_GLOBAL:
2241 return PGMMODE_AMD64;
2242
2243 case SUPPAGINGMODE_AMD64_NX:
2244 case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2245 return PGMMODE_AMD64_NX;
2246
2247 default: AssertMsgFailed(("enmHostMode=%d\n", pVM->pgm.s.enmHostMode)); break;
2248 }
2249
2250 return PGMMODE_INVALID;
2251}
2252
2253
2254/**
2255 * Get mode name.
2256 *
2257 * @returns read-only name string.
2258 * @param enmMode The mode which name is desired.
2259 */
2260VMMDECL(const char *) PGMGetModeName(PGMMODE enmMode)
2261{
2262 switch (enmMode)
2263 {
2264 case PGMMODE_REAL: return "Real";
2265 case PGMMODE_PROTECTED: return "Protected";
2266 case PGMMODE_32_BIT: return "32-bit";
2267 case PGMMODE_PAE: return "PAE";
2268 case PGMMODE_PAE_NX: return "PAE+NX";
2269 case PGMMODE_AMD64: return "AMD64";
2270 case PGMMODE_AMD64_NX: return "AMD64+NX";
2271 case PGMMODE_NESTED: return "Nested";
2272 case PGMMODE_EPT: return "EPT";
2273 default: return "unknown mode value";
2274 }
2275}
2276
2277
2278
2279/**
2280 * Notification from CPUM that the EFER.NXE bit has changed.
2281 *
2282 * @param pVCpu The virtual CPU for which EFER changed.
2283 * @param fNxe The new NXE state.
2284 */
2285VMM_INT_DECL(void) PGMNotifyNxeChanged(PVMCPU pVCpu, bool fNxe)
2286{
2287/** @todo VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu); */
2288 Log(("PGMNotifyNxeChanged: fNxe=%RTbool\n", fNxe));
2289
2290 pVCpu->pgm.s.fNoExecuteEnabled = fNxe;
2291 if (fNxe)
2292 {
2293 /*pVCpu->pgm.s.fGst32BitMbzBigPdeMask - N/A */
2294 pVCpu->pgm.s.fGstPaeMbzPteMask &= ~X86_PTE_PAE_NX;
2295 pVCpu->pgm.s.fGstPaeMbzPdeMask &= ~X86_PDE_PAE_NX;
2296 pVCpu->pgm.s.fGstPaeMbzBigPdeMask &= ~X86_PDE2M_PAE_NX;
2297 /*pVCpu->pgm.s.fGstPaeMbzPdpeMask - N/A */
2298 pVCpu->pgm.s.fGstAmd64MbzPteMask &= ~X86_PTE_PAE_NX;
2299 pVCpu->pgm.s.fGstAmd64MbzPdeMask &= ~X86_PDE_PAE_NX;
2300 pVCpu->pgm.s.fGstAmd64MbzBigPdeMask &= ~X86_PDE2M_PAE_NX;
2301 pVCpu->pgm.s.fGstAmd64MbzPdpeMask &= ~X86_PDPE_LM_NX;
2302 pVCpu->pgm.s.fGstAmd64MbzBigPdpeMask &= ~X86_PDPE_LM_NX;
2303 pVCpu->pgm.s.fGstAmd64MbzPml4eMask &= ~X86_PML4E_NX;
2304
2305 pVCpu->pgm.s.fGst64ShadowedPteMask |= X86_PTE_PAE_NX;
2306 pVCpu->pgm.s.fGst64ShadowedPdeMask |= X86_PDE_PAE_NX;
2307 pVCpu->pgm.s.fGst64ShadowedBigPdeMask |= X86_PDE2M_PAE_NX;
2308 pVCpu->pgm.s.fGst64ShadowedBigPde4PteMask |= X86_PDE2M_PAE_NX;
2309 pVCpu->pgm.s.fGstAmd64ShadowedPdpeMask |= X86_PDPE_LM_NX;
2310 pVCpu->pgm.s.fGstAmd64ShadowedPml4eMask |= X86_PML4E_NX;
2311 }
2312 else
2313 {
2314 /*pVCpu->pgm.s.fGst32BitMbzBigPdeMask - N/A */
2315 pVCpu->pgm.s.fGstPaeMbzPteMask |= X86_PTE_PAE_NX;
2316 pVCpu->pgm.s.fGstPaeMbzPdeMask |= X86_PDE_PAE_NX;
2317 pVCpu->pgm.s.fGstPaeMbzBigPdeMask |= X86_PDE2M_PAE_NX;
2318 /*pVCpu->pgm.s.fGstPaeMbzPdpeMask -N/A */
2319 pVCpu->pgm.s.fGstAmd64MbzPteMask |= X86_PTE_PAE_NX;
2320 pVCpu->pgm.s.fGstAmd64MbzPdeMask |= X86_PDE_PAE_NX;
2321 pVCpu->pgm.s.fGstAmd64MbzBigPdeMask |= X86_PDE2M_PAE_NX;
2322 pVCpu->pgm.s.fGstAmd64MbzPdpeMask |= X86_PDPE_LM_NX;
2323 pVCpu->pgm.s.fGstAmd64MbzBigPdpeMask |= X86_PDPE_LM_NX;
2324 pVCpu->pgm.s.fGstAmd64MbzPml4eMask |= X86_PML4E_NX;
2325
2326 pVCpu->pgm.s.fGst64ShadowedPteMask &= ~X86_PTE_PAE_NX;
2327 pVCpu->pgm.s.fGst64ShadowedPdeMask &= ~X86_PDE_PAE_NX;
2328 pVCpu->pgm.s.fGst64ShadowedBigPdeMask &= ~X86_PDE2M_PAE_NX;
2329 pVCpu->pgm.s.fGst64ShadowedBigPde4PteMask &= ~X86_PDE2M_PAE_NX;
2330 pVCpu->pgm.s.fGstAmd64ShadowedPdpeMask &= ~X86_PDPE_LM_NX;
2331 pVCpu->pgm.s.fGstAmd64ShadowedPml4eMask &= ~X86_PML4E_NX;
2332 }
2333}
2334
2335
2336/**
2337 * Check if any pgm pool pages are marked dirty (not monitored)
2338 *
2339 * @returns bool locked/not locked
2340 * @param pVM Pointer to the VM.
2341 */
2342VMMDECL(bool) PGMHasDirtyPages(PVM pVM)
2343{
2344 return pVM->pgm.s.CTX_SUFF(pPool)->cDirtyPages != 0;
2345}
2346
2347
2348/**
2349 * Check if this VCPU currently owns the PGM lock.
2350 *
2351 * @returns bool owner/not owner
2352 * @param pVM Pointer to the VM.
2353 */
2354VMMDECL(bool) PGMIsLockOwner(PVM pVM)
2355{
2356 return PDMCritSectIsOwner(&pVM->pgm.s.CritSectX);
2357}
2358
2359
2360/**
2361 * Enable or disable large page usage
2362 *
2363 * @returns VBox status code.
2364 * @param pVM Pointer to the VM.
2365 * @param fUseLargePages Use/not use large pages
2366 */
2367VMMDECL(int) PGMSetLargePageUsage(PVM pVM, bool fUseLargePages)
2368{
2369 VM_ASSERT_VALID_EXT_RETURN(pVM, VERR_INVALID_VM_HANDLE);
2370
2371 pVM->fUseLargePages = fUseLargePages;
2372 return VINF_SUCCESS;
2373}
2374
2375
2376/**
2377 * Acquire the PGM lock.
2378 *
2379 * @returns VBox status code
2380 * @param pVM Pointer to the VM.
2381 */
2382int pgmLock(PVM pVM)
2383{
2384 int rc = PDMCritSectEnter(&pVM->pgm.s.CritSectX, VERR_SEM_BUSY);
2385#if defined(IN_RC) || defined(IN_RING0)
2386 if (rc == VERR_SEM_BUSY)
2387 rc = VMMRZCallRing3NoCpu(pVM, VMMCALLRING3_PGM_LOCK, 0);
2388#endif
2389 AssertMsg(rc == VINF_SUCCESS, ("%Rrc\n", rc));
2390 return rc;
2391}
2392
2393
2394/**
2395 * Release the PGM lock.
2396 *
2397 * @returns VBox status code
2398 * @param pVM Pointer to the VM.
2399 */
2400void pgmUnlock(PVM pVM)
2401{
2402 uint32_t cDeprecatedPageLocks = pVM->pgm.s.cDeprecatedPageLocks;
2403 pVM->pgm.s.cDeprecatedPageLocks = 0;
2404 int rc = PDMCritSectLeave(&pVM->pgm.s.CritSectX);
2405 if (rc == VINF_SEM_NESTED)
2406 pVM->pgm.s.cDeprecatedPageLocks = cDeprecatedPageLocks;
2407}
2408
2409#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2410
2411/**
2412 * Common worker for pgmRZDynMapGCPageOffInlined and pgmRZDynMapGCPageV2Inlined.
2413 *
2414 * @returns VBox status code.
2415 * @param pVM Pointer to the VM.
2416 * @param pVCpu The current CPU.
2417 * @param GCPhys The guest physical address of the page to map. The
2418 * offset bits are not ignored.
2419 * @param ppv Where to return the address corresponding to @a GCPhys.
2420 */
2421int pgmRZDynMapGCPageCommon(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void **ppv RTLOG_COMMA_SRC_POS_DECL)
2422{
2423 pgmLock(pVM);
2424
2425 /*
2426 * Convert it to a writable page and it on to the dynamic mapper.
2427 */
2428 int rc;
2429 PPGMPAGE pPage = pgmPhysGetPage(pVM, GCPhys);
2430 if (RT_LIKELY(pPage))
2431 {
2432 rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
2433 if (RT_SUCCESS(rc))
2434 {
2435 void *pv;
2436 rc = pgmRZDynMapHCPageInlined(pVCpu, PGM_PAGE_GET_HCPHYS(pPage), &pv RTLOG_COMMA_SRC_POS_ARGS);
2437 if (RT_SUCCESS(rc))
2438 *ppv = (void *)((uintptr_t)pv | ((uintptr_t)GCPhys & PAGE_OFFSET_MASK));
2439 }
2440 else
2441 AssertRC(rc);
2442 }
2443 else
2444 {
2445 AssertMsgFailed(("Invalid physical address %RGp!\n", GCPhys));
2446 rc = VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2447 }
2448
2449 pgmUnlock(pVM);
2450 return rc;
2451}
2452
2453#endif /* IN_RC || VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
2454#if !defined(IN_R0) || defined(LOG_ENABLED)
2455
2456/** Format handler for PGMPAGE.
2457 * @copydoc FNRTSTRFORMATTYPE */
2458static DECLCALLBACK(size_t) pgmFormatTypeHandlerPage(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
2459 const char *pszType, void const *pvValue,
2460 int cchWidth, int cchPrecision, unsigned fFlags,
2461 void *pvUser)
2462{
2463 size_t cch;
2464 PCPGMPAGE pPage = (PCPGMPAGE)pvValue;
2465 if (RT_VALID_PTR(pPage))
2466 {
2467 char szTmp[64+80];
2468
2469 cch = 0;
2470
2471 /* The single char state stuff. */
2472 static const char s_achPageStates[4] = { 'Z', 'A', 'W', 'S' };
2473 szTmp[cch++] = s_achPageStates[PGM_PAGE_GET_STATE_NA(pPage)];
2474
2475#define IS_PART_INCLUDED(lvl) ( !(fFlags & RTSTR_F_PRECISION) || cchPrecision == (lvl) || cchPrecision >= (lvl)+10 )
2476 if (IS_PART_INCLUDED(5))
2477 {
2478 static const char s_achHandlerStates[4] = { '-', 't', 'w', 'a' };
2479 szTmp[cch++] = s_achHandlerStates[PGM_PAGE_GET_HNDL_PHYS_STATE(pPage)];
2480 szTmp[cch++] = s_achHandlerStates[PGM_PAGE_GET_HNDL_VIRT_STATE(pPage)];
2481 }
2482
2483 /* The type. */
2484 if (IS_PART_INCLUDED(4))
2485 {
2486 szTmp[cch++] = ':';
2487 static const char s_achPageTypes[8][4] = { "INV", "RAM", "MI2", "M2A", "SHA", "ROM", "MIO", "BAD" };
2488 szTmp[cch++] = s_achPageTypes[PGM_PAGE_GET_TYPE_NA(pPage)][0];
2489 szTmp[cch++] = s_achPageTypes[PGM_PAGE_GET_TYPE_NA(pPage)][1];
2490 szTmp[cch++] = s_achPageTypes[PGM_PAGE_GET_TYPE_NA(pPage)][2];
2491 }
2492
2493 /* The numbers. */
2494 if (IS_PART_INCLUDED(3))
2495 {
2496 szTmp[cch++] = ':';
2497 cch += RTStrFormatNumber(&szTmp[cch], PGM_PAGE_GET_HCPHYS_NA(pPage), 16, 12, 0, RTSTR_F_ZEROPAD | RTSTR_F_64BIT);
2498 }
2499
2500 if (IS_PART_INCLUDED(2))
2501 {
2502 szTmp[cch++] = ':';
2503 cch += RTStrFormatNumber(&szTmp[cch], PGM_PAGE_GET_PAGEID(pPage), 16, 7, 0, RTSTR_F_ZEROPAD | RTSTR_F_32BIT);
2504 }
2505
2506 if (IS_PART_INCLUDED(6))
2507 {
2508 szTmp[cch++] = ':';
2509 static const char s_achRefs[4] = { '-', 'U', '!', 'L' };
2510 szTmp[cch++] = s_achRefs[PGM_PAGE_GET_TD_CREFS_NA(pPage)];
2511 cch += RTStrFormatNumber(&szTmp[cch], PGM_PAGE_GET_TD_IDX_NA(pPage), 16, 4, 0, RTSTR_F_ZEROPAD | RTSTR_F_16BIT);
2512 }
2513#undef IS_PART_INCLUDED
2514
2515 cch = pfnOutput(pvArgOutput, szTmp, cch);
2516 }
2517 else
2518 cch = pfnOutput(pvArgOutput, "<bad-pgmpage-ptr>", sizeof("<bad-pgmpage-ptr>") - 1);
2519 NOREF(pszType); NOREF(cchWidth); NOREF(pvUser);
2520 return cch;
2521}
2522
2523
2524/** Format handler for PGMRAMRANGE.
2525 * @copydoc FNRTSTRFORMATTYPE */
2526static DECLCALLBACK(size_t) pgmFormatTypeHandlerRamRange(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
2527 const char *pszType, void const *pvValue,
2528 int cchWidth, int cchPrecision, unsigned fFlags,
2529 void *pvUser)
2530{
2531 size_t cch;
2532 PGMRAMRANGE const *pRam = (PGMRAMRANGE const *)pvValue;
2533 if (VALID_PTR(pRam))
2534 {
2535 char szTmp[80];
2536 cch = RTStrPrintf(szTmp, sizeof(szTmp), "%RGp-%RGp", pRam->GCPhys, pRam->GCPhysLast);
2537 cch = pfnOutput(pvArgOutput, szTmp, cch);
2538 }
2539 else
2540 cch = pfnOutput(pvArgOutput, "<bad-pgmramrange-ptr>", sizeof("<bad-pgmramrange-ptr>") - 1);
2541 NOREF(pszType); NOREF(cchWidth); NOREF(cchPrecision); NOREF(pvUser); NOREF(fFlags);
2542 return cch;
2543}
2544
2545/** Format type andlers to be registered/deregistered. */
2546static const struct
2547{
2548 char szType[24];
2549 PFNRTSTRFORMATTYPE pfnHandler;
2550} g_aPgmFormatTypes[] =
2551{
2552 { "pgmpage", pgmFormatTypeHandlerPage },
2553 { "pgmramrange", pgmFormatTypeHandlerRamRange }
2554};
2555
2556#endif /* !IN_R0 || LOG_ENABLED */
2557
2558/**
2559 * Registers the global string format types.
2560 *
2561 * This should be called at module load time or in some other manner that ensure
2562 * that it's called exactly one time.
2563 *
2564 * @returns IPRT status code on RTStrFormatTypeRegister failure.
2565 */
2566VMMDECL(int) PGMRegisterStringFormatTypes(void)
2567{
2568#if !defined(IN_R0) || defined(LOG_ENABLED)
2569 int rc = VINF_SUCCESS;
2570 unsigned i;
2571 for (i = 0; RT_SUCCESS(rc) && i < RT_ELEMENTS(g_aPgmFormatTypes); i++)
2572 {
2573 rc = RTStrFormatTypeRegister(g_aPgmFormatTypes[i].szType, g_aPgmFormatTypes[i].pfnHandler, NULL);
2574# ifdef IN_RING0
2575 if (rc == VERR_ALREADY_EXISTS)
2576 {
2577 /* in case of cleanup failure in ring-0 */
2578 RTStrFormatTypeDeregister(g_aPgmFormatTypes[i].szType);
2579 rc = RTStrFormatTypeRegister(g_aPgmFormatTypes[i].szType, g_aPgmFormatTypes[i].pfnHandler, NULL);
2580 }
2581# endif
2582 }
2583 if (RT_FAILURE(rc))
2584 while (i-- > 0)
2585 RTStrFormatTypeDeregister(g_aPgmFormatTypes[i].szType);
2586
2587 return rc;
2588#else
2589 return VINF_SUCCESS;
2590#endif
2591}
2592
2593
2594/**
2595 * Deregisters the global string format types.
2596 *
2597 * This should be called at module unload time or in some other manner that
2598 * ensure that it's called exactly one time.
2599 */
2600VMMDECL(void) PGMDeregisterStringFormatTypes(void)
2601{
2602#if !defined(IN_R0) || defined(LOG_ENABLED)
2603 for (unsigned i = 0; i < RT_ELEMENTS(g_aPgmFormatTypes); i++)
2604 RTStrFormatTypeDeregister(g_aPgmFormatTypes[i].szType);
2605#endif
2606}
2607
2608#ifdef VBOX_STRICT
2609
2610/**
2611 * Asserts that there are no mapping conflicts.
2612 *
2613 * @returns Number of conflicts.
2614 * @param pVM Pointer to the VM.
2615 */
2616VMMDECL(unsigned) PGMAssertNoMappingConflicts(PVM pVM)
2617{
2618 unsigned cErrors = 0;
2619
2620 /* Only applies to raw mode -> 1 VPCU */
2621 Assert(pVM->cCpus == 1);
2622 PVMCPU pVCpu = &pVM->aCpus[0];
2623
2624 /*
2625 * Check for mapping conflicts.
2626 */
2627 for (PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
2628 pMapping;
2629 pMapping = pMapping->CTX_SUFF(pNext))
2630 {
2631 /** @todo This is slow and should be optimized, but since it's just assertions I don't care now. */
2632 for (RTGCPTR GCPtr = pMapping->GCPtr;
2633 GCPtr <= pMapping->GCPtrLast;
2634 GCPtr += PAGE_SIZE)
2635 {
2636 int rc = PGMGstGetPage(pVCpu, (RTGCPTR)GCPtr, NULL, NULL);
2637 if (rc != VERR_PAGE_TABLE_NOT_PRESENT)
2638 {
2639 AssertMsgFailed(("Conflict at %RGv with %s\n", GCPtr, R3STRING(pMapping->pszDesc)));
2640 cErrors++;
2641 break;
2642 }
2643 }
2644 }
2645
2646 return cErrors;
2647}
2648
2649
2650/**
2651 * Asserts that everything related to the guest CR3 is correctly shadowed.
2652 *
2653 * This will call PGMAssertNoMappingConflicts() and PGMAssertHandlerAndFlagsInSync(),
2654 * and assert the correctness of the guest CR3 mapping before asserting that the
2655 * shadow page tables is in sync with the guest page tables.
2656 *
2657 * @returns Number of conflicts.
2658 * @param pVM Pointer to the VM.
2659 * @param pVCpu Pointer to the VMCPU.
2660 * @param cr3 The current guest CR3 register value.
2661 * @param cr4 The current guest CR4 register value.
2662 */
2663VMMDECL(unsigned) PGMAssertCR3(PVM pVM, PVMCPU pVCpu, uint64_t cr3, uint64_t cr4)
2664{
2665 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3), a);
2666 pgmLock(pVM);
2667 unsigned cErrors = PGM_BTH_PFN(AssertCR3, pVCpu)(pVCpu, cr3, cr4, 0, ~(RTGCPTR)0);
2668 pgmUnlock(pVM);
2669 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3), a);
2670 return cErrors;
2671}
2672
2673#endif /* VBOX_STRICT */
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