VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAll.cpp@ 45799

Last change on this file since 45799 was 45799, checked in by vboxsync, 12 years ago

Make the recompiler call PGMCr0WpEnabled.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id Revision
File size: 89.2 KB
Line 
1/* $Id: PGMAll.cpp 45799 2013-04-29 03:46:29Z vboxsync $ */
2/** @file
3 * PGM - Page Manager and Monitor - All context code.
4 */
5
6/*
7 * Copyright (C) 2006-2012 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/*******************************************************************************
19* Header Files *
20*******************************************************************************/
21#define LOG_GROUP LOG_GROUP_PGM
22#include <VBox/vmm/pgm.h>
23#include <VBox/vmm/cpum.h>
24#include <VBox/vmm/selm.h>
25#include <VBox/vmm/iom.h>
26#include <VBox/sup.h>
27#include <VBox/vmm/mm.h>
28#include <VBox/vmm/stam.h>
29#include <VBox/vmm/csam.h>
30#include <VBox/vmm/patm.h>
31#include <VBox/vmm/trpm.h>
32#ifdef VBOX_WITH_REM
33# include <VBox/vmm/rem.h>
34#endif
35#include <VBox/vmm/em.h>
36#include <VBox/vmm/hm.h>
37#include <VBox/vmm/hm_vmx.h>
38#include "PGMInternal.h"
39#include <VBox/vmm/vm.h>
40#include "PGMInline.h"
41#include <iprt/assert.h>
42#include <iprt/asm-amd64-x86.h>
43#include <iprt/string.h>
44#include <VBox/log.h>
45#include <VBox/param.h>
46#include <VBox/err.h>
47
48
49/*******************************************************************************
50* Structures and Typedefs *
51*******************************************************************************/
52/**
53 * Stated structure for PGM_GST_NAME(HandlerVirtualUpdate) that's
54 * passed to PGM_GST_NAME(VirtHandlerUpdateOne) during enumeration.
55 */
56typedef struct PGMHVUSTATE
57{
58 /** Pointer to the VM. */
59 PVM pVM;
60 /** Pointer to the VMCPU. */
61 PVMCPU pVCpu;
62 /** The todo flags. */
63 RTUINT fTodo;
64 /** The CR4 register value. */
65 uint32_t cr4;
66} PGMHVUSTATE, *PPGMHVUSTATE;
67
68
69/*******************************************************************************
70* Internal Functions *
71*******************************************************************************/
72DECLINLINE(int) pgmShwGetLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPT *ppPdpt, PX86PDPAE *ppPD);
73DECLINLINE(int) pgmShwGetPaePoolPagePD(PVMCPU pVCpu, RTGCPTR GCPtr, PPGMPOOLPAGE *ppShwPde);
74#ifndef IN_RC
75static int pgmShwSyncLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, X86PGPAEUINT uGstPml4e, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD);
76static int pgmShwGetEPTPDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PEPTPDPT *ppPdpt, PEPTPD *ppPD);
77#endif
78
79
80/*
81 * Shadow - 32-bit mode
82 */
83#define PGM_SHW_TYPE PGM_TYPE_32BIT
84#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
85#include "PGMAllShw.h"
86
87/* Guest - real mode */
88#define PGM_GST_TYPE PGM_TYPE_REAL
89#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
90#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
91#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
92#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
93#include "PGMGstDefs.h"
94#include "PGMAllGst.h"
95#include "PGMAllBth.h"
96#undef BTH_PGMPOOLKIND_PT_FOR_PT
97#undef BTH_PGMPOOLKIND_ROOT
98#undef PGM_BTH_NAME
99#undef PGM_GST_TYPE
100#undef PGM_GST_NAME
101
102/* Guest - protected mode */
103#define PGM_GST_TYPE PGM_TYPE_PROT
104#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
105#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
106#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
107#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
108#include "PGMGstDefs.h"
109#include "PGMAllGst.h"
110#include "PGMAllBth.h"
111#undef BTH_PGMPOOLKIND_PT_FOR_PT
112#undef BTH_PGMPOOLKIND_ROOT
113#undef PGM_BTH_NAME
114#undef PGM_GST_TYPE
115#undef PGM_GST_NAME
116
117/* Guest - 32-bit mode */
118#define PGM_GST_TYPE PGM_TYPE_32BIT
119#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
120#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
121#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
122#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
123#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD
124#include "PGMGstDefs.h"
125#include "PGMAllGst.h"
126#include "PGMAllBth.h"
127#undef BTH_PGMPOOLKIND_PT_FOR_BIG
128#undef BTH_PGMPOOLKIND_PT_FOR_PT
129#undef BTH_PGMPOOLKIND_ROOT
130#undef PGM_BTH_NAME
131#undef PGM_GST_TYPE
132#undef PGM_GST_NAME
133
134#undef PGM_SHW_TYPE
135#undef PGM_SHW_NAME
136
137
138/*
139 * Shadow - PAE mode
140 */
141#define PGM_SHW_TYPE PGM_TYPE_PAE
142#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
143#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
144#include "PGMAllShw.h"
145
146/* Guest - real mode */
147#define PGM_GST_TYPE PGM_TYPE_REAL
148#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
149#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
150#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
151#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
152#include "PGMGstDefs.h"
153#include "PGMAllBth.h"
154#undef BTH_PGMPOOLKIND_PT_FOR_PT
155#undef BTH_PGMPOOLKIND_ROOT
156#undef PGM_BTH_NAME
157#undef PGM_GST_TYPE
158#undef PGM_GST_NAME
159
160/* Guest - protected mode */
161#define PGM_GST_TYPE PGM_TYPE_PROT
162#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
163#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
164#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
165#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
166#include "PGMGstDefs.h"
167#include "PGMAllBth.h"
168#undef BTH_PGMPOOLKIND_PT_FOR_PT
169#undef BTH_PGMPOOLKIND_ROOT
170#undef PGM_BTH_NAME
171#undef PGM_GST_TYPE
172#undef PGM_GST_NAME
173
174/* Guest - 32-bit mode */
175#define PGM_GST_TYPE PGM_TYPE_32BIT
176#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
177#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
178#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
179#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
180#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_FOR_32BIT
181#include "PGMGstDefs.h"
182#include "PGMAllBth.h"
183#undef BTH_PGMPOOLKIND_PT_FOR_BIG
184#undef BTH_PGMPOOLKIND_PT_FOR_PT
185#undef BTH_PGMPOOLKIND_ROOT
186#undef PGM_BTH_NAME
187#undef PGM_GST_TYPE
188#undef PGM_GST_NAME
189
190
191/* Guest - PAE mode */
192#define PGM_GST_TYPE PGM_TYPE_PAE
193#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
194#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
195#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
196#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
197#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT
198#include "PGMGstDefs.h"
199#include "PGMAllGst.h"
200#include "PGMAllBth.h"
201#undef BTH_PGMPOOLKIND_PT_FOR_BIG
202#undef BTH_PGMPOOLKIND_PT_FOR_PT
203#undef BTH_PGMPOOLKIND_ROOT
204#undef PGM_BTH_NAME
205#undef PGM_GST_TYPE
206#undef PGM_GST_NAME
207
208#undef PGM_SHW_TYPE
209#undef PGM_SHW_NAME
210
211
212#ifndef IN_RC /* AMD64 implies VT-x/AMD-V */
213/*
214 * Shadow - AMD64 mode
215 */
216# define PGM_SHW_TYPE PGM_TYPE_AMD64
217# define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
218# include "PGMAllShw.h"
219
220/* Guest - protected mode (only used for AMD-V nested paging in 64 bits mode) */
221# define PGM_GST_TYPE PGM_TYPE_PROT
222# define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
223# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_PROT(name)
224# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
225# define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PD_PHYS
226# include "PGMGstDefs.h"
227# include "PGMAllBth.h"
228# undef BTH_PGMPOOLKIND_PT_FOR_PT
229# undef BTH_PGMPOOLKIND_ROOT
230# undef PGM_BTH_NAME
231# undef PGM_GST_TYPE
232# undef PGM_GST_NAME
233
234# ifdef VBOX_WITH_64_BITS_GUESTS
235/* Guest - AMD64 mode */
236# define PGM_GST_TYPE PGM_TYPE_AMD64
237# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
238# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
239# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
240# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
241# define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_64BIT_PML4
242# include "PGMGstDefs.h"
243# include "PGMAllGst.h"
244# include "PGMAllBth.h"
245# undef BTH_PGMPOOLKIND_PT_FOR_BIG
246# undef BTH_PGMPOOLKIND_PT_FOR_PT
247# undef BTH_PGMPOOLKIND_ROOT
248# undef PGM_BTH_NAME
249# undef PGM_GST_TYPE
250# undef PGM_GST_NAME
251# endif /* VBOX_WITH_64_BITS_GUESTS */
252
253# undef PGM_SHW_TYPE
254# undef PGM_SHW_NAME
255
256
257/*
258 * Shadow - Nested paging mode
259 */
260# define PGM_SHW_TYPE PGM_TYPE_NESTED
261# define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED(name)
262# include "PGMAllShw.h"
263
264/* Guest - real mode */
265# define PGM_GST_TYPE PGM_TYPE_REAL
266# define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
267# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_REAL(name)
268# include "PGMGstDefs.h"
269# include "PGMAllBth.h"
270# undef PGM_BTH_NAME
271# undef PGM_GST_TYPE
272# undef PGM_GST_NAME
273
274/* Guest - protected mode */
275# define PGM_GST_TYPE PGM_TYPE_PROT
276# define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
277# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PROT(name)
278# include "PGMGstDefs.h"
279# include "PGMAllBth.h"
280# undef PGM_BTH_NAME
281# undef PGM_GST_TYPE
282# undef PGM_GST_NAME
283
284/* Guest - 32-bit mode */
285# define PGM_GST_TYPE PGM_TYPE_32BIT
286# define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
287# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT(name)
288# include "PGMGstDefs.h"
289# include "PGMAllBth.h"
290# undef PGM_BTH_NAME
291# undef PGM_GST_TYPE
292# undef PGM_GST_NAME
293
294/* Guest - PAE mode */
295# define PGM_GST_TYPE PGM_TYPE_PAE
296# define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
297# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE(name)
298# include "PGMGstDefs.h"
299# include "PGMAllBth.h"
300# undef PGM_BTH_NAME
301# undef PGM_GST_TYPE
302# undef PGM_GST_NAME
303
304# ifdef VBOX_WITH_64_BITS_GUESTS
305/* Guest - AMD64 mode */
306# define PGM_GST_TYPE PGM_TYPE_AMD64
307# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
308# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64(name)
309# include "PGMGstDefs.h"
310# include "PGMAllBth.h"
311# undef PGM_BTH_NAME
312# undef PGM_GST_TYPE
313# undef PGM_GST_NAME
314# endif /* VBOX_WITH_64_BITS_GUESTS */
315
316# undef PGM_SHW_TYPE
317# undef PGM_SHW_NAME
318
319
320/*
321 * Shadow - EPT
322 */
323# define PGM_SHW_TYPE PGM_TYPE_EPT
324# define PGM_SHW_NAME(name) PGM_SHW_NAME_EPT(name)
325# include "PGMAllShw.h"
326
327/* Guest - real mode */
328# define PGM_GST_TYPE PGM_TYPE_REAL
329# define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
330# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_REAL(name)
331# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
332# include "PGMGstDefs.h"
333# include "PGMAllBth.h"
334# undef BTH_PGMPOOLKIND_PT_FOR_PT
335# undef PGM_BTH_NAME
336# undef PGM_GST_TYPE
337# undef PGM_GST_NAME
338
339/* Guest - protected mode */
340# define PGM_GST_TYPE PGM_TYPE_PROT
341# define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
342# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PROT(name)
343# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
344# include "PGMGstDefs.h"
345# include "PGMAllBth.h"
346# undef BTH_PGMPOOLKIND_PT_FOR_PT
347# undef PGM_BTH_NAME
348# undef PGM_GST_TYPE
349# undef PGM_GST_NAME
350
351/* Guest - 32-bit mode */
352# define PGM_GST_TYPE PGM_TYPE_32BIT
353# define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
354# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_32BIT(name)
355# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
356# include "PGMGstDefs.h"
357# include "PGMAllBth.h"
358# undef BTH_PGMPOOLKIND_PT_FOR_PT
359# undef PGM_BTH_NAME
360# undef PGM_GST_TYPE
361# undef PGM_GST_NAME
362
363/* Guest - PAE mode */
364# define PGM_GST_TYPE PGM_TYPE_PAE
365# define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
366# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PAE(name)
367# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
368# include "PGMGstDefs.h"
369# include "PGMAllBth.h"
370# undef BTH_PGMPOOLKIND_PT_FOR_PT
371# undef PGM_BTH_NAME
372# undef PGM_GST_TYPE
373# undef PGM_GST_NAME
374
375# ifdef VBOX_WITH_64_BITS_GUESTS
376/* Guest - AMD64 mode */
377# define PGM_GST_TYPE PGM_TYPE_AMD64
378# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
379# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_AMD64(name)
380# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
381# include "PGMGstDefs.h"
382# include "PGMAllBth.h"
383# undef BTH_PGMPOOLKIND_PT_FOR_PT
384# undef PGM_BTH_NAME
385# undef PGM_GST_TYPE
386# undef PGM_GST_NAME
387# endif /* VBOX_WITH_64_BITS_GUESTS */
388
389# undef PGM_SHW_TYPE
390# undef PGM_SHW_NAME
391
392#endif /* !IN_RC */
393
394
395#ifndef IN_RING3
396/**
397 * #PF Handler.
398 *
399 * @returns VBox status code (appropriate for trap handling and GC return).
400 * @param pVCpu Pointer to the VMCPU.
401 * @param uErr The trap error code.
402 * @param pRegFrame Trap register frame.
403 * @param pvFault The fault address.
404 */
405VMMDECL(int) PGMTrap0eHandler(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
406{
407 PVM pVM = pVCpu->CTX_SUFF(pVM);
408
409 Log(("PGMTrap0eHandler: uErr=%RGx pvFault=%RGv eip=%04x:%RGv cr3=%RGp\n", uErr, pvFault, pRegFrame->cs.Sel, (RTGCPTR)pRegFrame->rip, (RTGCPHYS)CPUMGetGuestCR3(pVCpu)));
410 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0e, a);
411 STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = NULL; } );
412
413
414#ifdef VBOX_WITH_STATISTICS
415 /*
416 * Error code stats.
417 */
418 if (uErr & X86_TRAP_PF_US)
419 {
420 if (!(uErr & X86_TRAP_PF_P))
421 {
422 if (uErr & X86_TRAP_PF_RW)
423 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eUSNotPresentWrite);
424 else
425 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eUSNotPresentRead);
426 }
427 else if (uErr & X86_TRAP_PF_RW)
428 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eUSWrite);
429 else if (uErr & X86_TRAP_PF_RSVD)
430 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eUSReserved);
431 else if (uErr & X86_TRAP_PF_ID)
432 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eUSNXE);
433 else
434 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eUSRead);
435 }
436 else
437 { /* Supervisor */
438 if (!(uErr & X86_TRAP_PF_P))
439 {
440 if (uErr & X86_TRAP_PF_RW)
441 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eSVNotPresentWrite);
442 else
443 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eSVNotPresentRead);
444 }
445 else if (uErr & X86_TRAP_PF_RW)
446 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eSVWrite);
447 else if (uErr & X86_TRAP_PF_ID)
448 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eSNXE);
449 else if (uErr & X86_TRAP_PF_RSVD)
450 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eSVReserved);
451 }
452#endif /* VBOX_WITH_STATISTICS */
453
454 /*
455 * Call the worker.
456 */
457 bool fLockTaken = false;
458 int rc = PGM_BTH_PFN(Trap0eHandler, pVCpu)(pVCpu, uErr, pRegFrame, pvFault, &fLockTaken);
459 if (fLockTaken)
460 {
461 PGM_LOCK_ASSERT_OWNER(pVM);
462 pgmUnlock(pVM);
463 }
464 LogFlow(("PGMTrap0eHandler: uErr=%RGx pvFault=%RGv rc=%Rrc\n", uErr, pvFault, rc));
465
466 /*
467 * Return code tweaks.
468 */
469 if (rc != VINF_SUCCESS)
470 {
471 if (rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
472 rc = VINF_SUCCESS;
473
474# ifdef IN_RING0
475 /* Note: hack alert for difficult to reproduce problem. */
476 if ( rc == VERR_PAGE_NOT_PRESENT /* SMP only ; disassembly might fail. */
477 || rc == VERR_PAGE_TABLE_NOT_PRESENT /* seen with UNI & SMP */
478 || rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT /* seen with SMP */
479 || rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT) /* precaution */
480 {
481 Log(("WARNING: Unexpected VERR_PAGE_TABLE_NOT_PRESENT (%d) for page fault at %RGv error code %x (rip=%RGv)\n", rc, pvFault, uErr, pRegFrame->rip));
482 /* Some kind of inconsistency in the SMP case; it's safe to just execute the instruction again; not sure about single VCPU VMs though. */
483 rc = VINF_SUCCESS;
484 }
485# endif
486 }
487
488 STAM_STATS({ if (rc == VINF_EM_RAW_GUEST_TRAP) STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eGuestPF); });
489 STAM_STATS({ if (!pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution))
490 pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Misc; });
491 STAM_PROFILE_STOP_EX(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0e, pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution), a);
492 return rc;
493}
494#endif /* !IN_RING3 */
495
496
497/**
498 * Prefetch a page
499 *
500 * Typically used to sync commonly used pages before entering raw mode
501 * after a CR3 reload.
502 *
503 * @returns VBox status code suitable for scheduling.
504 * @retval VINF_SUCCESS on success.
505 * @retval VINF_PGM_SYNC_CR3 if we're out of shadow pages or something like that.
506 * @param pVCpu Pointer to the VMCPU.
507 * @param GCPtrPage Page to invalidate.
508 */
509VMMDECL(int) PGMPrefetchPage(PVMCPU pVCpu, RTGCPTR GCPtrPage)
510{
511 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Prefetch), a);
512 int rc = PGM_BTH_PFN(PrefetchPage, pVCpu)(pVCpu, GCPtrPage);
513 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Prefetch), a);
514 AssertMsg(rc == VINF_SUCCESS || rc == VINF_PGM_SYNC_CR3 || RT_FAILURE(rc), ("rc=%Rrc\n", rc));
515 return rc;
516}
517
518
519/**
520 * Gets the mapping corresponding to the specified address (if any).
521 *
522 * @returns Pointer to the mapping.
523 * @returns NULL if not
524 *
525 * @param pVM Pointer to the VM.
526 * @param GCPtr The guest context pointer.
527 */
528PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr)
529{
530 PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
531 while (pMapping)
532 {
533 if ((uintptr_t)GCPtr < (uintptr_t)pMapping->GCPtr)
534 break;
535 if ((uintptr_t)GCPtr - (uintptr_t)pMapping->GCPtr < pMapping->cb)
536 return pMapping;
537 pMapping = pMapping->CTX_SUFF(pNext);
538 }
539 return NULL;
540}
541
542
543/**
544 * Verifies a range of pages for read or write access
545 *
546 * Only checks the guest's page tables
547 *
548 * @returns VBox status code.
549 * @param pVCpu Pointer to the VMCPU.
550 * @param Addr Guest virtual address to check
551 * @param cbSize Access size
552 * @param fAccess Access type (r/w, user/supervisor (X86_PTE_*))
553 * @remarks Current not in use.
554 */
555VMMDECL(int) PGMIsValidAccess(PVMCPU pVCpu, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess)
556{
557 /*
558 * Validate input.
559 */
560 if (fAccess & ~(X86_PTE_US | X86_PTE_RW))
561 {
562 AssertMsgFailed(("PGMIsValidAccess: invalid access type %08x\n", fAccess));
563 return VERR_INVALID_PARAMETER;
564 }
565
566 uint64_t fPage;
567 int rc = PGMGstGetPage(pVCpu, (RTGCPTR)Addr, &fPage, NULL);
568 if (RT_FAILURE(rc))
569 {
570 Log(("PGMIsValidAccess: access violation for %RGv rc=%d\n", Addr, rc));
571 return VINF_EM_RAW_GUEST_TRAP;
572 }
573
574 /*
575 * Check if the access would cause a page fault
576 *
577 * Note that hypervisor page directories are not present in the guest's tables, so this check
578 * is sufficient.
579 */
580 bool fWrite = !!(fAccess & X86_PTE_RW);
581 bool fUser = !!(fAccess & X86_PTE_US);
582 if ( !(fPage & X86_PTE_P)
583 || (fWrite && !(fPage & X86_PTE_RW))
584 || (fUser && !(fPage & X86_PTE_US)) )
585 {
586 Log(("PGMIsValidAccess: access violation for %RGv attr %#llx vs %d:%d\n", Addr, fPage, fWrite, fUser));
587 return VINF_EM_RAW_GUEST_TRAP;
588 }
589 if ( RT_SUCCESS(rc)
590 && PAGE_ADDRESS(Addr) != PAGE_ADDRESS(Addr + cbSize))
591 return PGMIsValidAccess(pVCpu, Addr + PAGE_SIZE, (cbSize > PAGE_SIZE) ? cbSize - PAGE_SIZE : 1, fAccess);
592 return rc;
593}
594
595
596/**
597 * Verifies a range of pages for read or write access
598 *
599 * Supports handling of pages marked for dirty bit tracking and CSAM
600 *
601 * @returns VBox status code.
602 * @param pVCpu Pointer to the VMCPU.
603 * @param Addr Guest virtual address to check
604 * @param cbSize Access size
605 * @param fAccess Access type (r/w, user/supervisor (X86_PTE_*))
606 */
607VMMDECL(int) PGMVerifyAccess(PVMCPU pVCpu, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess)
608{
609 PVM pVM = pVCpu->CTX_SUFF(pVM);
610
611 AssertMsg(!(fAccess & ~(X86_PTE_US | X86_PTE_RW)), ("PGMVerifyAccess: invalid access type %08x\n", fAccess));
612
613 /*
614 * Get going.
615 */
616 uint64_t fPageGst;
617 int rc = PGMGstGetPage(pVCpu, (RTGCPTR)Addr, &fPageGst, NULL);
618 if (RT_FAILURE(rc))
619 {
620 Log(("PGMVerifyAccess: access violation for %RGv rc=%d\n", Addr, rc));
621 return VINF_EM_RAW_GUEST_TRAP;
622 }
623
624 /*
625 * Check if the access would cause a page fault
626 *
627 * Note that hypervisor page directories are not present in the guest's tables, so this check
628 * is sufficient.
629 */
630 const bool fWrite = !!(fAccess & X86_PTE_RW);
631 const bool fUser = !!(fAccess & X86_PTE_US);
632 if ( !(fPageGst & X86_PTE_P)
633 || (fWrite && !(fPageGst & X86_PTE_RW))
634 || (fUser && !(fPageGst & X86_PTE_US)) )
635 {
636 Log(("PGMVerifyAccess: access violation for %RGv attr %#llx vs %d:%d\n", Addr, fPageGst, fWrite, fUser));
637 return VINF_EM_RAW_GUEST_TRAP;
638 }
639
640 if (!pVM->pgm.s.fNestedPaging)
641 {
642 /*
643 * Next step is to verify if we protected this page for dirty bit tracking or for CSAM scanning
644 */
645 rc = PGMShwGetPage(pVCpu, (RTGCPTR)Addr, NULL, NULL);
646 if ( rc == VERR_PAGE_NOT_PRESENT
647 || rc == VERR_PAGE_TABLE_NOT_PRESENT)
648 {
649 /*
650 * Page is not present in our page tables.
651 * Try to sync it!
652 */
653 Assert(X86_TRAP_PF_RW == X86_PTE_RW && X86_TRAP_PF_US == X86_PTE_US);
654 uint32_t uErr = fAccess & (X86_TRAP_PF_RW | X86_TRAP_PF_US);
655 rc = PGM_BTH_PFN(VerifyAccessSyncPage, pVCpu)(pVCpu, Addr, fPageGst, uErr);
656 if (rc != VINF_SUCCESS)
657 return rc;
658 }
659 else
660 AssertMsg(rc == VINF_SUCCESS, ("PGMShwGetPage %RGv failed with %Rrc\n", Addr, rc));
661 }
662
663#if 0 /* def VBOX_STRICT; triggers too often now */
664 /*
665 * This check is a bit paranoid, but useful.
666 */
667 /* Note! This will assert when writing to monitored pages (a bit annoying actually). */
668 uint64_t fPageShw;
669 rc = PGMShwGetPage(pVCpu, (RTGCPTR)Addr, &fPageShw, NULL);
670 if ( (rc == VERR_PAGE_NOT_PRESENT || RT_FAILURE(rc))
671 || (fWrite && !(fPageShw & X86_PTE_RW))
672 || (fUser && !(fPageShw & X86_PTE_US)) )
673 {
674 AssertMsgFailed(("Unexpected access violation for %RGv! rc=%Rrc write=%d user=%d\n",
675 Addr, rc, fWrite && !(fPageShw & X86_PTE_RW), fUser && !(fPageShw & X86_PTE_US)));
676 return VINF_EM_RAW_GUEST_TRAP;
677 }
678#endif
679
680 if ( RT_SUCCESS(rc)
681 && ( PAGE_ADDRESS(Addr) != PAGE_ADDRESS(Addr + cbSize - 1)
682 || Addr + cbSize < Addr))
683 {
684 /* Don't recursively call PGMVerifyAccess as we might run out of stack. */
685 for (;;)
686 {
687 Addr += PAGE_SIZE;
688 if (cbSize > PAGE_SIZE)
689 cbSize -= PAGE_SIZE;
690 else
691 cbSize = 1;
692 rc = PGMVerifyAccess(pVCpu, Addr, 1, fAccess);
693 if (rc != VINF_SUCCESS)
694 break;
695 if (PAGE_ADDRESS(Addr) == PAGE_ADDRESS(Addr + cbSize - 1))
696 break;
697 }
698 }
699 return rc;
700}
701
702
703/**
704 * Emulation of the invlpg instruction (HC only actually).
705 *
706 * @returns Strict VBox status code, special care required.
707 * @retval VINF_PGM_SYNC_CR3 - handled.
708 * @retval VINF_EM_RAW_EMULATE_INSTR - not handled (RC only).
709 * @retval VERR_REM_FLUSHED_PAGES_OVERFLOW - not handled.
710 *
711 * @param pVCpu Pointer to the VMCPU.
712 * @param GCPtrPage Page to invalidate.
713 *
714 * @remark ASSUMES the page table entry or page directory is valid. Fairly
715 * safe, but there could be edge cases!
716 *
717 * @todo Flush page or page directory only if necessary!
718 * @todo VBOXSTRICTRC
719 */
720VMMDECL(int) PGMInvalidatePage(PVMCPU pVCpu, RTGCPTR GCPtrPage)
721{
722 PVM pVM = pVCpu->CTX_SUFF(pVM);
723 int rc;
724 Log3(("PGMInvalidatePage: GCPtrPage=%RGv\n", GCPtrPage));
725
726#if !defined(IN_RING3) && defined(VBOX_WITH_REM)
727 /*
728 * Notify the recompiler so it can record this instruction.
729 */
730 REMNotifyInvalidatePage(pVM, GCPtrPage);
731#endif /* !IN_RING3 */
732
733
734#ifdef IN_RC
735 /*
736 * Check for conflicts and pending CR3 monitoring updates.
737 */
738 if (pgmMapAreMappingsFloating(pVM))
739 {
740 if ( pgmGetMapping(pVM, GCPtrPage)
741 && PGMGstGetPage(pVCpu, GCPtrPage, NULL, NULL) != VERR_PAGE_TABLE_NOT_PRESENT)
742 {
743 LogFlow(("PGMGCInvalidatePage: Conflict!\n"));
744 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
745 STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatRCInvlPgConflict);
746 return VINF_PGM_SYNC_CR3;
747 }
748
749 if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
750 {
751 LogFlow(("PGMGCInvalidatePage: PGM_SYNC_MONITOR_CR3 -> reinterpret instruction in R3\n"));
752 STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatRCInvlPgSyncMonCR3);
753 return VINF_EM_RAW_EMULATE_INSTR;
754 }
755 }
756#endif /* IN_RC */
757
758 /*
759 * Call paging mode specific worker.
760 */
761 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePage), a);
762 pgmLock(pVM);
763 rc = PGM_BTH_PFN(InvalidatePage, pVCpu)(pVCpu, GCPtrPage);
764 pgmUnlock(pVM);
765 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePage), a);
766
767#ifdef IN_RING3
768 /*
769 * Check if we have a pending update of the CR3 monitoring.
770 */
771 if ( RT_SUCCESS(rc)
772 && (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3))
773 {
774 pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
775 Assert(!pVM->pgm.s.fMappingsFixed); Assert(pgmMapAreMappingsEnabled(pVM));
776 }
777
778# ifdef VBOX_WITH_RAW_MODE
779 /*
780 * Inform CSAM about the flush
781 *
782 * Note: This is to check if monitored pages have been changed; when we implement
783 * callbacks for virtual handlers, this is no longer required.
784 */
785 CSAMR3FlushPage(pVM, GCPtrPage);
786# endif
787#endif /* IN_RING3 */
788
789 /* Ignore all irrelevant error codes. */
790 if ( rc == VERR_PAGE_NOT_PRESENT
791 || rc == VERR_PAGE_TABLE_NOT_PRESENT
792 || rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT
793 || rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT)
794 rc = VINF_SUCCESS;
795
796 return rc;
797}
798
799
800/**
801 * Executes an instruction using the interpreter.
802 *
803 * @returns VBox status code (appropriate for trap handling and GC return).
804 * @param pVM Pointer to the VM.
805 * @param pVCpu Pointer to the VMCPU.
806 * @param pRegFrame Register frame.
807 * @param pvFault Fault address.
808 */
809VMMDECL(VBOXSTRICTRC) PGMInterpretInstruction(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
810{
811 VBOXSTRICTRC rc = EMInterpretInstruction(pVCpu, pRegFrame, pvFault);
812 if (rc == VERR_EM_INTERPRETER)
813 rc = VINF_EM_RAW_EMULATE_INSTR;
814 if (rc != VINF_SUCCESS)
815 Log(("PGMInterpretInstruction: returns %Rrc (pvFault=%RGv)\n", VBOXSTRICTRC_VAL(rc), pvFault));
816 return rc;
817}
818
819
820/**
821 * Gets effective page information (from the VMM page directory).
822 *
823 * @returns VBox status.
824 * @param pVCpu Pointer to the VMCPU.
825 * @param GCPtr Guest Context virtual address of the page.
826 * @param pfFlags Where to store the flags. These are X86_PTE_*.
827 * @param pHCPhys Where to store the HC physical address of the page.
828 * This is page aligned.
829 * @remark You should use PGMMapGetPage() for pages in a mapping.
830 */
831VMMDECL(int) PGMShwGetPage(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys)
832{
833 pgmLock(pVCpu->CTX_SUFF(pVM));
834 int rc = PGM_SHW_PFN(GetPage, pVCpu)(pVCpu, GCPtr, pfFlags, pHCPhys);
835 pgmUnlock(pVCpu->CTX_SUFF(pVM));
836 return rc;
837}
838
839
840/**
841 * Modify page flags for a range of pages in the shadow context.
842 *
843 * The existing flags are ANDed with the fMask and ORed with the fFlags.
844 *
845 * @returns VBox status code.
846 * @param pVCpu Pointer to the VMCPU.
847 * @param GCPtr Virtual address of the first page in the range.
848 * @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
849 * @param fMask The AND mask - page flags X86_PTE_*.
850 * Be very CAREFUL when ~'ing constants which could be 32-bit!
851 * @param fOpFlags A combination of the PGM_MK_PK_XXX flags.
852 * @remark You must use PGMMapModifyPage() for pages in a mapping.
853 */
854DECLINLINE(int) pdmShwModifyPage(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags)
855{
856 AssertMsg(!(fFlags & X86_PTE_PAE_PG_MASK), ("fFlags=%#llx\n", fFlags));
857 Assert(!(fOpFlags & ~(PGM_MK_PG_IS_MMIO2 | PGM_MK_PG_IS_WRITE_FAULT)));
858
859 GCPtr &= PAGE_BASE_GC_MASK; /** @todo this ain't necessary, right... */
860
861 PVM pVM = pVCpu->CTX_SUFF(pVM);
862 pgmLock(pVM);
863 int rc = PGM_SHW_PFN(ModifyPage, pVCpu)(pVCpu, GCPtr, PAGE_SIZE, fFlags, fMask, fOpFlags);
864 pgmUnlock(pVM);
865 return rc;
866}
867
868
869/**
870 * Changing the page flags for a single page in the shadow page tables so as to
871 * make it read-only.
872 *
873 * @returns VBox status code.
874 * @param pVCpu Pointer to the VMCPU.
875 * @param GCPtr Virtual address of the first page in the range.
876 * @param fOpFlags A combination of the PGM_MK_PK_XXX flags.
877 */
878VMMDECL(int) PGMShwMakePageReadonly(PVMCPU pVCpu, RTGCPTR GCPtr, uint32_t fOpFlags)
879{
880 return pdmShwModifyPage(pVCpu, GCPtr, 0, ~(uint64_t)X86_PTE_RW, fOpFlags);
881}
882
883
884/**
885 * Changing the page flags for a single page in the shadow page tables so as to
886 * make it writable.
887 *
888 * The call must know with 101% certainty that the guest page tables maps this
889 * as writable too. This function will deal shared, zero and write monitored
890 * pages.
891 *
892 * @returns VBox status code.
893 * @param pVCpu Pointer to the VMCPU.
894 * @param GCPtr Virtual address of the first page in the range.
895 * @param fMmio2 Set if it is an MMIO2 page.
896 * @param fOpFlags A combination of the PGM_MK_PK_XXX flags.
897 */
898VMMDECL(int) PGMShwMakePageWritable(PVMCPU pVCpu, RTGCPTR GCPtr, uint32_t fOpFlags)
899{
900 return pdmShwModifyPage(pVCpu, GCPtr, X86_PTE_RW, ~(uint64_t)0, fOpFlags);
901}
902
903
904/**
905 * Changing the page flags for a single page in the shadow page tables so as to
906 * make it not present.
907 *
908 * @returns VBox status code.
909 * @param pVCpu Pointer to the VMCPU.
910 * @param GCPtr Virtual address of the first page in the range.
911 * @param fOpFlags A combination of the PGM_MK_PG_XXX flags.
912 */
913VMMDECL(int) PGMShwMakePageNotPresent(PVMCPU pVCpu, RTGCPTR GCPtr, uint32_t fOpFlags)
914{
915 return pdmShwModifyPage(pVCpu, GCPtr, 0, 0, fOpFlags);
916}
917
918
919/**
920 * Changing the page flags for a single page in the shadow page tables so as to
921 * make it supervisor and writable.
922 *
923 * This if for dealing with CR0.WP=0 and readonly user pages.
924 *
925 * @returns VBox status code.
926 * @param pVCpu Pointer to the VMCPU.
927 * @param GCPtr Virtual address of the first page in the range.
928 * @param fOpFlags A combination of the PGM_MK_PG_XXX flags.
929 */
930int pgmShwMakePageSupervisorAndWritable(PVMCPU pVCpu, RTGCPTR GCPtr, uint32_t fOpFlags)
931{
932 return pdmShwModifyPage(pVCpu, GCPtr, X86_PTE_RW, ~(uint64_t)X86_PTE_US, fOpFlags);
933}
934
935
936/**
937 * Gets the shadow page directory for the specified address, PAE.
938 *
939 * @returns Pointer to the shadow PD.
940 * @param pVCpu Pointer to the VMCPU.
941 * @param GCPtr The address.
942 * @param uGstPdpe Guest PDPT entry. Valid.
943 * @param ppPD Receives address of page directory
944 */
945int pgmShwSyncPaePDPtr(PVMCPU pVCpu, RTGCPTR GCPtr, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD)
946{
947 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
948 PX86PDPT pPdpt = pgmShwGetPaePDPTPtr(pVCpu);
949 PX86PDPE pPdpe = &pPdpt->a[iPdPt];
950 PVM pVM = pVCpu->CTX_SUFF(pVM);
951 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
952 PPGMPOOLPAGE pShwPage;
953 int rc;
954
955 PGM_LOCK_ASSERT_OWNER(pVM);
956
957 /* Allocate page directory if not present. */
958 if ( !pPdpe->n.u1Present
959 && !(pPdpe->u & X86_PDPE_PG_MASK))
960 {
961 RTGCPTR64 GCPdPt;
962 PGMPOOLKIND enmKind;
963
964 if (pVM->pgm.s.fNestedPaging || !CPUMIsGuestPagingEnabled(pVCpu))
965 {
966 /* AMD-V nested paging or real/protected mode without paging. */
967 GCPdPt = (RTGCPTR64)iPdPt << X86_PDPT_SHIFT;
968 enmKind = PGMPOOLKIND_PAE_PD_PHYS;
969 }
970 else
971 {
972 if (CPUMGetGuestCR4(pVCpu) & X86_CR4_PAE)
973 {
974 if (!(uGstPdpe & X86_PDPE_P))
975 {
976 /* PD not present; guest must reload CR3 to change it.
977 * No need to monitor anything in this case.
978 */
979 Assert(!HMIsEnabled(pVM));
980
981 GCPdPt = uGstPdpe & X86_PDPE_PG_MASK;
982 enmKind = PGMPOOLKIND_PAE_PD_PHYS;
983 uGstPdpe |= X86_PDPE_P;
984 }
985 else
986 {
987 GCPdPt = uGstPdpe & X86_PDPE_PG_MASK;
988 enmKind = PGMPOOLKIND_PAE_PD_FOR_PAE_PD;
989 }
990 }
991 else
992 {
993 GCPdPt = CPUMGetGuestCR3(pVCpu);
994 enmKind = (PGMPOOLKIND)(PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD + iPdPt);
995 }
996 }
997
998 /* Create a reference back to the PDPT by using the index in its shadow page. */
999 rc = pgmPoolAlloc(pVM, GCPdPt, enmKind, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
1000 pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPdPt, false /*fLockPage*/,
1001 &pShwPage);
1002 AssertRCReturn(rc, rc);
1003
1004 /* The PD was cached or created; hook it up now. */
1005 pPdpe->u |= pShwPage->Core.Key | (uGstPdpe & (X86_PDPE_P | X86_PDPE_A));
1006
1007# if defined(IN_RC)
1008 /*
1009 * In 32 bits PAE mode we *must* invalidate the TLB when changing a
1010 * PDPT entry; the CPU fetches them only during cr3 load, so any
1011 * non-present PDPT will continue to cause page faults.
1012 */
1013 ASMReloadCR3();
1014# endif
1015 PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdpe);
1016 }
1017 else
1018 {
1019 pShwPage = pgmPoolGetPage(pPool, pPdpe->u & X86_PDPE_PG_MASK);
1020 AssertReturn(pShwPage, VERR_PGM_POOL_GET_PAGE_FAILED);
1021 Assert((pPdpe->u & X86_PDPE_PG_MASK) == pShwPage->Core.Key);
1022
1023 pgmPoolCacheUsed(pPool, pShwPage);
1024 }
1025 *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1026 return VINF_SUCCESS;
1027}
1028
1029
1030/**
1031 * Gets the pointer to the shadow page directory entry for an address, PAE.
1032 *
1033 * @returns Pointer to the PDE.
1034 * @param pVCpu The current CPU.
1035 * @param GCPtr The address.
1036 * @param ppShwPde Receives the address of the pgm pool page for the shadow page directory
1037 */
1038DECLINLINE(int) pgmShwGetPaePoolPagePD(PVMCPU pVCpu, RTGCPTR GCPtr, PPGMPOOLPAGE *ppShwPde)
1039{
1040 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
1041 PX86PDPT pPdpt = pgmShwGetPaePDPTPtr(pVCpu);
1042 PVM pVM = pVCpu->CTX_SUFF(pVM);
1043
1044 PGM_LOCK_ASSERT_OWNER(pVM);
1045
1046 AssertReturn(pPdpt, VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT); /* can't happen */
1047 if (!pPdpt->a[iPdPt].n.u1Present)
1048 {
1049 LogFlow(("pgmShwGetPaePoolPagePD: PD %d not present (%RX64)\n", iPdPt, pPdpt->a[iPdPt].u));
1050 return VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT;
1051 }
1052 AssertMsg(pPdpt->a[iPdPt].u & X86_PDPE_PG_MASK, ("GCPtr=%RGv\n", GCPtr));
1053
1054 /* Fetch the pgm pool shadow descriptor. */
1055 PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pVM->pgm.s.CTX_SUFF(pPool), pPdpt->a[iPdPt].u & X86_PDPE_PG_MASK);
1056 AssertReturn(pShwPde, VERR_PGM_POOL_GET_PAGE_FAILED);
1057
1058 *ppShwPde = pShwPde;
1059 return VINF_SUCCESS;
1060}
1061
1062#ifndef IN_RC
1063
1064/**
1065 * Syncs the SHADOW page directory pointer for the specified address.
1066 *
1067 * Allocates backing pages in case the PDPT or PML4 entry is missing.
1068 *
1069 * The caller is responsible for making sure the guest has a valid PD before
1070 * calling this function.
1071 *
1072 * @returns VBox status.
1073 * @param pVCpu Pointer to the VMCPU.
1074 * @param GCPtr The address.
1075 * @param uGstPml4e Guest PML4 entry (valid).
1076 * @param uGstPdpe Guest PDPT entry (valid).
1077 * @param ppPD Receives address of page directory
1078 */
1079static int pgmShwSyncLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, X86PGPAEUINT uGstPml4e, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD)
1080{
1081 PVM pVM = pVCpu->CTX_SUFF(pVM);
1082 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1083 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
1084 PX86PML4E pPml4e = pgmShwGetLongModePML4EPtr(pVCpu, iPml4);
1085 bool fNestedPagingOrNoGstPaging = pVM->pgm.s.fNestedPaging || !CPUMIsGuestPagingEnabled(pVCpu);
1086 PPGMPOOLPAGE pShwPage;
1087 int rc;
1088
1089 PGM_LOCK_ASSERT_OWNER(pVM);
1090
1091 /* Allocate page directory pointer table if not present. */
1092 if ( !pPml4e->n.u1Present
1093 && !(pPml4e->u & X86_PML4E_PG_MASK))
1094 {
1095 RTGCPTR64 GCPml4;
1096 PGMPOOLKIND enmKind;
1097
1098 Assert(pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
1099
1100 if (fNestedPagingOrNoGstPaging)
1101 {
1102 /* AMD-V nested paging or real/protected mode without paging */
1103 GCPml4 = (RTGCPTR64)iPml4 << X86_PML4_SHIFT;
1104 enmKind = PGMPOOLKIND_64BIT_PDPT_FOR_PHYS;
1105 }
1106 else
1107 {
1108 GCPml4 = uGstPml4e & X86_PML4E_PG_MASK;
1109 enmKind = PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT;
1110 }
1111
1112 /* Create a reference back to the PDPT by using the index in its shadow page. */
1113 rc = pgmPoolAlloc(pVM, GCPml4, enmKind, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
1114 pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPml4, false /*fLockPage*/,
1115 &pShwPage);
1116 AssertRCReturn(rc, rc);
1117 }
1118 else
1119 {
1120 pShwPage = pgmPoolGetPage(pPool, pPml4e->u & X86_PML4E_PG_MASK);
1121 AssertReturn(pShwPage, VERR_PGM_POOL_GET_PAGE_FAILED);
1122
1123 pgmPoolCacheUsed(pPool, pShwPage);
1124 }
1125 /* The PDPT was cached or created; hook it up now. */
1126 pPml4e->u |= pShwPage->Core.Key | (uGstPml4e & pVCpu->pgm.s.fGstAmd64ShadowedPml4eMask);
1127
1128 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1129 PX86PDPT pPdpt = (PX86PDPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1130 PX86PDPE pPdpe = &pPdpt->a[iPdPt];
1131
1132 /* Allocate page directory if not present. */
1133 if ( !pPdpe->n.u1Present
1134 && !(pPdpe->u & X86_PDPE_PG_MASK))
1135 {
1136 RTGCPTR64 GCPdPt;
1137 PGMPOOLKIND enmKind;
1138
1139 if (fNestedPagingOrNoGstPaging)
1140 {
1141 /* AMD-V nested paging or real/protected mode without paging */
1142 GCPdPt = (RTGCPTR64)iPdPt << X86_PDPT_SHIFT;
1143 enmKind = PGMPOOLKIND_64BIT_PD_FOR_PHYS;
1144 }
1145 else
1146 {
1147 GCPdPt = uGstPdpe & X86_PDPE_PG_MASK;
1148 enmKind = PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD;
1149 }
1150
1151 /* Create a reference back to the PDPT by using the index in its shadow page. */
1152 rc = pgmPoolAlloc(pVM, GCPdPt, enmKind, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
1153 pShwPage->idx, iPdPt, false /*fLockPage*/,
1154 &pShwPage);
1155 AssertRCReturn(rc, rc);
1156 }
1157 else
1158 {
1159 pShwPage = pgmPoolGetPage(pPool, pPdpe->u & X86_PDPE_PG_MASK);
1160 AssertReturn(pShwPage, VERR_PGM_POOL_GET_PAGE_FAILED);
1161
1162 pgmPoolCacheUsed(pPool, pShwPage);
1163 }
1164 /* The PD was cached or created; hook it up now. */
1165 pPdpe->u |= pShwPage->Core.Key | (uGstPdpe & pVCpu->pgm.s.fGstAmd64ShadowedPdpeMask);
1166
1167 *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1168 return VINF_SUCCESS;
1169}
1170
1171
1172/**
1173 * Gets the SHADOW page directory pointer for the specified address (long mode).
1174 *
1175 * @returns VBox status.
1176 * @param pVCpu Pointer to the VMCPU.
1177 * @param GCPtr The address.
1178 * @param ppPdpt Receives address of pdpt
1179 * @param ppPD Receives address of page directory
1180 */
1181DECLINLINE(int) pgmShwGetLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPT *ppPdpt, PX86PDPAE *ppPD)
1182{
1183 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
1184 PCX86PML4E pPml4e = pgmShwGetLongModePML4EPtr(pVCpu, iPml4);
1185
1186 PGM_LOCK_ASSERT_OWNER(pVCpu->CTX_SUFF(pVM));
1187
1188 AssertReturn(pPml4e, VERR_PGM_PML4_MAPPING);
1189 if (ppPml4e)
1190 *ppPml4e = (PX86PML4E)pPml4e;
1191
1192 Log4(("pgmShwGetLongModePDPtr %RGv (%RHv) %RX64\n", GCPtr, pPml4e, pPml4e->u));
1193
1194 if (!pPml4e->n.u1Present)
1195 return VERR_PAGE_MAP_LEVEL4_NOT_PRESENT;
1196
1197 PVM pVM = pVCpu->CTX_SUFF(pVM);
1198 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1199 PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPml4e->u & X86_PML4E_PG_MASK);
1200 AssertReturn(pShwPage, VERR_PGM_POOL_GET_PAGE_FAILED);
1201
1202 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1203 PCX86PDPT pPdpt = *ppPdpt = (PX86PDPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1204 if (!pPdpt->a[iPdPt].n.u1Present)
1205 return VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT;
1206
1207 pShwPage = pgmPoolGetPage(pPool, pPdpt->a[iPdPt].u & X86_PDPE_PG_MASK);
1208 AssertReturn(pShwPage, VERR_PGM_POOL_GET_PAGE_FAILED);
1209
1210 *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1211 Log4(("pgmShwGetLongModePDPtr %RGv -> *ppPD=%p PDE=%p/%RX64\n", GCPtr, *ppPD, &(*ppPD)->a[(GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK], (*ppPD)->a[(GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK].u));
1212 return VINF_SUCCESS;
1213}
1214
1215
1216/**
1217 * Syncs the SHADOW EPT page directory pointer for the specified address. Allocates
1218 * backing pages in case the PDPT or PML4 entry is missing.
1219 *
1220 * @returns VBox status.
1221 * @param pVCpu Pointer to the VMCPU.
1222 * @param GCPtr The address.
1223 * @param ppPdpt Receives address of pdpt
1224 * @param ppPD Receives address of page directory
1225 */
1226static int pgmShwGetEPTPDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PEPTPDPT *ppPdpt, PEPTPD *ppPD)
1227{
1228 PVM pVM = pVCpu->CTX_SUFF(pVM);
1229 const unsigned iPml4 = (GCPtr >> EPT_PML4_SHIFT) & EPT_PML4_MASK;
1230 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1231 PEPTPML4 pPml4;
1232 PEPTPML4E pPml4e;
1233 PPGMPOOLPAGE pShwPage;
1234 int rc;
1235
1236 Assert(pVM->pgm.s.fNestedPaging);
1237 PGM_LOCK_ASSERT_OWNER(pVM);
1238
1239 pPml4 = (PEPTPML4)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
1240 Assert(pPml4);
1241
1242 /* Allocate page directory pointer table if not present. */
1243 pPml4e = &pPml4->a[iPml4];
1244 if ( !pPml4e->n.u1Present
1245 && !(pPml4e->u & EPT_PML4E_PG_MASK))
1246 {
1247 Assert(!(pPml4e->u & EPT_PML4E_PG_MASK));
1248 RTGCPTR64 GCPml4 = (RTGCPTR64)iPml4 << EPT_PML4_SHIFT;
1249
1250 rc = pgmPoolAlloc(pVM, GCPml4, PGMPOOLKIND_EPT_PDPT_FOR_PHYS, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
1251 pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPml4, false /*fLockPage*/,
1252 &pShwPage);
1253 AssertRCReturn(rc, rc);
1254 }
1255 else
1256 {
1257 pShwPage = pgmPoolGetPage(pPool, pPml4e->u & EPT_PML4E_PG_MASK);
1258 AssertReturn(pShwPage, VERR_PGM_POOL_GET_PAGE_FAILED);
1259
1260 pgmPoolCacheUsed(pPool, pShwPage);
1261 }
1262 /* The PDPT was cached or created; hook it up now and fill with the default value. */
1263 pPml4e->u = pShwPage->Core.Key;
1264 pPml4e->n.u1Present = 1;
1265 pPml4e->n.u1Write = 1;
1266 pPml4e->n.u1Execute = 1;
1267
1268 const unsigned iPdPt = (GCPtr >> EPT_PDPT_SHIFT) & EPT_PDPT_MASK;
1269 PEPTPDPT pPdpt = (PEPTPDPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1270 PEPTPDPTE pPdpe = &pPdpt->a[iPdPt];
1271
1272 if (ppPdpt)
1273 *ppPdpt = pPdpt;
1274
1275 /* Allocate page directory if not present. */
1276 if ( !pPdpe->n.u1Present
1277 && !(pPdpe->u & EPT_PDPTE_PG_MASK))
1278 {
1279 RTGCPTR64 GCPdPt = (RTGCPTR64)iPdPt << EPT_PDPT_SHIFT;
1280 rc = pgmPoolAlloc(pVM, GCPdPt, PGMPOOLKIND_EPT_PD_FOR_PHYS, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
1281 pShwPage->idx, iPdPt, false /*fLockPage*/,
1282 &pShwPage);
1283 AssertRCReturn(rc, rc);
1284 }
1285 else
1286 {
1287 pShwPage = pgmPoolGetPage(pPool, pPdpe->u & EPT_PDPTE_PG_MASK);
1288 AssertReturn(pShwPage, VERR_PGM_POOL_GET_PAGE_FAILED);
1289
1290 pgmPoolCacheUsed(pPool, pShwPage);
1291 }
1292 /* The PD was cached or created; hook it up now and fill with the default value. */
1293 pPdpe->u = pShwPage->Core.Key;
1294 pPdpe->n.u1Present = 1;
1295 pPdpe->n.u1Write = 1;
1296 pPdpe->n.u1Execute = 1;
1297
1298 *ppPD = (PEPTPD)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1299 return VINF_SUCCESS;
1300}
1301
1302#endif /* IN_RC */
1303
1304#ifdef IN_RING0
1305/**
1306 * Synchronizes a range of nested page table entries.
1307 *
1308 * The caller must own the PGM lock.
1309 *
1310 * @param pVCpu The current CPU.
1311 * @param GCPhys Where to start.
1312 * @param cPages How many pages which entries should be synced.
1313 * @param enmShwPagingMode The shadow paging mode (PGMMODE_EPT for VT-x,
1314 * host paging mode for AMD-V).
1315 */
1316int pgmShwSyncNestedPageLocked(PVMCPU pVCpu, RTGCPHYS GCPhysFault, uint32_t cPages, PGMMODE enmShwPagingMode)
1317{
1318 PGM_LOCK_ASSERT_OWNER(pVCpu->CTX_SUFF(pVM));
1319
1320 int rc;
1321 switch (enmShwPagingMode)
1322 {
1323 case PGMMODE_32_BIT:
1324 {
1325 X86PDE PdeDummy = { X86_PDE_P | X86_PDE_US | X86_PDE_RW | X86_PDE_A };
1326 rc = PGM_BTH_NAME_32BIT_PROT(SyncPage)(pVCpu, PdeDummy, GCPhysFault, cPages, ~0U /*uErr*/);
1327 break;
1328 }
1329
1330 case PGMMODE_PAE:
1331 case PGMMODE_PAE_NX:
1332 {
1333 X86PDEPAE PdeDummy = { X86_PDE_P | X86_PDE_US | X86_PDE_RW | X86_PDE_A };
1334 rc = PGM_BTH_NAME_PAE_PROT(SyncPage)(pVCpu, PdeDummy, GCPhysFault, cPages, ~0U /*uErr*/);
1335 break;
1336 }
1337
1338 case PGMMODE_AMD64:
1339 case PGMMODE_AMD64_NX:
1340 {
1341 X86PDEPAE PdeDummy = { X86_PDE_P | X86_PDE_US | X86_PDE_RW | X86_PDE_A };
1342 rc = PGM_BTH_NAME_AMD64_PROT(SyncPage)(pVCpu, PdeDummy, GCPhysFault, cPages, ~0U /*uErr*/);
1343 break;
1344 }
1345
1346 case PGMMODE_EPT:
1347 {
1348 X86PDEPAE PdeDummy = { X86_PDE_P | X86_PDE_US | X86_PDE_RW | X86_PDE_A };
1349 rc = PGM_BTH_NAME_EPT_PROT(SyncPage)(pVCpu, PdeDummy, GCPhysFault, cPages, ~0U /*uErr*/);
1350 break;
1351 }
1352
1353 default:
1354 AssertMsgFailedReturn(("%d\n", enmShwPagingMode), VERR_IPE_NOT_REACHED_DEFAULT_CASE);
1355 }
1356 return rc;
1357}
1358#endif /* IN_RING0 */
1359
1360
1361/**
1362 * Gets effective Guest OS page information.
1363 *
1364 * When GCPtr is in a big page, the function will return as if it was a normal
1365 * 4KB page. If the need for distinguishing between big and normal page becomes
1366 * necessary at a later point, a PGMGstGetPage() will be created for that
1367 * purpose.
1368 *
1369 * @returns VBox status.
1370 * @param pVCpu The current CPU.
1371 * @param GCPtr Guest Context virtual address of the page.
1372 * @param pfFlags Where to store the flags. These are X86_PTE_*, even for big pages.
1373 * @param pGCPhys Where to store the GC physical address of the page.
1374 * This is page aligned. The fact that the
1375 */
1376VMMDECL(int) PGMGstGetPage(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys)
1377{
1378 VMCPU_ASSERT_EMT(pVCpu);
1379 return PGM_GST_PFN(GetPage, pVCpu)(pVCpu, GCPtr, pfFlags, pGCPhys);
1380}
1381
1382
1383/**
1384 * Checks if the page is present.
1385 *
1386 * @returns true if the page is present.
1387 * @returns false if the page is not present.
1388 * @param pVCpu Pointer to the VMCPU.
1389 * @param GCPtr Address within the page.
1390 */
1391VMMDECL(bool) PGMGstIsPagePresent(PVMCPU pVCpu, RTGCPTR GCPtr)
1392{
1393 VMCPU_ASSERT_EMT(pVCpu);
1394 int rc = PGMGstGetPage(pVCpu, GCPtr, NULL, NULL);
1395 return RT_SUCCESS(rc);
1396}
1397
1398
1399/**
1400 * Sets (replaces) the page flags for a range of pages in the guest's tables.
1401 *
1402 * @returns VBox status.
1403 * @param pVCpu Pointer to the VMCPU.
1404 * @param GCPtr The address of the first page.
1405 * @param cb The size of the range in bytes.
1406 * @param fFlags Page flags X86_PTE_*, excluding the page mask of course.
1407 */
1408VMMDECL(int) PGMGstSetPage(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags)
1409{
1410 VMCPU_ASSERT_EMT(pVCpu);
1411 return PGMGstModifyPage(pVCpu, GCPtr, cb, fFlags, 0);
1412}
1413
1414
1415/**
1416 * Modify page flags for a range of pages in the guest's tables
1417 *
1418 * The existing flags are ANDed with the fMask and ORed with the fFlags.
1419 *
1420 * @returns VBox status code.
1421 * @param pVCpu Pointer to the VMCPU.
1422 * @param GCPtr Virtual address of the first page in the range.
1423 * @param cb Size (in bytes) of the range to apply the modification to.
1424 * @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
1425 * @param fMask The AND mask - page flags X86_PTE_*, excluding the page mask of course.
1426 * Be very CAREFUL when ~'ing constants which could be 32-bit!
1427 */
1428VMMDECL(int) PGMGstModifyPage(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
1429{
1430 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,GstModifyPage), a);
1431 VMCPU_ASSERT_EMT(pVCpu);
1432
1433 /*
1434 * Validate input.
1435 */
1436 AssertMsg(!(fFlags & X86_PTE_PAE_PG_MASK), ("fFlags=%#llx\n", fFlags));
1437 Assert(cb);
1438
1439 LogFlow(("PGMGstModifyPage %RGv %d bytes fFlags=%08llx fMask=%08llx\n", GCPtr, cb, fFlags, fMask));
1440
1441 /*
1442 * Adjust input.
1443 */
1444 cb += GCPtr & PAGE_OFFSET_MASK;
1445 cb = RT_ALIGN_Z(cb, PAGE_SIZE);
1446 GCPtr = (GCPtr & PAGE_BASE_GC_MASK);
1447
1448 /*
1449 * Call worker.
1450 */
1451 int rc = PGM_GST_PFN(ModifyPage, pVCpu)(pVCpu, GCPtr, cb, fFlags, fMask);
1452
1453 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,GstModifyPage), a);
1454 return rc;
1455}
1456
1457
1458#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
1459
1460/**
1461 * Performs the lazy mapping of the 32-bit guest PD.
1462 *
1463 * @returns VBox status code.
1464 * @param pVCpu The current CPU.
1465 * @param ppPd Where to return the pointer to the mapping. This is
1466 * always set.
1467 */
1468int pgmGstLazyMap32BitPD(PVMCPU pVCpu, PX86PD *ppPd)
1469{
1470 PVM pVM = pVCpu->CTX_SUFF(pVM);
1471 pgmLock(pVM);
1472
1473 Assert(!pVCpu->pgm.s.CTX_SUFF(pGst32BitPd));
1474
1475 RTGCPHYS GCPhysCR3 = pVCpu->pgm.s.GCPhysCR3 & X86_CR3_PAGE_MASK;
1476 PPGMPAGE pPage;
1477 int rc = pgmPhysGetPageEx(pVM, GCPhysCR3, &pPage);
1478 if (RT_SUCCESS(rc))
1479 {
1480 RTHCPTR HCPtrGuestCR3;
1481 rc = pgmPhysGCPhys2CCPtrInternalDepr(pVM, pPage, GCPhysCR3, (void **)&HCPtrGuestCR3);
1482 if (RT_SUCCESS(rc))
1483 {
1484 pVCpu->pgm.s.pGst32BitPdR3 = (R3PTRTYPE(PX86PD))HCPtrGuestCR3;
1485# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1486 pVCpu->pgm.s.pGst32BitPdR0 = (R0PTRTYPE(PX86PD))HCPtrGuestCR3;
1487# endif
1488 *ppPd = (PX86PD)HCPtrGuestCR3;
1489
1490 pgmUnlock(pVM);
1491 return VINF_SUCCESS;
1492 }
1493
1494 AssertRC(rc);
1495 }
1496 pgmUnlock(pVM);
1497
1498 *ppPd = NULL;
1499 return rc;
1500}
1501
1502
1503/**
1504 * Performs the lazy mapping of the PAE guest PDPT.
1505 *
1506 * @returns VBox status code.
1507 * @param pVCpu The current CPU.
1508 * @param ppPdpt Where to return the pointer to the mapping. This is
1509 * always set.
1510 */
1511int pgmGstLazyMapPaePDPT(PVMCPU pVCpu, PX86PDPT *ppPdpt)
1512{
1513 Assert(!pVCpu->pgm.s.CTX_SUFF(pGstPaePdpt));
1514 PVM pVM = pVCpu->CTX_SUFF(pVM);
1515 pgmLock(pVM);
1516
1517 RTGCPHYS GCPhysCR3 = pVCpu->pgm.s.GCPhysCR3 & X86_CR3_PAE_PAGE_MASK;
1518 PPGMPAGE pPage;
1519 int rc = pgmPhysGetPageEx(pVM, GCPhysCR3, &pPage);
1520 if (RT_SUCCESS(rc))
1521 {
1522 RTHCPTR HCPtrGuestCR3;
1523 rc = pgmPhysGCPhys2CCPtrInternalDepr(pVM, pPage, GCPhysCR3, (void **)&HCPtrGuestCR3);
1524 if (RT_SUCCESS(rc))
1525 {
1526 pVCpu->pgm.s.pGstPaePdptR3 = (R3PTRTYPE(PX86PDPT))HCPtrGuestCR3;
1527# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1528 pVCpu->pgm.s.pGstPaePdptR0 = (R0PTRTYPE(PX86PDPT))HCPtrGuestCR3;
1529# endif
1530 *ppPdpt = (PX86PDPT)HCPtrGuestCR3;
1531
1532 pgmUnlock(pVM);
1533 return VINF_SUCCESS;
1534 }
1535
1536 AssertRC(rc);
1537 }
1538
1539 pgmUnlock(pVM);
1540 *ppPdpt = NULL;
1541 return rc;
1542}
1543
1544
1545/**
1546 * Performs the lazy mapping / updating of a PAE guest PD.
1547 *
1548 * @returns Pointer to the mapping.
1549 * @returns VBox status code.
1550 * @param pVCpu The current CPU.
1551 * @param iPdpt Which PD entry to map (0..3).
1552 * @param ppPd Where to return the pointer to the mapping. This is
1553 * always set.
1554 */
1555int pgmGstLazyMapPaePD(PVMCPU pVCpu, uint32_t iPdpt, PX86PDPAE *ppPd)
1556{
1557 PVM pVM = pVCpu->CTX_SUFF(pVM);
1558 pgmLock(pVM);
1559
1560 PX86PDPT pGuestPDPT = pVCpu->pgm.s.CTX_SUFF(pGstPaePdpt);
1561 Assert(pGuestPDPT);
1562 Assert(pGuestPDPT->a[iPdpt].n.u1Present);
1563 RTGCPHYS GCPhys = pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK;
1564 bool const fChanged = pVCpu->pgm.s.aGCPhysGstPaePDs[iPdpt] != GCPhys;
1565
1566 PPGMPAGE pPage;
1567 int rc = pgmPhysGetPageEx(pVM, GCPhys, &pPage);
1568 if (RT_SUCCESS(rc))
1569 {
1570 RTRCPTR RCPtr = NIL_RTRCPTR;
1571 RTHCPTR HCPtr = NIL_RTHCPTR;
1572#if !defined(IN_RC) && !defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1573 rc = pgmPhysGCPhys2CCPtrInternalDepr(pVM, pPage, GCPhys, &HCPtr);
1574 AssertRC(rc);
1575#endif
1576 if (RT_SUCCESS(rc) && fChanged)
1577 {
1578 RCPtr = (RTRCPTR)(RTRCUINTPTR)(pVM->pgm.s.GCPtrCR3Mapping + (1 + iPdpt) * PAGE_SIZE);
1579 rc = PGMMap(pVM, (RTRCUINTPTR)RCPtr, PGM_PAGE_GET_HCPHYS(pPage), PAGE_SIZE, 0);
1580 }
1581 if (RT_SUCCESS(rc))
1582 {
1583 pVCpu->pgm.s.apGstPaePDsR3[iPdpt] = (R3PTRTYPE(PX86PDPAE))HCPtr;
1584# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1585 pVCpu->pgm.s.apGstPaePDsR0[iPdpt] = (R0PTRTYPE(PX86PDPAE))HCPtr;
1586# endif
1587 if (fChanged)
1588 {
1589 pVCpu->pgm.s.aGCPhysGstPaePDs[iPdpt] = GCPhys;
1590 pVCpu->pgm.s.apGstPaePDsRC[iPdpt] = (RCPTRTYPE(PX86PDPAE))RCPtr;
1591 }
1592
1593 *ppPd = pVCpu->pgm.s.CTX_SUFF(apGstPaePDs)[iPdpt];
1594 pgmUnlock(pVM);
1595 return VINF_SUCCESS;
1596 }
1597 }
1598
1599 /* Invalid page or some failure, invalidate the entry. */
1600 pVCpu->pgm.s.aGCPhysGstPaePDs[iPdpt] = NIL_RTGCPHYS;
1601 pVCpu->pgm.s.apGstPaePDsR3[iPdpt] = 0;
1602# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1603 pVCpu->pgm.s.apGstPaePDsR0[iPdpt] = 0;
1604# endif
1605 pVCpu->pgm.s.apGstPaePDsRC[iPdpt] = 0;
1606
1607 pgmUnlock(pVM);
1608 return rc;
1609}
1610
1611#endif /* !VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
1612#if !defined(IN_RC) && !defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1613/**
1614 * Performs the lazy mapping of the 32-bit guest PD.
1615 *
1616 * @returns VBox status code.
1617 * @param pVCpu The current CPU.
1618 * @param ppPml4 Where to return the pointer to the mapping. This will
1619 * always be set.
1620 */
1621int pgmGstLazyMapPml4(PVMCPU pVCpu, PX86PML4 *ppPml4)
1622{
1623 Assert(!pVCpu->pgm.s.CTX_SUFF(pGstAmd64Pml4));
1624 PVM pVM = pVCpu->CTX_SUFF(pVM);
1625 pgmLock(pVM);
1626
1627 RTGCPHYS GCPhysCR3 = pVCpu->pgm.s.GCPhysCR3 & X86_CR3_AMD64_PAGE_MASK;
1628 PPGMPAGE pPage;
1629 int rc = pgmPhysGetPageEx(pVM, GCPhysCR3, &pPage);
1630 if (RT_SUCCESS(rc))
1631 {
1632 RTHCPTR HCPtrGuestCR3;
1633 rc = pgmPhysGCPhys2CCPtrInternalDepr(pVM, pPage, GCPhysCR3, (void **)&HCPtrGuestCR3);
1634 if (RT_SUCCESS(rc))
1635 {
1636 pVCpu->pgm.s.pGstAmd64Pml4R3 = (R3PTRTYPE(PX86PML4))HCPtrGuestCR3;
1637# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1638 pVCpu->pgm.s.pGstAmd64Pml4R0 = (R0PTRTYPE(PX86PML4))HCPtrGuestCR3;
1639# endif
1640 *ppPml4 = (PX86PML4)HCPtrGuestCR3;
1641
1642 pgmUnlock(pVM);
1643 return VINF_SUCCESS;
1644 }
1645 }
1646
1647 pgmUnlock(pVM);
1648 *ppPml4 = NULL;
1649 return rc;
1650}
1651#endif
1652
1653
1654/**
1655 * Gets the PAE PDPEs values cached by the CPU.
1656 *
1657 * @returns VBox status code.
1658 * @param pVCpu Pointer to the VMCPU.
1659 * @param paPdpes Where to return the four PDPEs. The array
1660 * pointed to must have 4 entries.
1661 */
1662VMM_INT_DECL(int) PGMGstGetPaePdpes(PVMCPU pVCpu, PX86PDPE paPdpes)
1663{
1664 Assert(pVCpu->pgm.s.enmShadowMode == PGMMODE_EPT);
1665
1666 paPdpes[0] = pVCpu->pgm.s.aGstPaePdpeRegs[0];
1667 paPdpes[1] = pVCpu->pgm.s.aGstPaePdpeRegs[1];
1668 paPdpes[2] = pVCpu->pgm.s.aGstPaePdpeRegs[2];
1669 paPdpes[3] = pVCpu->pgm.s.aGstPaePdpeRegs[3];
1670 return VINF_SUCCESS;
1671}
1672
1673
1674/**
1675 * Sets the PAE PDPEs values cached by the CPU.
1676 *
1677 * @remarks This must be called *AFTER* PGMUpdateCR3.
1678 *
1679 * @returns VBox status code.
1680 * @param pVCpu Pointer to the VMCPU.
1681 * @param paPdpes The four PDPE values. The array pointed to must
1682 * have exactly 4 entries.
1683 *
1684 * @remarks No-long-jump zone!!!
1685 */
1686VMM_INT_DECL(int) PGMGstUpdatePaePdpes(PVMCPU pVCpu, PCX86PDPE paPdpes)
1687{
1688 Assert(pVCpu->pgm.s.enmShadowMode == PGMMODE_EPT);
1689
1690 for (unsigned i = 0; i < RT_ELEMENTS(pVCpu->pgm.s.aGstPaePdpeRegs); i++)
1691 {
1692 if (pVCpu->pgm.s.aGstPaePdpeRegs[i].u != paPdpes[i].u)
1693 {
1694 pVCpu->pgm.s.aGstPaePdpeRegs[i] = paPdpes[i];
1695
1696 /* Force lazy remapping if it changed in any way. */
1697 pVCpu->pgm.s.apGstPaePDsR3[i] = 0;
1698# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1699 pVCpu->pgm.s.apGstPaePDsR0[i] = 0;
1700# endif
1701 pVCpu->pgm.s.apGstPaePDsRC[i] = 0;
1702 pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
1703 }
1704 }
1705
1706 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES);
1707 return VINF_SUCCESS;
1708}
1709
1710
1711/**
1712 * Gets the current CR3 register value for the shadow memory context.
1713 * @returns CR3 value.
1714 * @param pVCpu Pointer to the VMCPU.
1715 */
1716VMMDECL(RTHCPHYS) PGMGetHyperCR3(PVMCPU pVCpu)
1717{
1718 PPGMPOOLPAGE pPoolPage = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
1719 AssertPtrReturn(pPoolPage, 0);
1720 return pPoolPage->Core.Key;
1721}
1722
1723
1724/**
1725 * Gets the current CR3 register value for the nested memory context.
1726 * @returns CR3 value.
1727 * @param pVCpu Pointer to the VMCPU.
1728 */
1729VMMDECL(RTHCPHYS) PGMGetNestedCR3(PVMCPU pVCpu, PGMMODE enmShadowMode)
1730{
1731 NOREF(enmShadowMode);
1732 Assert(pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
1733 return pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->Core.Key;
1734}
1735
1736
1737/**
1738 * Gets the current CR3 register value for the HC intermediate memory context.
1739 * @returns CR3 value.
1740 * @param pVM Pointer to the VM.
1741 */
1742VMMDECL(RTHCPHYS) PGMGetInterHCCR3(PVM pVM)
1743{
1744 switch (pVM->pgm.s.enmHostMode)
1745 {
1746 case SUPPAGINGMODE_32_BIT:
1747 case SUPPAGINGMODE_32_BIT_GLOBAL:
1748 return pVM->pgm.s.HCPhysInterPD;
1749
1750 case SUPPAGINGMODE_PAE:
1751 case SUPPAGINGMODE_PAE_GLOBAL:
1752 case SUPPAGINGMODE_PAE_NX:
1753 case SUPPAGINGMODE_PAE_GLOBAL_NX:
1754 return pVM->pgm.s.HCPhysInterPaePDPT;
1755
1756 case SUPPAGINGMODE_AMD64:
1757 case SUPPAGINGMODE_AMD64_GLOBAL:
1758 case SUPPAGINGMODE_AMD64_NX:
1759 case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1760 return pVM->pgm.s.HCPhysInterPaePDPT;
1761
1762 default:
1763 AssertMsgFailed(("enmHostMode=%d\n", pVM->pgm.s.enmHostMode));
1764 return NIL_RTHCPHYS;
1765 }
1766}
1767
1768
1769/**
1770 * Gets the current CR3 register value for the RC intermediate memory context.
1771 * @returns CR3 value.
1772 * @param pVM Pointer to the VM.
1773 * @param pVCpu Pointer to the VMCPU.
1774 */
1775VMMDECL(RTHCPHYS) PGMGetInterRCCR3(PVM pVM, PVMCPU pVCpu)
1776{
1777 switch (pVCpu->pgm.s.enmShadowMode)
1778 {
1779 case PGMMODE_32_BIT:
1780 return pVM->pgm.s.HCPhysInterPD;
1781
1782 case PGMMODE_PAE:
1783 case PGMMODE_PAE_NX:
1784 return pVM->pgm.s.HCPhysInterPaePDPT;
1785
1786 case PGMMODE_AMD64:
1787 case PGMMODE_AMD64_NX:
1788 return pVM->pgm.s.HCPhysInterPaePML4;
1789
1790 case PGMMODE_EPT:
1791 case PGMMODE_NESTED:
1792 return 0; /* not relevant */
1793
1794 default:
1795 AssertMsgFailed(("enmShadowMode=%d\n", pVCpu->pgm.s.enmShadowMode));
1796 return NIL_RTHCPHYS;
1797 }
1798}
1799
1800
1801/**
1802 * Gets the CR3 register value for the 32-Bit intermediate memory context.
1803 * @returns CR3 value.
1804 * @param pVM Pointer to the VM.
1805 */
1806VMMDECL(RTHCPHYS) PGMGetInter32BitCR3(PVM pVM)
1807{
1808 return pVM->pgm.s.HCPhysInterPD;
1809}
1810
1811
1812/**
1813 * Gets the CR3 register value for the PAE intermediate memory context.
1814 * @returns CR3 value.
1815 * @param pVM Pointer to the VM.
1816 */
1817VMMDECL(RTHCPHYS) PGMGetInterPaeCR3(PVM pVM)
1818{
1819 return pVM->pgm.s.HCPhysInterPaePDPT;
1820}
1821
1822
1823/**
1824 * Gets the CR3 register value for the AMD64 intermediate memory context.
1825 * @returns CR3 value.
1826 * @param pVM Pointer to the VM.
1827 */
1828VMMDECL(RTHCPHYS) PGMGetInterAmd64CR3(PVM pVM)
1829{
1830 return pVM->pgm.s.HCPhysInterPaePML4;
1831}
1832
1833
1834/**
1835 * Performs and schedules necessary updates following a CR3 load or reload.
1836 *
1837 * This will normally involve mapping the guest PD or nPDPT
1838 *
1839 * @returns VBox status code.
1840 * @retval VINF_PGM_SYNC_CR3 if monitoring requires a CR3 sync. This can
1841 * safely be ignored and overridden since the FF will be set too then.
1842 * @param pVCpu Pointer to the VMCPU.
1843 * @param cr3 The new cr3.
1844 * @param fGlobal Indicates whether this is a global flush or not.
1845 */
1846VMMDECL(int) PGMFlushTLB(PVMCPU pVCpu, uint64_t cr3, bool fGlobal)
1847{
1848 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FlushTLB), a);
1849 PVM pVM = pVCpu->CTX_SUFF(pVM);
1850
1851 VMCPU_ASSERT_EMT(pVCpu);
1852
1853 /*
1854 * Always flag the necessary updates; necessary for hardware acceleration
1855 */
1856 /** @todo optimize this, it shouldn't always be necessary. */
1857 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
1858 if (fGlobal)
1859 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
1860 LogFlow(("PGMFlushTLB: cr3=%RX64 OldCr3=%RX64 fGlobal=%d\n", cr3, pVCpu->pgm.s.GCPhysCR3, fGlobal));
1861
1862 /*
1863 * Remap the CR3 content and adjust the monitoring if CR3 was actually changed.
1864 */
1865 int rc = VINF_SUCCESS;
1866 RTGCPHYS GCPhysCR3;
1867 switch (pVCpu->pgm.s.enmGuestMode)
1868 {
1869 case PGMMODE_PAE:
1870 case PGMMODE_PAE_NX:
1871 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAE_PAGE_MASK);
1872 break;
1873 case PGMMODE_AMD64:
1874 case PGMMODE_AMD64_NX:
1875 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_AMD64_PAGE_MASK);
1876 break;
1877 default:
1878 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAGE_MASK);
1879 break;
1880 }
1881 PGM_A20_APPLY_TO_VAR(pVCpu, GCPhysCR3);
1882
1883 if (pVCpu->pgm.s.GCPhysCR3 != GCPhysCR3)
1884 {
1885 RTGCPHYS GCPhysOldCR3 = pVCpu->pgm.s.GCPhysCR3;
1886 pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3;
1887 rc = PGM_BTH_PFN(MapCR3, pVCpu)(pVCpu, GCPhysCR3);
1888 if (RT_LIKELY(rc == VINF_SUCCESS))
1889 {
1890 if (pgmMapAreMappingsFloating(pVM))
1891 pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
1892 }
1893 else
1894 {
1895 AssertMsg(rc == VINF_PGM_SYNC_CR3, ("%Rrc\n", rc));
1896 Assert(VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL | VMCPU_FF_PGM_SYNC_CR3));
1897 pVCpu->pgm.s.GCPhysCR3 = GCPhysOldCR3;
1898 pVCpu->pgm.s.fSyncFlags |= PGM_SYNC_MAP_CR3;
1899 if (pgmMapAreMappingsFloating(pVM))
1900 pVCpu->pgm.s.fSyncFlags |= PGM_SYNC_MONITOR_CR3;
1901 }
1902
1903 if (fGlobal)
1904 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FlushTLBNewCR3Global));
1905 else
1906 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FlushTLBNewCR3));
1907 }
1908 else
1909 {
1910# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
1911 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1912 if (pPool->cDirtyPages)
1913 {
1914 pgmLock(pVM);
1915 pgmPoolResetDirtyPages(pVM);
1916 pgmUnlock(pVM);
1917 }
1918# endif
1919 /*
1920 * Check if we have a pending update of the CR3 monitoring.
1921 */
1922 if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
1923 {
1924 pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
1925 Assert(!pVM->pgm.s.fMappingsFixed); Assert(pgmMapAreMappingsEnabled(pVM));
1926 }
1927 if (fGlobal)
1928 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FlushTLBSameCR3Global));
1929 else
1930 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FlushTLBSameCR3));
1931 }
1932
1933 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FlushTLB), a);
1934 return rc;
1935}
1936
1937
1938/**
1939 * Performs and schedules necessary updates following a CR3 load or reload when
1940 * using nested or extended paging.
1941 *
1942 * This API is an alternative to PDMFlushTLB that avoids actually flushing the
1943 * TLB and triggering a SyncCR3.
1944 *
1945 * This will normally involve mapping the guest PD or nPDPT
1946 *
1947 * @returns VBox status code.
1948 * @retval VINF_SUCCESS.
1949 * @retval (If applied when not in nested mode: VINF_PGM_SYNC_CR3 if monitoring
1950 * requires a CR3 sync. This can safely be ignored and overridden since
1951 * the FF will be set too then.)
1952 * @param pVCpu Pointer to the VMCPU.
1953 * @param cr3 The new cr3.
1954 */
1955VMMDECL(int) PGMUpdateCR3(PVMCPU pVCpu, uint64_t cr3)
1956{
1957 VMCPU_ASSERT_EMT(pVCpu);
1958 LogFlow(("PGMUpdateCR3: cr3=%RX64 OldCr3=%RX64\n", cr3, pVCpu->pgm.s.GCPhysCR3));
1959
1960 /* We assume we're only called in nested paging mode. */
1961 Assert(pVCpu->CTX_SUFF(pVM)->pgm.s.fNestedPaging || pVCpu->pgm.s.enmShadowMode == PGMMODE_EPT);
1962 Assert(!pgmMapAreMappingsEnabled(pVCpu->CTX_SUFF(pVM)));
1963 Assert(!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3));
1964
1965 /*
1966 * Remap the CR3 content and adjust the monitoring if CR3 was actually changed.
1967 */
1968 int rc = VINF_SUCCESS;
1969 RTGCPHYS GCPhysCR3;
1970 switch (pVCpu->pgm.s.enmGuestMode)
1971 {
1972 case PGMMODE_PAE:
1973 case PGMMODE_PAE_NX:
1974 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAE_PAGE_MASK);
1975 break;
1976 case PGMMODE_AMD64:
1977 case PGMMODE_AMD64_NX:
1978 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_AMD64_PAGE_MASK);
1979 break;
1980 default:
1981 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAGE_MASK);
1982 break;
1983 }
1984 PGM_A20_APPLY_TO_VAR(pVCpu, GCPhysCR3);
1985
1986 if (pVCpu->pgm.s.GCPhysCR3 != GCPhysCR3)
1987 {
1988 pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3;
1989 rc = PGM_BTH_PFN(MapCR3, pVCpu)(pVCpu, GCPhysCR3);
1990 AssertRCSuccess(rc); /* Assumes VINF_PGM_SYNC_CR3 doesn't apply to nested paging. */ /** @todo this isn't true for the mac, but we need hw to test/fix this. */
1991 }
1992
1993 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_HM_UPDATE_CR3);
1994 return rc;
1995}
1996
1997
1998/**
1999 * Synchronize the paging structures.
2000 *
2001 * This function is called in response to the VM_FF_PGM_SYNC_CR3 and
2002 * VM_FF_PGM_SYNC_CR3_NONGLOBAL. Those two force action flags are set
2003 * in several places, most importantly whenever the CR3 is loaded.
2004 *
2005 * @returns VBox status code.
2006 * @param pVCpu Pointer to the VMCPU.
2007 * @param cr0 Guest context CR0 register
2008 * @param cr3 Guest context CR3 register
2009 * @param cr4 Guest context CR4 register
2010 * @param fGlobal Including global page directories or not
2011 */
2012VMMDECL(int) PGMSyncCR3(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
2013{
2014 int rc;
2015
2016 VMCPU_ASSERT_EMT(pVCpu);
2017
2018 /*
2019 * The pool may have pending stuff and even require a return to ring-3 to
2020 * clear the whole thing.
2021 */
2022 rc = pgmPoolSyncCR3(pVCpu);
2023 if (rc != VINF_SUCCESS)
2024 return rc;
2025
2026 /*
2027 * We might be called when we shouldn't.
2028 *
2029 * The mode switching will ensure that the PD is resynced after every mode
2030 * switch. So, if we find ourselves here when in protected or real mode
2031 * we can safely clear the FF and return immediately.
2032 */
2033 if (pVCpu->pgm.s.enmGuestMode <= PGMMODE_PROTECTED)
2034 {
2035 Assert((cr0 & (X86_CR0_PG | X86_CR0_PE)) != (X86_CR0_PG | X86_CR0_PE));
2036 Assert(!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL));
2037 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2038 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
2039 return VINF_SUCCESS;
2040 }
2041
2042 /* If global pages are not supported, then all flushes are global. */
2043 if (!(cr4 & X86_CR4_PGE))
2044 fGlobal = true;
2045 LogFlow(("PGMSyncCR3: cr0=%RX64 cr3=%RX64 cr4=%RX64 fGlobal=%d[%d,%d]\n", cr0, cr3, cr4, fGlobal,
2046 VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3), VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)));
2047
2048 /*
2049 * Check if we need to finish an aborted MapCR3 call (see PGMFlushTLB).
2050 * This should be done before SyncCR3.
2051 */
2052 if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MAP_CR3)
2053 {
2054 pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MAP_CR3;
2055
2056 RTGCPHYS GCPhysCR3Old = pVCpu->pgm.s.GCPhysCR3; NOREF(GCPhysCR3Old);
2057 RTGCPHYS GCPhysCR3;
2058 switch (pVCpu->pgm.s.enmGuestMode)
2059 {
2060 case PGMMODE_PAE:
2061 case PGMMODE_PAE_NX:
2062 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAE_PAGE_MASK);
2063 break;
2064 case PGMMODE_AMD64:
2065 case PGMMODE_AMD64_NX:
2066 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_AMD64_PAGE_MASK);
2067 break;
2068 default:
2069 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAGE_MASK);
2070 break;
2071 }
2072 PGM_A20_APPLY_TO_VAR(pVCpu, GCPhysCR3);
2073
2074 if (pVCpu->pgm.s.GCPhysCR3 != GCPhysCR3)
2075 {
2076 pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3;
2077 rc = PGM_BTH_PFN(MapCR3, pVCpu)(pVCpu, GCPhysCR3);
2078 }
2079
2080 /* Make sure we check for pending pgm pool syncs as we clear VMCPU_FF_PGM_SYNC_CR3 later on! */
2081 if ( rc == VINF_PGM_SYNC_CR3
2082 || (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL))
2083 {
2084 Log(("PGMSyncCR3: pending pgm pool sync after MapCR3!\n"));
2085#ifdef IN_RING3
2086 rc = pgmPoolSyncCR3(pVCpu);
2087#else
2088 if (rc == VINF_PGM_SYNC_CR3)
2089 pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3Old;
2090 return VINF_PGM_SYNC_CR3;
2091#endif
2092 }
2093 AssertRCReturn(rc, rc);
2094 AssertRCSuccessReturn(rc, VERR_IPE_UNEXPECTED_INFO_STATUS);
2095 }
2096
2097 /*
2098 * Let the 'Bth' function do the work and we'll just keep track of the flags.
2099 */
2100 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3), a);
2101 rc = PGM_BTH_PFN(SyncCR3, pVCpu)(pVCpu, cr0, cr3, cr4, fGlobal);
2102 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3), a);
2103 AssertMsg(rc == VINF_SUCCESS || rc == VINF_PGM_SYNC_CR3 || RT_FAILURE(rc), ("rc=%Rrc\n", rc));
2104 if (rc == VINF_SUCCESS)
2105 {
2106 if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL)
2107 {
2108 /* Go back to ring 3 if a pgm pool sync is again pending. */
2109 return VINF_PGM_SYNC_CR3;
2110 }
2111
2112 if (!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS))
2113 {
2114 Assert(!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL));
2115 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2116 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
2117 }
2118
2119 /*
2120 * Check if we have a pending update of the CR3 monitoring.
2121 */
2122 if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
2123 {
2124 pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
2125 Assert(!pVCpu->CTX_SUFF(pVM)->pgm.s.fMappingsFixed);
2126 Assert(pgmMapAreMappingsEnabled(pVCpu->CTX_SUFF(pVM)));
2127 }
2128 }
2129
2130 /*
2131 * Now flush the CR3 (guest context).
2132 */
2133 if (rc == VINF_SUCCESS)
2134 PGM_INVL_VCPU_TLBS(pVCpu);
2135 return rc;
2136}
2137
2138
2139/**
2140 * Called whenever CR0 or CR4 in a way which may affect the paging mode.
2141 *
2142 * @returns VBox status code, with the following informational code for
2143 * VM scheduling.
2144 * @retval VINF_SUCCESS if the was no change, or it was successfully dealt with.
2145 * @retval VINF_PGM_CHANGE_MODE if we're in RC or R0 and the mode changes.
2146 * (I.e. not in R3.)
2147 * @retval VINF_EM_SUSPEND or VINF_EM_OFF on a fatal runtime error. (R3 only)
2148 *
2149 * @param pVCpu Pointer to the VMCPU.
2150 * @param cr0 The new cr0.
2151 * @param cr4 The new cr4.
2152 * @param efer The new extended feature enable register.
2153 */
2154VMMDECL(int) PGMChangeMode(PVMCPU pVCpu, uint64_t cr0, uint64_t cr4, uint64_t efer)
2155{
2156 PGMMODE enmGuestMode;
2157
2158 VMCPU_ASSERT_EMT(pVCpu);
2159
2160 /*
2161 * Calc the new guest mode.
2162 */
2163 if (!(cr0 & X86_CR0_PE))
2164 enmGuestMode = PGMMODE_REAL;
2165 else if (!(cr0 & X86_CR0_PG))
2166 enmGuestMode = PGMMODE_PROTECTED;
2167 else if (!(cr4 & X86_CR4_PAE))
2168 {
2169 bool const fPse = !!(cr4 & X86_CR4_PSE);
2170 if (pVCpu->pgm.s.fGst32BitPageSizeExtension != fPse)
2171 Log(("PGMChangeMode: CR4.PSE %d -> %d\n", pVCpu->pgm.s.fGst32BitPageSizeExtension, fPse));
2172 pVCpu->pgm.s.fGst32BitPageSizeExtension = fPse;
2173 enmGuestMode = PGMMODE_32_BIT;
2174 }
2175 else if (!(efer & MSR_K6_EFER_LME))
2176 {
2177 if (!(efer & MSR_K6_EFER_NXE))
2178 enmGuestMode = PGMMODE_PAE;
2179 else
2180 enmGuestMode = PGMMODE_PAE_NX;
2181 }
2182 else
2183 {
2184 if (!(efer & MSR_K6_EFER_NXE))
2185 enmGuestMode = PGMMODE_AMD64;
2186 else
2187 enmGuestMode = PGMMODE_AMD64_NX;
2188 }
2189
2190 /*
2191 * Did it change?
2192 */
2193 if (pVCpu->pgm.s.enmGuestMode == enmGuestMode)
2194 return VINF_SUCCESS;
2195
2196 /* Flush the TLB */
2197 PGM_INVL_VCPU_TLBS(pVCpu);
2198
2199#ifdef IN_RING3
2200 return PGMR3ChangeMode(pVCpu->CTX_SUFF(pVM), pVCpu, enmGuestMode);
2201#else
2202 LogFlow(("PGMChangeMode: returns VINF_PGM_CHANGE_MODE.\n"));
2203 return VINF_PGM_CHANGE_MODE;
2204#endif
2205}
2206
2207
2208/**
2209 * Called by CPUM or REM when CR0.WP changes to 1.
2210 *
2211 * @param pVCpu The cross context virtual CPU structure of the caller.
2212 * @thread EMT
2213 */
2214VMMDECL(void) PGMCr0WpEnabled(PVMCPU pVCpu)
2215{
2216 /*
2217 * Netware WP0+RO+US hack cleanup when WP0 -> WP1.
2218 *
2219 * Use the counter to judge whether there might be pool pages with active
2220 * hacks in them. If there are, we will be running the risk of messing up
2221 * the guest by allowing it to write to read-only pages. Thus, we have to
2222 * clear the page pool ASAP if there is the slightest chance.
2223 */
2224 if (pVCpu->pgm.s.cNetwareWp0Hacks > 0)
2225 {
2226 Assert(pVCpu->CTX_SUFF(pVM)->cCpus == 1);
2227
2228 Log(("PGMCr0WpEnabled: %llu WP0 hacks active - clearing page pool\n", pVCpu->pgm.s.cNetwareWp0Hacks));
2229 pVCpu->pgm.s.cNetwareWp0Hacks = 0;
2230 pVCpu->pgm.s.fSyncFlags |= PGM_SYNC_CLEAR_PGM_POOL;
2231 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2232 }
2233}
2234
2235
2236/**
2237 * Gets the current guest paging mode.
2238 *
2239 * If you just need the CPU mode (real/protected/long), use CPUMGetGuestMode().
2240 *
2241 * @returns The current paging mode.
2242 * @param pVCpu Pointer to the VMCPU.
2243 */
2244VMMDECL(PGMMODE) PGMGetGuestMode(PVMCPU pVCpu)
2245{
2246 return pVCpu->pgm.s.enmGuestMode;
2247}
2248
2249
2250/**
2251 * Gets the current shadow paging mode.
2252 *
2253 * @returns The current paging mode.
2254 * @param pVCpu Pointer to the VMCPU.
2255 */
2256VMMDECL(PGMMODE) PGMGetShadowMode(PVMCPU pVCpu)
2257{
2258 return pVCpu->pgm.s.enmShadowMode;
2259}
2260
2261
2262/**
2263 * Gets the current host paging mode.
2264 *
2265 * @returns The current paging mode.
2266 * @param pVM Pointer to the VM.
2267 */
2268VMMDECL(PGMMODE) PGMGetHostMode(PVM pVM)
2269{
2270 switch (pVM->pgm.s.enmHostMode)
2271 {
2272 case SUPPAGINGMODE_32_BIT:
2273 case SUPPAGINGMODE_32_BIT_GLOBAL:
2274 return PGMMODE_32_BIT;
2275
2276 case SUPPAGINGMODE_PAE:
2277 case SUPPAGINGMODE_PAE_GLOBAL:
2278 return PGMMODE_PAE;
2279
2280 case SUPPAGINGMODE_PAE_NX:
2281 case SUPPAGINGMODE_PAE_GLOBAL_NX:
2282 return PGMMODE_PAE_NX;
2283
2284 case SUPPAGINGMODE_AMD64:
2285 case SUPPAGINGMODE_AMD64_GLOBAL:
2286 return PGMMODE_AMD64;
2287
2288 case SUPPAGINGMODE_AMD64_NX:
2289 case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2290 return PGMMODE_AMD64_NX;
2291
2292 default: AssertMsgFailed(("enmHostMode=%d\n", pVM->pgm.s.enmHostMode)); break;
2293 }
2294
2295 return PGMMODE_INVALID;
2296}
2297
2298
2299/**
2300 * Get mode name.
2301 *
2302 * @returns read-only name string.
2303 * @param enmMode The mode which name is desired.
2304 */
2305VMMDECL(const char *) PGMGetModeName(PGMMODE enmMode)
2306{
2307 switch (enmMode)
2308 {
2309 case PGMMODE_REAL: return "Real";
2310 case PGMMODE_PROTECTED: return "Protected";
2311 case PGMMODE_32_BIT: return "32-bit";
2312 case PGMMODE_PAE: return "PAE";
2313 case PGMMODE_PAE_NX: return "PAE+NX";
2314 case PGMMODE_AMD64: return "AMD64";
2315 case PGMMODE_AMD64_NX: return "AMD64+NX";
2316 case PGMMODE_NESTED: return "Nested";
2317 case PGMMODE_EPT: return "EPT";
2318 default: return "unknown mode value";
2319 }
2320}
2321
2322
2323
2324/**
2325 * Notification from CPUM that the EFER.NXE bit has changed.
2326 *
2327 * @param pVCpu The virtual CPU for which EFER changed.
2328 * @param fNxe The new NXE state.
2329 */
2330VMM_INT_DECL(void) PGMNotifyNxeChanged(PVMCPU pVCpu, bool fNxe)
2331{
2332/** @todo VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu); */
2333 Log(("PGMNotifyNxeChanged: fNxe=%RTbool\n", fNxe));
2334
2335 pVCpu->pgm.s.fNoExecuteEnabled = fNxe;
2336 if (fNxe)
2337 {
2338 /*pVCpu->pgm.s.fGst32BitMbzBigPdeMask - N/A */
2339 pVCpu->pgm.s.fGstPaeMbzPteMask &= ~X86_PTE_PAE_NX;
2340 pVCpu->pgm.s.fGstPaeMbzPdeMask &= ~X86_PDE_PAE_NX;
2341 pVCpu->pgm.s.fGstPaeMbzBigPdeMask &= ~X86_PDE2M_PAE_NX;
2342 /*pVCpu->pgm.s.fGstPaeMbzPdpeMask - N/A */
2343 pVCpu->pgm.s.fGstAmd64MbzPteMask &= ~X86_PTE_PAE_NX;
2344 pVCpu->pgm.s.fGstAmd64MbzPdeMask &= ~X86_PDE_PAE_NX;
2345 pVCpu->pgm.s.fGstAmd64MbzBigPdeMask &= ~X86_PDE2M_PAE_NX;
2346 pVCpu->pgm.s.fGstAmd64MbzPdpeMask &= ~X86_PDPE_LM_NX;
2347 pVCpu->pgm.s.fGstAmd64MbzBigPdpeMask &= ~X86_PDPE_LM_NX;
2348 pVCpu->pgm.s.fGstAmd64MbzPml4eMask &= ~X86_PML4E_NX;
2349
2350 pVCpu->pgm.s.fGst64ShadowedPteMask |= X86_PTE_PAE_NX;
2351 pVCpu->pgm.s.fGst64ShadowedPdeMask |= X86_PDE_PAE_NX;
2352 pVCpu->pgm.s.fGst64ShadowedBigPdeMask |= X86_PDE2M_PAE_NX;
2353 pVCpu->pgm.s.fGst64ShadowedBigPde4PteMask |= X86_PDE2M_PAE_NX;
2354 pVCpu->pgm.s.fGstAmd64ShadowedPdpeMask |= X86_PDPE_LM_NX;
2355 pVCpu->pgm.s.fGstAmd64ShadowedPml4eMask |= X86_PML4E_NX;
2356 }
2357 else
2358 {
2359 /*pVCpu->pgm.s.fGst32BitMbzBigPdeMask - N/A */
2360 pVCpu->pgm.s.fGstPaeMbzPteMask |= X86_PTE_PAE_NX;
2361 pVCpu->pgm.s.fGstPaeMbzPdeMask |= X86_PDE_PAE_NX;
2362 pVCpu->pgm.s.fGstPaeMbzBigPdeMask |= X86_PDE2M_PAE_NX;
2363 /*pVCpu->pgm.s.fGstPaeMbzPdpeMask -N/A */
2364 pVCpu->pgm.s.fGstAmd64MbzPteMask |= X86_PTE_PAE_NX;
2365 pVCpu->pgm.s.fGstAmd64MbzPdeMask |= X86_PDE_PAE_NX;
2366 pVCpu->pgm.s.fGstAmd64MbzBigPdeMask |= X86_PDE2M_PAE_NX;
2367 pVCpu->pgm.s.fGstAmd64MbzPdpeMask |= X86_PDPE_LM_NX;
2368 pVCpu->pgm.s.fGstAmd64MbzBigPdpeMask |= X86_PDPE_LM_NX;
2369 pVCpu->pgm.s.fGstAmd64MbzPml4eMask |= X86_PML4E_NX;
2370
2371 pVCpu->pgm.s.fGst64ShadowedPteMask &= ~X86_PTE_PAE_NX;
2372 pVCpu->pgm.s.fGst64ShadowedPdeMask &= ~X86_PDE_PAE_NX;
2373 pVCpu->pgm.s.fGst64ShadowedBigPdeMask &= ~X86_PDE2M_PAE_NX;
2374 pVCpu->pgm.s.fGst64ShadowedBigPde4PteMask &= ~X86_PDE2M_PAE_NX;
2375 pVCpu->pgm.s.fGstAmd64ShadowedPdpeMask &= ~X86_PDPE_LM_NX;
2376 pVCpu->pgm.s.fGstAmd64ShadowedPml4eMask &= ~X86_PML4E_NX;
2377 }
2378}
2379
2380
2381/**
2382 * Check if any pgm pool pages are marked dirty (not monitored)
2383 *
2384 * @returns bool locked/not locked
2385 * @param pVM Pointer to the VM.
2386 */
2387VMMDECL(bool) PGMHasDirtyPages(PVM pVM)
2388{
2389 return pVM->pgm.s.CTX_SUFF(pPool)->cDirtyPages != 0;
2390}
2391
2392
2393/**
2394 * Check if this VCPU currently owns the PGM lock.
2395 *
2396 * @returns bool owner/not owner
2397 * @param pVM Pointer to the VM.
2398 */
2399VMMDECL(bool) PGMIsLockOwner(PVM pVM)
2400{
2401 return PDMCritSectIsOwner(&pVM->pgm.s.CritSectX);
2402}
2403
2404
2405/**
2406 * Enable or disable large page usage
2407 *
2408 * @returns VBox status code.
2409 * @param pVM Pointer to the VM.
2410 * @param fUseLargePages Use/not use large pages
2411 */
2412VMMDECL(int) PGMSetLargePageUsage(PVM pVM, bool fUseLargePages)
2413{
2414 VM_ASSERT_VALID_EXT_RETURN(pVM, VERR_INVALID_VM_HANDLE);
2415
2416 pVM->fUseLargePages = fUseLargePages;
2417 return VINF_SUCCESS;
2418}
2419
2420
2421/**
2422 * Acquire the PGM lock.
2423 *
2424 * @returns VBox status code
2425 * @param pVM Pointer to the VM.
2426 */
2427int pgmLock(PVM pVM)
2428{
2429 int rc = PDMCritSectEnter(&pVM->pgm.s.CritSectX, VERR_SEM_BUSY);
2430#if defined(IN_RC) || defined(IN_RING0)
2431 if (rc == VERR_SEM_BUSY)
2432 rc = VMMRZCallRing3NoCpu(pVM, VMMCALLRING3_PGM_LOCK, 0);
2433#endif
2434 AssertMsg(rc == VINF_SUCCESS, ("%Rrc\n", rc));
2435 return rc;
2436}
2437
2438
2439/**
2440 * Release the PGM lock.
2441 *
2442 * @returns VBox status code
2443 * @param pVM Pointer to the VM.
2444 */
2445void pgmUnlock(PVM pVM)
2446{
2447 uint32_t cDeprecatedPageLocks = pVM->pgm.s.cDeprecatedPageLocks;
2448 pVM->pgm.s.cDeprecatedPageLocks = 0;
2449 int rc = PDMCritSectLeave(&pVM->pgm.s.CritSectX);
2450 if (rc == VINF_SEM_NESTED)
2451 pVM->pgm.s.cDeprecatedPageLocks = cDeprecatedPageLocks;
2452}
2453
2454#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2455
2456/**
2457 * Common worker for pgmRZDynMapGCPageOffInlined and pgmRZDynMapGCPageV2Inlined.
2458 *
2459 * @returns VBox status code.
2460 * @param pVM Pointer to the VM.
2461 * @param pVCpu The current CPU.
2462 * @param GCPhys The guest physical address of the page to map. The
2463 * offset bits are not ignored.
2464 * @param ppv Where to return the address corresponding to @a GCPhys.
2465 */
2466int pgmRZDynMapGCPageCommon(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void **ppv RTLOG_COMMA_SRC_POS_DECL)
2467{
2468 pgmLock(pVM);
2469
2470 /*
2471 * Convert it to a writable page and it on to the dynamic mapper.
2472 */
2473 int rc;
2474 PPGMPAGE pPage = pgmPhysGetPage(pVM, GCPhys);
2475 if (RT_LIKELY(pPage))
2476 {
2477 rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
2478 if (RT_SUCCESS(rc))
2479 {
2480 void *pv;
2481 rc = pgmRZDynMapHCPageInlined(pVCpu, PGM_PAGE_GET_HCPHYS(pPage), &pv RTLOG_COMMA_SRC_POS_ARGS);
2482 if (RT_SUCCESS(rc))
2483 *ppv = (void *)((uintptr_t)pv | ((uintptr_t)GCPhys & PAGE_OFFSET_MASK));
2484 }
2485 else
2486 AssertRC(rc);
2487 }
2488 else
2489 {
2490 AssertMsgFailed(("Invalid physical address %RGp!\n", GCPhys));
2491 rc = VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2492 }
2493
2494 pgmUnlock(pVM);
2495 return rc;
2496}
2497
2498#endif /* IN_RC || VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
2499#if !defined(IN_R0) || defined(LOG_ENABLED)
2500
2501/** Format handler for PGMPAGE.
2502 * @copydoc FNRTSTRFORMATTYPE */
2503static DECLCALLBACK(size_t) pgmFormatTypeHandlerPage(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
2504 const char *pszType, void const *pvValue,
2505 int cchWidth, int cchPrecision, unsigned fFlags,
2506 void *pvUser)
2507{
2508 size_t cch;
2509 PCPGMPAGE pPage = (PCPGMPAGE)pvValue;
2510 if (RT_VALID_PTR(pPage))
2511 {
2512 char szTmp[64+80];
2513
2514 cch = 0;
2515
2516 /* The single char state stuff. */
2517 static const char s_achPageStates[4] = { 'Z', 'A', 'W', 'S' };
2518 szTmp[cch++] = s_achPageStates[PGM_PAGE_GET_STATE_NA(pPage)];
2519
2520#define IS_PART_INCLUDED(lvl) ( !(fFlags & RTSTR_F_PRECISION) || cchPrecision == (lvl) || cchPrecision >= (lvl)+10 )
2521 if (IS_PART_INCLUDED(5))
2522 {
2523 static const char s_achHandlerStates[4] = { '-', 't', 'w', 'a' };
2524 szTmp[cch++] = s_achHandlerStates[PGM_PAGE_GET_HNDL_PHYS_STATE(pPage)];
2525 szTmp[cch++] = s_achHandlerStates[PGM_PAGE_GET_HNDL_VIRT_STATE(pPage)];
2526 }
2527
2528 /* The type. */
2529 if (IS_PART_INCLUDED(4))
2530 {
2531 szTmp[cch++] = ':';
2532 static const char s_achPageTypes[8][4] = { "INV", "RAM", "MI2", "M2A", "SHA", "ROM", "MIO", "BAD" };
2533 szTmp[cch++] = s_achPageTypes[PGM_PAGE_GET_TYPE_NA(pPage)][0];
2534 szTmp[cch++] = s_achPageTypes[PGM_PAGE_GET_TYPE_NA(pPage)][1];
2535 szTmp[cch++] = s_achPageTypes[PGM_PAGE_GET_TYPE_NA(pPage)][2];
2536 }
2537
2538 /* The numbers. */
2539 if (IS_PART_INCLUDED(3))
2540 {
2541 szTmp[cch++] = ':';
2542 cch += RTStrFormatNumber(&szTmp[cch], PGM_PAGE_GET_HCPHYS_NA(pPage), 16, 12, 0, RTSTR_F_ZEROPAD | RTSTR_F_64BIT);
2543 }
2544
2545 if (IS_PART_INCLUDED(2))
2546 {
2547 szTmp[cch++] = ':';
2548 cch += RTStrFormatNumber(&szTmp[cch], PGM_PAGE_GET_PAGEID(pPage), 16, 7, 0, RTSTR_F_ZEROPAD | RTSTR_F_32BIT);
2549 }
2550
2551 if (IS_PART_INCLUDED(6))
2552 {
2553 szTmp[cch++] = ':';
2554 static const char s_achRefs[4] = { '-', 'U', '!', 'L' };
2555 szTmp[cch++] = s_achRefs[PGM_PAGE_GET_TD_CREFS_NA(pPage)];
2556 cch += RTStrFormatNumber(&szTmp[cch], PGM_PAGE_GET_TD_IDX_NA(pPage), 16, 4, 0, RTSTR_F_ZEROPAD | RTSTR_F_16BIT);
2557 }
2558#undef IS_PART_INCLUDED
2559
2560 cch = pfnOutput(pvArgOutput, szTmp, cch);
2561 }
2562 else
2563 cch = pfnOutput(pvArgOutput, "<bad-pgmpage-ptr>", sizeof("<bad-pgmpage-ptr>") - 1);
2564 NOREF(pszType); NOREF(cchWidth); NOREF(pvUser);
2565 return cch;
2566}
2567
2568
2569/** Format handler for PGMRAMRANGE.
2570 * @copydoc FNRTSTRFORMATTYPE */
2571static DECLCALLBACK(size_t) pgmFormatTypeHandlerRamRange(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
2572 const char *pszType, void const *pvValue,
2573 int cchWidth, int cchPrecision, unsigned fFlags,
2574 void *pvUser)
2575{
2576 size_t cch;
2577 PGMRAMRANGE const *pRam = (PGMRAMRANGE const *)pvValue;
2578 if (VALID_PTR(pRam))
2579 {
2580 char szTmp[80];
2581 cch = RTStrPrintf(szTmp, sizeof(szTmp), "%RGp-%RGp", pRam->GCPhys, pRam->GCPhysLast);
2582 cch = pfnOutput(pvArgOutput, szTmp, cch);
2583 }
2584 else
2585 cch = pfnOutput(pvArgOutput, "<bad-pgmramrange-ptr>", sizeof("<bad-pgmramrange-ptr>") - 1);
2586 NOREF(pszType); NOREF(cchWidth); NOREF(cchPrecision); NOREF(pvUser); NOREF(fFlags);
2587 return cch;
2588}
2589
2590/** Format type andlers to be registered/deregistered. */
2591static const struct
2592{
2593 char szType[24];
2594 PFNRTSTRFORMATTYPE pfnHandler;
2595} g_aPgmFormatTypes[] =
2596{
2597 { "pgmpage", pgmFormatTypeHandlerPage },
2598 { "pgmramrange", pgmFormatTypeHandlerRamRange }
2599};
2600
2601#endif /* !IN_R0 || LOG_ENABLED */
2602
2603/**
2604 * Registers the global string format types.
2605 *
2606 * This should be called at module load time or in some other manner that ensure
2607 * that it's called exactly one time.
2608 *
2609 * @returns IPRT status code on RTStrFormatTypeRegister failure.
2610 */
2611VMMDECL(int) PGMRegisterStringFormatTypes(void)
2612{
2613#if !defined(IN_R0) || defined(LOG_ENABLED)
2614 int rc = VINF_SUCCESS;
2615 unsigned i;
2616 for (i = 0; RT_SUCCESS(rc) && i < RT_ELEMENTS(g_aPgmFormatTypes); i++)
2617 {
2618 rc = RTStrFormatTypeRegister(g_aPgmFormatTypes[i].szType, g_aPgmFormatTypes[i].pfnHandler, NULL);
2619# ifdef IN_RING0
2620 if (rc == VERR_ALREADY_EXISTS)
2621 {
2622 /* in case of cleanup failure in ring-0 */
2623 RTStrFormatTypeDeregister(g_aPgmFormatTypes[i].szType);
2624 rc = RTStrFormatTypeRegister(g_aPgmFormatTypes[i].szType, g_aPgmFormatTypes[i].pfnHandler, NULL);
2625 }
2626# endif
2627 }
2628 if (RT_FAILURE(rc))
2629 while (i-- > 0)
2630 RTStrFormatTypeDeregister(g_aPgmFormatTypes[i].szType);
2631
2632 return rc;
2633#else
2634 return VINF_SUCCESS;
2635#endif
2636}
2637
2638
2639/**
2640 * Deregisters the global string format types.
2641 *
2642 * This should be called at module unload time or in some other manner that
2643 * ensure that it's called exactly one time.
2644 */
2645VMMDECL(void) PGMDeregisterStringFormatTypes(void)
2646{
2647#if !defined(IN_R0) || defined(LOG_ENABLED)
2648 for (unsigned i = 0; i < RT_ELEMENTS(g_aPgmFormatTypes); i++)
2649 RTStrFormatTypeDeregister(g_aPgmFormatTypes[i].szType);
2650#endif
2651}
2652
2653#ifdef VBOX_STRICT
2654
2655/**
2656 * Asserts that there are no mapping conflicts.
2657 *
2658 * @returns Number of conflicts.
2659 * @param pVM Pointer to the VM.
2660 */
2661VMMDECL(unsigned) PGMAssertNoMappingConflicts(PVM pVM)
2662{
2663 unsigned cErrors = 0;
2664
2665 /* Only applies to raw mode -> 1 VPCU */
2666 Assert(pVM->cCpus == 1);
2667 PVMCPU pVCpu = &pVM->aCpus[0];
2668
2669 /*
2670 * Check for mapping conflicts.
2671 */
2672 for (PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
2673 pMapping;
2674 pMapping = pMapping->CTX_SUFF(pNext))
2675 {
2676 /** @todo This is slow and should be optimized, but since it's just assertions I don't care now. */
2677 for (RTGCPTR GCPtr = pMapping->GCPtr;
2678 GCPtr <= pMapping->GCPtrLast;
2679 GCPtr += PAGE_SIZE)
2680 {
2681 int rc = PGMGstGetPage(pVCpu, (RTGCPTR)GCPtr, NULL, NULL);
2682 if (rc != VERR_PAGE_TABLE_NOT_PRESENT)
2683 {
2684 AssertMsgFailed(("Conflict at %RGv with %s\n", GCPtr, R3STRING(pMapping->pszDesc)));
2685 cErrors++;
2686 break;
2687 }
2688 }
2689 }
2690
2691 return cErrors;
2692}
2693
2694
2695/**
2696 * Asserts that everything related to the guest CR3 is correctly shadowed.
2697 *
2698 * This will call PGMAssertNoMappingConflicts() and PGMAssertHandlerAndFlagsInSync(),
2699 * and assert the correctness of the guest CR3 mapping before asserting that the
2700 * shadow page tables is in sync with the guest page tables.
2701 *
2702 * @returns Number of conflicts.
2703 * @param pVM Pointer to the VM.
2704 * @param pVCpu Pointer to the VMCPU.
2705 * @param cr3 The current guest CR3 register value.
2706 * @param cr4 The current guest CR4 register value.
2707 */
2708VMMDECL(unsigned) PGMAssertCR3(PVM pVM, PVMCPU pVCpu, uint64_t cr3, uint64_t cr4)
2709{
2710 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3), a);
2711 pgmLock(pVM);
2712 unsigned cErrors = PGM_BTH_PFN(AssertCR3, pVCpu)(pVCpu, cr3, cr4, 0, ~(RTGCPTR)0);
2713 pgmUnlock(pVM);
2714 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3), a);
2715 return cErrors;
2716}
2717
2718#endif /* VBOX_STRICT */
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette