PGMAll.cpp@ 6902

Last change on this file since 6902 was 6902, checked in by vboxsync, 17 years ago
Converted MM_RAM_FLAGS_PHYSICAL_HANDLER, _WRITE, _ALL and _TEMP_OFF into a 2-bit state field (u2HandlerPhysStateX). I've tripple checked this change, but if I overlooked something real odd stuff might happen...
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 54.9 KB

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1	/* $Id: PGMAll.cpp 6902 2008-02-11 16:51:52Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor - All context code.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 innotek GmbH
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/*******************************************************************************
19	* Header Files *
20	*******************************************************************************/
21	#define LOG_GROUP LOG_GROUP_PGM
22	#include <VBox/pgm.h>
23	#include <VBox/cpum.h>
24	#include <VBox/selm.h>
25	#include <VBox/iom.h>
26	#include <VBox/sup.h>
27	#include <VBox/mm.h>
28	#include <VBox/stam.h>
29	#include <VBox/csam.h>
30	#include <VBox/patm.h>
31	#include <VBox/trpm.h>
32	#include <VBox/rem.h>
33	#include <VBox/em.h>
34	#include "PGMInternal.h"
35	#include <VBox/vm.h>
36	#include <iprt/assert.h>
37	#include <iprt/asm.h>
38	#include <iprt/string.h>
39	#include <VBox/log.h>
40	#include <VBox/param.h>
41	#include <VBox/err.h>
42
43
44	/*******************************************************************************
45	* Structures and Typedefs *
46	*******************************************************************************/
47	/**
48	* Stated structure for PGM_GST_NAME(HandlerVirtualUpdate) that's
49	* passed to PGM_GST_NAME(VirtHandlerUpdateOne) during enumeration.
50	*/
51	typedef struct PGMHVUSTATE
52	{
53	/** The VM handle. */
54	PVM pVM;
55	/** The todo flags. */
56	RTUINT fTodo;
57	/** The CR4 register value. */
58	uint32_t cr4;
59	} PGMHVUSTATE, *PPGMHVUSTATE;
60
61
62	/*******************************************************************************
63	* Internal Functions *
64	*******************************************************************************/
65	/** @def DUMP_PDE_BIG
66	* Debug routine for dumping a big PDE.
67	*/
68	#ifdef DEBUG_Sander
69	/** Debug routine for dumping a big PDE. */
70	static void pgmDumpPDEBig(const char *pszPrefix, int iPD, VBOXPDE Pde)
71	{
72	Log(("%s: BIG %d u10PageNo=%08X P=%d W=%d U=%d CACHE=%d ACC=%d DIR=%d GBL=%d\n", pszPrefix, iPD, Pde.b.u10PageNo, Pde.b.u1Present, Pde.b.u1Write, Pde.b.u1User, Pde.b.u1CacheDisable, Pde.b.u1Accessed, Pde.b.u1Dirty, Pde.b.u1Global));
73	Log(("%s: BIG %d WRT=%d AVAIL=%X RSV=%X PAT=%d\n", pszPrefix, iPD, Pde.b.u1WriteThru, Pde.b.u3Available, Pde.b.u8PageNoHigh, Pde.b.u1PAT));
74	}
75	#define DUMP_PDE_BIG(a, b, c) pgmDumpPDEBig(a, b, c)
76	#else
77	#define DUMP_PDE_BIG(a, b, c) do { } while (0)
78	#endif
79
80
81
82	#if 1///@todo ndef RT_ARCH_AMD64
83	/*
84	* Shadow - 32-bit mode
85	*/
86	#define PGM_SHW_TYPE PGM_TYPE_32BIT
87	#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
88	#include "PGMAllShw.h"
89
90	/* Guest - real mode */
91	#define PGM_GST_TYPE PGM_TYPE_REAL
92	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
93	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
94	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
95	#include "PGMAllGst.h"
96	#include "PGMAllBth.h"
97	#undef BTH_PGMPOOLKIND_PT_FOR_PT
98	#undef PGM_BTH_NAME
99	#undef PGM_GST_TYPE
100	#undef PGM_GST_NAME
101
102	/* Guest - protected mode */
103	#define PGM_GST_TYPE PGM_TYPE_PROT
104	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
105	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
106	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
107	#include "PGMAllGst.h"
108	#include "PGMAllBth.h"
109	#undef BTH_PGMPOOLKIND_PT_FOR_PT
110	#undef PGM_BTH_NAME
111	#undef PGM_GST_TYPE
112	#undef PGM_GST_NAME
113
114	/* Guest - 32-bit mode */
115	#define PGM_GST_TYPE PGM_TYPE_32BIT
116	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
117	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
118	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
119	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
120	#include "PGMAllGst.h"
121	#include "PGMAllBth.h"
122	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
123	#undef BTH_PGMPOOLKIND_PT_FOR_PT
124	#undef PGM_BTH_NAME
125	#undef PGM_GST_TYPE
126	#undef PGM_GST_NAME
127
128	#undef PGM_SHW_TYPE
129	#undef PGM_SHW_NAME
130	#endif /* !RT_ARCH_AMD64 */
131
132
133	/*
134	* Shadow - PAE mode
135	*/
136	#define PGM_SHW_TYPE PGM_TYPE_PAE
137	#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
138	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
139	#include "PGMAllShw.h"
140
141	/* Guest - real mode */
142	#define PGM_GST_TYPE PGM_TYPE_REAL
143	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
144	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
145	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
146	#include "PGMAllBth.h"
147	#undef BTH_PGMPOOLKIND_PT_FOR_PT
148	#undef PGM_BTH_NAME
149	#undef PGM_GST_TYPE
150	#undef PGM_GST_NAME
151
152	/* Guest - protected mode */
153	#define PGM_GST_TYPE PGM_TYPE_PROT
154	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
155	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
156	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
157	#include "PGMAllBth.h"
158	#undef BTH_PGMPOOLKIND_PT_FOR_PT
159	#undef PGM_BTH_NAME
160	#undef PGM_GST_TYPE
161	#undef PGM_GST_NAME
162
163	/* Guest - 32-bit mode */
164	#define PGM_GST_TYPE PGM_TYPE_32BIT
165	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
166	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
167	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
168	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
169	#include "PGMAllBth.h"
170	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
171	#undef BTH_PGMPOOLKIND_PT_FOR_PT
172	#undef PGM_BTH_NAME
173	#undef PGM_GST_TYPE
174	#undef PGM_GST_NAME
175
176
177	/* Guest - PAE mode */
178	#define PGM_GST_TYPE PGM_TYPE_PAE
179	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
180	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
181	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
182	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
183	#include "PGMAllGst.h"
184	#include "PGMAllBth.h"
185	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
186	#undef BTH_PGMPOOLKIND_PT_FOR_PT
187	#undef PGM_BTH_NAME
188	#undef PGM_GST_TYPE
189	#undef PGM_GST_NAME
190
191	#undef PGM_SHW_TYPE
192	#undef PGM_SHW_NAME
193
194
195	/*
196	* Shadow - AMD64 mode
197	*/
198	#define PGM_SHW_TYPE PGM_TYPE_AMD64
199	#define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
200	#include "PGMAllShw.h"
201
202	/* Guest - real mode */
203	#define PGM_GST_TYPE PGM_TYPE_REAL
204	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
205	#define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_REAL(name)
206	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
207	#include "PGMAllBth.h"
208	#undef BTH_PGMPOOLKIND_PT_FOR_PT
209	#undef PGM_BTH_NAME
210	#undef PGM_GST_NAME
211	#undef PGM_GST_TYPE
212
213	/* Guest - protected mode */
214	#define PGM_GST_TYPE PGM_TYPE_PROT
215	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
216	#define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_PROT(name)
217	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
218	#include "PGMAllBth.h"
219	#undef BTH_PGMPOOLKIND_PT_FOR_PT
220	#undef PGM_BTH_NAME
221	#undef PGM_GST_TYPE
222	#undef PGM_GST_NAME
223
224	/* Guest - AMD64 mode */
225	#define PGM_GST_TYPE PGM_TYPE_AMD64
226	#define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
227	#define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
228	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
229	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
230	#include "PGMAllGst.h"
231	#include "PGMAllBth.h"
232	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
233	#undef BTH_PGMPOOLKIND_PT_FOR_PT
234	#undef PGM_BTH_NAME
235	#undef PGM_GST_TYPE
236	#undef PGM_GST_NAME
237
238	#undef PGM_SHW_TYPE
239	#undef PGM_SHW_NAME
240
241
242
243	/**
244	* #PF Handler.
245	*
246	* @returns VBox status code (appropriate for trap handling and GC return).
247	* @param pVM VM Handle.
248	* @param uErr The trap error code.
249	* @param pRegFrame Trap register frame.
250	* @param pvFault The fault address.
251	*/
252	PGMDECL(int) PGMTrap0eHandler(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
253	{
254	LogFlow(("PGMTrap0eHandler: uErr=%#x pvFault=%VGv eip=%VGv\n", uErr, pvFault, pRegFrame->eip));
255	STAM_PROFILE_START(&pVM->pgm.s.StatGCTrap0e, a);
256	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = NULL; } );
257
258
259	#ifdef VBOX_WITH_STATISTICS
260	/*
261	* Error code stats.
262	*/
263	if (uErr & X86_TRAP_PF_US)
264	{
265	if (!(uErr & X86_TRAP_PF_P))
266	{
267	if (uErr & X86_TRAP_PF_RW)
268	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eUSNotPresentWrite);
269	else
270	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eUSNotPresentRead);
271	}
272	else if (uErr & X86_TRAP_PF_RW)
273	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eUSWrite);
274	else if (uErr & X86_TRAP_PF_RSVD)
275	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eUSReserved);
276	else
277	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eUSRead);
278	}
279	else
280	{ //supervisor
281	if (!(uErr & X86_TRAP_PF_P))
282	{
283	if (uErr & X86_TRAP_PF_RW)
284	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eSVNotPresentWrite);
285	else
286	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eSVNotPresentRead);
287	}
288	else if (uErr & X86_TRAP_PF_RW)
289	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eSVWrite);
290	else if (uErr & X86_TRAP_PF_RSVD)
291	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eSVReserved);
292	}
293	#endif
294
295	/*
296	* Call the worker.
297	*/
298	int rc = PGM_BTH_PFN(Trap0eHandler, pVM)(pVM, uErr, pRegFrame, pvFault);
299	if (rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
300	rc = VINF_SUCCESS;
301	STAM_STATS({ if (!pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution))
302	pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eMisc; });
303	STAM_PROFILE_STOP_EX(&pVM->pgm.s.StatGCTrap0e, pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution), a);
304	return rc;
305	}
306
307
308	/**
309	* Prefetch a page
310	*
311	* Typically used to sync commonly used pages before entering raw mode
312	* after a CR3 reload.
313	*
314	* @returns VBox status code suitable for scheduling.
315	* @retval VINF_SUCCESS on success.
316	* @retval VINF_PGM_SYNC_CR3 if we're out of shadow pages or something like that.
317	* @param pVM VM handle.
318	* @param GCPtrPage Page to invalidate.
319	*/
320	PGMDECL(int) PGMPrefetchPage(PVM pVM, RTGCPTR GCPtrPage)
321	{
322	STAM_PROFILE_START(&pVM->pgm.s.StatHCPrefetch, a);
323	int rc = PGM_BTH_PFN(PrefetchPage, pVM)(pVM, (RTGCUINTPTR)GCPtrPage);
324	STAM_PROFILE_STOP(&pVM->pgm.s.StatHCPrefetch, a);
325	AssertMsg(rc == VINF_SUCCESS \|\| rc == VINF_PGM_SYNC_CR3 \|\| VBOX_FAILURE(rc), ("rc=%Vrc\n", rc));
326	return rc;
327	}
328
329
330	/**
331	* Gets the mapping corresponding to the specified address (if any).
332	*
333	* @returns Pointer to the mapping.
334	* @returns NULL if not
335	*
336	* @param pVM The virtual machine.
337	* @param GCPtr The guest context pointer.
338	*/
339	PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr)
340	{
341	PPGMMAPPING pMapping = CTXALLSUFF(pVM->pgm.s.pMappings);
342	while (pMapping)
343	{
344	if ((uintptr_t)GCPtr < (uintptr_t)pMapping->GCPtr)
345	break;
346	if ((uintptr_t)GCPtr - (uintptr_t)pMapping->GCPtr < pMapping->cb)
347	{
348	STAM_COUNTER_INC(&pVM->pgm.s.StatGCSyncPTConflict);
349	return pMapping;
350	}
351	pMapping = CTXALLSUFF(pMapping->pNext);
352	}
353	return NULL;
354	}
355
356
357	/**
358	* Verifies a range of pages for read or write access
359	*
360	* Only checks the guest's page tables
361	*
362	* @returns VBox status code.
363	* @param pVM VM handle.
364	* @param Addr Guest virtual address to check
365	* @param cbSize Access size
366	* @param fAccess Access type (r/w, user/supervisor (X86_PTE_*))
367	*/
368	PGMDECL(int) PGMIsValidAccess(PVM pVM, RTGCUINTPTR Addr, uint32_t cbSize, uint32_t fAccess)
369	{
370	/*
371	* Validate input.
372	*/
373	if (fAccess & ~(X86_PTE_US \| X86_PTE_RW))
374	{
375	AssertMsgFailed(("PGMIsValidAccess: invalid access type %08x\n", fAccess));
376	return VERR_INVALID_PARAMETER;
377	}
378
379	uint64_t fPage;
380	int rc = PGMGstGetPage(pVM, (RTGCPTR)Addr, &fPage, NULL);
381	if (VBOX_FAILURE(rc))
382	{
383	Log(("PGMIsValidAccess: access violation for %VGv rc=%d\n", Addr, rc));
384	return VINF_EM_RAW_GUEST_TRAP;
385	}
386
387	/*
388	* Check if the access would cause a page fault
389	*
390	* Note that hypervisor page directories are not present in the guest's tables, so this check
391	* is sufficient.
392	*/
393	bool fWrite = !!(fAccess & X86_PTE_RW);
394	bool fUser = !!(fAccess & X86_PTE_US);
395	if ( !(fPage & X86_PTE_P)
396	\|\| (fWrite && !(fPage & X86_PTE_RW))
397	\|\| (fUser && !(fPage & X86_PTE_US)) )
398	{
399	Log(("PGMIsValidAccess: access violation for %VGv attr %#llx vs %d:%d\n", Addr, fPage, fWrite, fUser));
400	return VINF_EM_RAW_GUEST_TRAP;
401	}
402	if ( VBOX_SUCCESS(rc)
403	&& PAGE_ADDRESS(Addr) != PAGE_ADDRESS(Addr + cbSize))
404	return PGMIsValidAccess(pVM, Addr + PAGE_SIZE, (cbSize > PAGE_SIZE) ? cbSize - PAGE_SIZE : 1, fAccess);
405	return rc;
406	}
407
408
409	/**
410	* Verifies a range of pages for read or write access
411	*
412	* Supports handling of pages marked for dirty bit tracking and CSAM
413	*
414	* @returns VBox status code.
415	* @param pVM VM handle.
416	* @param Addr Guest virtual address to check
417	* @param cbSize Access size
418	* @param fAccess Access type (r/w, user/supervisor (X86_PTE_*))
419	*/
420	PGMDECL(int) PGMVerifyAccess(PVM pVM, RTGCUINTPTR Addr, uint32_t cbSize, uint32_t fAccess)
421	{
422	/*
423	* Validate input.
424	*/
425	if (fAccess & ~(X86_PTE_US \| X86_PTE_RW))
426	{
427	AssertMsgFailed(("PGMVerifyAccess: invalid access type %08x\n", fAccess));
428	return VERR_INVALID_PARAMETER;
429	}
430
431	uint64_t fPageGst;
432	int rc = PGMGstGetPage(pVM, (RTGCPTR)Addr, &fPageGst, NULL);
433	if (VBOX_FAILURE(rc))
434	{
435	Log(("PGMVerifyAccess: access violation for %VGv rc=%d\n", Addr, rc));
436	return VINF_EM_RAW_GUEST_TRAP;
437	}
438
439	/*
440	* Check if the access would cause a page fault
441	*
442	* Note that hypervisor page directories are not present in the guest's tables, so this check
443	* is sufficient.
444	*/
445	const bool fWrite = !!(fAccess & X86_PTE_RW);
446	const bool fUser = !!(fAccess & X86_PTE_US);
447	if ( !(fPageGst & X86_PTE_P)
448	\|\| (fWrite && !(fPageGst & X86_PTE_RW))
449	\|\| (fUser && !(fPageGst & X86_PTE_US)) )
450	{
451	Log(("PGMVerifyAccess: access violation for %VGv attr %#llx vs %d:%d\n", Addr, fPageGst, fWrite, fUser));
452	return VINF_EM_RAW_GUEST_TRAP;
453	}
454
455	/*
456	* Next step is to verify if we protected this page for dirty bit tracking or for CSAM scanning
457	*/
458	rc = PGMShwGetPage(pVM, (RTGCPTR)Addr, NULL, NULL);
459	if ( rc == VERR_PAGE_NOT_PRESENT
460	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT)
461	{
462	/*
463	* Page is not present in our page tables.
464	* Try to sync it!
465	*/
466	Assert(X86_TRAP_PF_RW == X86_PTE_RW && X86_TRAP_PF_US == X86_PTE_US);
467	uint32_t uErr = fAccess & (X86_TRAP_PF_RW \| X86_TRAP_PF_US);
468	rc = PGM_BTH_PFN(VerifyAccessSyncPage, pVM)(pVM, Addr, fPageGst, uErr);
469	if (rc != VINF_SUCCESS)
470	return rc;
471	}
472	else
473	AssertMsg(rc == VINF_SUCCESS, ("PGMShwGetPage %VGv failed with %Vrc\n", Addr, rc));
474
475	#if 0 /* def VBOX_STRICT; triggers too often now */
476	/*
477	* This check is a bit paranoid, but useful.
478	*/
479	/** @note this will assert when writing to monitored pages (a bit annoying actually) */
480	uint64_t fPageShw;
481	rc = PGMShwGetPage(pVM, (RTGCPTR)Addr, &fPageShw, NULL);
482	if ( (rc == VERR_PAGE_NOT_PRESENT \|\| VBOX_FAILURE(rc))
483	\|\| (fWrite && !(fPageShw & X86_PTE_RW))
484	\|\| (fUser && !(fPageShw & X86_PTE_US)) )
485	{
486	AssertMsgFailed(("Unexpected access violation for %VGv! rc=%Vrc write=%d user=%d\n",
487	Addr, rc, fWrite && !(fPageShw & X86_PTE_RW), fUser && !(fPageShw & X86_PTE_US)));
488	return VINF_EM_RAW_GUEST_TRAP;
489	}
490	#endif
491
492	if ( VBOX_SUCCESS(rc)
493	&& ( PAGE_ADDRESS(Addr) != PAGE_ADDRESS(Addr + cbSize - 1)
494	\|\| Addr + cbSize < Addr))
495	{
496	/* Don't recursively call PGMVerifyAccess as we might run out of stack. */
497	for (;;)
498	{
499	Addr += PAGE_SIZE;
500	if (cbSize > PAGE_SIZE)
501	cbSize -= PAGE_SIZE;
502	else
503	cbSize = 1;
504	rc = PGMVerifyAccess(pVM, Addr, 1, fAccess);
505	if (rc != VINF_SUCCESS)
506	break;
507	if (PAGE_ADDRESS(Addr) == PAGE_ADDRESS(Addr + cbSize - 1))
508	break;
509	}
510	}
511	return rc;
512	}
513
514
515	#ifndef IN_GC
516	/**
517	* Emulation of the invlpg instruction (HC only actually).
518	*
519	* @returns VBox status code.
520	* @param pVM VM handle.
521	* @param GCPtrPage Page to invalidate.
522	* @remark ASSUMES the page table entry or page directory is
523	* valid. Fairly safe, but there could be edge cases!
524	* @todo Flush page or page directory only if necessary!
525	*/
526	PGMDECL(int) PGMInvalidatePage(PVM pVM, RTGCPTR GCPtrPage)
527	{
528	int rc;
529
530	LogFlow(("PGMInvalidatePage: GCPtrPage=%VGv\n", GCPtrPage));
531
532	/** @todo merge PGMGCInvalidatePage with this one */
533
534	#ifndef IN_RING3
535	/*
536	* Notify the recompiler so it can record this instruction.
537	* Failure happens when it's out of space. We'll return to HC in that case.
538	*/
539	rc = REMNotifyInvalidatePage(pVM, GCPtrPage);
540	if (VBOX_FAILURE(rc))
541	return rc;
542	#endif
543
544	STAM_PROFILE_START(&CTXMID(pVM->pgm.s.Stat,InvalidatePage), a);
545	rc = PGM_BTH_PFN(InvalidatePage, pVM)(pVM, GCPtrPage);
546	STAM_PROFILE_STOP(&CTXMID(pVM->pgm.s.Stat,InvalidatePage), a);
547
548	#ifndef IN_RING0
549	/*
550	* Check if we have a pending update of the CR3 monitoring.
551	*/
552	if ( VBOX_SUCCESS(rc)
553	&& (pVM->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3))
554	{
555	pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
556	Assert(!pVM->pgm.s.fMappingsFixed);
557	Assert(pVM->pgm.s.GCPhysCR3 == pVM->pgm.s.GCPhysGstCR3Monitored);
558	rc = PGM_GST_PFN(MonitorCR3, pVM)(pVM, pVM->pgm.s.GCPhysCR3);
559	}
560	#endif
561
562	#ifdef IN_RING3
563	/*
564	* Inform CSAM about the flush
565	*/
566	/** @note this is to check if monitored pages have been changed; when we implement callbacks for virtual handlers, this is no longer required. */
567	CSAMR3FlushPage(pVM, GCPtrPage);
568	#endif
569	return rc;
570	}
571	#endif
572
573
574	/**
575	* Executes an instruction using the interpreter.
576	*
577	* @returns VBox status code (appropriate for trap handling and GC return).
578	* @param pVM VM handle.
579	* @param pRegFrame Register frame.
580	* @param pvFault Fault address.
581	*/
582	PGMDECL(int) PGMInterpretInstruction(PVM pVM, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
583	{
584	#ifdef IN_RING0
585	/** @todo */
586	int rc = VINF_EM_RAW_EMULATE_INSTR;
587	#else
588	uint32_t cb;
589	int rc = EMInterpretInstruction(pVM, pRegFrame, pvFault, &cb);
590	if (rc == VERR_EM_INTERPRETER)
591	rc = VINF_EM_RAW_EMULATE_INSTR;
592	if (rc != VINF_SUCCESS)
593	Log(("PGMInterpretInstruction: returns %Rrc (pvFault=%VGv)\n", rc, pvFault));
594	#endif
595	return rc;
596	}
597
598
599	/**
600	* Gets effective page information (from the VMM page directory).
601	*
602	* @returns VBox status.
603	* @param pVM VM Handle.
604	* @param GCPtr Guest Context virtual address of the page.
605	* @param pfFlags Where to store the flags. These are X86_PTE_*.
606	* @param pHCPhys Where to store the HC physical address of the page.
607	* This is page aligned.
608	* @remark You should use PGMMapGetPage() for pages in a mapping.
609	*/
610	PGMDECL(int) PGMShwGetPage(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys)
611	{
612	return PGM_SHW_PFN(GetPage,pVM)(pVM, (RTGCUINTPTR)GCPtr, pfFlags, pHCPhys);
613	}
614
615
616	/**
617	* Sets (replaces) the page flags for a range of pages in the shadow context.
618	*
619	* @returns VBox status.
620	* @param pVM VM handle.
621	* @param GCPtr The address of the first page.
622	* @param cb The size of the range in bytes.
623	* @param fFlags Page flags X86_PTE_*, excluding the page mask of course.
624	* @remark You must use PGMMapSetPage() for pages in a mapping.
625	*/
626	PGMDECL(int) PGMShwSetPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags)
627	{
628	return PGMShwModifyPage(pVM, GCPtr, cb, fFlags, 0);
629	}
630
631
632	/**
633	* Modify page flags for a range of pages in the shadow context.
634	*
635	* The existing flags are ANDed with the fMask and ORed with the fFlags.
636	*
637	* @returns VBox status code.
638	* @param pVM VM handle.
639	* @param GCPtr Virtual address of the first page in the range.
640	* @param cb Size (in bytes) of the range to apply the modification to.
641	* @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
642	* @param fMask The AND mask - page flags X86_PTE_*.
643	* Be very CAREFUL when ~'ing constants which could be 32-bit!
644	* @remark You must use PGMMapModifyPage() for pages in a mapping.
645	*/
646	PGMDECL(int) PGMShwModifyPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
647	{
648	/*
649	* Validate input.
650	*/
651	if (fFlags & X86_PTE_PAE_PG_MASK)
652	{
653	AssertMsgFailed(("fFlags=%#llx\n", fFlags));
654	return VERR_INVALID_PARAMETER;
655	}
656	if (!cb)
657	{
658	AssertFailed();
659	return VERR_INVALID_PARAMETER;
660	}
661
662	/*
663	* Align the input.
664	*/
665	cb += (RTGCUINTPTR)GCPtr & PAGE_OFFSET_MASK;
666	cb = RT_ALIGN_Z(cb, PAGE_SIZE);
667	GCPtr = (RTGCPTR)((RTGCUINTPTR)GCPtr & PAGE_BASE_GC_MASK); /** @todo this ain't necessary, right... */
668
669	/*
670	* Call worker.
671	*/
672	return PGM_SHW_PFN(ModifyPage, pVM)(pVM, (RTGCUINTPTR)GCPtr, cb, fFlags, fMask);
673	}
674
675
676	/**
677	* Gets effective Guest OS page information.
678	*
679	* When GCPtr is in a big page, the function will return as if it was a normal
680	* 4KB page. If the need for distinguishing between big and normal page becomes
681	* necessary at a later point, a PGMGstGetPage() will be created for that
682	* purpose.
683	*
684	* @returns VBox status.
685	* @param pVM VM Handle.
686	* @param GCPtr Guest Context virtual address of the page.
687	* @param pfFlags Where to store the flags. These are X86_PTE_*, even for big pages.
688	* @param pGCPhys Where to store the GC physical address of the page.
689	* This is page aligned. The fact that the
690	*/
691	PGMDECL(int) PGMGstGetPage(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys)
692	{
693	return PGM_GST_PFN(GetPage,pVM)(pVM, (RTGCUINTPTR)GCPtr, pfFlags, pGCPhys);
694	}
695
696
697	/**
698	* Checks if the page is present.
699	*
700	* @returns true if the page is present.
701	* @returns false if the page is not present.
702	* @param pVM The VM handle.
703	* @param GCPtr Address within the page.
704	*/
705	PGMDECL(bool) PGMGstIsPagePresent(PVM pVM, RTGCPTR GCPtr)
706	{
707	int rc = PGMGstGetPage(pVM, GCPtr, NULL, NULL);
708	return VBOX_SUCCESS(rc);
709	}
710
711
712	/**
713	* Sets (replaces) the page flags for a range of pages in the guest's tables.
714	*
715	* @returns VBox status.
716	* @param pVM VM handle.
717	* @param GCPtr The address of the first page.
718	* @param cb The size of the range in bytes.
719	* @param fFlags Page flags X86_PTE_*, excluding the page mask of course.
720	*/
721	PGMDECL(int) PGMGstSetPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags)
722	{
723	return PGMGstModifyPage(pVM, GCPtr, cb, fFlags, 0);
724	}
725
726
727	/**
728	* Modify page flags for a range of pages in the guest's tables
729	*
730	* The existing flags are ANDed with the fMask and ORed with the fFlags.
731	*
732	* @returns VBox status code.
733	* @param pVM VM handle.
734	* @param GCPtr Virtual address of the first page in the range.
735	* @param cb Size (in bytes) of the range to apply the modification to.
736	* @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
737	* @param fMask The AND mask - page flags X86_PTE_*, excluding the page mask of course.
738	* Be very CAREFUL when ~'ing constants which could be 32-bit!
739	*/
740	PGMDECL(int) PGMGstModifyPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
741	{
742	STAM_PROFILE_START(&CTXMID(pVM->pgm.s.Stat,GstModifyPage), a);
743
744	/*
745	* Validate input.
746	*/
747	if (fFlags & X86_PTE_PAE_PG_MASK)
748	{
749	AssertMsgFailed(("fFlags=%#llx\n", fFlags));
750	STAM_PROFILE_STOP(&CTXMID(pVM->pgm.s.Stat,GstModifyPage), a);
751	return VERR_INVALID_PARAMETER;
752	}
753
754	if (!cb)
755	{
756	AssertFailed();
757	STAM_PROFILE_STOP(&CTXMID(pVM->pgm.s.Stat,GstModifyPage), a);
758	return VERR_INVALID_PARAMETER;
759	}
760
761	LogFlow(("PGMGstModifyPage %VGv %d bytes fFlags=%08llx fMask=%08llx\n", GCPtr, cb, fFlags, fMask));
762
763	/*
764	* Adjust input.
765	*/
766	cb += (RTGCUINTPTR)GCPtr & PAGE_OFFSET_MASK;
767	cb = RT_ALIGN_Z(cb, PAGE_SIZE);
768	GCPtr = (RTGCPTR)((RTGCUINTPTR)GCPtr & PAGE_BASE_GC_MASK);
769
770	/*
771	* Call worker.
772	*/
773	int rc = PGM_GST_PFN(ModifyPage, pVM)(pVM, (RTGCUINTPTR)GCPtr, cb, fFlags, fMask);
774
775	STAM_PROFILE_STOP(&CTXMID(pVM->pgm.s.Stat,GstModifyPage), a);
776	return rc;
777	}
778
779
780	/**
781	* Temporarily turns off the access monitoring of a page within a monitored
782	* physical write/all page access handler region.
783	*
784	* Use this when no further \#PFs are required for that page. Be aware that
785	* a page directory sync might reset the flags, and turn on access monitoring
786	* for the page.
787	*
788	* The caller must do required page table modifications.
789	*
790	* @returns VBox status code.
791	* @param pVM VM Handle
792	* @param GCPhys Start physical address earlier passed to PGMR3HandlerPhysicalRegister().
793	* This must be a fully page aligned range or we risk messing up other
794	* handlers installed for the start and end pages.
795	* @param GCPhysPage Physical address of the page to turn off access monitoring for.
796	* @todo move to PGMAllHandler.cpp
797	*/
798	PGMDECL(int) PGMHandlerPhysicalPageTempOff(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage)
799	{
800	/*
801	* Validate the range.
802	*/
803	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)RTAvlroGCPhysGet(&pVM->pgm.s.CTXSUFF(pTrees)->PhysHandlers, GCPhys);
804	if (pCur)
805	{
806	if ( GCPhysPage >= pCur->Core.Key
807	&& GCPhysPage <= pCur->Core.KeyLast)
808	{
809	Assert(!(pCur->Core.Key & PAGE_OFFSET_MASK));
810	Assert((pCur->Core.KeyLast & PAGE_OFFSET_MASK) == PAGE_OFFSET_MASK);
811
812	AssertReturn( pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
813	\|\| pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_ALL,
814	VERR_ACCESS_DENIED);
815
816	/*
817	* Change the page status.
818	*/
819	PPGMPAGE pPage;
820	int rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhysPage, &pPage);
821	AssertRCReturn(rc, rc);
822	PGM_PAGE_SET_HNDL_PHYS_STATE(pPage, PGM_PAGE_HNDL_PHYS_STATE_DISABLED);
823	return VINF_SUCCESS;
824	}
825
826	AssertMsgFailed(("The page %#x is outside the range %#x-%#x\n",
827	GCPhysPage, pCur->Core.Key, pCur->Core.KeyLast));
828	return VERR_INVALID_PARAMETER;
829	}
830
831	AssertMsgFailed(("Specified physical handler start address %#x is invalid.\n", GCPhys));
832	return VERR_PGM_HANDLER_NOT_FOUND;
833	}
834
835
836	/**
837	* Turns access monitoring of a page within a monitored
838	* physical write/all page access handler regio back on.
839	*
840	* The caller must do required page table modifications.
841	*
842	* @returns VBox status code.
843	* @param pVM VM Handle
844	* @param GCPhys Start physical address earlier passed to PGMR3HandlerPhysicalRegister().
845	* This must be a fully page aligned range or we risk messing up other
846	* handlers installed for the start and end pages.
847	* @param GCPhysPage Physical address of the page to turn on access monitoring for.
848	* @todo move to PGMAllHandler.cpp
849	*/
850	PGMDECL(int) PGMHandlerPhysicalPageReset(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage)
851	{
852	/*
853	* Validate the range.
854	*/
855	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)RTAvlroGCPhysGet(&pVM->pgm.s.CTXSUFF(pTrees)->PhysHandlers, GCPhys);
856	if (pCur)
857	{
858	if ( GCPhysPage >= pCur->Core.Key
859	&& GCPhysPage <= pCur->Core.KeyLast)
860	{
861	Assert(!(pCur->Core.Key & PAGE_OFFSET_MASK));
862	Assert((pCur->Core.KeyLast & PAGE_OFFSET_MASK) == PAGE_OFFSET_MASK);
863
864	AssertReturn( pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
865	\|\| pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_ALL,
866	VERR_ACCESS_DENIED);
867
868	/*
869	* Change the page status.
870	*/
871	PPGMPAGE pPage;
872	int rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhysPage, &pPage);
873	AssertRCReturn(rc, rc);
874	PGM_PAGE_SET_HNDL_PHYS_STATE(pPage, pgmHandlerPhysicalCalcState(pCur));
875	return VINF_SUCCESS;
876	}
877
878	AssertMsgFailed(("The page %#x is outside the range %#x-%#x\n",
879	GCPhysPage, pCur->Core.Key, pCur->Core.KeyLast));
880	return VERR_INVALID_PARAMETER;
881	}
882
883	AssertMsgFailed(("Specified physical handler start address %#x is invalid.\n", GCPhys));
884	return VERR_PGM_HANDLER_NOT_FOUND;
885	}
886
887
888	/**
889	* Checks if a physical range is handled
890	*
891	* @returns boolean
892	* @param pVM VM Handle
893	* @param GCPhys Start physical address earlier passed to PGMR3HandlerPhysicalRegister().
894	* @todo move to PGMAllHandler.cpp
895	*/
896	PGMDECL(bool) PGMHandlerPhysicalIsRegistered(PVM pVM, RTGCPHYS GCPhys)
897	{
898	/*
899	* Find the handler.
900	*/
901	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)RTAvlroGCPhysRangeGet(&pVM->pgm.s.CTXSUFF(pTrees)->PhysHandlers, GCPhys);
902	if (pCur)
903	{
904	if ( GCPhys >= pCur->Core.Key
905	&& GCPhys <= pCur->Core.KeyLast)
906	{
907	Assert( pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
908	\|\| pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_ALL
909	\|\| pCur->enmType == PGMPHYSHANDLERTYPE_MMIO);
910	return true;
911	}
912	}
913
914	return false;
915	}
916
917
918	#ifdef VBOX_STRICT
919	DECLCALLBACK(int) pgmVirtHandlerDumpPhysRange(PAVLROGCPHYSNODECORE pNode, void *pvUser)
920	{
921	PPGMPHYS2VIRTHANDLER pCur = (PPGMPHYS2VIRTHANDLER)pNode;
922	PPGMVIRTHANDLER pVirt = (PPGMVIRTHANDLER)((uintptr_t)pCur + pCur->offVirtHandler);
923	Log(("PHYS2VIRT: Range %VGp-%VGp for virtual handler: %s\n", pCur->Core.Key, pCur->Core.KeyLast, pVirt->pszDesc));
924	return 0;
925	}
926
927
928	void pgmHandlerVirtualDumpPhysPages(PVM pVM)
929	{
930	RTAvlroGCPhysDoWithAll(CTXSUFF(&pVM->pgm.s.pTrees)->PhysToVirtHandlers, true, pgmVirtHandlerDumpPhysRange, 0);
931	}
932	#endif /* VBOX_STRICT */
933
934
935	/**
936	* Gets the current CR3 register value for the shadow memory context.
937	* @returns CR3 value.
938	* @param pVM The VM handle.
939	*/
940	PGMDECL(uint32_t) PGMGetHyperCR3(PVM pVM)
941	{
942	switch (pVM->pgm.s.enmShadowMode)
943	{
944	case PGMMODE_32_BIT:
945	return pVM->pgm.s.HCPhys32BitPD;
946
947	case PGMMODE_PAE:
948	case PGMMODE_PAE_NX:
949	return pVM->pgm.s.HCPhysPaePDPTR;
950
951	case PGMMODE_AMD64:
952	case PGMMODE_AMD64_NX:
953	return pVM->pgm.s.HCPhysPaePML4;
954
955	default:
956	AssertMsgFailed(("enmShadowMode=%d\n", pVM->pgm.s.enmShadowMode));
957	return ~0;
958	}
959	}
960
961
962	/**
963	* Gets the CR3 register value for the 32-Bit shadow memory context.
964	* @returns CR3 value.
965	* @param pVM The VM handle.
966	*/
967	PGMDECL(uint32_t) PGMGetHyper32BitCR3(PVM pVM)
968	{
969	return pVM->pgm.s.HCPhys32BitPD;
970	}
971
972
973	/**
974	* Gets the CR3 register value for the PAE shadow memory context.
975	* @returns CR3 value.
976	* @param pVM The VM handle.
977	*/
978	PGMDECL(uint32_t) PGMGetHyperPaeCR3(PVM pVM)
979	{
980	return pVM->pgm.s.HCPhysPaePDPTR;
981	}
982
983
984	/**
985	* Gets the CR3 register value for the AMD64 shadow memory context.
986	* @returns CR3 value.
987	* @param pVM The VM handle.
988	*/
989	PGMDECL(uint32_t) PGMGetHyperAmd64CR3(PVM pVM)
990	{
991	return pVM->pgm.s.HCPhysPaePML4;
992	}
993
994
995	/**
996	* Gets the current CR3 register value for the HC intermediate memory context.
997	* @returns CR3 value.
998	* @param pVM The VM handle.
999	*/
1000	PGMDECL(uint32_t) PGMGetInterHCCR3(PVM pVM)
1001	{
1002	switch (pVM->pgm.s.enmHostMode)
1003	{
1004	case SUPPAGINGMODE_32_BIT:
1005	case SUPPAGINGMODE_32_BIT_GLOBAL:
1006	return pVM->pgm.s.HCPhysInterPD;
1007
1008	case SUPPAGINGMODE_PAE:
1009	case SUPPAGINGMODE_PAE_GLOBAL:
1010	case SUPPAGINGMODE_PAE_NX:
1011	case SUPPAGINGMODE_PAE_GLOBAL_NX:
1012	return pVM->pgm.s.HCPhysInterPaePDPTR;
1013
1014	case SUPPAGINGMODE_AMD64:
1015	case SUPPAGINGMODE_AMD64_GLOBAL:
1016	case SUPPAGINGMODE_AMD64_NX:
1017	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1018	return pVM->pgm.s.HCPhysInterPaePDPTR;
1019
1020	default:
1021	AssertMsgFailed(("enmHostMode=%d\n", pVM->pgm.s.enmHostMode));
1022	return ~0;
1023	}
1024	}
1025
1026
1027	/**
1028	* Gets the current CR3 register value for the GC intermediate memory context.
1029	* @returns CR3 value.
1030	* @param pVM The VM handle.
1031	*/
1032	PGMDECL(uint32_t) PGMGetInterGCCR3(PVM pVM)
1033	{
1034	switch (pVM->pgm.s.enmShadowMode)
1035	{
1036	case PGMMODE_32_BIT:
1037	return pVM->pgm.s.HCPhysInterPD;
1038
1039	case PGMMODE_PAE:
1040	case PGMMODE_PAE_NX:
1041	return pVM->pgm.s.HCPhysInterPaePDPTR;
1042
1043	case PGMMODE_AMD64:
1044	case PGMMODE_AMD64_NX:
1045	return pVM->pgm.s.HCPhysInterPaePML4;
1046
1047	default:
1048	AssertMsgFailed(("enmShadowMode=%d\n", pVM->pgm.s.enmShadowMode));
1049	return ~0;
1050	}
1051	}
1052
1053
1054	/**
1055	* Gets the CR3 register value for the 32-Bit intermediate memory context.
1056	* @returns CR3 value.
1057	* @param pVM The VM handle.
1058	*/
1059	PGMDECL(uint32_t) PGMGetInter32BitCR3(PVM pVM)
1060	{
1061	return pVM->pgm.s.HCPhysInterPD;
1062	}
1063
1064
1065	/**
1066	* Gets the CR3 register value for the PAE intermediate memory context.
1067	* @returns CR3 value.
1068	* @param pVM The VM handle.
1069	*/
1070	PGMDECL(uint32_t) PGMGetInterPaeCR3(PVM pVM)
1071	{
1072	return pVM->pgm.s.HCPhysInterPaePDPTR;
1073	}
1074
1075
1076	/**
1077	* Gets the CR3 register value for the AMD64 intermediate memory context.
1078	* @returns CR3 value.
1079	* @param pVM The VM handle.
1080	*/
1081	PGMDECL(uint32_t) PGMGetInterAmd64CR3(PVM pVM)
1082	{
1083	return pVM->pgm.s.HCPhysInterPaePML4;
1084	}
1085
1086
1087	/**
1088	* Performs and schedules necessary updates following a CR3 load or reload.
1089	*
1090	* This will normally involve mapping the guest PD or nPDPTR
1091	*
1092	* @returns VBox status code.
1093	* @retval VINF_PGM_SYNC_CR3 if monitoring requires a CR3 sync. This can
1094	* safely be ignored and overridden since the FF will be set too then.
1095	* @param pVM VM handle.
1096	* @param cr3 The new cr3.
1097	* @param fGlobal Indicates whether this is a global flush or not.
1098	*/
1099	PGMDECL(int) PGMFlushTLB(PVM pVM, uint32_t cr3, bool fGlobal)
1100	{
1101	/*
1102	* Always flag the necessary updates; necessary for hardware acceleration
1103	*/
1104	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
1105	if (fGlobal)
1106	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
1107
1108	/*
1109	* When in real or protected mode there is no TLB flushing, but
1110	* we may still be called because of REM not caring/knowing this.
1111	* REM is simple and we wish to keep it that way.
1112	*/
1113	if (pVM->pgm.s.enmGuestMode <= PGMMODE_PROTECTED)
1114	return VINF_SUCCESS;
1115	LogFlow(("PGMFlushTLB: cr3=%#x OldCr3=%#x fGlobal=%d\n", cr3, pVM->pgm.s.GCPhysCR3, fGlobal));
1116	STAM_PROFILE_START(&pVM->pgm.s.StatFlushTLB, a);
1117
1118	/*
1119	* Remap the CR3 content and adjust the monitoring if CR3 was actually changed.
1120	*/
1121	int rc = VINF_SUCCESS;
1122	RTGCPHYS GCPhysCR3;
1123	if ( pVM->pgm.s.enmGuestMode == PGMMODE_PAE
1124	\|\| pVM->pgm.s.enmGuestMode == PGMMODE_PAE_NX
1125	\|\| pVM->pgm.s.enmGuestMode == PGMMODE_AMD64
1126	\|\| pVM->pgm.s.enmGuestMode == PGMMODE_AMD64_NX)
1127	GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAE_PAGE_MASK);
1128	else
1129	GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAGE_MASK);
1130	if (pVM->pgm.s.GCPhysCR3 != GCPhysCR3)
1131	{
1132	pVM->pgm.s.GCPhysCR3 = GCPhysCR3;
1133	rc = PGM_GST_PFN(MapCR3, pVM)(pVM, GCPhysCR3);
1134	if (VBOX_SUCCESS(rc) && !pVM->pgm.s.fMappingsFixed)
1135	{
1136	pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
1137	rc = PGM_GST_PFN(MonitorCR3, pVM)(pVM, GCPhysCR3);
1138	}
1139	if (fGlobal)
1140	STAM_COUNTER_INC(&pVM->pgm.s.StatFlushTLBNewCR3Global);
1141	else
1142	STAM_COUNTER_INC(&pVM->pgm.s.StatFlushTLBNewCR3);
1143	}
1144	else
1145	{
1146	/*
1147	* Check if we have a pending update of the CR3 monitoring.
1148	*/
1149	if (pVM->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
1150	{
1151	pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
1152	Assert(!pVM->pgm.s.fMappingsFixed);
1153	rc = PGM_GST_PFN(MonitorCR3, pVM)(pVM, GCPhysCR3);
1154	}
1155	if (fGlobal)
1156	STAM_COUNTER_INC(&pVM->pgm.s.StatFlushTLBSameCR3Global);
1157	else
1158	STAM_COUNTER_INC(&pVM->pgm.s.StatFlushTLBSameCR3);
1159	}
1160
1161	STAM_PROFILE_STOP(&pVM->pgm.s.StatFlushTLB, a);
1162	return rc;
1163	}
1164
1165
1166	/**
1167	* Synchronize the paging structures.
1168	*
1169	* This function is called in response to the VM_FF_PGM_SYNC_CR3 and
1170	* VM_FF_PGM_SYNC_CR3_NONGLOBAL. Those two force action flags are set
1171	* in several places, most importantly whenever the CR3 is loaded.
1172	*
1173	* @returns VBox status code.
1174	* @param pVM The virtual machine.
1175	* @param cr0 Guest context CR0 register
1176	* @param cr3 Guest context CR3 register
1177	* @param cr4 Guest context CR4 register
1178	* @param fGlobal Including global page directories or not
1179	*/
1180	PGMDECL(int) PGMSyncCR3(PVM pVM, uint32_t cr0, uint32_t cr3, uint32_t cr4, bool fGlobal)
1181	{
1182	/*
1183	* We might be called when we shouldn't.
1184	*
1185	* The mode switching will ensure that the PD is resynced
1186	* after every mode switch. So, if we find ourselves here
1187	* when in protected or real mode we can safely disable the
1188	* FF and return immediately.
1189	*/
1190	if (pVM->pgm.s.enmGuestMode <= PGMMODE_PROTECTED)
1191	{
1192	Assert((cr0 & (X86_CR0_PG \| X86_CR0_PE)) != (X86_CR0_PG \| X86_CR0_PE));
1193	VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3);
1194	VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
1195	return VINF_SUCCESS;
1196	}
1197
1198	/* If global pages are not supported, then all flushes are global */
1199	if (!(cr4 & X86_CR4_PGE))
1200	fGlobal = true;
1201	LogFlow(("PGMSyncCR3: cr0=%08x cr3=%08x cr4=%08x fGlobal=%d[%d,%d]\n", cr0, cr3, cr4, fGlobal,
1202	VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3), VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL)));
1203
1204	/*
1205	* Let the 'Bth' function do the work and we'll just keep track of the flags.
1206	*/
1207	STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat,SyncCR3), a);
1208	int rc = PGM_BTH_PFN(SyncCR3, pVM)(pVM, cr0, cr3, cr4, fGlobal);
1209	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncCR3), a);
1210	AssertMsg(rc == VINF_SUCCESS \|\| rc == VINF_PGM_SYNC_CR3 \|\| VBOX_FAILURE(rc), ("rc=%VRc\n", rc));
1211	if (rc == VINF_SUCCESS)
1212	{
1213	if (!(pVM->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS))
1214	{
1215	VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3);
1216	VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
1217	}
1218
1219	/*
1220	* Check if we have a pending update of the CR3 monitoring.
1221	*/
1222	if (pVM->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
1223	{
1224	pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
1225	Assert(!pVM->pgm.s.fMappingsFixed);
1226	Assert(pVM->pgm.s.GCPhysCR3 == pVM->pgm.s.GCPhysGstCR3Monitored);
1227	rc = PGM_GST_PFN(MonitorCR3, pVM)(pVM, pVM->pgm.s.GCPhysCR3);
1228	}
1229	}
1230
1231	/*
1232	* Now flush the CR3 (guest context).
1233	*/
1234	if (rc == VINF_SUCCESS)
1235	PGM_INVL_GUEST_TLBS();
1236	return rc;
1237	}
1238
1239
1240	/**
1241	* Called whenever CR0 or CR4 in a way which may change
1242	* the paging mode.
1243	*
1244	* @returns VBox status code fit for scheduling in GC and R0.
1245	* @retval VINF_SUCCESS if the was no change, or it was successfully dealt with.
1246	* @retval VINF_PGM_CHANGE_MODE if we're in GC or R0 and the mode changes.
1247	* @param pVM VM handle.
1248	* @param cr0 The new cr0.
1249	* @param cr4 The new cr4.
1250	* @param efer The new extended feature enable register.
1251	*/
1252	PGMDECL(int) PGMChangeMode(PVM pVM, uint32_t cr0, uint32_t cr4, uint64_t efer)
1253	{
1254	PGMMODE enmGuestMode;
1255
1256	/*
1257	* Calc the new guest mode.
1258	*/
1259	if (!(cr0 & X86_CR0_PE))
1260	enmGuestMode = PGMMODE_REAL;
1261	else if (!(cr0 & X86_CR0_PG))
1262	enmGuestMode = PGMMODE_PROTECTED;
1263	else if (!(cr4 & X86_CR4_PAE))
1264	enmGuestMode = PGMMODE_32_BIT;
1265	else if (!(efer & MSR_K6_EFER_LME))
1266	{
1267	if (!(efer & MSR_K6_EFER_NXE))
1268	enmGuestMode = PGMMODE_PAE;
1269	else
1270	enmGuestMode = PGMMODE_PAE_NX;
1271	}
1272	else
1273	{
1274	if (!(efer & MSR_K6_EFER_NXE))
1275	enmGuestMode = PGMMODE_AMD64;
1276	else
1277	enmGuestMode = PGMMODE_AMD64_NX;
1278	}
1279
1280	/*
1281	* Did it change?
1282	*/
1283	if (pVM->pgm.s.enmGuestMode == enmGuestMode)
1284	return VINF_SUCCESS;
1285	#ifdef IN_RING3
1286	return pgmR3ChangeMode(pVM, enmGuestMode);
1287	#else
1288	Log(("PGMChangeMode: returns VINF_PGM_CHANGE_MODE.\n"));
1289	return VINF_PGM_CHANGE_MODE;
1290	#endif
1291	}
1292
1293
1294	/**
1295	* Gets the current guest paging mode.
1296	*
1297	* If you just need the CPU mode (real/protected/long), use CPUMGetGuestMode().
1298	*
1299	* @returns The current paging mode.
1300	* @param pVM The VM handle.
1301	*/
1302	PGMDECL(PGMMODE) PGMGetGuestMode(PVM pVM)
1303	{
1304	return pVM->pgm.s.enmGuestMode;
1305	}
1306
1307
1308	/**
1309	* Gets the current shadow paging mode.
1310	*
1311	* @returns The current paging mode.
1312	* @param pVM The VM handle.
1313	*/
1314	PGMDECL(PGMMODE) PGMGetShadowMode(PVM pVM)
1315	{
1316	return pVM->pgm.s.enmShadowMode;
1317	}
1318
1319
1320	/**
1321	* Get mode name.
1322	*
1323	* @returns read-only name string.
1324	* @param enmMode The mode which name is desired.
1325	*/
1326	PGMDECL(const char *) PGMGetModeName(PGMMODE enmMode)
1327	{
1328	switch (enmMode)
1329	{
1330	case PGMMODE_REAL: return "real";
1331	case PGMMODE_PROTECTED: return "protected";
1332	case PGMMODE_32_BIT: return "32-bit";
1333	case PGMMODE_PAE: return "PAE";
1334	case PGMMODE_PAE_NX: return "PAE+NX";
1335	case PGMMODE_AMD64: return "AMD64";
1336	case PGMMODE_AMD64_NX: return "AMD64+NX";
1337	default: return "unknown mode value";
1338	}
1339	}
1340
1341
1342	/**
1343	* Acquire the PGM lock.
1344	*
1345	* @returns VBox status code
1346	* @param pVM The VM to operate on.
1347	*/
1348	int pgmLock(PVM pVM)
1349	{
1350	int rc = PDMCritSectEnter(&pVM->pgm.s.CritSect, VERR_SEM_BUSY);
1351	#ifdef IN_GC
1352	if (rc == VERR_SEM_BUSY)
1353	rc = VMMGCCallHost(pVM, VMMCALLHOST_PGM_LOCK, 0);
1354	#elif defined(IN_RING0)
1355	if (rc == VERR_SEM_BUSY)
1356	rc = VMMR0CallHost(pVM, VMMCALLHOST_PGM_LOCK, 0);
1357	#endif
1358	AssertRC(rc);
1359	return rc;
1360	}
1361
1362
1363	/**
1364	* Release the PGM lock.
1365	*
1366	* @returns VBox status code
1367	* @param pVM The VM to operate on.
1368	*/
1369	void pgmUnlock(PVM pVM)
1370	{
1371	PDMCritSectLeave(&pVM->pgm.s.CritSect);
1372	}
1373
1374
1375	#ifdef VBOX_STRICT
1376
1377	/**
1378	* State structure used by the PGMAssertHandlerAndFlagsInSync() function
1379	* and its AVL enumerators.
1380	*/
1381	typedef struct PGMAHAFIS
1382	{
1383	/** The VM handle. */
1384	PVM pVM;
1385	/** Number of errors. */
1386	unsigned cErrors;
1387	/** The flags we've found. */
1388	unsigned fFlagsFound;
1389	/** The flags we're matching up to.
1390	* This is also on the stack as a const, thus only valid during enumeration. */
1391	unsigned fFlags;
1392	/** The current physical address. */
1393	RTGCPHYS GCPhys;
1394	} PGMAHAFIS, *PPGMAHAFIS;
1395
1396	/**
1397	* Verify virtual handler by matching physical address.
1398	*
1399	* @returns 0
1400	* @param pNode Pointer to a PGMVIRTHANDLER.
1401	* @param pvUser Pointer to user parameter.
1402	*/
1403	static DECLCALLBACK(int) pgmVirtHandlerVerifyOneByPhysAddr(PAVLROGCPTRNODECORE pNode, void *pvUser)
1404	{
1405	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)pNode;
1406	PPGMAHAFIS pState = (PPGMAHAFIS)pvUser;
1407
1408	for (unsigned iPage = 0; iPage < pCur->cPages; iPage++)
1409	{
1410	if ((pCur->aPhysToVirt[iPage].Core.Key & X86_PTE_PAE_PG_MASK) == pState->GCPhys)
1411	{
1412	switch (pCur->enmType)
1413	{
1414	case PGMVIRTHANDLERTYPE_EIP:
1415	case PGMVIRTHANDLERTYPE_NORMAL: pState->fFlagsFound \|= MM_RAM_FLAGS_VIRTUAL_HANDLER; break;
1416	case PGMVIRTHANDLERTYPE_WRITE: pState->fFlagsFound \|= MM_RAM_FLAGS_VIRTUAL_HANDLER \| MM_RAM_FLAGS_VIRTUAL_WRITE; break;
1417	case PGMVIRTHANDLERTYPE_ALL: pState->fFlagsFound \|= MM_RAM_FLAGS_VIRTUAL_HANDLER \| MM_RAM_FLAGS_VIRTUAL_ALL; break;
1418	/* hypervisor handlers need no flags and wouldn't have nowhere to put them in any case. */
1419	case PGMVIRTHANDLERTYPE_HYPERVISOR:
1420	return 0;
1421	}
1422	if ( (pState->fFlags & (MM_RAM_FLAGS_VIRTUAL_HANDLER \| MM_RAM_FLAGS_VIRTUAL_WRITE \| MM_RAM_FLAGS_VIRTUAL_ALL))
1423	== pState->fFlagsFound)
1424	break;
1425	}
1426	}
1427	return 0;
1428	}
1429
1430
1431	/**
1432	* Verify a virtual handler.
1433	*
1434	* @returns 0
1435	* @param pNode Pointer to a PGMVIRTHANDLER.
1436	* @param pvUser Pointer to user parameter.
1437	*/
1438	static DECLCALLBACK(int) pgmVirtHandlerVerifyOne(PAVLROGCPTRNODECORE pNode, void *pvUser)
1439	{
1440	PPGMVIRTHANDLER pVirt = (PPGMVIRTHANDLER)pNode;
1441	PPGMAHAFIS pState = (PPGMAHAFIS)pvUser;
1442	PVM pVM = pState->pVM;
1443
1444	if ( pVirt->aPhysToVirt[0].Core.Key != NIL_RTGCPHYS
1445	&& (pVirt->aPhysToVirt[0].Core.Key & PAGE_OFFSET_MASK) != ((RTGCUINTPTR)pVirt->GCPtr & PAGE_OFFSET_MASK))
1446	{
1447	AssertMsgFailed(("virt handler phys out has incorrect key! %VGp %VGv %s\n",
1448	pVirt->aPhysToVirt[0].Core.Key, pVirt->GCPtr, HCSTRING(pVirt->pszDesc)));
1449	pState->cErrors++;
1450	}
1451
1452	/*
1453	* Calc flags.
1454	*/
1455	unsigned fFlags;
1456	switch (pVirt->enmType)
1457	{
1458	case PGMVIRTHANDLERTYPE_EIP:
1459	case PGMVIRTHANDLERTYPE_NORMAL: fFlags = MM_RAM_FLAGS_VIRTUAL_HANDLER; break;
1460	case PGMVIRTHANDLERTYPE_WRITE: fFlags = MM_RAM_FLAGS_VIRTUAL_HANDLER \| MM_RAM_FLAGS_VIRTUAL_WRITE; break;
1461	case PGMVIRTHANDLERTYPE_ALL: fFlags = MM_RAM_FLAGS_VIRTUAL_HANDLER \| MM_RAM_FLAGS_VIRTUAL_ALL; break;
1462	/* hypervisor handlers need no flags and wouldn't have nowhere to put them in any case. */
1463	case PGMVIRTHANDLERTYPE_HYPERVISOR:
1464	return 0;
1465	default:
1466	AssertMsgFailed(("unknown enmType=%d\n", pVirt->enmType));
1467	return 0;
1468	}
1469
1470	/*
1471	* Check pages against flags.
1472	*/
1473	RTGCUINTPTR GCPtr = (RTGCUINTPTR)pVirt->GCPtr;
1474	for (unsigned iPage = 0; iPage < pVirt->cPages; iPage++, GCPtr += PAGE_SIZE)
1475	{
1476	RTGCPHYS GCPhysGst;
1477	uint64_t fGst;
1478	int rc = PGMGstGetPage(pVM, (RTGCPTR)GCPtr, &fGst, &GCPhysGst);
1479	if (rc == VERR_PAGE_NOT_PRESENT)
1480	{
1481	if (pVirt->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
1482	{
1483	AssertMsgFailed(("virt handler phys out of sync. %VGp GCPhysNew=~0 iPage=%#x %VGv %s\n",
1484	pVirt->aPhysToVirt[iPage].Core.Key, iPage, GCPtr, HCSTRING(pVirt->pszDesc)));
1485	pState->cErrors++;
1486	}
1487	continue;
1488	}
1489
1490	AssertRCReturn(rc, 0);
1491	if ((pVirt->aPhysToVirt[iPage].Core.Key & X86_PTE_PAE_PG_MASK) != GCPhysGst)
1492	{
1493	AssertMsgFailed(("virt handler phys out of sync. %VGp GCPhysGst=%VGp iPage=%#x %VGv %s\n",
1494	pVirt->aPhysToVirt[iPage].Core.Key, GCPhysGst, iPage, GCPtr, HCSTRING(pVirt->pszDesc)));
1495	pState->cErrors++;
1496	continue;
1497	}
1498
1499	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, GCPhysGst);
1500	if (!pPage)
1501	{
1502	AssertMsgFailed(("virt handler getting ram flags. GCPhysGst=%VGp iPage=%#x %VGv %s\n",
1503	GCPhysGst, iPage, GCPtr, HCSTRING(pVirt->pszDesc)));
1504	pState->cErrors++;
1505	continue;
1506	}
1507
1508	if ((pPage->HCPhys & fFlags) != fFlags) /** @todo PAGE FLAGS */
1509	{
1510	AssertMsgFailed(("virt handler flags mismatch. HCPhys=%VHp fFlags=%#x GCPhysGst=%VGp iPage=%#x %VGv %s\n",
1511	pPage->HCPhys, fFlags, GCPhysGst, iPage, GCPtr, HCSTRING(pVirt->pszDesc)));
1512	pState->cErrors++;
1513	continue;
1514	}
1515	} /* for pages in virtual mapping. */
1516
1517	return 0;
1518	}
1519
1520
1521	/**
1522	* Asserts that the handlers+guest-page-tables == ramrange-flags and
1523	* that the physical addresses associated with virtual handlers are correct.
1524	*
1525	* @returns Number of mismatches.
1526	* @param pVM The VM handle.
1527	*/
1528	PGMDECL(unsigned) PGMAssertHandlerAndFlagsInSync(PVM pVM)
1529	{
1530	PPGM pPGM = &pVM->pgm.s;
1531	PGMAHAFIS State;
1532	State.cErrors = 0;
1533	State.pVM = pVM;
1534
1535	/*
1536	* Check the RAM flags against the handlers.
1537	*/
1538	for (PPGMRAMRANGE pRam = CTXALLSUFF(pPGM->pRamRanges); pRam; pRam = CTXALLSUFF(pRam->pNext))
1539	{
1540	const unsigned cPages = pRam->cb >> PAGE_SHIFT;
1541	for (unsigned iPage = 0; iPage < cPages; iPage++)
1542	{
1543	PGMPAGE const *pPage = &pRam->aPages[iPage];
1544	if (PGM_PAGE_HAVE_ANY_HANDLERS(pPage))
1545	{
1546	State.GCPhys = pRam->GCPhys + (iPage << PAGE_SHIFT);
1547	State.fFlagsFound = 0; /* build flags and compare. */
1548
1549	/*
1550	* Physical first - calculate the state based on the handlers
1551	* active on the page, then compare.
1552	*/
1553	if (PGM_PAGE_HAVE_ANY_PHYSICAL_HANDLERS(pPage))
1554	{
1555	/* the first */
1556	PPGMPHYSHANDLER pPhys = (PPGMPHYSHANDLER)RTAvlroGCPhysRangeGet(&pPGM->CTXSUFF(pTrees)->PhysHandlers, State.GCPhys);
1557	if (!pPhys)
1558	{
1559	pPhys = (PPGMPHYSHANDLER)RTAvlroGCPhysGetBestFit(&pPGM->CTXSUFF(pTrees)->PhysHandlers, State.GCPhys, true);
1560	if ( pPhys
1561	&& pPhys->Core.Key > (State.GCPhys + PAGE_SIZE - 1))
1562	pPhys = NULL;
1563	Assert(!pPhys \|\| pPhys->Core.Key >= State.GCPhys);
1564	}
1565	if (pPhys)
1566	{
1567	unsigned uState = pgmHandlerPhysicalCalcState(pPhys);
1568
1569	/* more? */
1570	while (pPhys->Core.KeyLast < (State.GCPhys \| PAGE_OFFSET_MASK))
1571	{
1572	PPGMPHYSHANDLER pPhys2 = (PPGMPHYSHANDLER)RTAvlroGCPhysGetBestFit(&pPGM->CTXSUFF(pTrees)->PhysHandlers,
1573	pPhys->Core.KeyLast + 1, true);
1574	if ( !pPhys2
1575	\|\| pPhys2->Core.Key > (State.GCPhys \| PAGE_OFFSET_MASK))
1576	break;
1577	unsigned uState2 = pgmHandlerPhysicalCalcState(pPhys2);
1578	uState = RT_MAX(uState, uState2);
1579	pPhys2 = pPhys2;
1580	}
1581
1582	/* compare.*/
1583	if ( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) != uState
1584	&& PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) != PGM_PAGE_HNDL_PHYS_STATE_DISABLED)
1585	{
1586	AssertMsgFailed(("ram range vs phys handler flags mismatch. GCPhys=%RGp state=%d expected=%d %s\n",
1587	State.GCPhys, PGM_PAGE_GET_HNDL_PHYS_STATE(pPage), uState, pPhys->pszDesc));
1588	State.cErrors++;
1589	}
1590
1591	#ifdef IN_RING3
1592	/* validate that REM is handling it. */
1593	if (!REMR3IsPageAccessHandled(pVM, State.GCPhys))
1594	{
1595	AssertMsgFailed(("ram range vs phys handler REM mismatch. GCPhys=%RGp state=%d %s\n",
1596	State.GCPhys, PGM_PAGE_GET_HNDL_PHYS_STATE(pPage), pPhys->pszDesc));
1597	State.cErrors++;
1598	}
1599	#endif
1600	}
1601	else
1602	{
1603	AssertMsgFailed(("ram range vs phys handler mismatch. no handler for GCPhys=%RGp\n", State.GCPhys));
1604	State.cErrors++;
1605	}
1606	}
1607
1608	/* virtual flags. */
1609	if (PGM_PAGE_HAVE_ACTIVE_VIRTUAL_HANDLERS(pPage))
1610	{
1611	State.fFlags = pPage->HCPhys & (MM_RAM_FLAGS_VIRTUAL_HANDLER \| MM_RAM_FLAGS_VIRTUAL_WRITE \| MM_RAM_FLAGS_VIRTUAL_ALL); /// @todo PAGE FLAGS
1612	RTAvlroGCPtrDoWithAll(CTXSUFF(&pVM->pgm.s.pTrees)->VirtHandlers, true, pgmVirtHandlerVerifyOneByPhysAddr, &State);
1613	if (State.fFlags != State.fFlagsFound)
1614	{
1615	AssertMsgFailed(("ram range vs virt handler flags mismatch. GCPhys=%RGp fFlags=%#x fFlagsFound=%#x\n",
1616	State.GCPhys, State.fFlags, State.fFlagsFound));
1617	State.cErrors++;
1618	}
1619
1620	}
1621	}
1622	} /* foreach page in ram range. */
1623	} /* foreach ram range. */
1624
1625	/*
1626	* Check that the physical addresses of the virtual handlers matches up.
1627	*/
1628	RTAvlroGCPtrDoWithAll(CTXSUFF(&pVM->pgm.s.pTrees)->VirtHandlers, true, pgmVirtHandlerVerifyOne, &State);
1629
1630	/*
1631	* Do the reverse check for physical handlers.
1632	*/
1633	/** @todo */
1634
1635	return State.cErrors;
1636	}
1637
1638
1639	/**
1640	* Asserts that there are no mapping conflicts.
1641	*
1642	* @returns Number of conflicts.
1643	* @param pVM The VM Handle.
1644	*/
1645	PGMDECL(unsigned) PGMAssertNoMappingConflicts(PVM pVM)
1646	{
1647	unsigned cErrors = 0;
1648
1649	/*
1650	* Check for mapping conflicts.
1651	*/
1652	for (PPGMMAPPING pMapping = CTXALLSUFF(pVM->pgm.s.pMappings);
1653	pMapping;
1654	pMapping = CTXALLSUFF(pMapping->pNext))
1655	{
1656	/** @todo This is slow and should be optimized, but since it's just assertions I don't care now. */
1657	for (RTGCUINTPTR GCPtr = (RTGCUINTPTR)pMapping->GCPtr;
1658	GCPtr <= (RTGCUINTPTR)pMapping->GCPtrLast;
1659	GCPtr += PAGE_SIZE)
1660	{
1661	int rc = PGMGstGetPage(pVM, (RTGCPTR)GCPtr, NULL, NULL);
1662	if (rc != VERR_PAGE_TABLE_NOT_PRESENT)
1663	{
1664	AssertMsgFailed(("Conflict at %VGv with %s\n", GCPtr, HCSTRING(pMapping->pszDesc)));
1665	cErrors++;
1666	break;
1667	}
1668	}
1669	}
1670
1671	return cErrors;
1672	}
1673
1674
1675	/**
1676	* Asserts that everything related to the guest CR3 is correctly shadowed.
1677	*
1678	* This will call PGMAssertNoMappingConflicts() and PGMAssertHandlerAndFlagsInSync(),
1679	* and assert the correctness of the guest CR3 mapping before asserting that the
1680	* shadow page tables is in sync with the guest page tables.
1681	*
1682	* @returns Number of conflicts.
1683	* @param pVM The VM Handle.
1684	* @param cr3 The current guest CR3 register value.
1685	* @param cr4 The current guest CR4 register value.
1686	*/
1687	PGMDECL(unsigned) PGMAssertCR3(PVM pVM, uint32_t cr3, uint32_t cr4)
1688	{
1689	STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat,SyncCR3), a);
1690	unsigned cErrors = PGM_BTH_PFN(AssertCR3, pVM)(pVM, cr3, cr4, 0, ~(RTGCUINTPTR)0);
1691	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncCR3), a);
1692	return cErrors;
1693	}
1694
1695	#endif /* VBOX_STRICT */

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAll.cpp@ 6902

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