VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAll.cpp@ 9756

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1/* $Id: PGMAll.cpp 9755 2008-06-17 11:07:05Z vboxsync $ */
2/** @file
3 * PGM - Page Manager and Monitor - All context code.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22/*******************************************************************************
23* Header Files *
24*******************************************************************************/
25#define LOG_GROUP LOG_GROUP_PGM
26#include <VBox/pgm.h>
27#include <VBox/cpum.h>
28#include <VBox/selm.h>
29#include <VBox/iom.h>
30#include <VBox/sup.h>
31#include <VBox/mm.h>
32#include <VBox/stam.h>
33#include <VBox/csam.h>
34#include <VBox/patm.h>
35#include <VBox/trpm.h>
36#include <VBox/rem.h>
37#include <VBox/em.h>
38#include <VBox/hwaccm.h>
39#include "PGMInternal.h"
40#include <VBox/vm.h>
41#include <iprt/assert.h>
42#include <iprt/asm.h>
43#include <iprt/string.h>
44#include <VBox/log.h>
45#include <VBox/param.h>
46#include <VBox/err.h>
47
48
49/*******************************************************************************
50* Structures and Typedefs *
51*******************************************************************************/
52/**
53 * Stated structure for PGM_GST_NAME(HandlerVirtualUpdate) that's
54 * passed to PGM_GST_NAME(VirtHandlerUpdateOne) during enumeration.
55 */
56typedef struct PGMHVUSTATE
57{
58 /** The VM handle. */
59 PVM pVM;
60 /** The todo flags. */
61 RTUINT fTodo;
62 /** The CR4 register value. */
63 uint32_t cr4;
64} PGMHVUSTATE, *PPGMHVUSTATE;
65
66
67/*******************************************************************************
68* Internal Functions *
69*******************************************************************************/
70
71/*
72 * Shadow - 32-bit mode
73 */
74#define PGM_SHW_TYPE PGM_TYPE_32BIT
75#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
76#include "PGMAllShw.h"
77
78/* Guest - real mode */
79#define PGM_GST_TYPE PGM_TYPE_REAL
80#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
81#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
82#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
83#include "PGMAllGst.h"
84#include "PGMAllBth.h"
85#undef BTH_PGMPOOLKIND_PT_FOR_PT
86#undef PGM_BTH_NAME
87#undef PGM_GST_TYPE
88#undef PGM_GST_NAME
89
90/* Guest - protected mode */
91#define PGM_GST_TYPE PGM_TYPE_PROT
92#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
93#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
94#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
95#include "PGMAllGst.h"
96#include "PGMAllBth.h"
97#undef BTH_PGMPOOLKIND_PT_FOR_PT
98#undef PGM_BTH_NAME
99#undef PGM_GST_TYPE
100#undef PGM_GST_NAME
101
102/* Guest - 32-bit mode */
103#define PGM_GST_TYPE PGM_TYPE_32BIT
104#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
105#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
106#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
107#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
108#include "PGMAllGst.h"
109#include "PGMAllBth.h"
110#undef BTH_PGMPOOLKIND_PT_FOR_BIG
111#undef BTH_PGMPOOLKIND_PT_FOR_PT
112#undef PGM_BTH_NAME
113#undef PGM_GST_TYPE
114#undef PGM_GST_NAME
115
116#undef PGM_SHW_TYPE
117#undef PGM_SHW_NAME
118
119
120/*
121 * Shadow - PAE mode
122 */
123#define PGM_SHW_TYPE PGM_TYPE_PAE
124#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
125#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
126#include "PGMAllShw.h"
127
128/* Guest - real mode */
129#define PGM_GST_TYPE PGM_TYPE_REAL
130#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
131#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
132#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
133#include "PGMAllBth.h"
134#undef BTH_PGMPOOLKIND_PT_FOR_PT
135#undef PGM_BTH_NAME
136#undef PGM_GST_TYPE
137#undef PGM_GST_NAME
138
139/* Guest - protected mode */
140#define PGM_GST_TYPE PGM_TYPE_PROT
141#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
142#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
143#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
144#include "PGMAllBth.h"
145#undef BTH_PGMPOOLKIND_PT_FOR_PT
146#undef PGM_BTH_NAME
147#undef PGM_GST_TYPE
148#undef PGM_GST_NAME
149
150/* Guest - 32-bit mode */
151#define PGM_GST_TYPE PGM_TYPE_32BIT
152#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
153#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
154#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
155#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
156#include "PGMAllBth.h"
157#undef BTH_PGMPOOLKIND_PT_FOR_BIG
158#undef BTH_PGMPOOLKIND_PT_FOR_PT
159#undef PGM_BTH_NAME
160#undef PGM_GST_TYPE
161#undef PGM_GST_NAME
162
163
164/* Guest - PAE mode */
165#define PGM_GST_TYPE PGM_TYPE_PAE
166#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
167#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
168#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
169#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
170#include "PGMAllGst.h"
171#include "PGMAllBth.h"
172#undef BTH_PGMPOOLKIND_PT_FOR_BIG
173#undef BTH_PGMPOOLKIND_PT_FOR_PT
174#undef PGM_BTH_NAME
175#undef PGM_GST_TYPE
176#undef PGM_GST_NAME
177
178#undef PGM_SHW_TYPE
179#undef PGM_SHW_NAME
180
181
182#ifndef IN_GC /* AMD64 implies VT-x/AMD-V */
183/*
184 * Shadow - AMD64 mode
185 */
186#define PGM_SHW_TYPE PGM_TYPE_AMD64
187#define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
188#include "PGMAllShw.h"
189
190/* Guest - protected mode */
191#define PGM_GST_TYPE PGM_TYPE_PROT
192#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
193#define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_PROT(name)
194#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
195#include "PGMAllBth.h"
196#undef BTH_PGMPOOLKIND_PT_FOR_PT
197#undef PGM_BTH_NAME
198#undef PGM_GST_TYPE
199#undef PGM_GST_NAME
200
201/* Guest - AMD64 mode */
202#define PGM_GST_TYPE PGM_TYPE_AMD64
203#define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
204#define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
205#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
206#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
207#include "PGMAllGst.h"
208#include "PGMAllBth.h"
209#undef BTH_PGMPOOLKIND_PT_FOR_BIG
210#undef BTH_PGMPOOLKIND_PT_FOR_PT
211#undef PGM_BTH_NAME
212#undef PGM_GST_TYPE
213#undef PGM_GST_NAME
214
215#undef PGM_SHW_TYPE
216#undef PGM_SHW_NAME
217
218/*
219 * Shadow - Nested paging mode
220 */
221#define PGM_SHW_TYPE PGM_TYPE_NESTED
222#define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED(name)
223#include "PGMAllShw.h"
224
225/* Guest - real mode */
226#define PGM_GST_TYPE PGM_TYPE_REAL
227#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
228#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_REAL(name)
229#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
230#include "PGMAllBth.h"
231#undef BTH_PGMPOOLKIND_PT_FOR_PT
232#undef PGM_BTH_NAME
233#undef PGM_GST_TYPE
234#undef PGM_GST_NAME
235
236/* Guest - protected mode */
237#define PGM_GST_TYPE PGM_TYPE_PROT
238#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
239#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PROT(name)
240#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
241#include "PGMAllBth.h"
242#undef BTH_PGMPOOLKIND_PT_FOR_PT
243#undef PGM_BTH_NAME
244#undef PGM_GST_TYPE
245#undef PGM_GST_NAME
246
247/* Guest - 32-bit mode */
248#define PGM_GST_TYPE PGM_TYPE_32BIT
249#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
250#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT(name)
251#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
252#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
253#include "PGMAllBth.h"
254#undef BTH_PGMPOOLKIND_PT_FOR_BIG
255#undef BTH_PGMPOOLKIND_PT_FOR_PT
256#undef PGM_BTH_NAME
257#undef PGM_GST_TYPE
258#undef PGM_GST_NAME
259
260/* Guest - PAE mode */
261#define PGM_GST_TYPE PGM_TYPE_PAE
262#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
263#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE(name)
264#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
265#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
266#include "PGMAllBth.h"
267#undef BTH_PGMPOOLKIND_PT_FOR_BIG
268#undef BTH_PGMPOOLKIND_PT_FOR_PT
269#undef PGM_BTH_NAME
270#undef PGM_GST_TYPE
271#undef PGM_GST_NAME
272
273/* Guest - AMD64 mode */
274#define PGM_GST_TYPE PGM_TYPE_AMD64
275#define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
276#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64(name)
277#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
278#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
279#include "PGMAllBth.h"
280#undef BTH_PGMPOOLKIND_PT_FOR_BIG
281#undef BTH_PGMPOOLKIND_PT_FOR_PT
282#undef PGM_BTH_NAME
283#undef PGM_GST_TYPE
284#undef PGM_GST_NAME
285
286#undef PGM_SHW_TYPE
287#undef PGM_SHW_NAME
288#endif
289
290/**
291 * #PF Handler.
292 *
293 * @returns VBox status code (appropriate for trap handling and GC return).
294 * @param pVM VM Handle.
295 * @param uErr The trap error code.
296 * @param pRegFrame Trap register frame.
297 * @param pvFault The fault address.
298 */
299PGMDECL(int) PGMTrap0eHandler(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
300{
301 LogFlow(("PGMTrap0eHandler: uErr=%#x pvFault=%VGv eip=%VGv\n", (uint32_t)uErr, pvFault, pRegFrame->rip));
302 STAM_PROFILE_START(&pVM->pgm.s.StatGCTrap0e, a);
303 STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = NULL; } );
304
305
306#ifdef VBOX_WITH_STATISTICS
307 /*
308 * Error code stats.
309 */
310 if (uErr & X86_TRAP_PF_US)
311 {
312 if (!(uErr & X86_TRAP_PF_P))
313 {
314 if (uErr & X86_TRAP_PF_RW)
315 STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eUSNotPresentWrite);
316 else
317 STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eUSNotPresentRead);
318 }
319 else if (uErr & X86_TRAP_PF_RW)
320 STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eUSWrite);
321 else if (uErr & X86_TRAP_PF_RSVD)
322 STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eUSReserved);
323 else if (uErr & X86_TRAP_PF_ID)
324 STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eUSNXE);
325 else
326 STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eUSRead);
327 }
328 else
329 { /* Supervisor */
330 if (!(uErr & X86_TRAP_PF_P))
331 {
332 if (uErr & X86_TRAP_PF_RW)
333 STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eSVNotPresentWrite);
334 else
335 STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eSVNotPresentRead);
336 }
337 else if (uErr & X86_TRAP_PF_RW)
338 STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eSVWrite);
339 else if (uErr & X86_TRAP_PF_ID)
340 STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eSNXE);
341 else if (uErr & X86_TRAP_PF_RSVD)
342 STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eSVReserved);
343 }
344#endif
345
346 /*
347 * Call the worker.
348 */
349 int rc = PGM_BTH_PFN(Trap0eHandler, pVM)(pVM, uErr, pRegFrame, pvFault);
350 if (rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
351 rc = VINF_SUCCESS;
352 STAM_STATS({ if (!pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution))
353 pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eMisc; });
354 STAM_PROFILE_STOP_EX(&pVM->pgm.s.StatGCTrap0e, pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution), a);
355 return rc;
356}
357
358/**
359 * Prefetch a page
360 *
361 * Typically used to sync commonly used pages before entering raw mode
362 * after a CR3 reload.
363 *
364 * @returns VBox status code suitable for scheduling.
365 * @retval VINF_SUCCESS on success.
366 * @retval VINF_PGM_SYNC_CR3 if we're out of shadow pages or something like that.
367 * @param pVM VM handle.
368 * @param GCPtrPage Page to invalidate.
369 */
370PGMDECL(int) PGMPrefetchPage(PVM pVM, RTGCPTR GCPtrPage)
371{
372 STAM_PROFILE_START(&pVM->pgm.s.StatHCPrefetch, a);
373 int rc = PGM_BTH_PFN(PrefetchPage, pVM)(pVM, (RTGCUINTPTR)GCPtrPage);
374 STAM_PROFILE_STOP(&pVM->pgm.s.StatHCPrefetch, a);
375 AssertMsg(rc == VINF_SUCCESS || rc == VINF_PGM_SYNC_CR3 || VBOX_FAILURE(rc), ("rc=%Vrc\n", rc));
376 return rc;
377}
378
379
380/**
381 * Gets the mapping corresponding to the specified address (if any).
382 *
383 * @returns Pointer to the mapping.
384 * @returns NULL if not
385 *
386 * @param pVM The virtual machine.
387 * @param GCPtr The guest context pointer.
388 */
389PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr)
390{
391 PPGMMAPPING pMapping = CTXALLSUFF(pVM->pgm.s.pMappings);
392 while (pMapping)
393 {
394 if ((uintptr_t)GCPtr < (uintptr_t)pMapping->GCPtr)
395 break;
396 if ((uintptr_t)GCPtr - (uintptr_t)pMapping->GCPtr < pMapping->cb)
397 {
398 STAM_COUNTER_INC(&pVM->pgm.s.StatGCSyncPTConflict);
399 return pMapping;
400 }
401 pMapping = CTXALLSUFF(pMapping->pNext);
402 }
403 return NULL;
404}
405
406
407/**
408 * Verifies a range of pages for read or write access
409 *
410 * Only checks the guest's page tables
411 *
412 * @returns VBox status code.
413 * @param pVM VM handle.
414 * @param Addr Guest virtual address to check
415 * @param cbSize Access size
416 * @param fAccess Access type (r/w, user/supervisor (X86_PTE_*))
417 */
418PGMDECL(int) PGMIsValidAccess(PVM pVM, RTGCUINTPTR Addr, uint32_t cbSize, uint32_t fAccess)
419{
420 /*
421 * Validate input.
422 */
423 if (fAccess & ~(X86_PTE_US | X86_PTE_RW))
424 {
425 AssertMsgFailed(("PGMIsValidAccess: invalid access type %08x\n", fAccess));
426 return VERR_INVALID_PARAMETER;
427 }
428
429 uint64_t fPage;
430 int rc = PGMGstGetPage(pVM, (RTGCPTR)Addr, &fPage, NULL);
431 if (VBOX_FAILURE(rc))
432 {
433 Log(("PGMIsValidAccess: access violation for %VGv rc=%d\n", Addr, rc));
434 return VINF_EM_RAW_GUEST_TRAP;
435 }
436
437 /*
438 * Check if the access would cause a page fault
439 *
440 * Note that hypervisor page directories are not present in the guest's tables, so this check
441 * is sufficient.
442 */
443 bool fWrite = !!(fAccess & X86_PTE_RW);
444 bool fUser = !!(fAccess & X86_PTE_US);
445 if ( !(fPage & X86_PTE_P)
446 || (fWrite && !(fPage & X86_PTE_RW))
447 || (fUser && !(fPage & X86_PTE_US)) )
448 {
449 Log(("PGMIsValidAccess: access violation for %VGv attr %#llx vs %d:%d\n", Addr, fPage, fWrite, fUser));
450 return VINF_EM_RAW_GUEST_TRAP;
451 }
452 if ( VBOX_SUCCESS(rc)
453 && PAGE_ADDRESS(Addr) != PAGE_ADDRESS(Addr + cbSize))
454 return PGMIsValidAccess(pVM, Addr + PAGE_SIZE, (cbSize > PAGE_SIZE) ? cbSize - PAGE_SIZE : 1, fAccess);
455 return rc;
456}
457
458
459/**
460 * Verifies a range of pages for read or write access
461 *
462 * Supports handling of pages marked for dirty bit tracking and CSAM
463 *
464 * @returns VBox status code.
465 * @param pVM VM handle.
466 * @param Addr Guest virtual address to check
467 * @param cbSize Access size
468 * @param fAccess Access type (r/w, user/supervisor (X86_PTE_*))
469 */
470PGMDECL(int) PGMVerifyAccess(PVM pVM, RTGCUINTPTR Addr, uint32_t cbSize, uint32_t fAccess)
471{
472 /*
473 * Validate input.
474 */
475 if (fAccess & ~(X86_PTE_US | X86_PTE_RW))
476 {
477 AssertMsgFailed(("PGMVerifyAccess: invalid access type %08x\n", fAccess));
478 return VERR_INVALID_PARAMETER;
479 }
480
481 uint64_t fPageGst;
482 int rc = PGMGstGetPage(pVM, (RTGCPTR)Addr, &fPageGst, NULL);
483 if (VBOX_FAILURE(rc))
484 {
485 Log(("PGMVerifyAccess: access violation for %VGv rc=%d\n", Addr, rc));
486 return VINF_EM_RAW_GUEST_TRAP;
487 }
488
489 /*
490 * Check if the access would cause a page fault
491 *
492 * Note that hypervisor page directories are not present in the guest's tables, so this check
493 * is sufficient.
494 */
495 const bool fWrite = !!(fAccess & X86_PTE_RW);
496 const bool fUser = !!(fAccess & X86_PTE_US);
497 if ( !(fPageGst & X86_PTE_P)
498 || (fWrite && !(fPageGst & X86_PTE_RW))
499 || (fUser && !(fPageGst & X86_PTE_US)) )
500 {
501 Log(("PGMVerifyAccess: access violation for %VGv attr %#llx vs %d:%d\n", Addr, fPageGst, fWrite, fUser));
502 return VINF_EM_RAW_GUEST_TRAP;
503 }
504
505 if (!HWACCMIsNestedPagingActive(pVM))
506 {
507 /*
508 * Next step is to verify if we protected this page for dirty bit tracking or for CSAM scanning
509 */
510 rc = PGMShwGetPage(pVM, (RTGCPTR)Addr, NULL, NULL);
511 if ( rc == VERR_PAGE_NOT_PRESENT
512 || rc == VERR_PAGE_TABLE_NOT_PRESENT)
513 {
514 /*
515 * Page is not present in our page tables.
516 * Try to sync it!
517 */
518 Assert(X86_TRAP_PF_RW == X86_PTE_RW && X86_TRAP_PF_US == X86_PTE_US);
519 uint32_t uErr = fAccess & (X86_TRAP_PF_RW | X86_TRAP_PF_US);
520 rc = PGM_BTH_PFN(VerifyAccessSyncPage, pVM)(pVM, Addr, fPageGst, uErr);
521 if (rc != VINF_SUCCESS)
522 return rc;
523 }
524 else
525 AssertMsg(rc == VINF_SUCCESS, ("PGMShwGetPage %VGv failed with %Vrc\n", Addr, rc));
526 }
527
528#if 0 /* def VBOX_STRICT; triggers too often now */
529 /*
530 * This check is a bit paranoid, but useful.
531 */
532 /** @note this will assert when writing to monitored pages (a bit annoying actually) */
533 uint64_t fPageShw;
534 rc = PGMShwGetPage(pVM, (RTGCPTR)Addr, &fPageShw, NULL);
535 if ( (rc == VERR_PAGE_NOT_PRESENT || VBOX_FAILURE(rc))
536 || (fWrite && !(fPageShw & X86_PTE_RW))
537 || (fUser && !(fPageShw & X86_PTE_US)) )
538 {
539 AssertMsgFailed(("Unexpected access violation for %VGv! rc=%Vrc write=%d user=%d\n",
540 Addr, rc, fWrite && !(fPageShw & X86_PTE_RW), fUser && !(fPageShw & X86_PTE_US)));
541 return VINF_EM_RAW_GUEST_TRAP;
542 }
543#endif
544
545 if ( VBOX_SUCCESS(rc)
546 && ( PAGE_ADDRESS(Addr) != PAGE_ADDRESS(Addr + cbSize - 1)
547 || Addr + cbSize < Addr))
548 {
549 /* Don't recursively call PGMVerifyAccess as we might run out of stack. */
550 for (;;)
551 {
552 Addr += PAGE_SIZE;
553 if (cbSize > PAGE_SIZE)
554 cbSize -= PAGE_SIZE;
555 else
556 cbSize = 1;
557 rc = PGMVerifyAccess(pVM, Addr, 1, fAccess);
558 if (rc != VINF_SUCCESS)
559 break;
560 if (PAGE_ADDRESS(Addr) == PAGE_ADDRESS(Addr + cbSize - 1))
561 break;
562 }
563 }
564 return rc;
565}
566
567
568#ifndef IN_GC
569/**
570 * Emulation of the invlpg instruction (HC only actually).
571 *
572 * @returns VBox status code.
573 * @param pVM VM handle.
574 * @param GCPtrPage Page to invalidate.
575 * @remark ASSUMES the page table entry or page directory is
576 * valid. Fairly safe, but there could be edge cases!
577 * @todo Flush page or page directory only if necessary!
578 */
579PGMDECL(int) PGMInvalidatePage(PVM pVM, RTGCPTR GCPtrPage)
580{
581 int rc;
582
583 Log2(("PGMInvalidatePage: GCPtrPage=%VGv\n", GCPtrPage));
584
585 /** @todo merge PGMGCInvalidatePage with this one */
586
587#ifndef IN_RING3
588 /*
589 * Notify the recompiler so it can record this instruction.
590 * Failure happens when it's out of space. We'll return to HC in that case.
591 */
592 rc = REMNotifyInvalidatePage(pVM, GCPtrPage);
593 if (VBOX_FAILURE(rc))
594 return rc;
595#endif
596
597 STAM_PROFILE_START(&CTXMID(pVM->pgm.s.Stat,InvalidatePage), a);
598 rc = PGM_BTH_PFN(InvalidatePage, pVM)(pVM, GCPtrPage);
599 STAM_PROFILE_STOP(&CTXMID(pVM->pgm.s.Stat,InvalidatePage), a);
600
601#ifndef IN_RING0
602 /*
603 * Check if we have a pending update of the CR3 monitoring.
604 */
605 if ( VBOX_SUCCESS(rc)
606 && (pVM->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3))
607 {
608 pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
609 Assert(!pVM->pgm.s.fMappingsFixed);
610 Assert(pVM->pgm.s.GCPhysCR3 == pVM->pgm.s.GCPhysGstCR3Monitored);
611 rc = PGM_GST_PFN(MonitorCR3, pVM)(pVM, pVM->pgm.s.GCPhysCR3);
612 }
613#endif
614
615#ifdef IN_RING3
616 /*
617 * Inform CSAM about the flush
618 */
619 /** @note this is to check if monitored pages have been changed; when we implement callbacks for virtual handlers, this is no longer required. */
620 CSAMR3FlushPage(pVM, GCPtrPage);
621#endif
622 return rc;
623}
624#endif
625
626
627/**
628 * Executes an instruction using the interpreter.
629 *
630 * @returns VBox status code (appropriate for trap handling and GC return).
631 * @param pVM VM handle.
632 * @param pRegFrame Register frame.
633 * @param pvFault Fault address.
634 */
635PGMDECL(int) PGMInterpretInstruction(PVM pVM, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
636{
637 uint32_t cb;
638 int rc = EMInterpretInstruction(pVM, pRegFrame, pvFault, &cb);
639 if (rc == VERR_EM_INTERPRETER)
640 rc = VINF_EM_RAW_EMULATE_INSTR;
641 if (rc != VINF_SUCCESS)
642 Log(("PGMInterpretInstruction: returns %Rrc (pvFault=%VGv)\n", rc, pvFault));
643 return rc;
644}
645
646
647/**
648 * Gets effective page information (from the VMM page directory).
649 *
650 * @returns VBox status.
651 * @param pVM VM Handle.
652 * @param GCPtr Guest Context virtual address of the page.
653 * @param pfFlags Where to store the flags. These are X86_PTE_*.
654 * @param pHCPhys Where to store the HC physical address of the page.
655 * This is page aligned.
656 * @remark You should use PGMMapGetPage() for pages in a mapping.
657 */
658PGMDECL(int) PGMShwGetPage(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys)
659{
660 return PGM_SHW_PFN(GetPage,pVM)(pVM, (RTGCUINTPTR)GCPtr, pfFlags, pHCPhys);
661}
662
663
664/**
665 * Sets (replaces) the page flags for a range of pages in the shadow context.
666 *
667 * @returns VBox status.
668 * @param pVM VM handle.
669 * @param GCPtr The address of the first page.
670 * @param cb The size of the range in bytes.
671 * @param fFlags Page flags X86_PTE_*, excluding the page mask of course.
672 * @remark You must use PGMMapSetPage() for pages in a mapping.
673 */
674PGMDECL(int) PGMShwSetPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags)
675{
676 return PGMShwModifyPage(pVM, GCPtr, cb, fFlags, 0);
677}
678
679
680/**
681 * Modify page flags for a range of pages in the shadow context.
682 *
683 * The existing flags are ANDed with the fMask and ORed with the fFlags.
684 *
685 * @returns VBox status code.
686 * @param pVM VM handle.
687 * @param GCPtr Virtual address of the first page in the range.
688 * @param cb Size (in bytes) of the range to apply the modification to.
689 * @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
690 * @param fMask The AND mask - page flags X86_PTE_*.
691 * Be very CAREFUL when ~'ing constants which could be 32-bit!
692 * @remark You must use PGMMapModifyPage() for pages in a mapping.
693 */
694PGMDECL(int) PGMShwModifyPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
695{
696 /*
697 * Validate input.
698 */
699 if (fFlags & X86_PTE_PAE_PG_MASK)
700 {
701 AssertMsgFailed(("fFlags=%#llx\n", fFlags));
702 return VERR_INVALID_PARAMETER;
703 }
704 if (!cb)
705 {
706 AssertFailed();
707 return VERR_INVALID_PARAMETER;
708 }
709
710 /*
711 * Align the input.
712 */
713 cb += (RTGCUINTPTR)GCPtr & PAGE_OFFSET_MASK;
714 cb = RT_ALIGN_Z(cb, PAGE_SIZE);
715 GCPtr = (RTGCPTR)((RTGCUINTPTR)GCPtr & PAGE_BASE_GC_MASK); /** @todo this ain't necessary, right... */
716
717 /*
718 * Call worker.
719 */
720 return PGM_SHW_PFN(ModifyPage, pVM)(pVM, (RTGCUINTPTR)GCPtr, cb, fFlags, fMask);
721}
722
723#ifndef IN_GC
724/**
725 * Syncs the SHADOW page directory pointer for the specified address. Allocates
726 * backing pages in case the PDPT or PML4 entry is missing.
727 *
728 * @returns VBox status.
729 * @param pVM VM handle.
730 * @param GCPtr The address.
731 * @param pGstPml4e Guest PML4 entry
732 * @param pGstPdpe Guest PDPT entry
733 * @param ppPD Receives address of page directory
734 */
735PGMDECL(int) PGMShwSyncLongModePDPtr(PVM pVM, RTGCUINTPTR64 GCPtr, PX86PML4E pGstPml4e, PX86PDPE pGstPdpe, PX86PDPAE *ppPD)
736{
737 PPGM pPGM = &pVM->pgm.s;
738 const unsigned iPml4e = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
739 PPGMPOOL pPool = pPGM->CTXSUFF(pPool);
740 PX86PML4E pPml4e;
741 PPGMPOOLPAGE pShwPage;
742 int rc;
743
744 Assert(!HWACCMIsNestedPagingActive(pVM));
745
746 /* Allocate page directory pointer table if not present. */
747 pPml4e = &pPGM->pHCPaePML4->a[iPml4e];
748 if ( !pPml4e->n.u1Present
749 && !(pPml4e->u & X86_PML4E_PG_MASK))
750 {
751 PX86PML4E pPml4eGst = &pPGM->pGstPaePML4HC->a[iPml4e];
752
753 Assert(!(pPml4e->u & X86_PML4E_PG_MASK));
754 rc = pgmPoolAlloc(pVM, pPml4eGst->u & X86_PML4E_PG_MASK, PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT, PGMPOOL_IDX_PML4, iPml4e, &pShwPage);
755 if (rc == VERR_PGM_POOL_FLUSHED)
756 return VINF_PGM_SYNC_CR3;
757
758 AssertRCReturn(rc, rc);
759 }
760 else
761 {
762 pShwPage = pgmPoolGetPage(pPool, pPml4e->u & X86_PML4E_PG_MASK);
763 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
764 }
765 /* The PDPT was cached or created; hook it up now. */
766 pPml4e->u |= pShwPage->Core.Key
767 | (pGstPml4e->u & ~(X86_PML4E_PG_MASK | X86_PML4E_AVL_MASK | X86_PML4E_PCD | X86_PML4E_PWT));
768
769 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
770 PX86PDPT pPdpt = (PX86PDPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
771 PX86PDPE pPdpe = &pPdpt->a[iPdPt];
772
773 /* Allocate page directory if not present. */
774 if ( !pPdpe->n.u1Present
775 && !(pPdpe->u & X86_PDPE_PG_MASK))
776 {
777 PX86PML4E pPml4eGst = &pPGM->pGstPaePML4HC->a[iPml4e];
778 PX86PDPT pPdptGst;
779 rc = PGM_GCPHYS_2_PTR(pVM, pPml4eGst->u & X86_PML4E_PG_MASK, &pPdptGst);
780 AssertRCReturn(rc, rc);
781
782 Assert(!(pPdpe->u & X86_PDPE_PG_MASK));
783 /* Create a reference back to the PDPT by using the index in its shadow page. */
784 rc = pgmPoolAlloc(pVM, pPdptGst->a[iPdPt].u & X86_PDPE_PG_MASK, PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD, pShwPage->idx, iPdPt, &pShwPage);
785 if (rc == VERR_PGM_POOL_FLUSHED)
786 return VINF_PGM_SYNC_CR3;
787
788 AssertRCReturn(rc, rc);
789 }
790 else
791 {
792 pShwPage = pgmPoolGetPage(pPool, pPdpe->u & X86_PDPE_PG_MASK);
793 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
794 }
795 /* The PD was cached or created; hook it up now. */
796 pPdpe->u |= pShwPage->Core.Key
797 | (pGstPdpe->u & ~(X86_PDPE_PG_MASK | X86_PDPE_AVL_MASK | X86_PDPE_PCD | X86_PDPE_PWT));
798
799 *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
800 return VINF_SUCCESS;
801}
802
803/**
804 * Gets the SHADOW page directory pointer for the specified address.
805 *
806 * @returns VBox status.
807 * @param pVM VM handle.
808 * @param GCPtr The address.
809 * @param ppPdpt Receives address of pdpt
810 * @param ppPD Receives address of page directory
811 */
812PGMDECL(int) PGMShwGetLongModePDPtr(PVM pVM, RTGCUINTPTR64 GCPtr, PX86PDPT *ppPdpt, PX86PDPAE *ppPD)
813{
814 PPGM pPGM = &pVM->pgm.s;
815 const unsigned iPml4e = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
816 PPGMPOOL pPool = pPGM->CTXSUFF(pPool);
817 PX86PML4E pPml4e;
818 PPGMPOOLPAGE pShwPage;
819
820 Assert(!HWACCMIsNestedPagingActive(pVM));
821
822 pPml4e = &pPGM->pHCPaePML4->a[iPml4e];
823 if (!pPml4e->n.u1Present)
824 return VERR_PAGE_MAP_LEVEL4_NOT_PRESENT;
825
826 pShwPage = pgmPoolGetPage(pPool, pPml4e->u & X86_PML4E_PG_MASK);
827 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
828
829 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
830 PX86PDPT pPdpt = (PX86PDPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
831 PX86PDPE pPdpe = &pPdpt->a[iPdPt];
832
833 *ppPdpt = pPdpt;
834 if (!pPdpe->n.u1Present)
835 return VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT;
836
837 pShwPage = pgmPoolGetPage(pPool, pPdpe->u & X86_PDPE_PG_MASK);
838 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
839
840 *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
841 return VINF_SUCCESS;
842}
843#endif
844
845/**
846 * Gets effective Guest OS page information.
847 *
848 * When GCPtr is in a big page, the function will return as if it was a normal
849 * 4KB page. If the need for distinguishing between big and normal page becomes
850 * necessary at a later point, a PGMGstGetPage() will be created for that
851 * purpose.
852 *
853 * @returns VBox status.
854 * @param pVM VM Handle.
855 * @param GCPtr Guest Context virtual address of the page.
856 * @param pfFlags Where to store the flags. These are X86_PTE_*, even for big pages.
857 * @param pGCPhys Where to store the GC physical address of the page.
858 * This is page aligned. The fact that the
859 */
860PGMDECL(int) PGMGstGetPage(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys)
861{
862 return PGM_GST_PFN(GetPage,pVM)(pVM, (RTGCUINTPTR)GCPtr, pfFlags, pGCPhys);
863}
864
865
866/**
867 * Checks if the page is present.
868 *
869 * @returns true if the page is present.
870 * @returns false if the page is not present.
871 * @param pVM The VM handle.
872 * @param GCPtr Address within the page.
873 */
874PGMDECL(bool) PGMGstIsPagePresent(PVM pVM, RTGCPTR GCPtr)
875{
876 int rc = PGMGstGetPage(pVM, GCPtr, NULL, NULL);
877 return VBOX_SUCCESS(rc);
878}
879
880
881/**
882 * Sets (replaces) the page flags for a range of pages in the guest's tables.
883 *
884 * @returns VBox status.
885 * @param pVM VM handle.
886 * @param GCPtr The address of the first page.
887 * @param cb The size of the range in bytes.
888 * @param fFlags Page flags X86_PTE_*, excluding the page mask of course.
889 */
890PGMDECL(int) PGMGstSetPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags)
891{
892 return PGMGstModifyPage(pVM, GCPtr, cb, fFlags, 0);
893}
894
895
896/**
897 * Modify page flags for a range of pages in the guest's tables
898 *
899 * The existing flags are ANDed with the fMask and ORed with the fFlags.
900 *
901 * @returns VBox status code.
902 * @param pVM VM handle.
903 * @param GCPtr Virtual address of the first page in the range.
904 * @param cb Size (in bytes) of the range to apply the modification to.
905 * @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
906 * @param fMask The AND mask - page flags X86_PTE_*, excluding the page mask of course.
907 * Be very CAREFUL when ~'ing constants which could be 32-bit!
908 */
909PGMDECL(int) PGMGstModifyPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
910{
911 STAM_PROFILE_START(&CTXMID(pVM->pgm.s.Stat,GstModifyPage), a);
912
913 /*
914 * Validate input.
915 */
916 if (fFlags & X86_PTE_PAE_PG_MASK)
917 {
918 AssertMsgFailed(("fFlags=%#llx\n", fFlags));
919 STAM_PROFILE_STOP(&CTXMID(pVM->pgm.s.Stat,GstModifyPage), a);
920 return VERR_INVALID_PARAMETER;
921 }
922
923 if (!cb)
924 {
925 AssertFailed();
926 STAM_PROFILE_STOP(&CTXMID(pVM->pgm.s.Stat,GstModifyPage), a);
927 return VERR_INVALID_PARAMETER;
928 }
929
930 LogFlow(("PGMGstModifyPage %VGv %d bytes fFlags=%08llx fMask=%08llx\n", GCPtr, cb, fFlags, fMask));
931
932 /*
933 * Adjust input.
934 */
935 cb += (RTGCUINTPTR)GCPtr & PAGE_OFFSET_MASK;
936 cb = RT_ALIGN_Z(cb, PAGE_SIZE);
937 GCPtr = (RTGCPTR)((RTGCUINTPTR)GCPtr & PAGE_BASE_GC_MASK);
938
939 /*
940 * Call worker.
941 */
942 int rc = PGM_GST_PFN(ModifyPage, pVM)(pVM, (RTGCUINTPTR)GCPtr, cb, fFlags, fMask);
943
944 STAM_PROFILE_STOP(&CTXMID(pVM->pgm.s.Stat,GstModifyPage), a);
945 return rc;
946}
947
948
949/**
950 * Gets the current CR3 register value for the shadow memory context.
951 * @returns CR3 value.
952 * @param pVM The VM handle.
953 */
954PGMDECL(uint32_t) PGMGetHyperCR3(PVM pVM)
955{
956 PGMMODE enmShadowMode = pVM->pgm.s.enmShadowMode;
957 switch (enmShadowMode)
958 {
959 case PGMMODE_32_BIT:
960 return pVM->pgm.s.HCPhys32BitPD;
961
962 case PGMMODE_PAE:
963 case PGMMODE_PAE_NX:
964 return pVM->pgm.s.HCPhysPaePDPT;
965
966 case PGMMODE_AMD64:
967 case PGMMODE_AMD64_NX:
968 return pVM->pgm.s.HCPhysPaePML4;
969
970 case PGMMODE_NESTED:
971 return PGMGetNestedCR3(pVM, PGMGetHostMode(pVM));
972
973 default:
974 AssertMsgFailed(("enmShadowMode=%d\n", enmShadowMode));
975 return ~0;
976 }
977}
978
979/**
980 * Gets the current CR3 register value for the nested memory context.
981 * @returns CR3 value.
982 * @param pVM The VM handle.
983 */
984PGMDECL(uint32_t) PGMGetNestedCR3(PVM pVM, PGMMODE enmShadowMode)
985{
986 switch (enmShadowMode)
987 {
988 case PGMMODE_32_BIT:
989 return pVM->pgm.s.HCPhys32BitPD;
990
991 case PGMMODE_PAE:
992 case PGMMODE_PAE_NX:
993 return pVM->pgm.s.HCPhysPaePDPT;
994
995 case PGMMODE_AMD64:
996 case PGMMODE_AMD64_NX:
997 return pVM->pgm.s.HCPhysPaePML4;
998
999 default:
1000 AssertMsgFailed(("enmShadowMode=%d\n", enmShadowMode));
1001 return ~0;
1002 }
1003}
1004
1005
1006/**
1007 * Gets the CR3 register value for the 32-Bit shadow memory context.
1008 * @returns CR3 value.
1009 * @param pVM The VM handle.
1010 */
1011PGMDECL(uint32_t) PGMGetHyper32BitCR3(PVM pVM)
1012{
1013 return pVM->pgm.s.HCPhys32BitPD;
1014}
1015
1016
1017/**
1018 * Gets the CR3 register value for the PAE shadow memory context.
1019 * @returns CR3 value.
1020 * @param pVM The VM handle.
1021 */
1022PGMDECL(uint32_t) PGMGetHyperPaeCR3(PVM pVM)
1023{
1024 return pVM->pgm.s.HCPhysPaePDPT;
1025}
1026
1027
1028/**
1029 * Gets the CR3 register value for the AMD64 shadow memory context.
1030 * @returns CR3 value.
1031 * @param pVM The VM handle.
1032 */
1033PGMDECL(uint32_t) PGMGetHyperAmd64CR3(PVM pVM)
1034{
1035 return pVM->pgm.s.HCPhysPaePML4;
1036}
1037
1038
1039/**
1040 * Gets the current CR3 register value for the HC intermediate memory context.
1041 * @returns CR3 value.
1042 * @param pVM The VM handle.
1043 */
1044PGMDECL(uint32_t) PGMGetInterHCCR3(PVM pVM)
1045{
1046 switch (pVM->pgm.s.enmHostMode)
1047 {
1048 case SUPPAGINGMODE_32_BIT:
1049 case SUPPAGINGMODE_32_BIT_GLOBAL:
1050 return pVM->pgm.s.HCPhysInterPD;
1051
1052 case SUPPAGINGMODE_PAE:
1053 case SUPPAGINGMODE_PAE_GLOBAL:
1054 case SUPPAGINGMODE_PAE_NX:
1055 case SUPPAGINGMODE_PAE_GLOBAL_NX:
1056 return pVM->pgm.s.HCPhysInterPaePDPT;
1057
1058 case SUPPAGINGMODE_AMD64:
1059 case SUPPAGINGMODE_AMD64_GLOBAL:
1060 case SUPPAGINGMODE_AMD64_NX:
1061 case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1062 return pVM->pgm.s.HCPhysInterPaePDPT;
1063
1064 default:
1065 AssertMsgFailed(("enmHostMode=%d\n", pVM->pgm.s.enmHostMode));
1066 return ~0;
1067 }
1068}
1069
1070
1071/**
1072 * Gets the current CR3 register value for the GC intermediate memory context.
1073 * @returns CR3 value.
1074 * @param pVM The VM handle.
1075 */
1076PGMDECL(uint32_t) PGMGetInterGCCR3(PVM pVM)
1077{
1078 switch (pVM->pgm.s.enmShadowMode)
1079 {
1080 case PGMMODE_32_BIT:
1081 return pVM->pgm.s.HCPhysInterPD;
1082
1083 case PGMMODE_PAE:
1084 case PGMMODE_PAE_NX:
1085 return pVM->pgm.s.HCPhysInterPaePDPT;
1086
1087 case PGMMODE_AMD64:
1088 case PGMMODE_AMD64_NX:
1089 return pVM->pgm.s.HCPhysInterPaePML4;
1090
1091 case PGMMODE_NESTED:
1092 return 0; /* not relevant */
1093
1094 default:
1095 AssertMsgFailed(("enmShadowMode=%d\n", pVM->pgm.s.enmShadowMode));
1096 return ~0;
1097 }
1098}
1099
1100
1101/**
1102 * Gets the CR3 register value for the 32-Bit intermediate memory context.
1103 * @returns CR3 value.
1104 * @param pVM The VM handle.
1105 */
1106PGMDECL(uint32_t) PGMGetInter32BitCR3(PVM pVM)
1107{
1108 return pVM->pgm.s.HCPhysInterPD;
1109}
1110
1111
1112/**
1113 * Gets the CR3 register value for the PAE intermediate memory context.
1114 * @returns CR3 value.
1115 * @param pVM The VM handle.
1116 */
1117PGMDECL(uint32_t) PGMGetInterPaeCR3(PVM pVM)
1118{
1119 return pVM->pgm.s.HCPhysInterPaePDPT;
1120}
1121
1122
1123/**
1124 * Gets the CR3 register value for the AMD64 intermediate memory context.
1125 * @returns CR3 value.
1126 * @param pVM The VM handle.
1127 */
1128PGMDECL(uint32_t) PGMGetInterAmd64CR3(PVM pVM)
1129{
1130 return pVM->pgm.s.HCPhysInterPaePML4;
1131}
1132
1133
1134/**
1135 * Performs and schedules necessary updates following a CR3 load or reload.
1136 *
1137 * This will normally involve mapping the guest PD or nPDPT
1138 *
1139 * @returns VBox status code.
1140 * @retval VINF_PGM_SYNC_CR3 if monitoring requires a CR3 sync. This can
1141 * safely be ignored and overridden since the FF will be set too then.
1142 * @param pVM VM handle.
1143 * @param cr3 The new cr3.
1144 * @param fGlobal Indicates whether this is a global flush or not.
1145 */
1146PGMDECL(int) PGMFlushTLB(PVM pVM, uint64_t cr3, bool fGlobal)
1147{
1148 STAM_PROFILE_START(&pVM->pgm.s.StatFlushTLB, a);
1149
1150 /*
1151 * Always flag the necessary updates; necessary for hardware acceleration
1152 */
1153 VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
1154 if (fGlobal)
1155 VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
1156 LogFlow(("PGMFlushTLB: cr3=%VX64 OldCr3=%VX64 fGlobal=%d\n", cr3, pVM->pgm.s.GCPhysCR3, fGlobal));
1157
1158 /*
1159 * Remap the CR3 content and adjust the monitoring if CR3 was actually changed.
1160 */
1161 int rc = VINF_SUCCESS;
1162 RTGCPHYS GCPhysCR3;
1163 if ( pVM->pgm.s.enmGuestMode == PGMMODE_PAE
1164 || pVM->pgm.s.enmGuestMode == PGMMODE_PAE_NX
1165 || pVM->pgm.s.enmGuestMode == PGMMODE_AMD64
1166 || pVM->pgm.s.enmGuestMode == PGMMODE_AMD64_NX)
1167 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAE_PAGE_MASK);
1168 else
1169 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAGE_MASK);
1170 if (pVM->pgm.s.GCPhysCR3 != GCPhysCR3)
1171 {
1172 pVM->pgm.s.GCPhysCR3 = GCPhysCR3;
1173 rc = PGM_GST_PFN(MapCR3, pVM)(pVM, GCPhysCR3);
1174 if (VBOX_SUCCESS(rc) && !pVM->pgm.s.fMappingsFixed)
1175 {
1176 pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
1177 rc = PGM_GST_PFN(MonitorCR3, pVM)(pVM, GCPhysCR3);
1178 }
1179 if (fGlobal)
1180 STAM_COUNTER_INC(&pVM->pgm.s.StatFlushTLBNewCR3Global);
1181 else
1182 STAM_COUNTER_INC(&pVM->pgm.s.StatFlushTLBNewCR3);
1183 }
1184 else
1185 {
1186 /*
1187 * Check if we have a pending update of the CR3 monitoring.
1188 */
1189 if (pVM->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
1190 {
1191 pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
1192 Assert(!pVM->pgm.s.fMappingsFixed);
1193 rc = PGM_GST_PFN(MonitorCR3, pVM)(pVM, GCPhysCR3);
1194 }
1195 if (fGlobal)
1196 STAM_COUNTER_INC(&pVM->pgm.s.StatFlushTLBSameCR3Global);
1197 else
1198 STAM_COUNTER_INC(&pVM->pgm.s.StatFlushTLBSameCR3);
1199 }
1200
1201 STAM_PROFILE_STOP(&pVM->pgm.s.StatFlushTLB, a);
1202 return rc;
1203}
1204
1205/**
1206 * Performs and schedules necessary updates following a CR3 load or reload,
1207 * without actually the TLB as with PGMFlushTLB.
1208 *
1209 * This will normally involve mapping the guest PD or nPDPT
1210 *
1211 * @returns VBox status code.
1212 * @retval VINF_PGM_SYNC_CR3 if monitoring requires a CR3 sync. This can
1213 * safely be ignored and overridden since the FF will be set too then.
1214 * @param pVM VM handle.
1215 * @param cr3 The new cr3.
1216 */
1217PGMDECL(int) PGMUpdateCR3(PVM pVM, uint64_t cr3)
1218{
1219 LogFlow(("PGMUpdateCR3: cr3=%VX64 OldCr3=%VX64\n", cr3, pVM->pgm.s.GCPhysCR3));
1220
1221 /* We assume we're only called in nested paging mode. */
1222 Assert(pVM->pgm.s.fMappingsFixed);
1223 Assert(!(pVM->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3));
1224 Assert(pVM->pgm.s.enmShadowMode == PGMMODE_NESTED);
1225
1226 /*
1227 * Remap the CR3 content and adjust the monitoring if CR3 was actually changed.
1228 */
1229 int rc = VINF_SUCCESS;
1230 RTGCPHYS GCPhysCR3;
1231 if ( pVM->pgm.s.enmGuestMode == PGMMODE_PAE
1232 || pVM->pgm.s.enmGuestMode == PGMMODE_PAE_NX
1233 || pVM->pgm.s.enmGuestMode == PGMMODE_AMD64
1234 || pVM->pgm.s.enmGuestMode == PGMMODE_AMD64_NX)
1235 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAE_PAGE_MASK);
1236 else
1237 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAGE_MASK);
1238 if (pVM->pgm.s.GCPhysCR3 != GCPhysCR3)
1239 {
1240 pVM->pgm.s.GCPhysCR3 = GCPhysCR3;
1241 rc = PGM_GST_PFN(MapCR3, pVM)(pVM, GCPhysCR3);
1242 }
1243 AssertRC(rc);
1244 return rc;
1245}
1246
1247/**
1248 * Synchronize the paging structures.
1249 *
1250 * This function is called in response to the VM_FF_PGM_SYNC_CR3 and
1251 * VM_FF_PGM_SYNC_CR3_NONGLOBAL. Those two force action flags are set
1252 * in several places, most importantly whenever the CR3 is loaded.
1253 *
1254 * @returns VBox status code.
1255 * @param pVM The virtual machine.
1256 * @param cr0 Guest context CR0 register
1257 * @param cr3 Guest context CR3 register
1258 * @param cr4 Guest context CR4 register
1259 * @param fGlobal Including global page directories or not
1260 */
1261PGMDECL(int) PGMSyncCR3(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
1262{
1263 /*
1264 * We might be called when we shouldn't.
1265 *
1266 * The mode switching will ensure that the PD is resynced
1267 * after every mode switch. So, if we find ourselves here
1268 * when in protected or real mode we can safely disable the
1269 * FF and return immediately.
1270 */
1271 if (pVM->pgm.s.enmGuestMode <= PGMMODE_PROTECTED)
1272 {
1273 Assert((cr0 & (X86_CR0_PG | X86_CR0_PE)) != (X86_CR0_PG | X86_CR0_PE));
1274 VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3);
1275 VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
1276 return VINF_SUCCESS;
1277 }
1278
1279 /* If global pages are not supported, then all flushes are global */
1280 if (!(cr4 & X86_CR4_PGE))
1281 fGlobal = true;
1282 LogFlow(("PGMSyncCR3: cr0=%VX64 cr3=%VX64 cr4=%VX64 fGlobal=%d[%d,%d]\n", cr0, cr3, cr4, fGlobal,
1283 VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3), VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL)));
1284
1285 /*
1286 * Let the 'Bth' function do the work and we'll just keep track of the flags.
1287 */
1288 STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat,SyncCR3), a);
1289 int rc = PGM_BTH_PFN(SyncCR3, pVM)(pVM, cr0, cr3, cr4, fGlobal);
1290 STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncCR3), a);
1291 AssertMsg(rc == VINF_SUCCESS || rc == VINF_PGM_SYNC_CR3 || VBOX_FAILURE(rc), ("rc=%VRc\n", rc));
1292 if (rc == VINF_SUCCESS)
1293 {
1294 if (!(pVM->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS))
1295 {
1296 VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3);
1297 VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
1298 }
1299
1300 /*
1301 * Check if we have a pending update of the CR3 monitoring.
1302 */
1303 if (pVM->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
1304 {
1305 pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
1306 Assert(!pVM->pgm.s.fMappingsFixed);
1307 Assert(pVM->pgm.s.GCPhysCR3 == pVM->pgm.s.GCPhysGstCR3Monitored);
1308 rc = PGM_GST_PFN(MonitorCR3, pVM)(pVM, pVM->pgm.s.GCPhysCR3);
1309 }
1310 }
1311
1312 /*
1313 * Now flush the CR3 (guest context).
1314 */
1315 if (rc == VINF_SUCCESS)
1316 PGM_INVL_GUEST_TLBS();
1317 return rc;
1318}
1319
1320
1321/**
1322 * Called whenever CR0 or CR4 in a way which may change
1323 * the paging mode.
1324 *
1325 * @returns VBox status code fit for scheduling in GC and R0.
1326 * @retval VINF_SUCCESS if the was no change, or it was successfully dealt with.
1327 * @retval VINF_PGM_CHANGE_MODE if we're in GC or R0 and the mode changes.
1328 * @param pVM VM handle.
1329 * @param cr0 The new cr0.
1330 * @param cr4 The new cr4.
1331 * @param efer The new extended feature enable register.
1332 */
1333PGMDECL(int) PGMChangeMode(PVM pVM, uint64_t cr0, uint64_t cr4, uint64_t efer)
1334{
1335 PGMMODE enmGuestMode;
1336
1337 /*
1338 * Calc the new guest mode.
1339 */
1340 if (!(cr0 & X86_CR0_PE))
1341 enmGuestMode = PGMMODE_REAL;
1342 else if (!(cr0 & X86_CR0_PG))
1343 enmGuestMode = PGMMODE_PROTECTED;
1344 else if (!(cr4 & X86_CR4_PAE))
1345 enmGuestMode = PGMMODE_32_BIT;
1346 else if (!(efer & MSR_K6_EFER_LME))
1347 {
1348 if (!(efer & MSR_K6_EFER_NXE))
1349 enmGuestMode = PGMMODE_PAE;
1350 else
1351 enmGuestMode = PGMMODE_PAE_NX;
1352 }
1353 else
1354 {
1355 if (!(efer & MSR_K6_EFER_NXE))
1356 enmGuestMode = PGMMODE_AMD64;
1357 else
1358 enmGuestMode = PGMMODE_AMD64_NX;
1359 }
1360
1361 /*
1362 * Did it change?
1363 */
1364 if (pVM->pgm.s.enmGuestMode == enmGuestMode)
1365 return VINF_SUCCESS;
1366#ifdef IN_RING3
1367 return PGMR3ChangeMode(pVM, enmGuestMode);
1368#else
1369 Log(("PGMChangeMode: returns VINF_PGM_CHANGE_MODE.\n"));
1370 return VINF_PGM_CHANGE_MODE;
1371#endif
1372}
1373
1374
1375/**
1376 * Gets the current guest paging mode.
1377 *
1378 * If you just need the CPU mode (real/protected/long), use CPUMGetGuestMode().
1379 *
1380 * @returns The current paging mode.
1381 * @param pVM The VM handle.
1382 */
1383PGMDECL(PGMMODE) PGMGetGuestMode(PVM pVM)
1384{
1385 return pVM->pgm.s.enmGuestMode;
1386}
1387
1388
1389/**
1390 * Gets the current shadow paging mode.
1391 *
1392 * @returns The current paging mode.
1393 * @param pVM The VM handle.
1394 */
1395PGMDECL(PGMMODE) PGMGetShadowMode(PVM pVM)
1396{
1397 return pVM->pgm.s.enmShadowMode;
1398}
1399
1400/**
1401 * Gets the current host paging mode.
1402 *
1403 * @returns The current paging mode.
1404 * @param pVM The VM handle.
1405 */
1406PGMDECL(PGMMODE) PGMGetHostMode(PVM pVM)
1407{
1408 switch (pVM->pgm.s.enmHostMode)
1409 {
1410 case SUPPAGINGMODE_32_BIT:
1411 case SUPPAGINGMODE_32_BIT_GLOBAL:
1412 return PGMMODE_32_BIT;
1413
1414 case SUPPAGINGMODE_PAE:
1415 case SUPPAGINGMODE_PAE_GLOBAL:
1416 return PGMMODE_PAE;
1417
1418 case SUPPAGINGMODE_PAE_NX:
1419 case SUPPAGINGMODE_PAE_GLOBAL_NX:
1420 return PGMMODE_PAE_NX;
1421
1422 case SUPPAGINGMODE_AMD64:
1423 case SUPPAGINGMODE_AMD64_GLOBAL:
1424 return PGMMODE_AMD64;
1425
1426 case SUPPAGINGMODE_AMD64_NX:
1427 case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1428 return PGMMODE_AMD64_NX;
1429
1430 default: AssertMsgFailed(("enmHostMode=%d\n", pVM->pgm.s.enmHostMode)); break;
1431 }
1432
1433 return PGMMODE_INVALID;
1434}
1435
1436
1437/**
1438 * Get mode name.
1439 *
1440 * @returns read-only name string.
1441 * @param enmMode The mode which name is desired.
1442 */
1443PGMDECL(const char *) PGMGetModeName(PGMMODE enmMode)
1444{
1445 switch (enmMode)
1446 {
1447 case PGMMODE_REAL: return "real";
1448 case PGMMODE_PROTECTED: return "protected";
1449 case PGMMODE_32_BIT: return "32-bit";
1450 case PGMMODE_PAE: return "PAE";
1451 case PGMMODE_PAE_NX: return "PAE+NX";
1452 case PGMMODE_AMD64: return "AMD64";
1453 case PGMMODE_AMD64_NX: return "AMD64+NX";
1454 default: return "unknown mode value";
1455 }
1456}
1457
1458
1459/**
1460 * Acquire the PGM lock.
1461 *
1462 * @returns VBox status code
1463 * @param pVM The VM to operate on.
1464 */
1465int pgmLock(PVM pVM)
1466{
1467 int rc = PDMCritSectEnter(&pVM->pgm.s.CritSect, VERR_SEM_BUSY);
1468#ifdef IN_GC
1469 if (rc == VERR_SEM_BUSY)
1470 rc = VMMGCCallHost(pVM, VMMCALLHOST_PGM_LOCK, 0);
1471#elif defined(IN_RING0)
1472 if (rc == VERR_SEM_BUSY)
1473 rc = VMMR0CallHost(pVM, VMMCALLHOST_PGM_LOCK, 0);
1474#endif
1475 AssertRC(rc);
1476 return rc;
1477}
1478
1479
1480/**
1481 * Release the PGM lock.
1482 *
1483 * @returns VBox status code
1484 * @param pVM The VM to operate on.
1485 */
1486void pgmUnlock(PVM pVM)
1487{
1488 PDMCritSectLeave(&pVM->pgm.s.CritSect);
1489}
1490
1491
1492#ifdef VBOX_STRICT
1493
1494/**
1495 * Asserts that there are no mapping conflicts.
1496 *
1497 * @returns Number of conflicts.
1498 * @param pVM The VM Handle.
1499 */
1500PGMDECL(unsigned) PGMAssertNoMappingConflicts(PVM pVM)
1501{
1502 unsigned cErrors = 0;
1503
1504 /*
1505 * Check for mapping conflicts.
1506 */
1507 for (PPGMMAPPING pMapping = CTXALLSUFF(pVM->pgm.s.pMappings);
1508 pMapping;
1509 pMapping = CTXALLSUFF(pMapping->pNext))
1510 {
1511 /** @todo This is slow and should be optimized, but since it's just assertions I don't care now. */
1512 for (RTGCUINTPTR GCPtr = (RTGCUINTPTR)pMapping->GCPtr;
1513 GCPtr <= (RTGCUINTPTR)pMapping->GCPtrLast;
1514 GCPtr += PAGE_SIZE)
1515 {
1516 int rc = PGMGstGetPage(pVM, (RTGCPTR)GCPtr, NULL, NULL);
1517 if (rc != VERR_PAGE_TABLE_NOT_PRESENT)
1518 {
1519 AssertMsgFailed(("Conflict at %VGv with %s\n", GCPtr, HCSTRING(pMapping->pszDesc)));
1520 cErrors++;
1521 break;
1522 }
1523 }
1524 }
1525
1526 return cErrors;
1527}
1528
1529
1530/**
1531 * Asserts that everything related to the guest CR3 is correctly shadowed.
1532 *
1533 * This will call PGMAssertNoMappingConflicts() and PGMAssertHandlerAndFlagsInSync(),
1534 * and assert the correctness of the guest CR3 mapping before asserting that the
1535 * shadow page tables is in sync with the guest page tables.
1536 *
1537 * @returns Number of conflicts.
1538 * @param pVM The VM Handle.
1539 * @param cr3 The current guest CR3 register value.
1540 * @param cr4 The current guest CR4 register value.
1541 */
1542PGMDECL(unsigned) PGMAssertCR3(PVM pVM, uint64_t cr3, uint64_t cr4)
1543{
1544 STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat,SyncCR3), a);
1545 unsigned cErrors = PGM_BTH_PFN(AssertCR3, pVM)(pVM, cr3, cr4, 0, ~(RTGCUINTPTR)0);
1546 STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncCR3), a);
1547 return cErrors;
1548 return 0;
1549}
1550
1551#endif /* VBOX_STRICT */
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