VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAll.cpp@ 9893

Last change on this file since 9893 was 9893, checked in by vboxsync, 16 years ago

Attempt to fix PAE (can't verify now).
AMD64 paging updates.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id
File size: 50.8 KB
Line 
1/* $Id: PGMAll.cpp 9893 2008-06-24 15:56:57Z vboxsync $ */
2/** @file
3 * PGM - Page Manager and Monitor - All context code.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22/*******************************************************************************
23* Header Files *
24*******************************************************************************/
25#define LOG_GROUP LOG_GROUP_PGM
26#include <VBox/pgm.h>
27#include <VBox/cpum.h>
28#include <VBox/selm.h>
29#include <VBox/iom.h>
30#include <VBox/sup.h>
31#include <VBox/mm.h>
32#include <VBox/stam.h>
33#include <VBox/csam.h>
34#include <VBox/patm.h>
35#include <VBox/trpm.h>
36#include <VBox/rem.h>
37#include <VBox/em.h>
38#include <VBox/hwaccm.h>
39#include "PGMInternal.h"
40#include <VBox/vm.h>
41#include <iprt/assert.h>
42#include <iprt/asm.h>
43#include <iprt/string.h>
44#include <VBox/log.h>
45#include <VBox/param.h>
46#include <VBox/err.h>
47
48
49/*******************************************************************************
50* Structures and Typedefs *
51*******************************************************************************/
52/**
53 * Stated structure for PGM_GST_NAME(HandlerVirtualUpdate) that's
54 * passed to PGM_GST_NAME(VirtHandlerUpdateOne) during enumeration.
55 */
56typedef struct PGMHVUSTATE
57{
58 /** The VM handle. */
59 PVM pVM;
60 /** The todo flags. */
61 RTUINT fTodo;
62 /** The CR4 register value. */
63 uint32_t cr4;
64} PGMHVUSTATE, *PPGMHVUSTATE;
65
66
67/*******************************************************************************
68* Internal Functions *
69*******************************************************************************/
70
71/*
72 * Shadow - 32-bit mode
73 */
74#define PGM_SHW_TYPE PGM_TYPE_32BIT
75#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
76#include "PGMAllShw.h"
77
78/* Guest - real mode */
79#define PGM_GST_TYPE PGM_TYPE_REAL
80#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
81#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
82#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
83#include "PGMAllGst.h"
84#include "PGMAllBth.h"
85#undef BTH_PGMPOOLKIND_PT_FOR_PT
86#undef PGM_BTH_NAME
87#undef PGM_GST_TYPE
88#undef PGM_GST_NAME
89
90/* Guest - protected mode */
91#define PGM_GST_TYPE PGM_TYPE_PROT
92#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
93#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
94#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
95#include "PGMAllGst.h"
96#include "PGMAllBth.h"
97#undef BTH_PGMPOOLKIND_PT_FOR_PT
98#undef PGM_BTH_NAME
99#undef PGM_GST_TYPE
100#undef PGM_GST_NAME
101
102/* Guest - 32-bit mode */
103#define PGM_GST_TYPE PGM_TYPE_32BIT
104#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
105#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
106#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
107#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
108#include "PGMAllGst.h"
109#include "PGMAllBth.h"
110#undef BTH_PGMPOOLKIND_PT_FOR_BIG
111#undef BTH_PGMPOOLKIND_PT_FOR_PT
112#undef PGM_BTH_NAME
113#undef PGM_GST_TYPE
114#undef PGM_GST_NAME
115
116#undef PGM_SHW_TYPE
117#undef PGM_SHW_NAME
118
119
120/*
121 * Shadow - PAE mode
122 */
123#define PGM_SHW_TYPE PGM_TYPE_PAE
124#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
125#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
126#include "PGMAllShw.h"
127
128/* Guest - real mode */
129#define PGM_GST_TYPE PGM_TYPE_REAL
130#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
131#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
132#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
133#include "PGMAllBth.h"
134#undef BTH_PGMPOOLKIND_PT_FOR_PT
135#undef PGM_BTH_NAME
136#undef PGM_GST_TYPE
137#undef PGM_GST_NAME
138
139/* Guest - protected mode */
140#define PGM_GST_TYPE PGM_TYPE_PROT
141#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
142#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
143#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
144#include "PGMAllBth.h"
145#undef BTH_PGMPOOLKIND_PT_FOR_PT
146#undef PGM_BTH_NAME
147#undef PGM_GST_TYPE
148#undef PGM_GST_NAME
149
150/* Guest - 32-bit mode */
151#define PGM_GST_TYPE PGM_TYPE_32BIT
152#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
153#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
154#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
155#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
156#include "PGMAllBth.h"
157#undef BTH_PGMPOOLKIND_PT_FOR_BIG
158#undef BTH_PGMPOOLKIND_PT_FOR_PT
159#undef PGM_BTH_NAME
160#undef PGM_GST_TYPE
161#undef PGM_GST_NAME
162
163
164/* Guest - PAE mode */
165#define PGM_GST_TYPE PGM_TYPE_PAE
166#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
167#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
168#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
169#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
170#include "PGMAllGst.h"
171#include "PGMAllBth.h"
172#undef BTH_PGMPOOLKIND_PT_FOR_BIG
173#undef BTH_PGMPOOLKIND_PT_FOR_PT
174#undef PGM_BTH_NAME
175#undef PGM_GST_TYPE
176#undef PGM_GST_NAME
177
178#undef PGM_SHW_TYPE
179#undef PGM_SHW_NAME
180
181
182#ifndef IN_GC /* AMD64 implies VT-x/AMD-V */
183/*
184 * Shadow - AMD64 mode
185 */
186#define PGM_SHW_TYPE PGM_TYPE_AMD64
187#define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
188#include "PGMAllShw.h"
189
190/* Guest - protected mode */
191#define PGM_GST_TYPE PGM_TYPE_PROT
192#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
193#define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_PROT(name)
194#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
195#include "PGMAllBth.h"
196#undef BTH_PGMPOOLKIND_PT_FOR_PT
197#undef PGM_BTH_NAME
198#undef PGM_GST_TYPE
199#undef PGM_GST_NAME
200
201/* Guest - AMD64 mode */
202#define PGM_GST_TYPE PGM_TYPE_AMD64
203#define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
204#define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
205#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
206#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
207#include "PGMAllGst.h"
208#include "PGMAllBth.h"
209#undef BTH_PGMPOOLKIND_PT_FOR_BIG
210#undef BTH_PGMPOOLKIND_PT_FOR_PT
211#undef PGM_BTH_NAME
212#undef PGM_GST_TYPE
213#undef PGM_GST_NAME
214
215#undef PGM_SHW_TYPE
216#undef PGM_SHW_NAME
217
218/*
219 * Shadow - Nested paging mode
220 */
221#define PGM_SHW_TYPE PGM_TYPE_NESTED
222#define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED(name)
223#include "PGMAllShw.h"
224
225/* Guest - real mode */
226#define PGM_GST_TYPE PGM_TYPE_REAL
227#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
228#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_REAL(name)
229#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
230#include "PGMAllBth.h"
231#undef BTH_PGMPOOLKIND_PT_FOR_PT
232#undef PGM_BTH_NAME
233#undef PGM_GST_TYPE
234#undef PGM_GST_NAME
235
236/* Guest - protected mode */
237#define PGM_GST_TYPE PGM_TYPE_PROT
238#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
239#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PROT(name)
240#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
241#include "PGMAllBth.h"
242#undef BTH_PGMPOOLKIND_PT_FOR_PT
243#undef PGM_BTH_NAME
244#undef PGM_GST_TYPE
245#undef PGM_GST_NAME
246
247/* Guest - 32-bit mode */
248#define PGM_GST_TYPE PGM_TYPE_32BIT
249#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
250#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT(name)
251#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
252#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
253#include "PGMAllBth.h"
254#undef BTH_PGMPOOLKIND_PT_FOR_BIG
255#undef BTH_PGMPOOLKIND_PT_FOR_PT
256#undef PGM_BTH_NAME
257#undef PGM_GST_TYPE
258#undef PGM_GST_NAME
259
260/* Guest - PAE mode */
261#define PGM_GST_TYPE PGM_TYPE_PAE
262#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
263#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE(name)
264#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
265#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
266#include "PGMAllBth.h"
267#undef BTH_PGMPOOLKIND_PT_FOR_BIG
268#undef BTH_PGMPOOLKIND_PT_FOR_PT
269#undef PGM_BTH_NAME
270#undef PGM_GST_TYPE
271#undef PGM_GST_NAME
272
273/* Guest - AMD64 mode */
274#define PGM_GST_TYPE PGM_TYPE_AMD64
275#define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
276#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64(name)
277#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
278#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
279#include "PGMAllBth.h"
280#undef BTH_PGMPOOLKIND_PT_FOR_BIG
281#undef BTH_PGMPOOLKIND_PT_FOR_PT
282#undef PGM_BTH_NAME
283#undef PGM_GST_TYPE
284#undef PGM_GST_NAME
285
286#undef PGM_SHW_TYPE
287#undef PGM_SHW_NAME
288#endif
289
290/**
291 * #PF Handler.
292 *
293 * @returns VBox status code (appropriate for trap handling and GC return).
294 * @param pVM VM Handle.
295 * @param uErr The trap error code.
296 * @param pRegFrame Trap register frame.
297 * @param pvFault The fault address.
298 */
299PGMDECL(int) PGMTrap0eHandler(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
300{
301 LogFlow(("PGMTrap0eHandler: uErr=%#x pvFault=%VGv eip=%VGv\n", (uint32_t)uErr, pvFault, pRegFrame->rip));
302 STAM_PROFILE_START(&pVM->pgm.s.StatGCTrap0e, a);
303 STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = NULL; } );
304
305
306#ifdef VBOX_WITH_STATISTICS
307 /*
308 * Error code stats.
309 */
310 if (uErr & X86_TRAP_PF_US)
311 {
312 if (!(uErr & X86_TRAP_PF_P))
313 {
314 if (uErr & X86_TRAP_PF_RW)
315 STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eUSNotPresentWrite);
316 else
317 STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eUSNotPresentRead);
318 }
319 else if (uErr & X86_TRAP_PF_RW)
320 STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eUSWrite);
321 else if (uErr & X86_TRAP_PF_RSVD)
322 STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eUSReserved);
323 else if (uErr & X86_TRAP_PF_ID)
324 STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eUSNXE);
325 else
326 STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eUSRead);
327 }
328 else
329 { /* Supervisor */
330 if (!(uErr & X86_TRAP_PF_P))
331 {
332 if (uErr & X86_TRAP_PF_RW)
333 STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eSVNotPresentWrite);
334 else
335 STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eSVNotPresentRead);
336 }
337 else if (uErr & X86_TRAP_PF_RW)
338 STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eSVWrite);
339 else if (uErr & X86_TRAP_PF_ID)
340 STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eSNXE);
341 else if (uErr & X86_TRAP_PF_RSVD)
342 STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eSVReserved);
343 }
344#endif
345
346 /*
347 * Call the worker.
348 */
349 int rc = PGM_BTH_PFN(Trap0eHandler, pVM)(pVM, uErr, pRegFrame, pvFault);
350 if (rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
351 rc = VINF_SUCCESS;
352 STAM_STATS({ if (!pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution))
353 pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eMisc; });
354 STAM_PROFILE_STOP_EX(&pVM->pgm.s.StatGCTrap0e, pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution), a);
355 return rc;
356}
357
358/**
359 * Prefetch a page
360 *
361 * Typically used to sync commonly used pages before entering raw mode
362 * after a CR3 reload.
363 *
364 * @returns VBox status code suitable for scheduling.
365 * @retval VINF_SUCCESS on success.
366 * @retval VINF_PGM_SYNC_CR3 if we're out of shadow pages or something like that.
367 * @param pVM VM handle.
368 * @param GCPtrPage Page to invalidate.
369 */
370PGMDECL(int) PGMPrefetchPage(PVM pVM, RTGCPTR GCPtrPage)
371{
372 STAM_PROFILE_START(&pVM->pgm.s.StatHCPrefetch, a);
373 int rc = PGM_BTH_PFN(PrefetchPage, pVM)(pVM, (RTGCUINTPTR)GCPtrPage);
374 STAM_PROFILE_STOP(&pVM->pgm.s.StatHCPrefetch, a);
375 AssertMsg(rc == VINF_SUCCESS || rc == VINF_PGM_SYNC_CR3 || VBOX_FAILURE(rc), ("rc=%Vrc\n", rc));
376 return rc;
377}
378
379
380/**
381 * Gets the mapping corresponding to the specified address (if any).
382 *
383 * @returns Pointer to the mapping.
384 * @returns NULL if not
385 *
386 * @param pVM The virtual machine.
387 * @param GCPtr The guest context pointer.
388 */
389PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr)
390{
391 PPGMMAPPING pMapping = CTXALLSUFF(pVM->pgm.s.pMappings);
392 while (pMapping)
393 {
394 if ((uintptr_t)GCPtr < (uintptr_t)pMapping->GCPtr)
395 break;
396 if ((uintptr_t)GCPtr - (uintptr_t)pMapping->GCPtr < pMapping->cb)
397 {
398 STAM_COUNTER_INC(&pVM->pgm.s.StatGCSyncPTConflict);
399 return pMapping;
400 }
401 pMapping = CTXALLSUFF(pMapping->pNext);
402 }
403 return NULL;
404}
405
406
407/**
408 * Verifies a range of pages for read or write access
409 *
410 * Only checks the guest's page tables
411 *
412 * @returns VBox status code.
413 * @param pVM VM handle.
414 * @param Addr Guest virtual address to check
415 * @param cbSize Access size
416 * @param fAccess Access type (r/w, user/supervisor (X86_PTE_*))
417 */
418PGMDECL(int) PGMIsValidAccess(PVM pVM, RTGCUINTPTR Addr, uint32_t cbSize, uint32_t fAccess)
419{
420 /*
421 * Validate input.
422 */
423 if (fAccess & ~(X86_PTE_US | X86_PTE_RW))
424 {
425 AssertMsgFailed(("PGMIsValidAccess: invalid access type %08x\n", fAccess));
426 return VERR_INVALID_PARAMETER;
427 }
428
429 uint64_t fPage;
430 int rc = PGMGstGetPage(pVM, (RTGCPTR)Addr, &fPage, NULL);
431 if (VBOX_FAILURE(rc))
432 {
433 Log(("PGMIsValidAccess: access violation for %VGv rc=%d\n", Addr, rc));
434 return VINF_EM_RAW_GUEST_TRAP;
435 }
436
437 /*
438 * Check if the access would cause a page fault
439 *
440 * Note that hypervisor page directories are not present in the guest's tables, so this check
441 * is sufficient.
442 */
443 bool fWrite = !!(fAccess & X86_PTE_RW);
444 bool fUser = !!(fAccess & X86_PTE_US);
445 if ( !(fPage & X86_PTE_P)
446 || (fWrite && !(fPage & X86_PTE_RW))
447 || (fUser && !(fPage & X86_PTE_US)) )
448 {
449 Log(("PGMIsValidAccess: access violation for %VGv attr %#llx vs %d:%d\n", Addr, fPage, fWrite, fUser));
450 return VINF_EM_RAW_GUEST_TRAP;
451 }
452 if ( VBOX_SUCCESS(rc)
453 && PAGE_ADDRESS(Addr) != PAGE_ADDRESS(Addr + cbSize))
454 return PGMIsValidAccess(pVM, Addr + PAGE_SIZE, (cbSize > PAGE_SIZE) ? cbSize - PAGE_SIZE : 1, fAccess);
455 return rc;
456}
457
458
459/**
460 * Verifies a range of pages for read or write access
461 *
462 * Supports handling of pages marked for dirty bit tracking and CSAM
463 *
464 * @returns VBox status code.
465 * @param pVM VM handle.
466 * @param Addr Guest virtual address to check
467 * @param cbSize Access size
468 * @param fAccess Access type (r/w, user/supervisor (X86_PTE_*))
469 */
470PGMDECL(int) PGMVerifyAccess(PVM pVM, RTGCUINTPTR Addr, uint32_t cbSize, uint32_t fAccess)
471{
472 /*
473 * Validate input.
474 */
475 if (fAccess & ~(X86_PTE_US | X86_PTE_RW))
476 {
477 AssertMsgFailed(("PGMVerifyAccess: invalid access type %08x\n", fAccess));
478 return VERR_INVALID_PARAMETER;
479 }
480
481 uint64_t fPageGst;
482 int rc = PGMGstGetPage(pVM, (RTGCPTR)Addr, &fPageGst, NULL);
483 if (VBOX_FAILURE(rc))
484 {
485 Log(("PGMVerifyAccess: access violation for %VGv rc=%d\n", Addr, rc));
486 return VINF_EM_RAW_GUEST_TRAP;
487 }
488
489 /*
490 * Check if the access would cause a page fault
491 *
492 * Note that hypervisor page directories are not present in the guest's tables, so this check
493 * is sufficient.
494 */
495 const bool fWrite = !!(fAccess & X86_PTE_RW);
496 const bool fUser = !!(fAccess & X86_PTE_US);
497 if ( !(fPageGst & X86_PTE_P)
498 || (fWrite && !(fPageGst & X86_PTE_RW))
499 || (fUser && !(fPageGst & X86_PTE_US)) )
500 {
501 Log(("PGMVerifyAccess: access violation for %VGv attr %#llx vs %d:%d\n", Addr, fPageGst, fWrite, fUser));
502 return VINF_EM_RAW_GUEST_TRAP;
503 }
504
505 if (!HWACCMIsNestedPagingActive(pVM))
506 {
507 /*
508 * Next step is to verify if we protected this page for dirty bit tracking or for CSAM scanning
509 */
510 rc = PGMShwGetPage(pVM, (RTGCPTR)Addr, NULL, NULL);
511 if ( rc == VERR_PAGE_NOT_PRESENT
512 || rc == VERR_PAGE_TABLE_NOT_PRESENT)
513 {
514 /*
515 * Page is not present in our page tables.
516 * Try to sync it!
517 */
518 Assert(X86_TRAP_PF_RW == X86_PTE_RW && X86_TRAP_PF_US == X86_PTE_US);
519 uint32_t uErr = fAccess & (X86_TRAP_PF_RW | X86_TRAP_PF_US);
520 rc = PGM_BTH_PFN(VerifyAccessSyncPage, pVM)(pVM, Addr, fPageGst, uErr);
521 if (rc != VINF_SUCCESS)
522 return rc;
523 }
524 else
525 AssertMsg(rc == VINF_SUCCESS, ("PGMShwGetPage %VGv failed with %Vrc\n", Addr, rc));
526 }
527
528#if 0 /* def VBOX_STRICT; triggers too often now */
529 /*
530 * This check is a bit paranoid, but useful.
531 */
532 /** @note this will assert when writing to monitored pages (a bit annoying actually) */
533 uint64_t fPageShw;
534 rc = PGMShwGetPage(pVM, (RTGCPTR)Addr, &fPageShw, NULL);
535 if ( (rc == VERR_PAGE_NOT_PRESENT || VBOX_FAILURE(rc))
536 || (fWrite && !(fPageShw & X86_PTE_RW))
537 || (fUser && !(fPageShw & X86_PTE_US)) )
538 {
539 AssertMsgFailed(("Unexpected access violation for %VGv! rc=%Vrc write=%d user=%d\n",
540 Addr, rc, fWrite && !(fPageShw & X86_PTE_RW), fUser && !(fPageShw & X86_PTE_US)));
541 return VINF_EM_RAW_GUEST_TRAP;
542 }
543#endif
544
545 if ( VBOX_SUCCESS(rc)
546 && ( PAGE_ADDRESS(Addr) != PAGE_ADDRESS(Addr + cbSize - 1)
547 || Addr + cbSize < Addr))
548 {
549 /* Don't recursively call PGMVerifyAccess as we might run out of stack. */
550 for (;;)
551 {
552 Addr += PAGE_SIZE;
553 if (cbSize > PAGE_SIZE)
554 cbSize -= PAGE_SIZE;
555 else
556 cbSize = 1;
557 rc = PGMVerifyAccess(pVM, Addr, 1, fAccess);
558 if (rc != VINF_SUCCESS)
559 break;
560 if (PAGE_ADDRESS(Addr) == PAGE_ADDRESS(Addr + cbSize - 1))
561 break;
562 }
563 }
564 return rc;
565}
566
567
568#ifndef IN_GC
569/**
570 * Emulation of the invlpg instruction (HC only actually).
571 *
572 * @returns VBox status code.
573 * @param pVM VM handle.
574 * @param GCPtrPage Page to invalidate.
575 * @remark ASSUMES the page table entry or page directory is
576 * valid. Fairly safe, but there could be edge cases!
577 * @todo Flush page or page directory only if necessary!
578 */
579PGMDECL(int) PGMInvalidatePage(PVM pVM, RTGCPTR GCPtrPage)
580{
581 int rc;
582
583 Log2(("PGMInvalidatePage: GCPtrPage=%VGv\n", GCPtrPage));
584
585 /** @todo merge PGMGCInvalidatePage with this one */
586
587#ifndef IN_RING3
588 /*
589 * Notify the recompiler so it can record this instruction.
590 * Failure happens when it's out of space. We'll return to HC in that case.
591 */
592 rc = REMNotifyInvalidatePage(pVM, GCPtrPage);
593 if (VBOX_FAILURE(rc))
594 return rc;
595#endif
596
597 STAM_PROFILE_START(&CTXMID(pVM->pgm.s.Stat,InvalidatePage), a);
598 rc = PGM_BTH_PFN(InvalidatePage, pVM)(pVM, GCPtrPage);
599 STAM_PROFILE_STOP(&CTXMID(pVM->pgm.s.Stat,InvalidatePage), a);
600
601#ifndef IN_RING0
602 /*
603 * Check if we have a pending update of the CR3 monitoring.
604 */
605 if ( VBOX_SUCCESS(rc)
606 && (pVM->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3))
607 {
608 pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
609 Assert(!pVM->pgm.s.fMappingsFixed);
610 Assert(pVM->pgm.s.GCPhysCR3 == pVM->pgm.s.GCPhysGstCR3Monitored);
611 rc = PGM_GST_PFN(MonitorCR3, pVM)(pVM, pVM->pgm.s.GCPhysCR3);
612 }
613#endif
614
615#ifdef IN_RING3
616 /*
617 * Inform CSAM about the flush
618 */
619 /** @note this is to check if monitored pages have been changed; when we implement callbacks for virtual handlers, this is no longer required. */
620 CSAMR3FlushPage(pVM, GCPtrPage);
621#endif
622 return rc;
623}
624#endif
625
626
627/**
628 * Executes an instruction using the interpreter.
629 *
630 * @returns VBox status code (appropriate for trap handling and GC return).
631 * @param pVM VM handle.
632 * @param pRegFrame Register frame.
633 * @param pvFault Fault address.
634 */
635PGMDECL(int) PGMInterpretInstruction(PVM pVM, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
636{
637 uint32_t cb;
638 int rc = EMInterpretInstruction(pVM, pRegFrame, pvFault, &cb);
639 if (rc == VERR_EM_INTERPRETER)
640 rc = VINF_EM_RAW_EMULATE_INSTR;
641 if (rc != VINF_SUCCESS)
642 Log(("PGMInterpretInstruction: returns %Rrc (pvFault=%VGv)\n", rc, pvFault));
643 return rc;
644}
645
646
647/**
648 * Gets effective page information (from the VMM page directory).
649 *
650 * @returns VBox status.
651 * @param pVM VM Handle.
652 * @param GCPtr Guest Context virtual address of the page.
653 * @param pfFlags Where to store the flags. These are X86_PTE_*.
654 * @param pHCPhys Where to store the HC physical address of the page.
655 * This is page aligned.
656 * @remark You should use PGMMapGetPage() for pages in a mapping.
657 */
658PGMDECL(int) PGMShwGetPage(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys)
659{
660 return PGM_SHW_PFN(GetPage,pVM)(pVM, (RTGCUINTPTR)GCPtr, pfFlags, pHCPhys);
661}
662
663
664/**
665 * Sets (replaces) the page flags for a range of pages in the shadow context.
666 *
667 * @returns VBox status.
668 * @param pVM VM handle.
669 * @param GCPtr The address of the first page.
670 * @param cb The size of the range in bytes.
671 * @param fFlags Page flags X86_PTE_*, excluding the page mask of course.
672 * @remark You must use PGMMapSetPage() for pages in a mapping.
673 */
674PGMDECL(int) PGMShwSetPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags)
675{
676 return PGMShwModifyPage(pVM, GCPtr, cb, fFlags, 0);
677}
678
679
680/**
681 * Modify page flags for a range of pages in the shadow context.
682 *
683 * The existing flags are ANDed with the fMask and ORed with the fFlags.
684 *
685 * @returns VBox status code.
686 * @param pVM VM handle.
687 * @param GCPtr Virtual address of the first page in the range.
688 * @param cb Size (in bytes) of the range to apply the modification to.
689 * @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
690 * @param fMask The AND mask - page flags X86_PTE_*.
691 * Be very CAREFUL when ~'ing constants which could be 32-bit!
692 * @remark You must use PGMMapModifyPage() for pages in a mapping.
693 */
694PGMDECL(int) PGMShwModifyPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
695{
696 /*
697 * Validate input.
698 */
699 if (fFlags & X86_PTE_PAE_PG_MASK)
700 {
701 AssertMsgFailed(("fFlags=%#llx\n", fFlags));
702 return VERR_INVALID_PARAMETER;
703 }
704 if (!cb)
705 {
706 AssertFailed();
707 return VERR_INVALID_PARAMETER;
708 }
709
710 /*
711 * Align the input.
712 */
713 cb += (RTGCUINTPTR)GCPtr & PAGE_OFFSET_MASK;
714 cb = RT_ALIGN_Z(cb, PAGE_SIZE);
715 GCPtr = (RTGCPTR)((RTGCUINTPTR)GCPtr & PAGE_BASE_GC_MASK); /** @todo this ain't necessary, right... */
716
717 /*
718 * Call worker.
719 */
720 return PGM_SHW_PFN(ModifyPage, pVM)(pVM, (RTGCUINTPTR)GCPtr, cb, fFlags, fMask);
721}
722
723/**
724 * Syncs the SHADOW page directory pointer for the specified address. Allocates
725 * backing pages in case the PDPT entry is missing.
726 *
727 * @returns VBox status.
728 * @param pVM VM handle.
729 * @param GCPtr The address.
730 * @param pGstPdpe Guest PDPT entry
731 * @param ppPD Receives address of page directory
732 */
733PGMDECL(int) PGMShwSyncPAEPDPtr(PVM pVM, RTGCUINTPTR GCPtr, PX86PDPE pGstPdpe, PX86PDPAE *ppPD)
734{
735 PPGM pPGM = &pVM->pgm.s;
736 PPGMPOOL pPool = pPGM->CTXSUFF(pPool);
737 PPGMPOOLPAGE pShwPage;
738 int rc;
739
740 Assert(!HWACCMIsNestedPagingActive(pVM));
741
742 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
743 PX86PDPT pPdpt = pVM->pgm.s.CTXMID(p,PaePDPT);
744 PX86PDPE pPdpe = &pPdpt->a[iPdPt];
745
746 /* Allocate page directory if not present. */
747 if ( !pPdpe->n.u1Present
748 && !(pPdpe->u & X86_PDPE_PG_MASK))
749 {
750 PX86PDPE pPdptGst = &CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt];
751
752 Assert(!(pPdpe->u & X86_PDPE_PG_MASK));
753 /* Create a reference back to the PDPT by using the index in its shadow page. */
754 rc = pgmPoolAlloc(pVM, pPdptGst->u & X86_PDPE_PG_MASK, PGMPOOLKIND_PAE_PD_FOR_PAE_PD, PGMPOOL_IDX_PDPT, iPdPt, &pShwPage);
755 if (rc == VERR_PGM_POOL_FLUSHED)
756 return VINF_PGM_SYNC_CR3;
757
758 AssertRCReturn(rc, rc);
759 }
760 else
761 {
762 pShwPage = pgmPoolGetPage(pPool, pPdpe->u & X86_PDPE_PG_MASK);
763 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
764 }
765 /* The PD was cached or created; hook it up now. */
766 pPdpe->u |= pShwPage->Core.Key
767 | (pGstPdpe->u & ~(X86_PDPE_PG_MASK | X86_PDPE_AVL_MASK | X86_PDPE_PCD | X86_PDPE_PWT));
768
769 *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
770 return VINF_SUCCESS;
771}
772
773/**
774 * Gets the SHADOW page directory pointer for the specified address.
775 *
776 * @returns VBox status.
777 * @param pVM VM handle.
778 * @param GCPtr The address.
779 * @param ppPdpt Receives address of pdpt
780 * @param ppPD Receives address of page directory
781 */
782PGMDECL(int) PGMShwGetPAEPDPtr(PVM pVM, RTGCUINTPTR GCPtr, PX86PDPT *ppPdpt, PX86PDPAE *ppPD)
783{
784 PPGM pPGM = &pVM->pgm.s;
785 PPGMPOOL pPool = pPGM->CTXSUFF(pPool);
786 PPGMPOOLPAGE pShwPage;
787
788 Assert(!HWACCMIsNestedPagingActive(pVM));
789
790 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
791 PX86PDPT pPdpt = pVM->pgm.s.CTXMID(p,PaePDPT);
792 PX86PDPE pPdpe = &pPdpt->a[iPdPt];
793
794 *ppPdpt = pPdpt;
795 if (!pPdpe->n.u1Present)
796 return VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT;
797
798 pShwPage = pgmPoolGetPage(pPool, pPdpe->u & X86_PDPE_PG_MASK);
799 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
800
801 *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
802 return VINF_SUCCESS;
803}
804
805#ifndef IN_GC
806/**
807 * Syncs the SHADOW page directory pointer for the specified address. Allocates
808 * backing pages in case the PDPT or PML4 entry is missing.
809 *
810 * @returns VBox status.
811 * @param pVM VM handle.
812 * @param GCPtr The address.
813 * @param pGstPml4e Guest PML4 entry
814 * @param pGstPdpe Guest PDPT entry
815 * @param ppPD Receives address of page directory
816 */
817PGMDECL(int) PGMShwSyncLongModePDPtr(PVM pVM, RTGCUINTPTR64 GCPtr, PX86PML4E pGstPml4e, PX86PDPE pGstPdpe, PX86PDPAE *ppPD)
818{
819 PPGM pPGM = &pVM->pgm.s;
820 const unsigned iPml4e = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
821 PPGMPOOL pPool = pPGM->CTXSUFF(pPool);
822 PX86PML4E pPml4e;
823 PPGMPOOLPAGE pShwPage;
824 int rc;
825
826 Assert(!HWACCMIsNestedPagingActive(pVM));
827 AssertReturn(pVM->pgm.s.pHCPaePML4, VERR_INTERNAL_ERROR);
828
829 Assert(pVM->pgm.s.pHCPaePML4);
830 /* Allocate page directory pointer table if not present. */
831 pPml4e = &pPGM->pHCPaePML4->a[iPml4e];
832 if ( !pPml4e->n.u1Present
833 && !(pPml4e->u & X86_PML4E_PG_MASK))
834 {
835 PX86PML4E pPml4eGst = &pPGM->pGstPaePML4HC->a[iPml4e];
836
837 Assert(!(pPml4e->u & X86_PML4E_PG_MASK));
838 rc = pgmPoolAlloc(pVM, pPml4eGst->u & X86_PML4E_PG_MASK, PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT, pVM->pgm.s.pShwAmd64CR3->idx, iPml4e, &pShwPage);
839 if (rc == VERR_PGM_POOL_FLUSHED)
840 return VINF_PGM_SYNC_CR3;
841
842 AssertRCReturn(rc, rc);
843 }
844 else
845 {
846 pShwPage = pgmPoolGetPage(pPool, pPml4e->u & X86_PML4E_PG_MASK);
847 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
848 }
849 /* The PDPT was cached or created; hook it up now. */
850 pPml4e->u |= pShwPage->Core.Key
851 | (pGstPml4e->u & ~(X86_PML4E_PG_MASK | X86_PML4E_AVL_MASK | X86_PML4E_PCD | X86_PML4E_PWT));
852
853 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
854 PX86PDPT pPdpt = (PX86PDPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
855 PX86PDPE pPdpe = &pPdpt->a[iPdPt];
856
857 /* Allocate page directory if not present. */
858 if ( !pPdpe->n.u1Present
859 && !(pPdpe->u & X86_PDPE_PG_MASK))
860 {
861 PX86PML4E pPml4eGst = &pPGM->pGstPaePML4HC->a[iPml4e];
862 PX86PDPT pPdptGst;
863 rc = PGM_GCPHYS_2_PTR(pVM, pPml4eGst->u & X86_PML4E_PG_MASK, &pPdptGst);
864 AssertRCReturn(rc, rc);
865
866 Assert(!(pPdpe->u & X86_PDPE_PG_MASK));
867 /* Create a reference back to the PDPT by using the index in its shadow page. */
868 rc = pgmPoolAlloc(pVM, pPdptGst->a[iPdPt].u & X86_PDPE_PG_MASK, PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD, pShwPage->idx, iPdPt, &pShwPage);
869 if (rc == VERR_PGM_POOL_FLUSHED)
870 return VINF_PGM_SYNC_CR3;
871
872 AssertRCReturn(rc, rc);
873 }
874 else
875 {
876 pShwPage = pgmPoolGetPage(pPool, pPdpe->u & X86_PDPE_PG_MASK);
877 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
878 }
879 /* The PD was cached or created; hook it up now. */
880 pPdpe->u |= pShwPage->Core.Key
881 | (pGstPdpe->u & ~(X86_PDPE_PG_MASK | X86_PDPE_AVL_MASK | X86_PDPE_PCD | X86_PDPE_PWT));
882
883 *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
884 return VINF_SUCCESS;
885}
886
887/**
888 * Gets the SHADOW page directory pointer for the specified address.
889 *
890 * @returns VBox status.
891 * @param pVM VM handle.
892 * @param GCPtr The address.
893 * @param ppPdpt Receives address of pdpt
894 * @param ppPD Receives address of page directory
895 */
896PGMDECL(int) PGMShwGetLongModePDPtr(PVM pVM, RTGCUINTPTR64 GCPtr, PX86PDPT *ppPdpt, PX86PDPAE *ppPD)
897{
898 PPGM pPGM = &pVM->pgm.s;
899 const unsigned iPml4e = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
900 PPGMPOOL pPool = pPGM->CTXSUFF(pPool);
901 PX86PML4E pPml4e;
902 PPGMPOOLPAGE pShwPage;
903
904 Assert(!HWACCMIsNestedPagingActive(pVM));
905 AssertReturn(pVM->pgm.s.pHCPaePML4, VERR_INTERNAL_ERROR);
906
907 pPml4e = &pPGM->pHCPaePML4->a[iPml4e];
908 if (!pPml4e->n.u1Present)
909 return VERR_PAGE_MAP_LEVEL4_NOT_PRESENT;
910
911 pShwPage = pgmPoolGetPage(pPool, pPml4e->u & X86_PML4E_PG_MASK);
912 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
913
914 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
915 PX86PDPT pPdpt = (PX86PDPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
916 PX86PDPE pPdpe = &pPdpt->a[iPdPt];
917
918 *ppPdpt = pPdpt;
919 if (!pPdpe->n.u1Present)
920 return VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT;
921
922 pShwPage = pgmPoolGetPage(pPool, pPdpe->u & X86_PDPE_PG_MASK);
923 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
924
925 *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
926 return VINF_SUCCESS;
927}
928#endif
929
930/**
931 * Gets effective Guest OS page information.
932 *
933 * When GCPtr is in a big page, the function will return as if it was a normal
934 * 4KB page. If the need for distinguishing between big and normal page becomes
935 * necessary at a later point, a PGMGstGetPage() will be created for that
936 * purpose.
937 *
938 * @returns VBox status.
939 * @param pVM VM Handle.
940 * @param GCPtr Guest Context virtual address of the page.
941 * @param pfFlags Where to store the flags. These are X86_PTE_*, even for big pages.
942 * @param pGCPhys Where to store the GC physical address of the page.
943 * This is page aligned. The fact that the
944 */
945PGMDECL(int) PGMGstGetPage(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys)
946{
947 return PGM_GST_PFN(GetPage,pVM)(pVM, (RTGCUINTPTR)GCPtr, pfFlags, pGCPhys);
948}
949
950
951/**
952 * Checks if the page is present.
953 *
954 * @returns true if the page is present.
955 * @returns false if the page is not present.
956 * @param pVM The VM handle.
957 * @param GCPtr Address within the page.
958 */
959PGMDECL(bool) PGMGstIsPagePresent(PVM pVM, RTGCPTR GCPtr)
960{
961 int rc = PGMGstGetPage(pVM, GCPtr, NULL, NULL);
962 return VBOX_SUCCESS(rc);
963}
964
965
966/**
967 * Sets (replaces) the page flags for a range of pages in the guest's tables.
968 *
969 * @returns VBox status.
970 * @param pVM VM handle.
971 * @param GCPtr The address of the first page.
972 * @param cb The size of the range in bytes.
973 * @param fFlags Page flags X86_PTE_*, excluding the page mask of course.
974 */
975PGMDECL(int) PGMGstSetPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags)
976{
977 return PGMGstModifyPage(pVM, GCPtr, cb, fFlags, 0);
978}
979
980
981/**
982 * Modify page flags for a range of pages in the guest's tables
983 *
984 * The existing flags are ANDed with the fMask and ORed with the fFlags.
985 *
986 * @returns VBox status code.
987 * @param pVM VM handle.
988 * @param GCPtr Virtual address of the first page in the range.
989 * @param cb Size (in bytes) of the range to apply the modification to.
990 * @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
991 * @param fMask The AND mask - page flags X86_PTE_*, excluding the page mask of course.
992 * Be very CAREFUL when ~'ing constants which could be 32-bit!
993 */
994PGMDECL(int) PGMGstModifyPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
995{
996 STAM_PROFILE_START(&CTXMID(pVM->pgm.s.Stat,GstModifyPage), a);
997
998 /*
999 * Validate input.
1000 */
1001 if (fFlags & X86_PTE_PAE_PG_MASK)
1002 {
1003 AssertMsgFailed(("fFlags=%#llx\n", fFlags));
1004 STAM_PROFILE_STOP(&CTXMID(pVM->pgm.s.Stat,GstModifyPage), a);
1005 return VERR_INVALID_PARAMETER;
1006 }
1007
1008 if (!cb)
1009 {
1010 AssertFailed();
1011 STAM_PROFILE_STOP(&CTXMID(pVM->pgm.s.Stat,GstModifyPage), a);
1012 return VERR_INVALID_PARAMETER;
1013 }
1014
1015 LogFlow(("PGMGstModifyPage %VGv %d bytes fFlags=%08llx fMask=%08llx\n", GCPtr, cb, fFlags, fMask));
1016
1017 /*
1018 * Adjust input.
1019 */
1020 cb += (RTGCUINTPTR)GCPtr & PAGE_OFFSET_MASK;
1021 cb = RT_ALIGN_Z(cb, PAGE_SIZE);
1022 GCPtr = (RTGCPTR)((RTGCUINTPTR)GCPtr & PAGE_BASE_GC_MASK);
1023
1024 /*
1025 * Call worker.
1026 */
1027 int rc = PGM_GST_PFN(ModifyPage, pVM)(pVM, (RTGCUINTPTR)GCPtr, cb, fFlags, fMask);
1028
1029 STAM_PROFILE_STOP(&CTXMID(pVM->pgm.s.Stat,GstModifyPage), a);
1030 return rc;
1031}
1032
1033
1034/**
1035 * Gets the current CR3 register value for the shadow memory context.
1036 * @returns CR3 value.
1037 * @param pVM The VM handle.
1038 */
1039PGMDECL(uint32_t) PGMGetHyperCR3(PVM pVM)
1040{
1041 PGMMODE enmShadowMode = pVM->pgm.s.enmShadowMode;
1042 switch (enmShadowMode)
1043 {
1044 case PGMMODE_32_BIT:
1045 return pVM->pgm.s.HCPhys32BitPD;
1046
1047 case PGMMODE_PAE:
1048 case PGMMODE_PAE_NX:
1049 return pVM->pgm.s.HCPhysPaePDPT;
1050
1051 case PGMMODE_AMD64:
1052 case PGMMODE_AMD64_NX:
1053 return pVM->pgm.s.HCPhysPaePML4;
1054
1055 case PGMMODE_NESTED:
1056 return PGMGetNestedCR3(pVM, PGMGetHostMode(pVM));
1057
1058 default:
1059 AssertMsgFailed(("enmShadowMode=%d\n", enmShadowMode));
1060 return ~0;
1061 }
1062}
1063
1064/**
1065 * Gets the current CR3 register value for the nested memory context.
1066 * @returns CR3 value.
1067 * @param pVM The VM handle.
1068 */
1069PGMDECL(uint32_t) PGMGetNestedCR3(PVM pVM, PGMMODE enmShadowMode)
1070{
1071 switch (enmShadowMode)
1072 {
1073 case PGMMODE_32_BIT:
1074 return pVM->pgm.s.HCPhys32BitPD;
1075
1076 case PGMMODE_PAE:
1077 case PGMMODE_PAE_NX:
1078 return pVM->pgm.s.HCPhysPaePDPT;
1079
1080 case PGMMODE_AMD64:
1081 case PGMMODE_AMD64_NX:
1082 return pVM->pgm.s.HCPhysPaePML4;
1083
1084 default:
1085 AssertMsgFailed(("enmShadowMode=%d\n", enmShadowMode));
1086 return ~0;
1087 }
1088}
1089
1090
1091/**
1092 * Gets the CR3 register value for the 32-Bit shadow memory context.
1093 * @returns CR3 value.
1094 * @param pVM The VM handle.
1095 */
1096PGMDECL(uint32_t) PGMGetHyper32BitCR3(PVM pVM)
1097{
1098 return pVM->pgm.s.HCPhys32BitPD;
1099}
1100
1101
1102/**
1103 * Gets the CR3 register value for the PAE shadow memory context.
1104 * @returns CR3 value.
1105 * @param pVM The VM handle.
1106 */
1107PGMDECL(uint32_t) PGMGetHyperPaeCR3(PVM pVM)
1108{
1109 return pVM->pgm.s.HCPhysPaePDPT;
1110}
1111
1112
1113/**
1114 * Gets the CR3 register value for the AMD64 shadow memory context.
1115 * @returns CR3 value.
1116 * @param pVM The VM handle.
1117 */
1118PGMDECL(uint32_t) PGMGetHyperAmd64CR3(PVM pVM)
1119{
1120 return pVM->pgm.s.HCPhysPaePML4;
1121}
1122
1123
1124/**
1125 * Gets the current CR3 register value for the HC intermediate memory context.
1126 * @returns CR3 value.
1127 * @param pVM The VM handle.
1128 */
1129PGMDECL(uint32_t) PGMGetInterHCCR3(PVM pVM)
1130{
1131 switch (pVM->pgm.s.enmHostMode)
1132 {
1133 case SUPPAGINGMODE_32_BIT:
1134 case SUPPAGINGMODE_32_BIT_GLOBAL:
1135 return pVM->pgm.s.HCPhysInterPD;
1136
1137 case SUPPAGINGMODE_PAE:
1138 case SUPPAGINGMODE_PAE_GLOBAL:
1139 case SUPPAGINGMODE_PAE_NX:
1140 case SUPPAGINGMODE_PAE_GLOBAL_NX:
1141 return pVM->pgm.s.HCPhysInterPaePDPT;
1142
1143 case SUPPAGINGMODE_AMD64:
1144 case SUPPAGINGMODE_AMD64_GLOBAL:
1145 case SUPPAGINGMODE_AMD64_NX:
1146 case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1147 return pVM->pgm.s.HCPhysInterPaePDPT;
1148
1149 default:
1150 AssertMsgFailed(("enmHostMode=%d\n", pVM->pgm.s.enmHostMode));
1151 return ~0;
1152 }
1153}
1154
1155
1156/**
1157 * Gets the current CR3 register value for the GC intermediate memory context.
1158 * @returns CR3 value.
1159 * @param pVM The VM handle.
1160 */
1161PGMDECL(uint32_t) PGMGetInterGCCR3(PVM pVM)
1162{
1163 switch (pVM->pgm.s.enmShadowMode)
1164 {
1165 case PGMMODE_32_BIT:
1166 return pVM->pgm.s.HCPhysInterPD;
1167
1168 case PGMMODE_PAE:
1169 case PGMMODE_PAE_NX:
1170 return pVM->pgm.s.HCPhysInterPaePDPT;
1171
1172 case PGMMODE_AMD64:
1173 case PGMMODE_AMD64_NX:
1174 return pVM->pgm.s.HCPhysInterPaePML4;
1175
1176 case PGMMODE_NESTED:
1177 return 0; /* not relevant */
1178
1179 default:
1180 AssertMsgFailed(("enmShadowMode=%d\n", pVM->pgm.s.enmShadowMode));
1181 return ~0;
1182 }
1183}
1184
1185
1186/**
1187 * Gets the CR3 register value for the 32-Bit intermediate memory context.
1188 * @returns CR3 value.
1189 * @param pVM The VM handle.
1190 */
1191PGMDECL(uint32_t) PGMGetInter32BitCR3(PVM pVM)
1192{
1193 return pVM->pgm.s.HCPhysInterPD;
1194}
1195
1196
1197/**
1198 * Gets the CR3 register value for the PAE intermediate memory context.
1199 * @returns CR3 value.
1200 * @param pVM The VM handle.
1201 */
1202PGMDECL(uint32_t) PGMGetInterPaeCR3(PVM pVM)
1203{
1204 return pVM->pgm.s.HCPhysInterPaePDPT;
1205}
1206
1207
1208/**
1209 * Gets the CR3 register value for the AMD64 intermediate memory context.
1210 * @returns CR3 value.
1211 * @param pVM The VM handle.
1212 */
1213PGMDECL(uint32_t) PGMGetInterAmd64CR3(PVM pVM)
1214{
1215 return pVM->pgm.s.HCPhysInterPaePML4;
1216}
1217
1218
1219/**
1220 * Performs and schedules necessary updates following a CR3 load or reload.
1221 *
1222 * This will normally involve mapping the guest PD or nPDPT
1223 *
1224 * @returns VBox status code.
1225 * @retval VINF_PGM_SYNC_CR3 if monitoring requires a CR3 sync. This can
1226 * safely be ignored and overridden since the FF will be set too then.
1227 * @param pVM VM handle.
1228 * @param cr3 The new cr3.
1229 * @param fGlobal Indicates whether this is a global flush or not.
1230 */
1231PGMDECL(int) PGMFlushTLB(PVM pVM, uint64_t cr3, bool fGlobal)
1232{
1233 STAM_PROFILE_START(&pVM->pgm.s.StatFlushTLB, a);
1234
1235 /*
1236 * Always flag the necessary updates; necessary for hardware acceleration
1237 */
1238 VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
1239 if (fGlobal)
1240 VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
1241 LogFlow(("PGMFlushTLB: cr3=%VX64 OldCr3=%VX64 fGlobal=%d\n", cr3, pVM->pgm.s.GCPhysCR3, fGlobal));
1242
1243 /*
1244 * Remap the CR3 content and adjust the monitoring if CR3 was actually changed.
1245 */
1246 int rc = VINF_SUCCESS;
1247 RTGCPHYS GCPhysCR3;
1248 if ( pVM->pgm.s.enmGuestMode == PGMMODE_PAE
1249 || pVM->pgm.s.enmGuestMode == PGMMODE_PAE_NX
1250 || pVM->pgm.s.enmGuestMode == PGMMODE_AMD64
1251 || pVM->pgm.s.enmGuestMode == PGMMODE_AMD64_NX)
1252 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAE_PAGE_MASK);
1253 else
1254 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAGE_MASK);
1255 if (pVM->pgm.s.GCPhysCR3 != GCPhysCR3)
1256 {
1257 pVM->pgm.s.GCPhysCR3 = GCPhysCR3;
1258 rc = PGM_GST_PFN(MapCR3, pVM)(pVM, GCPhysCR3);
1259 if (VBOX_SUCCESS(rc) && !pVM->pgm.s.fMappingsFixed)
1260 {
1261 pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
1262 rc = PGM_GST_PFN(MonitorCR3, pVM)(pVM, GCPhysCR3);
1263 }
1264 if (fGlobal)
1265 STAM_COUNTER_INC(&pVM->pgm.s.StatFlushTLBNewCR3Global);
1266 else
1267 STAM_COUNTER_INC(&pVM->pgm.s.StatFlushTLBNewCR3);
1268 }
1269 else
1270 {
1271 /*
1272 * Check if we have a pending update of the CR3 monitoring.
1273 */
1274 if (pVM->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
1275 {
1276 pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
1277 Assert(!pVM->pgm.s.fMappingsFixed);
1278 rc = PGM_GST_PFN(MonitorCR3, pVM)(pVM, GCPhysCR3);
1279 }
1280 if (fGlobal)
1281 STAM_COUNTER_INC(&pVM->pgm.s.StatFlushTLBSameCR3Global);
1282 else
1283 STAM_COUNTER_INC(&pVM->pgm.s.StatFlushTLBSameCR3);
1284 }
1285
1286 STAM_PROFILE_STOP(&pVM->pgm.s.StatFlushTLB, a);
1287 return rc;
1288}
1289
1290/**
1291 * Performs and schedules necessary updates following a CR3 load or reload,
1292 * without actually the TLB as with PGMFlushTLB.
1293 *
1294 * This will normally involve mapping the guest PD or nPDPT
1295 *
1296 * @returns VBox status code.
1297 * @retval VINF_PGM_SYNC_CR3 if monitoring requires a CR3 sync. This can
1298 * safely be ignored and overridden since the FF will be set too then.
1299 * @param pVM VM handle.
1300 * @param cr3 The new cr3.
1301 */
1302PGMDECL(int) PGMUpdateCR3(PVM pVM, uint64_t cr3)
1303{
1304 LogFlow(("PGMUpdateCR3: cr3=%VX64 OldCr3=%VX64\n", cr3, pVM->pgm.s.GCPhysCR3));
1305
1306 /* We assume we're only called in nested paging mode. */
1307 Assert(pVM->pgm.s.fMappingsFixed);
1308 Assert(!(pVM->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3));
1309 Assert(pVM->pgm.s.enmShadowMode == PGMMODE_NESTED);
1310
1311 /*
1312 * Remap the CR3 content and adjust the monitoring if CR3 was actually changed.
1313 */
1314 int rc = VINF_SUCCESS;
1315 RTGCPHYS GCPhysCR3;
1316 if ( pVM->pgm.s.enmGuestMode == PGMMODE_PAE
1317 || pVM->pgm.s.enmGuestMode == PGMMODE_PAE_NX
1318 || pVM->pgm.s.enmGuestMode == PGMMODE_AMD64
1319 || pVM->pgm.s.enmGuestMode == PGMMODE_AMD64_NX)
1320 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAE_PAGE_MASK);
1321 else
1322 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAGE_MASK);
1323 if (pVM->pgm.s.GCPhysCR3 != GCPhysCR3)
1324 {
1325 pVM->pgm.s.GCPhysCR3 = GCPhysCR3;
1326 rc = PGM_GST_PFN(MapCR3, pVM)(pVM, GCPhysCR3);
1327 }
1328 AssertRC(rc);
1329 return rc;
1330}
1331
1332/**
1333 * Synchronize the paging structures.
1334 *
1335 * This function is called in response to the VM_FF_PGM_SYNC_CR3 and
1336 * VM_FF_PGM_SYNC_CR3_NONGLOBAL. Those two force action flags are set
1337 * in several places, most importantly whenever the CR3 is loaded.
1338 *
1339 * @returns VBox status code.
1340 * @param pVM The virtual machine.
1341 * @param cr0 Guest context CR0 register
1342 * @param cr3 Guest context CR3 register
1343 * @param cr4 Guest context CR4 register
1344 * @param fGlobal Including global page directories or not
1345 */
1346PGMDECL(int) PGMSyncCR3(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
1347{
1348 /*
1349 * We might be called when we shouldn't.
1350 *
1351 * The mode switching will ensure that the PD is resynced
1352 * after every mode switch. So, if we find ourselves here
1353 * when in protected or real mode we can safely disable the
1354 * FF and return immediately.
1355 */
1356 if (pVM->pgm.s.enmGuestMode <= PGMMODE_PROTECTED)
1357 {
1358 Assert((cr0 & (X86_CR0_PG | X86_CR0_PE)) != (X86_CR0_PG | X86_CR0_PE));
1359 VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3);
1360 VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
1361 return VINF_SUCCESS;
1362 }
1363
1364 /* If global pages are not supported, then all flushes are global */
1365 if (!(cr4 & X86_CR4_PGE))
1366 fGlobal = true;
1367 LogFlow(("PGMSyncCR3: cr0=%VX64 cr3=%VX64 cr4=%VX64 fGlobal=%d[%d,%d]\n", cr0, cr3, cr4, fGlobal,
1368 VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3), VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL)));
1369
1370 /*
1371 * Let the 'Bth' function do the work and we'll just keep track of the flags.
1372 */
1373 STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat,SyncCR3), a);
1374 int rc = PGM_BTH_PFN(SyncCR3, pVM)(pVM, cr0, cr3, cr4, fGlobal);
1375 STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncCR3), a);
1376 AssertMsg(rc == VINF_SUCCESS || rc == VINF_PGM_SYNC_CR3 || VBOX_FAILURE(rc), ("rc=%VRc\n", rc));
1377 if (rc == VINF_SUCCESS)
1378 {
1379 if (!(pVM->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS))
1380 {
1381 VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3);
1382 VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
1383 }
1384
1385 /*
1386 * Check if we have a pending update of the CR3 monitoring.
1387 */
1388 if (pVM->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
1389 {
1390 pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
1391 Assert(!pVM->pgm.s.fMappingsFixed);
1392 Assert(pVM->pgm.s.GCPhysCR3 == pVM->pgm.s.GCPhysGstCR3Monitored);
1393 rc = PGM_GST_PFN(MonitorCR3, pVM)(pVM, pVM->pgm.s.GCPhysCR3);
1394 }
1395 }
1396
1397 /*
1398 * Now flush the CR3 (guest context).
1399 */
1400 if (rc == VINF_SUCCESS)
1401 PGM_INVL_GUEST_TLBS();
1402 return rc;
1403}
1404
1405
1406/**
1407 * Called whenever CR0 or CR4 in a way which may change
1408 * the paging mode.
1409 *
1410 * @returns VBox status code fit for scheduling in GC and R0.
1411 * @retval VINF_SUCCESS if the was no change, or it was successfully dealt with.
1412 * @retval VINF_PGM_CHANGE_MODE if we're in GC or R0 and the mode changes.
1413 * @param pVM VM handle.
1414 * @param cr0 The new cr0.
1415 * @param cr4 The new cr4.
1416 * @param efer The new extended feature enable register.
1417 */
1418PGMDECL(int) PGMChangeMode(PVM pVM, uint64_t cr0, uint64_t cr4, uint64_t efer)
1419{
1420 PGMMODE enmGuestMode;
1421
1422 /*
1423 * Calc the new guest mode.
1424 */
1425 if (!(cr0 & X86_CR0_PE))
1426 enmGuestMode = PGMMODE_REAL;
1427 else if (!(cr0 & X86_CR0_PG))
1428 enmGuestMode = PGMMODE_PROTECTED;
1429 else if (!(cr4 & X86_CR4_PAE))
1430 enmGuestMode = PGMMODE_32_BIT;
1431 else if (!(efer & MSR_K6_EFER_LME))
1432 {
1433 if (!(efer & MSR_K6_EFER_NXE))
1434 enmGuestMode = PGMMODE_PAE;
1435 else
1436 enmGuestMode = PGMMODE_PAE_NX;
1437 }
1438 else
1439 {
1440 if (!(efer & MSR_K6_EFER_NXE))
1441 enmGuestMode = PGMMODE_AMD64;
1442 else
1443 enmGuestMode = PGMMODE_AMD64_NX;
1444 }
1445
1446 /*
1447 * Did it change?
1448 */
1449 if (pVM->pgm.s.enmGuestMode == enmGuestMode)
1450 return VINF_SUCCESS;
1451#ifdef IN_RING3
1452 return PGMR3ChangeMode(pVM, enmGuestMode);
1453#else
1454 Log(("PGMChangeMode: returns VINF_PGM_CHANGE_MODE.\n"));
1455 return VINF_PGM_CHANGE_MODE;
1456#endif
1457}
1458
1459
1460/**
1461 * Gets the current guest paging mode.
1462 *
1463 * If you just need the CPU mode (real/protected/long), use CPUMGetGuestMode().
1464 *
1465 * @returns The current paging mode.
1466 * @param pVM The VM handle.
1467 */
1468PGMDECL(PGMMODE) PGMGetGuestMode(PVM pVM)
1469{
1470 return pVM->pgm.s.enmGuestMode;
1471}
1472
1473
1474/**
1475 * Gets the current shadow paging mode.
1476 *
1477 * @returns The current paging mode.
1478 * @param pVM The VM handle.
1479 */
1480PGMDECL(PGMMODE) PGMGetShadowMode(PVM pVM)
1481{
1482 return pVM->pgm.s.enmShadowMode;
1483}
1484
1485/**
1486 * Gets the current host paging mode.
1487 *
1488 * @returns The current paging mode.
1489 * @param pVM The VM handle.
1490 */
1491PGMDECL(PGMMODE) PGMGetHostMode(PVM pVM)
1492{
1493 switch (pVM->pgm.s.enmHostMode)
1494 {
1495 case SUPPAGINGMODE_32_BIT:
1496 case SUPPAGINGMODE_32_BIT_GLOBAL:
1497 return PGMMODE_32_BIT;
1498
1499 case SUPPAGINGMODE_PAE:
1500 case SUPPAGINGMODE_PAE_GLOBAL:
1501 return PGMMODE_PAE;
1502
1503 case SUPPAGINGMODE_PAE_NX:
1504 case SUPPAGINGMODE_PAE_GLOBAL_NX:
1505 return PGMMODE_PAE_NX;
1506
1507 case SUPPAGINGMODE_AMD64:
1508 case SUPPAGINGMODE_AMD64_GLOBAL:
1509 return PGMMODE_AMD64;
1510
1511 case SUPPAGINGMODE_AMD64_NX:
1512 case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1513 return PGMMODE_AMD64_NX;
1514
1515 default: AssertMsgFailed(("enmHostMode=%d\n", pVM->pgm.s.enmHostMode)); break;
1516 }
1517
1518 return PGMMODE_INVALID;
1519}
1520
1521
1522/**
1523 * Get mode name.
1524 *
1525 * @returns read-only name string.
1526 * @param enmMode The mode which name is desired.
1527 */
1528PGMDECL(const char *) PGMGetModeName(PGMMODE enmMode)
1529{
1530 switch (enmMode)
1531 {
1532 case PGMMODE_REAL: return "real";
1533 case PGMMODE_PROTECTED: return "protected";
1534 case PGMMODE_32_BIT: return "32-bit";
1535 case PGMMODE_PAE: return "PAE";
1536 case PGMMODE_PAE_NX: return "PAE+NX";
1537 case PGMMODE_AMD64: return "AMD64";
1538 case PGMMODE_AMD64_NX: return "AMD64+NX";
1539 default: return "unknown mode value";
1540 }
1541}
1542
1543
1544/**
1545 * Acquire the PGM lock.
1546 *
1547 * @returns VBox status code
1548 * @param pVM The VM to operate on.
1549 */
1550int pgmLock(PVM pVM)
1551{
1552 int rc = PDMCritSectEnter(&pVM->pgm.s.CritSect, VERR_SEM_BUSY);
1553#ifdef IN_GC
1554 if (rc == VERR_SEM_BUSY)
1555 rc = VMMGCCallHost(pVM, VMMCALLHOST_PGM_LOCK, 0);
1556#elif defined(IN_RING0)
1557 if (rc == VERR_SEM_BUSY)
1558 rc = VMMR0CallHost(pVM, VMMCALLHOST_PGM_LOCK, 0);
1559#endif
1560 AssertRC(rc);
1561 return rc;
1562}
1563
1564
1565/**
1566 * Release the PGM lock.
1567 *
1568 * @returns VBox status code
1569 * @param pVM The VM to operate on.
1570 */
1571void pgmUnlock(PVM pVM)
1572{
1573 PDMCritSectLeave(&pVM->pgm.s.CritSect);
1574}
1575
1576
1577#ifdef VBOX_STRICT
1578
1579/**
1580 * Asserts that there are no mapping conflicts.
1581 *
1582 * @returns Number of conflicts.
1583 * @param pVM The VM Handle.
1584 */
1585PGMDECL(unsigned) PGMAssertNoMappingConflicts(PVM pVM)
1586{
1587 unsigned cErrors = 0;
1588
1589 /*
1590 * Check for mapping conflicts.
1591 */
1592 for (PPGMMAPPING pMapping = CTXALLSUFF(pVM->pgm.s.pMappings);
1593 pMapping;
1594 pMapping = CTXALLSUFF(pMapping->pNext))
1595 {
1596 /** @todo This is slow and should be optimized, but since it's just assertions I don't care now. */
1597 for (RTGCUINTPTR GCPtr = (RTGCUINTPTR)pMapping->GCPtr;
1598 GCPtr <= (RTGCUINTPTR)pMapping->GCPtrLast;
1599 GCPtr += PAGE_SIZE)
1600 {
1601 int rc = PGMGstGetPage(pVM, (RTGCPTR)GCPtr, NULL, NULL);
1602 if (rc != VERR_PAGE_TABLE_NOT_PRESENT)
1603 {
1604 AssertMsgFailed(("Conflict at %VGv with %s\n", GCPtr, HCSTRING(pMapping->pszDesc)));
1605 cErrors++;
1606 break;
1607 }
1608 }
1609 }
1610
1611 return cErrors;
1612}
1613
1614
1615/**
1616 * Asserts that everything related to the guest CR3 is correctly shadowed.
1617 *
1618 * This will call PGMAssertNoMappingConflicts() and PGMAssertHandlerAndFlagsInSync(),
1619 * and assert the correctness of the guest CR3 mapping before asserting that the
1620 * shadow page tables is in sync with the guest page tables.
1621 *
1622 * @returns Number of conflicts.
1623 * @param pVM The VM Handle.
1624 * @param cr3 The current guest CR3 register value.
1625 * @param cr4 The current guest CR4 register value.
1626 */
1627PGMDECL(unsigned) PGMAssertCR3(PVM pVM, uint64_t cr3, uint64_t cr4)
1628{
1629 STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat,SyncCR3), a);
1630 unsigned cErrors = PGM_BTH_PFN(AssertCR3, pVM)(pVM, cr3, cr4, 0, ~(RTGCUINTPTR)0);
1631 STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncCR3), a);
1632 return cErrors;
1633 return 0;
1634}
1635
1636#endif /* VBOX_STRICT */
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