PGMAllBth.h@ 14082

Last change on this file since 14082 was 14038, checked in by vboxsync, 16 years ago
#1865: PGM - and another one.
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1	/* $Id: PGMAllBth.h 14038 2008-11-10 18:23:15Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Shadow+Guest Paging Template - All context code.
4	*
5	* This file is a big challenge!
6	*/
7
8	/*
9	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
10	*
11	* This file is part of VirtualBox Open Source Edition (OSE), as
12	* available from http://www.virtualbox.org. This file is free software;
13	* you can redistribute it and/or modify it under the terms of the GNU
14	* General Public License (GPL) as published by the Free Software
15	* Foundation, in version 2 as it comes in the "COPYING" file of the
16	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
17	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
18	*
19	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
20	* Clara, CA 95054 USA or visit http://www.sun.com if you need
21	* additional information or have any questions.
22	*/
23
24	/*******************************************************************************
25	* Internal Functions *
26	*******************************************************************************/
27	__BEGIN_DECLS
28	PGM_BTH_DECL(int, Trap0eHandler)(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
29	PGM_BTH_DECL(int, InvalidatePage)(PVM pVM, RTGCPTR GCPtrPage);
30	PGM_BTH_DECL(int, SyncPage)(PVM pVM, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr);
31	PGM_BTH_DECL(int, CheckPageFault)(PVM pVM, uint32_t uErr, PSHWPDE pPdeDst, PGSTPDE pPdeSrc, RTGCPTR GCPtrPage);
32	PGM_BTH_DECL(int, SyncPT)(PVM pVM, unsigned iPD, PGSTPD pPDSrc, RTGCPTR GCPtrPage);
33	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVM pVM, RTGCPTR Addr, unsigned fPage, unsigned uErr);
34	PGM_BTH_DECL(int, PrefetchPage)(PVM pVM, RTGCPTR GCPtrPage);
35	PGM_BTH_DECL(int, SyncCR3)(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
36	#ifdef VBOX_STRICT
37	PGM_BTH_DECL(unsigned, AssertCR3)(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr = 0, RTGCPTR cb = ~(RTGCPTR)0);
38	#endif
39	#ifdef PGMPOOL_WITH_USER_TRACKING
40	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVM pVM, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys);
41	#endif
42	__END_DECLS
43
44
45	/* Filter out some illegal combinations of guest and shadow paging, so we can remove redundant checks inside functions. */
46	#if PGM_GST_TYPE == PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
47	# error "Invalid combination; PAE guest implies PAE shadow"
48	#endif
49
50	#if (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
51	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT)
52	# error "Invalid combination; real or protected mode without paging implies 32 bits or PAE shadow paging."
53	#endif
54
55	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) \
56	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT)
57	# error "Invalid combination; 32 bits guest paging or PAE implies 32 bits or PAE shadow paging."
58	#endif
59
60	#if (PGM_GST_TYPE == PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT) \
61	\|\| (PGM_SHW_TYPE == PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PROT)
62	# error "Invalid combination; AMD64 guest implies AMD64 shadow and vice versa"
63	#endif
64
65	#ifdef IN_RING0 /* no mappings in VT-x and AMD-V mode */
66	# define PGM_WITHOUT_MAPPINGS
67	#endif
68
69
70	#ifndef IN_RING3
71	/**
72	* #PF Handler for raw-mode guest execution.
73	*
74	* @returns VBox status code (appropriate for trap handling and GC return).
75	* @param pVM VM Handle.
76	* @param uErr The trap error code.
77	* @param pRegFrame Trap register frame.
78	* @param pvFault The fault address.
79	*/
80	PGM_BTH_DECL(int, Trap0eHandler)(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
81	{
82	# if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
83	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
84	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT)
85
86	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE != PGM_TYPE_PAE
87	/*
88	* Hide the instruction fetch trap indicator for now.
89	*/
90	/** @todo NXE will change this and we must fix NXE in the switcher too! */
91	if (uErr & X86_TRAP_PF_ID)
92	{
93	uErr &= ~X86_TRAP_PF_ID;
94	TRPMSetErrorCode(pVM, uErr);
95	}
96	# endif
97
98	/*
99	* Get PDs.
100	*/
101	int rc;
102	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
103	# if PGM_GST_TYPE == PGM_TYPE_32BIT
104	const unsigned iPDSrc = pvFault >> GST_PD_SHIFT;
105	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(&pVM->pgm.s);
106
107	# elif PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
108
109	# if PGM_GST_TYPE == PGM_TYPE_PAE
110	unsigned iPDSrc;
111	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, pvFault, &iPDSrc, NULL);
112
113	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
114	unsigned iPDSrc;
115	PX86PML4E pPml4eSrc;
116	X86PDPE PdpeSrc;
117	PGSTPD pPDSrc;
118
119	pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, pvFault, &pPml4eSrc, &PdpeSrc, &iPDSrc);
120	Assert(pPml4eSrc);
121	# endif
122	/* Quick check for a valid guest trap. */
123	if (!pPDSrc)
124	{
125	# if PGM_GST_TYPE == PGM_TYPE_AMD64 && GC_ARCH_BITS == 64
126	LogFlow(("Trap0eHandler: guest PML4 %d not present CR3=%RGp\n", (int)((pvFault >> X86_PML4_SHIFT) & X86_PML4_MASK), CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK));
127	# else
128	LogFlow(("Trap0eHandler: guest iPDSrc=%u not present CR3=%RGp\n", iPDSrc, CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK));
129	# endif
130	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2GuestTrap; });
131	TRPMSetErrorCode(pVM, uErr);
132	return VINF_EM_RAW_GUEST_TRAP;
133	}
134	# endif
135
136	# else /* !PGM_WITH_PAGING */
137	PGSTPD pPDSrc = NULL;
138	const unsigned iPDSrc = 0;
139	# endif /* !PGM_WITH_PAGING */
140
141
142	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
143	const unsigned iPDDst = pvFault >> SHW_PD_SHIFT;
144	PX86PD pPDDst = pVM->pgm.s.CTXMID(p,32BitPD);
145
146	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
147	const unsigned iPDDst = pvFault >> SHW_PD_SHIFT;
148	PX86PDPAE pPDDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]; /* We treat this as a PD with 2048 entries, so no need to and with SHW_PD_MASK to get iPDDst */
149
150	# if PGM_GST_TYPE == PGM_TYPE_PAE
151	/* Did we mark the PDPT as not present in SyncCR3? */
152	unsigned iPdpte = (pvFault >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
153	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(&pVM->pgm.s);
154	if (!pPdptDst->a[iPdpte].n.u1Present)
155	pPdptDst->a[iPdpte].n.u1Present = 1;
156
157	# endif
158
159	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
160	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
161	PX86PDPAE pPDDst;
162	# if PGM_GST_TYPE == PGM_TYPE_PROT
163	/* AMD-V nested paging */
164	X86PML4E Pml4eSrc;
165	X86PDPE PdpeSrc;
166	PX86PML4E pPml4eSrc = &Pml4eSrc;
167
168	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
169	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A;
170	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A;
171	# endif
172
173	rc = pgmShwSyncLongModePDPtr(pVM, pvFault, pPml4eSrc, &PdpeSrc, &pPDDst);
174	if (rc != VINF_SUCCESS)
175	{
176	AssertRC(rc);
177	return rc;
178	}
179	Assert(pPDDst);
180
181	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
182	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
183	PEPTPD pPDDst;
184
185	rc = pgmShwGetEPTPDPtr(pVM, pvFault, NULL, &pPDDst);
186	if (rc != VINF_SUCCESS)
187	{
188	AssertRC(rc);
189	return rc;
190	}
191	Assert(pPDDst);
192	# endif
193
194	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
195	/*
196	* If we successfully correct the write protection fault due to dirty bit
197	* tracking, or this page fault is a genuine one, then return immediately.
198	*/
199	STAM_PROFILE_START(&pVM->pgm.s.StatRZTrap0eTimeCheckPageFault, e);
200	rc = PGM_BTH_NAME(CheckPageFault)(pVM, uErr, &pPDDst->a[iPDDst], &pPDSrc->a[iPDSrc], pvFault);
201	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeCheckPageFault, e);
202	if ( rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT
203	\|\| rc == VINF_EM_RAW_GUEST_TRAP)
204	{
205	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution)
206	= rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? &pVM->pgm.s.StatRZTrap0eTime2DirtyAndAccessed : &pVM->pgm.s.StatRZTrap0eTime2GuestTrap; });
207	LogBird(("Trap0eHandler: returns %s\n", rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? "VINF_SUCCESS" : "VINF_EM_RAW_GUEST_TRAP"));
208	return rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? VINF_SUCCESS : rc;
209	}
210
211	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0ePD[iPDSrc]);
212	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
213
214	/*
215	* A common case is the not-present error caused by lazy page table syncing.
216	*
217	* It is IMPORTANT that we weed out any access to non-present shadow PDEs here
218	* so we can safely assume that the shadow PT is present when calling SyncPage later.
219	*
220	* On failure, we ASSUME that SyncPT is out of memory or detected some kind
221	* of mapping conflict and defer to SyncCR3 in R3.
222	* (Again, we do NOT support access handlers for non-present guest pages.)
223	*
224	*/
225	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
226	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
227	# else
228	GSTPDE PdeSrc;
229	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
230	PdeSrc.n.u1Present = 1;
231	PdeSrc.n.u1Write = 1;
232	PdeSrc.n.u1Accessed = 1;
233	PdeSrc.n.u1User = 1;
234	# endif
235	if ( !(uErr & X86_TRAP_PF_P) /* not set means page not present instead of page protection violation */
236	&& !pPDDst->a[iPDDst].n.u1Present
237	&& PdeSrc.n.u1Present
238	)
239
240	{
241	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2SyncPT; });
242	STAM_PROFILE_START(&pVM->pgm.s.StatRZTrap0eTimeSyncPT, f);
243	LogFlow(("=>SyncPT %04x = %08x\n", iPDSrc, PdeSrc.au32[0]));
244	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, pvFault);
245	if (RT_SUCCESS(rc))
246	{
247	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeSyncPT, f);
248	return rc;
249	}
250	Log(("SyncPT: %d failed!! rc=%d\n", iPDSrc, rc));
251	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3); /** @todo no need to do global sync, right? */
252	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeSyncPT, f);
253	return VINF_PGM_SYNC_CR3;
254	}
255
256	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
257	/*
258	* Check if this address is within any of our mappings.
259	*
260	* This is very fast and it's gonna save us a bit of effort below and prevent
261	* us from screwing ourself with MMIO2 pages which have a GC Mapping (VRam).
262	* (BTW, it's impossible to have physical access handlers in a mapping.)
263	*/
264	if (pgmMapAreMappingsEnabled(&pVM->pgm.s))
265	{
266	STAM_PROFILE_START(&pVM->pgm.s.StatRZTrap0eTimeMapping, a);
267	PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
268	for ( ; pMapping; pMapping = pMapping->CTX_SUFF(pNext))
269	{
270	if (pvFault < pMapping->GCPtr)
271	break;
272	if (pvFault - pMapping->GCPtr < pMapping->cb)
273	{
274	/*
275	* The first thing we check is if we've got an undetected conflict.
276	*/
277	if (!pVM->pgm.s.fMappingsFixed)
278	{
279	unsigned iPT = pMapping->cb >> GST_PD_SHIFT;
280	while (iPT-- > 0)
281	if (pPDSrc->a[iPDSrc + iPT].n.u1Present)
282	{
283	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eConflicts);
284	Log(("Trap0e: Detected Conflict %RGv-%RGv\n", pMapping->GCPtr, pMapping->GCPtrLast));
285	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3); /** @todo no need to do global sync,right? */
286	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeMapping, a);
287	return VINF_PGM_SYNC_CR3;
288	}
289	}
290
291	/*
292	* Check if the fault address is in a virtual page access handler range.
293	*/
294	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->HyperVirtHandlers, pvFault);
295	if ( pCur
296	&& pvFault - pCur->Core.Key < pCur->cb
297	&& uErr & X86_TRAP_PF_RW)
298	{
299	# ifdef IN_RC
300	STAM_PROFILE_START(&pCur->Stat, h);
301	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
302	STAM_PROFILE_STOP(&pCur->Stat, h);
303	# else
304	AssertFailed();
305	rc = VINF_EM_RAW_EMULATE_INSTR; /* can't happen with VMX */
306	# endif
307	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersMapping);
308	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeMapping, a);
309	return rc;
310	}
311
312	/*
313	* Pretend we're not here and let the guest handle the trap.
314	*/
315	TRPMSetErrorCode(pVM, uErr & ~X86_TRAP_PF_P);
316	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eGuestPFMapping);
317	LogFlow(("PGM: Mapping access -> route trap to recompiler!\n"));
318	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeMapping, a);
319	return VINF_EM_RAW_GUEST_TRAP;
320	}
321	}
322	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeMapping, a);
323	} /* pgmAreMappingsEnabled(&pVM->pgm.s) */
324	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
325
326	/*
327	* Check if this fault address is flagged for special treatment,
328	* which means we'll have to figure out the physical address and
329	* check flags associated with it.
330	*
331	* ASSUME that we can limit any special access handling to pages
332	* in page tables which the guest believes to be present.
333	*/
334	if (PdeSrc.n.u1Present)
335	{
336	RTGCPHYS GCPhys = NIL_RTGCPHYS;
337
338	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
339	# if PGM_GST_TYPE == PGM_TYPE_AMD64
340	bool fBigPagesSupported = true;
341	# else
342	bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
343	# endif
344	if ( PdeSrc.b.u1Size
345	&& fBigPagesSupported)
346	GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc)
347	\| ((RTGCPHYS)pvFault & (GST_BIG_PAGE_OFFSET_MASK ^ PAGE_OFFSET_MASK));
348	else
349	{
350	PGSTPT pPTSrc;
351	rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
352	if (RT_SUCCESS(rc))
353	{
354	unsigned iPTESrc = (pvFault >> GST_PT_SHIFT) & GST_PT_MASK;
355	if (pPTSrc->a[iPTESrc].n.u1Present)
356	GCPhys = pPTSrc->a[iPTESrc].u & GST_PTE_PG_MASK;
357	}
358	}
359	# else
360	/* No paging so the fault address is the physical address */
361	GCPhys = (RTGCPHYS)(pvFault & ~PAGE_OFFSET_MASK);
362	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
363
364	/*
365	* If we have a GC address we'll check if it has any flags set.
366	*/
367	if (GCPhys != NIL_RTGCPHYS)
368	{
369	STAM_PROFILE_START(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
370
371	PPGMPAGE pPage;
372	rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
373	if (RT_SUCCESS(rc))
374	{
375	if ( PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(pPage)
376	\|\| PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(pPage))
377	{
378	if (PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage))
379	{
380	/*
381	* Physical page access handler.
382	*/
383	const RTGCPHYS GCPhysFault = GCPhys \| (pvFault & PAGE_OFFSET_MASK);
384	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)RTAvlroGCPhysRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->PhysHandlers, GCPhysFault);
385	if (pCur)
386	{
387	# ifdef PGM_SYNC_N_PAGES
388	/*
389	* If the region is write protected and we got a page not present fault, then sync
390	* the pages. If the fault was caused by a read, then restart the instruction.
391	* In case of write access continue to the GC write handler.
392	*
393	* ASSUMES that there is only one handler per page or that they have similar write properties.
394	*/
395	if ( pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
396	&& !(uErr & X86_TRAP_PF_P))
397	{
398	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, pvFault, PGM_SYNC_NR_PAGES, uErr);
399	if ( RT_FAILURE(rc)
400	\|\| !(uErr & X86_TRAP_PF_RW)
401	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
402	{
403	AssertRC(rc);
404	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersOutOfSync);
405	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
406	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2OutOfSyncHndPhys; });
407	return rc;
408	}
409	}
410	# endif
411
412	AssertMsg( pCur->enmType != PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
413	\|\| (pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE && (uErr & X86_TRAP_PF_RW)),
414	("Unexpected trap for physical handler: %08X (phys=%08x) HCPhys=%X uErr=%X, enum=%d\n", pvFault, GCPhys, pPage->HCPhys, uErr, pCur->enmType));
415
416	# if defined(IN_RC) \|\| defined(IN_RING0)
417	if (pCur->CTX_SUFF(pfnHandler))
418	{
419	STAM_PROFILE_START(&pCur->Stat, h);
420	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, GCPhysFault, pCur->CTX_SUFF(pvUser));
421	STAM_PROFILE_STOP(&pCur->Stat, h);
422	}
423	else
424	# endif
425	rc = VINF_EM_RAW_EMULATE_INSTR;
426	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersPhysical);
427	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
428	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2HndPhys; });
429	return rc;
430	}
431	}
432	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
433	else
434	{
435	# ifdef PGM_SYNC_N_PAGES
436	/*
437	* If the region is write protected and we got a page not present fault, then sync
438	* the pages. If the fault was caused by a read, then restart the instruction.
439	* In case of write access continue to the GC write handler.
440	*/
441	if ( PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) < PGM_PAGE_HNDL_PHYS_STATE_ALL
442	&& !(uErr & X86_TRAP_PF_P))
443	{
444	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, pvFault, PGM_SYNC_NR_PAGES, uErr);
445	if ( RT_FAILURE(rc)
446	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
447	\|\| !(uErr & X86_TRAP_PF_RW))
448	{
449	AssertRC(rc);
450	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersOutOfSync);
451	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
452	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2OutOfSyncHndVirt; });
453	return rc;
454	}
455	}
456	# endif
457	/*
458	* Ok, it's an virtual page access handler.
459	*
460	* Since it's faster to search by address, we'll do that first
461	* and then retry by GCPhys if that fails.
462	*/
463	/** @todo r=bird: perhaps we should consider looking up by physical address directly now? */
464	/** @note r=svl: true, but lookup on virtual address should remain as a fallback as phys & virt trees might be out of sync, because the
465	* page was changed without us noticing it (not-present -> present without invlpg or mov cr3, xxx)
466	*/
467	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
468	if (pCur)
469	{
470	AssertMsg(!(pvFault - pCur->Core.Key < pCur->cb)
471	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
472	\|\| !(uErr & X86_TRAP_PF_P)
473	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
474	("Unexpected trap for virtual handler: %RGv (phys=%RGp) HCPhys=%HGp uErr=%X, enum=%d\n", pvFault, GCPhys, pPage->HCPhys, uErr, pCur->enmType));
475
476	if ( pvFault - pCur->Core.Key < pCur->cb
477	&& ( uErr & X86_TRAP_PF_RW
478	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
479	{
480	# ifdef IN_RC
481	STAM_PROFILE_START(&pCur->Stat, h);
482	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
483	STAM_PROFILE_STOP(&pCur->Stat, h);
484	# else
485	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
486	# endif
487	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersVirtual);
488	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
489	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2HndVirt; });
490	return rc;
491	}
492	/* Unhandled part of a monitored page */
493	}
494	else
495	{
496	/* Check by physical address. */
497	PPGMVIRTHANDLER pCur;
498	unsigned iPage;
499	rc = pgmHandlerVirtualFindByPhysAddr(pVM, GCPhys + (pvFault & PAGE_OFFSET_MASK),
500	&pCur, &iPage);
501	Assert(RT_SUCCESS(rc) \|\| !pCur);
502	if ( pCur
503	&& ( uErr & X86_TRAP_PF_RW
504	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
505	{
506	Assert((pCur->aPhysToVirt[iPage].Core.Key & X86_PTE_PAE_PG_MASK) == GCPhys);
507	# ifdef IN_RC
508	RTGCPTR off = (iPage << PAGE_SHIFT) + (pvFault & PAGE_OFFSET_MASK) - (pCur->Core.Key & PAGE_OFFSET_MASK);
509	Assert(off < pCur->cb);
510	STAM_PROFILE_START(&pCur->Stat, h);
511	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, off);
512	STAM_PROFILE_STOP(&pCur->Stat, h);
513	# else
514	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
515	# endif
516	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersVirtualByPhys);
517	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
518	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2HndVirt; });
519	return rc;
520	}
521	}
522	}
523	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
524
525	/*
526	* There is a handled area of the page, but this fault doesn't belong to it.
527	* We must emulate the instruction.
528	*
529	* To avoid crashing (non-fatal) in the interpreter and go back to the recompiler
530	* we first check if this was a page-not-present fault for a page with only
531	* write access handlers. Restart the instruction if it wasn't a write access.
532	*/
533	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersUnhandled);
534
535	if ( !PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
536	&& !(uErr & X86_TRAP_PF_P))
537	{
538	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, pvFault, PGM_SYNC_NR_PAGES, uErr);
539	if ( RT_FAILURE(rc)
540	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
541	\|\| !(uErr & X86_TRAP_PF_RW))
542	{
543	AssertRC(rc);
544	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersOutOfSync);
545	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
546	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2OutOfSyncHndPhys; });
547	return rc;
548	}
549	}
550
551	/** @todo This particular case can cause quite a lot of overhead. E.g. early stage of kernel booting in Ubuntu 6.06
552	* It's writing to an unhandled part of the LDT page several million times.
553	*/
554	rc = PGMInterpretInstruction(pVM, pRegFrame, pvFault);
555	LogFlow(("PGM: PGMInterpretInstruction -> rc=%d HCPhys=%RHp%s%s\n",
556	rc, pPage->HCPhys,
557	PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage) ? " phys" : "",
558	PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage) ? " virt" : ""));
559	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
560	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2HndUnhandled; });
561	return rc;
562	} /* if any kind of handler */
563
564	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
565	if (uErr & X86_TRAP_PF_P)
566	{
567	/*
568	* The page isn't marked, but it might still be monitored by a virtual page access handler.
569	* (ASSUMES no temporary disabling of virtual handlers.)
570	*/
571	/** @todo r=bird: Since the purpose is to catch out of sync pages with virtual handler(s) here,
572	* we should correct both the shadow page table and physical memory flags, and not only check for
573	* accesses within the handler region but for access to pages with virtual handlers. */
574	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
575	if (pCur)
576	{
577	AssertMsg( !(pvFault - pCur->Core.Key < pCur->cb)
578	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
579	\|\| !(uErr & X86_TRAP_PF_P)
580	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
581	("Unexpected trap for virtual handler: %08X (phys=%08x) HCPhys=%X uErr=%X, enum=%d\n", pvFault, GCPhys, pPage->HCPhys, uErr, pCur->enmType));
582
583	if ( pvFault - pCur->Core.Key < pCur->cb
584	&& ( uErr & X86_TRAP_PF_RW
585	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
586	{
587	# ifdef IN_RC
588	STAM_PROFILE_START(&pCur->Stat, h);
589	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
590	STAM_PROFILE_STOP(&pCur->Stat, h);
591	# else
592	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
593	# endif
594	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersVirtualUnmarked);
595	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
596	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2HndVirt; });
597	return rc;
598	}
599	}
600	}
601	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
602	}
603	else
604	{
605	/* When the guest accesses invalid physical memory (e.g. probing of RAM or accessing a remapped MMIO range), then we'll fall
606	* back to the recompiler to emulate the instruction.
607	*/
608	LogFlow(("pgmPhysGetPageEx %RGp failed with %Rrc\n", GCPhys, rc));
609	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersInvalid);
610	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
611	return VINF_EM_RAW_EMULATE_INSTR;
612	}
613
614	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
615
616	# ifdef PGM_OUT_OF_SYNC_IN_GC
617	/*
618	* We are here only if page is present in Guest page tables and trap is not handled
619	* by our handlers.
620	* Check it for page out-of-sync situation.
621	*/
622	STAM_PROFILE_START(&pVM->pgm.s.StatRZTrap0eTimeOutOfSync, c);
623
624	if (!(uErr & X86_TRAP_PF_P))
625	{
626	/*
627	* Page is not present in our page tables.
628	* Try to sync it!
629	* BTW, fPageShw is invalid in this branch!
630	*/
631	if (uErr & X86_TRAP_PF_US)
632	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncUser));
633	else /* supervisor */
634	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
635
636	# if defined(LOG_ENABLED) && !defined(IN_RING0)
637	RTGCPHYS GCPhys;
638	uint64_t fPageGst;
639	PGMGstGetPage(pVM, pvFault, &fPageGst, &GCPhys);
640	Log(("Page out of sync: %RGv eip=%08x PdeSrc.n.u1User=%d fPageGst=%08llx GCPhys=%RGp scan=%d\n",
641	pvFault, pRegFrame->eip, PdeSrc.n.u1User, fPageGst, GCPhys, CSAMDoesPageNeedScanning(pVM, (RTRCPTR)pRegFrame->eip)));
642	# endif /* LOG_ENABLED */
643
644	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0)
645	if (CPUMGetGuestCPL(pVM, pRegFrame) == 0)
646	{
647	uint64_t fPageGst;
648	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, NULL);
649	if ( RT_SUCCESS(rc)
650	&& !(fPageGst & X86_PTE_US))
651	{
652	/* Note: can't check for X86_TRAP_ID bit, because that requires execute disable support on the CPU */
653	if ( pvFault == (RTGCPTR)pRegFrame->eip
654	\|\| pvFault - pRegFrame->eip < 8 /* instruction crossing a page boundary */
655	# ifdef CSAM_DETECT_NEW_CODE_PAGES
656	\|\| ( !PATMIsPatchGCAddr(pVM, (RTGCPTR)pRegFrame->eip)
657	&& CSAMDoesPageNeedScanning(pVM, (RTRCPTR)pRegFrame->eip)) /* any new code we encounter here */
658	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
659	)
660	{
661	LogFlow(("CSAMExecFault %RX32\n", pRegFrame->eip));
662	rc = CSAMExecFault(pVM, (RTRCPTR)pRegFrame->eip);
663	if (rc != VINF_SUCCESS)
664	{
665	/*
666	* CSAM needs to perform a job in ring 3.
667	*
668	* Sync the page before going to the host context; otherwise we'll end up in a loop if
669	* CSAM fails (e.g. instruction crosses a page boundary and the next page is not present)
670	*/
671	LogFlow(("CSAM ring 3 job\n"));
672	int rc2 = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, pvFault, 1, uErr);
673	AssertRC(rc2);
674
675	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeOutOfSync, c);
676	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2CSAM; });
677	return rc;
678	}
679	}
680	# ifdef CSAM_DETECT_NEW_CODE_PAGES
681	else if ( uErr == X86_TRAP_PF_RW
682	&& pRegFrame->ecx >= 0x100 /* early check for movswd count */
683	&& pRegFrame->ecx < 0x10000)
684	{
685	/* In case of a write to a non-present supervisor shadow page, we'll take special precautions
686	* to detect loading of new code pages.
687	*/
688
689	/*
690	* Decode the instruction.
691	*/
692	RTGCPTR PC;
693	rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->eip, &PC);
694	if (rc == VINF_SUCCESS)
695	{
696	DISCPUSTATE Cpu;
697	uint32_t cbOp;
698	rc = EMInterpretDisasOneEx(pVM, PC, pRegFrame, &Cpu, &cbOp);
699
700	/* For now we'll restrict this to rep movsw/d instructions */
701	if ( rc == VINF_SUCCESS
702	&& Cpu.pCurInstr->opcode == OP_MOVSWD
703	&& (Cpu.prefix & PREFIX_REP))
704	{
705	CSAMMarkPossibleCodePage(pVM, pvFault);
706	}
707	}
708	}
709	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
710
711	/*
712	* Mark this page as safe.
713	*/
714	/** @todo not correct for pages that contain both code and data!! */
715	Log2(("CSAMMarkPage %RGv; scanned=%d\n", pvFault, true));
716	CSAMMarkPage(pVM, (RTRCPTR)pvFault, true);
717	}
718	}
719	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0) */
720	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, pvFault, PGM_SYNC_NR_PAGES, uErr);
721	if (RT_SUCCESS(rc))
722	{
723	/* The page was successfully synced, return to the guest. */
724	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeOutOfSync, c);
725	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2OutOfSync; });
726	return VINF_SUCCESS;
727	}
728	}
729	else
730	{
731	/*
732	* A side effect of not flushing global PDEs are out of sync pages due
733	* to physical monitored regions, that are no longer valid.
734	* Assume for now it only applies to the read/write flag
735	*/
736	if (RT_SUCCESS(rc) && (uErr & X86_TRAP_PF_RW))
737	{
738	if (uErr & X86_TRAP_PF_US)
739	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncUser));
740	else /* supervisor */
741	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
742
743
744	/*
745	* Note: Do NOT use PGM_SYNC_NR_PAGES here. That only works if the page is not present, which is not true in this case.
746	*/
747	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, pvFault, 1, uErr);
748	if (RT_SUCCESS(rc))
749	{
750	/*
751	* Page was successfully synced, return to guest.
752	*/
753	# ifdef VBOX_STRICT
754	RTGCPHYS GCPhys;
755	uint64_t fPageGst;
756	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, &GCPhys);
757	Assert(RT_SUCCESS(rc) && fPageGst & X86_PTE_RW);
758	LogFlow(("Obsolete physical monitor page out of sync %RGv - phys %RGp flags=%08llx\n", pvFault, GCPhys, (uint64_t)fPageGst));
759
760	uint64_t fPageShw;
761	rc = PGMShwGetPage(pVM, pvFault, &fPageShw, NULL);
762	AssertMsg(RT_SUCCESS(rc) && fPageShw & X86_PTE_RW, ("rc=%Rrc fPageShw=%RX64\n", rc, fPageShw));
763	# endif /* VBOX_STRICT */
764	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeOutOfSync, c);
765	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2OutOfSyncHndObs; });
766	return VINF_SUCCESS;
767	}
768
769	/* Check to see if we need to emulate the instruction as X86_CR0_WP has been cleared. */
770	if ( CPUMGetGuestCPL(pVM, pRegFrame) == 0
771	&& ((CPUMGetGuestCR0(pVM) & (X86_CR0_WP \| X86_CR0_PG)) == X86_CR0_PG)
772	&& (uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RW \| X86_TRAP_PF_P))
773	{
774	uint64_t fPageGst;
775	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, NULL);
776	if ( RT_SUCCESS(rc)
777	&& !(fPageGst & X86_PTE_RW))
778	{
779	rc = PGMInterpretInstruction(pVM, pRegFrame, pvFault);
780	if (RT_SUCCESS(rc))
781	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eWPEmulInRZ);
782	else
783	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eWPEmulToR3);
784	return rc;
785	}
786	AssertMsgFailed(("Unexpected r/w page %RGv flag=%x rc=%Rrc\n", pvFault, (uint32_t)fPageGst, rc));
787	}
788	}
789
790	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
791	# ifdef VBOX_STRICT
792	/*
793	* Check for VMM page flags vs. Guest page flags consistency.
794	* Currently only for debug purposes.
795	*/
796	if (RT_SUCCESS(rc))
797	{
798	/* Get guest page flags. */
799	uint64_t fPageGst;
800	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, NULL);
801	if (RT_SUCCESS(rc))
802	{
803	uint64_t fPageShw;
804	rc = PGMShwGetPage(pVM, pvFault, &fPageShw, NULL);
805
806	/*
807	* Compare page flags.
808	* Note: we have AVL, A, D bits desynched.
809	*/
810	AssertMsg((fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)) == (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)),
811	("Page flags mismatch! pvFault=%RGv GCPhys=%RGp fPageShw=%08llx fPageGst=%08llx\n", pvFault, GCPhys, fPageShw, fPageGst));
812	}
813	else
814	AssertMsgFailed(("PGMGstGetPage rc=%Rrc\n", rc));
815	}
816	else
817	AssertMsgFailed(("PGMGCGetPage rc=%Rrc\n", rc));
818	# endif /* VBOX_STRICT */
819	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
820	}
821	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeOutOfSync, c);
822	# endif /* PGM_OUT_OF_SYNC_IN_GC */
823	}
824	else
825	{
826	/*
827	* Page not present in Guest OS or invalid page table address.
828	* This is potential virtual page access handler food.
829	*
830	* For the present we'll say that our access handlers don't
831	* work for this case - we've already discarded the page table
832	* not present case which is identical to this.
833	*
834	* When we perchance find we need this, we will probably have AVL
835	* trees (offset based) to operate on and we can measure their speed
836	* agains mapping a page table and probably rearrange this handling
837	* a bit. (Like, searching virtual ranges before checking the
838	* physical address.)
839	*/
840	}
841	}
842
843
844	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
845	/*
846	* Conclusion, this is a guest trap.
847	*/
848	LogFlow(("PGM: Unhandled #PF -> route trap to recompiler!\n"));
849	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eGuestPFUnh);
850	return VINF_EM_RAW_GUEST_TRAP;
851	# else
852	/* present, but not a monitored page; perhaps the guest is probing physical memory */
853	return VINF_EM_RAW_EMULATE_INSTR;
854	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
855
856
857	# else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
858
859	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
860	return VERR_INTERNAL_ERROR;
861	# endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
862	}
863	#endif /* !IN_RING3 */
864
865
866	/**
867	* Emulation of the invlpg instruction.
868	*
869	*
870	* @returns VBox status code.
871	*
872	* @param pVM VM handle.
873	* @param GCPtrPage Page to invalidate.
874	*
875	* @remark ASSUMES that the guest is updating before invalidating. This order
876	* isn't required by the CPU, so this is speculative and could cause
877	* trouble.
878	*
879	* @todo Flush page or page directory only if necessary!
880	* @todo Add a #define for simply invalidating the page.
881	*/
882	PGM_BTH_DECL(int, InvalidatePage)(PVM pVM, RTGCPTR GCPtrPage)
883	{
884	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
885	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
886	&& PGM_SHW_TYPE != PGM_TYPE_EPT
887	int rc;
888
889	LogFlow(("InvalidatePage %RGv\n", GCPtrPage));
890	/*
891	* Get the shadow PD entry and skip out if this PD isn't present.
892	* (Guessing that it is frequent for a shadow PDE to not be present, do this first.)
893	*/
894	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
895	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
896	PX86PDE pPdeDst = &pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst];
897	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
898	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT; /* no mask; flat index into the 2048 entry array. */
899	const unsigned iPdpte = (GCPtrPage >> X86_PDPT_SHIFT); NOREF(iPdpte);
900	PX86PDEPAE pPdeDst = &pVM->pgm.s.CTXMID(ap,PaePDs[0])->a[iPDDst];
901	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(&pVM->pgm.s);
902
903	/* If the shadow PDPE isn't present, then skip the invalidate. */
904	if (!pPdptDst->a[iPdpte].n.u1Present)
905	{
906	Assert(!(pPdptDst->a[iPdpte].u & PGM_PLXFLAGS_MAPPING));
907	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
908	return VINF_SUCCESS;
909	}
910
911	# else /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
912	/* PML4 */
913	AssertReturn(pVM->pgm.s.pShwPaePml4R3, VERR_INTERNAL_ERROR);
914
915	const unsigned iPml4 = (GCPtrPage >> X86_PML4_SHIFT) & X86_PML4_MASK;
916	const unsigned iPdpte = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
917	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
918	PX86PDPAE pPDDst;
919	PX86PDPT pPdptDst;
920	PX86PML4E pPml4eDst;
921	rc = pgmShwGetLongModePDPtr(pVM, GCPtrPage, &pPml4eDst, &pPdptDst, &pPDDst);
922	if (rc != VINF_SUCCESS)
923	{
924	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT \|\| rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
925	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
926	if (!VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3))
927	PGM_INVL_GUEST_TLBS();
928	return VINF_SUCCESS;
929	}
930	Assert(pPDDst);
931
932	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
933	PX86PDPE pPdpeDst = &pPdptDst->a[iPdpte];
934
935	if (!pPdpeDst->n.u1Present)
936	{
937	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
938	if (!VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3))
939	PGM_INVL_GUEST_TLBS();
940	return VINF_SUCCESS;
941	}
942
943	# endif /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
944
945	const SHWPDE PdeDst = *pPdeDst;
946	if (!PdeDst.n.u1Present)
947	{
948	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
949	return VINF_SUCCESS;
950	}
951
952	/*
953	* Get the guest PD entry and calc big page.
954	*/
955	# if PGM_GST_TYPE == PGM_TYPE_32BIT
956	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(&pVM->pgm.s);
957	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
958	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
959	# else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
960	unsigned iPDSrc;
961	# if PGM_GST_TYPE == PGM_TYPE_PAE
962	X86PDPE PdpeSrc;
963	PX86PDPAE pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtrPage, &iPDSrc, &PdpeSrc);
964	# else /* AMD64 */
965	PX86PML4E pPml4eSrc;
966	X86PDPE PdpeSrc;
967	PX86PDPAE pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
968	# endif
969	GSTPDE PdeSrc;
970
971	if (pPDSrc)
972	PdeSrc = pPDSrc->a[iPDSrc];
973	else
974	PdeSrc.u = 0;
975	# endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
976
977	# if PGM_GST_TYPE == PGM_TYPE_AMD64
978	const bool fIsBigPage = PdeSrc.b.u1Size;
979	# else
980	const bool fIsBigPage = PdeSrc.b.u1Size && (CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
981	# endif
982
983	# ifdef IN_RING3
984	/*
985	* If a CR3 Sync is pending we may ignore the invalidate page operation
986	* depending on the kind of sync and if it's a global page or not.
987	* This doesn't make sense in GC/R0 so we'll skip it entirely there.
988	*/
989	# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
990	if ( VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3)
991	\|\| ( VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
992	&& fIsBigPage
993	&& PdeSrc.b.u1Global
994	)
995	)
996	# else
997	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL) )
998	# endif
999	{
1000	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
1001	return VINF_SUCCESS;
1002	}
1003	# endif /* IN_RING3 */
1004
1005	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1006	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1007
1008	/* Fetch the pgm pool shadow descriptor. */
1009	PPGMPOOLPAGE pShwPdpt = pgmPoolGetPageByHCPhys(pVM, pPml4eDst->u & X86_PML4E_PG_MASK);
1010	Assert(pShwPdpt);
1011
1012	/* Fetch the pgm pool shadow descriptor. */
1013	PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(pVM, pPdptDst->a[iPdpte].u & SHW_PDPE_PG_MASK);
1014	Assert(pShwPde);
1015
1016	Assert(pPml4eDst->n.u1Present && (pPml4eDst->u & SHW_PDPT_MASK));
1017	RTGCPHYS GCPhysPdpt = pPml4eSrc->u & X86_PML4E_PG_MASK;
1018
1019	if ( !pPml4eSrc->n.u1Present
1020	\|\| pShwPdpt->GCPhys != GCPhysPdpt)
1021	{
1022	LogFlow(("InvalidatePage: Out-of-sync PML4E (P/GCPhys) at %RGv GCPhys=%RGp vs %RGp Pml4eSrc=%RX64 Pml4eDst=%RX64\n",
1023	GCPtrPage, pShwPdpt->GCPhys, GCPhysPdpt, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
1024	pgmPoolFreeByPage(pPool, pShwPdpt, pVM->pgm.s.CTX_SUFF(pShwAmd64CR3)->idx, iPml4);
1025	pPml4eDst->u = 0;
1026	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNPs));
1027	PGM_INVL_GUEST_TLBS();
1028	return VINF_SUCCESS;
1029	}
1030	if ( pPml4eSrc->n.u1User != pPml4eDst->n.u1User
1031	\|\| (!pPml4eSrc->n.u1Write && pPml4eDst->n.u1Write))
1032	{
1033	/*
1034	* Mark not present so we can resync the PML4E when it's used.
1035	*/
1036	LogFlow(("InvalidatePage: Out-of-sync PML4E at %RGv Pml4eSrc=%RX64 Pml4eDst=%RX64\n",
1037	GCPtrPage, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
1038	pgmPoolFreeByPage(pPool, pShwPdpt, pVM->pgm.s.CTX_SUFF(pShwAmd64CR3)->idx, iPml4);
1039	pPml4eDst->u = 0;
1040	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1041	PGM_INVL_GUEST_TLBS();
1042	}
1043	else if (!pPml4eSrc->n.u1Accessed)
1044	{
1045	/*
1046	* Mark not present so we can set the accessed bit.
1047	*/
1048	LogFlow(("InvalidatePage: Out-of-sync PML4E (A) at %RGv Pml4eSrc=%RX64 Pml4eDst=%RX64\n",
1049	GCPtrPage, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
1050	pgmPoolFreeByPage(pPool, pShwPdpt, pVM->pgm.s.CTX_SUFF(pShwAmd64CR3)->idx, iPml4);
1051	pPml4eDst->u = 0;
1052	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNAs));
1053	PGM_INVL_GUEST_TLBS();
1054	}
1055
1056	/* Check if the PDPT entry has changed. */
1057	Assert(pPdpeDst->n.u1Present && pPdpeDst->u & SHW_PDPT_MASK);
1058	RTGCPHYS GCPhysPd = PdpeSrc.u & GST_PDPE_PG_MASK;
1059	if ( !PdpeSrc.n.u1Present
1060	\|\| pShwPde->GCPhys != GCPhysPd)
1061	{
1062	LogFlow(("InvalidatePage: Out-of-sync PDPE (P/GCPhys) at %RGv GCPhys=%RGp vs %RGp PdpeSrc=%RX64 PdpeDst=%RX64\n",
1063	GCPtrPage, pShwPde->GCPhys, GCPhysPd, (uint64_t)PdpeSrc.u, (uint64_t)pPdpeDst->u));
1064	pgmPoolFreeByPage(pPool, pShwPde, pShwPdpt->idx, iPdpte);
1065	pPdpeDst->u = 0;
1066	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNPs));
1067	PGM_INVL_GUEST_TLBS();
1068	return VINF_SUCCESS;
1069	}
1070	if ( PdpeSrc.lm.u1User != pPdpeDst->lm.u1User
1071	\|\| (!PdpeSrc.lm.u1Write && pPdpeDst->lm.u1Write))
1072	{
1073	/*
1074	* Mark not present so we can resync the PDPTE when it's used.
1075	*/
1076	LogFlow(("InvalidatePage: Out-of-sync PDPE at %RGv PdpeSrc=%RX64 PdpeDst=%RX64\n",
1077	GCPtrPage, (uint64_t)PdpeSrc.u, (uint64_t)pPdpeDst->u));
1078	pgmPoolFreeByPage(pPool, pShwPde, pShwPdpt->idx, iPdpte);
1079	pPdpeDst->u = 0;
1080	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1081	PGM_INVL_GUEST_TLBS();
1082	}
1083	else if (!PdpeSrc.lm.u1Accessed)
1084	{
1085	/*
1086	* Mark not present so we can set the accessed bit.
1087	*/
1088	LogFlow(("InvalidatePage: Out-of-sync PDPE (A) at %RGv PdpeSrc=%RX64 PdpeDst=%RX64\n",
1089	GCPtrPage, (uint64_t)PdpeSrc.u, (uint64_t)pPdpeDst->u));
1090	pgmPoolFreeByPage(pPool, pShwPde, pShwPdpt->idx, iPdpte);
1091	pPdpeDst->u = 0;
1092	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNAs));
1093	PGM_INVL_GUEST_TLBS();
1094	}
1095	# endif /* PGM_GST_TYPE == PGM_TYPE_AMD64 */
1096
1097	# if PGM_GST_TYPE == PGM_TYPE_PAE
1098	/*
1099	* Update the shadow PDPE and free all the shadow PD entries if the PDPE is marked not present.
1100	* Note: This shouldn't actually be necessary as we monitor the PDPT page for changes.
1101	*/
1102	if (!pPDSrc)
1103	{
1104	/* Guest PDPE not present */
1105	PX86PDPAE pPDPAE = pVM->pgm.s.CTXMID(ap,PaePDs)[0]; /* root of the 2048 PDE array */
1106	PX86PDEPAE pPDEDst = &pPDPAE->a[iPdpte * X86_PG_PAE_ENTRIES];
1107	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1108
1109	Assert(!PdpeSrc.n.u1Present);
1110	LogFlow(("InvalidatePage: guest PDPE %d not present; clear shw pdpe\n", iPdpte));
1111
1112	/* for each page directory entry */
1113	for (unsigned iPD = 0; iPD < X86_PG_PAE_ENTRIES; iPD++)
1114	{
1115	if ( pPDEDst[iPD].n.u1Present
1116	&& !(pPDEDst[iPD].u & PGM_PDFLAGS_MAPPING))
1117	{
1118	pgmPoolFreeByPage(pPool, pgmPoolGetPage(pPool, pPDEDst[iPD].u & SHW_PDE_PG_MASK), SHW_POOL_ROOT_IDX, iPdpte * X86_PG_PAE_ENTRIES + iPD);
1119	pPDEDst[iPD].u = 0;
1120	}
1121	}
1122	if (!(pPdptDst->a[iPdpte].u & PGM_PLXFLAGS_MAPPING))
1123	pPdptDst->a[iPdpte].n.u1Present = 0;
1124	PGM_INVL_GUEST_TLBS();
1125	}
1126	AssertMsg(pVM->pgm.s.fMappingsFixed \|\| (PdpeSrc.u & X86_PDPE_PG_MASK) == pVM->pgm.s.aGCPhysGstPaePDsMonitored[iPdpte], ("%RGp vs %RGp (mon)\n", (PdpeSrc.u & X86_PDPE_PG_MASK), pVM->pgm.s.aGCPhysGstPaePDsMonitored[iPdpte]));
1127	# endif
1128
1129
1130	/*
1131	* Deal with the Guest PDE.
1132	*/
1133	rc = VINF_SUCCESS;
1134	if (PdeSrc.n.u1Present)
1135	{
1136	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
1137	{
1138	/*
1139	* Conflict - Let SyncPT deal with it to avoid duplicate code.
1140	*/
1141	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1142	Assert(PGMGetGuestMode(pVM) <= PGMMODE_PAE);
1143	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, GCPtrPage);
1144	}
1145	else if ( PdeSrc.n.u1User != PdeDst.n.u1User
1146	\|\| (!PdeSrc.n.u1Write && PdeDst.n.u1Write))
1147	{
1148	/*
1149	* Mark not present so we can resync the PDE when it's used.
1150	*/
1151	LogFlow(("InvalidatePage: Out-of-sync at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
1152	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1153	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1154	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1155	# else
1156	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1157	# endif
1158	pPdeDst->u = 0;
1159	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1160	PGM_INVL_GUEST_TLBS();
1161	}
1162	else if (!PdeSrc.n.u1Accessed)
1163	{
1164	/*
1165	* Mark not present so we can set the accessed bit.
1166	*/
1167	LogFlow(("InvalidatePage: Out-of-sync (A) at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
1168	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1169	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1170	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1171	# else
1172	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1173	# endif
1174	pPdeDst->u = 0;
1175	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNAs));
1176	PGM_INVL_GUEST_TLBS();
1177	}
1178	else if (!fIsBigPage)
1179	{
1180	/*
1181	* 4KB - page.
1182	*/
1183	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1184	RTGCPHYS GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
1185	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1186	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1187	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE/2);
1188	# endif
1189	if (pShwPage->GCPhys == GCPhys)
1190	{
1191	# if 0 /* likely cause of a major performance regression; must be SyncPageWorkerTrackDeref then */
1192	const unsigned iPTEDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1193	PSHWPT pPT = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1194	if (pPT->a[iPTEDst].n.u1Present)
1195	{
1196	# ifdef PGMPOOL_WITH_USER_TRACKING
1197	/* This is very unlikely with caching/monitoring enabled. */
1198	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPT->a[iPTEDst].u & SHW_PTE_PG_MASK);
1199	# endif
1200	pPT->a[iPTEDst].u = 0;
1201	}
1202	# else /* Syncing it here isn't 100% safe and it's probably not worth spending time syncing it. */
1203	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, 1, 0);
1204	if (RT_SUCCESS(rc))
1205	rc = VINF_SUCCESS;
1206	# endif
1207	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePage4KBPages));
1208	PGM_INVL_PG(GCPtrPage);
1209	}
1210	else
1211	{
1212	/*
1213	* The page table address changed.
1214	*/
1215	LogFlow(("InvalidatePage: Out-of-sync at %RGp PdeSrc=%RX64 PdeDst=%RX64 ShwGCPhys=%RGp iPDDst=%#x\n",
1216	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, iPDDst));
1217	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1218	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1219	# else
1220	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1221	# endif
1222	pPdeDst->u = 0;
1223	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1224	PGM_INVL_GUEST_TLBS();
1225	}
1226	}
1227	else
1228	{
1229	/*
1230	* 2/4MB - page.
1231	*/
1232	/* Before freeing the page, check if anything really changed. */
1233	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1234	RTGCPHYS GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
1235	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1236	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1237	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
1238	# endif
1239	if ( pShwPage->GCPhys == GCPhys
1240	&& pShwPage->enmKind == BTH_PGMPOOLKIND_PT_FOR_BIG)
1241	{
1242	/* ASSUMES a the given bits are identical for 4M and normal PDEs */
1243	/** @todo PAT */
1244	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD))
1245	== (PdeDst.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD))
1246	&& ( PdeSrc.b.u1Dirty /** @todo rainy day: What about read-only 4M pages? not very common, but still... */
1247	\|\| (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)))
1248	{
1249	LogFlow(("Skipping flush for big page containing %RGv (PD=%X .u=%RX64)-> nothing has changed!\n", GCPtrPage, iPDSrc, PdeSrc.u));
1250	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePage4MBPagesSkip));
1251	return VINF_SUCCESS;
1252	}
1253	}
1254
1255	/*
1256	* Ok, the page table is present and it's been changed in the guest.
1257	* If we're in host context, we'll just mark it as not present taking the lazy approach.
1258	* We could do this for some flushes in GC too, but we need an algorithm for
1259	* deciding which 4MB pages containing code likely to be executed very soon.
1260	*/
1261	LogFlow(("InvalidatePage: Out-of-sync PD at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
1262	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1263	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1264	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1265	# else
1266	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1267	# endif
1268	pPdeDst->u = 0;
1269	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePage4MBPages));
1270	PGM_INVL_BIG_PG(GCPtrPage);
1271	}
1272	}
1273	else
1274	{
1275	/*
1276	* Page directory is not present, mark shadow PDE not present.
1277	*/
1278	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
1279	{
1280	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1281	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1282	# else
1283	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1284	# endif
1285	pPdeDst->u = 0;
1286	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNPs));
1287	PGM_INVL_PG(GCPtrPage);
1288	}
1289	else
1290	{
1291	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1292	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDMappings));
1293	}
1294	}
1295
1296	return rc;
1297
1298	#else /* guest real and protected mode */
1299	/* There's no such thing as InvalidatePage when paging is disabled, so just ignore. */
1300	return VINF_SUCCESS;
1301	#endif
1302	}
1303
1304
1305	#ifdef PGMPOOL_WITH_USER_TRACKING
1306	/**
1307	* Update the tracking of shadowed pages.
1308	*
1309	* @param pVM The VM handle.
1310	* @param pShwPage The shadow page.
1311	* @param HCPhys The physical page we is being dereferenced.
1312	*/
1313	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVM pVM, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys)
1314	{
1315	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1316	STAM_PROFILE_START(&pVM->pgm.s.StatTrackDeref, a);
1317	LogFlow(("SyncPageWorkerTrackDeref: Damn HCPhys=%RHp pShwPage->idx=%#x!!!\n", HCPhys, pShwPage->idx));
1318
1319	/** @todo If this turns out to be a bottle neck (very likely) two things can be done:
1320	* 1. have a medium sized HCPhys -> GCPhys TLB (hash?)
1321	* 2. write protect all shadowed pages. I.e. implement caching.
1322	*/
1323	/*
1324	* Find the guest address.
1325	*/
1326	for (PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
1327	pRam;
1328	pRam = pRam->CTX_SUFF(pNext))
1329	{
1330	unsigned iPage = pRam->cb >> PAGE_SHIFT;
1331	while (iPage-- > 0)
1332	{
1333	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
1334	{
1335	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1336	pgmTrackDerefGCPhys(pPool, pShwPage, &pRam->aPages[iPage]);
1337	pShwPage->cPresent--;
1338	pPool->cPresent--;
1339	STAM_PROFILE_STOP(&pVM->pgm.s.StatTrackDeref, a);
1340	return;
1341	}
1342	}
1343	}
1344
1345	for (;;)
1346	AssertReleaseMsgFailed(("HCPhys=%RHp wasn't found!\n", HCPhys));
1347	# else /* !PGMPOOL_WITH_GCPHYS_TRACKING */
1348	pShwPage->cPresent--;
1349	pVM->pgm.s.CTX_SUFF(pPool)->cPresent--;
1350	# endif /* !PGMPOOL_WITH_GCPHYS_TRACKING */
1351	}
1352
1353
1354	/**
1355	* Update the tracking of shadowed pages.
1356	*
1357	* @param pVM The VM handle.
1358	* @param pShwPage The shadow page.
1359	* @param u16 The top 16-bit of the pPage->HCPhys.
1360	* @param pPage Pointer to the guest page. this will be modified.
1361	* @param iPTDst The index into the shadow table.
1362	*/
1363	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackAddref)(PVM pVM, PPGMPOOLPAGE pShwPage, uint16_t u16, PPGMPAGE pPage, const unsigned iPTDst)
1364	{
1365	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1366	/*
1367	* We're making certain assumptions about the placement of cRef and idx.
1368	*/
1369	Assert(MM_RAM_FLAGS_IDX_SHIFT == 48);
1370	Assert(MM_RAM_FLAGS_CREFS_SHIFT > MM_RAM_FLAGS_IDX_SHIFT);
1371
1372	/*
1373	* Just deal with the simple first time here.
1374	*/
1375	if (!u16)
1376	{
1377	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackVirgin);
1378	u16 = (1 << (MM_RAM_FLAGS_CREFS_SHIFT - MM_RAM_FLAGS_IDX_SHIFT)) \| pShwPage->idx;
1379	}
1380	else
1381	u16 = pgmPoolTrackPhysExtAddref(pVM, u16, pShwPage->idx);
1382
1383	/* write back, trying to be clever... */
1384	Log2(("SyncPageWorkerTrackAddRef: u16=%#x pPage->HCPhys=%RHp->%RHp iPTDst=%#x\n",
1385	u16, pPage->HCPhys, (pPage->HCPhys & MM_RAM_FLAGS_NO_REFS_MASK) \| ((uint64_t)u16 << MM_RAM_FLAGS_CREFS_SHIFT), iPTDst));
1386	((uint16_t )&pPage->HCPhys + 3) = u16; /** @todo PAGE FLAGS */
1387	# endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
1388
1389	/* update statistics. */
1390	pVM->pgm.s.CTX_SUFF(pPool)->cPresent++;
1391	pShwPage->cPresent++;
1392	if (pShwPage->iFirstPresent > iPTDst)
1393	pShwPage->iFirstPresent = iPTDst;
1394	}
1395	#endif /* PGMPOOL_WITH_USER_TRACKING */
1396
1397
1398	/**
1399	* Creates a 4K shadow page for a guest page.
1400	*
1401	* For 4M pages the caller must convert the PDE4M to a PTE, this includes adjusting the
1402	* physical address. The PdeSrc argument only the flags are used. No page structured
1403	* will be mapped in this function.
1404	*
1405	* @param pVM VM handle.
1406	* @param pPteDst Destination page table entry.
1407	* @param PdeSrc Source page directory entry (i.e. Guest OS page directory entry).
1408	* Can safely assume that only the flags are being used.
1409	* @param PteSrc Source page table entry (i.e. Guest OS page table entry).
1410	* @param pShwPage Pointer to the shadow page.
1411	* @param iPTDst The index into the shadow table.
1412	*
1413	* @remark Not used for 2/4MB pages!
1414	*/
1415	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorker)(PVM pVM, PSHWPTE pPteDst, GSTPDE PdeSrc, GSTPTE PteSrc, PPGMPOOLPAGE pShwPage, unsigned iPTDst)
1416	{
1417	if (PteSrc.n.u1Present)
1418	{
1419	/*
1420	* Find the ram range.
1421	*/
1422	PPGMPAGE pPage;
1423	int rc = pgmPhysGetPageEx(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK, &pPage);
1424	if (RT_SUCCESS(rc))
1425	{
1426	/** @todo investiage PWT, PCD and PAT. */
1427	/*
1428	* Make page table entry.
1429	*/
1430	const RTHCPHYS HCPhys = pPage->HCPhys; /** @todo FLAGS */
1431	SHWPTE PteDst;
1432	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1433	{
1434	/** @todo r=bird: Are we actually handling dirty and access bits for pages with access handlers correctly? No. */
1435	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1436	{
1437	#if PGM_SHW_TYPE == PGM_TYPE_EPT
1438	PteDst.u = (HCPhys & EPT_PTE_PG_MASK);
1439	PteDst.n.u1Present = 1;
1440	PteDst.n.u1Execute = 1;
1441	PteDst.n.u1IgnorePAT = 1;
1442	PteDst.n.u3EMT = VMX_EPT_MEMTYPE_WB;
1443	/* PteDst.n.u1Write = 0 && PteDst.n.u1Size = 0 */
1444	#else
1445	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT \| X86_PTE_RW))
1446	\| (HCPhys & X86_PTE_PAE_PG_MASK);
1447	#endif
1448	}
1449	else
1450	{
1451	LogFlow(("SyncPageWorker: monitored page (%RHp) -> mark not present\n", HCPhys));
1452	PteDst.u = 0;
1453	}
1454	/** @todo count these two kinds. */
1455	}
1456	else
1457	{
1458	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1459	/*
1460	* If the page or page directory entry is not marked accessed,
1461	* we mark the page not present.
1462	*/
1463	if (!PteSrc.n.u1Accessed \|\| !PdeSrc.n.u1Accessed)
1464	{
1465	LogFlow(("SyncPageWorker: page and or page directory not accessed -> mark not present\n"));
1466	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,AccessedPage));
1467	PteDst.u = 0;
1468	}
1469	else
1470	/*
1471	* If the page is not flagged as dirty and is writable, then make it read-only, so we can set the dirty bit
1472	* when the page is modified.
1473	*/
1474	if (!PteSrc.n.u1Dirty && (PdeSrc.n.u1Write & PteSrc.n.u1Write))
1475	{
1476	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyPage));
1477	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT \| X86_PTE_RW))
1478	\| (HCPhys & X86_PTE_PAE_PG_MASK)
1479	\| PGM_PTFLAGS_TRACK_DIRTY;
1480	}
1481	else
1482	#endif
1483	{
1484	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyPageSkipped));
1485	#if PGM_SHW_TYPE == PGM_TYPE_EPT
1486	PteDst.u = (HCPhys & EPT_PTE_PG_MASK);
1487	PteDst.n.u1Present = 1;
1488	PteDst.n.u1Write = 1;
1489	PteDst.n.u1Execute = 1;
1490	PteDst.n.u1IgnorePAT = 1;
1491	PteDst.n.u3EMT = VMX_EPT_MEMTYPE_WB;
1492	/* PteDst.n.u1Size = 0 */
1493	#else
1494	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT))
1495	\| (HCPhys & X86_PTE_PAE_PG_MASK);
1496	#endif
1497	}
1498	}
1499
1500	#ifdef PGMPOOL_WITH_USER_TRACKING
1501	/*
1502	* Keep user track up to date.
1503	*/
1504	if (PteDst.n.u1Present)
1505	{
1506	if (!pPteDst->n.u1Present)
1507	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst);
1508	else if ((pPteDst->u & SHW_PTE_PG_MASK) != (PteDst.u & SHW_PTE_PG_MASK))
1509	{
1510	Log2(("SyncPageWorker: deref! *pPteDst=%RX64 PteDst=%RX64\n", (uint64_t)pPteDst->u, (uint64_t)PteDst.u));
1511	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1512	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst);
1513	}
1514	}
1515	else if (pPteDst->n.u1Present)
1516	{
1517	Log2(("SyncPageWorker: deref! *pPteDst=%RX64\n", (uint64_t)pPteDst->u));
1518	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1519	}
1520	#endif /* PGMPOOL_WITH_USER_TRACKING */
1521
1522	/*
1523	* Update statistics and commit the entry.
1524	*/
1525	if (!PteSrc.n.u1Global)
1526	pShwPage->fSeenNonGlobal = true;
1527	*pPteDst = PteDst;
1528	}
1529	/* else MMIO or invalid page, we must handle them manually in the #PF handler. */
1530	/** @todo count these. */
1531	}
1532	else
1533	{
1534	/*
1535	* Page not-present.
1536	*/
1537	LogFlow(("SyncPageWorker: page not present in Pte\n"));
1538	#ifdef PGMPOOL_WITH_USER_TRACKING
1539	/* Keep user track up to date. */
1540	if (pPteDst->n.u1Present)
1541	{
1542	Log2(("SyncPageWorker: deref! *pPteDst=%RX64\n", (uint64_t)pPteDst->u));
1543	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1544	}
1545	#endif /* PGMPOOL_WITH_USER_TRACKING */
1546	pPteDst->u = 0;
1547	/** @todo count these. */
1548	}
1549	}
1550
1551
1552	/**
1553	* Syncs a guest OS page.
1554	*
1555	* There are no conflicts at this point, neither is there any need for
1556	* page table allocations.
1557	*
1558	* @returns VBox status code.
1559	* @returns VINF_PGM_SYNCPAGE_MODIFIED_PDE if it modifies the PDE in any way.
1560	* @param pVM VM handle.
1561	* @param PdeSrc Page directory entry of the guest.
1562	* @param GCPtrPage Guest context page address.
1563	* @param cPages Number of pages to sync (PGM_SYNC_N_PAGES) (default=1).
1564	* @param uErr Fault error (X86_TRAP_PF_*).
1565	*/
1566	PGM_BTH_DECL(int, SyncPage)(PVM pVM, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr)
1567	{
1568	LogFlow(("SyncPage: GCPtrPage=%RGv cPages=%u uErr=%#x\n", GCPtrPage, cPages, uErr));
1569
1570	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
1571	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
1572	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
1573	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
1574	&& PGM_SHW_TYPE != PGM_TYPE_EPT
1575
1576	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
1577	bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
1578	# endif
1579
1580	/*
1581	* Assert preconditions.
1582	*/
1583	Assert(PdeSrc.n.u1Present);
1584	Assert(cPages);
1585	STAM_COUNTER_INC(&pVM->pgm.s.StatSyncPagePD[(GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK]);
1586
1587	/*
1588	* Get the shadow PDE, find the shadow page table in the pool.
1589	*/
1590	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1591	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
1592	X86PDE PdeDst = pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst];
1593	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1594	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
1595	const unsigned iPdpte = (GCPtrPage >> X86_PDPT_SHIFT); NOREF(iPdpte); /* no mask; flat index into the 2048 entry array. */
1596	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(&pVM->pgm.s); NOREF(pPdptDst);
1597	X86PDEPAE PdeDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[iPDDst];
1598	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1599	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
1600	const unsigned iPdpte = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1601	PX86PDPAE pPDDst;
1602	X86PDEPAE PdeDst;
1603	PX86PDPT pPdptDst;
1604
1605	int rc = pgmShwGetLongModePDPtr(pVM, GCPtrPage, NULL, &pPdptDst, &pPDDst);
1606	AssertRCSuccessReturn(rc, rc);
1607	Assert(pPDDst && pPdptDst);
1608	PdeDst = pPDDst->a[iPDDst];
1609	# endif
1610	Assert(PdeDst.n.u1Present);
1611	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1612
1613	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1614	/* Fetch the pgm pool shadow descriptor. */
1615	PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(pVM, pPdptDst->a[iPdpte].u & X86_PDPE_PG_MASK);
1616	Assert(pShwPde);
1617	# endif
1618
1619	/*
1620	* Check that the page is present and that the shadow PDE isn't out of sync.
1621	*/
1622	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1623	const bool fBigPage = PdeSrc.b.u1Size;
1624	# else
1625	const bool fBigPage = PdeSrc.b.u1Size && (CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
1626	# endif
1627	RTGCPHYS GCPhys;
1628	if (!fBigPage)
1629	{
1630	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
1631	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1632	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1633	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE/2);
1634	# endif
1635	}
1636	else
1637	{
1638	GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
1639	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1640	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1641	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
1642	# endif
1643	}
1644	if ( pShwPage->GCPhys == GCPhys
1645	&& PdeSrc.n.u1Present
1646	&& (PdeSrc.n.u1User == PdeDst.n.u1User)
1647	&& (PdeSrc.n.u1Write == PdeDst.n.u1Write \|\| !PdeDst.n.u1Write)
1648	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
1649	&& (!fNoExecuteBitValid \|\| PdeSrc.n.u1NoExecute == PdeDst.n.u1NoExecute)
1650	# endif
1651	)
1652	{
1653	/*
1654	* Check that the PDE is marked accessed already.
1655	* Since we set the accessed bit before getting here on a #PF, this
1656	* check is only meant for dealing with non-#PF'ing paths.
1657	*/
1658	if (PdeSrc.n.u1Accessed)
1659	{
1660	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1661	if (!fBigPage)
1662	{
1663	/*
1664	* 4KB Page - Map the guest page table.
1665	*/
1666	PGSTPT pPTSrc;
1667	int rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
1668	if (RT_SUCCESS(rc))
1669	{
1670	# ifdef PGM_SYNC_N_PAGES
1671	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
1672	if (cPages > 1 && !(uErr & X86_TRAP_PF_P))
1673	{
1674	/*
1675	* This code path is currently only taken when the caller is PGMTrap0eHandler
1676	* for non-present pages!
1677	*
1678	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
1679	* deal with locality.
1680	*/
1681	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1682	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1683	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1684	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
1685	# else
1686	const unsigned offPTSrc = 0;
1687	# endif
1688	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
1689	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
1690	iPTDst = 0;
1691	else
1692	iPTDst -= PGM_SYNC_NR_PAGES / 2;
1693	for (; iPTDst < iPTDstEnd; iPTDst++)
1694	{
1695	if (!pPTDst->a[iPTDst].n.u1Present)
1696	{
1697	GSTPTE PteSrc = pPTSrc->a[offPTSrc + iPTDst];
1698	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(GST_PT_MASK << GST_PT_SHIFT)) \| ((offPTSrc + iPTDst) << PAGE_SHIFT);
1699	NOREF(GCPtrCurPage);
1700	#ifndef IN_RING0
1701	/*
1702	* Assuming kernel code will be marked as supervisor - and not as user level
1703	* and executed using a conforming code selector - And marked as readonly.
1704	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
1705	*/
1706	PPGMPAGE pPage;
1707	if ( ((PdeSrc.u & PteSrc.u) & (X86_PTE_RW \| X86_PTE_US))
1708	\|\| iPTDst == ((GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK) /* always sync GCPtrPage */
1709	\|\| !CSAMDoesPageNeedScanning(pVM, (RTRCPTR)GCPtrCurPage)
1710	\|\| ( (pPage = pgmPhysGetPage(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK))
1711	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1712	)
1713	#endif /* else: CSAM not active */
1714	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1715	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
1716	GCPtrCurPage, PteSrc.n.u1Present,
1717	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1718	PteSrc.n.u1User & PdeSrc.n.u1User,
1719	(uint64_t)PteSrc.u,
1720	(uint64_t)pPTDst->a[iPTDst].u,
1721	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1722	}
1723	}
1724	}
1725	else
1726	# endif /* PGM_SYNC_N_PAGES */
1727	{
1728	const unsigned iPTSrc = (GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK;
1729	GSTPTE PteSrc = pPTSrc->a[iPTSrc];
1730	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1731	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1732	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s\n",
1733	GCPtrPage, PteSrc.n.u1Present,
1734	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1735	PteSrc.n.u1User & PdeSrc.n.u1User,
1736	(uint64_t)PteSrc.u,
1737	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1738	}
1739	}
1740	else /* MMIO or invalid page: emulated in #PF handler. */
1741	{
1742	LogFlow(("PGM_GCPHYS_2_PTR %RGp failed with %Rrc\n", GCPhys, rc));
1743	Assert(!pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK].n.u1Present);
1744	}
1745	}
1746	else
1747	{
1748	/*
1749	* 4/2MB page - lazy syncing shadow 4K pages.
1750	* (There are many causes of getting here, it's no longer only CSAM.)
1751	*/
1752	/* Calculate the GC physical address of this 4KB shadow page. */
1753	RTGCPHYS GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc) \| (GCPtrPage & GST_BIG_PAGE_OFFSET_MASK);
1754	/* Find ram range. */
1755	PPGMPAGE pPage;
1756	int rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
1757	if (RT_SUCCESS(rc))
1758	{
1759	/*
1760	* Make shadow PTE entry.
1761	*/
1762	const RTHCPHYS HCPhys = pPage->HCPhys; /** @todo PAGE FLAGS */
1763	SHWPTE PteDst;
1764	PteDst.u = (PdeSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT))
1765	\| (HCPhys & X86_PTE_PAE_PG_MASK);
1766	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1767	{
1768	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1769	PteDst.n.u1Write = 0;
1770	else
1771	PteDst.u = 0;
1772	}
1773	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1774	# ifdef PGMPOOL_WITH_USER_TRACKING
1775	if (PteDst.n.u1Present && !pPTDst->a[iPTDst].n.u1Present)
1776	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst);
1777	# endif
1778	pPTDst->a[iPTDst] = PteDst;
1779
1780
1781	/*
1782	* If the page is not flagged as dirty and is writable, then make it read-only
1783	* at PD level, so we can set the dirty bit when the page is modified.
1784	*
1785	* ASSUMES that page access handlers are implemented on page table entry level.
1786	* Thus we will first catch the dirty access and set PDE.D and restart. If
1787	* there is an access handler, we'll trap again and let it work on the problem.
1788	*/
1789	/** @todo r=bird: figure out why we need this here, SyncPT should've taken care of this already.
1790	* As for invlpg, it simply frees the whole shadow PT.
1791	* ...It's possibly because the guest clears it and the guest doesn't really tell us... */
1792	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
1793	{
1794	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyPageBig));
1795	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
1796	PdeDst.n.u1Write = 0;
1797	}
1798	else
1799	{
1800	PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
1801	PdeDst.n.u1Write = PdeSrc.n.u1Write;
1802	}
1803	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1804	pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst] = PdeDst;
1805	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1806	pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[iPDDst] = PdeDst;
1807	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1808	pPDDst->a[iPDDst] = PdeDst;
1809	# endif
1810	Log2(("SyncPage: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} GCPhys=%RGp%s\n",
1811	GCPtrPage, PdeSrc.n.u1Present, PdeSrc.n.u1Write, PdeSrc.n.u1User, (uint64_t)PdeSrc.u, GCPhys,
1812	PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1813	}
1814	else
1815	LogFlow(("PGM_GCPHYS_2_PTR %RGp (big) failed with %Rrc\n", GCPhys, rc));
1816	}
1817	return VINF_SUCCESS;
1818	}
1819	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPagePDNAs));
1820	}
1821	else
1822	{
1823	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPagePDOutOfSync));
1824	Log2(("SyncPage: Out-Of-Sync PDE at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
1825	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1826	}
1827
1828	/*
1829	* Mark the PDE not present. Restart the instruction and let #PF call SyncPT.
1830	* Yea, I'm lazy.
1831	*/
1832	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1833	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1834	pgmPoolFreeByPage(pPool, pShwPage, pShwPde->idx, iPDDst);
1835	# else
1836	pgmPoolFreeByPage(pPool, pShwPage, SHW_POOL_ROOT_IDX, iPDDst);
1837	# endif
1838
1839	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1840	pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst].u = 0;
1841	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1842	pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[iPDDst].u = 0;
1843	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1844	pPDDst->a[iPDDst].u = 0;
1845	# endif
1846	PGM_INVL_GUEST_TLBS();
1847	return VINF_PGM_SYNCPAGE_MODIFIED_PDE;
1848
1849	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
1850	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
1851	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT)
1852
1853	# ifdef PGM_SYNC_N_PAGES
1854	/*
1855	* Get the shadow PDE, find the shadow page table in the pool.
1856	*/
1857	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1858	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
1859	X86PDE PdeDst = pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst];
1860	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1861	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT; /* no mask; flat index into the 2048 entry array. */
1862	X86PDEPAE PdeDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[iPDDst];
1863	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1864	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
1865	const unsigned iPdpte = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64; NOREF(iPdpte);
1866	PX86PDPAE pPDDst;
1867	X86PDEPAE PdeDst;
1868	PX86PDPT pPdptDst;
1869
1870	int rc = pgmShwGetLongModePDPtr(pVM, GCPtrPage, NULL, &pPdptDst, &pPDDst);
1871	AssertRCSuccessReturn(rc, rc);
1872	Assert(pPDDst && pPdptDst);
1873	PdeDst = pPDDst->a[iPDDst];
1874	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
1875	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
1876	PEPTPD pPDDst;
1877	EPTPDE PdeDst;
1878
1879	int rc = pgmShwGetEPTPDPtr(pVM, GCPtrPage, NULL, &pPDDst);
1880	if (rc != VINF_SUCCESS)
1881	{
1882	AssertRC(rc);
1883	return rc;
1884	}
1885	Assert(pPDDst);
1886	PdeDst = pPDDst->a[iPDDst];
1887	# endif
1888	Assert(PdeDst.n.u1Present);
1889	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1890	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1891
1892	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
1893	if (cPages > 1 && !(uErr & X86_TRAP_PF_P))
1894	{
1895	/*
1896	* This code path is currently only taken when the caller is PGMTrap0eHandler
1897	* for non-present pages!
1898	*
1899	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
1900	* deal with locality.
1901	*/
1902	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1903	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
1904	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
1905	iPTDst = 0;
1906	else
1907	iPTDst -= PGM_SYNC_NR_PAGES / 2;
1908	for (; iPTDst < iPTDstEnd; iPTDst++)
1909	{
1910	if (!pPTDst->a[iPTDst].n.u1Present)
1911	{
1912	GSTPTE PteSrc;
1913
1914	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT);
1915
1916	/* Fake the page table entry */
1917	PteSrc.u = GCPtrCurPage;
1918	PteSrc.n.u1Present = 1;
1919	PteSrc.n.u1Dirty = 1;
1920	PteSrc.n.u1Accessed = 1;
1921	PteSrc.n.u1Write = 1;
1922	PteSrc.n.u1User = 1;
1923
1924	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1925
1926	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
1927	GCPtrCurPage, PteSrc.n.u1Present,
1928	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1929	PteSrc.n.u1User & PdeSrc.n.u1User,
1930	(uint64_t)PteSrc.u,
1931	(uint64_t)pPTDst->a[iPTDst].u,
1932	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1933	}
1934	else
1935	Log4(("%RGv iPTDst=%x pPTDst->a[iPTDst] %RX64\n", (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT), iPTDst, pPTDst->a[iPTDst].u));
1936	}
1937	}
1938	else
1939	# endif /* PGM_SYNC_N_PAGES */
1940	{
1941	GSTPTE PteSrc;
1942	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1943	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT);
1944
1945	/* Fake the page table entry */
1946	PteSrc.u = GCPtrCurPage;
1947	PteSrc.n.u1Present = 1;
1948	PteSrc.n.u1Dirty = 1;
1949	PteSrc.n.u1Accessed = 1;
1950	PteSrc.n.u1Write = 1;
1951	PteSrc.n.u1User = 1;
1952	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1953
1954	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}PteDst=%08llx%s\n",
1955	GCPtrPage, PteSrc.n.u1Present,
1956	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1957	PteSrc.n.u1User & PdeSrc.n.u1User,
1958	(uint64_t)PteSrc.u,
1959	(uint64_t)pPTDst->a[iPTDst].u,
1960	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1961	}
1962	return VINF_SUCCESS;
1963
1964	#else
1965	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
1966	return VERR_INTERNAL_ERROR;
1967	#endif
1968	}
1969
1970
1971	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1972	/**
1973	* Investigate page fault and handle write protection page faults caused by
1974	* dirty bit tracking.
1975	*
1976	* @returns VBox status code.
1977	* @param pVM VM handle.
1978	* @param uErr Page fault error code.
1979	* @param pPdeDst Shadow page directory entry.
1980	* @param pPdeSrc Guest page directory entry.
1981	* @param GCPtrPage Guest context page address.
1982	*/
1983	PGM_BTH_DECL(int, CheckPageFault)(PVM pVM, uint32_t uErr, PSHWPDE pPdeDst, PGSTPDE pPdeSrc, RTGCPTR GCPtrPage)
1984	{
1985	bool fWriteProtect = !!(CPUMGetGuestCR0(pVM) & X86_CR0_WP);
1986	bool fUserLevelFault = !!(uErr & X86_TRAP_PF_US);
1987	bool fWriteFault = !!(uErr & X86_TRAP_PF_RW);
1988	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1989	bool fBigPagesSupported = true;
1990	# else
1991	bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
1992	# endif
1993	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
1994	bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
1995	# endif
1996	unsigned uPageFaultLevel;
1997	int rc;
1998
1999	STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2000	LogFlow(("CheckPageFault: GCPtrPage=%RGv uErr=%#x PdeSrc=%08x\n", GCPtrPage, uErr, pPdeSrc->u));
2001
2002	# if PGM_GST_TYPE == PGM_TYPE_PAE \
2003	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
2004
2005	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2006	PX86PML4E pPml4eSrc;
2007	PX86PDPE pPdpeSrc;
2008
2009	pPdpeSrc = pgmGstGetLongModePDPTPtr(&pVM->pgm.s, GCPtrPage, &pPml4eSrc);
2010	Assert(pPml4eSrc);
2011
2012	/*
2013	* Real page fault? (PML4E level)
2014	*/
2015	if ( (uErr & X86_TRAP_PF_RSVD)
2016	\|\| !pPml4eSrc->n.u1Present
2017	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPml4eSrc->n.u1NoExecute)
2018	\|\| (fWriteFault && !pPml4eSrc->n.u1Write && (fUserLevelFault \|\| fWriteProtect))
2019	\|\| (fUserLevelFault && !pPml4eSrc->n.u1User)
2020	)
2021	{
2022	uPageFaultLevel = 0;
2023	goto l_UpperLevelPageFault;
2024	}
2025	Assert(pPdpeSrc);
2026
2027	# else /* PAE */
2028	PX86PDPE pPdpeSrc = pgmGstGetPaePDPEPtr(&pVM->pgm.s, GCPtrPage);
2029	# endif /* PAE */
2030
2031	/*
2032	* Real page fault? (PDPE level)
2033	*/
2034	if ( (uErr & X86_TRAP_PF_RSVD)
2035	\|\| !pPdpeSrc->n.u1Present
2036	# if PGM_GST_TYPE == PGM_TYPE_AMD64 /* NX, r/w, u/s bits in the PDPE are long mode only */
2037	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPdpeSrc->lm.u1NoExecute)
2038	\|\| (fWriteFault && !pPdpeSrc->lm.u1Write && (fUserLevelFault \|\| fWriteProtect))
2039	\|\| (fUserLevelFault && !pPdpeSrc->lm.u1User)
2040	# endif
2041	)
2042	{
2043	uPageFaultLevel = 1;
2044	goto l_UpperLevelPageFault;
2045	}
2046	# endif
2047
2048	/*
2049	* Real page fault? (PDE level)
2050	*/
2051	if ( (uErr & X86_TRAP_PF_RSVD)
2052	\|\| !pPdeSrc->n.u1Present
2053	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2054	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPdeSrc->n.u1NoExecute)
2055	# endif
2056	\|\| (fWriteFault && !pPdeSrc->n.u1Write && (fUserLevelFault \|\| fWriteProtect))
2057	\|\| (fUserLevelFault && !pPdeSrc->n.u1User) )
2058	{
2059	uPageFaultLevel = 2;
2060	goto l_UpperLevelPageFault;
2061	}
2062
2063	/*
2064	* First check the easy case where the page directory has been marked read-only to track
2065	* the dirty bit of an emulated BIG page
2066	*/
2067	if (pPdeSrc->b.u1Size && fBigPagesSupported)
2068	{
2069	/* Mark guest page directory as accessed */
2070	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2071	pPml4eSrc->n.u1Accessed = 1;
2072	pPdpeSrc->lm.u1Accessed = 1;
2073	# endif
2074	pPdeSrc->b.u1Accessed = 1;
2075
2076	/*
2077	* Only write protection page faults are relevant here.
2078	*/
2079	if (fWriteFault)
2080	{
2081	/* Mark guest page directory as dirty (BIG page only). */
2082	pPdeSrc->b.u1Dirty = 1;
2083
2084	if (pPdeDst->n.u1Present && (pPdeDst->u & PGM_PDFLAGS_TRACK_DIRTY))
2085	{
2086	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyPageTrap));
2087
2088	Assert(pPdeSrc->b.u1Write);
2089
2090	pPdeDst->n.u1Write = 1;
2091	pPdeDst->n.u1Accessed = 1;
2092	pPdeDst->au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
2093	PGM_INVL_BIG_PG(GCPtrPage);
2094	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2095	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT;
2096	}
2097	}
2098	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2099	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2100	}
2101	/* else: 4KB page table */
2102
2103	/*
2104	* Map the guest page table.
2105	*/
2106	PGSTPT pPTSrc;
2107	rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & GST_PDE_PG_MASK, &pPTSrc);
2108	if (RT_SUCCESS(rc))
2109	{
2110	/*
2111	* Real page fault?
2112	*/
2113	PGSTPTE pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
2114	const GSTPTE PteSrc = *pPteSrc;
2115	if ( !PteSrc.n.u1Present
2116	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2117	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && PteSrc.n.u1NoExecute)
2118	# endif
2119	\|\| (fWriteFault && !PteSrc.n.u1Write && (fUserLevelFault \|\| fWriteProtect))
2120	\|\| (fUserLevelFault && !PteSrc.n.u1User)
2121	)
2122	{
2123	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyTrackRealPF));
2124	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2125	LogFlow(("CheckPageFault: real page fault at %RGv PteSrc.u=%08x (2)\n", GCPtrPage, PteSrc.u));
2126
2127	/* Check the present bit as the shadow tables can cause different error codes by being out of sync.
2128	* See the 2nd case above as well.
2129	*/
2130	if (pPdeSrc->n.u1Present && pPteSrc->n.u1Present)
2131	TRPMSetErrorCode(pVM, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
2132
2133	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2134	return VINF_EM_RAW_GUEST_TRAP;
2135	}
2136	LogFlow(("CheckPageFault: page fault at %RGv PteSrc.u=%08x\n", GCPtrPage, PteSrc.u));
2137
2138	/*
2139	* Set the accessed bits in the page directory and the page table.
2140	*/
2141	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2142	pPml4eSrc->n.u1Accessed = 1;
2143	pPdpeSrc->lm.u1Accessed = 1;
2144	# endif
2145	pPdeSrc->n.u1Accessed = 1;
2146	pPteSrc->n.u1Accessed = 1;
2147
2148	/*
2149	* Only write protection page faults are relevant here.
2150	*/
2151	if (fWriteFault)
2152	{
2153	/* Write access, so mark guest entry as dirty. */
2154	# ifdef VBOX_WITH_STATISTICS
2155	if (!pPteSrc->n.u1Dirty)
2156	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtiedPage));
2157	else
2158	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,PageAlreadyDirty));
2159	# endif
2160
2161	pPteSrc->n.u1Dirty = 1;
2162
2163	if (pPdeDst->n.u1Present)
2164	{
2165	#ifndef IN_RING0
2166	/* Bail out here as pgmPoolGetPageByHCPhys will return NULL and we'll crash below.
2167	* Our individual shadow handlers will provide more information and force a fatal exit.
2168	*/
2169	if (MMHyperIsInsideArea(pVM, (RTGCPTR)GCPtrPage))
2170	{
2171	LogRel(("CheckPageFault: write to hypervisor region %RGv\n", GCPtrPage));
2172	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2173	return VINF_SUCCESS;
2174	}
2175	#endif
2176	/*
2177	* Map shadow page table.
2178	*/
2179	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, pPdeDst->u & SHW_PDE_PG_MASK);
2180	if (pShwPage)
2181	{
2182	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2183	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2184	if ( pPteDst->n.u1Present /** @todo Optimize accessed bit emulation? */
2185	&& (pPteDst->u & PGM_PTFLAGS_TRACK_DIRTY))
2186	{
2187	LogFlow(("DIRTY page trap addr=%RGv\n", GCPtrPage));
2188	# ifdef VBOX_STRICT
2189	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, pPteSrc->u & GST_PTE_PG_MASK);
2190	if (pPage)
2191	AssertMsg(!PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage),
2192	("Unexpected dirty bit tracking on monitored page %RGv (phys %RGp)!!!!!!\n", GCPtrPage, pPteSrc->u & X86_PTE_PAE_PG_MASK));
2193	# endif
2194	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyPageTrap));
2195
2196	Assert(pPteSrc->n.u1Write);
2197
2198	pPteDst->n.u1Write = 1;
2199	pPteDst->n.u1Dirty = 1;
2200	pPteDst->n.u1Accessed = 1;
2201	pPteDst->au32[0] &= ~PGM_PTFLAGS_TRACK_DIRTY;
2202	PGM_INVL_PG(GCPtrPage);
2203
2204	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2205	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT;
2206	}
2207	}
2208	else
2209	AssertMsgFailed(("pgmPoolGetPageByHCPhys %RGp failed!\n", pPdeDst->u & SHW_PDE_PG_MASK));
2210	}
2211	}
2212	/** @todo Optimize accessed bit emulation? */
2213	# ifdef VBOX_STRICT
2214	/*
2215	* Sanity check.
2216	*/
2217	else if ( !pPteSrc->n.u1Dirty
2218	&& (pPdeSrc->n.u1Write & pPteSrc->n.u1Write)
2219	&& pPdeDst->n.u1Present)
2220	{
2221	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, pPdeDst->u & SHW_PDE_PG_MASK);
2222	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2223	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2224	if ( pPteDst->n.u1Present
2225	&& pPteDst->n.u1Write)
2226	LogFlow(("Writable present page %RGv not marked for dirty bit tracking!!!\n", GCPtrPage));
2227	}
2228	# endif /* VBOX_STRICT */
2229	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2230	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2231	}
2232	AssertRC(rc);
2233	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2234	return rc;
2235
2236
2237	l_UpperLevelPageFault:
2238	/*
2239	* Pagefault detected while checking the PML4E, PDPE or PDE.
2240	* Single exit handler to get rid of duplicate code paths.
2241	*/
2242	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyTrackRealPF));
2243	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2244	Log(("CheckPageFault: real page fault at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2245
2246	if (
2247	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2248	pPml4eSrc->n.u1Present &&
2249	# endif
2250	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
2251	pPdpeSrc->n.u1Present &&
2252	# endif
2253	pPdeSrc->n.u1Present)
2254	{
2255	/* Check the present bit as the shadow tables can cause different error codes by being out of sync. */
2256	if (pPdeSrc->b.u1Size && fBigPagesSupported)
2257	{
2258	TRPMSetErrorCode(pVM, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
2259	}
2260	else
2261	{
2262	/*
2263	* Map the guest page table.
2264	*/
2265	PGSTPT pPTSrc;
2266	rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & GST_PDE_PG_MASK, &pPTSrc);
2267	if (RT_SUCCESS(rc))
2268	{
2269	PGSTPTE pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
2270	const GSTPTE PteSrc = *pPteSrc;
2271	if (pPteSrc->n.u1Present)
2272	TRPMSetErrorCode(pVM, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
2273	}
2274	AssertRC(rc);
2275	}
2276	}
2277	return VINF_EM_RAW_GUEST_TRAP;
2278	}
2279	#endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
2280
2281
2282	/**
2283	* Sync a shadow page table.
2284	*
2285	* The shadow page table is not present. This includes the case where
2286	* there is a conflict with a mapping.
2287	*
2288	* @returns VBox status code.
2289	* @param pVM VM handle.
2290	* @param iPD Page directory index.
2291	* @param pPDSrc Source page directory (i.e. Guest OS page directory).
2292	* Assume this is a temporary mapping.
2293	* @param GCPtrPage GC Pointer of the page that caused the fault
2294	*/
2295	PGM_BTH_DECL(int, SyncPT)(PVM pVM, unsigned iPDSrc, PGSTPD pPDSrc, RTGCPTR GCPtrPage)
2296	{
2297	STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2298	STAM_COUNTER_INC(&pVM->pgm.s.StatSyncPtPD[iPDSrc]);
2299	LogFlow(("SyncPT: GCPtrPage=%RGv\n", GCPtrPage));
2300
2301	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
2302	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
2303	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
2304	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2305	&& PGM_SHW_TYPE != PGM_TYPE_EPT
2306
2307	int rc = VINF_SUCCESS;
2308
2309	/*
2310	* Validate input a little bit.
2311	*/
2312	AssertMsg(iPDSrc == ((GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK), ("iPDSrc=%x GCPtrPage=%RGv\n", iPDSrc, GCPtrPage));
2313	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2314	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
2315	PX86PD pPDDst = pVM->pgm.s.CTXMID(p,32BitPD);
2316	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2317	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT; /* no mask; flat index into the 2048 entry array. */
2318	const unsigned iPdpte = (GCPtrPage >> X86_PDPT_SHIFT); NOREF(iPdpte);
2319	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(&pVM->pgm.s); NOREF(pPdptDst);
2320	PX86PDPAE pPDDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0];
2321	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2322	const unsigned iPdpte = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
2323	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2324	PX86PDPAE pPDDst;
2325	PX86PDPT pPdptDst;
2326	rc = pgmShwGetLongModePDPtr(pVM, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2327	AssertRCSuccessReturn(rc, rc);
2328	Assert(pPDDst);
2329	# endif
2330
2331	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2332	SHWPDE PdeDst = *pPdeDst;
2333
2334	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2335	/* Fetch the pgm pool shadow descriptor. */
2336	PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(pVM, pPdptDst->a[iPdpte].u & X86_PDPE_PG_MASK);
2337	Assert(pShwPde);
2338	# endif
2339
2340	# ifndef PGM_WITHOUT_MAPPINGS
2341	/*
2342	* Check for conflicts.
2343	* GC: In case of a conflict we'll go to Ring-3 and do a full SyncCR3.
2344	* HC: Simply resolve the conflict.
2345	*/
2346	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
2347	{
2348	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
2349	# ifndef IN_RING3
2350	Log(("SyncPT: Conflict at %RGv\n", GCPtrPage));
2351	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2352	return VERR_ADDRESS_CONFLICT;
2353	# else
2354	PPGMMAPPING pMapping = pgmGetMapping(pVM, (RTGCPTR)GCPtrPage);
2355	Assert(pMapping);
2356	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2357	int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2358	# elif PGM_GST_TYPE == PGM_TYPE_PAE
2359	int rc = pgmR3SyncPTResolveConflictPAE(pVM, pMapping, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2360	# else
2361	AssertFailed(); /* can't happen for amd64 */
2362	# endif
2363	if (RT_FAILURE(rc))
2364	{
2365	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2366	return rc;
2367	}
2368	PdeDst = *pPdeDst;
2369	# endif
2370	}
2371	# else /* PGM_WITHOUT_MAPPINGS */
2372	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
2373	# endif /* PGM_WITHOUT_MAPPINGS */
2374	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
2375
2376	/*
2377	* Sync page directory entry.
2378	*/
2379	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
2380	if (PdeSrc.n.u1Present)
2381	{
2382	/*
2383	* Allocate & map the page table.
2384	*/
2385	PSHWPT pPTDst;
2386	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2387	const bool fPageTable = !PdeSrc.b.u1Size;
2388	# else
2389	const bool fPageTable = !PdeSrc.b.u1Size \|\| !(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
2390	# endif
2391	PPGMPOOLPAGE pShwPage;
2392	RTGCPHYS GCPhys;
2393	if (fPageTable)
2394	{
2395	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
2396	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2397	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2398	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE / 2);
2399	# endif
2400	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2401	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, pShwPde->idx, iPDDst, &pShwPage);
2402	# else
2403	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, SHW_POOL_ROOT_IDX, iPDDst, &pShwPage);
2404	# endif
2405	}
2406	else
2407	{
2408	GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
2409	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2410	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
2411	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
2412	# endif
2413	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2414	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_BIG, pShwPde->idx, iPDDst, &pShwPage);
2415	# else
2416	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_BIG, SHW_POOL_ROOT_IDX, iPDDst, &pShwPage);
2417	# endif
2418	}
2419	if (rc == VINF_SUCCESS)
2420	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2421	else if (rc == VINF_PGM_CACHED_PAGE)
2422	{
2423	/*
2424	* The PT was cached, just hook it up.
2425	*/
2426	if (fPageTable)
2427	PdeDst.u = pShwPage->Core.Key
2428	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2429	else
2430	{
2431	PdeDst.u = pShwPage->Core.Key
2432	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2433	/* (see explanation and assumptions further down.) */
2434	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
2435	{
2436	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyPageBig));
2437	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2438	PdeDst.b.u1Write = 0;
2439	}
2440	}
2441	*pPdeDst = PdeDst;
2442	return VINF_SUCCESS;
2443	}
2444	else if (rc == VERR_PGM_POOL_FLUSHED)
2445	{
2446	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
2447	return VINF_PGM_SYNC_CR3;
2448	}
2449	else
2450	AssertMsgFailedReturn(("rc=%Rrc\n", rc), VERR_INTERNAL_ERROR);
2451	PdeDst.u &= X86_PDE_AVL_MASK;
2452	PdeDst.u \|= pShwPage->Core.Key;
2453
2454	/*
2455	* Page directory has been accessed (this is a fault situation, remember).
2456	*/
2457	pPDSrc->a[iPDSrc].n.u1Accessed = 1;
2458	if (fPageTable)
2459	{
2460	/*
2461	* Page table - 4KB.
2462	*
2463	* Sync all or just a few entries depending on PGM_SYNC_N_PAGES.
2464	*/
2465	Log2(("SyncPT: 4K %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx}\n",
2466	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u));
2467	PGSTPT pPTSrc;
2468	rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
2469	if (RT_SUCCESS(rc))
2470	{
2471	/*
2472	* Start by syncing the page directory entry so CSAM's TLB trick works.
2473	*/
2474	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| X86_PDE_AVL_MASK))
2475	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2476	*pPdeDst = PdeDst;
2477
2478	/*
2479	* Directory/page user or supervisor privilege: (same goes for read/write)
2480	*
2481	* Directory Page Combined
2482	* U/S U/S U/S
2483	* 0 0 0
2484	* 0 1 0
2485	* 1 0 0
2486	* 1 1 1
2487	*
2488	* Simple AND operation. Table listed for completeness.
2489	*
2490	*/
2491	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPT4K));
2492	# ifdef PGM_SYNC_N_PAGES
2493	unsigned iPTBase = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2494	unsigned iPTDst = iPTBase;
2495	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2496	if (iPTDst <= PGM_SYNC_NR_PAGES / 2)
2497	iPTDst = 0;
2498	else
2499	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2500	# else /* !PGM_SYNC_N_PAGES */
2501	unsigned iPTDst = 0;
2502	const unsigned iPTDstEnd = RT_ELEMENTS(pPTDst->a);
2503	# endif /* !PGM_SYNC_N_PAGES */
2504	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2505	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2506	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
2507	# else
2508	const unsigned offPTSrc = 0;
2509	# endif
2510	for (; iPTDst < iPTDstEnd; iPTDst++)
2511	{
2512	const unsigned iPTSrc = iPTDst + offPTSrc;
2513	const GSTPTE PteSrc = pPTSrc->a[iPTSrc];
2514
2515	if (PteSrc.n.u1Present) /* we've already cleared it above */
2516	{
2517	# ifndef IN_RING0
2518	/*
2519	* Assuming kernel code will be marked as supervisor - and not as user level
2520	* and executed using a conforming code selector - And marked as readonly.
2521	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
2522	*/
2523	PPGMPAGE pPage;
2524	if ( ((PdeSrc.u & pPTSrc->a[iPTSrc].u) & (X86_PTE_RW \| X86_PTE_US))
2525	\|\| !CSAMDoesPageNeedScanning(pVM, (RTRCPTR)((iPDSrc << GST_PD_SHIFT) \| (iPTSrc << PAGE_SHIFT)))
2526	\|\| ( (pPage = pgmPhysGetPage(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK))
2527	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2528	)
2529	# endif
2530	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2531	Log2(("SyncPT: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s dst.raw=%08llx iPTSrc=%x PdeSrc.u=%x physpte=%RGp\n",
2532	(RTGCPTR)((iPDSrc << GST_PD_SHIFT) \| (iPTSrc << PAGE_SHIFT)),
2533	PteSrc.n.u1Present,
2534	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2535	PteSrc.n.u1User & PdeSrc.n.u1User,
2536	(uint64_t)PteSrc.u,
2537	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : "", pPTDst->a[iPTDst].u, iPTSrc, PdeSrc.au32[0],
2538	(RTGCPHYS)((PdeSrc.u & GST_PDE_PG_MASK) + iPTSrc*sizeof(PteSrc)) ));
2539	}
2540	} /* for PTEs */
2541	}
2542	}
2543	else
2544	{
2545	/*
2546	* Big page - 2/4MB.
2547	*
2548	* We'll walk the ram range list in parallel and optimize lookups.
2549	* We will only sync on shadow page table at a time.
2550	*/
2551	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPT4M));
2552
2553	/**
2554	* @todo It might be more efficient to sync only a part of the 4MB page (similar to what we do for 4kb PDs).
2555	*/
2556
2557	/*
2558	* Start by syncing the page directory entry.
2559	*/
2560	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| (X86_PDE_AVL_MASK & ~PGM_PDFLAGS_TRACK_DIRTY)))
2561	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2562
2563	/*
2564	* If the page is not flagged as dirty and is writable, then make it read-only
2565	* at PD level, so we can set the dirty bit when the page is modified.
2566	*
2567	* ASSUMES that page access handlers are implemented on page table entry level.
2568	* Thus we will first catch the dirty access and set PDE.D and restart. If
2569	* there is an access handler, we'll trap again and let it work on the problem.
2570	*/
2571	/** @todo move the above stuff to a section in the PGM documentation. */
2572	Assert(!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY));
2573	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
2574	{
2575	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyPageBig));
2576	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2577	PdeDst.b.u1Write = 0;
2578	}
2579	*pPdeDst = PdeDst;
2580
2581	/*
2582	* Fill the shadow page table.
2583	*/
2584	/* Get address and flags from the source PDE. */
2585	SHWPTE PteDstBase;
2586	PteDstBase.u = PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT);
2587
2588	/* Loop thru the entries in the shadow PT. */
2589	const RTGCPTR GCPtr = (GCPtrPage >> SHW_PD_SHIFT) << SHW_PD_SHIFT; NOREF(GCPtr);
2590	Log2(("SyncPT: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} Shw=%RGv GCPhys=%RGp %s\n",
2591	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u, GCPtr,
2592	GCPhys, PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2593	PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
2594	unsigned iPTDst = 0;
2595	while (iPTDst < RT_ELEMENTS(pPTDst->a))
2596	{
2597	/* Advance ram range list. */
2598	while (pRam && GCPhys > pRam->GCPhysLast)
2599	pRam = pRam->CTX_SUFF(pNext);
2600	if (pRam && GCPhys >= pRam->GCPhys)
2601	{
2602	unsigned iHCPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
2603	do
2604	{
2605	/* Make shadow PTE. */
2606	PPGMPAGE pPage = &pRam->aPages[iHCPage];
2607	SHWPTE PteDst;
2608
2609	/* Make sure the RAM has already been allocated. */
2610	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC) /** @todo PAGE FLAGS */
2611	{
2612	if (RT_UNLIKELY(!PGM_PAGE_GET_HCPHYS(pPage)))
2613	{
2614	# ifdef IN_RING3
2615	int rc = pgmr3PhysGrowRange(pVM, GCPhys);
2616	# else
2617	int rc = CTXALLMID(VMM, CallHost)(pVM, VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
2618	# endif
2619	if (rc != VINF_SUCCESS)
2620	return rc;
2621	}
2622	}
2623
2624	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2625	{
2626	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
2627	{
2628	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage) \| PteDstBase.u;
2629	PteDst.n.u1Write = 0;
2630	}
2631	else
2632	PteDst.u = 0;
2633	}
2634	# ifndef IN_RING0
2635	/*
2636	* Assuming kernel code will be marked as supervisor and not as user level and executed
2637	* using a conforming code selector. Don't check for readonly, as that implies the whole
2638	* 4MB can be code or readonly data. Linux enables write access for its large pages.
2639	*/
2640	else if ( !PdeSrc.n.u1User
2641	&& CSAMDoesPageNeedScanning(pVM, (RTRCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT))))
2642	PteDst.u = 0;
2643	# endif
2644	else
2645	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage) \| PteDstBase.u;
2646	# ifdef PGMPOOL_WITH_USER_TRACKING
2647	if (PteDst.n.u1Present)
2648	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, pPage->HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst); /** @todo PAGE FLAGS */
2649	# endif
2650	/* commit it */
2651	pPTDst->a[iPTDst] = PteDst;
2652	Log4(("SyncPT: BIG %RGv PteDst:{P=%d RW=%d U=%d raw=%08llx}%s\n",
2653	(RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT)), PteDst.n.u1Present, PteDst.n.u1Write, PteDst.n.u1User, (uint64_t)PteDst.u,
2654	PteDst.u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2655
2656	/* advance */
2657	GCPhys += PAGE_SIZE;
2658	iHCPage++;
2659	iPTDst++;
2660	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2661	&& GCPhys <= pRam->GCPhysLast);
2662	}
2663	else if (pRam)
2664	{
2665	Log(("Invalid pages at %RGp\n", GCPhys));
2666	do
2667	{
2668	pPTDst->a[iPTDst].u = 0; /* MMIO or invalid page, we must handle them manually. */
2669	GCPhys += PAGE_SIZE;
2670	iPTDst++;
2671	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2672	&& GCPhys < pRam->GCPhys);
2673	}
2674	else
2675	{
2676	Log(("Invalid pages at %RGp (2)\n", GCPhys));
2677	for ( ; iPTDst < RT_ELEMENTS(pPTDst->a); iPTDst++)
2678	pPTDst->a[iPTDst].u = 0; /* MMIO or invalid page, we must handle them manually. */
2679	}
2680	} /* while more PTEs */
2681	} /* 4KB / 4MB */
2682	}
2683	else
2684	AssertRelease(!PdeDst.n.u1Present);
2685
2686	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2687	if (RT_FAILURE(rc))
2688	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPTFailed));
2689	return rc;
2690
2691	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2692	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2693	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT)
2694
2695	int rc = VINF_SUCCESS;
2696
2697	/*
2698	* Validate input a little bit.
2699	*/
2700	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2701	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
2702	PX86PD pPDDst = pVM->pgm.s.CTXMID(p,32BitPD);
2703	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2704	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT; /* no mask; flat index into the 2048 entry array. */
2705	PX86PDPAE pPDDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0];
2706	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2707	const unsigned iPdpte = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
2708	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2709	PX86PDPAE pPDDst;
2710	PX86PDPT pPdptDst;
2711	rc = pgmShwGetLongModePDPtr(pVM, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2712	AssertRCSuccessReturn(rc, rc);
2713	Assert(pPDDst);
2714
2715	/* Fetch the pgm pool shadow descriptor. */
2716	PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(pVM, pPdptDst->a[iPdpte].u & X86_PDPE_PG_MASK);
2717	Assert(pShwPde);
2718	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
2719	const unsigned iPdpte = (GCPtrPage >> EPT_PDPT_SHIFT) & EPT_PDPT_MASK;
2720	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2721	PEPTPD pPDDst;
2722	PEPTPDPT pPdptDst;
2723
2724	rc = pgmShwGetEPTPDPtr(pVM, GCPtrPage, &pPdptDst, &pPDDst);
2725	if (rc != VINF_SUCCESS)
2726	{
2727	AssertRC(rc);
2728	return rc;
2729	}
2730	Assert(pPDDst);
2731
2732	/* Fetch the pgm pool shadow descriptor. */
2733	PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(pVM, pPdptDst->a[iPdpte].u & EPT_PDPTE_PG_MASK);
2734	Assert(pShwPde);
2735	# endif
2736	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2737	SHWPDE PdeDst = *pPdeDst;
2738
2739	Assert(!(PdeDst.u & PGM_PDFLAGS_MAPPING));
2740	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
2741
2742	GSTPDE PdeSrc;
2743	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
2744	PdeSrc.n.u1Present = 1;
2745	PdeSrc.n.u1Write = 1;
2746	PdeSrc.n.u1Accessed = 1;
2747	PdeSrc.n.u1User = 1;
2748
2749	/*
2750	* Allocate & map the page table.
2751	*/
2752	PSHWPT pPTDst;
2753	PPGMPOOLPAGE pShwPage;
2754	RTGCPHYS GCPhys;
2755
2756	/* Virtual address = physical address */
2757	GCPhys = GCPtrPage & X86_PAGE_4K_BASE_MASK;
2758	# if PGM_SHW_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
2759	rc = pgmPoolAlloc(pVM, GCPhys & ~(RT_BIT_64(SHW_PD_SHIFT) - 1), BTH_PGMPOOLKIND_PT_FOR_PT, pShwPde->idx, iPDDst, &pShwPage);
2760	# else
2761	rc = pgmPoolAlloc(pVM, GCPhys & ~(RT_BIT_64(SHW_PD_SHIFT) - 1), BTH_PGMPOOLKIND_PT_FOR_PT, SHW_POOL_ROOT_IDX, iPDDst, &pShwPage);
2762	# endif
2763
2764	if ( rc == VINF_SUCCESS
2765	\|\| rc == VINF_PGM_CACHED_PAGE)
2766	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2767	else
2768	AssertMsgFailedReturn(("rc=%Rrc\n", rc), VERR_INTERNAL_ERROR);
2769
2770	PdeDst.u &= X86_PDE_AVL_MASK;
2771	PdeDst.u \|= pShwPage->Core.Key;
2772	PdeDst.n.u1Present = 1;
2773	PdeDst.n.u1Write = 1;
2774	# if PGM_SHW_TYPE == PGM_TYPE_EPT
2775	PdeDst.n.u1Execute = 1;
2776	# else
2777	PdeDst.n.u1User = 1;
2778	PdeDst.n.u1Accessed = 1;
2779	# endif
2780	*pPdeDst = PdeDst;
2781
2782	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, PGM_SYNC_NR_PAGES, 0 /* page not present */);
2783	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2784	return rc;
2785
2786	#else
2787	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_SHW_TYPE, PGM_GST_TYPE));
2788	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2789	return VERR_INTERNAL_ERROR;
2790	#endif
2791	}
2792
2793
2794
2795	/**
2796	* Prefetch a page/set of pages.
2797	*
2798	* Typically used to sync commonly used pages before entering raw mode
2799	* after a CR3 reload.
2800	*
2801	* @returns VBox status code.
2802	* @param pVM VM handle.
2803	* @param GCPtrPage Page to invalidate.
2804	*/
2805	PGM_BTH_DECL(int, PrefetchPage)(PVM pVM, RTGCPTR GCPtrPage)
2806	{
2807	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
2808	&& PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
2809	/*
2810	* Check that all Guest levels thru the PDE are present, getting the
2811	* PD and PDE in the processes.
2812	*/
2813	int rc = VINF_SUCCESS;
2814	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
2815	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2816	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
2817	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(&pVM->pgm.s);
2818	# elif PGM_GST_TYPE == PGM_TYPE_PAE
2819	unsigned iPDSrc;
2820	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtrPage, &iPDSrc, NULL);
2821	if (!pPDSrc)
2822	return VINF_SUCCESS; /* not present */
2823	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
2824	unsigned iPDSrc;
2825	PX86PML4E pPml4eSrc;
2826	X86PDPE PdpeSrc;
2827	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
2828	if (!pPDSrc)
2829	return VINF_SUCCESS; /* not present */
2830	# endif
2831	const GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
2832	# else
2833	PGSTPD pPDSrc = NULL;
2834	const unsigned iPDSrc = 0;
2835	GSTPDE PdeSrc;
2836
2837	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
2838	PdeSrc.n.u1Present = 1;
2839	PdeSrc.n.u1Write = 1;
2840	PdeSrc.n.u1Accessed = 1;
2841	PdeSrc.n.u1User = 1;
2842	# endif
2843
2844	if (PdeSrc.n.u1Present && PdeSrc.n.u1Accessed)
2845	{
2846	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2847	const X86PDE PdeDst = pVM->pgm.s.CTXMID(p,32BitPD)->a[GCPtrPage >> SHW_PD_SHIFT];
2848	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2849	const X86PDEPAE PdeDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[GCPtrPage >> SHW_PD_SHIFT];
2850	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2851	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2852	PX86PDPAE pPDDst;
2853	X86PDEPAE PdeDst;
2854
2855	# if PGM_GST_TYPE == PGM_TYPE_PROT
2856	/* AMD-V nested paging */
2857	X86PML4E Pml4eSrc;
2858	X86PDPE PdpeSrc;
2859	PX86PML4E pPml4eSrc = &Pml4eSrc;
2860
2861	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
2862	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_NX \| X86_PML4E_A;
2863	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_NX \| X86_PDPE_A;
2864	# endif
2865
2866	int rc = pgmShwSyncLongModePDPtr(pVM, GCPtrPage, pPml4eSrc, &PdpeSrc, &pPDDst);
2867	if (rc != VINF_SUCCESS)
2868	{
2869	AssertRC(rc);
2870	return rc;
2871	}
2872	Assert(pPDDst);
2873	PdeDst = pPDDst->a[iPDDst];
2874	# endif
2875	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
2876	{
2877	if (!PdeDst.n.u1Present)
2878	/** r=bird: This guy will set the A bit on the PDE, probably harmless. */
2879	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, GCPtrPage);
2880	else
2881	{
2882	/** @note We used to sync PGM_SYNC_NR_PAGES pages, which triggered assertions in CSAM, because
2883	* R/W attributes of nearby pages were reset. Not sure how that could happen. Anyway, it
2884	* makes no sense to prefetch more than one page.
2885	*/
2886	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, 1, 0);
2887	if (RT_SUCCESS(rc))
2888	rc = VINF_SUCCESS;
2889	}
2890	}
2891	}
2892	return rc;
2893
2894	#elif PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
2895	return VINF_SUCCESS; /* ignore */
2896	#endif
2897	}
2898
2899
2900
2901
2902	/**
2903	* Syncs a page during a PGMVerifyAccess() call.
2904	*
2905	* @returns VBox status code (informational included).
2906	* @param GCPtrPage The address of the page to sync.
2907	* @param fPage The effective guest page flags.
2908	* @param uErr The trap error code.
2909	*/
2910	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVM pVM, RTGCPTR GCPtrPage, unsigned fPage, unsigned uErr)
2911	{
2912	LogFlow(("VerifyAccessSyncPage: GCPtrPage=%RGv fPage=%#x uErr=%#x\n", GCPtrPage, fPage, uErr));
2913
2914	Assert(!HWACCMIsNestedPagingActive(pVM));
2915	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_TYPE_AMD64) \
2916	&& PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
2917
2918	# ifndef IN_RING0
2919	if (!(fPage & X86_PTE_US))
2920	{
2921	/*
2922	* Mark this page as safe.
2923	*/
2924	/** @todo not correct for pages that contain both code and data!! */
2925	Log(("CSAMMarkPage %RGv; scanned=%d\n", GCPtrPage, true));
2926	CSAMMarkPage(pVM, (RTRCPTR)GCPtrPage, true);
2927	}
2928	# endif
2929
2930	/*
2931	* Get guest PD and index.
2932	*/
2933	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
2934	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2935	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
2936	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(&pVM->pgm.s);
2937	# elif PGM_GST_TYPE == PGM_TYPE_PAE
2938	unsigned iPDSrc;
2939	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtrPage, &iPDSrc, NULL);
2940
2941	if (pPDSrc)
2942	{
2943	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
2944	return VINF_EM_RAW_GUEST_TRAP;
2945	}
2946	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
2947	unsigned iPDSrc;
2948	PX86PML4E pPml4eSrc;
2949	X86PDPE PdpeSrc;
2950	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
2951	if (!pPDSrc)
2952	{
2953	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
2954	return VINF_EM_RAW_GUEST_TRAP;
2955	}
2956	# endif
2957	# else
2958	PGSTPD pPDSrc = NULL;
2959	const unsigned iPDSrc = 0;
2960	# endif
2961	int rc = VINF_SUCCESS;
2962
2963	/*
2964	* First check if the shadow pd is present.
2965	*/
2966	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2967	PX86PDE pPdeDst = &pVM->pgm.s.CTXMID(p,32BitPD)->a[GCPtrPage >> SHW_PD_SHIFT];
2968	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2969	PX86PDEPAE pPdeDst = &pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[GCPtrPage >> SHW_PD_SHIFT];
2970	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2971	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2972	PX86PDPAE pPDDst;
2973	PX86PDEPAE pPdeDst;
2974
2975	# if PGM_GST_TYPE == PGM_TYPE_PROT
2976	/* AMD-V nested paging */
2977	X86PML4E Pml4eSrc;
2978	X86PDPE PdpeSrc;
2979	PX86PML4E pPml4eSrc = &Pml4eSrc;
2980
2981	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
2982	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_NX \| X86_PML4E_A;
2983	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_NX \| X86_PDPE_A;
2984	# endif
2985
2986	rc = pgmShwSyncLongModePDPtr(pVM, GCPtrPage, pPml4eSrc, &PdpeSrc, &pPDDst);
2987	if (rc != VINF_SUCCESS)
2988	{
2989	AssertRC(rc);
2990	return rc;
2991	}
2992	Assert(pPDDst);
2993	pPdeDst = &pPDDst->a[iPDDst];
2994	# endif
2995	if (!pPdeDst->n.u1Present)
2996	{
2997	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, GCPtrPage);
2998	AssertRC(rc);
2999	if (rc != VINF_SUCCESS)
3000	return rc;
3001	}
3002
3003	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3004	/* Check for dirty bit fault */
3005	rc = PGM_BTH_NAME(CheckPageFault)(pVM, uErr, pPdeDst, &pPDSrc->a[iPDSrc], GCPtrPage);
3006	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
3007	Log(("PGMVerifyAccess: success (dirty)\n"));
3008	else
3009	{
3010	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
3011	#else
3012	{
3013	GSTPDE PdeSrc;
3014	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
3015	PdeSrc.n.u1Present = 1;
3016	PdeSrc.n.u1Write = 1;
3017	PdeSrc.n.u1Accessed = 1;
3018	PdeSrc.n.u1User = 1;
3019
3020	#endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
3021	Assert(rc != VINF_EM_RAW_GUEST_TRAP);
3022	if (uErr & X86_TRAP_PF_US)
3023	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncUser));
3024	else /* supervisor */
3025	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
3026
3027	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, 1, 0);
3028	if (RT_SUCCESS(rc))
3029	{
3030	/* Page was successfully synced */
3031	Log2(("PGMVerifyAccess: success (sync)\n"));
3032	rc = VINF_SUCCESS;
3033	}
3034	else
3035	{
3036	Log(("PGMVerifyAccess: access violation for %RGv rc=%d\n", GCPtrPage, rc));
3037	return VINF_EM_RAW_GUEST_TRAP;
3038	}
3039	}
3040	return rc;
3041
3042	#else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
3043
3044	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
3045	return VERR_INTERNAL_ERROR;
3046	#endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
3047	}
3048
3049
3050	#if PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
3051	# if PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
3052	/**
3053	* Figures out which kind of shadow page this guest PDE warrants.
3054	*
3055	* @returns Shadow page kind.
3056	* @param pPdeSrc The guest PDE in question.
3057	* @param cr4 The current guest cr4 value.
3058	*/
3059	DECLINLINE(PGMPOOLKIND) PGM_BTH_NAME(CalcPageKind)(const GSTPDE *pPdeSrc, uint32_t cr4)
3060	{
3061	# if PMG_GST_TYPE == PGM_TYPE_AMD64
3062	if (!pPdeSrc->n.u1Size)
3063	# else
3064	if (!pPdeSrc->n.u1Size \|\| !(cr4 & X86_CR4_PSE))
3065	# endif
3066	return BTH_PGMPOOLKIND_PT_FOR_PT;
3067	//switch (pPdeSrc->u & (X86_PDE4M_RW \| X86_PDE4M_US /\| X86_PDE4M_PAE_NX/))
3068	//{
3069	// case 0:
3070	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RO;
3071	// case X86_PDE4M_RW:
3072	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW;
3073	// case X86_PDE4M_US:
3074	// return BTH_PGMPOOLKIND_PT_FOR_BIG_US;
3075	// case X86_PDE4M_RW \| X86_PDE4M_US:
3076	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_US;
3077	# if 0
3078	// case X86_PDE4M_PAE_NX:
3079	// return BTH_PGMPOOLKIND_PT_FOR_BIG_NX;
3080	// case X86_PDE4M_RW \| X86_PDE4M_PAE_NX:
3081	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_NX;
3082	// case X86_PDE4M_US \| X86_PDE4M_PAE_NX:
3083	// return BTH_PGMPOOLKIND_PT_FOR_BIG_US_NX;
3084	// case X86_PDE4M_RW \| X86_PDE4M_US \| X86_PDE4M_PAE_NX:
3085	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_US_NX;
3086	# endif
3087	return BTH_PGMPOOLKIND_PT_FOR_BIG;
3088	//}
3089	}
3090	# endif
3091	#endif
3092
3093	#undef MY_STAM_COUNTER_INC
3094	#define MY_STAM_COUNTER_INC(a) do { } while (0)
3095
3096
3097	/**
3098	* Syncs the paging hierarchy starting at CR3.
3099	*
3100	* @returns VBox status code, no specials.
3101	* @param pVM The virtual machine.
3102	* @param cr0 Guest context CR0 register
3103	* @param cr3 Guest context CR3 register
3104	* @param cr4 Guest context CR4 register
3105	* @param fGlobal Including global page directories or not
3106	*/
3107	PGM_BTH_DECL(int, SyncCR3)(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
3108	{
3109	if (VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3))
3110	fGlobal = true; /* Change this CR3 reload to be a global one. */
3111
3112	#if PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
3113	/*
3114	* Update page access handlers.
3115	* The virtual are always flushed, while the physical are only on demand.
3116	* WARNING: We are incorrectly not doing global flushing on Virtual Handler updates. We'll
3117	* have to look into that later because it will have a bad influence on the performance.
3118	* @note SvL: There's no need for that. Just invalidate the virtual range(s).
3119	* bird: Yes, but that won't work for aliases.
3120	*/
3121	/** @todo this MUST go away. See #1557. */
3122	STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3Handlers), h);
3123	PGM_GST_NAME(HandlerVirtualUpdate)(pVM, cr4);
3124	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3Handlers), h);
3125	#endif
3126
3127	#ifdef PGMPOOL_WITH_MONITORING
3128	int rc = pgmPoolSyncCR3(pVM);
3129	if (rc != VINF_SUCCESS)
3130	return rc;
3131	#endif
3132
3133	#if PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3134	/** @todo check if this is really necessary */
3135	HWACCMFlushTLB(pVM);
3136	return VINF_SUCCESS;
3137
3138	#elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3139	/* No need to check all paging levels; we zero out the shadow parts when the guest modifies its tables. */
3140	return VINF_SUCCESS;
3141	#else
3142
3143	Assert(fGlobal \|\| (cr4 & X86_CR4_PGE));
3144	MY_STAM_COUNTER_INC(fGlobal ? &pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3Global) : &pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3NotGlobal));
3145
3146	# if PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
3147	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3148	bool fBigPagesSupported = true;
3149	# else
3150	bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
3151	# endif
3152
3153	/*
3154	* Get page directory addresses.
3155	*/
3156	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3157	PX86PDE pPDEDst = &pVM->pgm.s.CTXMID(p,32BitPD)->a[0];
3158	# else /* PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64*/
3159	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3160	PX86PDEPAE pPDEDst = &pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[0];
3161	# endif
3162	# endif
3163
3164	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3165	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(&pVM->pgm.s);
3166	Assert(pPDSrc);
3167	# ifndef IN_RC
3168	Assert(PGMPhysGCPhys2HCPtrAssert(pVM, (RTGCPHYS)(cr3 & GST_CR3_PAGE_MASK), sizeof(*pPDSrc)) == pPDSrc);
3169	# endif
3170	# endif
3171
3172	/*
3173	* Iterate the page directory.
3174	*/
3175	PPGMMAPPING pMapping;
3176	unsigned iPdNoMapping;
3177	const bool fRawR0Enabled = EMIsRawRing0Enabled(pVM);
3178	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3179
3180	/* Only check mappings if they are supposed to be put into the shadow page table. */
3181	if (pgmMapAreMappingsEnabled(&pVM->pgm.s))
3182	{
3183	pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
3184	iPdNoMapping = (pMapping) ? (pMapping->GCPtr >> GST_PD_SHIFT) : ~0U;
3185	}
3186	else
3187	{
3188	pMapping = 0;
3189	iPdNoMapping = ~0U;
3190	}
3191	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3192	for (uint64_t iPml4 = 0; iPml4 < X86_PG_PAE_ENTRIES; iPml4++)
3193	{
3194	PPGMPOOLPAGE pShwPdpt = NULL;
3195	PX86PML4E pPml4eSrc, pPml4eDst;
3196	RTGCPHYS GCPhysPdptSrc;
3197
3198	pPml4eSrc = &pVM->pgm.s.CTXSUFF(pGstPaePML4)->a[iPml4];
3199	pPml4eDst = &pVM->pgm.s.CTXMID(p,PaePML4)->a[iPml4];
3200
3201	/* Fetch the pgm pool shadow descriptor if the shadow pml4e is present. */
3202	if (!pPml4eDst->n.u1Present)
3203	continue;
3204	pShwPdpt = pgmPoolGetPage(pPool, pPml4eDst->u & X86_PML4E_PG_MASK);
3205
3206	GCPhysPdptSrc = pPml4eSrc->u & X86_PML4E_PG_MASK_FULL;
3207
3208	/* Anything significant changed? */
3209	if ( pPml4eSrc->n.u1Present != pPml4eDst->n.u1Present
3210	\|\| GCPhysPdptSrc != pShwPdpt->GCPhys)
3211	{
3212	/* Free it. */
3213	LogFlow(("SyncCR3: Out-of-sync PML4E (GCPhys) GCPtr=%RX64 %RGp vs %RGp PdpeSrc=%RX64 PdpeDst=%RX64\n",
3214	(uint64_t)iPml4 << X86_PML4_SHIFT, pShwPdpt->GCPhys, GCPhysPdptSrc, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
3215	pgmPoolFreeByPage(pPool, pShwPdpt, pVM->pgm.s.pHCShwAmd64CR3->idx, iPml4);
3216	pPml4eDst->u = 0;
3217	continue;
3218	}
3219	/* Force an attribute sync. */
3220	pPml4eDst->n.u1User = pPml4eSrc->n.u1User;
3221	pPml4eDst->n.u1Write = pPml4eSrc->n.u1Write;
3222	pPml4eDst->n.u1NoExecute = pPml4eSrc->n.u1NoExecute;
3223
3224	# else
3225	{
3226	# endif
3227	# if PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
3228	for (uint64_t iPdpte = 0; iPdpte < GST_PDPE_ENTRIES; iPdpte++)
3229	{
3230	unsigned iPDSrc;
3231	# if PGM_GST_TYPE == PGM_TYPE_PAE
3232	X86PDPE PdpeSrc;
3233	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, iPdpte << X86_PDPT_SHIFT, &iPDSrc, &PdpeSrc);
3234	PX86PDPAE pPDPAE = pVM->pgm.s.CTXMID(ap,PaePDs)[0];
3235	PX86PDEPAE pPDEDst = &pPDPAE->a[iPdpte * X86_PG_PAE_ENTRIES];
3236	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(&pVM->pgm.s);
3237
3238	if (pPDSrc == NULL)
3239	{
3240	/* PDPE not present */
3241	if (pPdptDst->a[iPdpte].n.u1Present)
3242	{
3243	LogFlow(("SyncCR3: guest PDPE %d not present; clear shw pdpe\n", iPdpte));
3244	/* for each page directory entry */
3245	for (unsigned iPD = 0; iPD < RT_ELEMENTS(pPDSrc->a); iPD++)
3246	{
3247	if ( pPDEDst[iPD].n.u1Present
3248	&& !(pPDEDst[iPD].u & PGM_PDFLAGS_MAPPING))
3249	{
3250	pgmPoolFreeByPage(pPool, pgmPoolGetPage(pPool, pPDEDst[iPD].u & SHW_PDE_PG_MASK), SHW_POOL_ROOT_IDX, iPdpte * X86_PG_PAE_ENTRIES + iPD);
3251	pPDEDst[iPD].u = 0;
3252	}
3253	}
3254	}
3255	if (!(pPdptDst->a[iPdpte].u & PGM_PLXFLAGS_MAPPING))
3256	pPdptDst->a[iPdpte].n.u1Present = 0;
3257	continue;
3258	}
3259	# else /* PGM_GST_TYPE != PGM_TYPE_PAE */
3260	PPGMPOOLPAGE pShwPde = NULL;
3261	RTGCPHYS GCPhysPdeSrc;
3262	PX86PDPE pPdpeDst;
3263	PX86PML4E pPml4eSrc;
3264	X86PDPE PdpeSrc;
3265	PX86PDPT pPdptDst;
3266	PX86PDPAE pPDDst;
3267	PX86PDEPAE pPDEDst;
3268	RTGCPTR GCPtr = (iPml4 << X86_PML4_SHIFT) \|\| (iPdpte << X86_PDPT_SHIFT);
3269	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, GCPtr, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3270
3271	int rc = pgmShwGetLongModePDPtr(pVM, GCPtr, NULL, &pPdptDst, &pPDDst);
3272	if (rc != VINF_SUCCESS)
3273	{
3274	if (rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT)
3275	break; /* next PML4E */
3276
3277	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
3278	continue; /* next PDPTE */
3279	}
3280	Assert(pPDDst);
3281	pPDEDst = &pPDDst->a[0];
3282	Assert(iPDSrc == 0);
3283
3284	pPdpeDst = &pPdptDst->a[iPdpte];
3285
3286	/* Fetch the pgm pool shadow descriptor if the shadow pdpte is present. */
3287	if (!pPdpeDst->n.u1Present)
3288	continue; /* next PDPTE */
3289
3290	pShwPde = pgmPoolGetPage(pPool, pPdpeDst->u & X86_PDPE_PG_MASK);
3291	GCPhysPdeSrc = PdpeSrc.u & X86_PDPE_PG_MASK;
3292
3293	/* Anything significant changed? */
3294	if ( PdpeSrc.n.u1Present != pPdpeDst->n.u1Present
3295	\|\| GCPhysPdeSrc != pShwPde->GCPhys)
3296	{
3297	/* Free it. */
3298	LogFlow(("SyncCR3: Out-of-sync PDPE (GCPhys) GCPtr=%RX64 %RGp vs %RGp PdpeSrc=%RX64 PdpeDst=%RX64\n",
3299	((uint64_t)iPml4 << X86_PML4_SHIFT) + ((uint64_t)iPdpte << X86_PDPT_SHIFT), pShwPde->GCPhys, GCPhysPdeSrc, (uint64_t)PdpeSrc.u, (uint64_t)pPdpeDst->u));
3300
3301	/* Mark it as not present if there's no hypervisor mapping present. (bit flipped at the top of Trap0eHandler) */
3302	Assert(!(pPdpeDst->u & PGM_PLXFLAGS_MAPPING));
3303	pgmPoolFreeByPage(pPool, pShwPde, pShwPde->idx, iPdpte);
3304	pPdpeDst->u = 0;
3305	continue; /* next guest PDPTE */
3306	}
3307	/* Force an attribute sync. */
3308	pPdpeDst->lm.u1User = PdpeSrc.lm.u1User;
3309	pPdpeDst->lm.u1Write = PdpeSrc.lm.u1Write;
3310	pPdpeDst->lm.u1NoExecute = PdpeSrc.lm.u1NoExecute;
3311	# endif /* PGM_GST_TYPE != PGM_TYPE_PAE */
3312
3313	# else /* PGM_GST_TYPE != PGM_TYPE_PAE && PGM_GST_TYPE != PGM_TYPE_AMD64 */
3314	{
3315	# endif /* PGM_GST_TYPE != PGM_TYPE_PAE && PGM_GST_TYPE != PGM_TYPE_AMD64 */
3316	for (unsigned iPD = 0; iPD < RT_ELEMENTS(pPDSrc->a); iPD++)
3317	{
3318	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3319	Assert(&pVM->pgm.s.CTXMID(p,32BitPD)->a[iPD] == pPDEDst);
3320	# elif PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3321	AssertMsg(&pVM->pgm.s.CTXMID(ap,PaePDs)[iPD * 2 / 512]->a[iPD * 2 % 512] == pPDEDst, ("%p vs %p\n", &pVM->pgm.s.CTXMID(ap,PaePDs)[iPD * 2 / 512]->a[iPD * 2 % 512], pPDEDst));
3322	# endif
3323	GSTPDE PdeSrc = pPDSrc->a[iPD];
3324	if ( PdeSrc.n.u1Present
3325	&& (PdeSrc.n.u1User \|\| fRawR0Enabled))
3326	{
3327	# if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
3328	\|\| PGM_GST_TYPE == PGM_TYPE_PAE) \
3329	&& !defined(PGM_WITHOUT_MAPPINGS)
3330
3331	/*
3332	* Check for conflicts with GC mappings.
3333	*/
3334	# if PGM_GST_TYPE == PGM_TYPE_PAE
3335	if (iPD + iPdpte * X86_PG_PAE_ENTRIES == iPdNoMapping)
3336	# else
3337	if (iPD == iPdNoMapping)
3338	# endif
3339	{
3340	if (pVM->pgm.s.fMappingsFixed)
3341	{
3342	/* It's fixed, just skip the mapping. */
3343	const unsigned cPTs = pMapping->cb >> GST_PD_SHIFT;
3344	iPD += cPTs - 1;
3345	pPDEDst += cPTs + (PGM_GST_TYPE != PGM_SHW_TYPE) * cPTs; /* Only applies to the pae shadow and 32 bits guest case */
3346	pMapping = pMapping->CTX_SUFF(pNext);
3347	iPdNoMapping = pMapping ? pMapping->GCPtr >> GST_PD_SHIFT : ~0U;
3348	continue;
3349	}
3350	# ifdef IN_RING3
3351	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3352	int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, iPD << GST_PD_SHIFT);
3353	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3354	int rc = pgmR3SyncPTResolveConflictPAE(pVM, pMapping, (iPdpte << GST_PDPT_SHIFT) + (iPD << GST_PD_SHIFT));
3355	# endif
3356	if (RT_FAILURE(rc))
3357	return rc;
3358
3359	/*
3360	* Update iPdNoMapping and pMapping.
3361	*/
3362	pMapping = pVM->pgm.s.pMappingsR3;
3363	while (pMapping && pMapping->GCPtr < (iPD << GST_PD_SHIFT))
3364	pMapping = pMapping->pNextR3;
3365	iPdNoMapping = pMapping ? pMapping->GCPtr >> GST_PD_SHIFT : ~0U;
3366	# else
3367	LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
3368	return VINF_PGM_SYNC_CR3;
3369	# endif
3370	}
3371	# else /* (PGM_GST_TYPE != PGM_TYPE_32BIT && PGM_GST_TYPE != PGM_TYPE_PAE) \|\| PGM_WITHOUT_MAPPINGS */
3372	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
3373	# endif /* (PGM_GST_TYPE != PGM_TYPE_32BIT && PGM_GST_TYPE != PGM_TYPE_PAE) \|\| PGM_WITHOUT_MAPPINGS */
3374
3375	/*
3376	* Sync page directory entry.
3377	*
3378	* The current approach is to allocated the page table but to set
3379	* the entry to not-present and postpone the page table synching till
3380	* it's actually used.
3381	*/
3382	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3383	for (unsigned i = 0, iPdShw = iPD * 2; i < 2; i++, iPdShw++) /* pray that the compiler unrolls this */
3384	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3385	const unsigned iPdShw = iPD + iPdpte * X86_PG_PAE_ENTRIES; NOREF(iPdShw);
3386	# else
3387	const unsigned iPdShw = iPD; NOREF(iPdShw);
3388	# endif
3389	{
3390	SHWPDE PdeDst = *pPDEDst;
3391	if (PdeDst.n.u1Present)
3392	{
3393	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
3394	RTGCPHYS GCPhys;
3395	if ( !PdeSrc.b.u1Size
3396	\|\| !fBigPagesSupported)
3397	{
3398	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
3399	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3400	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
3401	GCPhys \|= i * (PAGE_SIZE / 2);
3402	# endif
3403	}
3404	else
3405	{
3406	GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
3407	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3408	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
3409	GCPhys \|= i * X86_PAGE_2M_SIZE;
3410	# endif
3411	}
3412
3413	if ( pShwPage->GCPhys == GCPhys
3414	&& pShwPage->enmKind == PGM_BTH_NAME(CalcPageKind)(&PdeSrc, cr4)
3415	&& ( pShwPage->fCached
3416	\|\| ( !fGlobal
3417	&& ( false
3418	# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
3419	\|\| ( (PdeSrc.u & (X86_PDE4M_PS \| X86_PDE4M_G)) == (X86_PDE4M_PS \| X86_PDE4M_G)
3420	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3421	&& (cr4 & X86_CR4_PGE)) /* global 2/4MB page. */
3422	# else
3423	&& (cr4 & (X86_CR4_PGE \| X86_CR4_PSE)) == (X86_CR4_PGE \| X86_CR4_PSE)) /* global 2/4MB page. */
3424	# endif
3425	\|\| ( !pShwPage->fSeenNonGlobal
3426	&& (cr4 & X86_CR4_PGE))
3427	# endif
3428	)
3429	)
3430	)
3431	&& ( (PdeSrc.u & (X86_PDE_US \| X86_PDE_RW)) == (PdeDst.u & (X86_PDE_US \| X86_PDE_RW))
3432	\|\| ( fBigPagesSupported
3433	&& ((PdeSrc.u & (X86_PDE_US \| X86_PDE4M_PS \| X86_PDE4M_D)) \| PGM_PDFLAGS_TRACK_DIRTY)
3434	== ((PdeDst.u & (X86_PDE_US \| X86_PDE_RW \| PGM_PDFLAGS_TRACK_DIRTY)) \| X86_PDE4M_PS))
3435	)
3436	)
3437	{
3438	# ifdef VBOX_WITH_STATISTICS
3439	if ( !fGlobal
3440	&& (PdeSrc.u & (X86_PDE4M_PS \| X86_PDE4M_G)) == (X86_PDE4M_PS \| X86_PDE4M_G)
3441	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3442	&& (cr4 & X86_CR4_PGE)) /* global 2/4MB page. */
3443	# else
3444	&& (cr4 & (X86_CR4_PGE \| X86_CR4_PSE)) == (X86_CR4_PGE \| X86_CR4_PSE))
3445	# endif
3446	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3DstSkippedGlobalPD));
3447	else if (!fGlobal && !pShwPage->fSeenNonGlobal && (cr4 & X86_CR4_PGE))
3448	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3DstSkippedGlobalPT));
3449	else
3450	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3DstCacheHit));
3451	# endif /* VBOX_WITH_STATISTICS */
3452	/** @todo a replacement strategy isn't really needed unless we're using a very small pool < 512 pages.
3453	* The whole ageing stuff should be put in yet another set of #ifdefs. For now, let's just skip it. */
3454	//# ifdef PGMPOOL_WITH_CACHE
3455	// pgmPoolCacheUsed(pPool, pShwPage);
3456	//# endif
3457	}
3458	else
3459	{
3460	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3461	pgmPoolFreeByPage(pPool, pShwPage, pShwPde->idx, iPdShw);
3462	# else
3463	pgmPoolFreeByPage(pPool, pShwPage, SHW_POOL_ROOT_IDX, iPdShw);
3464	# endif
3465	pPDEDst->u = 0;
3466	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3DstFreed));
3467	}
3468	}
3469	else
3470	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3DstNotPresent));
3471	pPDEDst++;
3472	}
3473	}
3474	# if PGM_GST_TYPE == PGM_TYPE_PAE
3475	else if (iPD + iPdpte * X86_PG_PAE_ENTRIES != iPdNoMapping)
3476	# else
3477	else if (iPD != iPdNoMapping)
3478	# endif
3479	{
3480	/*
3481	* Check if there is any page directory to mark not present here.
3482	*/
3483	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3484	for (unsigned i = 0, iPdShw = iPD * 2; i < 2; i++, iPdShw++) /* pray that the compiler unrolls this */
3485	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3486	const unsigned iPdShw = iPD + iPdpte * X86_PG_PAE_ENTRIES; NOREF(iPdShw);
3487	# else
3488	const unsigned iPdShw = iPD; NOREF(iPdShw);
3489	# endif
3490	{
3491	if (pPDEDst->n.u1Present)
3492	{
3493	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3494	pgmPoolFreeByPage(pPool, pgmPoolGetPage(pPool, pPDEDst->u & SHW_PDE_PG_MASK), pShwPde->idx, iPdShw);
3495	# else
3496	pgmPoolFreeByPage(pPool, pgmPoolGetPage(pPool, pPDEDst->u & SHW_PDE_PG_MASK), SHW_POOL_ROOT_IDX, iPdShw);
3497	# endif
3498	pPDEDst->u = 0;
3499	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3DstFreedSrcNP));
3500	}
3501	pPDEDst++;
3502	}
3503	}
3504	else
3505	{
3506	# if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
3507	\|\| PGM_GST_TYPE == PGM_TYPE_PAE) \
3508	&& !defined(PGM_WITHOUT_MAPPINGS)
3509
3510	const unsigned cPTs = pMapping->cb >> GST_PD_SHIFT;
3511
3512	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
3513	if (pVM->pgm.s.fMappingsFixed)
3514	{
3515	/* It's fixed, just skip the mapping. */
3516	pMapping = pMapping->CTX_SUFF(pNext);
3517	iPdNoMapping = pMapping ? pMapping->GCPtr >> GST_PD_SHIFT : ~0U;
3518	}
3519	else
3520	{
3521	/*
3522	* Check for conflicts for subsequent pagetables
3523	* and advance to the next mapping.
3524	*/
3525	iPdNoMapping = ~0U;
3526	unsigned iPT = cPTs;
3527	while (iPT-- > 1)
3528	{
3529	if ( pPDSrc->a[iPD + iPT].n.u1Present
3530	&& (pPDSrc->a[iPD + iPT].n.u1User \|\| fRawR0Enabled))
3531	{
3532	# ifdef IN_RING3
3533	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3534	int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, iPD << GST_PD_SHIFT);
3535	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3536	int rc = pgmR3SyncPTResolveConflictPAE(pVM, pMapping, (iPdpte << GST_PDPT_SHIFT) + (iPD << GST_PD_SHIFT));
3537	# endif
3538	if (RT_FAILURE(rc))
3539	return rc;
3540
3541	/*
3542	* Update iPdNoMapping and pMapping.
3543	*/
3544	pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
3545	while (pMapping && pMapping->GCPtr < (iPD << GST_PD_SHIFT))
3546	pMapping = pMapping->CTX_SUFF(pNext);
3547	iPdNoMapping = pMapping ? pMapping->GCPtr >> GST_PD_SHIFT : ~0U;
3548	break;
3549	# else
3550	LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
3551	return VINF_PGM_SYNC_CR3;
3552	# endif
3553	}
3554	}
3555	if (iPdNoMapping == ~0U && pMapping)
3556	{
3557	pMapping = pMapping->CTX_SUFF(pNext);
3558	if (pMapping)
3559	iPdNoMapping = pMapping->GCPtr >> GST_PD_SHIFT;
3560	}
3561	}
3562
3563	/* advance. */
3564	iPD += cPTs - 1;
3565	pPDEDst += cPTs + (PGM_GST_TYPE != PGM_SHW_TYPE) * cPTs; /* Only applies to the pae shadow and 32 bits guest case */
3566	# if PGM_GST_TYPE != PGM_SHW_TYPE
3567	AssertCompile(PGM_GST_TYPE == PGM_TYPE_32BIT && PGM_SHW_TYPE == PGM_TYPE_PAE);
3568	# endif
3569	# else /* (PGM_GST_TYPE != PGM_TYPE_32BIT && PGM_GST_TYPE != PGM_TYPE_PAE) \|\| PGM_WITHOUT_MAPPINGS */
3570	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
3571	# endif /* (PGM_GST_TYPE != PGM_TYPE_32BIT && PGM_GST_TYPE != PGM_TYPE_PAE) \|\| PGM_WITHOUT_MAPPINGS */
3572	}
3573
3574	} /* for iPD */
3575	} /* for each PDPTE (PAE) */
3576	} /* for each page map level 4 entry (amd64) */
3577	return VINF_SUCCESS;
3578
3579	# else /* guest real and protected mode */
3580	return VINF_SUCCESS;
3581	# endif
3582	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT */
3583	}
3584
3585
3586
3587
3588	#ifdef VBOX_STRICT
3589	#ifdef IN_RC
3590	# undef AssertMsgFailed
3591	# define AssertMsgFailed Log
3592	#endif
3593	#ifdef IN_RING3
3594	# include <VBox/dbgf.h>
3595
3596	/**
3597	* Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
3598	*
3599	* @returns VBox status code (VINF_SUCCESS).
3600	* @param pVM The VM handle.
3601	* @param cr3 The root of the hierarchy.
3602	* @param crr The cr4, only PAE and PSE is currently used.
3603	* @param fLongMode Set if long mode, false if not long mode.
3604	* @param cMaxDepth Number of levels to dump.
3605	* @param pHlp Pointer to the output functions.
3606	*/
3607	__BEGIN_DECLS
3608	VMMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint32_t cr3, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp);
3609	__END_DECLS
3610
3611	#endif
3612
3613	/**
3614	* Checks that the shadow page table is in sync with the guest one.
3615	*
3616	* @returns The number of errors.
3617	* @param pVM The virtual machine.
3618	* @param cr3 Guest context CR3 register
3619	* @param cr4 Guest context CR4 register
3620	* @param GCPtr Where to start. Defaults to 0.
3621	* @param cb How much to check. Defaults to everything.
3622	*/
3623	PGM_BTH_DECL(unsigned, AssertCR3)(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb)
3624	{
3625	#if PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3626	return 0;
3627	#else
3628	unsigned cErrors = 0;
3629
3630	#if PGM_GST_TYPE == PGM_TYPE_PAE
3631	/** @todo currently broken; crashes below somewhere */
3632	AssertFailed();
3633	#endif
3634
3635	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
3636	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3637	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
3638
3639	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3640	bool fBigPagesSupported = true;
3641	# else
3642	bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
3643	# endif
3644	PPGM pPGM = &pVM->pgm.s;
3645	RTGCPHYS GCPhysGst; /* page address derived from the guest page tables. */
3646	RTHCPHYS HCPhysShw; /* page address derived from the shadow page tables. */
3647	# ifndef IN_RING0
3648	RTHCPHYS HCPhys; /* general usage. */
3649	# endif
3650	int rc;
3651
3652	/*
3653	* Check that the Guest CR3 and all its mappings are correct.
3654	*/
3655	AssertMsgReturn(pPGM->GCPhysCR3 == (cr3 & GST_CR3_PAGE_MASK),
3656	("Invalid GCPhysCR3=%RGp cr3=%RGp\n", pPGM->GCPhysCR3, (RTGCPHYS)cr3),
3657	false);
3658	# if !defined(IN_RING0) && PGM_GST_TYPE != PGM_TYPE_AMD64
3659	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3660	rc = PGMShwGetPage(pVM, (RTGCPTR)pPGM->pGuestPDRC, NULL, &HCPhysShw);
3661	# else
3662	rc = PGMShwGetPage(pVM, (RTGCPTR)pPGM->pGstPaePDPTRC, NULL, &HCPhysShw);
3663	# endif
3664	AssertRCReturn(rc, 1);
3665	HCPhys = NIL_RTHCPHYS;
3666	rc = pgmRamGCPhys2HCPhys(pPGM, cr3 & GST_CR3_PAGE_MASK, &HCPhys);
3667	AssertMsgReturn(HCPhys == HCPhysShw, ("HCPhys=%RHp HCPhyswShw=%RHp (cr3)\n", HCPhys, HCPhysShw), false);
3668	# if PGM_GST_TYPE == PGM_TYPE_32BIT && defined(IN_RING3)
3669	RTGCPHYS GCPhys;
3670	rc = PGMR3DbgR3Ptr2GCPhys(pVM, pPGM->pGuestPDR3, &GCPhys);
3671	AssertRCReturn(rc, 1);
3672	AssertMsgReturn((cr3 & GST_CR3_PAGE_MASK) == GCPhys, ("GCPhys=%RGp cr3=%RGp\n", GCPhys, (RTGCPHYS)cr3), false);
3673	# endif
3674	#endif /* !IN_RING0 */
3675
3676	/*
3677	* Get and check the Shadow CR3.
3678	*/
3679	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3680	unsigned cPDEs = X86_PG_ENTRIES;
3681	unsigned cIncrement = X86_PG_ENTRIES * PAGE_SIZE;
3682	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3683	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3684	unsigned cPDEs = X86_PG_PAE_ENTRIES * 4; /* treat it as a 2048 entry table. */
3685	# else
3686	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3687	# endif
3688	unsigned cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3689	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3690	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3691	unsigned cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3692	# endif
3693	if (cb != ~(RTGCPTR)0)
3694	cPDEs = RT_MIN(cb >> SHW_PD_SHIFT, 1);
3695
3696	/** @todo call the other two PGMAssert() functions. /
3697
3698	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
3699	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3700	# endif
3701
3702	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3703	unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3704
3705	for (; iPml4 < X86_PG_PAE_ENTRIES; iPml4++)
3706	{
3707	PPGMPOOLPAGE pShwPdpt = NULL;
3708	PX86PML4E pPml4eSrc;
3709	PX86PML4E pPml4eDst;
3710	RTGCPHYS GCPhysPdptSrc;
3711
3712	pPml4eSrc = pgmGstGetLongModePML4EPtr(&pVM->pgm.s, iPml4);
3713	pPml4eDst = pgmShwGetLongModePML4EPtr(&pVM->pgm.s, iPml4);
3714
3715	/* Fetch the pgm pool shadow descriptor if the shadow pml4e is present. */
3716	if (!pPml4eDst->n.u1Present)
3717	{
3718	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3719	continue;
3720	}
3721
3722	# if PGM_GST_TYPE == PGM_TYPE_PAE
3723	/* not correct to call pgmPoolGetPage */
3724	AssertFailed();
3725	# endif
3726	pShwPdpt = pgmPoolGetPage(pPool, pPml4eDst->u & X86_PML4E_PG_MASK);
3727	GCPhysPdptSrc = pPml4eSrc->u & X86_PML4E_PG_MASK_FULL;
3728
3729	if (pPml4eSrc->n.u1Present != pPml4eDst->n.u1Present)
3730	{
3731	AssertMsgFailed(("Present bit doesn't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3732	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3733	cErrors++;
3734	continue;
3735	}
3736
3737	if (GCPhysPdptSrc != pShwPdpt->GCPhys)
3738	{
3739	AssertMsgFailed(("Physical address doesn't match! iPml4 %d pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, pPml4eDst->u, pPml4eSrc->u, pShwPdpt->GCPhys, GCPhysPdptSrc));
3740	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3741	cErrors++;
3742	continue;
3743	}
3744
3745	if ( pPml4eDst->n.u1User != pPml4eSrc->n.u1User
3746	\|\| pPml4eDst->n.u1Write != pPml4eSrc->n.u1Write
3747	\|\| pPml4eDst->n.u1NoExecute != pPml4eSrc->n.u1NoExecute)
3748	{
3749	AssertMsgFailed(("User/Write/NoExec bits don't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3750	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3751	cErrors++;
3752	continue;
3753	}
3754	# else
3755	{
3756	# endif
3757
3758	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
3759	/*
3760	* Check the PDPTEs too.
3761	*/
3762	unsigned iPdpte = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
3763
3764	for (;iPdpte <= SHW_PDPT_MASK; iPdpte++)
3765	{
3766	unsigned iPDSrc;
3767	PPGMPOOLPAGE pShwPde = NULL;
3768	PX86PDPE pPdpeDst;
3769	RTGCPHYS GCPhysPdeSrc;
3770	# if PGM_GST_TYPE == PGM_TYPE_PAE
3771	X86PDPE PdpeSrc;
3772	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtr, &iPDSrc, &PdpeSrc);
3773	PX86PDPAE pPDDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0];
3774	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(&pVM->pgm.s);
3775	# else
3776	PX86PML4E pPml4eSrc;
3777	X86PDPE PdpeSrc;
3778	PX86PDPT pPdptDst;
3779	PX86PDPAE pPDDst;
3780	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, GCPtr, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3781
3782	rc = pgmShwGetLongModePDPtr(pVM, GCPtr, NULL, &pPdptDst, &pPDDst);
3783	if (rc != VINF_SUCCESS)
3784	{
3785	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
3786	GCPtr += 512 * _2M;
3787	continue; /* next PDPTE */
3788	}
3789	Assert(pPDDst);
3790	# endif
3791	Assert(iPDSrc == 0);
3792
3793	pPdpeDst = &pPdptDst->a[iPdpte];
3794
3795	if (!pPdpeDst->n.u1Present)
3796	{
3797	GCPtr += 512 * _2M;
3798	continue; /* next PDPTE */
3799	}
3800
3801	pShwPde = pgmPoolGetPage(pPool, pPdpeDst->u & X86_PDPE_PG_MASK);
3802	GCPhysPdeSrc = PdpeSrc.u & X86_PDPE_PG_MASK;
3803
3804	if (pPdpeDst->n.u1Present != PdpeSrc.n.u1Present)
3805	{
3806	AssertMsgFailed(("Present bit doesn't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3807	GCPtr += 512 * _2M;
3808	cErrors++;
3809	continue;
3810	}
3811
3812	if (GCPhysPdeSrc != pShwPde->GCPhys)
3813	{
3814	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3815	AssertMsgFailed(("Physical address doesn't match! iPml4 %d iPdpte %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, iPdpte, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3816	# else
3817	AssertMsgFailed(("Physical address doesn't match! iPdpte %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPdpte, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3818	# endif
3819	GCPtr += 512 * _2M;
3820	cErrors++;
3821	continue;
3822	}
3823
3824	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3825	if ( pPdpeDst->lm.u1User != PdpeSrc.lm.u1User
3826	\|\| pPdpeDst->lm.u1Write != PdpeSrc.lm.u1Write
3827	\|\| pPdpeDst->lm.u1NoExecute != PdpeSrc.lm.u1NoExecute)
3828	{
3829	AssertMsgFailed(("User/Write/NoExec bits don't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3830	GCPtr += 512 * _2M;
3831	cErrors++;
3832	continue;
3833	}
3834	# endif
3835
3836	# else
3837	{
3838	# endif
3839	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3840	GSTPD const *pPDSrc = pgmGstGet32bitPDPtr(&pVM->pgm.s);
3841	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3842	PCX86PD pPDDst = pPGM->CTXMID(p,32BitPD);
3843	# else
3844	PCX86PDPAE pPDDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]; /* We treat this as a PD with 2048 entries, so no need to and with SHW_PD_MASK to get iPDDst */
3845	# endif
3846	# endif
3847	/*
3848	* Iterate the shadow page directory.
3849	*/
3850	GCPtr = (GCPtr >> SHW_PD_SHIFT) << SHW_PD_SHIFT;
3851	unsigned iPDDst = (GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK;
3852
3853	for (;
3854	iPDDst < cPDEs;
3855	iPDDst++, GCPtr += cIncrement)
3856	{
3857	const SHWPDE PdeDst = pPDDst->a[iPDDst];
3858	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
3859	{
3860	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
3861	if ((PdeDst.u & X86_PDE_AVL_MASK) != PGM_PDFLAGS_MAPPING)
3862	{
3863	AssertMsgFailed(("Mapping shall only have PGM_PDFLAGS_MAPPING set! PdeDst.u=%#RX64\n", (uint64_t)PdeDst.u));
3864	cErrors++;
3865	continue;
3866	}
3867	}
3868	else if ( (PdeDst.u & X86_PDE_P)
3869	\|\| ((PdeDst.u & (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY)) == (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY))
3870	)
3871	{
3872	HCPhysShw = PdeDst.u & SHW_PDE_PG_MASK;
3873	PPGMPOOLPAGE pPoolPage = pgmPoolGetPageByHCPhys(pVM, HCPhysShw);
3874	if (!pPoolPage)
3875	{
3876	AssertMsgFailed(("Invalid page table address %RHp at %RGv! PdeDst=%#RX64\n",
3877	HCPhysShw, GCPtr, (uint64_t)PdeDst.u));
3878	cErrors++;
3879	continue;
3880	}
3881	const SHWPT pPTDst = (const SHWPT )PGMPOOL_PAGE_2_PTR(pVM, pPoolPage);
3882
3883	if (PdeDst.u & (X86_PDE4M_PWT \| X86_PDE4M_PCD))
3884	{
3885	AssertMsgFailed(("PDE flags PWT and/or PCD is set at %RGv! These flags are not virtualized! PdeDst=%#RX64\n",
3886	GCPtr, (uint64_t)PdeDst.u));
3887	cErrors++;
3888	}
3889
3890	if (PdeDst.u & (X86_PDE4M_G \| X86_PDE4M_D))
3891	{
3892	AssertMsgFailed(("4K PDE reserved flags at %RGv! PdeDst=%#RX64\n",
3893	GCPtr, (uint64_t)PdeDst.u));
3894	cErrors++;
3895	}
3896
3897	const GSTPDE PdeSrc = pPDSrc->a[(iPDDst >> (GST_PD_SHIFT - SHW_PD_SHIFT)) & GST_PD_MASK];
3898	if (!PdeSrc.n.u1Present)
3899	{
3900	AssertMsgFailed(("Guest PDE at %RGv is not present! PdeDst=%#RX64 PdeSrc=%#RX64\n",
3901	GCPtr, (uint64_t)PdeDst.u, (uint64_t)PdeSrc.u));
3902	cErrors++;
3903	continue;
3904	}
3905
3906	if ( !PdeSrc.b.u1Size
3907	\|\| !fBigPagesSupported)
3908	{
3909	GCPhysGst = PdeSrc.u & GST_PDE_PG_MASK;
3910	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3911	GCPhysGst \|= (iPDDst & 1) * (PAGE_SIZE / 2);
3912	# endif
3913	}
3914	else
3915	{
3916	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3917	if (PdeSrc.u & X86_PDE4M_PG_HIGH_MASK)
3918	{
3919	AssertMsgFailed(("Guest PDE at %RGv is using PSE36 or similar! PdeSrc=%#RX64\n",
3920	GCPtr, (uint64_t)PdeSrc.u));
3921	cErrors++;
3922	continue;
3923	}
3924	# endif
3925	GCPhysGst = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
3926	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3927	GCPhysGst \|= GCPtr & RT_BIT(X86_PAGE_2M_SHIFT);
3928	# endif
3929	}
3930
3931	if ( pPoolPage->enmKind
3932	!= (!PdeSrc.b.u1Size \|\| !fBigPagesSupported ? BTH_PGMPOOLKIND_PT_FOR_PT : BTH_PGMPOOLKIND_PT_FOR_BIG))
3933	{
3934	AssertMsgFailed(("Invalid shadow page table kind %d at %RGv! PdeSrc=%#RX64\n",
3935	pPoolPage->enmKind, GCPtr, (uint64_t)PdeSrc.u));
3936	cErrors++;
3937	}
3938
3939	PPGMPAGE pPhysPage = pgmPhysGetPage(pPGM, GCPhysGst);
3940	if (!pPhysPage)
3941	{
3942	AssertMsgFailed(("Cannot find guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
3943	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3944	cErrors++;
3945	continue;
3946	}
3947
3948	if (GCPhysGst != pPoolPage->GCPhys)
3949	{
3950	AssertMsgFailed(("GCPhysGst=%RGp != pPage->GCPhys=%RGp at %RGv\n",
3951	GCPhysGst, pPoolPage->GCPhys, GCPtr));
3952	cErrors++;
3953	continue;
3954	}
3955
3956	if ( !PdeSrc.b.u1Size
3957	\|\| !fBigPagesSupported)
3958	{
3959	/*
3960	* Page Table.
3961	*/
3962	const GSTPT *pPTSrc;
3963	rc = PGM_GCPHYS_2_PTR(pVM, GCPhysGst & ~(RTGCPHYS)(PAGE_SIZE - 1), &pPTSrc);
3964	if (RT_FAILURE(rc))
3965	{
3966	AssertMsgFailed(("Cannot map/convert guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
3967	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3968	cErrors++;
3969	continue;
3970	}
3971	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/))
3972	!= (PdeDst.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/)))
3973	{
3974	/// @todo We get here a lot on out-of-sync CR3 entries. The access handler should zap them to avoid false alarms here!
3975	// (This problem will go away when/if we shadow multiple CR3s.)
3976	AssertMsgFailed(("4K PDE flags mismatch at %RGv! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3977	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3978	cErrors++;
3979	continue;
3980	}
3981	if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
3982	{
3983	AssertMsgFailed(("4K PDEs cannot have PGM_PDFLAGS_TRACK_DIRTY set! GCPtr=%RGv PdeDst=%#RX64\n",
3984	GCPtr, (uint64_t)PdeDst.u));
3985	cErrors++;
3986	continue;
3987	}
3988
3989	/* iterate the page table. */
3990	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3991	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
3992	const unsigned offPTSrc = ((GCPtr >> SHW_PD_SHIFT) & 1) * 512;
3993	# else
3994	const unsigned offPTSrc = 0;
3995	# endif
3996	for (unsigned iPT = 0, off = 0;
3997	iPT < RT_ELEMENTS(pPTDst->a);
3998	iPT++, off += PAGE_SIZE)
3999	{
4000	const SHWPTE PteDst = pPTDst->a[iPT];
4001
4002	/* skip not-present entries. */
4003	if (!(PteDst.u & (X86_PTE_P \| PGM_PTFLAGS_TRACK_DIRTY))) /** @todo deal with ALL handlers and CSAM !P pages! */
4004	continue;
4005	Assert(PteDst.n.u1Present);
4006
4007	const GSTPTE PteSrc = pPTSrc->a[iPT + offPTSrc];
4008	if (!PteSrc.n.u1Present)
4009	{
4010	# ifdef IN_RING3
4011	PGMAssertHandlerAndFlagsInSync(pVM);
4012	PGMR3DumpHierarchyGC(pVM, cr3, cr4, (PdeSrc.u & GST_PDE_PG_MASK));
4013	# endif
4014	AssertMsgFailed(("Out of sync (!P) PTE at %RGv! PteSrc=%#RX64 PteDst=%#RX64 pPTSrc=%RGv iPTSrc=%x PdeSrc=%x physpte=%RGp\n",
4015	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u, pPTSrc, iPT + offPTSrc, PdeSrc.au32[0],
4016	(PdeSrc.u & GST_PDE_PG_MASK) + (iPT + offPTSrc)*sizeof(PteSrc)));
4017	cErrors++;
4018	continue;
4019	}
4020
4021	uint64_t fIgnoreFlags = GST_PTE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_G \| X86_PTE_D \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT;
4022	# if 1 /** @todo sync accessed bit properly... */
4023	fIgnoreFlags \|= X86_PTE_A;
4024	# endif
4025
4026	/* match the physical addresses */
4027	HCPhysShw = PteDst.u & SHW_PTE_PG_MASK;
4028	GCPhysGst = PteSrc.u & GST_PTE_PG_MASK;
4029
4030	# ifdef IN_RING3
4031	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
4032	if (RT_FAILURE(rc))
4033	{
4034	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
4035	{
4036	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
4037	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4038	cErrors++;
4039	continue;
4040	}
4041	}
4042	else if (HCPhysShw != (HCPhys & SHW_PTE_PG_MASK))
4043	{
4044	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4045	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4046	cErrors++;
4047	continue;
4048	}
4049	# endif
4050
4051	pPhysPage = pgmPhysGetPage(pPGM, GCPhysGst);
4052	if (!pPhysPage)
4053	{
4054	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
4055	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
4056	{
4057	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
4058	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4059	cErrors++;
4060	continue;
4061	}
4062	# endif
4063	if (PteDst.n.u1Write)
4064	{
4065	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4066	GCPtr + off, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4067	cErrors++;
4068	}
4069	fIgnoreFlags \|= X86_PTE_RW;
4070	}
4071	else if (HCPhysShw != (PGM_PAGE_GET_HCPHYS(pPhysPage) & SHW_PTE_PG_MASK))
4072	{
4073	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4074	GCPtr + off, HCPhysShw, pPhysPage->HCPhys, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4075	cErrors++;
4076	continue;
4077	}
4078
4079	/* flags */
4080	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
4081	{
4082	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
4083	{
4084	if (PteDst.n.u1Write)
4085	{
4086	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! HCPhys=%RHp PteSrc=%#RX64 PteDst=%#RX64\n",
4087	GCPtr + off, pPhysPage->HCPhys, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4088	cErrors++;
4089	continue;
4090	}
4091	fIgnoreFlags \|= X86_PTE_RW;
4092	}
4093	else
4094	{
4095	if (PteDst.n.u1Present)
4096	{
4097	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! HCPhys=%RHp PteSrc=%#RX64 PteDst=%#RX64\n",
4098	GCPtr + off, pPhysPage->HCPhys, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4099	cErrors++;
4100	continue;
4101	}
4102	fIgnoreFlags \|= X86_PTE_P;
4103	}
4104	}
4105	else
4106	{
4107	if (!PteSrc.n.u1Dirty && PteSrc.n.u1Write)
4108	{
4109	if (PteDst.n.u1Write)
4110	{
4111	AssertMsgFailed(("!DIRTY page at %RGv is writable! PteSrc=%#RX64 PteDst=%#RX64\n",
4112	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4113	cErrors++;
4114	continue;
4115	}
4116	if (!(PteDst.u & PGM_PTFLAGS_TRACK_DIRTY))
4117	{
4118	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4119	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4120	cErrors++;
4121	continue;
4122	}
4123	if (PteDst.n.u1Dirty)
4124	{
4125	AssertMsgFailed(("!DIRTY page at %RGv is marked DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4126	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4127	cErrors++;
4128	}
4129	# if 0 /** @todo sync access bit properly... */
4130	if (PteDst.n.u1Accessed != PteSrc.n.u1Accessed)
4131	{
4132	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4133	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4134	cErrors++;
4135	}
4136	fIgnoreFlags \|= X86_PTE_RW;
4137	# else
4138	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4139	# endif
4140	}
4141	else if (PteDst.u & PGM_PTFLAGS_TRACK_DIRTY)
4142	{
4143	/* access bit emulation (not implemented). */
4144	if (PteSrc.n.u1Accessed \|\| PteDst.n.u1Present)
4145	{
4146	AssertMsgFailed(("PGM_PTFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PteSrc=%#RX64 PteDst=%#RX64\n",
4147	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4148	cErrors++;
4149	continue;
4150	}
4151	if (!PteDst.n.u1Accessed)
4152	{
4153	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PteSrc=%#RX64 PteDst=%#RX64\n",
4154	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4155	cErrors++;
4156	}
4157	fIgnoreFlags \|= X86_PTE_P;
4158	}
4159	# ifdef DEBUG_sandervl
4160	fIgnoreFlags \|= X86_PTE_D \| X86_PTE_A;
4161	# endif
4162	}
4163
4164	if ( (PteSrc.u & ~fIgnoreFlags) != (PteDst.u & ~fIgnoreFlags)
4165	&& (PteSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (PteDst.u & ~fIgnoreFlags)
4166	)
4167	{
4168	AssertMsgFailed(("Flags mismatch at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PteSrc=%#RX64 PteDst=%#RX64\n",
4169	GCPtr + off, (uint64_t)PteSrc.u & ~fIgnoreFlags, (uint64_t)PteDst.u & ~fIgnoreFlags,
4170	fIgnoreFlags, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4171	cErrors++;
4172	continue;
4173	}
4174	} /* foreach PTE */
4175	}
4176	else
4177	{
4178	/*
4179	* Big Page.
4180	*/
4181	uint64_t fIgnoreFlags = X86_PDE_AVL_MASK \| GST_PDE_PG_MASK \| X86_PDE4M_G \| X86_PDE4M_D \| X86_PDE4M_PS \| X86_PDE4M_PWT \| X86_PDE4M_PCD;
4182	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
4183	{
4184	if (PdeDst.n.u1Write)
4185	{
4186	AssertMsgFailed(("!DIRTY page at %RGv is writable! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4187	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4188	cErrors++;
4189	continue;
4190	}
4191	if (!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY))
4192	{
4193	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4194	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4195	cErrors++;
4196	continue;
4197	}
4198	# if 0 /** @todo sync access bit properly... */
4199	if (PdeDst.n.u1Accessed != PdeSrc.b.u1Accessed)
4200	{
4201	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4202	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4203	cErrors++;
4204	}
4205	fIgnoreFlags \|= X86_PTE_RW;
4206	# else
4207	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4208	# endif
4209	}
4210	else if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
4211	{
4212	/* access bit emulation (not implemented). */
4213	if (PdeSrc.b.u1Accessed \|\| PdeDst.n.u1Present)
4214	{
4215	AssertMsgFailed(("PGM_PDFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4216	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4217	cErrors++;
4218	continue;
4219	}
4220	if (!PdeDst.n.u1Accessed)
4221	{
4222	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4223	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4224	cErrors++;
4225	}
4226	fIgnoreFlags \|= X86_PTE_P;
4227	}
4228
4229	if ((PdeSrc.u & ~fIgnoreFlags) != (PdeDst.u & ~fIgnoreFlags))
4230	{
4231	AssertMsgFailed(("Flags mismatch (B) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PdeDst=%#RX64\n",
4232	GCPtr, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PdeDst.u & ~fIgnoreFlags,
4233	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4234	cErrors++;
4235	}
4236
4237	/* iterate the page table. */
4238	for (unsigned iPT = 0, off = 0;
4239	iPT < RT_ELEMENTS(pPTDst->a);
4240	iPT++, off += PAGE_SIZE, GCPhysGst += PAGE_SIZE)
4241	{
4242	const SHWPTE PteDst = pPTDst->a[iPT];
4243
4244	if (PteDst.u & PGM_PTFLAGS_TRACK_DIRTY)
4245	{
4246	AssertMsgFailed(("The PTE at %RGv emulating a 2/4M page is marked TRACK_DIRTY! PdeSrc=%#RX64 PteDst=%#RX64\n",
4247	GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4248	cErrors++;
4249	}
4250
4251	/* skip not-present entries. */
4252	if (!PteDst.n.u1Present) /** @todo deal with ALL handlers and CSAM !P pages! */
4253	continue;
4254
4255	fIgnoreFlags = X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT \| X86_PTE_D \| X86_PTE_A \| X86_PTE_G \| X86_PTE_PAE_NX;
4256
4257	/* match the physical addresses */
4258	HCPhysShw = PteDst.u & X86_PTE_PAE_PG_MASK;
4259
4260	# ifdef IN_RING3
4261	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
4262	if (RT_FAILURE(rc))
4263	{
4264	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
4265	{
4266	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4267	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4268	cErrors++;
4269	}
4270	}
4271	else if (HCPhysShw != (HCPhys & X86_PTE_PAE_PG_MASK))
4272	{
4273	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4274	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4275	cErrors++;
4276	continue;
4277	}
4278	# endif
4279	pPhysPage = pgmPhysGetPage(pPGM, GCPhysGst);
4280	if (!pPhysPage)
4281	{
4282	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
4283	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
4284	{
4285	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4286	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4287	cErrors++;
4288	continue;
4289	}
4290	# endif
4291	if (PteDst.n.u1Write)
4292	{
4293	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4294	GCPtr + off, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4295	cErrors++;
4296	}
4297	fIgnoreFlags \|= X86_PTE_RW;
4298	}
4299	else if (HCPhysShw != (pPhysPage->HCPhys & X86_PTE_PAE_PG_MASK))
4300	{
4301	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4302	GCPtr + off, HCPhysShw, pPhysPage->HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4303	cErrors++;
4304	continue;
4305	}
4306
4307	/* flags */
4308	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
4309	{
4310	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
4311	{
4312	if (PGM_PAGE_GET_HNDL_PHYS_STATE(pPhysPage) != PGM_PAGE_HNDL_PHYS_STATE_DISABLED)
4313	{
4314	if (PteDst.n.u1Write)
4315	{
4316	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! HCPhys=%RHp PdeSrc=%#RX64 PteDst=%#RX64\n",
4317	GCPtr + off, pPhysPage->HCPhys, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4318	cErrors++;
4319	continue;
4320	}
4321	fIgnoreFlags \|= X86_PTE_RW;
4322	}
4323	}
4324	else
4325	{
4326	if (PteDst.n.u1Present)
4327	{
4328	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! HCPhys=%RHp PdeSrc=%#RX64 PteDst=%#RX64\n",
4329	GCPtr + off, pPhysPage->HCPhys, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4330	cErrors++;
4331	continue;
4332	}
4333	fIgnoreFlags \|= X86_PTE_P;
4334	}
4335	}
4336
4337	if ( (PdeSrc.u & ~fIgnoreFlags) != (PteDst.u & ~fIgnoreFlags)
4338	&& (PdeSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (PteDst.u & ~fIgnoreFlags) /* lazy phys handler dereg. */
4339	)
4340	{
4341	AssertMsgFailed(("Flags mismatch (BT) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PteDst=%#RX64\n",
4342	GCPtr + off, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PteDst.u & ~fIgnoreFlags,
4343	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4344	cErrors++;
4345	continue;
4346	}
4347	} /* for each PTE */
4348	}
4349	}
4350	/* not present */
4351
4352	} /* for each PDE */
4353
4354	} /* for each PDPTE */
4355
4356	} /* for each PML4E */
4357
4358	# ifdef DEBUG
4359	if (cErrors)
4360	LogFlow(("AssertCR3: cErrors=%d\n", cErrors));
4361	# endif
4362
4363	#endif
4364	return cErrors;
4365
4366	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT */
4367	}
4368	#endif /* VBOX_STRICT */
4369

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllBth.h@ 14082

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