PGMAllBth.h@ 14141

Last change on this file since 14141 was 14138, checked in by vboxsync, 16 years ago
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1	/* $Id: PGMAllBth.h 14138 2008-11-12 18:30:35Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Shadow+Guest Paging Template - All context code.
4	*
5	* This file is a big challenge!
6	*/
7
8	/*
9	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
10	*
11	* This file is part of VirtualBox Open Source Edition (OSE), as
12	* available from http://www.virtualbox.org. This file is free software;
13	* you can redistribute it and/or modify it under the terms of the GNU
14	* General Public License (GPL) as published by the Free Software
15	* Foundation, in version 2 as it comes in the "COPYING" file of the
16	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
17	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
18	*
19	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
20	* Clara, CA 95054 USA or visit http://www.sun.com if you need
21	* additional information or have any questions.
22	*/
23
24	/*******************************************************************************
25	* Internal Functions *
26	*******************************************************************************/
27	__BEGIN_DECLS
28	PGM_BTH_DECL(int, Trap0eHandler)(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
29	PGM_BTH_DECL(int, InvalidatePage)(PVM pVM, RTGCPTR GCPtrPage);
30	PGM_BTH_DECL(int, SyncPage)(PVM pVM, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr);
31	PGM_BTH_DECL(int, CheckPageFault)(PVM pVM, uint32_t uErr, PSHWPDE pPdeDst, PGSTPDE pPdeSrc, RTGCPTR GCPtrPage);
32	PGM_BTH_DECL(int, SyncPT)(PVM pVM, unsigned iPD, PGSTPD pPDSrc, RTGCPTR GCPtrPage);
33	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVM pVM, RTGCPTR Addr, unsigned fPage, unsigned uErr);
34	PGM_BTH_DECL(int, PrefetchPage)(PVM pVM, RTGCPTR GCPtrPage);
35	PGM_BTH_DECL(int, SyncCR3)(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
36	#ifdef VBOX_STRICT
37	PGM_BTH_DECL(unsigned, AssertCR3)(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr = 0, RTGCPTR cb = ~(RTGCPTR)0);
38	#endif
39	#ifdef PGMPOOL_WITH_USER_TRACKING
40	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVM pVM, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys);
41	#endif
42	__END_DECLS
43
44
45	/* Filter out some illegal combinations of guest and shadow paging, so we can remove redundant checks inside functions. */
46	#if PGM_GST_TYPE == PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
47	# error "Invalid combination; PAE guest implies PAE shadow"
48	#endif
49
50	#if (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
51	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT)
52	# error "Invalid combination; real or protected mode without paging implies 32 bits or PAE shadow paging."
53	#endif
54
55	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) \
56	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT)
57	# error "Invalid combination; 32 bits guest paging or PAE implies 32 bits or PAE shadow paging."
58	#endif
59
60	#if (PGM_GST_TYPE == PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT) \
61	\|\| (PGM_SHW_TYPE == PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PROT)
62	# error "Invalid combination; AMD64 guest implies AMD64 shadow and vice versa"
63	#endif
64
65	#ifdef IN_RING0 /* no mappings in VT-x and AMD-V mode */
66	# define PGM_WITHOUT_MAPPINGS
67	#endif
68
69
70	#ifndef IN_RING3
71	/**
72	* #PF Handler for raw-mode guest execution.
73	*
74	* @returns VBox status code (appropriate for trap handling and GC return).
75	* @param pVM VM Handle.
76	* @param uErr The trap error code.
77	* @param pRegFrame Trap register frame.
78	* @param pvFault The fault address.
79	*/
80	PGM_BTH_DECL(int, Trap0eHandler)(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
81	{
82	# if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
83	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
84	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT)
85
86	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE != PGM_TYPE_PAE
87	/*
88	* Hide the instruction fetch trap indicator for now.
89	*/
90	/** @todo NXE will change this and we must fix NXE in the switcher too! */
91	if (uErr & X86_TRAP_PF_ID)
92	{
93	uErr &= ~X86_TRAP_PF_ID;
94	TRPMSetErrorCode(pVM, uErr);
95	}
96	# endif
97
98	/*
99	* Get PDs.
100	*/
101	int rc;
102	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
103	# if PGM_GST_TYPE == PGM_TYPE_32BIT
104	const unsigned iPDSrc = pvFault >> GST_PD_SHIFT;
105	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(&pVM->pgm.s);
106
107	# elif PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
108
109	# if PGM_GST_TYPE == PGM_TYPE_PAE
110	unsigned iPDSrc;
111	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, pvFault, &iPDSrc, NULL);
112
113	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
114	unsigned iPDSrc;
115	PX86PML4E pPml4eSrc;
116	X86PDPE PdpeSrc;
117	PGSTPD pPDSrc;
118
119	pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, pvFault, &pPml4eSrc, &PdpeSrc, &iPDSrc);
120	Assert(pPml4eSrc);
121	# endif
122	/* Quick check for a valid guest trap. */
123	if (!pPDSrc)
124	{
125	# if PGM_GST_TYPE == PGM_TYPE_AMD64 && GC_ARCH_BITS == 64
126	LogFlow(("Trap0eHandler: guest PML4 %d not present CR3=%RGp\n", (int)((pvFault >> X86_PML4_SHIFT) & X86_PML4_MASK), CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK));
127	# else
128	LogFlow(("Trap0eHandler: guest iPDSrc=%u not present CR3=%RGp\n", iPDSrc, CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK));
129	# endif
130	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2GuestTrap; });
131	TRPMSetErrorCode(pVM, uErr);
132	return VINF_EM_RAW_GUEST_TRAP;
133	}
134	# endif
135
136	# else /* !PGM_WITH_PAGING */
137	PGSTPD pPDSrc = NULL;
138	const unsigned iPDSrc = 0;
139	# endif /* !PGM_WITH_PAGING */
140
141
142	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
143	const unsigned iPDDst = pvFault >> SHW_PD_SHIFT;
144	PX86PD pPDDst = pVM->pgm.s.CTXMID(p,32BitPD);
145
146	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
147	const unsigned iPDDst = (pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK; /* pPDDst index, not used with the pool. */
148	PX86PDPAE pPDDst = pgmShwGetPaePDPtr(&pVM->pgm.s, pvFault);
149
150	# if PGM_GST_TYPE == PGM_TYPE_PAE
151	/* Did we mark the PDPT as not present in SyncCR3? */
152	unsigned iPdpt = (pvFault >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
153	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(&pVM->pgm.s);
154	if (!pPdptDst->a[iPdpt].n.u1Present)
155	pPdptDst->a[iPdpt].n.u1Present = 1;
156	# endif /* GST PAE */
157
158	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
159	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
160	PX86PDPAE pPDDst;
161	# if PGM_GST_TYPE == PGM_TYPE_PROT
162	/* AMD-V nested paging */
163	X86PML4E Pml4eSrc;
164	X86PDPE PdpeSrc;
165	PX86PML4E pPml4eSrc = &Pml4eSrc;
166
167	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
168	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A;
169	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A;
170	# endif
171
172	rc = pgmShwSyncLongModePDPtr(pVM, pvFault, pPml4eSrc, &PdpeSrc, &pPDDst);
173	if (rc != VINF_SUCCESS)
174	{
175	AssertRC(rc);
176	return rc;
177	}
178	Assert(pPDDst);
179
180	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
181	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
182	PEPTPD pPDDst;
183
184	rc = pgmShwGetEPTPDPtr(pVM, pvFault, NULL, &pPDDst);
185	if (rc != VINF_SUCCESS)
186	{
187	AssertRC(rc);
188	return rc;
189	}
190	Assert(pPDDst);
191	# endif
192
193	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
194	/*
195	* If we successfully correct the write protection fault due to dirty bit
196	* tracking, or this page fault is a genuine one, then return immediately.
197	*/
198	STAM_PROFILE_START(&pVM->pgm.s.StatRZTrap0eTimeCheckPageFault, e);
199	rc = PGM_BTH_NAME(CheckPageFault)(pVM, uErr, &pPDDst->a[iPDDst], &pPDSrc->a[iPDSrc], pvFault);
200	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeCheckPageFault, e);
201	if ( rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT
202	\|\| rc == VINF_EM_RAW_GUEST_TRAP)
203	{
204	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution)
205	= rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? &pVM->pgm.s.StatRZTrap0eTime2DirtyAndAccessed : &pVM->pgm.s.StatRZTrap0eTime2GuestTrap; });
206	LogBird(("Trap0eHandler: returns %s\n", rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? "VINF_SUCCESS" : "VINF_EM_RAW_GUEST_TRAP"));
207	return rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? VINF_SUCCESS : rc;
208	}
209
210	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0ePD[iPDSrc]);
211	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
212
213	/*
214	* A common case is the not-present error caused by lazy page table syncing.
215	*
216	* It is IMPORTANT that we weed out any access to non-present shadow PDEs here
217	* so we can safely assume that the shadow PT is present when calling SyncPage later.
218	*
219	* On failure, we ASSUME that SyncPT is out of memory or detected some kind
220	* of mapping conflict and defer to SyncCR3 in R3.
221	* (Again, we do NOT support access handlers for non-present guest pages.)
222	*
223	*/
224	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
225	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
226	# else
227	GSTPDE PdeSrc;
228	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
229	PdeSrc.n.u1Present = 1;
230	PdeSrc.n.u1Write = 1;
231	PdeSrc.n.u1Accessed = 1;
232	PdeSrc.n.u1User = 1;
233	# endif
234	if ( !(uErr & X86_TRAP_PF_P) /* not set means page not present instead of page protection violation */
235	&& !pPDDst->a[iPDDst].n.u1Present
236	&& PdeSrc.n.u1Present
237	)
238
239	{
240	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2SyncPT; });
241	STAM_PROFILE_START(&pVM->pgm.s.StatRZTrap0eTimeSyncPT, f);
242	LogFlow(("=>SyncPT %04x = %08x\n", iPDSrc, PdeSrc.au32[0]));
243	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, pvFault);
244	if (RT_SUCCESS(rc))
245	{
246	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeSyncPT, f);
247	return rc;
248	}
249	Log(("SyncPT: %d failed!! rc=%d\n", iPDSrc, rc));
250	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3); /** @todo no need to do global sync, right? */
251	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeSyncPT, f);
252	return VINF_PGM_SYNC_CR3;
253	}
254
255	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
256	/*
257	* Check if this address is within any of our mappings.
258	*
259	* This is very fast and it's gonna save us a bit of effort below and prevent
260	* us from screwing ourself with MMIO2 pages which have a GC Mapping (VRam).
261	* (BTW, it's impossible to have physical access handlers in a mapping.)
262	*/
263	if (pgmMapAreMappingsEnabled(&pVM->pgm.s))
264	{
265	STAM_PROFILE_START(&pVM->pgm.s.StatRZTrap0eTimeMapping, a);
266	PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
267	for ( ; pMapping; pMapping = pMapping->CTX_SUFF(pNext))
268	{
269	if (pvFault < pMapping->GCPtr)
270	break;
271	if (pvFault - pMapping->GCPtr < pMapping->cb)
272	{
273	/*
274	* The first thing we check is if we've got an undetected conflict.
275	*/
276	if (!pVM->pgm.s.fMappingsFixed)
277	{
278	unsigned iPT = pMapping->cb >> GST_PD_SHIFT;
279	while (iPT-- > 0)
280	if (pPDSrc->a[iPDSrc + iPT].n.u1Present)
281	{
282	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eConflicts);
283	Log(("Trap0e: Detected Conflict %RGv-%RGv\n", pMapping->GCPtr, pMapping->GCPtrLast));
284	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3); /** @todo no need to do global sync,right? */
285	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeMapping, a);
286	return VINF_PGM_SYNC_CR3;
287	}
288	}
289
290	/*
291	* Check if the fault address is in a virtual page access handler range.
292	*/
293	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->HyperVirtHandlers, pvFault);
294	if ( pCur
295	&& pvFault - pCur->Core.Key < pCur->cb
296	&& uErr & X86_TRAP_PF_RW)
297	{
298	# ifdef IN_RC
299	STAM_PROFILE_START(&pCur->Stat, h);
300	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
301	STAM_PROFILE_STOP(&pCur->Stat, h);
302	# else
303	AssertFailed();
304	rc = VINF_EM_RAW_EMULATE_INSTR; /* can't happen with VMX */
305	# endif
306	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersMapping);
307	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeMapping, a);
308	return rc;
309	}
310
311	/*
312	* Pretend we're not here and let the guest handle the trap.
313	*/
314	TRPMSetErrorCode(pVM, uErr & ~X86_TRAP_PF_P);
315	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eGuestPFMapping);
316	LogFlow(("PGM: Mapping access -> route trap to recompiler!\n"));
317	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeMapping, a);
318	return VINF_EM_RAW_GUEST_TRAP;
319	}
320	}
321	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeMapping, a);
322	} /* pgmAreMappingsEnabled(&pVM->pgm.s) */
323	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
324
325	/*
326	* Check if this fault address is flagged for special treatment,
327	* which means we'll have to figure out the physical address and
328	* check flags associated with it.
329	*
330	* ASSUME that we can limit any special access handling to pages
331	* in page tables which the guest believes to be present.
332	*/
333	if (PdeSrc.n.u1Present)
334	{
335	RTGCPHYS GCPhys = NIL_RTGCPHYS;
336
337	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
338	# if PGM_GST_TYPE == PGM_TYPE_AMD64
339	bool fBigPagesSupported = true;
340	# else
341	bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
342	# endif
343	if ( PdeSrc.b.u1Size
344	&& fBigPagesSupported)
345	GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc)
346	\| ((RTGCPHYS)pvFault & (GST_BIG_PAGE_OFFSET_MASK ^ PAGE_OFFSET_MASK));
347	else
348	{
349	PGSTPT pPTSrc;
350	rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
351	if (RT_SUCCESS(rc))
352	{
353	unsigned iPTESrc = (pvFault >> GST_PT_SHIFT) & GST_PT_MASK;
354	if (pPTSrc->a[iPTESrc].n.u1Present)
355	GCPhys = pPTSrc->a[iPTESrc].u & GST_PTE_PG_MASK;
356	}
357	}
358	# else
359	/* No paging so the fault address is the physical address */
360	GCPhys = (RTGCPHYS)(pvFault & ~PAGE_OFFSET_MASK);
361	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
362
363	/*
364	* If we have a GC address we'll check if it has any flags set.
365	*/
366	if (GCPhys != NIL_RTGCPHYS)
367	{
368	STAM_PROFILE_START(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
369
370	PPGMPAGE pPage;
371	rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
372	if (RT_SUCCESS(rc))
373	{
374	if ( PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(pPage)
375	\|\| PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(pPage))
376	{
377	if (PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage))
378	{
379	/*
380	* Physical page access handler.
381	*/
382	const RTGCPHYS GCPhysFault = GCPhys \| (pvFault & PAGE_OFFSET_MASK);
383	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)RTAvlroGCPhysRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->PhysHandlers, GCPhysFault);
384	if (pCur)
385	{
386	# ifdef PGM_SYNC_N_PAGES
387	/*
388	* If the region is write protected and we got a page not present fault, then sync
389	* the pages. If the fault was caused by a read, then restart the instruction.
390	* In case of write access continue to the GC write handler.
391	*
392	* ASSUMES that there is only one handler per page or that they have similar write properties.
393	*/
394	if ( pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
395	&& !(uErr & X86_TRAP_PF_P))
396	{
397	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, pvFault, PGM_SYNC_NR_PAGES, uErr);
398	if ( RT_FAILURE(rc)
399	\|\| !(uErr & X86_TRAP_PF_RW)
400	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
401	{
402	AssertRC(rc);
403	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersOutOfSync);
404	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
405	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2OutOfSyncHndPhys; });
406	return rc;
407	}
408	}
409	# endif
410
411	AssertMsg( pCur->enmType != PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
412	\|\| (pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE && (uErr & X86_TRAP_PF_RW)),
413	("Unexpected trap for physical handler: %08X (phys=%08x) HCPhys=%X uErr=%X, enum=%d\n", pvFault, GCPhys, pPage->HCPhys, uErr, pCur->enmType));
414
415	# if defined(IN_RC) \|\| defined(IN_RING0)
416	if (pCur->CTX_SUFF(pfnHandler))
417	{
418	STAM_PROFILE_START(&pCur->Stat, h);
419	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, GCPhysFault, pCur->CTX_SUFF(pvUser));
420	STAM_PROFILE_STOP(&pCur->Stat, h);
421	}
422	else
423	# endif
424	rc = VINF_EM_RAW_EMULATE_INSTR;
425	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersPhysical);
426	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
427	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2HndPhys; });
428	return rc;
429	}
430	}
431	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
432	else
433	{
434	# ifdef PGM_SYNC_N_PAGES
435	/*
436	* If the region is write protected and we got a page not present fault, then sync
437	* the pages. If the fault was caused by a read, then restart the instruction.
438	* In case of write access continue to the GC write handler.
439	*/
440	if ( PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) < PGM_PAGE_HNDL_PHYS_STATE_ALL
441	&& !(uErr & X86_TRAP_PF_P))
442	{
443	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, pvFault, PGM_SYNC_NR_PAGES, uErr);
444	if ( RT_FAILURE(rc)
445	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
446	\|\| !(uErr & X86_TRAP_PF_RW))
447	{
448	AssertRC(rc);
449	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersOutOfSync);
450	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
451	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2OutOfSyncHndVirt; });
452	return rc;
453	}
454	}
455	# endif
456	/*
457	* Ok, it's an virtual page access handler.
458	*
459	* Since it's faster to search by address, we'll do that first
460	* and then retry by GCPhys if that fails.
461	*/
462	/** @todo r=bird: perhaps we should consider looking up by physical address directly now? */
463	/** @note r=svl: true, but lookup on virtual address should remain as a fallback as phys & virt trees might be out of sync, because the
464	* page was changed without us noticing it (not-present -> present without invlpg or mov cr3, xxx)
465	*/
466	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
467	if (pCur)
468	{
469	AssertMsg(!(pvFault - pCur->Core.Key < pCur->cb)
470	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
471	\|\| !(uErr & X86_TRAP_PF_P)
472	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
473	("Unexpected trap for virtual handler: %RGv (phys=%RGp) HCPhys=%HGp uErr=%X, enum=%d\n", pvFault, GCPhys, pPage->HCPhys, uErr, pCur->enmType));
474
475	if ( pvFault - pCur->Core.Key < pCur->cb
476	&& ( uErr & X86_TRAP_PF_RW
477	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
478	{
479	# ifdef IN_RC
480	STAM_PROFILE_START(&pCur->Stat, h);
481	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
482	STAM_PROFILE_STOP(&pCur->Stat, h);
483	# else
484	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
485	# endif
486	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersVirtual);
487	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
488	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2HndVirt; });
489	return rc;
490	}
491	/* Unhandled part of a monitored page */
492	}
493	else
494	{
495	/* Check by physical address. */
496	PPGMVIRTHANDLER pCur;
497	unsigned iPage;
498	rc = pgmHandlerVirtualFindByPhysAddr(pVM, GCPhys + (pvFault & PAGE_OFFSET_MASK),
499	&pCur, &iPage);
500	Assert(RT_SUCCESS(rc) \|\| !pCur);
501	if ( pCur
502	&& ( uErr & X86_TRAP_PF_RW
503	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
504	{
505	Assert((pCur->aPhysToVirt[iPage].Core.Key & X86_PTE_PAE_PG_MASK) == GCPhys);
506	# ifdef IN_RC
507	RTGCPTR off = (iPage << PAGE_SHIFT) + (pvFault & PAGE_OFFSET_MASK) - (pCur->Core.Key & PAGE_OFFSET_MASK);
508	Assert(off < pCur->cb);
509	STAM_PROFILE_START(&pCur->Stat, h);
510	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, off);
511	STAM_PROFILE_STOP(&pCur->Stat, h);
512	# else
513	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
514	# endif
515	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersVirtualByPhys);
516	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
517	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2HndVirt; });
518	return rc;
519	}
520	}
521	}
522	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
523
524	/*
525	* There is a handled area of the page, but this fault doesn't belong to it.
526	* We must emulate the instruction.
527	*
528	* To avoid crashing (non-fatal) in the interpreter and go back to the recompiler
529	* we first check if this was a page-not-present fault for a page with only
530	* write access handlers. Restart the instruction if it wasn't a write access.
531	*/
532	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersUnhandled);
533
534	if ( !PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
535	&& !(uErr & X86_TRAP_PF_P))
536	{
537	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, pvFault, PGM_SYNC_NR_PAGES, uErr);
538	if ( RT_FAILURE(rc)
539	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
540	\|\| !(uErr & X86_TRAP_PF_RW))
541	{
542	AssertRC(rc);
543	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersOutOfSync);
544	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
545	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2OutOfSyncHndPhys; });
546	return rc;
547	}
548	}
549
550	/** @todo This particular case can cause quite a lot of overhead. E.g. early stage of kernel booting in Ubuntu 6.06
551	* It's writing to an unhandled part of the LDT page several million times.
552	*/
553	rc = PGMInterpretInstruction(pVM, pRegFrame, pvFault);
554	LogFlow(("PGM: PGMInterpretInstruction -> rc=%d HCPhys=%RHp%s%s\n",
555	rc, pPage->HCPhys,
556	PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage) ? " phys" : "",
557	PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage) ? " virt" : ""));
558	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
559	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2HndUnhandled; });
560	return rc;
561	} /* if any kind of handler */
562
563	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
564	if (uErr & X86_TRAP_PF_P)
565	{
566	/*
567	* The page isn't marked, but it might still be monitored by a virtual page access handler.
568	* (ASSUMES no temporary disabling of virtual handlers.)
569	*/
570	/** @todo r=bird: Since the purpose is to catch out of sync pages with virtual handler(s) here,
571	* we should correct both the shadow page table and physical memory flags, and not only check for
572	* accesses within the handler region but for access to pages with virtual handlers. */
573	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
574	if (pCur)
575	{
576	AssertMsg( !(pvFault - pCur->Core.Key < pCur->cb)
577	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
578	\|\| !(uErr & X86_TRAP_PF_P)
579	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
580	("Unexpected trap for virtual handler: %08X (phys=%08x) HCPhys=%X uErr=%X, enum=%d\n", pvFault, GCPhys, pPage->HCPhys, uErr, pCur->enmType));
581
582	if ( pvFault - pCur->Core.Key < pCur->cb
583	&& ( uErr & X86_TRAP_PF_RW
584	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
585	{
586	# ifdef IN_RC
587	STAM_PROFILE_START(&pCur->Stat, h);
588	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
589	STAM_PROFILE_STOP(&pCur->Stat, h);
590	# else
591	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
592	# endif
593	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersVirtualUnmarked);
594	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
595	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2HndVirt; });
596	return rc;
597	}
598	}
599	}
600	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
601	}
602	else
603	{
604	/* When the guest accesses invalid physical memory (e.g. probing of RAM or accessing a remapped MMIO range), then we'll fall
605	* back to the recompiler to emulate the instruction.
606	*/
607	LogFlow(("pgmPhysGetPageEx %RGp failed with %Rrc\n", GCPhys, rc));
608	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersInvalid);
609	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
610	return VINF_EM_RAW_EMULATE_INSTR;
611	}
612
613	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
614
615	# ifdef PGM_OUT_OF_SYNC_IN_GC
616	/*
617	* We are here only if page is present in Guest page tables and trap is not handled
618	* by our handlers.
619	* Check it for page out-of-sync situation.
620	*/
621	STAM_PROFILE_START(&pVM->pgm.s.StatRZTrap0eTimeOutOfSync, c);
622
623	if (!(uErr & X86_TRAP_PF_P))
624	{
625	/*
626	* Page is not present in our page tables.
627	* Try to sync it!
628	* BTW, fPageShw is invalid in this branch!
629	*/
630	if (uErr & X86_TRAP_PF_US)
631	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncUser));
632	else /* supervisor */
633	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
634
635	# if defined(LOG_ENABLED) && !defined(IN_RING0)
636	RTGCPHYS GCPhys;
637	uint64_t fPageGst;
638	PGMGstGetPage(pVM, pvFault, &fPageGst, &GCPhys);
639	Log(("Page out of sync: %RGv eip=%08x PdeSrc.n.u1User=%d fPageGst=%08llx GCPhys=%RGp scan=%d\n",
640	pvFault, pRegFrame->eip, PdeSrc.n.u1User, fPageGst, GCPhys, CSAMDoesPageNeedScanning(pVM, (RTRCPTR)pRegFrame->eip)));
641	# endif /* LOG_ENABLED */
642
643	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0)
644	if (CPUMGetGuestCPL(pVM, pRegFrame) == 0)
645	{
646	uint64_t fPageGst;
647	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, NULL);
648	if ( RT_SUCCESS(rc)
649	&& !(fPageGst & X86_PTE_US))
650	{
651	/* Note: can't check for X86_TRAP_ID bit, because that requires execute disable support on the CPU */
652	if ( pvFault == (RTGCPTR)pRegFrame->eip
653	\|\| pvFault - pRegFrame->eip < 8 /* instruction crossing a page boundary */
654	# ifdef CSAM_DETECT_NEW_CODE_PAGES
655	\|\| ( !PATMIsPatchGCAddr(pVM, (RTGCPTR)pRegFrame->eip)
656	&& CSAMDoesPageNeedScanning(pVM, (RTRCPTR)pRegFrame->eip)) /* any new code we encounter here */
657	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
658	)
659	{
660	LogFlow(("CSAMExecFault %RX32\n", pRegFrame->eip));
661	rc = CSAMExecFault(pVM, (RTRCPTR)pRegFrame->eip);
662	if (rc != VINF_SUCCESS)
663	{
664	/*
665	* CSAM needs to perform a job in ring 3.
666	*
667	* Sync the page before going to the host context; otherwise we'll end up in a loop if
668	* CSAM fails (e.g. instruction crosses a page boundary and the next page is not present)
669	*/
670	LogFlow(("CSAM ring 3 job\n"));
671	int rc2 = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, pvFault, 1, uErr);
672	AssertRC(rc2);
673
674	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeOutOfSync, c);
675	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2CSAM; });
676	return rc;
677	}
678	}
679	# ifdef CSAM_DETECT_NEW_CODE_PAGES
680	else if ( uErr == X86_TRAP_PF_RW
681	&& pRegFrame->ecx >= 0x100 /* early check for movswd count */
682	&& pRegFrame->ecx < 0x10000)
683	{
684	/* In case of a write to a non-present supervisor shadow page, we'll take special precautions
685	* to detect loading of new code pages.
686	*/
687
688	/*
689	* Decode the instruction.
690	*/
691	RTGCPTR PC;
692	rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->eip, &PC);
693	if (rc == VINF_SUCCESS)
694	{
695	DISCPUSTATE Cpu;
696	uint32_t cbOp;
697	rc = EMInterpretDisasOneEx(pVM, PC, pRegFrame, &Cpu, &cbOp);
698
699	/* For now we'll restrict this to rep movsw/d instructions */
700	if ( rc == VINF_SUCCESS
701	&& Cpu.pCurInstr->opcode == OP_MOVSWD
702	&& (Cpu.prefix & PREFIX_REP))
703	{
704	CSAMMarkPossibleCodePage(pVM, pvFault);
705	}
706	}
707	}
708	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
709
710	/*
711	* Mark this page as safe.
712	*/
713	/** @todo not correct for pages that contain both code and data!! */
714	Log2(("CSAMMarkPage %RGv; scanned=%d\n", pvFault, true));
715	CSAMMarkPage(pVM, (RTRCPTR)pvFault, true);
716	}
717	}
718	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0) */
719	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, pvFault, PGM_SYNC_NR_PAGES, uErr);
720	if (RT_SUCCESS(rc))
721	{
722	/* The page was successfully synced, return to the guest. */
723	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeOutOfSync, c);
724	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2OutOfSync; });
725	return VINF_SUCCESS;
726	}
727	}
728	else
729	{
730	/*
731	* A side effect of not flushing global PDEs are out of sync pages due
732	* to physical monitored regions, that are no longer valid.
733	* Assume for now it only applies to the read/write flag
734	*/
735	if (RT_SUCCESS(rc) && (uErr & X86_TRAP_PF_RW))
736	{
737	if (uErr & X86_TRAP_PF_US)
738	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncUser));
739	else /* supervisor */
740	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
741
742
743	/*
744	* Note: Do NOT use PGM_SYNC_NR_PAGES here. That only works if the page is not present, which is not true in this case.
745	*/
746	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, pvFault, 1, uErr);
747	if (RT_SUCCESS(rc))
748	{
749	/*
750	* Page was successfully synced, return to guest.
751	*/
752	# ifdef VBOX_STRICT
753	RTGCPHYS GCPhys;
754	uint64_t fPageGst;
755	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, &GCPhys);
756	Assert(RT_SUCCESS(rc) && fPageGst & X86_PTE_RW);
757	LogFlow(("Obsolete physical monitor page out of sync %RGv - phys %RGp flags=%08llx\n", pvFault, GCPhys, (uint64_t)fPageGst));
758
759	uint64_t fPageShw;
760	rc = PGMShwGetPage(pVM, pvFault, &fPageShw, NULL);
761	AssertMsg(RT_SUCCESS(rc) && fPageShw & X86_PTE_RW, ("rc=%Rrc fPageShw=%RX64\n", rc, fPageShw));
762	# endif /* VBOX_STRICT */
763	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeOutOfSync, c);
764	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2OutOfSyncHndObs; });
765	return VINF_SUCCESS;
766	}
767
768	/* Check to see if we need to emulate the instruction as X86_CR0_WP has been cleared. */
769	if ( CPUMGetGuestCPL(pVM, pRegFrame) == 0
770	&& ((CPUMGetGuestCR0(pVM) & (X86_CR0_WP \| X86_CR0_PG)) == X86_CR0_PG)
771	&& (uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RW \| X86_TRAP_PF_P))
772	{
773	uint64_t fPageGst;
774	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, NULL);
775	if ( RT_SUCCESS(rc)
776	&& !(fPageGst & X86_PTE_RW))
777	{
778	rc = PGMInterpretInstruction(pVM, pRegFrame, pvFault);
779	if (RT_SUCCESS(rc))
780	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eWPEmulInRZ);
781	else
782	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eWPEmulToR3);
783	return rc;
784	}
785	AssertMsgFailed(("Unexpected r/w page %RGv flag=%x rc=%Rrc\n", pvFault, (uint32_t)fPageGst, rc));
786	}
787	}
788
789	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
790	# ifdef VBOX_STRICT
791	/*
792	* Check for VMM page flags vs. Guest page flags consistency.
793	* Currently only for debug purposes.
794	*/
795	if (RT_SUCCESS(rc))
796	{
797	/* Get guest page flags. */
798	uint64_t fPageGst;
799	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, NULL);
800	if (RT_SUCCESS(rc))
801	{
802	uint64_t fPageShw;
803	rc = PGMShwGetPage(pVM, pvFault, &fPageShw, NULL);
804
805	/*
806	* Compare page flags.
807	* Note: we have AVL, A, D bits desynched.
808	*/
809	AssertMsg((fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)) == (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)),
810	("Page flags mismatch! pvFault=%RGv GCPhys=%RGp fPageShw=%08llx fPageGst=%08llx\n", pvFault, GCPhys, fPageShw, fPageGst));
811	}
812	else
813	AssertMsgFailed(("PGMGstGetPage rc=%Rrc\n", rc));
814	}
815	else
816	AssertMsgFailed(("PGMGCGetPage rc=%Rrc\n", rc));
817	# endif /* VBOX_STRICT */
818	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
819	}
820	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeOutOfSync, c);
821	# endif /* PGM_OUT_OF_SYNC_IN_GC */
822	}
823	else
824	{
825	/*
826	* Page not present in Guest OS or invalid page table address.
827	* This is potential virtual page access handler food.
828	*
829	* For the present we'll say that our access handlers don't
830	* work for this case - we've already discarded the page table
831	* not present case which is identical to this.
832	*
833	* When we perchance find we need this, we will probably have AVL
834	* trees (offset based) to operate on and we can measure their speed
835	* agains mapping a page table and probably rearrange this handling
836	* a bit. (Like, searching virtual ranges before checking the
837	* physical address.)
838	*/
839	}
840	}
841
842
843	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
844	/*
845	* Conclusion, this is a guest trap.
846	*/
847	LogFlow(("PGM: Unhandled #PF -> route trap to recompiler!\n"));
848	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eGuestPFUnh);
849	return VINF_EM_RAW_GUEST_TRAP;
850	# else
851	/* present, but not a monitored page; perhaps the guest is probing physical memory */
852	return VINF_EM_RAW_EMULATE_INSTR;
853	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
854
855
856	# else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
857
858	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
859	return VERR_INTERNAL_ERROR;
860	# endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
861	}
862	#endif /* !IN_RING3 */
863
864
865	/**
866	* Emulation of the invlpg instruction.
867	*
868	*
869	* @returns VBox status code.
870	*
871	* @param pVM VM handle.
872	* @param GCPtrPage Page to invalidate.
873	*
874	* @remark ASSUMES that the guest is updating before invalidating. This order
875	* isn't required by the CPU, so this is speculative and could cause
876	* trouble.
877	*
878	* @todo Flush page or page directory only if necessary!
879	* @todo Add a #define for simply invalidating the page.
880	*/
881	PGM_BTH_DECL(int, InvalidatePage)(PVM pVM, RTGCPTR GCPtrPage)
882	{
883	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
884	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
885	&& PGM_SHW_TYPE != PGM_TYPE_EPT
886	int rc;
887
888	LogFlow(("InvalidatePage %RGv\n", GCPtrPage));
889	/*
890	* Get the shadow PD entry and skip out if this PD isn't present.
891	* (Guessing that it is frequent for a shadow PDE to not be present, do this first.)
892	*/
893	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
894	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
895	PX86PDE pPdeDst = &pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst];
896	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
897	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT);
898	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(&pVM->pgm.s);
899
900	/* If the shadow PDPE isn't present, then skip the invalidate. */
901	if (!pPdptDst->a[iPdpt].n.u1Present)
902	{
903	Assert(!(pPdptDst->a[iPdpt].u & PGM_PLXFLAGS_MAPPING));
904	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
905	return VINF_SUCCESS;
906	}
907
908	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) /& SHW_PD_MASK - pool index only atm! /;
909	PX86PDEPAE pPdeDst = pgmShwGetPaePDEPtr(&pVM->pgm.s, GCPtrPage);
910
911	# else /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
912	/* PML4 */
913	AssertReturn(pVM->pgm.s.pShwPaePml4R3, VERR_INTERNAL_ERROR);
914
915	const unsigned iPml4 = (GCPtrPage >> X86_PML4_SHIFT) & X86_PML4_MASK;
916	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
917	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
918	PX86PDPAE pPDDst;
919	PX86PDPT pPdptDst;
920	PX86PML4E pPml4eDst;
921	rc = pgmShwGetLongModePDPtr(pVM, GCPtrPage, &pPml4eDst, &pPdptDst, &pPDDst);
922	if (rc != VINF_SUCCESS)
923	{
924	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT \|\| rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
925	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
926	if (!VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3))
927	PGM_INVL_GUEST_TLBS();
928	return VINF_SUCCESS;
929	}
930	Assert(pPDDst);
931
932	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
933	PX86PDPE pPdpeDst = &pPdptDst->a[iPdpt];
934
935	if (!pPdpeDst->n.u1Present)
936	{
937	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
938	if (!VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3))
939	PGM_INVL_GUEST_TLBS();
940	return VINF_SUCCESS;
941	}
942
943	# endif /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
944
945	const SHWPDE PdeDst = *pPdeDst;
946	if (!PdeDst.n.u1Present)
947	{
948	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
949	return VINF_SUCCESS;
950	}
951
952	/*
953	* Get the guest PD entry and calc big page.
954	*/
955	# if PGM_GST_TYPE == PGM_TYPE_32BIT
956	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(&pVM->pgm.s);
957	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
958	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
959	# else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
960	unsigned iPDSrc;
961	# if PGM_GST_TYPE == PGM_TYPE_PAE
962	X86PDPE PdpeSrc;
963	PX86PDPAE pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtrPage, &iPDSrc, &PdpeSrc);
964	# else /* AMD64 */
965	PX86PML4E pPml4eSrc;
966	X86PDPE PdpeSrc;
967	PX86PDPAE pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
968	# endif
969	GSTPDE PdeSrc;
970
971	if (pPDSrc)
972	PdeSrc = pPDSrc->a[iPDSrc];
973	else
974	PdeSrc.u = 0;
975	# endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
976
977	# if PGM_GST_TYPE == PGM_TYPE_AMD64
978	const bool fIsBigPage = PdeSrc.b.u1Size;
979	# else
980	const bool fIsBigPage = PdeSrc.b.u1Size && (CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
981	# endif
982
983	# ifdef IN_RING3
984	/*
985	* If a CR3 Sync is pending we may ignore the invalidate page operation
986	* depending on the kind of sync and if it's a global page or not.
987	* This doesn't make sense in GC/R0 so we'll skip it entirely there.
988	*/
989	# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
990	if ( VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3)
991	\|\| ( VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
992	&& fIsBigPage
993	&& PdeSrc.b.u1Global
994	)
995	)
996	# else
997	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL) )
998	# endif
999	{
1000	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
1001	return VINF_SUCCESS;
1002	}
1003	# endif /* IN_RING3 */
1004
1005	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1006	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1007
1008	/* Fetch the pgm pool shadow descriptor. */
1009	PPGMPOOLPAGE pShwPdpt = pgmPoolGetPageByHCPhys(pVM, pPml4eDst->u & X86_PML4E_PG_MASK);
1010	Assert(pShwPdpt);
1011
1012	/* Fetch the pgm pool shadow descriptor. */
1013	PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(pVM, pPdptDst->a[iPdpt].u & SHW_PDPE_PG_MASK);
1014	Assert(pShwPde);
1015
1016	Assert(pPml4eDst->n.u1Present && (pPml4eDst->u & SHW_PDPT_MASK));
1017	RTGCPHYS GCPhysPdpt = pPml4eSrc->u & X86_PML4E_PG_MASK;
1018
1019	if ( !pPml4eSrc->n.u1Present
1020	\|\| pShwPdpt->GCPhys != GCPhysPdpt)
1021	{
1022	LogFlow(("InvalidatePage: Out-of-sync PML4E (P/GCPhys) at %RGv GCPhys=%RGp vs %RGp Pml4eSrc=%RX64 Pml4eDst=%RX64\n",
1023	GCPtrPage, pShwPdpt->GCPhys, GCPhysPdpt, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
1024	pgmPoolFreeByPage(pPool, pShwPdpt, pVM->pgm.s.CTX_SUFF(pShwAmd64CR3)->idx, iPml4);
1025	pPml4eDst->u = 0;
1026	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNPs));
1027	PGM_INVL_GUEST_TLBS();
1028	return VINF_SUCCESS;
1029	}
1030	if ( pPml4eSrc->n.u1User != pPml4eDst->n.u1User
1031	\|\| (!pPml4eSrc->n.u1Write && pPml4eDst->n.u1Write))
1032	{
1033	/*
1034	* Mark not present so we can resync the PML4E when it's used.
1035	*/
1036	LogFlow(("InvalidatePage: Out-of-sync PML4E at %RGv Pml4eSrc=%RX64 Pml4eDst=%RX64\n",
1037	GCPtrPage, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
1038	pgmPoolFreeByPage(pPool, pShwPdpt, pVM->pgm.s.CTX_SUFF(pShwAmd64CR3)->idx, iPml4);
1039	pPml4eDst->u = 0;
1040	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1041	PGM_INVL_GUEST_TLBS();
1042	}
1043	else if (!pPml4eSrc->n.u1Accessed)
1044	{
1045	/*
1046	* Mark not present so we can set the accessed bit.
1047	*/
1048	LogFlow(("InvalidatePage: Out-of-sync PML4E (A) at %RGv Pml4eSrc=%RX64 Pml4eDst=%RX64\n",
1049	GCPtrPage, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
1050	pgmPoolFreeByPage(pPool, pShwPdpt, pVM->pgm.s.CTX_SUFF(pShwAmd64CR3)->idx, iPml4);
1051	pPml4eDst->u = 0;
1052	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNAs));
1053	PGM_INVL_GUEST_TLBS();
1054	}
1055
1056	/* Check if the PDPT entry has changed. */
1057	Assert(pPdpeDst->n.u1Present && pPdpeDst->u & SHW_PDPT_MASK);
1058	RTGCPHYS GCPhysPd = PdpeSrc.u & GST_PDPE_PG_MASK;
1059	if ( !PdpeSrc.n.u1Present
1060	\|\| pShwPde->GCPhys != GCPhysPd)
1061	{
1062	LogFlow(("InvalidatePage: Out-of-sync PDPE (P/GCPhys) at %RGv GCPhys=%RGp vs %RGp PdpeSrc=%RX64 PdpeDst=%RX64\n",
1063	GCPtrPage, pShwPde->GCPhys, GCPhysPd, (uint64_t)PdpeSrc.u, (uint64_t)pPdpeDst->u));
1064	pgmPoolFreeByPage(pPool, pShwPde, pShwPdpt->idx, iPdpt);
1065	pPdpeDst->u = 0;
1066	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNPs));
1067	PGM_INVL_GUEST_TLBS();
1068	return VINF_SUCCESS;
1069	}
1070	if ( PdpeSrc.lm.u1User != pPdpeDst->lm.u1User
1071	\|\| (!PdpeSrc.lm.u1Write && pPdpeDst->lm.u1Write))
1072	{
1073	/*
1074	* Mark not present so we can resync the PDPTE when it's used.
1075	*/
1076	LogFlow(("InvalidatePage: Out-of-sync PDPE at %RGv PdpeSrc=%RX64 PdpeDst=%RX64\n",
1077	GCPtrPage, (uint64_t)PdpeSrc.u, (uint64_t)pPdpeDst->u));
1078	pgmPoolFreeByPage(pPool, pShwPde, pShwPdpt->idx, iPdpt);
1079	pPdpeDst->u = 0;
1080	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1081	PGM_INVL_GUEST_TLBS();
1082	}
1083	else if (!PdpeSrc.lm.u1Accessed)
1084	{
1085	/*
1086	* Mark not present so we can set the accessed bit.
1087	*/
1088	LogFlow(("InvalidatePage: Out-of-sync PDPE (A) at %RGv PdpeSrc=%RX64 PdpeDst=%RX64\n",
1089	GCPtrPage, (uint64_t)PdpeSrc.u, (uint64_t)pPdpeDst->u));
1090	pgmPoolFreeByPage(pPool, pShwPde, pShwPdpt->idx, iPdpt);
1091	pPdpeDst->u = 0;
1092	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNAs));
1093	PGM_INVL_GUEST_TLBS();
1094	}
1095	# endif /* PGM_GST_TYPE == PGM_TYPE_AMD64 */
1096
1097	# if PGM_GST_TYPE == PGM_TYPE_PAE
1098	/*
1099	* Update the shadow PDPE and free all the shadow PD entries if the PDPE is marked not present.
1100	* Note: This shouldn't actually be necessary as we monitor the PDPT page for changes.
1101	*/
1102	if (!pPDSrc)
1103	{
1104	/* Guest PDPE not present */
1105	PX86PDPAE pPDDst = pgmShwGetPaePDPtr(&pVM->pgm.s, GCPtrPage);
1106	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1107
1108	Assert(!PdpeSrc.n.u1Present);
1109	LogFlow(("InvalidatePage: guest PDPE %d not present; clear shw pdpe\n", iPdpt));
1110
1111	/* for each page directory entry */
1112	for (unsigned iPD = 0; iPD < X86_PG_PAE_ENTRIES; iPD++)
1113	{
1114	if ( pPDDst->a[iPD].n.u1Present
1115	&& !(pPDDst->a[iPD].u & PGM_PDFLAGS_MAPPING))
1116	{
1117	pgmPoolFree(pVM, pPDDst->a[iPD].u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPdpt * X86_PG_PAE_ENTRIES + iPD);
1118	pPDDst->a[iPD].u = 0;
1119	}
1120	}
1121	if (!(pPdptDst->a[iPdpt].u & PGM_PLXFLAGS_MAPPING))
1122	pPdptDst->a[iPdpt].n.u1Present = 0;
1123	PGM_INVL_GUEST_TLBS();
1124	}
1125	AssertMsg(pVM->pgm.s.fMappingsFixed \|\| (PdpeSrc.u & X86_PDPE_PG_MASK) == pVM->pgm.s.aGCPhysGstPaePDsMonitored[iPdpt], ("%RGp vs %RGp (mon)\n", (PdpeSrc.u & X86_PDPE_PG_MASK), pVM->pgm.s.aGCPhysGstPaePDsMonitored[iPdpt]));
1126	# endif
1127
1128
1129	/*
1130	* Deal with the Guest PDE.
1131	*/
1132	rc = VINF_SUCCESS;
1133	if (PdeSrc.n.u1Present)
1134	{
1135	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
1136	{
1137	/*
1138	* Conflict - Let SyncPT deal with it to avoid duplicate code.
1139	*/
1140	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1141	Assert(PGMGetGuestMode(pVM) <= PGMMODE_PAE);
1142	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, GCPtrPage);
1143	}
1144	else if ( PdeSrc.n.u1User != PdeDst.n.u1User
1145	\|\| (!PdeSrc.n.u1Write && PdeDst.n.u1Write))
1146	{
1147	/*
1148	* Mark not present so we can resync the PDE when it's used.
1149	*/
1150	LogFlow(("InvalidatePage: Out-of-sync at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
1151	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1152	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1153	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1154	# else
1155	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1156	# endif
1157	pPdeDst->u = 0;
1158	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1159	PGM_INVL_GUEST_TLBS();
1160	}
1161	else if (!PdeSrc.n.u1Accessed)
1162	{
1163	/*
1164	* Mark not present so we can set the accessed bit.
1165	*/
1166	LogFlow(("InvalidatePage: Out-of-sync (A) at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
1167	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1168	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1169	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1170	# else
1171	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1172	# endif
1173	pPdeDst->u = 0;
1174	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNAs));
1175	PGM_INVL_GUEST_TLBS();
1176	}
1177	else if (!fIsBigPage)
1178	{
1179	/*
1180	* 4KB - page.
1181	*/
1182	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1183	RTGCPHYS GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
1184	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1185	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1186	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE/2);
1187	# endif
1188	if (pShwPage->GCPhys == GCPhys)
1189	{
1190	# if 0 /* likely cause of a major performance regression; must be SyncPageWorkerTrackDeref then */
1191	const unsigned iPTEDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1192	PSHWPT pPT = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1193	if (pPT->a[iPTEDst].n.u1Present)
1194	{
1195	# ifdef PGMPOOL_WITH_USER_TRACKING
1196	/* This is very unlikely with caching/monitoring enabled. */
1197	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPT->a[iPTEDst].u & SHW_PTE_PG_MASK);
1198	# endif
1199	pPT->a[iPTEDst].u = 0;
1200	}
1201	# else /* Syncing it here isn't 100% safe and it's probably not worth spending time syncing it. */
1202	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, 1, 0);
1203	if (RT_SUCCESS(rc))
1204	rc = VINF_SUCCESS;
1205	# endif
1206	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePage4KBPages));
1207	PGM_INVL_PG(GCPtrPage);
1208	}
1209	else
1210	{
1211	/*
1212	* The page table address changed.
1213	*/
1214	LogFlow(("InvalidatePage: Out-of-sync at %RGp PdeSrc=%RX64 PdeDst=%RX64 ShwGCPhys=%RGp iPDDst=%#x\n",
1215	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, iPDDst));
1216	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1217	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1218	# else
1219	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1220	# endif
1221	pPdeDst->u = 0;
1222	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1223	PGM_INVL_GUEST_TLBS();
1224	}
1225	}
1226	else
1227	{
1228	/*
1229	* 2/4MB - page.
1230	*/
1231	/* Before freeing the page, check if anything really changed. */
1232	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1233	RTGCPHYS GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
1234	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1235	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1236	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
1237	# endif
1238	if ( pShwPage->GCPhys == GCPhys
1239	&& pShwPage->enmKind == BTH_PGMPOOLKIND_PT_FOR_BIG)
1240	{
1241	/* ASSUMES a the given bits are identical for 4M and normal PDEs */
1242	/** @todo PAT */
1243	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD))
1244	== (PdeDst.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD))
1245	&& ( PdeSrc.b.u1Dirty /** @todo rainy day: What about read-only 4M pages? not very common, but still... */
1246	\|\| (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)))
1247	{
1248	LogFlow(("Skipping flush for big page containing %RGv (PD=%X .u=%RX64)-> nothing has changed!\n", GCPtrPage, iPDSrc, PdeSrc.u));
1249	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePage4MBPagesSkip));
1250	return VINF_SUCCESS;
1251	}
1252	}
1253
1254	/*
1255	* Ok, the page table is present and it's been changed in the guest.
1256	* If we're in host context, we'll just mark it as not present taking the lazy approach.
1257	* We could do this for some flushes in GC too, but we need an algorithm for
1258	* deciding which 4MB pages containing code likely to be executed very soon.
1259	*/
1260	LogFlow(("InvalidatePage: Out-of-sync PD at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
1261	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1262	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1263	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1264	# else
1265	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1266	# endif
1267	pPdeDst->u = 0;
1268	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePage4MBPages));
1269	PGM_INVL_BIG_PG(GCPtrPage);
1270	}
1271	}
1272	else
1273	{
1274	/*
1275	* Page directory is not present, mark shadow PDE not present.
1276	*/
1277	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
1278	{
1279	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1280	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1281	# else
1282	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1283	# endif
1284	pPdeDst->u = 0;
1285	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNPs));
1286	PGM_INVL_PG(GCPtrPage);
1287	}
1288	else
1289	{
1290	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1291	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDMappings));
1292	}
1293	}
1294
1295	return rc;
1296
1297	#else /* guest real and protected mode */
1298	/* There's no such thing as InvalidatePage when paging is disabled, so just ignore. */
1299	return VINF_SUCCESS;
1300	#endif
1301	}
1302
1303
1304	#ifdef PGMPOOL_WITH_USER_TRACKING
1305	/**
1306	* Update the tracking of shadowed pages.
1307	*
1308	* @param pVM The VM handle.
1309	* @param pShwPage The shadow page.
1310	* @param HCPhys The physical page we is being dereferenced.
1311	*/
1312	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVM pVM, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys)
1313	{
1314	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1315	STAM_PROFILE_START(&pVM->pgm.s.StatTrackDeref, a);
1316	LogFlow(("SyncPageWorkerTrackDeref: Damn HCPhys=%RHp pShwPage->idx=%#x!!!\n", HCPhys, pShwPage->idx));
1317
1318	/** @todo If this turns out to be a bottle neck (very likely) two things can be done:
1319	* 1. have a medium sized HCPhys -> GCPhys TLB (hash?)
1320	* 2. write protect all shadowed pages. I.e. implement caching.
1321	*/
1322	/*
1323	* Find the guest address.
1324	*/
1325	for (PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
1326	pRam;
1327	pRam = pRam->CTX_SUFF(pNext))
1328	{
1329	unsigned iPage = pRam->cb >> PAGE_SHIFT;
1330	while (iPage-- > 0)
1331	{
1332	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
1333	{
1334	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1335	pgmTrackDerefGCPhys(pPool, pShwPage, &pRam->aPages[iPage]);
1336	pShwPage->cPresent--;
1337	pPool->cPresent--;
1338	STAM_PROFILE_STOP(&pVM->pgm.s.StatTrackDeref, a);
1339	return;
1340	}
1341	}
1342	}
1343
1344	for (;;)
1345	AssertReleaseMsgFailed(("HCPhys=%RHp wasn't found!\n", HCPhys));
1346	# else /* !PGMPOOL_WITH_GCPHYS_TRACKING */
1347	pShwPage->cPresent--;
1348	pVM->pgm.s.CTX_SUFF(pPool)->cPresent--;
1349	# endif /* !PGMPOOL_WITH_GCPHYS_TRACKING */
1350	}
1351
1352
1353	/**
1354	* Update the tracking of shadowed pages.
1355	*
1356	* @param pVM The VM handle.
1357	* @param pShwPage The shadow page.
1358	* @param u16 The top 16-bit of the pPage->HCPhys.
1359	* @param pPage Pointer to the guest page. this will be modified.
1360	* @param iPTDst The index into the shadow table.
1361	*/
1362	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackAddref)(PVM pVM, PPGMPOOLPAGE pShwPage, uint16_t u16, PPGMPAGE pPage, const unsigned iPTDst)
1363	{
1364	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1365	/*
1366	* We're making certain assumptions about the placement of cRef and idx.
1367	*/
1368	Assert(MM_RAM_FLAGS_IDX_SHIFT == 48);
1369	Assert(MM_RAM_FLAGS_CREFS_SHIFT > MM_RAM_FLAGS_IDX_SHIFT);
1370
1371	/*
1372	* Just deal with the simple first time here.
1373	*/
1374	if (!u16)
1375	{
1376	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackVirgin);
1377	u16 = (1 << (MM_RAM_FLAGS_CREFS_SHIFT - MM_RAM_FLAGS_IDX_SHIFT)) \| pShwPage->idx;
1378	}
1379	else
1380	u16 = pgmPoolTrackPhysExtAddref(pVM, u16, pShwPage->idx);
1381
1382	/* write back, trying to be clever... */
1383	Log2(("SyncPageWorkerTrackAddRef: u16=%#x pPage->HCPhys=%RHp->%RHp iPTDst=%#x\n",
1384	u16, pPage->HCPhys, (pPage->HCPhys & MM_RAM_FLAGS_NO_REFS_MASK) \| ((uint64_t)u16 << MM_RAM_FLAGS_CREFS_SHIFT), iPTDst));
1385	((uint16_t )&pPage->HCPhys + 3) = u16; /** @todo PAGE FLAGS */
1386	# endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
1387
1388	/* update statistics. */
1389	pVM->pgm.s.CTX_SUFF(pPool)->cPresent++;
1390	pShwPage->cPresent++;
1391	if (pShwPage->iFirstPresent > iPTDst)
1392	pShwPage->iFirstPresent = iPTDst;
1393	}
1394	#endif /* PGMPOOL_WITH_USER_TRACKING */
1395
1396
1397	/**
1398	* Creates a 4K shadow page for a guest page.
1399	*
1400	* For 4M pages the caller must convert the PDE4M to a PTE, this includes adjusting the
1401	* physical address. The PdeSrc argument only the flags are used. No page structured
1402	* will be mapped in this function.
1403	*
1404	* @param pVM VM handle.
1405	* @param pPteDst Destination page table entry.
1406	* @param PdeSrc Source page directory entry (i.e. Guest OS page directory entry).
1407	* Can safely assume that only the flags are being used.
1408	* @param PteSrc Source page table entry (i.e. Guest OS page table entry).
1409	* @param pShwPage Pointer to the shadow page.
1410	* @param iPTDst The index into the shadow table.
1411	*
1412	* @remark Not used for 2/4MB pages!
1413	*/
1414	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorker)(PVM pVM, PSHWPTE pPteDst, GSTPDE PdeSrc, GSTPTE PteSrc, PPGMPOOLPAGE pShwPage, unsigned iPTDst)
1415	{
1416	if (PteSrc.n.u1Present)
1417	{
1418	/*
1419	* Find the ram range.
1420	*/
1421	PPGMPAGE pPage;
1422	int rc = pgmPhysGetPageEx(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK, &pPage);
1423	if (RT_SUCCESS(rc))
1424	{
1425	/** @todo investiage PWT, PCD and PAT. */
1426	/*
1427	* Make page table entry.
1428	*/
1429	const RTHCPHYS HCPhys = pPage->HCPhys; /** @todo FLAGS */
1430	SHWPTE PteDst;
1431	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1432	{
1433	/** @todo r=bird: Are we actually handling dirty and access bits for pages with access handlers correctly? No. */
1434	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1435	{
1436	#if PGM_SHW_TYPE == PGM_TYPE_EPT
1437	PteDst.u = (HCPhys & EPT_PTE_PG_MASK);
1438	PteDst.n.u1Present = 1;
1439	PteDst.n.u1Execute = 1;
1440	PteDst.n.u1IgnorePAT = 1;
1441	PteDst.n.u3EMT = VMX_EPT_MEMTYPE_WB;
1442	/* PteDst.n.u1Write = 0 && PteDst.n.u1Size = 0 */
1443	#else
1444	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT \| X86_PTE_RW))
1445	\| (HCPhys & X86_PTE_PAE_PG_MASK);
1446	#endif
1447	}
1448	else
1449	{
1450	LogFlow(("SyncPageWorker: monitored page (%RHp) -> mark not present\n", HCPhys));
1451	PteDst.u = 0;
1452	}
1453	/** @todo count these two kinds. */
1454	}
1455	else
1456	{
1457	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1458	/*
1459	* If the page or page directory entry is not marked accessed,
1460	* we mark the page not present.
1461	*/
1462	if (!PteSrc.n.u1Accessed \|\| !PdeSrc.n.u1Accessed)
1463	{
1464	LogFlow(("SyncPageWorker: page and or page directory not accessed -> mark not present\n"));
1465	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,AccessedPage));
1466	PteDst.u = 0;
1467	}
1468	else
1469	/*
1470	* If the page is not flagged as dirty and is writable, then make it read-only, so we can set the dirty bit
1471	* when the page is modified.
1472	*/
1473	if (!PteSrc.n.u1Dirty && (PdeSrc.n.u1Write & PteSrc.n.u1Write))
1474	{
1475	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyPage));
1476	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT \| X86_PTE_RW))
1477	\| (HCPhys & X86_PTE_PAE_PG_MASK)
1478	\| PGM_PTFLAGS_TRACK_DIRTY;
1479	}
1480	else
1481	#endif
1482	{
1483	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyPageSkipped));
1484	#if PGM_SHW_TYPE == PGM_TYPE_EPT
1485	PteDst.u = (HCPhys & EPT_PTE_PG_MASK);
1486	PteDst.n.u1Present = 1;
1487	PteDst.n.u1Write = 1;
1488	PteDst.n.u1Execute = 1;
1489	PteDst.n.u1IgnorePAT = 1;
1490	PteDst.n.u3EMT = VMX_EPT_MEMTYPE_WB;
1491	/* PteDst.n.u1Size = 0 */
1492	#else
1493	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT))
1494	\| (HCPhys & X86_PTE_PAE_PG_MASK);
1495	#endif
1496	}
1497	}
1498
1499	#ifdef PGMPOOL_WITH_USER_TRACKING
1500	/*
1501	* Keep user track up to date.
1502	*/
1503	if (PteDst.n.u1Present)
1504	{
1505	if (!pPteDst->n.u1Present)
1506	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst);
1507	else if ((pPteDst->u & SHW_PTE_PG_MASK) != (PteDst.u & SHW_PTE_PG_MASK))
1508	{
1509	Log2(("SyncPageWorker: deref! *pPteDst=%RX64 PteDst=%RX64\n", (uint64_t)pPteDst->u, (uint64_t)PteDst.u));
1510	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1511	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst);
1512	}
1513	}
1514	else if (pPteDst->n.u1Present)
1515	{
1516	Log2(("SyncPageWorker: deref! *pPteDst=%RX64\n", (uint64_t)pPteDst->u));
1517	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1518	}
1519	#endif /* PGMPOOL_WITH_USER_TRACKING */
1520
1521	/*
1522	* Update statistics and commit the entry.
1523	*/
1524	if (!PteSrc.n.u1Global)
1525	pShwPage->fSeenNonGlobal = true;
1526	*pPteDst = PteDst;
1527	}
1528	/* else MMIO or invalid page, we must handle them manually in the #PF handler. */
1529	/** @todo count these. */
1530	}
1531	else
1532	{
1533	/*
1534	* Page not-present.
1535	*/
1536	LogFlow(("SyncPageWorker: page not present in Pte\n"));
1537	#ifdef PGMPOOL_WITH_USER_TRACKING
1538	/* Keep user track up to date. */
1539	if (pPteDst->n.u1Present)
1540	{
1541	Log2(("SyncPageWorker: deref! *pPteDst=%RX64\n", (uint64_t)pPteDst->u));
1542	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1543	}
1544	#endif /* PGMPOOL_WITH_USER_TRACKING */
1545	pPteDst->u = 0;
1546	/** @todo count these. */
1547	}
1548	}
1549
1550
1551	/**
1552	* Syncs a guest OS page.
1553	*
1554	* There are no conflicts at this point, neither is there any need for
1555	* page table allocations.
1556	*
1557	* @returns VBox status code.
1558	* @returns VINF_PGM_SYNCPAGE_MODIFIED_PDE if it modifies the PDE in any way.
1559	* @param pVM VM handle.
1560	* @param PdeSrc Page directory entry of the guest.
1561	* @param GCPtrPage Guest context page address.
1562	* @param cPages Number of pages to sync (PGM_SYNC_N_PAGES) (default=1).
1563	* @param uErr Fault error (X86_TRAP_PF_*).
1564	*/
1565	PGM_BTH_DECL(int, SyncPage)(PVM pVM, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr)
1566	{
1567	LogFlow(("SyncPage: GCPtrPage=%RGv cPages=%u uErr=%#x\n", GCPtrPage, cPages, uErr));
1568
1569	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
1570	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
1571	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
1572	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
1573	&& PGM_SHW_TYPE != PGM_TYPE_EPT
1574
1575	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
1576	bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
1577	# endif
1578
1579	/*
1580	* Assert preconditions.
1581	*/
1582	Assert(PdeSrc.n.u1Present);
1583	Assert(cPages);
1584	STAM_COUNTER_INC(&pVM->pgm.s.StatSyncPagePD[(GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK]);
1585
1586	/*
1587	* Get the shadow PDE, find the shadow page table in the pool.
1588	*/
1589	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1590	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
1591	X86PDE PdeDst = pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst];
1592
1593	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1594	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) /& SHW_PD_MASK - only pool index atm! /;
1595	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT);
1596	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(&pVM->pgm.s); NOREF(pPdptDst);
1597	PX86PDEPAE pPdeDst = pgmShwGetPaePDEPtr(&pVM->pgm.s, GCPtrPage);
1598	AssertReturn(pPdeDst, VERR_INTERNAL_ERROR);
1599	X86PDEPAE PdeDst = *pPdeDst;
1600
1601	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1602	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1603	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1604	PX86PDPAE pPDDst;
1605	X86PDEPAE PdeDst;
1606	PX86PDPT pPdptDst;
1607
1608	int rc = pgmShwGetLongModePDPtr(pVM, GCPtrPage, NULL, &pPdptDst, &pPDDst);
1609	AssertRCSuccessReturn(rc, rc);
1610	Assert(pPDDst && pPdptDst);
1611	PdeDst = pPDDst->a[iPDDst];
1612	# endif
1613	Assert(PdeDst.n.u1Present);
1614	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1615
1616	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1617	/* Fetch the pgm pool shadow descriptor. */
1618	PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(pVM, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
1619	Assert(pShwPde);
1620	# endif
1621
1622	/*
1623	* Check that the page is present and that the shadow PDE isn't out of sync.
1624	*/
1625	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1626	const bool fBigPage = PdeSrc.b.u1Size;
1627	# else
1628	const bool fBigPage = PdeSrc.b.u1Size && (CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
1629	# endif
1630	RTGCPHYS GCPhys;
1631	if (!fBigPage)
1632	{
1633	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
1634	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1635	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1636	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE/2);
1637	# endif
1638	}
1639	else
1640	{
1641	GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
1642	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1643	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1644	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
1645	# endif
1646	}
1647	if ( pShwPage->GCPhys == GCPhys
1648	&& PdeSrc.n.u1Present
1649	&& (PdeSrc.n.u1User == PdeDst.n.u1User)
1650	&& (PdeSrc.n.u1Write == PdeDst.n.u1Write \|\| !PdeDst.n.u1Write)
1651	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
1652	&& (!fNoExecuteBitValid \|\| PdeSrc.n.u1NoExecute == PdeDst.n.u1NoExecute)
1653	# endif
1654	)
1655	{
1656	/*
1657	* Check that the PDE is marked accessed already.
1658	* Since we set the accessed bit before getting here on a #PF, this
1659	* check is only meant for dealing with non-#PF'ing paths.
1660	*/
1661	if (PdeSrc.n.u1Accessed)
1662	{
1663	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1664	if (!fBigPage)
1665	{
1666	/*
1667	* 4KB Page - Map the guest page table.
1668	*/
1669	PGSTPT pPTSrc;
1670	int rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
1671	if (RT_SUCCESS(rc))
1672	{
1673	# ifdef PGM_SYNC_N_PAGES
1674	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
1675	if (cPages > 1 && !(uErr & X86_TRAP_PF_P))
1676	{
1677	/*
1678	* This code path is currently only taken when the caller is PGMTrap0eHandler
1679	* for non-present pages!
1680	*
1681	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
1682	* deal with locality.
1683	*/
1684	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1685	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1686	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1687	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
1688	# else
1689	const unsigned offPTSrc = 0;
1690	# endif
1691	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
1692	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
1693	iPTDst = 0;
1694	else
1695	iPTDst -= PGM_SYNC_NR_PAGES / 2;
1696	for (; iPTDst < iPTDstEnd; iPTDst++)
1697	{
1698	if (!pPTDst->a[iPTDst].n.u1Present)
1699	{
1700	GSTPTE PteSrc = pPTSrc->a[offPTSrc + iPTDst];
1701	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(GST_PT_MASK << GST_PT_SHIFT)) \| ((offPTSrc + iPTDst) << PAGE_SHIFT);
1702	NOREF(GCPtrCurPage);
1703	#ifndef IN_RING0
1704	/*
1705	* Assuming kernel code will be marked as supervisor - and not as user level
1706	* and executed using a conforming code selector - And marked as readonly.
1707	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
1708	*/
1709	PPGMPAGE pPage;
1710	if ( ((PdeSrc.u & PteSrc.u) & (X86_PTE_RW \| X86_PTE_US))
1711	\|\| iPTDst == ((GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK) /* always sync GCPtrPage */
1712	\|\| !CSAMDoesPageNeedScanning(pVM, (RTRCPTR)GCPtrCurPage)
1713	\|\| ( (pPage = pgmPhysGetPage(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK))
1714	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1715	)
1716	#endif /* else: CSAM not active */
1717	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1718	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
1719	GCPtrCurPage, PteSrc.n.u1Present,
1720	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1721	PteSrc.n.u1User & PdeSrc.n.u1User,
1722	(uint64_t)PteSrc.u,
1723	(uint64_t)pPTDst->a[iPTDst].u,
1724	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1725	}
1726	}
1727	}
1728	else
1729	# endif /* PGM_SYNC_N_PAGES */
1730	{
1731	const unsigned iPTSrc = (GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK;
1732	GSTPTE PteSrc = pPTSrc->a[iPTSrc];
1733	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1734	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1735	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s\n",
1736	GCPtrPage, PteSrc.n.u1Present,
1737	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1738	PteSrc.n.u1User & PdeSrc.n.u1User,
1739	(uint64_t)PteSrc.u,
1740	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1741	}
1742	}
1743	else /* MMIO or invalid page: emulated in #PF handler. */
1744	{
1745	LogFlow(("PGM_GCPHYS_2_PTR %RGp failed with %Rrc\n", GCPhys, rc));
1746	Assert(!pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK].n.u1Present);
1747	}
1748	}
1749	else
1750	{
1751	/*
1752	* 4/2MB page - lazy syncing shadow 4K pages.
1753	* (There are many causes of getting here, it's no longer only CSAM.)
1754	*/
1755	/* Calculate the GC physical address of this 4KB shadow page. */
1756	RTGCPHYS GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc) \| (GCPtrPage & GST_BIG_PAGE_OFFSET_MASK);
1757	/* Find ram range. */
1758	PPGMPAGE pPage;
1759	int rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
1760	if (RT_SUCCESS(rc))
1761	{
1762	/*
1763	* Make shadow PTE entry.
1764	*/
1765	const RTHCPHYS HCPhys = pPage->HCPhys; /** @todo PAGE FLAGS */
1766	SHWPTE PteDst;
1767	PteDst.u = (PdeSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT))
1768	\| (HCPhys & X86_PTE_PAE_PG_MASK);
1769	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1770	{
1771	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1772	PteDst.n.u1Write = 0;
1773	else
1774	PteDst.u = 0;
1775	}
1776	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1777	# ifdef PGMPOOL_WITH_USER_TRACKING
1778	if (PteDst.n.u1Present && !pPTDst->a[iPTDst].n.u1Present)
1779	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst);
1780	# endif
1781	pPTDst->a[iPTDst] = PteDst;
1782
1783
1784	/*
1785	* If the page is not flagged as dirty and is writable, then make it read-only
1786	* at PD level, so we can set the dirty bit when the page is modified.
1787	*
1788	* ASSUMES that page access handlers are implemented on page table entry level.
1789	* Thus we will first catch the dirty access and set PDE.D and restart. If
1790	* there is an access handler, we'll trap again and let it work on the problem.
1791	*/
1792	/** @todo r=bird: figure out why we need this here, SyncPT should've taken care of this already.
1793	* As for invlpg, it simply frees the whole shadow PT.
1794	* ...It's possibly because the guest clears it and the guest doesn't really tell us... */
1795	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
1796	{
1797	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyPageBig));
1798	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
1799	PdeDst.n.u1Write = 0;
1800	}
1801	else
1802	{
1803	PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
1804	PdeDst.n.u1Write = PdeSrc.n.u1Write;
1805	}
1806	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1807	pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst] = PdeDst;
1808	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1809	*pPdeDst = PdeDst;
1810	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1811	pPDDst->a[iPDDst] = PdeDst;
1812	# endif
1813	Log2(("SyncPage: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} GCPhys=%RGp%s\n",
1814	GCPtrPage, PdeSrc.n.u1Present, PdeSrc.n.u1Write, PdeSrc.n.u1User, (uint64_t)PdeSrc.u, GCPhys,
1815	PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1816	}
1817	else
1818	LogFlow(("PGM_GCPHYS_2_PTR %RGp (big) failed with %Rrc\n", GCPhys, rc));
1819	}
1820	return VINF_SUCCESS;
1821	}
1822	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPagePDNAs));
1823	}
1824	else
1825	{
1826	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPagePDOutOfSync));
1827	Log2(("SyncPage: Out-Of-Sync PDE at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
1828	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1829	}
1830
1831	/*
1832	* Mark the PDE not present. Restart the instruction and let #PF call SyncPT.
1833	* Yea, I'm lazy.
1834	*/
1835	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1836	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1837	pgmPoolFreeByPage(pPool, pShwPage, pShwPde->idx, iPDDst);
1838	# else
1839	pgmPoolFreeByPage(pPool, pShwPage, SHW_POOL_ROOT_IDX, iPDDst);
1840	# endif
1841
1842	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1843	pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst].u = 0;
1844	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1845	pPdeDst->u = 0;
1846	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1847	pPDDst->a[iPDDst].u = 0;
1848	# endif
1849	PGM_INVL_GUEST_TLBS();
1850	return VINF_PGM_SYNCPAGE_MODIFIED_PDE;
1851
1852	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
1853	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
1854	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT)
1855
1856	# ifdef PGM_SYNC_N_PAGES
1857	/*
1858	* Get the shadow PDE, find the shadow page table in the pool.
1859	*/
1860	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1861	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
1862	X86PDE PdeDst = pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst];
1863	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1864	X86PDEPAE PdeDst = pgmShwGetPaePDE(&pVM->pgm.s, GCPtrPage);
1865
1866	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1867	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
1868	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64; NOREF(iPdpt);
1869	PX86PDPAE pPDDst;
1870	X86PDEPAE PdeDst;
1871	PX86PDPT pPdptDst;
1872
1873	int rc = pgmShwGetLongModePDPtr(pVM, GCPtrPage, NULL, &pPdptDst, &pPDDst);
1874	AssertRCSuccessReturn(rc, rc);
1875	Assert(pPDDst && pPdptDst);
1876	PdeDst = pPDDst->a[iPDDst];
1877	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
1878	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
1879	PEPTPD pPDDst;
1880	EPTPDE PdeDst;
1881
1882	int rc = pgmShwGetEPTPDPtr(pVM, GCPtrPage, NULL, &pPDDst);
1883	if (rc != VINF_SUCCESS)
1884	{
1885	AssertRC(rc);
1886	return rc;
1887	}
1888	Assert(pPDDst);
1889	PdeDst = pPDDst->a[iPDDst];
1890	# endif
1891	Assert(PdeDst.n.u1Present);
1892	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1893	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1894
1895	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
1896	if (cPages > 1 && !(uErr & X86_TRAP_PF_P))
1897	{
1898	/*
1899	* This code path is currently only taken when the caller is PGMTrap0eHandler
1900	* for non-present pages!
1901	*
1902	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
1903	* deal with locality.
1904	*/
1905	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1906	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
1907	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
1908	iPTDst = 0;
1909	else
1910	iPTDst -= PGM_SYNC_NR_PAGES / 2;
1911	for (; iPTDst < iPTDstEnd; iPTDst++)
1912	{
1913	if (!pPTDst->a[iPTDst].n.u1Present)
1914	{
1915	GSTPTE PteSrc;
1916
1917	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT);
1918
1919	/* Fake the page table entry */
1920	PteSrc.u = GCPtrCurPage;
1921	PteSrc.n.u1Present = 1;
1922	PteSrc.n.u1Dirty = 1;
1923	PteSrc.n.u1Accessed = 1;
1924	PteSrc.n.u1Write = 1;
1925	PteSrc.n.u1User = 1;
1926
1927	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1928
1929	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
1930	GCPtrCurPage, PteSrc.n.u1Present,
1931	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1932	PteSrc.n.u1User & PdeSrc.n.u1User,
1933	(uint64_t)PteSrc.u,
1934	(uint64_t)pPTDst->a[iPTDst].u,
1935	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1936	}
1937	else
1938	Log4(("%RGv iPTDst=%x pPTDst->a[iPTDst] %RX64\n", (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT), iPTDst, pPTDst->a[iPTDst].u));
1939	}
1940	}
1941	else
1942	# endif /* PGM_SYNC_N_PAGES */
1943	{
1944	GSTPTE PteSrc;
1945	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1946	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT);
1947
1948	/* Fake the page table entry */
1949	PteSrc.u = GCPtrCurPage;
1950	PteSrc.n.u1Present = 1;
1951	PteSrc.n.u1Dirty = 1;
1952	PteSrc.n.u1Accessed = 1;
1953	PteSrc.n.u1Write = 1;
1954	PteSrc.n.u1User = 1;
1955	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1956
1957	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}PteDst=%08llx%s\n",
1958	GCPtrPage, PteSrc.n.u1Present,
1959	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1960	PteSrc.n.u1User & PdeSrc.n.u1User,
1961	(uint64_t)PteSrc.u,
1962	(uint64_t)pPTDst->a[iPTDst].u,
1963	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1964	}
1965	return VINF_SUCCESS;
1966
1967	#else
1968	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
1969	return VERR_INTERNAL_ERROR;
1970	#endif
1971	}
1972
1973
1974	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1975	/**
1976	* Investigate page fault and handle write protection page faults caused by
1977	* dirty bit tracking.
1978	*
1979	* @returns VBox status code.
1980	* @param pVM VM handle.
1981	* @param uErr Page fault error code.
1982	* @param pPdeDst Shadow page directory entry.
1983	* @param pPdeSrc Guest page directory entry.
1984	* @param GCPtrPage Guest context page address.
1985	*/
1986	PGM_BTH_DECL(int, CheckPageFault)(PVM pVM, uint32_t uErr, PSHWPDE pPdeDst, PGSTPDE pPdeSrc, RTGCPTR GCPtrPage)
1987	{
1988	bool fWriteProtect = !!(CPUMGetGuestCR0(pVM) & X86_CR0_WP);
1989	bool fUserLevelFault = !!(uErr & X86_TRAP_PF_US);
1990	bool fWriteFault = !!(uErr & X86_TRAP_PF_RW);
1991	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1992	bool fBigPagesSupported = true;
1993	# else
1994	bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
1995	# endif
1996	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
1997	bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
1998	# endif
1999	unsigned uPageFaultLevel;
2000	int rc;
2001
2002	STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2003	LogFlow(("CheckPageFault: GCPtrPage=%RGv uErr=%#x PdeSrc=%08x\n", GCPtrPage, uErr, pPdeSrc->u));
2004
2005	# if PGM_GST_TYPE == PGM_TYPE_PAE \
2006	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
2007
2008	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2009	PX86PML4E pPml4eSrc;
2010	PX86PDPE pPdpeSrc;
2011
2012	pPdpeSrc = pgmGstGetLongModePDPTPtr(&pVM->pgm.s, GCPtrPage, &pPml4eSrc);
2013	Assert(pPml4eSrc);
2014
2015	/*
2016	* Real page fault? (PML4E level)
2017	*/
2018	if ( (uErr & X86_TRAP_PF_RSVD)
2019	\|\| !pPml4eSrc->n.u1Present
2020	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPml4eSrc->n.u1NoExecute)
2021	\|\| (fWriteFault && !pPml4eSrc->n.u1Write && (fUserLevelFault \|\| fWriteProtect))
2022	\|\| (fUserLevelFault && !pPml4eSrc->n.u1User)
2023	)
2024	{
2025	uPageFaultLevel = 0;
2026	goto l_UpperLevelPageFault;
2027	}
2028	Assert(pPdpeSrc);
2029
2030	# else /* PAE */
2031	PX86PDPE pPdpeSrc = pgmGstGetPaePDPEPtr(&pVM->pgm.s, GCPtrPage);
2032	# endif /* PAE */
2033
2034	/*
2035	* Real page fault? (PDPE level)
2036	*/
2037	if ( (uErr & X86_TRAP_PF_RSVD)
2038	\|\| !pPdpeSrc->n.u1Present
2039	# if PGM_GST_TYPE == PGM_TYPE_AMD64 /* NX, r/w, u/s bits in the PDPE are long mode only */
2040	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPdpeSrc->lm.u1NoExecute)
2041	\|\| (fWriteFault && !pPdpeSrc->lm.u1Write && (fUserLevelFault \|\| fWriteProtect))
2042	\|\| (fUserLevelFault && !pPdpeSrc->lm.u1User)
2043	# endif
2044	)
2045	{
2046	uPageFaultLevel = 1;
2047	goto l_UpperLevelPageFault;
2048	}
2049	# endif
2050
2051	/*
2052	* Real page fault? (PDE level)
2053	*/
2054	if ( (uErr & X86_TRAP_PF_RSVD)
2055	\|\| !pPdeSrc->n.u1Present
2056	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2057	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPdeSrc->n.u1NoExecute)
2058	# endif
2059	\|\| (fWriteFault && !pPdeSrc->n.u1Write && (fUserLevelFault \|\| fWriteProtect))
2060	\|\| (fUserLevelFault && !pPdeSrc->n.u1User) )
2061	{
2062	uPageFaultLevel = 2;
2063	goto l_UpperLevelPageFault;
2064	}
2065
2066	/*
2067	* First check the easy case where the page directory has been marked read-only to track
2068	* the dirty bit of an emulated BIG page
2069	*/
2070	if (pPdeSrc->b.u1Size && fBigPagesSupported)
2071	{
2072	/* Mark guest page directory as accessed */
2073	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2074	pPml4eSrc->n.u1Accessed = 1;
2075	pPdpeSrc->lm.u1Accessed = 1;
2076	# endif
2077	pPdeSrc->b.u1Accessed = 1;
2078
2079	/*
2080	* Only write protection page faults are relevant here.
2081	*/
2082	if (fWriteFault)
2083	{
2084	/* Mark guest page directory as dirty (BIG page only). */
2085	pPdeSrc->b.u1Dirty = 1;
2086
2087	if (pPdeDst->n.u1Present && (pPdeDst->u & PGM_PDFLAGS_TRACK_DIRTY))
2088	{
2089	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyPageTrap));
2090
2091	Assert(pPdeSrc->b.u1Write);
2092
2093	pPdeDst->n.u1Write = 1;
2094	pPdeDst->n.u1Accessed = 1;
2095	pPdeDst->au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
2096	PGM_INVL_BIG_PG(GCPtrPage);
2097	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2098	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT;
2099	}
2100	}
2101	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2102	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2103	}
2104	/* else: 4KB page table */
2105
2106	/*
2107	* Map the guest page table.
2108	*/
2109	PGSTPT pPTSrc;
2110	rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & GST_PDE_PG_MASK, &pPTSrc);
2111	if (RT_SUCCESS(rc))
2112	{
2113	/*
2114	* Real page fault?
2115	*/
2116	PGSTPTE pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
2117	const GSTPTE PteSrc = *pPteSrc;
2118	if ( !PteSrc.n.u1Present
2119	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2120	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && PteSrc.n.u1NoExecute)
2121	# endif
2122	\|\| (fWriteFault && !PteSrc.n.u1Write && (fUserLevelFault \|\| fWriteProtect))
2123	\|\| (fUserLevelFault && !PteSrc.n.u1User)
2124	)
2125	{
2126	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyTrackRealPF));
2127	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2128	LogFlow(("CheckPageFault: real page fault at %RGv PteSrc.u=%08x (2)\n", GCPtrPage, PteSrc.u));
2129
2130	/* Check the present bit as the shadow tables can cause different error codes by being out of sync.
2131	* See the 2nd case above as well.
2132	*/
2133	if (pPdeSrc->n.u1Present && pPteSrc->n.u1Present)
2134	TRPMSetErrorCode(pVM, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
2135
2136	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2137	return VINF_EM_RAW_GUEST_TRAP;
2138	}
2139	LogFlow(("CheckPageFault: page fault at %RGv PteSrc.u=%08x\n", GCPtrPage, PteSrc.u));
2140
2141	/*
2142	* Set the accessed bits in the page directory and the page table.
2143	*/
2144	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2145	pPml4eSrc->n.u1Accessed = 1;
2146	pPdpeSrc->lm.u1Accessed = 1;
2147	# endif
2148	pPdeSrc->n.u1Accessed = 1;
2149	pPteSrc->n.u1Accessed = 1;
2150
2151	/*
2152	* Only write protection page faults are relevant here.
2153	*/
2154	if (fWriteFault)
2155	{
2156	/* Write access, so mark guest entry as dirty. */
2157	# ifdef VBOX_WITH_STATISTICS
2158	if (!pPteSrc->n.u1Dirty)
2159	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtiedPage));
2160	else
2161	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,PageAlreadyDirty));
2162	# endif
2163
2164	pPteSrc->n.u1Dirty = 1;
2165
2166	if (pPdeDst->n.u1Present)
2167	{
2168	#ifndef IN_RING0
2169	/* Bail out here as pgmPoolGetPageByHCPhys will return NULL and we'll crash below.
2170	* Our individual shadow handlers will provide more information and force a fatal exit.
2171	*/
2172	if (MMHyperIsInsideArea(pVM, (RTGCPTR)GCPtrPage))
2173	{
2174	LogRel(("CheckPageFault: write to hypervisor region %RGv\n", GCPtrPage));
2175	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2176	return VINF_SUCCESS;
2177	}
2178	#endif
2179	/*
2180	* Map shadow page table.
2181	*/
2182	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, pPdeDst->u & SHW_PDE_PG_MASK);
2183	if (pShwPage)
2184	{
2185	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2186	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2187	if ( pPteDst->n.u1Present /** @todo Optimize accessed bit emulation? */
2188	&& (pPteDst->u & PGM_PTFLAGS_TRACK_DIRTY))
2189	{
2190	LogFlow(("DIRTY page trap addr=%RGv\n", GCPtrPage));
2191	# ifdef VBOX_STRICT
2192	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, pPteSrc->u & GST_PTE_PG_MASK);
2193	if (pPage)
2194	AssertMsg(!PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage),
2195	("Unexpected dirty bit tracking on monitored page %RGv (phys %RGp)!!!!!!\n", GCPtrPage, pPteSrc->u & X86_PTE_PAE_PG_MASK));
2196	# endif
2197	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyPageTrap));
2198
2199	Assert(pPteSrc->n.u1Write);
2200
2201	pPteDst->n.u1Write = 1;
2202	pPteDst->n.u1Dirty = 1;
2203	pPteDst->n.u1Accessed = 1;
2204	pPteDst->au32[0] &= ~PGM_PTFLAGS_TRACK_DIRTY;
2205	PGM_INVL_PG(GCPtrPage);
2206
2207	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2208	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT;
2209	}
2210	}
2211	else
2212	AssertMsgFailed(("pgmPoolGetPageByHCPhys %RGp failed!\n", pPdeDst->u & SHW_PDE_PG_MASK));
2213	}
2214	}
2215	/** @todo Optimize accessed bit emulation? */
2216	# ifdef VBOX_STRICT
2217	/*
2218	* Sanity check.
2219	*/
2220	else if ( !pPteSrc->n.u1Dirty
2221	&& (pPdeSrc->n.u1Write & pPteSrc->n.u1Write)
2222	&& pPdeDst->n.u1Present)
2223	{
2224	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, pPdeDst->u & SHW_PDE_PG_MASK);
2225	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2226	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2227	if ( pPteDst->n.u1Present
2228	&& pPteDst->n.u1Write)
2229	LogFlow(("Writable present page %RGv not marked for dirty bit tracking!!!\n", GCPtrPage));
2230	}
2231	# endif /* VBOX_STRICT */
2232	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2233	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2234	}
2235	AssertRC(rc);
2236	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2237	return rc;
2238
2239
2240	l_UpperLevelPageFault:
2241	/*
2242	* Pagefault detected while checking the PML4E, PDPE or PDE.
2243	* Single exit handler to get rid of duplicate code paths.
2244	*/
2245	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyTrackRealPF));
2246	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2247	Log(("CheckPageFault: real page fault at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2248
2249	if (
2250	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2251	pPml4eSrc->n.u1Present &&
2252	# endif
2253	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
2254	pPdpeSrc->n.u1Present &&
2255	# endif
2256	pPdeSrc->n.u1Present)
2257	{
2258	/* Check the present bit as the shadow tables can cause different error codes by being out of sync. */
2259	if (pPdeSrc->b.u1Size && fBigPagesSupported)
2260	{
2261	TRPMSetErrorCode(pVM, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
2262	}
2263	else
2264	{
2265	/*
2266	* Map the guest page table.
2267	*/
2268	PGSTPT pPTSrc;
2269	rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & GST_PDE_PG_MASK, &pPTSrc);
2270	if (RT_SUCCESS(rc))
2271	{
2272	PGSTPTE pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
2273	const GSTPTE PteSrc = *pPteSrc;
2274	if (pPteSrc->n.u1Present)
2275	TRPMSetErrorCode(pVM, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
2276	}
2277	AssertRC(rc);
2278	}
2279	}
2280	return VINF_EM_RAW_GUEST_TRAP;
2281	}
2282	#endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
2283
2284
2285	/**
2286	* Sync a shadow page table.
2287	*
2288	* The shadow page table is not present. This includes the case where
2289	* there is a conflict with a mapping.
2290	*
2291	* @returns VBox status code.
2292	* @param pVM VM handle.
2293	* @param iPD Page directory index.
2294	* @param pPDSrc Source page directory (i.e. Guest OS page directory).
2295	* Assume this is a temporary mapping.
2296	* @param GCPtrPage GC Pointer of the page that caused the fault
2297	*/
2298	PGM_BTH_DECL(int, SyncPT)(PVM pVM, unsigned iPDSrc, PGSTPD pPDSrc, RTGCPTR GCPtrPage)
2299	{
2300	STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2301	STAM_COUNTER_INC(&pVM->pgm.s.StatSyncPtPD[iPDSrc]);
2302	LogFlow(("SyncPT: GCPtrPage=%RGv\n", GCPtrPage));
2303
2304	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
2305	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
2306	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
2307	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2308	&& PGM_SHW_TYPE != PGM_TYPE_EPT
2309
2310	int rc = VINF_SUCCESS;
2311
2312	/*
2313	* Validate input a little bit.
2314	*/
2315	AssertMsg(iPDSrc == ((GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK), ("iPDSrc=%x GCPtrPage=%RGv\n", iPDSrc, GCPtrPage));
2316	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2317	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
2318	PX86PD pPDDst = pVM->pgm.s.CTXMID(p,32BitPD);
2319	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2320
2321	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2322	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) /& SHW_PD_MASK - only pool index atm! /;
2323	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT); NOREF(iPdpt);
2324	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(&pVM->pgm.s); NOREF(pPdptDst);
2325	PSHWPDE pPdeDst = pgmShwGetPaePDEPtr(&pVM->pgm.s, GCPtrPage);
2326
2327	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2328	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
2329	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2330	PX86PDPAE pPDDst;
2331	PX86PDPT pPdptDst;
2332	rc = pgmShwGetLongModePDPtr(pVM, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2333	AssertRCSuccessReturn(rc, rc);
2334	Assert(pPDDst);
2335	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2336	# endif
2337	SHWPDE PdeDst = *pPdeDst;
2338
2339	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2340	/* Fetch the pgm pool shadow descriptor. */
2341	PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(pVM, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
2342	Assert(pShwPde);
2343	# endif
2344
2345	# ifndef PGM_WITHOUT_MAPPINGS
2346	/*
2347	* Check for conflicts.
2348	* GC: In case of a conflict we'll go to Ring-3 and do a full SyncCR3.
2349	* HC: Simply resolve the conflict.
2350	*/
2351	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
2352	{
2353	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
2354	# ifndef IN_RING3
2355	Log(("SyncPT: Conflict at %RGv\n", GCPtrPage));
2356	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2357	return VERR_ADDRESS_CONFLICT;
2358	# else
2359	PPGMMAPPING pMapping = pgmGetMapping(pVM, (RTGCPTR)GCPtrPage);
2360	Assert(pMapping);
2361	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2362	int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2363	# elif PGM_GST_TYPE == PGM_TYPE_PAE
2364	int rc = pgmR3SyncPTResolveConflictPAE(pVM, pMapping, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2365	# else
2366	AssertFailed(); /* can't happen for amd64 */
2367	# endif
2368	if (RT_FAILURE(rc))
2369	{
2370	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2371	return rc;
2372	}
2373	PdeDst = *pPdeDst;
2374	# endif
2375	}
2376	# else /* PGM_WITHOUT_MAPPINGS */
2377	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
2378	# endif /* PGM_WITHOUT_MAPPINGS */
2379	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
2380
2381	/*
2382	* Sync page directory entry.
2383	*/
2384	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
2385	if (PdeSrc.n.u1Present)
2386	{
2387	/*
2388	* Allocate & map the page table.
2389	*/
2390	PSHWPT pPTDst;
2391	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2392	const bool fPageTable = !PdeSrc.b.u1Size;
2393	# else
2394	const bool fPageTable = !PdeSrc.b.u1Size \|\| !(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
2395	# endif
2396	PPGMPOOLPAGE pShwPage;
2397	RTGCPHYS GCPhys;
2398	if (fPageTable)
2399	{
2400	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
2401	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2402	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2403	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE / 2);
2404	# endif
2405	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2406	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, pShwPde->idx, iPDDst, &pShwPage);
2407	# else
2408	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, SHW_POOL_ROOT_IDX, iPDDst, &pShwPage);
2409	# endif
2410	}
2411	else
2412	{
2413	GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
2414	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2415	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
2416	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
2417	# endif
2418	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2419	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_BIG, pShwPde->idx, iPDDst, &pShwPage);
2420	# else
2421	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_BIG, SHW_POOL_ROOT_IDX, iPDDst, &pShwPage);
2422	# endif
2423	}
2424	if (rc == VINF_SUCCESS)
2425	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2426	else if (rc == VINF_PGM_CACHED_PAGE)
2427	{
2428	/*
2429	* The PT was cached, just hook it up.
2430	*/
2431	if (fPageTable)
2432	PdeDst.u = pShwPage->Core.Key
2433	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2434	else
2435	{
2436	PdeDst.u = pShwPage->Core.Key
2437	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2438	/* (see explanation and assumptions further down.) */
2439	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
2440	{
2441	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyPageBig));
2442	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2443	PdeDst.b.u1Write = 0;
2444	}
2445	}
2446	*pPdeDst = PdeDst;
2447	return VINF_SUCCESS;
2448	}
2449	else if (rc == VERR_PGM_POOL_FLUSHED)
2450	{
2451	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
2452	return VINF_PGM_SYNC_CR3;
2453	}
2454	else
2455	AssertMsgFailedReturn(("rc=%Rrc\n", rc), VERR_INTERNAL_ERROR);
2456	PdeDst.u &= X86_PDE_AVL_MASK;
2457	PdeDst.u \|= pShwPage->Core.Key;
2458
2459	/*
2460	* Page directory has been accessed (this is a fault situation, remember).
2461	*/
2462	pPDSrc->a[iPDSrc].n.u1Accessed = 1;
2463	if (fPageTable)
2464	{
2465	/*
2466	* Page table - 4KB.
2467	*
2468	* Sync all or just a few entries depending on PGM_SYNC_N_PAGES.
2469	*/
2470	Log2(("SyncPT: 4K %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx}\n",
2471	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u));
2472	PGSTPT pPTSrc;
2473	rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
2474	if (RT_SUCCESS(rc))
2475	{
2476	/*
2477	* Start by syncing the page directory entry so CSAM's TLB trick works.
2478	*/
2479	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| X86_PDE_AVL_MASK))
2480	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2481	*pPdeDst = PdeDst;
2482
2483	/*
2484	* Directory/page user or supervisor privilege: (same goes for read/write)
2485	*
2486	* Directory Page Combined
2487	* U/S U/S U/S
2488	* 0 0 0
2489	* 0 1 0
2490	* 1 0 0
2491	* 1 1 1
2492	*
2493	* Simple AND operation. Table listed for completeness.
2494	*
2495	*/
2496	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPT4K));
2497	# ifdef PGM_SYNC_N_PAGES
2498	unsigned iPTBase = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2499	unsigned iPTDst = iPTBase;
2500	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2501	if (iPTDst <= PGM_SYNC_NR_PAGES / 2)
2502	iPTDst = 0;
2503	else
2504	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2505	# else /* !PGM_SYNC_N_PAGES */
2506	unsigned iPTDst = 0;
2507	const unsigned iPTDstEnd = RT_ELEMENTS(pPTDst->a);
2508	# endif /* !PGM_SYNC_N_PAGES */
2509	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2510	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2511	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
2512	# else
2513	const unsigned offPTSrc = 0;
2514	# endif
2515	for (; iPTDst < iPTDstEnd; iPTDst++)
2516	{
2517	const unsigned iPTSrc = iPTDst + offPTSrc;
2518	const GSTPTE PteSrc = pPTSrc->a[iPTSrc];
2519
2520	if (PteSrc.n.u1Present) /* we've already cleared it above */
2521	{
2522	# ifndef IN_RING0
2523	/*
2524	* Assuming kernel code will be marked as supervisor - and not as user level
2525	* and executed using a conforming code selector - And marked as readonly.
2526	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
2527	*/
2528	PPGMPAGE pPage;
2529	if ( ((PdeSrc.u & pPTSrc->a[iPTSrc].u) & (X86_PTE_RW \| X86_PTE_US))
2530	\|\| !CSAMDoesPageNeedScanning(pVM, (RTRCPTR)((iPDSrc << GST_PD_SHIFT) \| (iPTSrc << PAGE_SHIFT)))
2531	\|\| ( (pPage = pgmPhysGetPage(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK))
2532	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2533	)
2534	# endif
2535	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2536	Log2(("SyncPT: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s dst.raw=%08llx iPTSrc=%x PdeSrc.u=%x physpte=%RGp\n",
2537	(RTGCPTR)((iPDSrc << GST_PD_SHIFT) \| (iPTSrc << PAGE_SHIFT)),
2538	PteSrc.n.u1Present,
2539	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2540	PteSrc.n.u1User & PdeSrc.n.u1User,
2541	(uint64_t)PteSrc.u,
2542	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : "", pPTDst->a[iPTDst].u, iPTSrc, PdeSrc.au32[0],
2543	(RTGCPHYS)((PdeSrc.u & GST_PDE_PG_MASK) + iPTSrc*sizeof(PteSrc)) ));
2544	}
2545	} /* for PTEs */
2546	}
2547	}
2548	else
2549	{
2550	/*
2551	* Big page - 2/4MB.
2552	*
2553	* We'll walk the ram range list in parallel and optimize lookups.
2554	* We will only sync on shadow page table at a time.
2555	*/
2556	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPT4M));
2557
2558	/**
2559	* @todo It might be more efficient to sync only a part of the 4MB page (similar to what we do for 4kb PDs).
2560	*/
2561
2562	/*
2563	* Start by syncing the page directory entry.
2564	*/
2565	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| (X86_PDE_AVL_MASK & ~PGM_PDFLAGS_TRACK_DIRTY)))
2566	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2567
2568	/*
2569	* If the page is not flagged as dirty and is writable, then make it read-only
2570	* at PD level, so we can set the dirty bit when the page is modified.
2571	*
2572	* ASSUMES that page access handlers are implemented on page table entry level.
2573	* Thus we will first catch the dirty access and set PDE.D and restart. If
2574	* there is an access handler, we'll trap again and let it work on the problem.
2575	*/
2576	/** @todo move the above stuff to a section in the PGM documentation. */
2577	Assert(!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY));
2578	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
2579	{
2580	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyPageBig));
2581	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2582	PdeDst.b.u1Write = 0;
2583	}
2584	*pPdeDst = PdeDst;
2585
2586	/*
2587	* Fill the shadow page table.
2588	*/
2589	/* Get address and flags from the source PDE. */
2590	SHWPTE PteDstBase;
2591	PteDstBase.u = PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT);
2592
2593	/* Loop thru the entries in the shadow PT. */
2594	const RTGCPTR GCPtr = (GCPtrPage >> SHW_PD_SHIFT) << SHW_PD_SHIFT; NOREF(GCPtr);
2595	Log2(("SyncPT: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} Shw=%RGv GCPhys=%RGp %s\n",
2596	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u, GCPtr,
2597	GCPhys, PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2598	PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
2599	unsigned iPTDst = 0;
2600	while (iPTDst < RT_ELEMENTS(pPTDst->a))
2601	{
2602	/* Advance ram range list. */
2603	while (pRam && GCPhys > pRam->GCPhysLast)
2604	pRam = pRam->CTX_SUFF(pNext);
2605	if (pRam && GCPhys >= pRam->GCPhys)
2606	{
2607	unsigned iHCPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
2608	do
2609	{
2610	/* Make shadow PTE. */
2611	PPGMPAGE pPage = &pRam->aPages[iHCPage];
2612	SHWPTE PteDst;
2613
2614	/* Make sure the RAM has already been allocated. */
2615	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC) /** @todo PAGE FLAGS */
2616	{
2617	if (RT_UNLIKELY(!PGM_PAGE_GET_HCPHYS(pPage)))
2618	{
2619	# ifdef IN_RING3
2620	int rc = pgmr3PhysGrowRange(pVM, GCPhys);
2621	# else
2622	int rc = CTXALLMID(VMM, CallHost)(pVM, VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
2623	# endif
2624	if (rc != VINF_SUCCESS)
2625	return rc;
2626	}
2627	}
2628
2629	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2630	{
2631	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
2632	{
2633	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage) \| PteDstBase.u;
2634	PteDst.n.u1Write = 0;
2635	}
2636	else
2637	PteDst.u = 0;
2638	}
2639	# ifndef IN_RING0
2640	/*
2641	* Assuming kernel code will be marked as supervisor and not as user level and executed
2642	* using a conforming code selector. Don't check for readonly, as that implies the whole
2643	* 4MB can be code or readonly data. Linux enables write access for its large pages.
2644	*/
2645	else if ( !PdeSrc.n.u1User
2646	&& CSAMDoesPageNeedScanning(pVM, (RTRCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT))))
2647	PteDst.u = 0;
2648	# endif
2649	else
2650	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage) \| PteDstBase.u;
2651	# ifdef PGMPOOL_WITH_USER_TRACKING
2652	if (PteDst.n.u1Present)
2653	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, pPage->HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst); /** @todo PAGE FLAGS */
2654	# endif
2655	/* commit it */
2656	pPTDst->a[iPTDst] = PteDst;
2657	Log4(("SyncPT: BIG %RGv PteDst:{P=%d RW=%d U=%d raw=%08llx}%s\n",
2658	(RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT)), PteDst.n.u1Present, PteDst.n.u1Write, PteDst.n.u1User, (uint64_t)PteDst.u,
2659	PteDst.u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2660
2661	/* advance */
2662	GCPhys += PAGE_SIZE;
2663	iHCPage++;
2664	iPTDst++;
2665	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2666	&& GCPhys <= pRam->GCPhysLast);
2667	}
2668	else if (pRam)
2669	{
2670	Log(("Invalid pages at %RGp\n", GCPhys));
2671	do
2672	{
2673	pPTDst->a[iPTDst].u = 0; /* MMIO or invalid page, we must handle them manually. */
2674	GCPhys += PAGE_SIZE;
2675	iPTDst++;
2676	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2677	&& GCPhys < pRam->GCPhys);
2678	}
2679	else
2680	{
2681	Log(("Invalid pages at %RGp (2)\n", GCPhys));
2682	for ( ; iPTDst < RT_ELEMENTS(pPTDst->a); iPTDst++)
2683	pPTDst->a[iPTDst].u = 0; /* MMIO or invalid page, we must handle them manually. */
2684	}
2685	} /* while more PTEs */
2686	} /* 4KB / 4MB */
2687	}
2688	else
2689	AssertRelease(!PdeDst.n.u1Present);
2690
2691	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2692	if (RT_FAILURE(rc))
2693	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPTFailed));
2694	return rc;
2695
2696	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2697	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2698	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT)
2699
2700
2701	/*
2702	* Validate input a little bit.
2703	*/
2704	int rc = VINF_SUCCESS;
2705	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2706	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
2707	PX86PD pPDDst = pVM->pgm.s.CTXMID(p,32BitPD);
2708	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2709
2710	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2711	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) /& SHW_PD_MASK - only pool index atm!/;
2712	PX86PDEPAE pPdeDst = pgmShwGetPaePDEPtr(&pVM->pgm.s, GCPtrPage);
2713
2714	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2715	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
2716	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2717	PX86PDPAE pPDDst;
2718	PX86PDPT pPdptDst;
2719	rc = pgmShwGetLongModePDPtr(pVM, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2720	AssertRCSuccessReturn(rc, rc);
2721	Assert(pPDDst);
2722	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2723
2724	/* Fetch the pgm pool shadow descriptor. */
2725	PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(pVM, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
2726	Assert(pShwPde);
2727
2728	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
2729	const unsigned iPdpt = (GCPtrPage >> EPT_PDPT_SHIFT) & EPT_PDPT_MASK;
2730	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2731	PEPTPD pPDDst;
2732	PEPTPDPT pPdptDst;
2733
2734	rc = pgmShwGetEPTPDPtr(pVM, GCPtrPage, &pPdptDst, &pPDDst);
2735	if (rc != VINF_SUCCESS)
2736	{
2737	AssertRC(rc);
2738	return rc;
2739	}
2740	Assert(pPDDst);
2741	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2742
2743	/* Fetch the pgm pool shadow descriptor. */
2744	PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(pVM, pPdptDst->a[iPdpt].u & EPT_PDPTE_PG_MASK);
2745	Assert(pShwPde);
2746	# endif
2747	SHWPDE PdeDst = *pPdeDst;
2748
2749	Assert(!(PdeDst.u & PGM_PDFLAGS_MAPPING));
2750	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
2751
2752	GSTPDE PdeSrc;
2753	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
2754	PdeSrc.n.u1Present = 1;
2755	PdeSrc.n.u1Write = 1;
2756	PdeSrc.n.u1Accessed = 1;
2757	PdeSrc.n.u1User = 1;
2758
2759	/*
2760	* Allocate & map the page table.
2761	*/
2762	PSHWPT pPTDst;
2763	PPGMPOOLPAGE pShwPage;
2764	RTGCPHYS GCPhys;
2765
2766	/* Virtual address = physical address */
2767	GCPhys = GCPtrPage & X86_PAGE_4K_BASE_MASK;
2768	# if PGM_SHW_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
2769	rc = pgmPoolAlloc(pVM, GCPhys & ~(RT_BIT_64(SHW_PD_SHIFT) - 1), BTH_PGMPOOLKIND_PT_FOR_PT, pShwPde->idx, iPDDst, &pShwPage);
2770	# else
2771	rc = pgmPoolAlloc(pVM, GCPhys & ~(RT_BIT_64(SHW_PD_SHIFT) - 1), BTH_PGMPOOLKIND_PT_FOR_PT, SHW_POOL_ROOT_IDX, iPDDst, &pShwPage);
2772	# endif
2773
2774	if ( rc == VINF_SUCCESS
2775	\|\| rc == VINF_PGM_CACHED_PAGE)
2776	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2777	else
2778	AssertMsgFailedReturn(("rc=%Rrc\n", rc), VERR_INTERNAL_ERROR);
2779
2780	PdeDst.u &= X86_PDE_AVL_MASK;
2781	PdeDst.u \|= pShwPage->Core.Key;
2782	PdeDst.n.u1Present = 1;
2783	PdeDst.n.u1Write = 1;
2784	# if PGM_SHW_TYPE == PGM_TYPE_EPT
2785	PdeDst.n.u1Execute = 1;
2786	# else
2787	PdeDst.n.u1User = 1;
2788	PdeDst.n.u1Accessed = 1;
2789	# endif
2790	*pPdeDst = PdeDst;
2791
2792	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, PGM_SYNC_NR_PAGES, 0 /* page not present */);
2793	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2794	return rc;
2795
2796	#else
2797	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_SHW_TYPE, PGM_GST_TYPE));
2798	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2799	return VERR_INTERNAL_ERROR;
2800	#endif
2801	}
2802
2803
2804
2805	/**
2806	* Prefetch a page/set of pages.
2807	*
2808	* Typically used to sync commonly used pages before entering raw mode
2809	* after a CR3 reload.
2810	*
2811	* @returns VBox status code.
2812	* @param pVM VM handle.
2813	* @param GCPtrPage Page to invalidate.
2814	*/
2815	PGM_BTH_DECL(int, PrefetchPage)(PVM pVM, RTGCPTR GCPtrPage)
2816	{
2817	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
2818	&& PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
2819	/*
2820	* Check that all Guest levels thru the PDE are present, getting the
2821	* PD and PDE in the processes.
2822	*/
2823	int rc = VINF_SUCCESS;
2824	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
2825	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2826	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
2827	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(&pVM->pgm.s);
2828	# elif PGM_GST_TYPE == PGM_TYPE_PAE
2829	unsigned iPDSrc;
2830	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtrPage, &iPDSrc, NULL);
2831	if (!pPDSrc)
2832	return VINF_SUCCESS; /* not present */
2833	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
2834	unsigned iPDSrc;
2835	PX86PML4E pPml4eSrc;
2836	X86PDPE PdpeSrc;
2837	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
2838	if (!pPDSrc)
2839	return VINF_SUCCESS; /* not present */
2840	# endif
2841	const GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
2842	# else
2843	PGSTPD pPDSrc = NULL;
2844	const unsigned iPDSrc = 0;
2845	GSTPDE PdeSrc;
2846
2847	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
2848	PdeSrc.n.u1Present = 1;
2849	PdeSrc.n.u1Write = 1;
2850	PdeSrc.n.u1Accessed = 1;
2851	PdeSrc.n.u1User = 1;
2852	# endif
2853
2854	if (PdeSrc.n.u1Present && PdeSrc.n.u1Accessed)
2855	{
2856	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2857	const X86PDE PdeDst = pVM->pgm.s.CTXMID(p,32BitPD)->a[GCPtrPage >> SHW_PD_SHIFT];
2858	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2859	const X86PDEPAE PdeDst = pgmShwGetPaePDE(&pVM->pgm.s, GCPtrPage);
2860	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2861	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2862	PX86PDPAE pPDDst;
2863	X86PDEPAE PdeDst;
2864
2865	# if PGM_GST_TYPE == PGM_TYPE_PROT
2866	/* AMD-V nested paging */
2867	X86PML4E Pml4eSrc;
2868	X86PDPE PdpeSrc;
2869	PX86PML4E pPml4eSrc = &Pml4eSrc;
2870
2871	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
2872	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_NX \| X86_PML4E_A;
2873	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_NX \| X86_PDPE_A;
2874	# endif
2875
2876	int rc = pgmShwSyncLongModePDPtr(pVM, GCPtrPage, pPml4eSrc, &PdpeSrc, &pPDDst);
2877	if (rc != VINF_SUCCESS)
2878	{
2879	AssertRC(rc);
2880	return rc;
2881	}
2882	Assert(pPDDst);
2883	PdeDst = pPDDst->a[iPDDst];
2884	# endif
2885	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
2886	{
2887	if (!PdeDst.n.u1Present)
2888	/** r=bird: This guy will set the A bit on the PDE, probably harmless. */
2889	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, GCPtrPage);
2890	else
2891	{
2892	/** @note We used to sync PGM_SYNC_NR_PAGES pages, which triggered assertions in CSAM, because
2893	* R/W attributes of nearby pages were reset. Not sure how that could happen. Anyway, it
2894	* makes no sense to prefetch more than one page.
2895	*/
2896	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, 1, 0);
2897	if (RT_SUCCESS(rc))
2898	rc = VINF_SUCCESS;
2899	}
2900	}
2901	}
2902	return rc;
2903
2904	#elif PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
2905	return VINF_SUCCESS; /* ignore */
2906	#endif
2907	}
2908
2909
2910
2911
2912	/**
2913	* Syncs a page during a PGMVerifyAccess() call.
2914	*
2915	* @returns VBox status code (informational included).
2916	* @param GCPtrPage The address of the page to sync.
2917	* @param fPage The effective guest page flags.
2918	* @param uErr The trap error code.
2919	*/
2920	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVM pVM, RTGCPTR GCPtrPage, unsigned fPage, unsigned uErr)
2921	{
2922	LogFlow(("VerifyAccessSyncPage: GCPtrPage=%RGv fPage=%#x uErr=%#x\n", GCPtrPage, fPage, uErr));
2923
2924	Assert(!HWACCMIsNestedPagingActive(pVM));
2925	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_TYPE_AMD64) \
2926	&& PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
2927
2928	# ifndef IN_RING0
2929	if (!(fPage & X86_PTE_US))
2930	{
2931	/*
2932	* Mark this page as safe.
2933	*/
2934	/** @todo not correct for pages that contain both code and data!! */
2935	Log(("CSAMMarkPage %RGv; scanned=%d\n", GCPtrPage, true));
2936	CSAMMarkPage(pVM, (RTRCPTR)GCPtrPage, true);
2937	}
2938	# endif
2939
2940	/*
2941	* Get guest PD and index.
2942	*/
2943	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
2944	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2945	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
2946	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(&pVM->pgm.s);
2947	# elif PGM_GST_TYPE == PGM_TYPE_PAE
2948	unsigned iPDSrc;
2949	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtrPage, &iPDSrc, NULL);
2950
2951	if (pPDSrc)
2952	{
2953	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
2954	return VINF_EM_RAW_GUEST_TRAP;
2955	}
2956	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
2957	unsigned iPDSrc;
2958	PX86PML4E pPml4eSrc;
2959	X86PDPE PdpeSrc;
2960	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
2961	if (!pPDSrc)
2962	{
2963	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
2964	return VINF_EM_RAW_GUEST_TRAP;
2965	}
2966	# endif
2967	# else
2968	PGSTPD pPDSrc = NULL;
2969	const unsigned iPDSrc = 0;
2970	# endif
2971	int rc = VINF_SUCCESS;
2972
2973	/*
2974	* First check if the shadow pd is present.
2975	*/
2976	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2977	PX86PDE pPdeDst = &pVM->pgm.s.CTXMID(p,32BitPD)->a[GCPtrPage >> SHW_PD_SHIFT];
2978	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2979	PX86PDEPAE pPdeDst = pgmShwGetPaePDEPtr(&pVM->pgm.s, GCPtrPage);
2980	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2981	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2982	PX86PDPAE pPDDst;
2983	PX86PDEPAE pPdeDst;
2984
2985	# if PGM_GST_TYPE == PGM_TYPE_PROT
2986	/* AMD-V nested paging */
2987	X86PML4E Pml4eSrc;
2988	X86PDPE PdpeSrc;
2989	PX86PML4E pPml4eSrc = &Pml4eSrc;
2990
2991	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
2992	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_NX \| X86_PML4E_A;
2993	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_NX \| X86_PDPE_A;
2994	# endif
2995
2996	rc = pgmShwSyncLongModePDPtr(pVM, GCPtrPage, pPml4eSrc, &PdpeSrc, &pPDDst);
2997	if (rc != VINF_SUCCESS)
2998	{
2999	AssertRC(rc);
3000	return rc;
3001	}
3002	Assert(pPDDst);
3003	pPdeDst = &pPDDst->a[iPDDst];
3004	# endif
3005	if (!pPdeDst->n.u1Present)
3006	{
3007	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, GCPtrPage);
3008	AssertRC(rc);
3009	if (rc != VINF_SUCCESS)
3010	return rc;
3011	}
3012
3013	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3014	/* Check for dirty bit fault */
3015	rc = PGM_BTH_NAME(CheckPageFault)(pVM, uErr, pPdeDst, &pPDSrc->a[iPDSrc], GCPtrPage);
3016	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
3017	Log(("PGMVerifyAccess: success (dirty)\n"));
3018	else
3019	{
3020	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
3021	#else
3022	{
3023	GSTPDE PdeSrc;
3024	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
3025	PdeSrc.n.u1Present = 1;
3026	PdeSrc.n.u1Write = 1;
3027	PdeSrc.n.u1Accessed = 1;
3028	PdeSrc.n.u1User = 1;
3029
3030	#endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
3031	Assert(rc != VINF_EM_RAW_GUEST_TRAP);
3032	if (uErr & X86_TRAP_PF_US)
3033	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncUser));
3034	else /* supervisor */
3035	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
3036
3037	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, 1, 0);
3038	if (RT_SUCCESS(rc))
3039	{
3040	/* Page was successfully synced */
3041	Log2(("PGMVerifyAccess: success (sync)\n"));
3042	rc = VINF_SUCCESS;
3043	}
3044	else
3045	{
3046	Log(("PGMVerifyAccess: access violation for %RGv rc=%d\n", GCPtrPage, rc));
3047	return VINF_EM_RAW_GUEST_TRAP;
3048	}
3049	}
3050	return rc;
3051
3052	#else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
3053
3054	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
3055	return VERR_INTERNAL_ERROR;
3056	#endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
3057	}
3058
3059
3060	#if PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
3061	# if PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
3062	/**
3063	* Figures out which kind of shadow page this guest PDE warrants.
3064	*
3065	* @returns Shadow page kind.
3066	* @param pPdeSrc The guest PDE in question.
3067	* @param cr4 The current guest cr4 value.
3068	*/
3069	DECLINLINE(PGMPOOLKIND) PGM_BTH_NAME(CalcPageKind)(const GSTPDE *pPdeSrc, uint32_t cr4)
3070	{
3071	# if PMG_GST_TYPE == PGM_TYPE_AMD64
3072	if (!pPdeSrc->n.u1Size)
3073	# else
3074	if (!pPdeSrc->n.u1Size \|\| !(cr4 & X86_CR4_PSE))
3075	# endif
3076	return BTH_PGMPOOLKIND_PT_FOR_PT;
3077	//switch (pPdeSrc->u & (X86_PDE4M_RW \| X86_PDE4M_US /\| X86_PDE4M_PAE_NX/))
3078	//{
3079	// case 0:
3080	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RO;
3081	// case X86_PDE4M_RW:
3082	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW;
3083	// case X86_PDE4M_US:
3084	// return BTH_PGMPOOLKIND_PT_FOR_BIG_US;
3085	// case X86_PDE4M_RW \| X86_PDE4M_US:
3086	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_US;
3087	# if 0
3088	// case X86_PDE4M_PAE_NX:
3089	// return BTH_PGMPOOLKIND_PT_FOR_BIG_NX;
3090	// case X86_PDE4M_RW \| X86_PDE4M_PAE_NX:
3091	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_NX;
3092	// case X86_PDE4M_US \| X86_PDE4M_PAE_NX:
3093	// return BTH_PGMPOOLKIND_PT_FOR_BIG_US_NX;
3094	// case X86_PDE4M_RW \| X86_PDE4M_US \| X86_PDE4M_PAE_NX:
3095	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_US_NX;
3096	# endif
3097	return BTH_PGMPOOLKIND_PT_FOR_BIG;
3098	//}
3099	}
3100	# endif
3101	#endif
3102
3103	#undef MY_STAM_COUNTER_INC
3104	#define MY_STAM_COUNTER_INC(a) do { } while (0)
3105
3106
3107	/**
3108	* Syncs the paging hierarchy starting at CR3.
3109	*
3110	* @returns VBox status code, no specials.
3111	* @param pVM The virtual machine.
3112	* @param cr0 Guest context CR0 register
3113	* @param cr3 Guest context CR3 register
3114	* @param cr4 Guest context CR4 register
3115	* @param fGlobal Including global page directories or not
3116	*/
3117	PGM_BTH_DECL(int, SyncCR3)(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
3118	{
3119	if (VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3))
3120	fGlobal = true; /* Change this CR3 reload to be a global one. */
3121
3122	#if PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
3123	/*
3124	* Update page access handlers.
3125	* The virtual are always flushed, while the physical are only on demand.
3126	* WARNING: We are incorrectly not doing global flushing on Virtual Handler updates. We'll
3127	* have to look into that later because it will have a bad influence on the performance.
3128	* @note SvL: There's no need for that. Just invalidate the virtual range(s).
3129	* bird: Yes, but that won't work for aliases.
3130	*/
3131	/** @todo this MUST go away. See #1557. */
3132	STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3Handlers), h);
3133	PGM_GST_NAME(HandlerVirtualUpdate)(pVM, cr4);
3134	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3Handlers), h);
3135	#endif
3136
3137	#ifdef PGMPOOL_WITH_MONITORING
3138	int rc = pgmPoolSyncCR3(pVM);
3139	if (rc != VINF_SUCCESS)
3140	return rc;
3141	#endif
3142
3143	#if PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3144	/*
3145	* Nested / EPT - almost no work.
3146	*/
3147	/** @todo check if this is really necessary */
3148	HWACCMFlushTLB(pVM);
3149	return VINF_SUCCESS;
3150
3151	#elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3152	/*
3153	* AMD64 (Shw & Gst) - No need to check all paging levels; we zero
3154	* out the shadow parts when the guest modifies its tables.
3155	*/
3156	return VINF_SUCCESS;
3157
3158	#else /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
3159	/*
3160	* PAE and 32-bit legacy mode (shadow).
3161	* (Guest PAE, 32-bit legacy, protected and real modes.)
3162	*/
3163	Assert(fGlobal \|\| (cr4 & X86_CR4_PGE));
3164	MY_STAM_COUNTER_INC(fGlobal ? &pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3Global) : &pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3NotGlobal));
3165
3166	# if PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE
3167	bool const fBigPagesSupported = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
3168
3169	/*
3170	* Get page directory addresses.
3171	*/
3172	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3173	PX86PDE pPDEDst = &pVM->pgm.s.CTXMID(p,32BitPD)->a[0];
3174	# else /* PGM_SHW_TYPE == PGM_TYPE_PAE */
3175	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3176	PX86PDEPAE pPDEDst = NULL;
3177	# endif
3178	# endif
3179
3180	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3181	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(&pVM->pgm.s);
3182	Assert(pPDSrc);
3183	# ifndef IN_RC
3184	Assert(PGMPhysGCPhys2HCPtrAssert(pVM, (RTGCPHYS)(cr3 & GST_CR3_PAGE_MASK), sizeof(*pPDSrc)) == pPDSrc);
3185	# endif
3186	# endif /* PGM_GST_TYPE == PGM_TYPE_32BIT */
3187
3188	/*
3189	* Iterate the the CR3 page.
3190	*/
3191	PPGMMAPPING pMapping;
3192	unsigned iPdNoMapping;
3193	const bool fRawR0Enabled = EMIsRawRing0Enabled(pVM);
3194	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3195
3196	/* Only check mappings if they are supposed to be put into the shadow page table. */
3197	if (pgmMapAreMappingsEnabled(&pVM->pgm.s))
3198	{
3199	pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
3200	iPdNoMapping = (pMapping) ? (pMapping->GCPtr >> GST_PD_SHIFT) : ~0U;
3201	}
3202	else
3203	{
3204	pMapping = 0;
3205	iPdNoMapping = ~0U;
3206	}
3207
3208	# if PGM_GST_TYPE == PGM_TYPE_PAE
3209	for (uint64_t iPdpt = 0; iPdpt < GST_PDPE_ENTRIES; iPdpt++)
3210	{
3211	unsigned iPDSrc;
3212	X86PDPE PdpeSrc;
3213	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, iPdpt << X86_PDPT_SHIFT, &iPDSrc, &PdpeSrc);
3214	PX86PDEPAE pPDEDst = pgmShwGetPaePDEPtr(&pVM->pgm.s, iPdpt << X86_PDPT_SHIFT);
3215	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(&pVM->pgm.s);
3216
3217	if (pPDSrc == NULL)
3218	{
3219	/* PDPE not present */
3220	if (pPdptDst->a[iPdpt].n.u1Present)
3221	{
3222	LogFlow(("SyncCR3: guest PDPE %lld not present; clear shw pdpe\n", iPdpt));
3223	/* for each page directory entry */
3224	for (unsigned iPD = 0; iPD < RT_ELEMENTS(pPDSrc->a); iPD++)
3225	{
3226	if ( pPDEDst[iPD].n.u1Present
3227	&& !(pPDEDst[iPD].u & PGM_PDFLAGS_MAPPING))
3228	{
3229	pgmPoolFree(pVM, pPDEDst[iPD].u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPdpt * X86_PG_PAE_ENTRIES + iPD);
3230	pPDEDst[iPD].u = 0;
3231	}
3232	}
3233	}
3234	if (!(pPdptDst->a[iPdpt].u & PGM_PLXFLAGS_MAPPING))
3235	pPdptDst->a[iPdpt].n.u1Present = 0;
3236	continue;
3237	}
3238	# else /* PGM_GST_TYPE != PGM_TYPE_PAE */
3239	{
3240	# endif /* PGM_GST_TYPE != PGM_TYPE_PAE */
3241	for (unsigned iPD = 0; iPD < RT_ELEMENTS(pPDSrc->a); iPD++)
3242	{
3243	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3244	if (!(iPD & (X86_PG_PAE_ENTRIES - 1))) /* Start of new PD. */
3245	pPDEDst = pgmShwGetPaePDEPtr(&pVM->pgm.s, (uint32_t)iPD << GST_PD_SHIFT);
3246	# endif
3247	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3248	Assert(&pVM->pgm.s.CTXMID(p,32BitPD)->a[iPD] == pPDEDst);
3249	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3250	# ifdef VBOX_STRICT
3251	RTGCPTR GCPtrStrict = (uint32_t)iPD << GST_PD_SHIFT;
3252	# if PGM_GST_TYPE == PGM_TYPE_PAE
3253	GCPtrStrict \|= iPdpt << X86_PDPT_SHIFT;
3254	# endif
3255	AssertMsg(pgmShwGetPaePDEPtr(&pVM->pgm.s, GCPtrStrict) == pPDEDst, ("%p vs %p (%RGv)\n", pgmShwGetPaePDEPtr(&pVM->pgm.s, GCPtrStrict), pPDEDst, GCPtrStrict));
3256	# endif /* VBOX_STRICT */
3257	# endif
3258	GSTPDE PdeSrc = pPDSrc->a[iPD];
3259	if ( PdeSrc.n.u1Present
3260	&& (PdeSrc.n.u1User \|\| fRawR0Enabled))
3261	{
3262	# if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
3263	\|\| PGM_GST_TYPE == PGM_TYPE_PAE) \
3264	&& !defined(PGM_WITHOUT_MAPPINGS)
3265
3266	/*
3267	* Check for conflicts with GC mappings.
3268	*/
3269	# if PGM_GST_TYPE == PGM_TYPE_PAE
3270	if (iPD + iPdpt * X86_PG_PAE_ENTRIES == iPdNoMapping)
3271	# else
3272	if (iPD == iPdNoMapping)
3273	# endif
3274	{
3275	if (pVM->pgm.s.fMappingsFixed)
3276	{
3277	/* It's fixed, just skip the mapping. */
3278	const unsigned cPTs = pMapping->cb >> GST_PD_SHIFT;
3279	Assert(PGM_GST_TYPE == PGM_TYPE_32BIT \|\| (iPD + cPTs - 1) / X86_PG_PAE_ENTRIES == iPD / X86_PG_PAE_ENTRIES);
3280	iPD += cPTs - 1;
3281	# if PGM_SHW_TYPE != PGM_GST_TYPE /* SHW==PAE && GST==32BIT */
3282	pPDEDst = pgmShwGetPaePDEPtr(&pVM->pgm.s, (uint32_t)(iPD + 1) << GST_PD_SHIFT);
3283	# else
3284	pPDEDst += cPTs;
3285	# endif
3286	pMapping = pMapping->CTX_SUFF(pNext);
3287	iPdNoMapping = pMapping ? pMapping->GCPtr >> GST_PD_SHIFT : ~0U;
3288	continue;
3289	}
3290	# ifdef IN_RING3
3291	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3292	int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, iPD << GST_PD_SHIFT);
3293	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3294	int rc = pgmR3SyncPTResolveConflictPAE(pVM, pMapping, (iPdpt << GST_PDPT_SHIFT) + (iPD << GST_PD_SHIFT));
3295	# endif
3296	if (RT_FAILURE(rc))
3297	return rc;
3298
3299	/*
3300	* Update iPdNoMapping and pMapping.
3301	*/
3302	pMapping = pVM->pgm.s.pMappingsR3;
3303	while (pMapping && pMapping->GCPtr < (iPD << GST_PD_SHIFT))
3304	pMapping = pMapping->pNextR3;
3305	iPdNoMapping = pMapping ? pMapping->GCPtr >> GST_PD_SHIFT : ~0U;
3306	# else /* !IN_RING3 */
3307	LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
3308	return VINF_PGM_SYNC_CR3;
3309	# endif /* !IN_RING3 */
3310	}
3311	# else /* (PGM_GST_TYPE != PGM_TYPE_32BIT && PGM_GST_TYPE != PGM_TYPE_PAE) \|\| PGM_WITHOUT_MAPPINGS */
3312	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
3313	# endif /* (PGM_GST_TYPE != PGM_TYPE_32BIT && PGM_GST_TYPE != PGM_TYPE_PAE) \|\| PGM_WITHOUT_MAPPINGS */
3314
3315	/*
3316	* Sync page directory entry.
3317	*
3318	* The current approach is to allocated the page table but to set
3319	* the entry to not-present and postpone the page table synching till
3320	* it's actually used.
3321	*/
3322	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3323	for (unsigned i = 0, iPdShw = iPD * 2; i < 2; i++, iPdShw++) /* pray that the compiler unrolls this */
3324	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3325	const unsigned iPdShw = iPD + iPdpt * X86_PG_PAE_ENTRIES; NOREF(iPdShw);
3326	# else
3327	const unsigned iPdShw = iPD; NOREF(iPdShw);
3328	# endif
3329	{
3330	SHWPDE PdeDst = *pPDEDst;
3331	if (PdeDst.n.u1Present)
3332	{
3333	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
3334	RTGCPHYS GCPhys;
3335	if ( !PdeSrc.b.u1Size
3336	\|\| !fBigPagesSupported)
3337	{
3338	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
3339	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3340	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
3341	GCPhys \|= i * (PAGE_SIZE / 2);
3342	# endif
3343	}
3344	else
3345	{
3346	GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
3347	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3348	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
3349	GCPhys \|= i * X86_PAGE_2M_SIZE;
3350	# endif
3351	}
3352
3353	if ( pShwPage->GCPhys == GCPhys
3354	&& pShwPage->enmKind == PGM_BTH_NAME(CalcPageKind)(&PdeSrc, cr4)
3355	&& ( pShwPage->fCached
3356	\|\| ( !fGlobal
3357	&& ( false
3358	# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
3359	\|\| ( (PdeSrc.u & (X86_PDE4M_PS \| X86_PDE4M_G)) == (X86_PDE4M_PS \| X86_PDE4M_G)
3360	&& (cr4 & (X86_CR4_PGE \| X86_CR4_PSE)) == (X86_CR4_PGE \| X86_CR4_PSE)) /* global 2/4MB page. */
3361	\|\| ( !pShwPage->fSeenNonGlobal
3362	&& (cr4 & X86_CR4_PGE))
3363	# endif
3364	)
3365	)
3366	)
3367	&& ( (PdeSrc.u & (X86_PDE_US \| X86_PDE_RW)) == (PdeDst.u & (X86_PDE_US \| X86_PDE_RW))
3368	\|\| ( fBigPagesSupported
3369	&& ((PdeSrc.u & (X86_PDE_US \| X86_PDE4M_PS \| X86_PDE4M_D)) \| PGM_PDFLAGS_TRACK_DIRTY)
3370	== ((PdeDst.u & (X86_PDE_US \| X86_PDE_RW \| PGM_PDFLAGS_TRACK_DIRTY)) \| X86_PDE4M_PS))
3371	)
3372	)
3373	{
3374	# ifdef VBOX_WITH_STATISTICS
3375	if ( !fGlobal
3376	&& (PdeSrc.u & (X86_PDE4M_PS \| X86_PDE4M_G)) == (X86_PDE4M_PS \| X86_PDE4M_G)
3377	&& (cr4 & (X86_CR4_PGE \| X86_CR4_PSE)) == (X86_CR4_PGE \| X86_CR4_PSE))
3378	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3DstSkippedGlobalPD));
3379	else if (!fGlobal && !pShwPage->fSeenNonGlobal && (cr4 & X86_CR4_PGE))
3380	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3DstSkippedGlobalPT));
3381	else
3382	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3DstCacheHit));
3383	# endif /* VBOX_WITH_STATISTICS */
3384	/** @todo a replacement strategy isn't really needed unless we're using a very small pool < 512 pages.
3385	* The whole ageing stuff should be put in yet another set of #ifdefs. For now, let's just skip it. */
3386	//# ifdef PGMPOOL_WITH_CACHE
3387	// pgmPoolCacheUsed(pPool, pShwPage);
3388	//# endif
3389	}
3390	else
3391	{
3392	pgmPoolFreeByPage(pPool, pShwPage, SHW_POOL_ROOT_IDX, iPdShw);
3393	pPDEDst->u = 0;
3394	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3DstFreed));
3395	}
3396	}
3397	else
3398	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3DstNotPresent));
3399
3400	/* advance */
3401	pPDEDst++;
3402	} /* foreach 2MB PAE PDE in 4MB guest PDE */
3403	}
3404	# if PGM_GST_TYPE == PGM_TYPE_PAE
3405	else if (iPD + iPdpt * X86_PG_PAE_ENTRIES != iPdNoMapping)
3406	# else
3407	else if (iPD != iPdNoMapping)
3408	# endif
3409	{
3410	/*
3411	* Check if there is any page directory to mark not present here.
3412	*/
3413	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3414	for (unsigned i = 0, iPdShw = iPD * 2; i < 2; i++, iPdShw++) /* pray that the compiler unrolls this */
3415	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3416	const unsigned iPdShw = iPD + iPdpt * X86_PG_PAE_ENTRIES;
3417	# else
3418	const unsigned iPdShw = iPD;
3419	# endif
3420	{
3421	if (pPDEDst->n.u1Present)
3422	{
3423	pgmPoolFree(pVM, pPDEDst->u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPdShw);
3424	pPDEDst->u = 0;
3425	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3DstFreedSrcNP));
3426	}
3427	pPDEDst++;
3428	}
3429	}
3430	else
3431	{
3432	# if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
3433	\|\| PGM_GST_TYPE == PGM_TYPE_PAE) \
3434	&& !defined(PGM_WITHOUT_MAPPINGS)
3435
3436	const unsigned cPTs = pMapping->cb >> GST_PD_SHIFT;
3437
3438	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
3439	if (pVM->pgm.s.fMappingsFixed)
3440	{
3441	/* It's fixed, just skip the mapping. */
3442	pMapping = pMapping->CTX_SUFF(pNext);
3443	iPdNoMapping = pMapping ? pMapping->GCPtr >> GST_PD_SHIFT : ~0U;
3444	}
3445	else
3446	{
3447	/*
3448	* Check for conflicts for subsequent pagetables
3449	* and advance to the next mapping.
3450	*/
3451	iPdNoMapping = ~0U;
3452	unsigned iPT = cPTs;
3453	while (iPT-- > 1)
3454	{
3455	if ( pPDSrc->a[iPD + iPT].n.u1Present
3456	&& (pPDSrc->a[iPD + iPT].n.u1User \|\| fRawR0Enabled))
3457	{
3458	# ifdef IN_RING3
3459	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3460	int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, iPD << GST_PD_SHIFT);
3461	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3462	int rc = pgmR3SyncPTResolveConflictPAE(pVM, pMapping, (iPdpt << GST_PDPT_SHIFT) + (iPD << GST_PD_SHIFT));
3463	# endif
3464	if (RT_FAILURE(rc))
3465	return rc;
3466
3467	/*
3468	* Update iPdNoMapping and pMapping.
3469	*/
3470	pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
3471	while (pMapping && pMapping->GCPtr < (iPD << GST_PD_SHIFT))
3472	pMapping = pMapping->CTX_SUFF(pNext);
3473	iPdNoMapping = pMapping ? pMapping->GCPtr >> GST_PD_SHIFT : ~0U;
3474	break;
3475	# else
3476	LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
3477	return VINF_PGM_SYNC_CR3;
3478	# endif
3479	}
3480	}
3481	if (iPdNoMapping == ~0U && pMapping)
3482	{
3483	pMapping = pMapping->CTX_SUFF(pNext);
3484	if (pMapping)
3485	iPdNoMapping = pMapping->GCPtr >> GST_PD_SHIFT;
3486	}
3487	}
3488
3489	/* advance. */
3490	Assert(PGM_GST_TYPE == PGM_TYPE_32BIT \|\| (iPD + cPTs - 1) / X86_PG_PAE_ENTRIES == iPD / X86_PG_PAE_ENTRIES);
3491	iPD += cPTs - 1;
3492	# if PGM_SHW_TYPE != PGM_GST_TYPE /* SHW==PAE && GST==32BIT */
3493	pPDEDst = pgmShwGetPaePDEPtr(&pVM->pgm.s, (uint32_t)(iPD + 1) << GST_PD_SHIFT);
3494	# else
3495	pPDEDst += cPTs;
3496	# endif
3497	# if PGM_GST_TYPE != PGM_SHW_TYPE
3498	AssertCompile(PGM_GST_TYPE == PGM_TYPE_32BIT && PGM_SHW_TYPE == PGM_TYPE_PAE);
3499	# endif
3500	# else /* (PGM_GST_TYPE != PGM_TYPE_32BIT && PGM_GST_TYPE != PGM_TYPE_PAE) \|\| PGM_WITHOUT_MAPPINGS */
3501	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
3502	# endif /* (PGM_GST_TYPE != PGM_TYPE_32BIT && PGM_GST_TYPE != PGM_TYPE_PAE) \|\| PGM_WITHOUT_MAPPINGS */
3503	}
3504
3505	} /* for iPD */
3506	} /* for each PDPTE (PAE) */
3507	return VINF_SUCCESS;
3508
3509	# else /* guest real and protected mode */
3510	return VINF_SUCCESS;
3511	# endif
3512	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
3513	}
3514
3515
3516
3517
3518	#ifdef VBOX_STRICT
3519	#ifdef IN_RC
3520	# undef AssertMsgFailed
3521	# define AssertMsgFailed Log
3522	#endif
3523	#ifdef IN_RING3
3524	# include <VBox/dbgf.h>
3525
3526	/**
3527	* Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
3528	*
3529	* @returns VBox status code (VINF_SUCCESS).
3530	* @param pVM The VM handle.
3531	* @param cr3 The root of the hierarchy.
3532	* @param crr The cr4, only PAE and PSE is currently used.
3533	* @param fLongMode Set if long mode, false if not long mode.
3534	* @param cMaxDepth Number of levels to dump.
3535	* @param pHlp Pointer to the output functions.
3536	*/
3537	__BEGIN_DECLS
3538	VMMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint32_t cr3, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp);
3539	__END_DECLS
3540
3541	#endif
3542
3543	/**
3544	* Checks that the shadow page table is in sync with the guest one.
3545	*
3546	* @returns The number of errors.
3547	* @param pVM The virtual machine.
3548	* @param cr3 Guest context CR3 register
3549	* @param cr4 Guest context CR4 register
3550	* @param GCPtr Where to start. Defaults to 0.
3551	* @param cb How much to check. Defaults to everything.
3552	*/
3553	PGM_BTH_DECL(unsigned, AssertCR3)(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb)
3554	{
3555	#if PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3556	return 0;
3557	#else
3558	unsigned cErrors = 0;
3559
3560	#if PGM_GST_TYPE == PGM_TYPE_PAE
3561	/** @todo currently broken; crashes below somewhere */
3562	AssertFailed();
3563	#endif
3564
3565	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
3566	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3567	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
3568
3569	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3570	bool fBigPagesSupported = true;
3571	# else
3572	bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
3573	# endif
3574	PPGM pPGM = &pVM->pgm.s;
3575	RTGCPHYS GCPhysGst; /* page address derived from the guest page tables. */
3576	RTHCPHYS HCPhysShw; /* page address derived from the shadow page tables. */
3577	# ifndef IN_RING0
3578	RTHCPHYS HCPhys; /* general usage. */
3579	# endif
3580	int rc;
3581
3582	/*
3583	* Check that the Guest CR3 and all its mappings are correct.
3584	*/
3585	AssertMsgReturn(pPGM->GCPhysCR3 == (cr3 & GST_CR3_PAGE_MASK),
3586	("Invalid GCPhysCR3=%RGp cr3=%RGp\n", pPGM->GCPhysCR3, (RTGCPHYS)cr3),
3587	false);
3588	# if !defined(IN_RING0) && PGM_GST_TYPE != PGM_TYPE_AMD64
3589	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3590	rc = PGMShwGetPage(pVM, (RTGCPTR)pPGM->pGuestPDRC, NULL, &HCPhysShw);
3591	# else
3592	rc = PGMShwGetPage(pVM, (RTGCPTR)pPGM->pGstPaePDPTRC, NULL, &HCPhysShw);
3593	# endif
3594	AssertRCReturn(rc, 1);
3595	HCPhys = NIL_RTHCPHYS;
3596	rc = pgmRamGCPhys2HCPhys(pPGM, cr3 & GST_CR3_PAGE_MASK, &HCPhys);
3597	AssertMsgReturn(HCPhys == HCPhysShw, ("HCPhys=%RHp HCPhyswShw=%RHp (cr3)\n", HCPhys, HCPhysShw), false);
3598	# if PGM_GST_TYPE == PGM_TYPE_32BIT && defined(IN_RING3)
3599	RTGCPHYS GCPhys;
3600	rc = PGMR3DbgR3Ptr2GCPhys(pVM, pPGM->pGuestPDR3, &GCPhys);
3601	AssertRCReturn(rc, 1);
3602	AssertMsgReturn((cr3 & GST_CR3_PAGE_MASK) == GCPhys, ("GCPhys=%RGp cr3=%RGp\n", GCPhys, (RTGCPHYS)cr3), false);
3603	# endif
3604	# endif /* !IN_RING0 */
3605
3606	/*
3607	* Get and check the Shadow CR3.
3608	*/
3609	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3610	unsigned cPDEs = X86_PG_ENTRIES;
3611	unsigned cIncrement = X86_PG_ENTRIES * PAGE_SIZE;
3612	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3613	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3614	unsigned cPDEs = X86_PG_PAE_ENTRIES * 4; /* treat it as a 2048 entry table. */
3615	# else
3616	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3617	# endif
3618	unsigned cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3619	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3620	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3621	unsigned cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3622	# endif
3623	if (cb != ~(RTGCPTR)0)
3624	cPDEs = RT_MIN(cb >> SHW_PD_SHIFT, 1);
3625
3626	/** @todo call the other two PGMAssert() functions. /
3627
3628	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
3629	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3630	# endif
3631
3632	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3633	unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3634
3635	for (; iPml4 < X86_PG_PAE_ENTRIES; iPml4++)
3636	{
3637	PPGMPOOLPAGE pShwPdpt = NULL;
3638	PX86PML4E pPml4eSrc;
3639	PX86PML4E pPml4eDst;
3640	RTGCPHYS GCPhysPdptSrc;
3641
3642	pPml4eSrc = pgmGstGetLongModePML4EPtr(&pVM->pgm.s, iPml4);
3643	pPml4eDst = pgmShwGetLongModePML4EPtr(&pVM->pgm.s, iPml4);
3644
3645	/* Fetch the pgm pool shadow descriptor if the shadow pml4e is present. */
3646	if (!pPml4eDst->n.u1Present)
3647	{
3648	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3649	continue;
3650	}
3651
3652	pShwPdpt = pgmPoolGetPage(pPool, pPml4eDst->u & X86_PML4E_PG_MASK);
3653	GCPhysPdptSrc = pPml4eSrc->u & X86_PML4E_PG_MASK_FULL;
3654
3655	if (pPml4eSrc->n.u1Present != pPml4eDst->n.u1Present)
3656	{
3657	AssertMsgFailed(("Present bit doesn't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3658	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3659	cErrors++;
3660	continue;
3661	}
3662
3663	if (GCPhysPdptSrc != pShwPdpt->GCPhys)
3664	{
3665	AssertMsgFailed(("Physical address doesn't match! iPml4 %d pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, pPml4eDst->u, pPml4eSrc->u, pShwPdpt->GCPhys, GCPhysPdptSrc));
3666	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3667	cErrors++;
3668	continue;
3669	}
3670
3671	if ( pPml4eDst->n.u1User != pPml4eSrc->n.u1User
3672	\|\| pPml4eDst->n.u1Write != pPml4eSrc->n.u1Write
3673	\|\| pPml4eDst->n.u1NoExecute != pPml4eSrc->n.u1NoExecute)
3674	{
3675	AssertMsgFailed(("User/Write/NoExec bits don't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3676	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3677	cErrors++;
3678	continue;
3679	}
3680	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
3681	{
3682	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
3683
3684	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
3685	/*
3686	* Check the PDPTEs too.
3687	*/
3688	unsigned iPdpt = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
3689
3690	for (;iPdpt <= SHW_PDPT_MASK; iPdpt++)
3691	{
3692	unsigned iPDSrc;
3693	PPGMPOOLPAGE pShwPde = NULL;
3694	PX86PDPE pPdpeDst;
3695	RTGCPHYS GCPhysPdeSrc;
3696	# if PGM_GST_TYPE == PGM_TYPE_PAE
3697	X86PDPE PdpeSrc;
3698	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtr, &iPDSrc, &PdpeSrc);
3699	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(&pVM->pgm.s);
3700	# else
3701	PX86PML4E pPml4eSrc;
3702	X86PDPE PdpeSrc;
3703	PX86PDPT pPdptDst;
3704	PX86PDPAE pPDDst;
3705	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, GCPtr, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3706
3707	rc = pgmShwGetLongModePDPtr(pVM, GCPtr, NULL, &pPdptDst, &pPDDst);
3708	if (rc != VINF_SUCCESS)
3709	{
3710	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
3711	GCPtr += 512 * _2M;
3712	continue; /* next PDPTE */
3713	}
3714	Assert(pPDDst);
3715	# endif
3716	Assert(iPDSrc == 0);
3717
3718	pPdpeDst = &pPdptDst->a[iPdpt];
3719
3720	if (!pPdpeDst->n.u1Present)
3721	{
3722	GCPtr += 512 * _2M;
3723	continue; /* next PDPTE */
3724	}
3725
3726	pShwPde = pgmPoolGetPage(pPool, pPdpeDst->u & X86_PDPE_PG_MASK);
3727	GCPhysPdeSrc = PdpeSrc.u & X86_PDPE_PG_MASK;
3728
3729	if (pPdpeDst->n.u1Present != PdpeSrc.n.u1Present)
3730	{
3731	AssertMsgFailed(("Present bit doesn't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3732	GCPtr += 512 * _2M;
3733	cErrors++;
3734	continue;
3735	}
3736
3737	if (GCPhysPdeSrc != pShwPde->GCPhys)
3738	{
3739	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3740	AssertMsgFailed(("Physical address doesn't match! iPml4 %d iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3741	# else
3742	AssertMsgFailed(("Physical address doesn't match! iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3743	# endif
3744	GCPtr += 512 * _2M;
3745	cErrors++;
3746	continue;
3747	}
3748
3749	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3750	if ( pPdpeDst->lm.u1User != PdpeSrc.lm.u1User
3751	\|\| pPdpeDst->lm.u1Write != PdpeSrc.lm.u1Write
3752	\|\| pPdpeDst->lm.u1NoExecute != PdpeSrc.lm.u1NoExecute)
3753	{
3754	AssertMsgFailed(("User/Write/NoExec bits don't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3755	GCPtr += 512 * _2M;
3756	cErrors++;
3757	continue;
3758	}
3759	# endif
3760
3761	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
3762	{
3763	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
3764	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3765	GSTPD const *pPDSrc = pgmGstGet32bitPDPtr(&pVM->pgm.s);
3766	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3767	PCX86PD pPDDst = pPGM->CTXMID(p,32BitPD);
3768	# endif
3769	# endif /* PGM_GST_TYPE == PGM_TYPE_32BIT */
3770	/*
3771	* Iterate the shadow page directory.
3772	*/
3773	GCPtr = (GCPtr >> SHW_PD_SHIFT) << SHW_PD_SHIFT;
3774	unsigned iPDDst = (GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK;
3775
3776	for (;
3777	iPDDst < cPDEs;
3778	iPDDst++, GCPtr += cIncrement)
3779	{
3780	# if PGM_SHW_TYPE == PGM_TYPE_PAE
3781	const SHWPDE PdeDst = *pgmShwGetPaePDEPtr(pPGM, GCPtr);
3782	# else
3783	const SHWPDE PdeDst = pPDDst->a[iPDDst];
3784	# endif
3785	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
3786	{
3787	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
3788	if ((PdeDst.u & X86_PDE_AVL_MASK) != PGM_PDFLAGS_MAPPING)
3789	{
3790	AssertMsgFailed(("Mapping shall only have PGM_PDFLAGS_MAPPING set! PdeDst.u=%#RX64\n", (uint64_t)PdeDst.u));
3791	cErrors++;
3792	continue;
3793	}
3794	}
3795	else if ( (PdeDst.u & X86_PDE_P)
3796	\|\| ((PdeDst.u & (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY)) == (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY))
3797	)
3798	{
3799	HCPhysShw = PdeDst.u & SHW_PDE_PG_MASK;
3800	PPGMPOOLPAGE pPoolPage = pgmPoolGetPageByHCPhys(pVM, HCPhysShw);
3801	if (!pPoolPage)
3802	{
3803	AssertMsgFailed(("Invalid page table address %RHp at %RGv! PdeDst=%#RX64\n",
3804	HCPhysShw, GCPtr, (uint64_t)PdeDst.u));
3805	cErrors++;
3806	continue;
3807	}
3808	const SHWPT pPTDst = (const SHWPT )PGMPOOL_PAGE_2_PTR(pVM, pPoolPage);
3809
3810	if (PdeDst.u & (X86_PDE4M_PWT \| X86_PDE4M_PCD))
3811	{
3812	AssertMsgFailed(("PDE flags PWT and/or PCD is set at %RGv! These flags are not virtualized! PdeDst=%#RX64\n",
3813	GCPtr, (uint64_t)PdeDst.u));
3814	cErrors++;
3815	}
3816
3817	if (PdeDst.u & (X86_PDE4M_G \| X86_PDE4M_D))
3818	{
3819	AssertMsgFailed(("4K PDE reserved flags at %RGv! PdeDst=%#RX64\n",
3820	GCPtr, (uint64_t)PdeDst.u));
3821	cErrors++;
3822	}
3823
3824	const GSTPDE PdeSrc = pPDSrc->a[(iPDDst >> (GST_PD_SHIFT - SHW_PD_SHIFT)) & GST_PD_MASK];
3825	if (!PdeSrc.n.u1Present)
3826	{
3827	AssertMsgFailed(("Guest PDE at %RGv is not present! PdeDst=%#RX64 PdeSrc=%#RX64\n",
3828	GCPtr, (uint64_t)PdeDst.u, (uint64_t)PdeSrc.u));
3829	cErrors++;
3830	continue;
3831	}
3832
3833	if ( !PdeSrc.b.u1Size
3834	\|\| !fBigPagesSupported)
3835	{
3836	GCPhysGst = PdeSrc.u & GST_PDE_PG_MASK;
3837	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3838	GCPhysGst \|= (iPDDst & 1) * (PAGE_SIZE / 2);
3839	# endif
3840	}
3841	else
3842	{
3843	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3844	if (PdeSrc.u & X86_PDE4M_PG_HIGH_MASK)
3845	{
3846	AssertMsgFailed(("Guest PDE at %RGv is using PSE36 or similar! PdeSrc=%#RX64\n",
3847	GCPtr, (uint64_t)PdeSrc.u));
3848	cErrors++;
3849	continue;
3850	}
3851	# endif
3852	GCPhysGst = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
3853	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3854	GCPhysGst \|= GCPtr & RT_BIT(X86_PAGE_2M_SHIFT);
3855	# endif
3856	}
3857
3858	if ( pPoolPage->enmKind
3859	!= (!PdeSrc.b.u1Size \|\| !fBigPagesSupported ? BTH_PGMPOOLKIND_PT_FOR_PT : BTH_PGMPOOLKIND_PT_FOR_BIG))
3860	{
3861	AssertMsgFailed(("Invalid shadow page table kind %d at %RGv! PdeSrc=%#RX64\n",
3862	pPoolPage->enmKind, GCPtr, (uint64_t)PdeSrc.u));
3863	cErrors++;
3864	}
3865
3866	PPGMPAGE pPhysPage = pgmPhysGetPage(pPGM, GCPhysGst);
3867	if (!pPhysPage)
3868	{
3869	AssertMsgFailed(("Cannot find guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
3870	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3871	cErrors++;
3872	continue;
3873	}
3874
3875	if (GCPhysGst != pPoolPage->GCPhys)
3876	{
3877	AssertMsgFailed(("GCPhysGst=%RGp != pPage->GCPhys=%RGp at %RGv\n",
3878	GCPhysGst, pPoolPage->GCPhys, GCPtr));
3879	cErrors++;
3880	continue;
3881	}
3882
3883	if ( !PdeSrc.b.u1Size
3884	\|\| !fBigPagesSupported)
3885	{
3886	/*
3887	* Page Table.
3888	*/
3889	const GSTPT *pPTSrc;
3890	rc = PGM_GCPHYS_2_PTR(pVM, GCPhysGst & ~(RTGCPHYS)(PAGE_SIZE - 1), &pPTSrc);
3891	if (RT_FAILURE(rc))
3892	{
3893	AssertMsgFailed(("Cannot map/convert guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
3894	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3895	cErrors++;
3896	continue;
3897	}
3898	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/))
3899	!= (PdeDst.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/)))
3900	{
3901	/// @todo We get here a lot on out-of-sync CR3 entries. The access handler should zap them to avoid false alarms here!
3902	// (This problem will go away when/if we shadow multiple CR3s.)
3903	AssertMsgFailed(("4K PDE flags mismatch at %RGv! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3904	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3905	cErrors++;
3906	continue;
3907	}
3908	if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
3909	{
3910	AssertMsgFailed(("4K PDEs cannot have PGM_PDFLAGS_TRACK_DIRTY set! GCPtr=%RGv PdeDst=%#RX64\n",
3911	GCPtr, (uint64_t)PdeDst.u));
3912	cErrors++;
3913	continue;
3914	}
3915
3916	/* iterate the page table. */
3917	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3918	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
3919	const unsigned offPTSrc = ((GCPtr >> SHW_PD_SHIFT) & 1) * 512;
3920	# else
3921	const unsigned offPTSrc = 0;
3922	# endif
3923	for (unsigned iPT = 0, off = 0;
3924	iPT < RT_ELEMENTS(pPTDst->a);
3925	iPT++, off += PAGE_SIZE)
3926	{
3927	const SHWPTE PteDst = pPTDst->a[iPT];
3928
3929	/* skip not-present entries. */
3930	if (!(PteDst.u & (X86_PTE_P \| PGM_PTFLAGS_TRACK_DIRTY))) /** @todo deal with ALL handlers and CSAM !P pages! */
3931	continue;
3932	Assert(PteDst.n.u1Present);
3933
3934	const GSTPTE PteSrc = pPTSrc->a[iPT + offPTSrc];
3935	if (!PteSrc.n.u1Present)
3936	{
3937	# ifdef IN_RING3
3938	PGMAssertHandlerAndFlagsInSync(pVM);
3939	PGMR3DumpHierarchyGC(pVM, cr3, cr4, (PdeSrc.u & GST_PDE_PG_MASK));
3940	# endif
3941	AssertMsgFailed(("Out of sync (!P) PTE at %RGv! PteSrc=%#RX64 PteDst=%#RX64 pPTSrc=%RGv iPTSrc=%x PdeSrc=%x physpte=%RGp\n",
3942	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u, pPTSrc, iPT + offPTSrc, PdeSrc.au32[0],
3943	(PdeSrc.u & GST_PDE_PG_MASK) + (iPT + offPTSrc)*sizeof(PteSrc)));
3944	cErrors++;
3945	continue;
3946	}
3947
3948	uint64_t fIgnoreFlags = GST_PTE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_G \| X86_PTE_D \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT;
3949	# if 1 /** @todo sync accessed bit properly... */
3950	fIgnoreFlags \|= X86_PTE_A;
3951	# endif
3952
3953	/* match the physical addresses */
3954	HCPhysShw = PteDst.u & SHW_PTE_PG_MASK;
3955	GCPhysGst = PteSrc.u & GST_PTE_PG_MASK;
3956
3957	# ifdef IN_RING3
3958	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
3959	if (RT_FAILURE(rc))
3960	{
3961	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
3962	{
3963	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
3964	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3965	cErrors++;
3966	continue;
3967	}
3968	}
3969	else if (HCPhysShw != (HCPhys & SHW_PTE_PG_MASK))
3970	{
3971	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
3972	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3973	cErrors++;
3974	continue;
3975	}
3976	# endif
3977
3978	pPhysPage = pgmPhysGetPage(pPGM, GCPhysGst);
3979	if (!pPhysPage)
3980	{
3981	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
3982	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
3983	{
3984	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
3985	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3986	cErrors++;
3987	continue;
3988	}
3989	# endif
3990	if (PteDst.n.u1Write)
3991	{
3992	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
3993	GCPtr + off, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3994	cErrors++;
3995	}
3996	fIgnoreFlags \|= X86_PTE_RW;
3997	}
3998	else if (HCPhysShw != (PGM_PAGE_GET_HCPHYS(pPhysPage) & SHW_PTE_PG_MASK))
3999	{
4000	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4001	GCPtr + off, HCPhysShw, pPhysPage->HCPhys, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4002	cErrors++;
4003	continue;
4004	}
4005
4006	/* flags */
4007	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
4008	{
4009	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
4010	{
4011	if (PteDst.n.u1Write)
4012	{
4013	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! HCPhys=%RHp PteSrc=%#RX64 PteDst=%#RX64\n",
4014	GCPtr + off, pPhysPage->HCPhys, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4015	cErrors++;
4016	continue;
4017	}
4018	fIgnoreFlags \|= X86_PTE_RW;
4019	}
4020	else
4021	{
4022	if (PteDst.n.u1Present)
4023	{
4024	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! HCPhys=%RHp PteSrc=%#RX64 PteDst=%#RX64\n",
4025	GCPtr + off, pPhysPage->HCPhys, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4026	cErrors++;
4027	continue;
4028	}
4029	fIgnoreFlags \|= X86_PTE_P;
4030	}
4031	}
4032	else
4033	{
4034	if (!PteSrc.n.u1Dirty && PteSrc.n.u1Write)
4035	{
4036	if (PteDst.n.u1Write)
4037	{
4038	AssertMsgFailed(("!DIRTY page at %RGv is writable! PteSrc=%#RX64 PteDst=%#RX64\n",
4039	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4040	cErrors++;
4041	continue;
4042	}
4043	if (!(PteDst.u & PGM_PTFLAGS_TRACK_DIRTY))
4044	{
4045	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4046	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4047	cErrors++;
4048	continue;
4049	}
4050	if (PteDst.n.u1Dirty)
4051	{
4052	AssertMsgFailed(("!DIRTY page at %RGv is marked DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4053	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4054	cErrors++;
4055	}
4056	# if 0 /** @todo sync access bit properly... */
4057	if (PteDst.n.u1Accessed != PteSrc.n.u1Accessed)
4058	{
4059	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4060	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4061	cErrors++;
4062	}
4063	fIgnoreFlags \|= X86_PTE_RW;
4064	# else
4065	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4066	# endif
4067	}
4068	else if (PteDst.u & PGM_PTFLAGS_TRACK_DIRTY)
4069	{
4070	/* access bit emulation (not implemented). */
4071	if (PteSrc.n.u1Accessed \|\| PteDst.n.u1Present)
4072	{
4073	AssertMsgFailed(("PGM_PTFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PteSrc=%#RX64 PteDst=%#RX64\n",
4074	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4075	cErrors++;
4076	continue;
4077	}
4078	if (!PteDst.n.u1Accessed)
4079	{
4080	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PteSrc=%#RX64 PteDst=%#RX64\n",
4081	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4082	cErrors++;
4083	}
4084	fIgnoreFlags \|= X86_PTE_P;
4085	}
4086	# ifdef DEBUG_sandervl
4087	fIgnoreFlags \|= X86_PTE_D \| X86_PTE_A;
4088	# endif
4089	}
4090
4091	if ( (PteSrc.u & ~fIgnoreFlags) != (PteDst.u & ~fIgnoreFlags)
4092	&& (PteSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (PteDst.u & ~fIgnoreFlags)
4093	)
4094	{
4095	AssertMsgFailed(("Flags mismatch at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PteSrc=%#RX64 PteDst=%#RX64\n",
4096	GCPtr + off, (uint64_t)PteSrc.u & ~fIgnoreFlags, (uint64_t)PteDst.u & ~fIgnoreFlags,
4097	fIgnoreFlags, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4098	cErrors++;
4099	continue;
4100	}
4101	} /* foreach PTE */
4102	}
4103	else
4104	{
4105	/*
4106	* Big Page.
4107	*/
4108	uint64_t fIgnoreFlags = X86_PDE_AVL_MASK \| GST_PDE_PG_MASK \| X86_PDE4M_G \| X86_PDE4M_D \| X86_PDE4M_PS \| X86_PDE4M_PWT \| X86_PDE4M_PCD;
4109	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
4110	{
4111	if (PdeDst.n.u1Write)
4112	{
4113	AssertMsgFailed(("!DIRTY page at %RGv is writable! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4114	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4115	cErrors++;
4116	continue;
4117	}
4118	if (!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY))
4119	{
4120	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4121	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4122	cErrors++;
4123	continue;
4124	}
4125	# if 0 /** @todo sync access bit properly... */
4126	if (PdeDst.n.u1Accessed != PdeSrc.b.u1Accessed)
4127	{
4128	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4129	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4130	cErrors++;
4131	}
4132	fIgnoreFlags \|= X86_PTE_RW;
4133	# else
4134	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4135	# endif
4136	}
4137	else if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
4138	{
4139	/* access bit emulation (not implemented). */
4140	if (PdeSrc.b.u1Accessed \|\| PdeDst.n.u1Present)
4141	{
4142	AssertMsgFailed(("PGM_PDFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4143	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4144	cErrors++;
4145	continue;
4146	}
4147	if (!PdeDst.n.u1Accessed)
4148	{
4149	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4150	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4151	cErrors++;
4152	}
4153	fIgnoreFlags \|= X86_PTE_P;
4154	}
4155
4156	if ((PdeSrc.u & ~fIgnoreFlags) != (PdeDst.u & ~fIgnoreFlags))
4157	{
4158	AssertMsgFailed(("Flags mismatch (B) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PdeDst=%#RX64\n",
4159	GCPtr, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PdeDst.u & ~fIgnoreFlags,
4160	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4161	cErrors++;
4162	}
4163
4164	/* iterate the page table. */
4165	for (unsigned iPT = 0, off = 0;
4166	iPT < RT_ELEMENTS(pPTDst->a);
4167	iPT++, off += PAGE_SIZE, GCPhysGst += PAGE_SIZE)
4168	{
4169	const SHWPTE PteDst = pPTDst->a[iPT];
4170
4171	if (PteDst.u & PGM_PTFLAGS_TRACK_DIRTY)
4172	{
4173	AssertMsgFailed(("The PTE at %RGv emulating a 2/4M page is marked TRACK_DIRTY! PdeSrc=%#RX64 PteDst=%#RX64\n",
4174	GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4175	cErrors++;
4176	}
4177
4178	/* skip not-present entries. */
4179	if (!PteDst.n.u1Present) /** @todo deal with ALL handlers and CSAM !P pages! */
4180	continue;
4181
4182	fIgnoreFlags = X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT \| X86_PTE_D \| X86_PTE_A \| X86_PTE_G \| X86_PTE_PAE_NX;
4183
4184	/* match the physical addresses */
4185	HCPhysShw = PteDst.u & X86_PTE_PAE_PG_MASK;
4186
4187	# ifdef IN_RING3
4188	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
4189	if (RT_FAILURE(rc))
4190	{
4191	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
4192	{
4193	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4194	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4195	cErrors++;
4196	}
4197	}
4198	else if (HCPhysShw != (HCPhys & X86_PTE_PAE_PG_MASK))
4199	{
4200	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4201	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4202	cErrors++;
4203	continue;
4204	}
4205	# endif
4206	pPhysPage = pgmPhysGetPage(pPGM, GCPhysGst);
4207	if (!pPhysPage)
4208	{
4209	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
4210	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
4211	{
4212	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4213	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4214	cErrors++;
4215	continue;
4216	}
4217	# endif
4218	if (PteDst.n.u1Write)
4219	{
4220	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4221	GCPtr + off, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4222	cErrors++;
4223	}
4224	fIgnoreFlags \|= X86_PTE_RW;
4225	}
4226	else if (HCPhysShw != (pPhysPage->HCPhys & X86_PTE_PAE_PG_MASK))
4227	{
4228	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4229	GCPtr + off, HCPhysShw, pPhysPage->HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4230	cErrors++;
4231	continue;
4232	}
4233
4234	/* flags */
4235	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
4236	{
4237	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
4238	{
4239	if (PGM_PAGE_GET_HNDL_PHYS_STATE(pPhysPage) != PGM_PAGE_HNDL_PHYS_STATE_DISABLED)
4240	{
4241	if (PteDst.n.u1Write)
4242	{
4243	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! HCPhys=%RHp PdeSrc=%#RX64 PteDst=%#RX64\n",
4244	GCPtr + off, pPhysPage->HCPhys, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4245	cErrors++;
4246	continue;
4247	}
4248	fIgnoreFlags \|= X86_PTE_RW;
4249	}
4250	}
4251	else
4252	{
4253	if (PteDst.n.u1Present)
4254	{
4255	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! HCPhys=%RHp PdeSrc=%#RX64 PteDst=%#RX64\n",
4256	GCPtr + off, pPhysPage->HCPhys, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4257	cErrors++;
4258	continue;
4259	}
4260	fIgnoreFlags \|= X86_PTE_P;
4261	}
4262	}
4263
4264	if ( (PdeSrc.u & ~fIgnoreFlags) != (PteDst.u & ~fIgnoreFlags)
4265	&& (PdeSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (PteDst.u & ~fIgnoreFlags) /* lazy phys handler dereg. */
4266	)
4267	{
4268	AssertMsgFailed(("Flags mismatch (BT) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PteDst=%#RX64\n",
4269	GCPtr + off, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PteDst.u & ~fIgnoreFlags,
4270	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4271	cErrors++;
4272	continue;
4273	}
4274	} /* for each PTE */
4275	}
4276	}
4277	/* not present */
4278
4279	} /* for each PDE */
4280
4281	} /* for each PDPTE */
4282
4283	} /* for each PML4E */
4284
4285	# ifdef DEBUG
4286	if (cErrors)
4287	LogFlow(("AssertCR3: cErrors=%d\n", cErrors));
4288	# endif
4289
4290	#endif /* GST == 32BIT, PAE or AMD64 */
4291	return cErrors;
4292
4293	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT */
4294	}
4295	#endif /* VBOX_STRICT */
4296

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllBth.h@ 14141

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