PGMAllBth.h@ 18646

Last change on this file since 18646 was 18617, checked in by vboxsync, 16 years ago
PGM,EM: Handle out of memory situations more gracefully - part 1. New debugger commands: .pgmerror and .pgmerroroff.
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File size: 189.4 KB

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1	/* $Id: PGMAllBth.h 18617 2009-04-01 22:11:29Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Shadow+Guest Paging Template - All context code.
4	*
5	* This file is a big challenge!
6	*/
7
8	/*
9	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
10	*
11	* This file is part of VirtualBox Open Source Edition (OSE), as
12	* available from http://www.virtualbox.org. This file is free software;
13	* you can redistribute it and/or modify it under the terms of the GNU
14	* General Public License (GPL) as published by the Free Software
15	* Foundation, in version 2 as it comes in the "COPYING" file of the
16	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
17	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
18	*
19	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
20	* Clara, CA 95054 USA or visit http://www.sun.com if you need
21	* additional information or have any questions.
22	*/
23
24	/*******************************************************************************
25	* Internal Functions *
26	*******************************************************************************/
27	__BEGIN_DECLS
28	PGM_BTH_DECL(int, Trap0eHandler)(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
29	PGM_BTH_DECL(int, InvalidatePage)(PVM pVM, RTGCPTR GCPtrPage);
30	PGM_BTH_DECL(int, SyncPage)(PVM pVM, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr);
31	PGM_BTH_DECL(int, CheckPageFault)(PVM pVM, uint32_t uErr, PSHWPDE pPdeDst, PGSTPDE pPdeSrc, RTGCPTR GCPtrPage);
32	PGM_BTH_DECL(int, SyncPT)(PVM pVM, unsigned iPD, PGSTPD pPDSrc, RTGCPTR GCPtrPage);
33	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVM pVM, RTGCPTR Addr, unsigned fPage, unsigned uErr);
34	PGM_BTH_DECL(int, PrefetchPage)(PVM pVM, RTGCPTR GCPtrPage);
35	PGM_BTH_DECL(int, SyncCR3)(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
36	#ifdef VBOX_STRICT
37	PGM_BTH_DECL(unsigned, AssertCR3)(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr = 0, RTGCPTR cb = ~(RTGCPTR)0);
38	#endif
39	#ifdef PGMPOOL_WITH_USER_TRACKING
40	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVM pVM, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys);
41	#endif
42	PGM_BTH_DECL(int, MapCR3)(PVM pVM, RTGCPHYS GCPhysCR3);
43	PGM_BTH_DECL(int, UnmapCR3)(PVM pVM);
44	__END_DECLS
45
46
47	/* Filter out some illegal combinations of guest and shadow paging, so we can remove redundant checks inside functions. */
48	#if PGM_GST_TYPE == PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
49	# error "Invalid combination; PAE guest implies PAE shadow"
50	#endif
51
52	#if (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
53	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT)
54	# error "Invalid combination; real or protected mode without paging implies 32 bits or PAE shadow paging."
55	#endif
56
57	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) \
58	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT)
59	# error "Invalid combination; 32 bits guest paging or PAE implies 32 bits or PAE shadow paging."
60	#endif
61
62	#if (PGM_GST_TYPE == PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT) \
63	\|\| (PGM_SHW_TYPE == PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PROT)
64	# error "Invalid combination; AMD64 guest implies AMD64 shadow and vice versa"
65	#endif
66
67	#ifdef IN_RING0 /* no mappings in VT-x and AMD-V mode */
68	# define PGM_WITHOUT_MAPPINGS
69	#endif
70
71
72	#ifndef IN_RING3
73	/**
74	* #PF Handler for raw-mode guest execution.
75	*
76	* @returns VBox status code (appropriate for trap handling and GC return).
77	*
78	* @param pVM VM Handle.
79	* @param uErr The trap error code.
80	* @param pRegFrame Trap register frame.
81	* @param pvFault The fault address.
82	*/
83	PGM_BTH_DECL(int, Trap0eHandler)(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
84	{
85	# if defined(IN_RC) && defined(VBOX_STRICT)
86	PGMDynCheckLocks(pVM);
87	# endif
88
89	# if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
90	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
91	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT)
92
93	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE != PGM_TYPE_PAE
94	/*
95	* Hide the instruction fetch trap indicator for now.
96	*/
97	/** @todo NXE will change this and we must fix NXE in the switcher too! */
98	if (uErr & X86_TRAP_PF_ID)
99	{
100	uErr &= ~X86_TRAP_PF_ID;
101	TRPMSetErrorCode(pVM, uErr);
102	}
103	# endif
104
105	/*
106	* Get PDs.
107	*/
108	int rc;
109	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
110	# if PGM_GST_TYPE == PGM_TYPE_32BIT
111	const unsigned iPDSrc = pvFault >> GST_PD_SHIFT;
112	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(&pVM->pgm.s);
113
114	# elif PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
115
116	# if PGM_GST_TYPE == PGM_TYPE_PAE
117	unsigned iPDSrc;
118	X86PDPE PdpeSrc;
119	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, pvFault, &iPDSrc, &PdpeSrc);
120
121	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
122	unsigned iPDSrc;
123	PX86PML4E pPml4eSrc;
124	X86PDPE PdpeSrc;
125	PGSTPD pPDSrc;
126
127	pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, pvFault, &pPml4eSrc, &PdpeSrc, &iPDSrc);
128	Assert(pPml4eSrc);
129	# endif
130
131	/* Quick check for a valid guest trap. (PAE & AMD64) */
132	if (!pPDSrc)
133	{
134	# if PGM_GST_TYPE == PGM_TYPE_AMD64 && GC_ARCH_BITS == 64
135	LogFlow(("Trap0eHandler: guest PML4 %d not present CR3=%RGp\n", (int)((pvFault >> X86_PML4_SHIFT) & X86_PML4_MASK), CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK));
136	# else
137	LogFlow(("Trap0eHandler: guest iPDSrc=%u not present CR3=%RGp\n", iPDSrc, CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK));
138	# endif
139	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2GuestTrap; });
140	TRPMSetErrorCode(pVM, uErr);
141	return VINF_EM_RAW_GUEST_TRAP;
142	}
143	# endif
144
145	# else /* !PGM_WITH_PAGING */
146	PGSTPD pPDSrc = NULL;
147	const unsigned iPDSrc = 0;
148	# endif /* !PGM_WITH_PAGING */
149
150
151	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
152	const unsigned iPDDst = pvFault >> SHW_PD_SHIFT;
153	PX86PD pPDDst = pgmShwGet32BitPDPtr(&pVM->pgm.s);
154
155	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
156	const unsigned iPDDst = (pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK; /* pPDDst index, not used with the pool. */
157
158	PX86PDPAE pPDDst;
159	# if PGM_GST_TYPE != PGM_TYPE_PAE
160	X86PDPE PdpeSrc;
161
162	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
163	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
164	# endif
165	rc = pgmShwSyncPaePDPtr(pVM, pvFault, &PdpeSrc, &pPDDst);
166	if (rc != VINF_SUCCESS)
167	{
168	AssertRC(rc);
169	return rc;
170	}
171	Assert(pPDDst);
172
173	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
174	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
175	PX86PDPAE pPDDst;
176	# if PGM_GST_TYPE == PGM_TYPE_PROT
177	/* AMD-V nested paging */
178	X86PML4E Pml4eSrc;
179	X86PDPE PdpeSrc;
180	PX86PML4E pPml4eSrc = &Pml4eSrc;
181
182	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
183	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A;
184	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A;
185	# endif
186
187	rc = pgmShwSyncLongModePDPtr(pVM, pvFault, pPml4eSrc, &PdpeSrc, &pPDDst);
188	if (rc != VINF_SUCCESS)
189	{
190	AssertRC(rc);
191	return rc;
192	}
193	Assert(pPDDst);
194
195	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
196	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
197	PEPTPD pPDDst;
198
199	rc = pgmShwGetEPTPDPtr(pVM, pvFault, NULL, &pPDDst);
200	if (rc != VINF_SUCCESS)
201	{
202	AssertRC(rc);
203	return rc;
204	}
205	Assert(pPDDst);
206	# endif
207
208	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
209	/*
210	* If we successfully correct the write protection fault due to dirty bit
211	* tracking, or this page fault is a genuine one, then return immediately.
212	*/
213	STAM_PROFILE_START(&pVM->pgm.s.StatRZTrap0eTimeCheckPageFault, e);
214	rc = PGM_BTH_NAME(CheckPageFault)(pVM, uErr, &pPDDst->a[iPDDst], &pPDSrc->a[iPDSrc], pvFault);
215	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeCheckPageFault, e);
216	if ( rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT
217	\|\| rc == VINF_EM_RAW_GUEST_TRAP)
218	{
219	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution)
220	= rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? &pVM->pgm.s.StatRZTrap0eTime2DirtyAndAccessed : &pVM->pgm.s.StatRZTrap0eTime2GuestTrap; });
221	LogBird(("Trap0eHandler: returns %s\n", rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? "VINF_SUCCESS" : "VINF_EM_RAW_GUEST_TRAP"));
222	return rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? VINF_SUCCESS : rc;
223	}
224
225	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0ePD[iPDSrc]);
226	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
227
228	/*
229	* A common case is the not-present error caused by lazy page table syncing.
230	*
231	* It is IMPORTANT that we weed out any access to non-present shadow PDEs here
232	* so we can safely assume that the shadow PT is present when calling SyncPage later.
233	*
234	* On failure, we ASSUME that SyncPT is out of memory or detected some kind
235	* of mapping conflict and defer to SyncCR3 in R3.
236	* (Again, we do NOT support access handlers for non-present guest pages.)
237	*
238	*/
239	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
240	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
241	# else
242	GSTPDE PdeSrc;
243	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
244	PdeSrc.n.u1Present = 1;
245	PdeSrc.n.u1Write = 1;
246	PdeSrc.n.u1Accessed = 1;
247	PdeSrc.n.u1User = 1;
248	# endif
249	if ( !(uErr & X86_TRAP_PF_P) /* not set means page not present instead of page protection violation */
250	&& !pPDDst->a[iPDDst].n.u1Present
251	&& PdeSrc.n.u1Present
252	)
253
254	{
255	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2SyncPT; });
256	STAM_PROFILE_START(&pVM->pgm.s.StatRZTrap0eTimeSyncPT, f);
257	LogFlow(("=>SyncPT %04x = %08x\n", iPDSrc, PdeSrc.au32[0]));
258	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, pvFault);
259	if (RT_SUCCESS(rc))
260	{
261	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeSyncPT, f);
262	return rc;
263	}
264	Log(("SyncPT: %d failed!! rc=%d\n", iPDSrc, rc));
265	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3); /** @todo no need to do global sync, right? */
266	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeSyncPT, f);
267	return VINF_PGM_SYNC_CR3;
268	}
269
270	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
271	/*
272	* Check if this address is within any of our mappings.
273	*
274	* This is very fast and it's gonna save us a bit of effort below and prevent
275	* us from screwing ourself with MMIO2 pages which have a GC Mapping (VRam).
276	* (BTW, it's impossible to have physical access handlers in a mapping.)
277	*/
278	if (pgmMapAreMappingsEnabled(&pVM->pgm.s))
279	{
280	STAM_PROFILE_START(&pVM->pgm.s.StatRZTrap0eTimeMapping, a);
281	PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
282	for ( ; pMapping; pMapping = pMapping->CTX_SUFF(pNext))
283	{
284	if (pvFault < pMapping->GCPtr)
285	break;
286	if (pvFault - pMapping->GCPtr < pMapping->cb)
287	{
288	/*
289	* The first thing we check is if we've got an undetected conflict.
290	*/
291	if (!pVM->pgm.s.fMappingsFixed)
292	{
293	unsigned iPT = pMapping->cb >> GST_PD_SHIFT;
294	while (iPT-- > 0)
295	if (pPDSrc->a[iPDSrc + iPT].n.u1Present)
296	{
297	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eConflicts);
298	Log(("Trap0e: Detected Conflict %RGv-%RGv\n", pMapping->GCPtr, pMapping->GCPtrLast));
299	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3); /** @todo no need to do global sync,right? */
300	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeMapping, a);
301	return VINF_PGM_SYNC_CR3;
302	}
303	}
304
305	/*
306	* Check if the fault address is in a virtual page access handler range.
307	*/
308	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->HyperVirtHandlers, pvFault);
309	if ( pCur
310	&& pvFault - pCur->Core.Key < pCur->cb
311	&& uErr & X86_TRAP_PF_RW)
312	{
313	# ifdef IN_RC
314	STAM_PROFILE_START(&pCur->Stat, h);
315	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
316	STAM_PROFILE_STOP(&pCur->Stat, h);
317	# else
318	AssertFailed();
319	rc = VINF_EM_RAW_EMULATE_INSTR; /* can't happen with VMX */
320	# endif
321	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersMapping);
322	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeMapping, a);
323	return rc;
324	}
325
326	/*
327	* Pretend we're not here and let the guest handle the trap.
328	*/
329	TRPMSetErrorCode(pVM, uErr & ~X86_TRAP_PF_P);
330	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eGuestPFMapping);
331	LogFlow(("PGM: Mapping access -> route trap to recompiler!\n"));
332	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeMapping, a);
333	return VINF_EM_RAW_GUEST_TRAP;
334	}
335	}
336	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeMapping, a);
337	} /* pgmAreMappingsEnabled(&pVM->pgm.s) */
338	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
339
340	/*
341	* Check if this fault address is flagged for special treatment,
342	* which means we'll have to figure out the physical address and
343	* check flags associated with it.
344	*
345	* ASSUME that we can limit any special access handling to pages
346	* in page tables which the guest believes to be present.
347	*/
348	if (PdeSrc.n.u1Present)
349	{
350	RTGCPHYS GCPhys = NIL_RTGCPHYS;
351
352	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
353	# if PGM_GST_TYPE == PGM_TYPE_AMD64
354	bool fBigPagesSupported = true;
355	# else
356	bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
357	# endif
358	if ( PdeSrc.b.u1Size
359	&& fBigPagesSupported)
360	GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc)
361	\| ((RTGCPHYS)pvFault & (GST_BIG_PAGE_OFFSET_MASK ^ PAGE_OFFSET_MASK));
362	else
363	{
364	PGSTPT pPTSrc;
365	rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
366	if (RT_SUCCESS(rc))
367	{
368	unsigned iPTESrc = (pvFault >> GST_PT_SHIFT) & GST_PT_MASK;
369	if (pPTSrc->a[iPTESrc].n.u1Present)
370	GCPhys = pPTSrc->a[iPTESrc].u & GST_PTE_PG_MASK;
371	}
372	}
373	# else
374	/* No paging so the fault address is the physical address */
375	GCPhys = (RTGCPHYS)(pvFault & ~PAGE_OFFSET_MASK);
376	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
377
378	/*
379	* If we have a GC address we'll check if it has any flags set.
380	*/
381	if (GCPhys != NIL_RTGCPHYS)
382	{
383	STAM_PROFILE_START(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
384
385	PPGMPAGE pPage;
386	rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
387	if (RT_SUCCESS(rc)) /** just handle the failure immediate (it returns) and make things easier to read. */
388	{
389	if ( PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(pPage)
390	\|\| PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(pPage))
391	{
392	if (PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage))
393	{
394	/*
395	* Physical page access handler.
396	*/
397	const RTGCPHYS GCPhysFault = GCPhys \| (pvFault & PAGE_OFFSET_MASK);
398	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)RTAvlroGCPhysRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->PhysHandlers, GCPhysFault);
399	if (pCur)
400	{
401	# ifdef PGM_SYNC_N_PAGES
402	/*
403	* If the region is write protected and we got a page not present fault, then sync
404	* the pages. If the fault was caused by a read, then restart the instruction.
405	* In case of write access continue to the GC write handler.
406	*
407	* ASSUMES that there is only one handler per page or that they have similar write properties.
408	*/
409	if ( pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
410	&& !(uErr & X86_TRAP_PF_P))
411	{
412	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, pvFault, PGM_SYNC_NR_PAGES, uErr);
413	if ( RT_FAILURE(rc)
414	\|\| !(uErr & X86_TRAP_PF_RW)
415	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
416	{
417	AssertRC(rc);
418	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersOutOfSync);
419	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
420	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2OutOfSyncHndPhys; });
421	return rc;
422	}
423	}
424	# endif
425
426	AssertMsg( pCur->enmType != PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
427	\|\| (pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE && (uErr & X86_TRAP_PF_RW)),
428	("Unexpected trap for physical handler: %08X (phys=%08x) pPage=%R[pgmpage] uErr=%X, enum=%d\n", pvFault, GCPhys, pPage, uErr, pCur->enmType));
429
430	# if defined(IN_RC) \|\| defined(IN_RING0)
431	if (pCur->CTX_SUFF(pfnHandler))
432	{
433	STAM_PROFILE_START(&pCur->Stat, h);
434	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, GCPhysFault, pCur->CTX_SUFF(pvUser));
435	STAM_PROFILE_STOP(&pCur->Stat, h);
436	}
437	else
438	# endif
439	rc = VINF_EM_RAW_EMULATE_INSTR;
440	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersPhysical);
441	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
442	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2HndPhys; });
443	return rc;
444	}
445	}
446	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
447	else
448	{
449	# ifdef PGM_SYNC_N_PAGES
450	/*
451	* If the region is write protected and we got a page not present fault, then sync
452	* the pages. If the fault was caused by a read, then restart the instruction.
453	* In case of write access continue to the GC write handler.
454	*/
455	if ( PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) < PGM_PAGE_HNDL_PHYS_STATE_ALL
456	&& !(uErr & X86_TRAP_PF_P))
457	{
458	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, pvFault, PGM_SYNC_NR_PAGES, uErr);
459	if ( RT_FAILURE(rc)
460	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
461	\|\| !(uErr & X86_TRAP_PF_RW))
462	{
463	AssertRC(rc);
464	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersOutOfSync);
465	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
466	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2OutOfSyncHndVirt; });
467	return rc;
468	}
469	}
470	# endif
471	/*
472	* Ok, it's an virtual page access handler.
473	*
474	* Since it's faster to search by address, we'll do that first
475	* and then retry by GCPhys if that fails.
476	*/
477	/** @todo r=bird: perhaps we should consider looking up by physical address directly now? */
478	/** @note r=svl: true, but lookup on virtual address should remain as a fallback as phys & virt trees might be out of sync, because the
479	* page was changed without us noticing it (not-present -> present without invlpg or mov cr3, xxx)
480	*/
481	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
482	if (pCur)
483	{
484	AssertMsg(!(pvFault - pCur->Core.Key < pCur->cb)
485	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
486	\|\| !(uErr & X86_TRAP_PF_P)
487	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
488	("Unexpected trap for virtual handler: %RGv (phys=%RGp) pPage=%R[pgmpage] uErr=%X, enum=%d\n", pvFault, GCPhys, pPage, uErr, pCur->enmType));
489
490	if ( pvFault - pCur->Core.Key < pCur->cb
491	&& ( uErr & X86_TRAP_PF_RW
492	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
493	{
494	# ifdef IN_RC
495	STAM_PROFILE_START(&pCur->Stat, h);
496	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
497	STAM_PROFILE_STOP(&pCur->Stat, h);
498	# else
499	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
500	# endif
501	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersVirtual);
502	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
503	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2HndVirt; });
504	return rc;
505	}
506	/* Unhandled part of a monitored page */
507	}
508	else
509	{
510	/* Check by physical address. */
511	PPGMVIRTHANDLER pCur;
512	unsigned iPage;
513	rc = pgmHandlerVirtualFindByPhysAddr(pVM, GCPhys + (pvFault & PAGE_OFFSET_MASK),
514	&pCur, &iPage);
515	Assert(RT_SUCCESS(rc) \|\| !pCur);
516	if ( pCur
517	&& ( uErr & X86_TRAP_PF_RW
518	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
519	{
520	Assert((pCur->aPhysToVirt[iPage].Core.Key & X86_PTE_PAE_PG_MASK) == GCPhys);
521	# ifdef IN_RC
522	RTGCPTR off = (iPage << PAGE_SHIFT) + (pvFault & PAGE_OFFSET_MASK) - (pCur->Core.Key & PAGE_OFFSET_MASK);
523	Assert(off < pCur->cb);
524	STAM_PROFILE_START(&pCur->Stat, h);
525	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, off);
526	STAM_PROFILE_STOP(&pCur->Stat, h);
527	# else
528	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
529	# endif
530	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersVirtualByPhys);
531	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
532	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2HndVirt; });
533	return rc;
534	}
535	}
536	}
537	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
538
539	/*
540	* There is a handled area of the page, but this fault doesn't belong to it.
541	* We must emulate the instruction.
542	*
543	* To avoid crashing (non-fatal) in the interpreter and go back to the recompiler
544	* we first check if this was a page-not-present fault for a page with only
545	* write access handlers. Restart the instruction if it wasn't a write access.
546	*/
547	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersUnhandled);
548
549	if ( !PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
550	&& !(uErr & X86_TRAP_PF_P))
551	{
552	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, pvFault, PGM_SYNC_NR_PAGES, uErr);
553	if ( RT_FAILURE(rc)
554	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
555	\|\| !(uErr & X86_TRAP_PF_RW))
556	{
557	AssertRC(rc);
558	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersOutOfSync);
559	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
560	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2OutOfSyncHndPhys; });
561	return rc;
562	}
563	}
564
565	/** @todo This particular case can cause quite a lot of overhead. E.g. early stage of kernel booting in Ubuntu 6.06
566	* It's writing to an unhandled part of the LDT page several million times.
567	*/
568	rc = PGMInterpretInstruction(pVM, pRegFrame, pvFault);
569	LogFlow(("PGM: PGMInterpretInstruction -> rc=%d pPage=%R[pgmpage]\n", rc, pPage));
570	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
571	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2HndUnhandled; });
572	return rc;
573	} /* if any kind of handler */
574
575	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
576	if (uErr & X86_TRAP_PF_P)
577	{
578	/*
579	* The page isn't marked, but it might still be monitored by a virtual page access handler.
580	* (ASSUMES no temporary disabling of virtual handlers.)
581	*/
582	/** @todo r=bird: Since the purpose is to catch out of sync pages with virtual handler(s) here,
583	* we should correct both the shadow page table and physical memory flags, and not only check for
584	* accesses within the handler region but for access to pages with virtual handlers. */
585	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
586	if (pCur)
587	{
588	AssertMsg( !(pvFault - pCur->Core.Key < pCur->cb)
589	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
590	\|\| !(uErr & X86_TRAP_PF_P)
591	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
592	("Unexpected trap for virtual handler: %08X (phys=%08x) %R[pgmpage] uErr=%X, enum=%d\n", pvFault, GCPhys, pPage, uErr, pCur->enmType));
593
594	if ( pvFault - pCur->Core.Key < pCur->cb
595	&& ( uErr & X86_TRAP_PF_RW
596	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
597	{
598	# ifdef IN_RC
599	STAM_PROFILE_START(&pCur->Stat, h);
600	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
601	STAM_PROFILE_STOP(&pCur->Stat, h);
602	# else
603	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
604	# endif
605	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersVirtualUnmarked);
606	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
607	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2HndVirt; });
608	return rc;
609	}
610	}
611	}
612	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
613	}
614	else
615	{
616	/*
617	* When the guest accesses invalid physical memory (e.g. probing
618	* of RAM or accessing a remapped MMIO range), then we'll fall
619	* back to the recompiler to emulate the instruction.
620	*/
621	LogFlow(("PGM #PF: pgmPhysGetPageEx(%RGp) failed with %Rrc\n", GCPhys, rc));
622	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersInvalid);
623	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
624	return VINF_EM_RAW_EMULATE_INSTR;
625	}
626
627	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
628
629	# ifdef PGM_OUT_OF_SYNC_IN_GC /** @todo remove this bugger. */
630	/*
631	* We are here only if page is present in Guest page tables and
632	* trap is not handled by our handlers.
633	*
634	* Check it for page out-of-sync situation.
635	*/
636	STAM_PROFILE_START(&pVM->pgm.s.StatRZTrap0eTimeOutOfSync, c);
637
638	if (!(uErr & X86_TRAP_PF_P))
639	{
640	/*
641	* Page is not present in our page tables.
642	* Try to sync it!
643	* BTW, fPageShw is invalid in this branch!
644	*/
645	if (uErr & X86_TRAP_PF_US)
646	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncUser));
647	else /* supervisor */
648	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
649
650	# if defined(LOG_ENABLED) && !defined(IN_RING0)
651	RTGCPHYS GCPhys;
652	uint64_t fPageGst;
653	PGMGstGetPage(pVM, pvFault, &fPageGst, &GCPhys);
654	Log(("Page out of sync: %RGv eip=%08x PdeSrc.n.u1User=%d fPageGst=%08llx GCPhys=%RGp scan=%d\n",
655	pvFault, pRegFrame->eip, PdeSrc.n.u1User, fPageGst, GCPhys, CSAMDoesPageNeedScanning(pVM, (RTRCPTR)pRegFrame->eip)));
656	# endif /* LOG_ENABLED */
657
658	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0)
659	if (CPUMGetGuestCPL(pVM, pRegFrame) == 0)
660	{
661	uint64_t fPageGst;
662	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, NULL);
663	if ( RT_SUCCESS(rc)
664	&& !(fPageGst & X86_PTE_US))
665	{
666	/* Note: can't check for X86_TRAP_ID bit, because that requires execute disable support on the CPU */
667	if ( pvFault == (RTGCPTR)pRegFrame->eip
668	\|\| pvFault - pRegFrame->eip < 8 /* instruction crossing a page boundary */
669	# ifdef CSAM_DETECT_NEW_CODE_PAGES
670	\|\| ( !PATMIsPatchGCAddr(pVM, (RTGCPTR)pRegFrame->eip)
671	&& CSAMDoesPageNeedScanning(pVM, (RTRCPTR)pRegFrame->eip)) /* any new code we encounter here */
672	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
673	)
674	{
675	LogFlow(("CSAMExecFault %RX32\n", pRegFrame->eip));
676	rc = CSAMExecFault(pVM, (RTRCPTR)pRegFrame->eip);
677	if (rc != VINF_SUCCESS)
678	{
679	/*
680	* CSAM needs to perform a job in ring 3.
681	*
682	* Sync the page before going to the host context; otherwise we'll end up in a loop if
683	* CSAM fails (e.g. instruction crosses a page boundary and the next page is not present)
684	*/
685	LogFlow(("CSAM ring 3 job\n"));
686	int rc2 = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, pvFault, 1, uErr);
687	AssertRC(rc2);
688
689	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeOutOfSync, c);
690	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2CSAM; });
691	return rc;
692	}
693	}
694	# ifdef CSAM_DETECT_NEW_CODE_PAGES
695	else if ( uErr == X86_TRAP_PF_RW
696	&& pRegFrame->ecx >= 0x100 /* early check for movswd count */
697	&& pRegFrame->ecx < 0x10000)
698	{
699	/* In case of a write to a non-present supervisor shadow page, we'll take special precautions
700	* to detect loading of new code pages.
701	*/
702
703	/*
704	* Decode the instruction.
705	*/
706	RTGCPTR PC;
707	rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->eip, &PC);
708	if (rc == VINF_SUCCESS)
709	{
710	DISCPUSTATE Cpu;
711	uint32_t cbOp;
712	rc = EMInterpretDisasOneEx(pVM, PC, pRegFrame, &Cpu, &cbOp);
713
714	/* For now we'll restrict this to rep movsw/d instructions */
715	if ( rc == VINF_SUCCESS
716	&& Cpu.pCurInstr->opcode == OP_MOVSWD
717	&& (Cpu.prefix & PREFIX_REP))
718	{
719	CSAMMarkPossibleCodePage(pVM, pvFault);
720	}
721	}
722	}
723	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
724
725	/*
726	* Mark this page as safe.
727	*/
728	/** @todo not correct for pages that contain both code and data!! */
729	Log2(("CSAMMarkPage %RGv; scanned=%d\n", pvFault, true));
730	CSAMMarkPage(pVM, (RTRCPTR)pvFault, true);
731	}
732	}
733	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0) */
734	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, pvFault, PGM_SYNC_NR_PAGES, uErr);
735	if (RT_SUCCESS(rc))
736	{
737	/* The page was successfully synced, return to the guest. */
738	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeOutOfSync, c);
739	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2OutOfSync; });
740	return VINF_SUCCESS;
741	}
742	}
743	else /* uErr & X86_TRAP_PF_P: */
744	{
745	/*
746	* Write protected pages is make writable when the guest makes the first
747	* write to it. This happens for pages that are shared, write monitored
748	* and not yet allocated.
749	*
750	* Also, a side effect of not flushing global PDEs are out of sync pages due
751	* to physical monitored regions, that are no longer valid.
752	* Assume for now it only applies to the read/write flag.
753	*/
754	if (RT_SUCCESS(rc) && (uErr & X86_TRAP_PF_RW))
755	{
756	# ifdef VBOX_WITH_NEW_PHYS_CODE
757	if (PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
758	{
759	Log(("PGM #PF: Make writable: %RGp %R[pgmpage] pvFault=%RGp uErr=%#x\n",
760	GCPhys, pPage, pvFault, uErr));
761	rc = pgmPhysPageMakeWritableUnlocked(pVM, pPage, GCPhys);
762	if (rc != VINF_SUCCESS)
763	{
764	AssertMsg(rc == VINF_PGM_SYNC_CR3 \|\| RT_FAILURE(rc), ("%Rrc\n", rc));
765	return rc;
766	}
767	if (RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)))
768	return VINF_EM_NO_MEMORY;
769	}
770	/// @todo count the above case; else
771	# endif /* VBOX_WITH_NEW_PHYS_CODE */
772	if (uErr & X86_TRAP_PF_US)
773	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncUser));
774	else /* supervisor */
775	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
776
777	/*
778	* Note: Do NOT use PGM_SYNC_NR_PAGES here. That only works if the
779	* page is not present, which is not true in this case.
780	*/
781	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, pvFault, 1, uErr);
782	if (RT_SUCCESS(rc))
783	{
784	/*
785	* Page was successfully synced, return to guest.
786	*/
787	# ifdef VBOX_STRICT
788	RTGCPHYS GCPhys;
789	uint64_t fPageGst;
790	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, &GCPhys);
791	Assert(RT_SUCCESS(rc) && fPageGst & X86_PTE_RW);
792	LogFlow(("Obsolete physical monitor page out of sync %RGv - phys %RGp flags=%08llx\n", pvFault, GCPhys, (uint64_t)fPageGst));
793
794	uint64_t fPageShw;
795	rc = PGMShwGetPage(pVM, pvFault, &fPageShw, NULL);
796	AssertMsg(RT_SUCCESS(rc) && fPageShw & X86_PTE_RW, ("rc=%Rrc fPageShw=%RX64\n", rc, fPageShw));
797	# endif /* VBOX_STRICT */
798	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeOutOfSync, c);
799	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2OutOfSyncHndObs; });
800	return VINF_SUCCESS;
801	}
802
803	/* Check to see if we need to emulate the instruction as X86_CR0_WP has been cleared. */
804	if ( CPUMGetGuestCPL(pVM, pRegFrame) == 0
805	&& ((CPUMGetGuestCR0(pVM) & (X86_CR0_WP \| X86_CR0_PG)) == X86_CR0_PG)
806	&& (uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RW \| X86_TRAP_PF_P))
807	{
808	uint64_t fPageGst;
809	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, NULL);
810	if ( RT_SUCCESS(rc)
811	&& !(fPageGst & X86_PTE_RW))
812	{
813	rc = PGMInterpretInstruction(pVM, pRegFrame, pvFault);
814	if (RT_SUCCESS(rc))
815	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eWPEmulInRZ);
816	else
817	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eWPEmulToR3);
818	return rc;
819	}
820	AssertMsgFailed(("Unexpected r/w page %RGv flag=%x rc=%Rrc\n", pvFault, (uint32_t)fPageGst, rc));
821	}
822	}
823
824	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
825	# ifdef VBOX_STRICT
826	/*
827	* Check for VMM page flags vs. Guest page flags consistency.
828	* Currently only for debug purposes.
829	*/
830	if (RT_SUCCESS(rc))
831	{
832	/* Get guest page flags. */
833	uint64_t fPageGst;
834	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, NULL);
835	if (RT_SUCCESS(rc))
836	{
837	uint64_t fPageShw;
838	rc = PGMShwGetPage(pVM, pvFault, &fPageShw, NULL);
839
840	/*
841	* Compare page flags.
842	* Note: we have AVL, A, D bits desynched.
843	*/
844	AssertMsg((fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)) == (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)),
845	("Page flags mismatch! pvFault=%RGv uErr=%x GCPhys=%RGp fPageShw=%RX64 fPageGst=%RX64\n", pvFault, (uint32_t)uErr, GCPhys, fPageShw, fPageGst));
846	}
847	else
848	AssertMsgFailed(("PGMGstGetPage rc=%Rrc\n", rc));
849	}
850	else
851	AssertMsgFailed(("PGMGCGetPage rc=%Rrc\n", rc));
852	# endif /* VBOX_STRICT */
853	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
854	}
855	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeOutOfSync, c);
856	# endif /* PGM_OUT_OF_SYNC_IN_GC */
857	}
858	else /* GCPhys == NIL_RTGCPHYS */
859	{
860	/*
861	* Page not present in Guest OS or invalid page table address.
862	* This is potential virtual page access handler food.
863	*
864	* For the present we'll say that our access handlers don't
865	* work for this case - we've already discarded the page table
866	* not present case which is identical to this.
867	*
868	* When we perchance find we need this, we will probably have AVL
869	* trees (offset based) to operate on and we can measure their speed
870	* agains mapping a page table and probably rearrange this handling
871	* a bit. (Like, searching virtual ranges before checking the
872	* physical address.)
873	*/
874	}
875	}
876	/* else: !present (guest) */
877
878
879	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
880	/*
881	* Conclusion, this is a guest trap.
882	*/
883	LogFlow(("PGM: Unhandled #PF -> route trap to recompiler!\n"));
884	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eGuestPFUnh);
885	return VINF_EM_RAW_GUEST_TRAP;
886	# else
887	/* present, but not a monitored page; perhaps the guest is probing physical memory */
888	return VINF_EM_RAW_EMULATE_INSTR;
889	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
890
891
892	# else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
893
894	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
895	return VERR_INTERNAL_ERROR;
896	# endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
897	}
898	#endif /* !IN_RING3 */
899
900
901	/**
902	* Emulation of the invlpg instruction.
903	*
904	*
905	* @returns VBox status code.
906	*
907	* @param pVM VM handle.
908	* @param GCPtrPage Page to invalidate.
909	*
910	* @remark ASSUMES that the guest is updating before invalidating. This order
911	* isn't required by the CPU, so this is speculative and could cause
912	* trouble.
913	*
914	* @todo Flush page or page directory only if necessary!
915	* @todo Add a #define for simply invalidating the page.
916	*/
917	PGM_BTH_DECL(int, InvalidatePage)(PVM pVM, RTGCPTR GCPtrPage)
918	{
919	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
920	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
921	&& PGM_SHW_TYPE != PGM_TYPE_EPT
922	int rc;
923
924	LogFlow(("InvalidatePage %RGv\n", GCPtrPage));
925	/*
926	* Get the shadow PD entry and skip out if this PD isn't present.
927	* (Guessing that it is frequent for a shadow PDE to not be present, do this first.)
928	*/
929	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
930	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
931	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(&pVM->pgm.s, GCPtrPage);
932
933	/* Fetch the pgm pool shadow descriptor. */
934	PPGMPOOLPAGE pShwPde = pVM->pgm.s.CTX_SUFF(pShwPageCR3);
935	Assert(pShwPde);
936
937	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
938	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT);
939	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(&pVM->pgm.s);
940
941	/* If the shadow PDPE isn't present, then skip the invalidate. */
942	if (!pPdptDst->a[iPdpt].n.u1Present)
943	{
944	Assert(!(pPdptDst->a[iPdpt].u & PGM_PLXFLAGS_MAPPING));
945	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
946	return VINF_SUCCESS;
947	}
948
949	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
950	PPGMPOOLPAGE pShwPde;
951	PX86PDPAE pPDDst;
952
953	/* Fetch the pgm pool shadow descriptor. */
954	rc = pgmShwGetPaePoolPagePD(&pVM->pgm.s, GCPtrPage, &pShwPde);
955	AssertRCSuccessReturn(rc, rc);
956	Assert(pShwPde);
957
958	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPde);
959	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
960
961	# else /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
962	/* PML4 */
963	const unsigned iPml4 = (GCPtrPage >> X86_PML4_SHIFT) & X86_PML4_MASK;
964	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
965	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
966	PX86PDPAE pPDDst;
967	PX86PDPT pPdptDst;
968	PX86PML4E pPml4eDst;
969	rc = pgmShwGetLongModePDPtr(pVM, GCPtrPage, &pPml4eDst, &pPdptDst, &pPDDst);
970	if (rc != VINF_SUCCESS)
971	{
972	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT \|\| rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
973	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
974	if (!VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3))
975	PGM_INVL_GUEST_TLBS();
976	return VINF_SUCCESS;
977	}
978	Assert(pPDDst);
979
980	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
981	PX86PDPE pPdpeDst = &pPdptDst->a[iPdpt];
982
983	if (!pPdpeDst->n.u1Present)
984	{
985	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
986	if (!VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3))
987	PGM_INVL_GUEST_TLBS();
988	return VINF_SUCCESS;
989	}
990
991	# endif /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
992
993	const SHWPDE PdeDst = *pPdeDst;
994	if (!PdeDst.n.u1Present)
995	{
996	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
997	return VINF_SUCCESS;
998	}
999
1000	# if defined(IN_RC)
1001	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
1002	PGMDynLockHCPage(pVM, (uint8_t *)pPdeDst);
1003	# endif
1004
1005	/*
1006	* Get the guest PD entry and calc big page.
1007	*/
1008	# if PGM_GST_TYPE == PGM_TYPE_32BIT
1009	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(&pVM->pgm.s);
1010	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
1011	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
1012	# else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1013	unsigned iPDSrc;
1014	# if PGM_GST_TYPE == PGM_TYPE_PAE
1015	X86PDPE PdpeSrc;
1016	PX86PDPAE pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtrPage, &iPDSrc, &PdpeSrc);
1017	# else /* AMD64 */
1018	PX86PML4E pPml4eSrc;
1019	X86PDPE PdpeSrc;
1020	PX86PDPAE pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
1021	# endif
1022	GSTPDE PdeSrc;
1023
1024	if (pPDSrc)
1025	PdeSrc = pPDSrc->a[iPDSrc];
1026	else
1027	PdeSrc.u = 0;
1028	# endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1029
1030	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1031	const bool fIsBigPage = PdeSrc.b.u1Size;
1032	# else
1033	const bool fIsBigPage = PdeSrc.b.u1Size && (CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
1034	# endif
1035
1036	# ifdef IN_RING3
1037	/*
1038	* If a CR3 Sync is pending we may ignore the invalidate page operation
1039	* depending on the kind of sync and if it's a global page or not.
1040	* This doesn't make sense in GC/R0 so we'll skip it entirely there.
1041	*/
1042	# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
1043	if ( VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3)
1044	\|\| ( VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
1045	&& fIsBigPage
1046	&& PdeSrc.b.u1Global
1047	)
1048	)
1049	# else
1050	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL) )
1051	# endif
1052	{
1053	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
1054	return VINF_SUCCESS;
1055	}
1056	# endif /* IN_RING3 */
1057
1058	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1059	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1060
1061	/* Fetch the pgm pool shadow descriptor. */
1062	PPGMPOOLPAGE pShwPdpt = pgmPoolGetPageByHCPhys(pVM, pPml4eDst->u & X86_PML4E_PG_MASK);
1063	Assert(pShwPdpt);
1064
1065	/* Fetch the pgm pool shadow descriptor. */
1066	PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(pVM, pPdptDst->a[iPdpt].u & SHW_PDPE_PG_MASK);
1067	Assert(pShwPde);
1068
1069	Assert(pPml4eDst->n.u1Present && (pPml4eDst->u & SHW_PDPT_MASK));
1070	RTGCPHYS GCPhysPdpt = pPml4eSrc->u & X86_PML4E_PG_MASK;
1071
1072	if ( !pPml4eSrc->n.u1Present
1073	\|\| pShwPdpt->GCPhys != GCPhysPdpt)
1074	{
1075	LogFlow(("InvalidatePage: Out-of-sync PML4E (P/GCPhys) at %RGv GCPhys=%RGp vs %RGp Pml4eSrc=%RX64 Pml4eDst=%RX64\n",
1076	GCPtrPage, pShwPdpt->GCPhys, GCPhysPdpt, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
1077	pgmPoolFreeByPage(pPool, pShwPdpt, pVM->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPml4);
1078	pPml4eDst->u = 0;
1079	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNPs));
1080	PGM_INVL_GUEST_TLBS();
1081	return VINF_SUCCESS;
1082	}
1083	if ( pPml4eSrc->n.u1User != pPml4eDst->n.u1User
1084	\|\| (!pPml4eSrc->n.u1Write && pPml4eDst->n.u1Write))
1085	{
1086	/*
1087	* Mark not present so we can resync the PML4E when it's used.
1088	*/
1089	LogFlow(("InvalidatePage: Out-of-sync PML4E at %RGv Pml4eSrc=%RX64 Pml4eDst=%RX64\n",
1090	GCPtrPage, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
1091	pgmPoolFreeByPage(pPool, pShwPdpt, pVM->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPml4);
1092	pPml4eDst->u = 0;
1093	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1094	PGM_INVL_GUEST_TLBS();
1095	}
1096	else if (!pPml4eSrc->n.u1Accessed)
1097	{
1098	/*
1099	* Mark not present so we can set the accessed bit.
1100	*/
1101	LogFlow(("InvalidatePage: Out-of-sync PML4E (A) at %RGv Pml4eSrc=%RX64 Pml4eDst=%RX64\n",
1102	GCPtrPage, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
1103	pgmPoolFreeByPage(pPool, pShwPdpt, pVM->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPml4);
1104	pPml4eDst->u = 0;
1105	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNAs));
1106	PGM_INVL_GUEST_TLBS();
1107	}
1108
1109	/* Check if the PDPT entry has changed. */
1110	Assert(pPdpeDst->n.u1Present && pPdpeDst->u & SHW_PDPT_MASK);
1111	RTGCPHYS GCPhysPd = PdpeSrc.u & GST_PDPE_PG_MASK;
1112	if ( !PdpeSrc.n.u1Present
1113	\|\| pShwPde->GCPhys != GCPhysPd)
1114	{
1115	LogFlow(("InvalidatePage: Out-of-sync PDPE (P/GCPhys) at %RGv GCPhys=%RGp vs %RGp PdpeSrc=%RX64 PdpeDst=%RX64\n",
1116	GCPtrPage, pShwPde->GCPhys, GCPhysPd, (uint64_t)PdpeSrc.u, (uint64_t)pPdpeDst->u));
1117	pgmPoolFreeByPage(pPool, pShwPde, pShwPdpt->idx, iPdpt);
1118	pPdpeDst->u = 0;
1119	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNPs));
1120	PGM_INVL_GUEST_TLBS();
1121	return VINF_SUCCESS;
1122	}
1123	if ( PdpeSrc.lm.u1User != pPdpeDst->lm.u1User
1124	\|\| (!PdpeSrc.lm.u1Write && pPdpeDst->lm.u1Write))
1125	{
1126	/*
1127	* Mark not present so we can resync the PDPTE when it's used.
1128	*/
1129	LogFlow(("InvalidatePage: Out-of-sync PDPE at %RGv PdpeSrc=%RX64 PdpeDst=%RX64\n",
1130	GCPtrPage, (uint64_t)PdpeSrc.u, (uint64_t)pPdpeDst->u));
1131	pgmPoolFreeByPage(pPool, pShwPde, pShwPdpt->idx, iPdpt);
1132	pPdpeDst->u = 0;
1133	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1134	PGM_INVL_GUEST_TLBS();
1135	}
1136	else if (!PdpeSrc.lm.u1Accessed)
1137	{
1138	/*
1139	* Mark not present so we can set the accessed bit.
1140	*/
1141	LogFlow(("InvalidatePage: Out-of-sync PDPE (A) at %RGv PdpeSrc=%RX64 PdpeDst=%RX64\n",
1142	GCPtrPage, (uint64_t)PdpeSrc.u, (uint64_t)pPdpeDst->u));
1143	pgmPoolFreeByPage(pPool, pShwPde, pShwPdpt->idx, iPdpt);
1144	pPdpeDst->u = 0;
1145	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNAs));
1146	PGM_INVL_GUEST_TLBS();
1147	}
1148	# endif /* PGM_GST_TYPE == PGM_TYPE_AMD64 */
1149
1150
1151	/*
1152	* Deal with the Guest PDE.
1153	*/
1154	rc = VINF_SUCCESS;
1155	if (PdeSrc.n.u1Present)
1156	{
1157	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
1158	{
1159	/*
1160	* Conflict - Let SyncPT deal with it to avoid duplicate code.
1161	*/
1162	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1163	Assert(PGMGetGuestMode(pVM) <= PGMMODE_PAE);
1164	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, GCPtrPage);
1165	}
1166	else if ( PdeSrc.n.u1User != PdeDst.n.u1User
1167	\|\| (!PdeSrc.n.u1Write && PdeDst.n.u1Write))
1168	{
1169	/*
1170	* Mark not present so we can resync the PDE when it's used.
1171	*/
1172	LogFlow(("InvalidatePage: Out-of-sync at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
1173	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1174	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1175	pPdeDst->u = 0;
1176	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1177	PGM_INVL_GUEST_TLBS();
1178	}
1179	else if (!PdeSrc.n.u1Accessed)
1180	{
1181	/*
1182	* Mark not present so we can set the accessed bit.
1183	*/
1184	LogFlow(("InvalidatePage: Out-of-sync (A) at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
1185	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1186	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1187	pPdeDst->u = 0;
1188	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNAs));
1189	PGM_INVL_GUEST_TLBS();
1190	}
1191	else if (!fIsBigPage)
1192	{
1193	/*
1194	* 4KB - page.
1195	*/
1196	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1197	RTGCPHYS GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
1198	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1199	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1200	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE/2);
1201	# endif
1202	if (pShwPage->GCPhys == GCPhys)
1203	{
1204	# if 0 /* likely cause of a major performance regression; must be SyncPageWorkerTrackDeref then */
1205	const unsigned iPTEDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1206	PSHWPT pPT = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1207	if (pPT->a[iPTEDst].n.u1Present)
1208	{
1209	# ifdef PGMPOOL_WITH_USER_TRACKING
1210	/* This is very unlikely with caching/monitoring enabled. */
1211	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPT->a[iPTEDst].u & SHW_PTE_PG_MASK);
1212	# endif
1213	pPT->a[iPTEDst].u = 0;
1214	}
1215	# else /* Syncing it here isn't 100% safe and it's probably not worth spending time syncing it. */
1216	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, 1, 0);
1217	if (RT_SUCCESS(rc))
1218	rc = VINF_SUCCESS;
1219	# endif
1220	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePage4KBPages));
1221	PGM_INVL_PG(GCPtrPage);
1222	}
1223	else
1224	{
1225	/*
1226	* The page table address changed.
1227	*/
1228	LogFlow(("InvalidatePage: Out-of-sync at %RGp PdeSrc=%RX64 PdeDst=%RX64 ShwGCPhys=%RGp iPDDst=%#x\n",
1229	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, iPDDst));
1230	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1231	pPdeDst->u = 0;
1232	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1233	PGM_INVL_GUEST_TLBS();
1234	}
1235	}
1236	else
1237	{
1238	/*
1239	* 2/4MB - page.
1240	*/
1241	/* Before freeing the page, check if anything really changed. */
1242	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1243	RTGCPHYS GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
1244	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1245	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1246	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
1247	# endif
1248	if ( pShwPage->GCPhys == GCPhys
1249	&& pShwPage->enmKind == BTH_PGMPOOLKIND_PT_FOR_BIG)
1250	{
1251	/* ASSUMES a the given bits are identical for 4M and normal PDEs */
1252	/** @todo PAT */
1253	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD))
1254	== (PdeDst.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD))
1255	&& ( PdeSrc.b.u1Dirty /** @todo rainy day: What about read-only 4M pages? not very common, but still... */
1256	\|\| (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)))
1257	{
1258	LogFlow(("Skipping flush for big page containing %RGv (PD=%X .u=%RX64)-> nothing has changed!\n", GCPtrPage, iPDSrc, PdeSrc.u));
1259	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePage4MBPagesSkip));
1260	# if defined(IN_RC)
1261	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
1262	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
1263	# endif
1264	return VINF_SUCCESS;
1265	}
1266	}
1267
1268	/*
1269	* Ok, the page table is present and it's been changed in the guest.
1270	* If we're in host context, we'll just mark it as not present taking the lazy approach.
1271	* We could do this for some flushes in GC too, but we need an algorithm for
1272	* deciding which 4MB pages containing code likely to be executed very soon.
1273	*/
1274	LogFlow(("InvalidatePage: Out-of-sync PD at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
1275	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1276	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1277	pPdeDst->u = 0;
1278	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePage4MBPages));
1279	PGM_INVL_BIG_PG(GCPtrPage);
1280	}
1281	}
1282	else
1283	{
1284	/*
1285	* Page directory is not present, mark shadow PDE not present.
1286	*/
1287	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
1288	{
1289	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1290	pPdeDst->u = 0;
1291	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNPs));
1292	PGM_INVL_PG(GCPtrPage);
1293	}
1294	else
1295	{
1296	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1297	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDMappings));
1298	}
1299	}
1300	# if defined(IN_RC)
1301	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
1302	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
1303	# endif
1304	return rc;
1305
1306	#else /* guest real and protected mode */
1307	/* There's no such thing as InvalidatePage when paging is disabled, so just ignore. */
1308	return VINF_SUCCESS;
1309	#endif
1310	}
1311
1312
1313	#ifdef PGMPOOL_WITH_USER_TRACKING
1314	/**
1315	* Update the tracking of shadowed pages.
1316	*
1317	* @param pVM The VM handle.
1318	* @param pShwPage The shadow page.
1319	* @param HCPhys The physical page we is being dereferenced.
1320	*/
1321	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVM pVM, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys)
1322	{
1323	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1324	STAM_PROFILE_START(&pVM->pgm.s.StatTrackDeref, a);
1325	LogFlow(("SyncPageWorkerTrackDeref: Damn HCPhys=%RHp pShwPage->idx=%#x!!!\n", HCPhys, pShwPage->idx));
1326
1327	/** @todo If this turns out to be a bottle neck (very likely) two things can be done:
1328	* 1. have a medium sized HCPhys -> GCPhys TLB (hash?)
1329	* 2. write protect all shadowed pages. I.e. implement caching.
1330	*/
1331	/*
1332	* Find the guest address.
1333	*/
1334	for (PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
1335	pRam;
1336	pRam = pRam->CTX_SUFF(pNext))
1337	{
1338	unsigned iPage = pRam->cb >> PAGE_SHIFT;
1339	while (iPage-- > 0)
1340	{
1341	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
1342	{
1343	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1344	pgmTrackDerefGCPhys(pPool, pShwPage, &pRam->aPages[iPage]);
1345	pShwPage->cPresent--;
1346	pPool->cPresent--;
1347	STAM_PROFILE_STOP(&pVM->pgm.s.StatTrackDeref, a);
1348	return;
1349	}
1350	}
1351	}
1352
1353	for (;;)
1354	AssertReleaseMsgFailed(("HCPhys=%RHp wasn't found!\n", HCPhys));
1355	# else /* !PGMPOOL_WITH_GCPHYS_TRACKING */
1356	pShwPage->cPresent--;
1357	pVM->pgm.s.CTX_SUFF(pPool)->cPresent--;
1358	# endif /* !PGMPOOL_WITH_GCPHYS_TRACKING */
1359	}
1360
1361
1362	/**
1363	* Update the tracking of shadowed pages.
1364	*
1365	* @param pVM The VM handle.
1366	* @param pShwPage The shadow page.
1367	* @param u16 The top 16-bit of the pPage->HCPhys.
1368	* @param pPage Pointer to the guest page. this will be modified.
1369	* @param iPTDst The index into the shadow table.
1370	*/
1371	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackAddref)(PVM pVM, PPGMPOOLPAGE pShwPage, uint16_t u16, PPGMPAGE pPage, const unsigned iPTDst)
1372	{
1373	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1374	/*
1375	* Just deal with the simple first time here.
1376	*/
1377	if (!u16)
1378	{
1379	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackVirgin);
1380	u16 = PGMPOOL_TD_MAKE(1, pShwPage->idx);
1381	}
1382	else
1383	u16 = pgmPoolTrackPhysExtAddref(pVM, u16, pShwPage->idx);
1384
1385	/* write back */
1386	Log2(("SyncPageWorkerTrackAddRef: u16=%#x->%#x iPTDst=%#x\n", u16, PGM_PAGE_GET_TRACKING(pPage), iPTDst));
1387	PGM_PAGE_SET_TRACKING(pPage, u16);
1388
1389	# endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
1390
1391	/* update statistics. */
1392	pVM->pgm.s.CTX_SUFF(pPool)->cPresent++;
1393	pShwPage->cPresent++;
1394	if (pShwPage->iFirstPresent > iPTDst)
1395	pShwPage->iFirstPresent = iPTDst;
1396	}
1397	#endif /* PGMPOOL_WITH_USER_TRACKING */
1398
1399
1400	/**
1401	* Creates a 4K shadow page for a guest page.
1402	*
1403	* For 4M pages the caller must convert the PDE4M to a PTE, this includes adjusting the
1404	* physical address. The PdeSrc argument only the flags are used. No page structured
1405	* will be mapped in this function.
1406	*
1407	* @param pVM VM handle.
1408	* @param pPteDst Destination page table entry.
1409	* @param PdeSrc Source page directory entry (i.e. Guest OS page directory entry).
1410	* Can safely assume that only the flags are being used.
1411	* @param PteSrc Source page table entry (i.e. Guest OS page table entry).
1412	* @param pShwPage Pointer to the shadow page.
1413	* @param iPTDst The index into the shadow table.
1414	*
1415	* @remark Not used for 2/4MB pages!
1416	*/
1417	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorker)(PVM pVM, PSHWPTE pPteDst, GSTPDE PdeSrc, GSTPTE PteSrc, PPGMPOOLPAGE pShwPage, unsigned iPTDst)
1418	{
1419	if (PteSrc.n.u1Present)
1420	{
1421	/*
1422	* Find the ram range.
1423	*/
1424	PPGMPAGE pPage;
1425	int rc = pgmPhysGetPageEx(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK, &pPage);
1426	if (RT_SUCCESS(rc))
1427	{
1428	#ifdef VBOX_WITH_NEW_PHYS_CODE
1429	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
1430	/* Try make the page writable if necessary. */
1431	if ( PteSrc.n.u1Write
1432	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
1433	&& PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
1434	{
1435	rc = pgmPhysPageMakeWritableUnlocked(pVM, pPage, PteSrc.u & GST_PTE_PG_MASK);
1436	AssertRC(rc);
1437	}
1438	# endif
1439	#endif
1440
1441	/** @todo investiage PWT, PCD and PAT. */
1442	/*
1443	* Make page table entry.
1444	*/
1445	SHWPTE PteDst;
1446	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1447	{
1448	/** @todo r=bird: Are we actually handling dirty and access bits for pages with access handlers correctly? No. */
1449	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1450	{
1451	#if PGM_SHW_TYPE == PGM_TYPE_EPT
1452	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage);
1453	PteDst.n.u1Present = 1;
1454	PteDst.n.u1Execute = 1;
1455	PteDst.n.u1IgnorePAT = 1;
1456	PteDst.n.u3EMT = VMX_EPT_MEMTYPE_WB;
1457	/* PteDst.n.u1Write = 0 && PteDst.n.u1Size = 0 */
1458	#else
1459	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT \| X86_PTE_RW))
1460	\| PGM_PAGE_GET_HCPHYS(pPage);
1461	#endif
1462	}
1463	else
1464	{
1465	LogFlow(("SyncPageWorker: monitored page (%RHp) -> mark not present\n", PGM_PAGE_GET_HCPHYS(pPage)));
1466	PteDst.u = 0;
1467	}
1468	/** @todo count these two kinds. */
1469	}
1470	else
1471	{
1472	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1473	/*
1474	* If the page or page directory entry is not marked accessed,
1475	* we mark the page not present.
1476	*/
1477	if (!PteSrc.n.u1Accessed \|\| !PdeSrc.n.u1Accessed)
1478	{
1479	LogFlow(("SyncPageWorker: page and or page directory not accessed -> mark not present\n"));
1480	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,AccessedPage));
1481	PteDst.u = 0;
1482	}
1483	else
1484	/*
1485	* If the page is not flagged as dirty and is writable, then make it read-only, so we can set the dirty bit
1486	* when the page is modified.
1487	*/
1488	if (!PteSrc.n.u1Dirty && (PdeSrc.n.u1Write & PteSrc.n.u1Write))
1489	{
1490	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyPage));
1491	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT \| X86_PTE_RW))
1492	\| PGM_PAGE_GET_HCPHYS(pPage)
1493	\| PGM_PTFLAGS_TRACK_DIRTY;
1494	}
1495	else
1496	#endif
1497	{
1498	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyPageSkipped));
1499	#if PGM_SHW_TYPE == PGM_TYPE_EPT
1500	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage);
1501	PteDst.n.u1Present = 1;
1502	PteDst.n.u1Write = 1;
1503	PteDst.n.u1Execute = 1;
1504	PteDst.n.u1IgnorePAT = 1;
1505	PteDst.n.u3EMT = VMX_EPT_MEMTYPE_WB;
1506	/* PteDst.n.u1Size = 0 */
1507	#else
1508	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT))
1509	\| PGM_PAGE_GET_HCPHYS(pPage);
1510	#endif
1511	}
1512	}
1513
1514	#ifdef VBOX_WITH_NEW_PHYS_CODE
1515	/*
1516	* Make sure only allocated pages are mapped writable.
1517	*/
1518	if ( PteDst.n.u1Write
1519	&& PteDst.n.u1Present
1520	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
1521	{
1522	PteDst.n.u1Write = 0; /** @todo this isn't quite working yet. */
1523	Log3(("SyncPageWorker: write-protecting %RGp pPage=%R[pgmpage]at iPTDst=%d\n", (RTGCPHYS)(PteSrc.u & X86_PTE_PAE_PG_MASK), pPage, iPTDst));
1524	}
1525	#endif
1526
1527	#ifdef PGMPOOL_WITH_USER_TRACKING
1528	/*
1529	* Keep user track up to date.
1530	*/
1531	if (PteDst.n.u1Present)
1532	{
1533	if (!pPteDst->n.u1Present)
1534	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1535	else if ((pPteDst->u & SHW_PTE_PG_MASK) != (PteDst.u & SHW_PTE_PG_MASK))
1536	{
1537	Log2(("SyncPageWorker: deref! *pPteDst=%RX64 PteDst=%RX64\n", (uint64_t)pPteDst->u, (uint64_t)PteDst.u));
1538	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1539	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1540	}
1541	}
1542	else if (pPteDst->n.u1Present)
1543	{
1544	Log2(("SyncPageWorker: deref! *pPteDst=%RX64\n", (uint64_t)pPteDst->u));
1545	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1546	}
1547	#endif /* PGMPOOL_WITH_USER_TRACKING */
1548
1549	/*
1550	* Update statistics and commit the entry.
1551	*/
1552	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1553	if (!PteSrc.n.u1Global)
1554	pShwPage->fSeenNonGlobal = true;
1555	#endif
1556	*pPteDst = PteDst;
1557	}
1558	/* else MMIO or invalid page, we must handle them manually in the #PF handler. */
1559	/** @todo count these. */
1560	}
1561	else
1562	{
1563	/*
1564	* Page not-present.
1565	*/
1566	LogFlow(("SyncPageWorker: page not present in Pte\n"));
1567	#ifdef PGMPOOL_WITH_USER_TRACKING
1568	/* Keep user track up to date. */
1569	if (pPteDst->n.u1Present)
1570	{
1571	Log2(("SyncPageWorker: deref! *pPteDst=%RX64\n", (uint64_t)pPteDst->u));
1572	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1573	}
1574	#endif /* PGMPOOL_WITH_USER_TRACKING */
1575	pPteDst->u = 0;
1576	/** @todo count these. */
1577	}
1578	}
1579
1580
1581	/**
1582	* Syncs a guest OS page.
1583	*
1584	* There are no conflicts at this point, neither is there any need for
1585	* page table allocations.
1586	*
1587	* @returns VBox status code.
1588	* @returns VINF_PGM_SYNCPAGE_MODIFIED_PDE if it modifies the PDE in any way.
1589	* @param pVM VM handle.
1590	* @param PdeSrc Page directory entry of the guest.
1591	* @param GCPtrPage Guest context page address.
1592	* @param cPages Number of pages to sync (PGM_SYNC_N_PAGES) (default=1).
1593	* @param uErr Fault error (X86_TRAP_PF_*).
1594	*/
1595	PGM_BTH_DECL(int, SyncPage)(PVM pVM, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr)
1596	{
1597	LogFlow(("SyncPage: GCPtrPage=%RGv cPages=%u uErr=%#x\n", GCPtrPage, cPages, uErr));
1598
1599	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
1600	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
1601	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
1602	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
1603	&& PGM_SHW_TYPE != PGM_TYPE_EPT
1604
1605	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
1606	bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
1607	# endif
1608
1609	/*
1610	* Assert preconditions.
1611	*/
1612	Assert(PdeSrc.n.u1Present);
1613	Assert(cPages);
1614	STAM_COUNTER_INC(&pVM->pgm.s.StatSyncPagePD[(GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK]);
1615
1616	/*
1617	* Get the shadow PDE, find the shadow page table in the pool.
1618	*/
1619	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1620	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1621	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(&pVM->pgm.s, GCPtrPage);
1622
1623	/* Fetch the pgm pool shadow descriptor. */
1624	PPGMPOOLPAGE pShwPde = pVM->pgm.s.CTX_SUFF(pShwPageCR3);
1625	Assert(pShwPde);
1626
1627	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1628	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1629	PPGMPOOLPAGE pShwPde;
1630	PX86PDPAE pPDDst;
1631
1632	/* Fetch the pgm pool shadow descriptor. */
1633	int rc = pgmShwGetPaePoolPagePD(&pVM->pgm.s, GCPtrPage, &pShwPde);
1634	AssertRCSuccessReturn(rc, rc);
1635	Assert(pShwPde);
1636
1637	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPde);
1638	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1639
1640	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1641	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1642	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1643	PX86PDPAE pPDDst;
1644	PX86PDPT pPdptDst;
1645
1646	int rc = pgmShwGetLongModePDPtr(pVM, GCPtrPage, NULL, &pPdptDst, &pPDDst);
1647	AssertRCSuccessReturn(rc, rc);
1648	Assert(pPDDst && pPdptDst);
1649	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1650	# endif
1651
1652	SHWPDE PdeDst = *pPdeDst;
1653	AssertMsg(PdeDst.n.u1Present, ("%p=%llx\n", pPdeDst, (uint64_t)PdeDst.u));
1654	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1655
1656	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1657	/* Fetch the pgm pool shadow descriptor. */
1658	PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(pVM, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
1659	Assert(pShwPde);
1660	# endif
1661
1662	# if defined(IN_RC)
1663	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
1664	PGMDynLockHCPage(pVM, (uint8_t *)pPdeDst);
1665	# endif
1666
1667	/*
1668	* Check that the page is present and that the shadow PDE isn't out of sync.
1669	*/
1670	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1671	const bool fBigPage = PdeSrc.b.u1Size;
1672	# else
1673	const bool fBigPage = PdeSrc.b.u1Size && (CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
1674	# endif
1675	RTGCPHYS GCPhys;
1676	if (!fBigPage)
1677	{
1678	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
1679	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1680	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1681	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE/2);
1682	# endif
1683	}
1684	else
1685	{
1686	GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
1687	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1688	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1689	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
1690	# endif
1691	}
1692	if ( pShwPage->GCPhys == GCPhys
1693	&& PdeSrc.n.u1Present
1694	&& (PdeSrc.n.u1User == PdeDst.n.u1User)
1695	&& (PdeSrc.n.u1Write == PdeDst.n.u1Write \|\| !PdeDst.n.u1Write)
1696	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
1697	&& (!fNoExecuteBitValid \|\| PdeSrc.n.u1NoExecute == PdeDst.n.u1NoExecute)
1698	# endif
1699	)
1700	{
1701	/*
1702	* Check that the PDE is marked accessed already.
1703	* Since we set the accessed bit before getting here on a #PF, this
1704	* check is only meant for dealing with non-#PF'ing paths.
1705	*/
1706	if (PdeSrc.n.u1Accessed)
1707	{
1708	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1709	if (!fBigPage)
1710	{
1711	/*
1712	* 4KB Page - Map the guest page table.
1713	*/
1714	PGSTPT pPTSrc;
1715	int rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
1716	if (RT_SUCCESS(rc))
1717	{
1718	# ifdef PGM_SYNC_N_PAGES
1719	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
1720	if ( cPages > 1
1721	&& !(uErr & X86_TRAP_PF_P)
1722	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1723	{
1724	/*
1725	* This code path is currently only taken when the caller is PGMTrap0eHandler
1726	* for non-present pages!
1727	*
1728	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
1729	* deal with locality.
1730	*/
1731	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1732	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1733	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1734	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
1735	# else
1736	const unsigned offPTSrc = 0;
1737	# endif
1738	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
1739	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
1740	iPTDst = 0;
1741	else
1742	iPTDst -= PGM_SYNC_NR_PAGES / 2;
1743	for (; iPTDst < iPTDstEnd; iPTDst++)
1744	{
1745	if (!pPTDst->a[iPTDst].n.u1Present)
1746	{
1747	GSTPTE PteSrc = pPTSrc->a[offPTSrc + iPTDst];
1748	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(GST_PT_MASK << GST_PT_SHIFT)) \| ((offPTSrc + iPTDst) << PAGE_SHIFT);
1749	NOREF(GCPtrCurPage);
1750	#ifndef IN_RING0
1751	/*
1752	* Assuming kernel code will be marked as supervisor - and not as user level
1753	* and executed using a conforming code selector - And marked as readonly.
1754	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
1755	*/
1756	PPGMPAGE pPage;
1757	if ( ((PdeSrc.u & PteSrc.u) & (X86_PTE_RW \| X86_PTE_US))
1758	\|\| iPTDst == ((GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK) /* always sync GCPtrPage */
1759	\|\| !CSAMDoesPageNeedScanning(pVM, (RTRCPTR)GCPtrCurPage)
1760	\|\| ( (pPage = pgmPhysGetPage(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK))
1761	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1762	)
1763	#endif /* else: CSAM not active */
1764	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1765	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
1766	GCPtrCurPage, PteSrc.n.u1Present,
1767	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1768	PteSrc.n.u1User & PdeSrc.n.u1User,
1769	(uint64_t)PteSrc.u,
1770	(uint64_t)pPTDst->a[iPTDst].u,
1771	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1772	}
1773	}
1774	}
1775	else
1776	# endif /* PGM_SYNC_N_PAGES */
1777	{
1778	const unsigned iPTSrc = (GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK;
1779	GSTPTE PteSrc = pPTSrc->a[iPTSrc];
1780	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1781	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1782	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s\n",
1783	GCPtrPage, PteSrc.n.u1Present,
1784	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1785	PteSrc.n.u1User & PdeSrc.n.u1User,
1786	(uint64_t)PteSrc.u,
1787	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1788	}
1789	}
1790	else /* MMIO or invalid page: emulated in #PF handler. */
1791	{
1792	LogFlow(("PGM_GCPHYS_2_PTR %RGp failed with %Rrc\n", GCPhys, rc));
1793	Assert(!pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK].n.u1Present);
1794	}
1795	}
1796	else
1797	{
1798	/*
1799	* 4/2MB page - lazy syncing shadow 4K pages.
1800	* (There are many causes of getting here, it's no longer only CSAM.)
1801	*/
1802	/* Calculate the GC physical address of this 4KB shadow page. */
1803	RTGCPHYS GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc) \| (GCPtrPage & GST_BIG_PAGE_OFFSET_MASK);
1804	/* Find ram range. */
1805	PPGMPAGE pPage;
1806	int rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
1807	if (RT_SUCCESS(rc))
1808	{
1809	# ifdef VBOX_WITH_NEW_PHYS_CODE
1810	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
1811	/* Try make the page writable if necessary. */
1812	if ( PdeSrc.n.u1Write
1813	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
1814	&& PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
1815	{
1816	rc = pgmPhysPageMakeWritableUnlocked(pVM, pPage, GCPhys);
1817	AssertRC(rc);
1818	}
1819	# endif
1820	# endif
1821
1822	/*
1823	* Make shadow PTE entry.
1824	*/
1825	SHWPTE PteDst;
1826	PteDst.u = (PdeSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT))
1827	\| PGM_PAGE_GET_HCPHYS(pPage);
1828	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1829	{
1830	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1831	PteDst.n.u1Write = 0;
1832	else
1833	PteDst.u = 0;
1834	}
1835	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1836	# ifdef PGMPOOL_WITH_USER_TRACKING
1837	if (PteDst.n.u1Present && !pPTDst->a[iPTDst].n.u1Present)
1838	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1839	# endif
1840	# ifdef VBOX_WITH_NEW_PHYS_CODE
1841	/* Make sure only allocated pages are mapped writable. */
1842	if ( PteDst.n.u1Write
1843	&& PteDst.n.u1Present
1844	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
1845	{
1846	PteDst.n.u1Write = 0; /** @todo this isn't quite working yet... */
1847	Log3(("SyncPage: write-protecting %RGp pPage=%R[pgmpage] at %RGv\n", GCPhys, pPage, GCPtrPage));
1848	}
1849	# endif
1850
1851	pPTDst->a[iPTDst] = PteDst;
1852
1853
1854	/*
1855	* If the page is not flagged as dirty and is writable, then make it read-only
1856	* at PD level, so we can set the dirty bit when the page is modified.
1857	*
1858	* ASSUMES that page access handlers are implemented on page table entry level.
1859	* Thus we will first catch the dirty access and set PDE.D and restart. If
1860	* there is an access handler, we'll trap again and let it work on the problem.
1861	*/
1862	/** @todo r=bird: figure out why we need this here, SyncPT should've taken care of this already.
1863	* As for invlpg, it simply frees the whole shadow PT.
1864	* ...It's possibly because the guest clears it and the guest doesn't really tell us... */
1865	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
1866	{
1867	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyPageBig));
1868	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
1869	PdeDst.n.u1Write = 0;
1870	}
1871	else
1872	{
1873	PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
1874	PdeDst.n.u1Write = PdeSrc.n.u1Write;
1875	}
1876	*pPdeDst = PdeDst;
1877	Log2(("SyncPage: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} GCPhys=%RGp%s\n",
1878	GCPtrPage, PdeSrc.n.u1Present, PdeSrc.n.u1Write, PdeSrc.n.u1User, (uint64_t)PdeSrc.u, GCPhys,
1879	PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1880	}
1881	else
1882	LogFlow(("PGM_GCPHYS_2_PTR %RGp (big) failed with %Rrc\n", GCPhys, rc));
1883	}
1884	# if defined(IN_RC)
1885	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
1886	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
1887	# endif
1888	return VINF_SUCCESS;
1889	}
1890	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPagePDNAs));
1891	}
1892	else
1893	{
1894	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPagePDOutOfSync));
1895	Log2(("SyncPage: Out-Of-Sync PDE at %RGp PdeSrc=%RX64 PdeDst=%RX64 (GCPhys %RGp vs %RGp)\n",
1896	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, GCPhys));
1897	}
1898
1899	/*
1900	* Mark the PDE not present. Restart the instruction and let #PF call SyncPT.
1901	* Yea, I'm lazy.
1902	*/
1903	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1904	pgmPoolFreeByPage(pPool, pShwPage, pShwPde->idx, iPDDst);
1905
1906	pPdeDst->u = 0;
1907
1908	# if defined(IN_RC)
1909	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
1910	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
1911	# endif
1912	PGM_INVL_GUEST_TLBS();
1913	return VINF_PGM_SYNCPAGE_MODIFIED_PDE;
1914
1915	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
1916	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
1917	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
1918	&& !defined(IN_RC)
1919
1920	# ifdef PGM_SYNC_N_PAGES
1921	/*
1922	* Get the shadow PDE, find the shadow page table in the pool.
1923	*/
1924	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1925	X86PDE PdeDst = pgmShwGet32BitPDE(&pVM->pgm.s, GCPtrPage);
1926
1927	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1928	X86PDEPAE PdeDst = pgmShwGetPaePDE(&pVM->pgm.s, GCPtrPage);
1929
1930	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1931	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
1932	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64; NOREF(iPdpt);
1933	PX86PDPAE pPDDst;
1934	X86PDEPAE PdeDst;
1935	PX86PDPT pPdptDst;
1936
1937	int rc = pgmShwGetLongModePDPtr(pVM, GCPtrPage, NULL, &pPdptDst, &pPDDst);
1938	AssertRCSuccessReturn(rc, rc);
1939	Assert(pPDDst && pPdptDst);
1940	PdeDst = pPDDst->a[iPDDst];
1941	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
1942	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
1943	PEPTPD pPDDst;
1944	EPTPDE PdeDst;
1945
1946	int rc = pgmShwGetEPTPDPtr(pVM, GCPtrPage, NULL, &pPDDst);
1947	if (rc != VINF_SUCCESS)
1948	{
1949	AssertRC(rc);
1950	return rc;
1951	}
1952	Assert(pPDDst);
1953	PdeDst = pPDDst->a[iPDDst];
1954	# endif
1955	AssertMsg(PdeDst.n.u1Present, ("%#llx\n", (uint64_t)PdeDst.u));
1956	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1957	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1958
1959	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
1960	if ( cPages > 1
1961	&& !(uErr & X86_TRAP_PF_P)
1962	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1963	{
1964	/*
1965	* This code path is currently only taken when the caller is PGMTrap0eHandler
1966	* for non-present pages!
1967	*
1968	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
1969	* deal with locality.
1970	*/
1971	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1972	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
1973	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
1974	iPTDst = 0;
1975	else
1976	iPTDst -= PGM_SYNC_NR_PAGES / 2;
1977	for (; iPTDst < iPTDstEnd; iPTDst++)
1978	{
1979	if (!pPTDst->a[iPTDst].n.u1Present)
1980	{
1981	GSTPTE PteSrc;
1982
1983	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT);
1984
1985	/* Fake the page table entry */
1986	PteSrc.u = GCPtrCurPage;
1987	PteSrc.n.u1Present = 1;
1988	PteSrc.n.u1Dirty = 1;
1989	PteSrc.n.u1Accessed = 1;
1990	PteSrc.n.u1Write = 1;
1991	PteSrc.n.u1User = 1;
1992
1993	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1994
1995	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
1996	GCPtrCurPage, PteSrc.n.u1Present,
1997	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1998	PteSrc.n.u1User & PdeSrc.n.u1User,
1999	(uint64_t)PteSrc.u,
2000	(uint64_t)pPTDst->a[iPTDst].u,
2001	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2002
2003	if (RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)))
2004	break;
2005	}
2006	else
2007	Log4(("%RGv iPTDst=%x pPTDst->a[iPTDst] %RX64\n", (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT), iPTDst, pPTDst->a[iPTDst].u));
2008	}
2009	}
2010	else
2011	# endif /* PGM_SYNC_N_PAGES */
2012	{
2013	GSTPTE PteSrc;
2014	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2015	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT);
2016
2017	/* Fake the page table entry */
2018	PteSrc.u = GCPtrCurPage;
2019	PteSrc.n.u1Present = 1;
2020	PteSrc.n.u1Dirty = 1;
2021	PteSrc.n.u1Accessed = 1;
2022	PteSrc.n.u1Write = 1;
2023	PteSrc.n.u1User = 1;
2024	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2025
2026	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}PteDst=%08llx%s\n",
2027	GCPtrPage, PteSrc.n.u1Present,
2028	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2029	PteSrc.n.u1User & PdeSrc.n.u1User,
2030	(uint64_t)PteSrc.u,
2031	(uint64_t)pPTDst->a[iPTDst].u,
2032	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2033	}
2034	return VINF_SUCCESS;
2035
2036	#else
2037	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
2038	return VERR_INTERNAL_ERROR;
2039	#endif
2040	}
2041
2042
2043	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
2044	/**
2045	* Investigate page fault and handle write protection page faults caused by
2046	* dirty bit tracking.
2047	*
2048	* @returns VBox status code.
2049	* @param pVM VM handle.
2050	* @param uErr Page fault error code.
2051	* @param pPdeDst Shadow page directory entry.
2052	* @param pPdeSrc Guest page directory entry.
2053	* @param GCPtrPage Guest context page address.
2054	*/
2055	PGM_BTH_DECL(int, CheckPageFault)(PVM pVM, uint32_t uErr, PSHWPDE pPdeDst, PGSTPDE pPdeSrc, RTGCPTR GCPtrPage)
2056	{
2057	bool fWriteProtect = !!(CPUMGetGuestCR0(pVM) & X86_CR0_WP);
2058	bool fUserLevelFault = !!(uErr & X86_TRAP_PF_US);
2059	bool fWriteFault = !!(uErr & X86_TRAP_PF_RW);
2060	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2061	bool fBigPagesSupported = true;
2062	# else
2063	bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
2064	# endif
2065	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2066	bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
2067	# endif
2068	unsigned uPageFaultLevel;
2069	int rc;
2070
2071	STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2072	LogFlow(("CheckPageFault: GCPtrPage=%RGv uErr=%#x PdeSrc=%08x\n", GCPtrPage, uErr, pPdeSrc->u));
2073
2074	# if PGM_GST_TYPE == PGM_TYPE_PAE \
2075	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
2076
2077	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2078	PX86PML4E pPml4eSrc;
2079	PX86PDPE pPdpeSrc;
2080
2081	pPdpeSrc = pgmGstGetLongModePDPTPtr(&pVM->pgm.s, GCPtrPage, &pPml4eSrc);
2082	Assert(pPml4eSrc);
2083
2084	/*
2085	* Real page fault? (PML4E level)
2086	*/
2087	if ( (uErr & X86_TRAP_PF_RSVD)
2088	\|\| !pPml4eSrc->n.u1Present
2089	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPml4eSrc->n.u1NoExecute)
2090	\|\| (fWriteFault && !pPml4eSrc->n.u1Write && (fUserLevelFault \|\| fWriteProtect))
2091	\|\| (fUserLevelFault && !pPml4eSrc->n.u1User)
2092	)
2093	{
2094	uPageFaultLevel = 0;
2095	goto l_UpperLevelPageFault;
2096	}
2097	Assert(pPdpeSrc);
2098
2099	# else /* PAE */
2100	PX86PDPE pPdpeSrc = pgmGstGetPaePDPEPtr(&pVM->pgm.s, GCPtrPage);
2101	# endif /* PAE */
2102
2103	/*
2104	* Real page fault? (PDPE level)
2105	*/
2106	if ( (uErr & X86_TRAP_PF_RSVD)
2107	\|\| !pPdpeSrc->n.u1Present
2108	# if PGM_GST_TYPE == PGM_TYPE_AMD64 /* NX, r/w, u/s bits in the PDPE are long mode only */
2109	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPdpeSrc->lm.u1NoExecute)
2110	\|\| (fWriteFault && !pPdpeSrc->lm.u1Write && (fUserLevelFault \|\| fWriteProtect))
2111	\|\| (fUserLevelFault && !pPdpeSrc->lm.u1User)
2112	# endif
2113	)
2114	{
2115	uPageFaultLevel = 1;
2116	goto l_UpperLevelPageFault;
2117	}
2118	# endif
2119
2120	/*
2121	* Real page fault? (PDE level)
2122	*/
2123	if ( (uErr & X86_TRAP_PF_RSVD)
2124	\|\| !pPdeSrc->n.u1Present
2125	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2126	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPdeSrc->n.u1NoExecute)
2127	# endif
2128	\|\| (fWriteFault && !pPdeSrc->n.u1Write && (fUserLevelFault \|\| fWriteProtect))
2129	\|\| (fUserLevelFault && !pPdeSrc->n.u1User) )
2130	{
2131	uPageFaultLevel = 2;
2132	goto l_UpperLevelPageFault;
2133	}
2134
2135	/*
2136	* First check the easy case where the page directory has been marked read-only to track
2137	* the dirty bit of an emulated BIG page
2138	*/
2139	if (pPdeSrc->b.u1Size && fBigPagesSupported)
2140	{
2141	/* Mark guest page directory as accessed */
2142	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2143	pPml4eSrc->n.u1Accessed = 1;
2144	pPdpeSrc->lm.u1Accessed = 1;
2145	# endif
2146	pPdeSrc->b.u1Accessed = 1;
2147
2148	/*
2149	* Only write protection page faults are relevant here.
2150	*/
2151	if (fWriteFault)
2152	{
2153	/* Mark guest page directory as dirty (BIG page only). */
2154	pPdeSrc->b.u1Dirty = 1;
2155
2156	if (pPdeDst->n.u1Present && (pPdeDst->u & PGM_PDFLAGS_TRACK_DIRTY))
2157	{
2158	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyPageTrap));
2159
2160	Assert(pPdeSrc->b.u1Write);
2161
2162	pPdeDst->n.u1Write = 1;
2163	pPdeDst->n.u1Accessed = 1;
2164	pPdeDst->au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
2165	PGM_INVL_BIG_PG(GCPtrPage);
2166	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2167	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT;
2168	}
2169	}
2170	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2171	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2172	}
2173	/* else: 4KB page table */
2174
2175	/*
2176	* Map the guest page table.
2177	*/
2178	PGSTPT pPTSrc;
2179	rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & GST_PDE_PG_MASK, &pPTSrc);
2180	if (RT_SUCCESS(rc))
2181	{
2182	/*
2183	* Real page fault?
2184	*/
2185	PGSTPTE pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
2186	const GSTPTE PteSrc = *pPteSrc;
2187	if ( !PteSrc.n.u1Present
2188	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2189	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && PteSrc.n.u1NoExecute)
2190	# endif
2191	\|\| (fWriteFault && !PteSrc.n.u1Write && (fUserLevelFault \|\| fWriteProtect))
2192	\|\| (fUserLevelFault && !PteSrc.n.u1User)
2193	)
2194	{
2195	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyTrackRealPF));
2196	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2197	LogFlow(("CheckPageFault: real page fault at %RGv PteSrc.u=%08x (2)\n", GCPtrPage, PteSrc.u));
2198
2199	/* Check the present bit as the shadow tables can cause different error codes by being out of sync.
2200	* See the 2nd case above as well.
2201	*/
2202	if (pPdeSrc->n.u1Present && pPteSrc->n.u1Present)
2203	TRPMSetErrorCode(pVM, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
2204
2205	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2206	return VINF_EM_RAW_GUEST_TRAP;
2207	}
2208	LogFlow(("CheckPageFault: page fault at %RGv PteSrc.u=%08x\n", GCPtrPage, PteSrc.u));
2209
2210	/*
2211	* Set the accessed bits in the page directory and the page table.
2212	*/
2213	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2214	pPml4eSrc->n.u1Accessed = 1;
2215	pPdpeSrc->lm.u1Accessed = 1;
2216	# endif
2217	pPdeSrc->n.u1Accessed = 1;
2218	pPteSrc->n.u1Accessed = 1;
2219
2220	/*
2221	* Only write protection page faults are relevant here.
2222	*/
2223	if (fWriteFault)
2224	{
2225	/* Write access, so mark guest entry as dirty. */
2226	# ifdef VBOX_WITH_STATISTICS
2227	if (!pPteSrc->n.u1Dirty)
2228	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtiedPage));
2229	else
2230	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,PageAlreadyDirty));
2231	# endif
2232
2233	pPteSrc->n.u1Dirty = 1;
2234
2235	if (pPdeDst->n.u1Present)
2236	{
2237	#ifndef IN_RING0
2238	/* Bail out here as pgmPoolGetPageByHCPhys will return NULL and we'll crash below.
2239	* Our individual shadow handlers will provide more information and force a fatal exit.
2240	*/
2241	if (MMHyperIsInsideArea(pVM, (RTGCPTR)GCPtrPage))
2242	{
2243	LogRel(("CheckPageFault: write to hypervisor region %RGv\n", GCPtrPage));
2244	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2245	return VINF_SUCCESS;
2246	}
2247	#endif
2248	/*
2249	* Map shadow page table.
2250	*/
2251	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, pPdeDst->u & SHW_PDE_PG_MASK);
2252	if (pShwPage)
2253	{
2254	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2255	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2256	if ( pPteDst->n.u1Present /** @todo Optimize accessed bit emulation? */
2257	&& (pPteDst->u & PGM_PTFLAGS_TRACK_DIRTY))
2258	{
2259	LogFlow(("DIRTY page trap addr=%RGv\n", GCPtrPage));
2260	# ifdef VBOX_STRICT
2261	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, pPteSrc->u & GST_PTE_PG_MASK);
2262	if (pPage)
2263	AssertMsg(!PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage),
2264	("Unexpected dirty bit tracking on monitored page %RGv (phys %RGp)!!!!!!\n", GCPtrPage, pPteSrc->u & X86_PTE_PAE_PG_MASK));
2265	# endif
2266	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyPageTrap));
2267
2268	Assert(pPteSrc->n.u1Write);
2269
2270	pPteDst->n.u1Write = 1;
2271	pPteDst->n.u1Dirty = 1;
2272	pPteDst->n.u1Accessed = 1;
2273	pPteDst->au32[0] &= ~PGM_PTFLAGS_TRACK_DIRTY;
2274	PGM_INVL_PG(GCPtrPage);
2275
2276	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2277	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT;
2278	}
2279	}
2280	else
2281	AssertMsgFailed(("pgmPoolGetPageByHCPhys %RGp failed!\n", pPdeDst->u & SHW_PDE_PG_MASK));
2282	}
2283	}
2284	/** @todo Optimize accessed bit emulation? */
2285	# ifdef VBOX_STRICT
2286	/*
2287	* Sanity check.
2288	*/
2289	else if ( !pPteSrc->n.u1Dirty
2290	&& (pPdeSrc->n.u1Write & pPteSrc->n.u1Write)
2291	&& pPdeDst->n.u1Present)
2292	{
2293	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, pPdeDst->u & SHW_PDE_PG_MASK);
2294	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2295	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2296	if ( pPteDst->n.u1Present
2297	&& pPteDst->n.u1Write)
2298	LogFlow(("Writable present page %RGv not marked for dirty bit tracking!!!\n", GCPtrPage));
2299	}
2300	# endif /* VBOX_STRICT */
2301	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2302	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2303	}
2304	AssertRC(rc);
2305	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2306	return rc;
2307
2308
2309	l_UpperLevelPageFault:
2310	/*
2311	* Pagefault detected while checking the PML4E, PDPE or PDE.
2312	* Single exit handler to get rid of duplicate code paths.
2313	*/
2314	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyTrackRealPF));
2315	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2316	Log(("CheckPageFault: real page fault at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2317
2318	if (
2319	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2320	pPml4eSrc->n.u1Present &&
2321	# endif
2322	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
2323	pPdpeSrc->n.u1Present &&
2324	# endif
2325	pPdeSrc->n.u1Present)
2326	{
2327	/* Check the present bit as the shadow tables can cause different error codes by being out of sync. */
2328	if (pPdeSrc->b.u1Size && fBigPagesSupported)
2329	{
2330	TRPMSetErrorCode(pVM, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
2331	}
2332	else
2333	{
2334	/*
2335	* Map the guest page table.
2336	*/
2337	PGSTPT pPTSrc;
2338	rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & GST_PDE_PG_MASK, &pPTSrc);
2339	if (RT_SUCCESS(rc))
2340	{
2341	PGSTPTE pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
2342	const GSTPTE PteSrc = *pPteSrc;
2343	if (pPteSrc->n.u1Present)
2344	TRPMSetErrorCode(pVM, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
2345	}
2346	AssertRC(rc);
2347	}
2348	}
2349	return VINF_EM_RAW_GUEST_TRAP;
2350	}
2351	#endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
2352
2353
2354	/**
2355	* Sync a shadow page table.
2356	*
2357	* The shadow page table is not present. This includes the case where
2358	* there is a conflict with a mapping.
2359	*
2360	* @returns VBox status code.
2361	* @param pVM VM handle.
2362	* @param iPD Page directory index.
2363	* @param pPDSrc Source page directory (i.e. Guest OS page directory).
2364	* Assume this is a temporary mapping.
2365	* @param GCPtrPage GC Pointer of the page that caused the fault
2366	*/
2367	PGM_BTH_DECL(int, SyncPT)(PVM pVM, unsigned iPDSrc, PGSTPD pPDSrc, RTGCPTR GCPtrPage)
2368	{
2369	STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2370	STAM_COUNTER_INC(&pVM->pgm.s.StatSyncPtPD[iPDSrc]);
2371	LogFlow(("SyncPT: GCPtrPage=%RGv\n", GCPtrPage));
2372
2373	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
2374	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
2375	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
2376	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2377	&& PGM_SHW_TYPE != PGM_TYPE_EPT
2378
2379	int rc = VINF_SUCCESS;
2380
2381	/*
2382	* Validate input a little bit.
2383	*/
2384	AssertMsg(iPDSrc == ((GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK), ("iPDSrc=%x GCPtrPage=%RGv\n", iPDSrc, GCPtrPage));
2385	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2386	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
2387	PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(&pVM->pgm.s, GCPtrPage);
2388
2389	/* Fetch the pgm pool shadow descriptor. */
2390	PPGMPOOLPAGE pShwPde = pVM->pgm.s.CTX_SUFF(pShwPageCR3);
2391	Assert(pShwPde);
2392
2393	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2394	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2395	PPGMPOOLPAGE pShwPde;
2396	PX86PDPAE pPDDst;
2397	PSHWPDE pPdeDst;
2398
2399	/* Fetch the pgm pool shadow descriptor. */
2400	rc = pgmShwGetPaePoolPagePD(&pVM->pgm.s, GCPtrPage, &pShwPde);
2401	AssertRCSuccessReturn(rc, rc);
2402	Assert(pShwPde);
2403
2404	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPde);
2405	pPdeDst = &pPDDst->a[iPDDst];
2406
2407	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2408	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
2409	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2410	PX86PDPAE pPDDst;
2411	PX86PDPT pPdptDst;
2412	rc = pgmShwGetLongModePDPtr(pVM, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2413	AssertRCSuccessReturn(rc, rc);
2414	Assert(pPDDst);
2415	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2416	# endif
2417	SHWPDE PdeDst = *pPdeDst;
2418
2419	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2420	/* Fetch the pgm pool shadow descriptor. */
2421	PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(pVM, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
2422	Assert(pShwPde);
2423	# endif
2424
2425	# ifndef PGM_WITHOUT_MAPPINGS
2426	/*
2427	* Check for conflicts.
2428	* GC: In case of a conflict we'll go to Ring-3 and do a full SyncCR3.
2429	* HC: Simply resolve the conflict.
2430	*/
2431	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
2432	{
2433	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
2434	# ifndef IN_RING3
2435	Log(("SyncPT: Conflict at %RGv\n", GCPtrPage));
2436	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2437	return VERR_ADDRESS_CONFLICT;
2438	# else
2439	PPGMMAPPING pMapping = pgmGetMapping(pVM, (RTGCPTR)GCPtrPage);
2440	Assert(pMapping);
2441	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2442	int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2443	# elif PGM_GST_TYPE == PGM_TYPE_PAE
2444	int rc = pgmR3SyncPTResolveConflictPAE(pVM, pMapping, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2445	# else
2446	AssertFailed(); /* can't happen for amd64 */
2447	# endif
2448	if (RT_FAILURE(rc))
2449	{
2450	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2451	return rc;
2452	}
2453	PdeDst = *pPdeDst;
2454	# endif
2455	}
2456	# else /* PGM_WITHOUT_MAPPINGS */
2457	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
2458	# endif /* PGM_WITHOUT_MAPPINGS */
2459	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
2460
2461	# if defined(IN_RC)
2462	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
2463	PGMDynLockHCPage(pVM, (uint8_t *)pPdeDst);
2464	# endif
2465
2466	/*
2467	* Sync page directory entry.
2468	*/
2469	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
2470	if (PdeSrc.n.u1Present)
2471	{
2472	/*
2473	* Allocate & map the page table.
2474	*/
2475	PSHWPT pPTDst;
2476	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2477	const bool fPageTable = !PdeSrc.b.u1Size;
2478	# else
2479	const bool fPageTable = !PdeSrc.b.u1Size \|\| !(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
2480	# endif
2481	PPGMPOOLPAGE pShwPage;
2482	RTGCPHYS GCPhys;
2483	if (fPageTable)
2484	{
2485	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
2486	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2487	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2488	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE / 2);
2489	# endif
2490	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, pShwPde->idx, iPDDst, &pShwPage);
2491	}
2492	else
2493	{
2494	GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
2495	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2496	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
2497	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
2498	# endif
2499	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_BIG, pShwPde->idx, iPDDst, &pShwPage);
2500	}
2501	if (rc == VINF_SUCCESS)
2502	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2503	else if (rc == VINF_PGM_CACHED_PAGE)
2504	{
2505	/*
2506	* The PT was cached, just hook it up.
2507	*/
2508	if (fPageTable)
2509	PdeDst.u = pShwPage->Core.Key
2510	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2511	else
2512	{
2513	PdeDst.u = pShwPage->Core.Key
2514	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2515	/* (see explanation and assumptions further down.) */
2516	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
2517	{
2518	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyPageBig));
2519	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2520	PdeDst.b.u1Write = 0;
2521	}
2522	}
2523	*pPdeDst = PdeDst;
2524	# if defined(IN_RC)
2525	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
2526	# endif
2527	return VINF_SUCCESS;
2528	}
2529	else if (rc == VERR_PGM_POOL_FLUSHED)
2530	{
2531	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
2532	# if defined(IN_RC)
2533	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
2534	# endif
2535	return VINF_PGM_SYNC_CR3;
2536	}
2537	else
2538	AssertMsgFailedReturn(("rc=%Rrc\n", rc), VERR_INTERNAL_ERROR);
2539	PdeDst.u &= X86_PDE_AVL_MASK;
2540	PdeDst.u \|= pShwPage->Core.Key;
2541
2542	/*
2543	* Page directory has been accessed (this is a fault situation, remember).
2544	*/
2545	pPDSrc->a[iPDSrc].n.u1Accessed = 1;
2546	if (fPageTable)
2547	{
2548	/*
2549	* Page table - 4KB.
2550	*
2551	* Sync all or just a few entries depending on PGM_SYNC_N_PAGES.
2552	*/
2553	Log2(("SyncPT: 4K %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx}\n",
2554	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u));
2555	PGSTPT pPTSrc;
2556	rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
2557	if (RT_SUCCESS(rc))
2558	{
2559	/*
2560	* Start by syncing the page directory entry so CSAM's TLB trick works.
2561	*/
2562	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| X86_PDE_AVL_MASK))
2563	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2564	*pPdeDst = PdeDst;
2565	# if defined(IN_RC)
2566	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
2567	# endif
2568
2569	/*
2570	* Directory/page user or supervisor privilege: (same goes for read/write)
2571	*
2572	* Directory Page Combined
2573	* U/S U/S U/S
2574	* 0 0 0
2575	* 0 1 0
2576	* 1 0 0
2577	* 1 1 1
2578	*
2579	* Simple AND operation. Table listed for completeness.
2580	*
2581	*/
2582	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPT4K));
2583	# ifdef PGM_SYNC_N_PAGES
2584	unsigned iPTBase = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2585	unsigned iPTDst = iPTBase;
2586	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2587	if (iPTDst <= PGM_SYNC_NR_PAGES / 2)
2588	iPTDst = 0;
2589	else
2590	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2591	# else /* !PGM_SYNC_N_PAGES */
2592	unsigned iPTDst = 0;
2593	const unsigned iPTDstEnd = RT_ELEMENTS(pPTDst->a);
2594	# endif /* !PGM_SYNC_N_PAGES */
2595	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2596	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2597	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
2598	# else
2599	const unsigned offPTSrc = 0;
2600	# endif
2601	for (; iPTDst < iPTDstEnd; iPTDst++)
2602	{
2603	const unsigned iPTSrc = iPTDst + offPTSrc;
2604	const GSTPTE PteSrc = pPTSrc->a[iPTSrc];
2605
2606	if (PteSrc.n.u1Present) /* we've already cleared it above */
2607	{
2608	# ifndef IN_RING0
2609	/*
2610	* Assuming kernel code will be marked as supervisor - and not as user level
2611	* and executed using a conforming code selector - And marked as readonly.
2612	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
2613	*/
2614	PPGMPAGE pPage;
2615	if ( ((PdeSrc.u & pPTSrc->a[iPTSrc].u) & (X86_PTE_RW \| X86_PTE_US))
2616	\|\| !CSAMDoesPageNeedScanning(pVM, (RTRCPTR)((iPDSrc << GST_PD_SHIFT) \| (iPTSrc << PAGE_SHIFT)))
2617	\|\| ( (pPage = pgmPhysGetPage(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK))
2618	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2619	)
2620	# endif
2621	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2622	Log2(("SyncPT: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s dst.raw=%08llx iPTSrc=%x PdeSrc.u=%x physpte=%RGp\n",
2623	(RTGCPTR)((iPDSrc << GST_PD_SHIFT) \| (iPTSrc << PAGE_SHIFT)),
2624	PteSrc.n.u1Present,
2625	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2626	PteSrc.n.u1User & PdeSrc.n.u1User,
2627	(uint64_t)PteSrc.u,
2628	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : "", pPTDst->a[iPTDst].u, iPTSrc, PdeSrc.au32[0],
2629	(RTGCPHYS)((PdeSrc.u & GST_PDE_PG_MASK) + iPTSrc*sizeof(PteSrc)) ));
2630	}
2631	} /* for PTEs */
2632	}
2633	}
2634	else
2635	{
2636	/*
2637	* Big page - 2/4MB.
2638	*
2639	* We'll walk the ram range list in parallel and optimize lookups.
2640	* We will only sync on shadow page table at a time.
2641	*/
2642	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPT4M));
2643
2644	/**
2645	* @todo It might be more efficient to sync only a part of the 4MB page (similar to what we do for 4kb PDs).
2646	*/
2647
2648	/*
2649	* Start by syncing the page directory entry.
2650	*/
2651	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| (X86_PDE_AVL_MASK & ~PGM_PDFLAGS_TRACK_DIRTY)))
2652	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2653
2654	/*
2655	* If the page is not flagged as dirty and is writable, then make it read-only
2656	* at PD level, so we can set the dirty bit when the page is modified.
2657	*
2658	* ASSUMES that page access handlers are implemented on page table entry level.
2659	* Thus we will first catch the dirty access and set PDE.D and restart. If
2660	* there is an access handler, we'll trap again and let it work on the problem.
2661	*/
2662	/** @todo move the above stuff to a section in the PGM documentation. */
2663	Assert(!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY));
2664	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
2665	{
2666	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyPageBig));
2667	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2668	PdeDst.b.u1Write = 0;
2669	}
2670	*pPdeDst = PdeDst;
2671	# if defined(IN_RC)
2672	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
2673	# endif
2674
2675	/*
2676	* Fill the shadow page table.
2677	*/
2678	/* Get address and flags from the source PDE. */
2679	SHWPTE PteDstBase;
2680	PteDstBase.u = PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT);
2681
2682	/* Loop thru the entries in the shadow PT. */
2683	const RTGCPTR GCPtr = (GCPtrPage >> SHW_PD_SHIFT) << SHW_PD_SHIFT; NOREF(GCPtr);
2684	Log2(("SyncPT: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} Shw=%RGv GCPhys=%RGp %s\n",
2685	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u, GCPtr,
2686	GCPhys, PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2687	PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
2688	unsigned iPTDst = 0;
2689	while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2690	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
2691	{
2692	/* Advance ram range list. */
2693	while (pRam && GCPhys > pRam->GCPhysLast)
2694	pRam = pRam->CTX_SUFF(pNext);
2695	if (pRam && GCPhys >= pRam->GCPhys)
2696	{
2697	unsigned iHCPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
2698	do
2699	{
2700	/* Make shadow PTE. */
2701	PPGMPAGE pPage = &pRam->aPages[iHCPage];
2702	SHWPTE PteDst;
2703
2704	# ifdef VBOX_WITH_NEW_PHYS_CODE
2705	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
2706	/* Try make the page writable if necessary. */
2707	if ( PteDstBase.n.u1Write
2708	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
2709	&& PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
2710	{
2711	rc = pgmPhysPageMakeWritableUnlocked(pVM, pPage, GCPhys);
2712	AssertRCReturn(rc, rc);
2713	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
2714	break;
2715	}
2716	# endif
2717	# else /* !VBOX_WITH_NEW_PHYS_CODE */
2718	/* Make sure the RAM has already been allocated. */
2719	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC) /** @todo PAGE FLAGS */
2720	{
2721	if (RT_UNLIKELY(!PGM_PAGE_GET_HCPHYS(pPage)))
2722	{
2723	# ifdef IN_RING3
2724	int rc = pgmr3PhysGrowRange(pVM, GCPhys);
2725	# else
2726	int rc = CTXALLMID(VMM, CallHost)(pVM, VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
2727	# endif
2728	if (rc != VINF_SUCCESS)
2729	return rc;
2730	}
2731	}
2732	# endif /* !VBOX_WITH_NEW_PHYS_CODE */
2733
2734	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2735	{
2736	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
2737	{
2738	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage) \| PteDstBase.u;
2739	PteDst.n.u1Write = 0;
2740	}
2741	else
2742	PteDst.u = 0;
2743	}
2744	# ifndef IN_RING0
2745	/*
2746	* Assuming kernel code will be marked as supervisor and not as user level and executed
2747	* using a conforming code selector. Don't check for readonly, as that implies the whole
2748	* 4MB can be code or readonly data. Linux enables write access for its large pages.
2749	*/
2750	else if ( !PdeSrc.n.u1User
2751	&& CSAMDoesPageNeedScanning(pVM, (RTRCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT))))
2752	PteDst.u = 0;
2753	# endif
2754	else
2755	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage) \| PteDstBase.u;
2756
2757	# ifdef VBOX_WITH_NEW_PHYS_CODE
2758	/* Only map writable pages writable. */
2759	if ( PteDst.n.u1Write
2760	&& PteDst.n.u1Present
2761	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
2762	{
2763	PteDst.n.u1Write = 0; /** @todo this isn't quite working yet... */
2764	Log3(("SyncPT: write-protecting %RGp pPage=%R[pgmpage] at %RGv\n", GCPhys, pPage, (RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT))));
2765	}
2766	# endif
2767
2768	# ifdef PGMPOOL_WITH_USER_TRACKING
2769	if (PteDst.n.u1Present)
2770	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
2771	# endif
2772	/* commit it */
2773	pPTDst->a[iPTDst] = PteDst;
2774	Log4(("SyncPT: BIG %RGv PteDst:{P=%d RW=%d U=%d raw=%08llx}%s\n",
2775	(RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT)), PteDst.n.u1Present, PteDst.n.u1Write, PteDst.n.u1User, (uint64_t)PteDst.u,
2776	PteDst.u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2777
2778	/* advance */
2779	GCPhys += PAGE_SIZE;
2780	iHCPage++;
2781	iPTDst++;
2782	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2783	&& GCPhys <= pRam->GCPhysLast);
2784	}
2785	else if (pRam)
2786	{
2787	Log(("Invalid pages at %RGp\n", GCPhys));
2788	do
2789	{
2790	pPTDst->a[iPTDst].u = 0; /* MMIO or invalid page, we must handle them manually. */
2791	GCPhys += PAGE_SIZE;
2792	iPTDst++;
2793	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2794	&& GCPhys < pRam->GCPhys);
2795	}
2796	else
2797	{
2798	Log(("Invalid pages at %RGp (2)\n", GCPhys));
2799	for ( ; iPTDst < RT_ELEMENTS(pPTDst->a); iPTDst++)
2800	pPTDst->a[iPTDst].u = 0; /* MMIO or invalid page, we must handle them manually. */
2801	}
2802	} /* while more PTEs */
2803	} /* 4KB / 4MB */
2804	}
2805	else
2806	AssertRelease(!PdeDst.n.u1Present);
2807
2808	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2809	if (RT_FAILURE(rc))
2810	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPTFailed));
2811	return rc;
2812
2813	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2814	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2815	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2816	&& !defined(IN_RC)
2817
2818	/*
2819	* Validate input a little bit.
2820	*/
2821	int rc = VINF_SUCCESS;
2822	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2823	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2824	PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(&pVM->pgm.s, GCPtrPage);
2825
2826	/* Fetch the pgm pool shadow descriptor. */
2827	PPGMPOOLPAGE pShwPde = pVM->pgm.s.CTX_SUFF(pShwPageCR3);
2828	Assert(pShwPde);
2829
2830	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2831	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2832	PPGMPOOLPAGE pShwPde;
2833	PX86PDPAE pPDDst;
2834	PSHWPDE pPdeDst;
2835
2836	/* Fetch the pgm pool shadow descriptor. */
2837	rc = pgmShwGetPaePoolPagePD(&pVM->pgm.s, GCPtrPage, &pShwPde);
2838	AssertRCSuccessReturn(rc, rc);
2839	Assert(pShwPde);
2840
2841	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPde);
2842	pPdeDst = &pPDDst->a[iPDDst];
2843
2844	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2845	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
2846	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2847	PX86PDPAE pPDDst;
2848	PX86PDPT pPdptDst;
2849	rc = pgmShwGetLongModePDPtr(pVM, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2850	AssertRCSuccessReturn(rc, rc);
2851	Assert(pPDDst);
2852	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2853
2854	/* Fetch the pgm pool shadow descriptor. */
2855	PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(pVM, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
2856	Assert(pShwPde);
2857
2858	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
2859	const unsigned iPdpt = (GCPtrPage >> EPT_PDPT_SHIFT) & EPT_PDPT_MASK;
2860	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2861	PEPTPD pPDDst;
2862	PEPTPDPT pPdptDst;
2863
2864	rc = pgmShwGetEPTPDPtr(pVM, GCPtrPage, &pPdptDst, &pPDDst);
2865	if (rc != VINF_SUCCESS)
2866	{
2867	AssertRC(rc);
2868	return rc;
2869	}
2870	Assert(pPDDst);
2871	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2872
2873	/* Fetch the pgm pool shadow descriptor. */
2874	PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(pVM, pPdptDst->a[iPdpt].u & EPT_PDPTE_PG_MASK);
2875	Assert(pShwPde);
2876	# endif
2877	SHWPDE PdeDst = *pPdeDst;
2878
2879	Assert(!(PdeDst.u & PGM_PDFLAGS_MAPPING));
2880	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
2881
2882	GSTPDE PdeSrc;
2883	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
2884	PdeSrc.n.u1Present = 1;
2885	PdeSrc.n.u1Write = 1;
2886	PdeSrc.n.u1Accessed = 1;
2887	PdeSrc.n.u1User = 1;
2888
2889	/*
2890	* Allocate & map the page table.
2891	*/
2892	PSHWPT pPTDst;
2893	PPGMPOOLPAGE pShwPage;
2894	RTGCPHYS GCPhys;
2895
2896	/* Virtual address = physical address */
2897	GCPhys = GCPtrPage & X86_PAGE_4K_BASE_MASK;
2898	rc = pgmPoolAlloc(pVM, GCPhys & ~(RT_BIT_64(SHW_PD_SHIFT) - 1), BTH_PGMPOOLKIND_PT_FOR_PT, pShwPde->idx, iPDDst, &pShwPage);
2899
2900	if ( rc == VINF_SUCCESS
2901	\|\| rc == VINF_PGM_CACHED_PAGE)
2902	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2903	else
2904	AssertMsgFailedReturn(("rc=%Rrc\n", rc), VERR_INTERNAL_ERROR);
2905
2906	PdeDst.u &= X86_PDE_AVL_MASK;
2907	PdeDst.u \|= pShwPage->Core.Key;
2908	PdeDst.n.u1Present = 1;
2909	PdeDst.n.u1Write = 1;
2910	# if PGM_SHW_TYPE == PGM_TYPE_EPT
2911	PdeDst.n.u1Execute = 1;
2912	# else
2913	PdeDst.n.u1User = 1;
2914	PdeDst.n.u1Accessed = 1;
2915	# endif
2916	*pPdeDst = PdeDst;
2917
2918	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, PGM_SYNC_NR_PAGES, 0 /* page not present */);
2919	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2920	return rc;
2921
2922	#else
2923	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_SHW_TYPE, PGM_GST_TYPE));
2924	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2925	return VERR_INTERNAL_ERROR;
2926	#endif
2927	}
2928
2929
2930
2931	/**
2932	* Prefetch a page/set of pages.
2933	*
2934	* Typically used to sync commonly used pages before entering raw mode
2935	* after a CR3 reload.
2936	*
2937	* @returns VBox status code.
2938	* @param pVM VM handle.
2939	* @param GCPtrPage Page to invalidate.
2940	*/
2941	PGM_BTH_DECL(int, PrefetchPage)(PVM pVM, RTGCPTR GCPtrPage)
2942	{
2943	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
2944	&& PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
2945	/*
2946	* Check that all Guest levels thru the PDE are present, getting the
2947	* PD and PDE in the processes.
2948	*/
2949	int rc = VINF_SUCCESS;
2950	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
2951	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2952	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
2953	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(&pVM->pgm.s);
2954	# elif PGM_GST_TYPE == PGM_TYPE_PAE
2955	unsigned iPDSrc;
2956	X86PDPE PdpeSrc;
2957	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtrPage, &iPDSrc, &PdpeSrc);
2958	if (!pPDSrc)
2959	return VINF_SUCCESS; /* not present */
2960	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
2961	unsigned iPDSrc;
2962	PX86PML4E pPml4eSrc;
2963	X86PDPE PdpeSrc;
2964	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
2965	if (!pPDSrc)
2966	return VINF_SUCCESS; /* not present */
2967	# endif
2968	const GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
2969	# else
2970	PGSTPD pPDSrc = NULL;
2971	const unsigned iPDSrc = 0;
2972	GSTPDE PdeSrc;
2973
2974	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
2975	PdeSrc.n.u1Present = 1;
2976	PdeSrc.n.u1Write = 1;
2977	PdeSrc.n.u1Accessed = 1;
2978	PdeSrc.n.u1User = 1;
2979	# endif
2980
2981	if (PdeSrc.n.u1Present && PdeSrc.n.u1Accessed)
2982	{
2983	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2984	const X86PDE PdeDst = pgmShwGet32BitPDE(&pVM->pgm.s, GCPtrPage);
2985	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2986	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2987	PX86PDPAE pPDDst;
2988	X86PDEPAE PdeDst;
2989	# if PGM_GST_TYPE != PGM_TYPE_PAE
2990	X86PDPE PdpeSrc;
2991
2992	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
2993	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
2994	# endif
2995	int rc = pgmShwSyncPaePDPtr(pVM, GCPtrPage, &PdpeSrc, &pPDDst);
2996	if (rc != VINF_SUCCESS)
2997	{
2998	AssertRC(rc);
2999	return rc;
3000	}
3001	Assert(pPDDst);
3002	PdeDst = pPDDst->a[iPDDst];
3003
3004	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3005	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3006	PX86PDPAE pPDDst;
3007	X86PDEPAE PdeDst;
3008
3009	# if PGM_GST_TYPE == PGM_TYPE_PROT
3010	/* AMD-V nested paging */
3011	X86PML4E Pml4eSrc;
3012	X86PDPE PdpeSrc;
3013	PX86PML4E pPml4eSrc = &Pml4eSrc;
3014
3015	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
3016	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_NX \| X86_PML4E_A;
3017	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_NX \| X86_PDPE_A;
3018	# endif
3019
3020	int rc = pgmShwSyncLongModePDPtr(pVM, GCPtrPage, pPml4eSrc, &PdpeSrc, &pPDDst);
3021	if (rc != VINF_SUCCESS)
3022	{
3023	AssertRC(rc);
3024	return rc;
3025	}
3026	Assert(pPDDst);
3027	PdeDst = pPDDst->a[iPDDst];
3028	# endif
3029	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
3030	{
3031	if (!PdeDst.n.u1Present)
3032	/** r=bird: This guy will set the A bit on the PDE, probably harmless. */
3033	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, GCPtrPage);
3034	else
3035	{
3036	/** @note We used to sync PGM_SYNC_NR_PAGES pages, which triggered assertions in CSAM, because
3037	* R/W attributes of nearby pages were reset. Not sure how that could happen. Anyway, it
3038	* makes no sense to prefetch more than one page.
3039	*/
3040	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, 1, 0);
3041	if (RT_SUCCESS(rc))
3042	rc = VINF_SUCCESS;
3043	}
3044	}
3045	}
3046	return rc;
3047
3048	#elif PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3049	return VINF_SUCCESS; /* ignore */
3050	#endif
3051	}
3052
3053
3054
3055
3056	/**
3057	* Syncs a page during a PGMVerifyAccess() call.
3058	*
3059	* @returns VBox status code (informational included).
3060	* @param GCPtrPage The address of the page to sync.
3061	* @param fPage The effective guest page flags.
3062	* @param uErr The trap error code.
3063	*/
3064	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVM pVM, RTGCPTR GCPtrPage, unsigned fPage, unsigned uErr)
3065	{
3066	LogFlow(("VerifyAccessSyncPage: GCPtrPage=%RGv fPage=%#x uErr=%#x\n", GCPtrPage, fPage, uErr));
3067
3068	Assert(!HWACCMIsNestedPagingActive(pVM));
3069	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_TYPE_AMD64) \
3070	&& PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
3071
3072	# ifndef IN_RING0
3073	if (!(fPage & X86_PTE_US))
3074	{
3075	/*
3076	* Mark this page as safe.
3077	*/
3078	/** @todo not correct for pages that contain both code and data!! */
3079	Log(("CSAMMarkPage %RGv; scanned=%d\n", GCPtrPage, true));
3080	CSAMMarkPage(pVM, (RTRCPTR)GCPtrPage, true);
3081	}
3082	# endif
3083
3084	/*
3085	* Get guest PD and index.
3086	*/
3087	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3088	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3089	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
3090	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(&pVM->pgm.s);
3091	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3092	unsigned iPDSrc;
3093	X86PDPE PdpeSrc;
3094	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtrPage, &iPDSrc, &PdpeSrc);
3095
3096	if (pPDSrc)
3097	{
3098	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
3099	return VINF_EM_RAW_GUEST_TRAP;
3100	}
3101	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
3102	unsigned iPDSrc;
3103	PX86PML4E pPml4eSrc;
3104	X86PDPE PdpeSrc;
3105	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3106	if (!pPDSrc)
3107	{
3108	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
3109	return VINF_EM_RAW_GUEST_TRAP;
3110	}
3111	# endif
3112	# else
3113	PGSTPD pPDSrc = NULL;
3114	const unsigned iPDSrc = 0;
3115	# endif
3116	int rc = VINF_SUCCESS;
3117
3118	/*
3119	* First check if the shadow pd is present.
3120	*/
3121	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3122	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(&pVM->pgm.s, GCPtrPage);
3123	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3124	PX86PDEPAE pPdeDst;
3125	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3126	PX86PDPAE pPDDst;
3127	# if PGM_GST_TYPE != PGM_TYPE_PAE
3128	X86PDPE PdpeSrc;
3129
3130	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
3131	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
3132	# endif
3133	rc = pgmShwSyncPaePDPtr(pVM, GCPtrPage, &PdpeSrc, &pPDDst);
3134	if (rc != VINF_SUCCESS)
3135	{
3136	AssertRC(rc);
3137	return rc;
3138	}
3139	Assert(pPDDst);
3140	pPdeDst = &pPDDst->a[iPDDst];
3141
3142	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3143	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3144	PX86PDPAE pPDDst;
3145	PX86PDEPAE pPdeDst;
3146
3147	# if PGM_GST_TYPE == PGM_TYPE_PROT
3148	/* AMD-V nested paging */
3149	X86PML4E Pml4eSrc;
3150	X86PDPE PdpeSrc;
3151	PX86PML4E pPml4eSrc = &Pml4eSrc;
3152
3153	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
3154	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_NX \| X86_PML4E_A;
3155	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_NX \| X86_PDPE_A;
3156	# endif
3157
3158	rc = pgmShwSyncLongModePDPtr(pVM, GCPtrPage, pPml4eSrc, &PdpeSrc, &pPDDst);
3159	if (rc != VINF_SUCCESS)
3160	{
3161	AssertRC(rc);
3162	return rc;
3163	}
3164	Assert(pPDDst);
3165	pPdeDst = &pPDDst->a[iPDDst];
3166	# endif
3167
3168	if (!pPdeDst->n.u1Present)
3169	{
3170	# if defined(IN_RC)
3171	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
3172	PGMDynLockHCPage(pVM, (uint8_t *)pPdeDst);
3173	# endif
3174	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, GCPtrPage);
3175	# if defined(IN_RC)
3176	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
3177	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
3178	# endif
3179	AssertRC(rc);
3180	if (rc != VINF_SUCCESS)
3181	return rc;
3182	}
3183
3184	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3185	/* Check for dirty bit fault */
3186	rc = PGM_BTH_NAME(CheckPageFault)(pVM, uErr, pPdeDst, &pPDSrc->a[iPDSrc], GCPtrPage);
3187	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
3188	Log(("PGMVerifyAccess: success (dirty)\n"));
3189	else
3190	{
3191	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
3192	#else
3193	{
3194	GSTPDE PdeSrc;
3195	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
3196	PdeSrc.n.u1Present = 1;
3197	PdeSrc.n.u1Write = 1;
3198	PdeSrc.n.u1Accessed = 1;
3199	PdeSrc.n.u1User = 1;
3200
3201	#endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
3202	Assert(rc != VINF_EM_RAW_GUEST_TRAP);
3203	if (uErr & X86_TRAP_PF_US)
3204	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncUser));
3205	else /* supervisor */
3206	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
3207
3208	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, 1, 0);
3209	if (RT_SUCCESS(rc))
3210	{
3211	/* Page was successfully synced */
3212	Log2(("PGMVerifyAccess: success (sync)\n"));
3213	rc = VINF_SUCCESS;
3214	}
3215	else
3216	{
3217	Log(("PGMVerifyAccess: access violation for %RGv rc=%d\n", GCPtrPage, rc));
3218	return VINF_EM_RAW_GUEST_TRAP;
3219	}
3220	}
3221	return rc;
3222
3223	#else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
3224
3225	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
3226	return VERR_INTERNAL_ERROR;
3227	#endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
3228	}
3229
3230
3231	#if PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
3232	# if PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
3233	/**
3234	* Figures out which kind of shadow page this guest PDE warrants.
3235	*
3236	* @returns Shadow page kind.
3237	* @param pPdeSrc The guest PDE in question.
3238	* @param cr4 The current guest cr4 value.
3239	*/
3240	DECLINLINE(PGMPOOLKIND) PGM_BTH_NAME(CalcPageKind)(const GSTPDE *pPdeSrc, uint32_t cr4)
3241	{
3242	# if PMG_GST_TYPE == PGM_TYPE_AMD64
3243	if (!pPdeSrc->n.u1Size)
3244	# else
3245	if (!pPdeSrc->n.u1Size \|\| !(cr4 & X86_CR4_PSE))
3246	# endif
3247	return BTH_PGMPOOLKIND_PT_FOR_PT;
3248	//switch (pPdeSrc->u & (X86_PDE4M_RW \| X86_PDE4M_US /\| X86_PDE4M_PAE_NX/))
3249	//{
3250	// case 0:
3251	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RO;
3252	// case X86_PDE4M_RW:
3253	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW;
3254	// case X86_PDE4M_US:
3255	// return BTH_PGMPOOLKIND_PT_FOR_BIG_US;
3256	// case X86_PDE4M_RW \| X86_PDE4M_US:
3257	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_US;
3258	# if 0
3259	// case X86_PDE4M_PAE_NX:
3260	// return BTH_PGMPOOLKIND_PT_FOR_BIG_NX;
3261	// case X86_PDE4M_RW \| X86_PDE4M_PAE_NX:
3262	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_NX;
3263	// case X86_PDE4M_US \| X86_PDE4M_PAE_NX:
3264	// return BTH_PGMPOOLKIND_PT_FOR_BIG_US_NX;
3265	// case X86_PDE4M_RW \| X86_PDE4M_US \| X86_PDE4M_PAE_NX:
3266	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_US_NX;
3267	# endif
3268	return BTH_PGMPOOLKIND_PT_FOR_BIG;
3269	//}
3270	}
3271	# endif
3272	#endif
3273
3274	#undef MY_STAM_COUNTER_INC
3275	#define MY_STAM_COUNTER_INC(a) do { } while (0)
3276
3277
3278	/**
3279	* Syncs the paging hierarchy starting at CR3.
3280	*
3281	* @returns VBox status code, no specials.
3282	* @param pVM The virtual machine.
3283	* @param cr0 Guest context CR0 register
3284	* @param cr3 Guest context CR3 register
3285	* @param cr4 Guest context CR4 register
3286	* @param fGlobal Including global page directories or not
3287	*/
3288	PGM_BTH_DECL(int, SyncCR3)(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
3289	{
3290	if (VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3))
3291	fGlobal = true; /* Change this CR3 reload to be a global one. */
3292
3293	LogFlow(("SyncCR3 %d\n", fGlobal));
3294
3295	#if PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
3296	/*
3297	* Update page access handlers.
3298	* The virtual are always flushed, while the physical are only on demand.
3299	* WARNING: We are incorrectly not doing global flushing on Virtual Handler updates. We'll
3300	* have to look into that later because it will have a bad influence on the performance.
3301	* @note SvL: There's no need for that. Just invalidate the virtual range(s).
3302	* bird: Yes, but that won't work for aliases.
3303	*/
3304	/** @todo this MUST go away. See #1557. */
3305	STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3Handlers), h);
3306	PGM_GST_NAME(HandlerVirtualUpdate)(pVM, cr4);
3307	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3Handlers), h);
3308	#endif
3309
3310	#if PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3311	/*
3312	* Nested / EPT - almost no work.
3313	*/
3314	/** @todo check if this is really necessary; the call does it as well... */
3315	HWACCMFlushTLB(pVM);
3316	return VINF_SUCCESS;
3317
3318	#elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3319	/*
3320	* AMD64 (Shw & Gst) - No need to check all paging levels; we zero
3321	* out the shadow parts when the guest modifies its tables.
3322	*/
3323	return VINF_SUCCESS;
3324
3325	#else /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
3326
3327	# ifdef PGM_WITHOUT_MAPPINGS
3328	Assert(pVM->pgm.s.fMappingsFixed);
3329	return VINF_SUCCESS;
3330	# else
3331	/* Nothing to do when mappings are fixed. */
3332	if (pVM->pgm.s.fMappingsFixed)
3333	return VINF_SUCCESS;
3334
3335	int rc = PGMMapResolveConflicts(pVM);
3336	Assert(rc == VINF_SUCCESS \|\| rc == VINF_PGM_SYNC_CR3);
3337	if (rc == VINF_PGM_SYNC_CR3)
3338	{
3339	LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
3340	return VINF_PGM_SYNC_CR3;
3341	}
3342	# endif
3343	return VINF_SUCCESS;
3344	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
3345	}
3346
3347
3348
3349
3350	#ifdef VBOX_STRICT
3351	#ifdef IN_RC
3352	# undef AssertMsgFailed
3353	# define AssertMsgFailed Log
3354	#endif
3355	#ifdef IN_RING3
3356	# include <VBox/dbgf.h>
3357
3358	/**
3359	* Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
3360	*
3361	* @returns VBox status code (VINF_SUCCESS).
3362	* @param pVM The VM handle.
3363	* @param cr3 The root of the hierarchy.
3364	* @param crr The cr4, only PAE and PSE is currently used.
3365	* @param fLongMode Set if long mode, false if not long mode.
3366	* @param cMaxDepth Number of levels to dump.
3367	* @param pHlp Pointer to the output functions.
3368	*/
3369	__BEGIN_DECLS
3370	VMMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint32_t cr3, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp);
3371	__END_DECLS
3372
3373	#endif
3374
3375	/**
3376	* Checks that the shadow page table is in sync with the guest one.
3377	*
3378	* @returns The number of errors.
3379	* @param pVM The virtual machine.
3380	* @param cr3 Guest context CR3 register
3381	* @param cr4 Guest context CR4 register
3382	* @param GCPtr Where to start. Defaults to 0.
3383	* @param cb How much to check. Defaults to everything.
3384	*/
3385	PGM_BTH_DECL(unsigned, AssertCR3)(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb)
3386	{
3387	#if PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3388	return 0;
3389	#else
3390	unsigned cErrors = 0;
3391
3392	#if PGM_GST_TYPE == PGM_TYPE_PAE
3393	/** @todo currently broken; crashes below somewhere */
3394	AssertFailed();
3395	#endif
3396
3397	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
3398	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3399	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
3400
3401	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3402	bool fBigPagesSupported = true;
3403	# else
3404	bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
3405	# endif
3406	PPGM pPGM = &pVM->pgm.s;
3407	RTGCPHYS GCPhysGst; /* page address derived from the guest page tables. */
3408	RTHCPHYS HCPhysShw; /* page address derived from the shadow page tables. */
3409	# ifndef IN_RING0
3410	RTHCPHYS HCPhys; /* general usage. */
3411	# endif
3412	int rc;
3413
3414	/*
3415	* Check that the Guest CR3 and all its mappings are correct.
3416	*/
3417	AssertMsgReturn(pPGM->GCPhysCR3 == (cr3 & GST_CR3_PAGE_MASK),
3418	("Invalid GCPhysCR3=%RGp cr3=%RGp\n", pPGM->GCPhysCR3, (RTGCPHYS)cr3),
3419	false);
3420	# if !defined(IN_RING0) && PGM_GST_TYPE != PGM_TYPE_AMD64
3421	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3422	rc = PGMShwGetPage(pVM, (RTGCPTR)pPGM->pGst32BitPdRC, NULL, &HCPhysShw);
3423	# else
3424	rc = PGMShwGetPage(pVM, (RTGCPTR)pPGM->pGstPaePdptRC, NULL, &HCPhysShw);
3425	# endif
3426	AssertRCReturn(rc, 1);
3427	HCPhys = NIL_RTHCPHYS;
3428	rc = pgmRamGCPhys2HCPhys(pPGM, cr3 & GST_CR3_PAGE_MASK, &HCPhys);
3429	AssertMsgReturn(HCPhys == HCPhysShw, ("HCPhys=%RHp HCPhyswShw=%RHp (cr3)\n", HCPhys, HCPhysShw), false);
3430	# if PGM_GST_TYPE == PGM_TYPE_32BIT && defined(IN_RING3)
3431	pgmGstGet32bitPDPtr(pPGM);
3432	RTGCPHYS GCPhys;
3433	rc = PGMR3DbgR3Ptr2GCPhys(pVM, pPGM->pGst32BitPdR3, &GCPhys);
3434	AssertRCReturn(rc, 1);
3435	AssertMsgReturn((cr3 & GST_CR3_PAGE_MASK) == GCPhys, ("GCPhys=%RGp cr3=%RGp\n", GCPhys, (RTGCPHYS)cr3), false);
3436	# endif
3437	# endif /* !IN_RING0 */
3438
3439	/*
3440	* Get and check the Shadow CR3.
3441	*/
3442	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3443	unsigned cPDEs = X86_PG_ENTRIES;
3444	unsigned cIncrement = X86_PG_ENTRIES * PAGE_SIZE;
3445	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3446	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3447	unsigned cPDEs = X86_PG_PAE_ENTRIES * 4; /* treat it as a 2048 entry table. */
3448	# else
3449	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3450	# endif
3451	unsigned cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3452	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3453	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3454	unsigned cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3455	# endif
3456	if (cb != ~(RTGCPTR)0)
3457	cPDEs = RT_MIN(cb >> SHW_PD_SHIFT, 1);
3458
3459	/** @todo call the other two PGMAssert() functions. /
3460
3461	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
3462	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3463	# endif
3464
3465	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3466	unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3467
3468	for (; iPml4 < X86_PG_PAE_ENTRIES; iPml4++)
3469	{
3470	PPGMPOOLPAGE pShwPdpt = NULL;
3471	PX86PML4E pPml4eSrc;
3472	PX86PML4E pPml4eDst;
3473	RTGCPHYS GCPhysPdptSrc;
3474
3475	pPml4eSrc = pgmGstGetLongModePML4EPtr(&pVM->pgm.s, iPml4);
3476	pPml4eDst = pgmShwGetLongModePML4EPtr(&pVM->pgm.s, iPml4);
3477
3478	/* Fetch the pgm pool shadow descriptor if the shadow pml4e is present. */
3479	if (!pPml4eDst->n.u1Present)
3480	{
3481	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3482	continue;
3483	}
3484
3485	pShwPdpt = pgmPoolGetPage(pPool, pPml4eDst->u & X86_PML4E_PG_MASK);
3486	GCPhysPdptSrc = pPml4eSrc->u & X86_PML4E_PG_MASK_FULL;
3487
3488	if (pPml4eSrc->n.u1Present != pPml4eDst->n.u1Present)
3489	{
3490	AssertMsgFailed(("Present bit doesn't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3491	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3492	cErrors++;
3493	continue;
3494	}
3495
3496	if (GCPhysPdptSrc != pShwPdpt->GCPhys)
3497	{
3498	AssertMsgFailed(("Physical address doesn't match! iPml4 %d pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, pPml4eDst->u, pPml4eSrc->u, pShwPdpt->GCPhys, GCPhysPdptSrc));
3499	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3500	cErrors++;
3501	continue;
3502	}
3503
3504	if ( pPml4eDst->n.u1User != pPml4eSrc->n.u1User
3505	\|\| pPml4eDst->n.u1Write != pPml4eSrc->n.u1Write
3506	\|\| pPml4eDst->n.u1NoExecute != pPml4eSrc->n.u1NoExecute)
3507	{
3508	AssertMsgFailed(("User/Write/NoExec bits don't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3509	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3510	cErrors++;
3511	continue;
3512	}
3513	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
3514	{
3515	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
3516
3517	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
3518	/*
3519	* Check the PDPTEs too.
3520	*/
3521	unsigned iPdpt = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
3522
3523	for (;iPdpt <= SHW_PDPT_MASK; iPdpt++)
3524	{
3525	unsigned iPDSrc;
3526	PPGMPOOLPAGE pShwPde = NULL;
3527	PX86PDPE pPdpeDst;
3528	RTGCPHYS GCPhysPdeSrc;
3529	# if PGM_GST_TYPE == PGM_TYPE_PAE
3530	X86PDPE PdpeSrc;
3531	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtr, &iPDSrc, &PdpeSrc);
3532	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(&pVM->pgm.s);
3533	# else
3534	PX86PML4E pPml4eSrc;
3535	X86PDPE PdpeSrc;
3536	PX86PDPT pPdptDst;
3537	PX86PDPAE pPDDst;
3538	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, GCPtr, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3539
3540	rc = pgmShwGetLongModePDPtr(pVM, GCPtr, NULL, &pPdptDst, &pPDDst);
3541	if (rc != VINF_SUCCESS)
3542	{
3543	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
3544	GCPtr += 512 * _2M;
3545	continue; /* next PDPTE */
3546	}
3547	Assert(pPDDst);
3548	# endif
3549	Assert(iPDSrc == 0);
3550
3551	pPdpeDst = &pPdptDst->a[iPdpt];
3552
3553	if (!pPdpeDst->n.u1Present)
3554	{
3555	GCPtr += 512 * _2M;
3556	continue; /* next PDPTE */
3557	}
3558
3559	pShwPde = pgmPoolGetPage(pPool, pPdpeDst->u & X86_PDPE_PG_MASK);
3560	GCPhysPdeSrc = PdpeSrc.u & X86_PDPE_PG_MASK;
3561
3562	if (pPdpeDst->n.u1Present != PdpeSrc.n.u1Present)
3563	{
3564	AssertMsgFailed(("Present bit doesn't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3565	GCPtr += 512 * _2M;
3566	cErrors++;
3567	continue;
3568	}
3569
3570	if (GCPhysPdeSrc != pShwPde->GCPhys)
3571	{
3572	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3573	AssertMsgFailed(("Physical address doesn't match! iPml4 %d iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3574	# else
3575	AssertMsgFailed(("Physical address doesn't match! iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3576	# endif
3577	GCPtr += 512 * _2M;
3578	cErrors++;
3579	continue;
3580	}
3581
3582	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3583	if ( pPdpeDst->lm.u1User != PdpeSrc.lm.u1User
3584	\|\| pPdpeDst->lm.u1Write != PdpeSrc.lm.u1Write
3585	\|\| pPdpeDst->lm.u1NoExecute != PdpeSrc.lm.u1NoExecute)
3586	{
3587	AssertMsgFailed(("User/Write/NoExec bits don't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3588	GCPtr += 512 * _2M;
3589	cErrors++;
3590	continue;
3591	}
3592	# endif
3593
3594	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
3595	{
3596	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
3597	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3598	GSTPD const *pPDSrc = pgmGstGet32bitPDPtr(&pVM->pgm.s);
3599	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3600	PCX86PD pPDDst = pgmShwGet32BitPDPtr(&pVM->pgm.s);
3601	# endif
3602	# endif /* PGM_GST_TYPE == PGM_TYPE_32BIT */
3603	/*
3604	* Iterate the shadow page directory.
3605	*/
3606	GCPtr = (GCPtr >> SHW_PD_SHIFT) << SHW_PD_SHIFT;
3607	unsigned iPDDst = (GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK;
3608
3609	for (;
3610	iPDDst < cPDEs;
3611	iPDDst++, GCPtr += cIncrement)
3612	{
3613	# if PGM_SHW_TYPE == PGM_TYPE_PAE
3614	const SHWPDE PdeDst = *pgmShwGetPaePDEPtr(pPGM, GCPtr);
3615	# else
3616	const SHWPDE PdeDst = pPDDst->a[iPDDst];
3617	# endif
3618	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
3619	{
3620	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
3621	if ((PdeDst.u & X86_PDE_AVL_MASK) != PGM_PDFLAGS_MAPPING)
3622	{
3623	AssertMsgFailed(("Mapping shall only have PGM_PDFLAGS_MAPPING set! PdeDst.u=%#RX64\n", (uint64_t)PdeDst.u));
3624	cErrors++;
3625	continue;
3626	}
3627	}
3628	else if ( (PdeDst.u & X86_PDE_P)
3629	\|\| ((PdeDst.u & (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY)) == (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY))
3630	)
3631	{
3632	HCPhysShw = PdeDst.u & SHW_PDE_PG_MASK;
3633	PPGMPOOLPAGE pPoolPage = pgmPoolGetPageByHCPhys(pVM, HCPhysShw);
3634	if (!pPoolPage)
3635	{
3636	AssertMsgFailed(("Invalid page table address %RHp at %RGv! PdeDst=%#RX64\n",
3637	HCPhysShw, GCPtr, (uint64_t)PdeDst.u));
3638	cErrors++;
3639	continue;
3640	}
3641	const SHWPT pPTDst = (const SHWPT )PGMPOOL_PAGE_2_PTR(pVM, pPoolPage);
3642
3643	if (PdeDst.u & (X86_PDE4M_PWT \| X86_PDE4M_PCD))
3644	{
3645	AssertMsgFailed(("PDE flags PWT and/or PCD is set at %RGv! These flags are not virtualized! PdeDst=%#RX64\n",
3646	GCPtr, (uint64_t)PdeDst.u));
3647	cErrors++;
3648	}
3649
3650	if (PdeDst.u & (X86_PDE4M_G \| X86_PDE4M_D))
3651	{
3652	AssertMsgFailed(("4K PDE reserved flags at %RGv! PdeDst=%#RX64\n",
3653	GCPtr, (uint64_t)PdeDst.u));
3654	cErrors++;
3655	}
3656
3657	const GSTPDE PdeSrc = pPDSrc->a[(iPDDst >> (GST_PD_SHIFT - SHW_PD_SHIFT)) & GST_PD_MASK];
3658	if (!PdeSrc.n.u1Present)
3659	{
3660	AssertMsgFailed(("Guest PDE at %RGv is not present! PdeDst=%#RX64 PdeSrc=%#RX64\n",
3661	GCPtr, (uint64_t)PdeDst.u, (uint64_t)PdeSrc.u));
3662	cErrors++;
3663	continue;
3664	}
3665
3666	if ( !PdeSrc.b.u1Size
3667	\|\| !fBigPagesSupported)
3668	{
3669	GCPhysGst = PdeSrc.u & GST_PDE_PG_MASK;
3670	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3671	GCPhysGst \|= (iPDDst & 1) * (PAGE_SIZE / 2);
3672	# endif
3673	}
3674	else
3675	{
3676	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3677	if (PdeSrc.u & X86_PDE4M_PG_HIGH_MASK)
3678	{
3679	AssertMsgFailed(("Guest PDE at %RGv is using PSE36 or similar! PdeSrc=%#RX64\n",
3680	GCPtr, (uint64_t)PdeSrc.u));
3681	cErrors++;
3682	continue;
3683	}
3684	# endif
3685	GCPhysGst = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
3686	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3687	GCPhysGst \|= GCPtr & RT_BIT(X86_PAGE_2M_SHIFT);
3688	# endif
3689	}
3690
3691	if ( pPoolPage->enmKind
3692	!= (!PdeSrc.b.u1Size \|\| !fBigPagesSupported ? BTH_PGMPOOLKIND_PT_FOR_PT : BTH_PGMPOOLKIND_PT_FOR_BIG))
3693	{
3694	AssertMsgFailed(("Invalid shadow page table kind %d at %RGv! PdeSrc=%#RX64\n",
3695	pPoolPage->enmKind, GCPtr, (uint64_t)PdeSrc.u));
3696	cErrors++;
3697	}
3698
3699	PPGMPAGE pPhysPage = pgmPhysGetPage(pPGM, GCPhysGst);
3700	if (!pPhysPage)
3701	{
3702	AssertMsgFailed(("Cannot find guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
3703	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3704	cErrors++;
3705	continue;
3706	}
3707
3708	if (GCPhysGst != pPoolPage->GCPhys)
3709	{
3710	AssertMsgFailed(("GCPhysGst=%RGp != pPage->GCPhys=%RGp at %RGv\n",
3711	GCPhysGst, pPoolPage->GCPhys, GCPtr));
3712	cErrors++;
3713	continue;
3714	}
3715
3716	if ( !PdeSrc.b.u1Size
3717	\|\| !fBigPagesSupported)
3718	{
3719	/*
3720	* Page Table.
3721	*/
3722	const GSTPT *pPTSrc;
3723	rc = PGM_GCPHYS_2_PTR(pVM, GCPhysGst & ~(RTGCPHYS)(PAGE_SIZE - 1), &pPTSrc);
3724	if (RT_FAILURE(rc))
3725	{
3726	AssertMsgFailed(("Cannot map/convert guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
3727	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3728	cErrors++;
3729	continue;
3730	}
3731	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/))
3732	!= (PdeDst.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/)))
3733	{
3734	/// @todo We get here a lot on out-of-sync CR3 entries. The access handler should zap them to avoid false alarms here!
3735	// (This problem will go away when/if we shadow multiple CR3s.)
3736	AssertMsgFailed(("4K PDE flags mismatch at %RGv! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3737	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3738	cErrors++;
3739	continue;
3740	}
3741	if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
3742	{
3743	AssertMsgFailed(("4K PDEs cannot have PGM_PDFLAGS_TRACK_DIRTY set! GCPtr=%RGv PdeDst=%#RX64\n",
3744	GCPtr, (uint64_t)PdeDst.u));
3745	cErrors++;
3746	continue;
3747	}
3748
3749	/* iterate the page table. */
3750	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3751	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
3752	const unsigned offPTSrc = ((GCPtr >> SHW_PD_SHIFT) & 1) * 512;
3753	# else
3754	const unsigned offPTSrc = 0;
3755	# endif
3756	for (unsigned iPT = 0, off = 0;
3757	iPT < RT_ELEMENTS(pPTDst->a);
3758	iPT++, off += PAGE_SIZE)
3759	{
3760	const SHWPTE PteDst = pPTDst->a[iPT];
3761
3762	/* skip not-present entries. */
3763	if (!(PteDst.u & (X86_PTE_P \| PGM_PTFLAGS_TRACK_DIRTY))) /** @todo deal with ALL handlers and CSAM !P pages! */
3764	continue;
3765	Assert(PteDst.n.u1Present);
3766
3767	const GSTPTE PteSrc = pPTSrc->a[iPT + offPTSrc];
3768	if (!PteSrc.n.u1Present)
3769	{
3770	# ifdef IN_RING3
3771	PGMAssertHandlerAndFlagsInSync(pVM);
3772	PGMR3DumpHierarchyGC(pVM, cr3, cr4, (PdeSrc.u & GST_PDE_PG_MASK));
3773	# endif
3774	AssertMsgFailed(("Out of sync (!P) PTE at %RGv! PteSrc=%#RX64 PteDst=%#RX64 pPTSrc=%RGv iPTSrc=%x PdeSrc=%x physpte=%RGp\n",
3775	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u, pPTSrc, iPT + offPTSrc, PdeSrc.au32[0],
3776	(PdeSrc.u & GST_PDE_PG_MASK) + (iPT + offPTSrc)*sizeof(PteSrc)));
3777	cErrors++;
3778	continue;
3779	}
3780
3781	uint64_t fIgnoreFlags = GST_PTE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_G \| X86_PTE_D \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT;
3782	# if 1 /** @todo sync accessed bit properly... */
3783	fIgnoreFlags \|= X86_PTE_A;
3784	# endif
3785
3786	/* match the physical addresses */
3787	HCPhysShw = PteDst.u & SHW_PTE_PG_MASK;
3788	GCPhysGst = PteSrc.u & GST_PTE_PG_MASK;
3789
3790	# ifdef IN_RING3
3791	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
3792	if (RT_FAILURE(rc))
3793	{
3794	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
3795	{
3796	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
3797	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3798	cErrors++;
3799	continue;
3800	}
3801	}
3802	else if (HCPhysShw != (HCPhys & SHW_PTE_PG_MASK))
3803	{
3804	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
3805	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3806	cErrors++;
3807	continue;
3808	}
3809	# endif
3810
3811	pPhysPage = pgmPhysGetPage(pPGM, GCPhysGst);
3812	if (!pPhysPage)
3813	{
3814	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
3815	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
3816	{
3817	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
3818	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3819	cErrors++;
3820	continue;
3821	}
3822	# endif
3823	if (PteDst.n.u1Write)
3824	{
3825	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
3826	GCPtr + off, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3827	cErrors++;
3828	}
3829	fIgnoreFlags \|= X86_PTE_RW;
3830	}
3831	else if (HCPhysShw != PGM_PAGE_GET_HCPHYS(pPhysPage))
3832	{
3833	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp pPhysPage:%R[pgmpage] GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
3834	GCPtr + off, HCPhysShw, pPhysPage, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3835	cErrors++;
3836	continue;
3837	}
3838
3839	/* flags */
3840	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
3841	{
3842	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
3843	{
3844	if (PteDst.n.u1Write)
3845	{
3846	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! pPhysPage=%R[pgmpage] PteSrc=%#RX64 PteDst=%#RX64\n",
3847	GCPtr + off, pPhysPage, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3848	cErrors++;
3849	continue;
3850	}
3851	fIgnoreFlags \|= X86_PTE_RW;
3852	}
3853	else
3854	{
3855	if (PteDst.n.u1Present)
3856	{
3857	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! pPhysPage=%R[pgmpage] PteSrc=%#RX64 PteDst=%#RX64\n",
3858	GCPtr + off, pPhysPage, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3859	cErrors++;
3860	continue;
3861	}
3862	fIgnoreFlags \|= X86_PTE_P;
3863	}
3864	}
3865	else
3866	{
3867	if (!PteSrc.n.u1Dirty && PteSrc.n.u1Write)
3868	{
3869	if (PteDst.n.u1Write)
3870	{
3871	AssertMsgFailed(("!DIRTY page at %RGv is writable! PteSrc=%#RX64 PteDst=%#RX64\n",
3872	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3873	cErrors++;
3874	continue;
3875	}
3876	if (!(PteDst.u & PGM_PTFLAGS_TRACK_DIRTY))
3877	{
3878	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
3879	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3880	cErrors++;
3881	continue;
3882	}
3883	if (PteDst.n.u1Dirty)
3884	{
3885	AssertMsgFailed(("!DIRTY page at %RGv is marked DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
3886	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3887	cErrors++;
3888	}
3889	# if 0 /** @todo sync access bit properly... */
3890	if (PteDst.n.u1Accessed != PteSrc.n.u1Accessed)
3891	{
3892	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
3893	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3894	cErrors++;
3895	}
3896	fIgnoreFlags \|= X86_PTE_RW;
3897	# else
3898	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
3899	# endif
3900	}
3901	else if (PteDst.u & PGM_PTFLAGS_TRACK_DIRTY)
3902	{
3903	/* access bit emulation (not implemented). */
3904	if (PteSrc.n.u1Accessed \|\| PteDst.n.u1Present)
3905	{
3906	AssertMsgFailed(("PGM_PTFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PteSrc=%#RX64 PteDst=%#RX64\n",
3907	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3908	cErrors++;
3909	continue;
3910	}
3911	if (!PteDst.n.u1Accessed)
3912	{
3913	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PteSrc=%#RX64 PteDst=%#RX64\n",
3914	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3915	cErrors++;
3916	}
3917	fIgnoreFlags \|= X86_PTE_P;
3918	}
3919	# ifdef DEBUG_sandervl
3920	fIgnoreFlags \|= X86_PTE_D \| X86_PTE_A;
3921	# endif
3922	}
3923
3924	if ( (PteSrc.u & ~fIgnoreFlags) != (PteDst.u & ~fIgnoreFlags)
3925	&& (PteSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (PteDst.u & ~fIgnoreFlags)
3926	)
3927	{
3928	AssertMsgFailed(("Flags mismatch at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PteSrc=%#RX64 PteDst=%#RX64\n",
3929	GCPtr + off, (uint64_t)PteSrc.u & ~fIgnoreFlags, (uint64_t)PteDst.u & ~fIgnoreFlags,
3930	fIgnoreFlags, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3931	cErrors++;
3932	continue;
3933	}
3934	} /* foreach PTE */
3935	}
3936	else
3937	{
3938	/*
3939	* Big Page.
3940	*/
3941	uint64_t fIgnoreFlags = X86_PDE_AVL_MASK \| GST_PDE_PG_MASK \| X86_PDE4M_G \| X86_PDE4M_D \| X86_PDE4M_PS \| X86_PDE4M_PWT \| X86_PDE4M_PCD;
3942	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
3943	{
3944	if (PdeDst.n.u1Write)
3945	{
3946	AssertMsgFailed(("!DIRTY page at %RGv is writable! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3947	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3948	cErrors++;
3949	continue;
3950	}
3951	if (!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY))
3952	{
3953	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
3954	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3955	cErrors++;
3956	continue;
3957	}
3958	# if 0 /** @todo sync access bit properly... */
3959	if (PdeDst.n.u1Accessed != PdeSrc.b.u1Accessed)
3960	{
3961	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
3962	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3963	cErrors++;
3964	}
3965	fIgnoreFlags \|= X86_PTE_RW;
3966	# else
3967	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
3968	# endif
3969	}
3970	else if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
3971	{
3972	/* access bit emulation (not implemented). */
3973	if (PdeSrc.b.u1Accessed \|\| PdeDst.n.u1Present)
3974	{
3975	AssertMsgFailed(("PGM_PDFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3976	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3977	cErrors++;
3978	continue;
3979	}
3980	if (!PdeDst.n.u1Accessed)
3981	{
3982	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3983	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3984	cErrors++;
3985	}
3986	fIgnoreFlags \|= X86_PTE_P;
3987	}
3988
3989	if ((PdeSrc.u & ~fIgnoreFlags) != (PdeDst.u & ~fIgnoreFlags))
3990	{
3991	AssertMsgFailed(("Flags mismatch (B) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PdeDst=%#RX64\n",
3992	GCPtr, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PdeDst.u & ~fIgnoreFlags,
3993	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3994	cErrors++;
3995	}
3996
3997	/* iterate the page table. */
3998	for (unsigned iPT = 0, off = 0;
3999	iPT < RT_ELEMENTS(pPTDst->a);
4000	iPT++, off += PAGE_SIZE, GCPhysGst += PAGE_SIZE)
4001	{
4002	const SHWPTE PteDst = pPTDst->a[iPT];
4003
4004	if (PteDst.u & PGM_PTFLAGS_TRACK_DIRTY)
4005	{
4006	AssertMsgFailed(("The PTE at %RGv emulating a 2/4M page is marked TRACK_DIRTY! PdeSrc=%#RX64 PteDst=%#RX64\n",
4007	GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4008	cErrors++;
4009	}
4010
4011	/* skip not-present entries. */
4012	if (!PteDst.n.u1Present) /** @todo deal with ALL handlers and CSAM !P pages! */
4013	continue;
4014
4015	fIgnoreFlags = X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT \| X86_PTE_D \| X86_PTE_A \| X86_PTE_G \| X86_PTE_PAE_NX;
4016
4017	/* match the physical addresses */
4018	HCPhysShw = PteDst.u & X86_PTE_PAE_PG_MASK;
4019
4020	# ifdef IN_RING3
4021	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
4022	if (RT_FAILURE(rc))
4023	{
4024	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
4025	{
4026	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4027	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4028	cErrors++;
4029	}
4030	}
4031	else if (HCPhysShw != (HCPhys & X86_PTE_PAE_PG_MASK))
4032	{
4033	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4034	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4035	cErrors++;
4036	continue;
4037	}
4038	# endif
4039	pPhysPage = pgmPhysGetPage(pPGM, GCPhysGst);
4040	if (!pPhysPage)
4041	{
4042	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
4043	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
4044	{
4045	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4046	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4047	cErrors++;
4048	continue;
4049	}
4050	# endif
4051	if (PteDst.n.u1Write)
4052	{
4053	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4054	GCPtr + off, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4055	cErrors++;
4056	}
4057	fIgnoreFlags \|= X86_PTE_RW;
4058	}
4059	else if (HCPhysShw != PGM_PAGE_GET_HCPHYS(pPhysPage))
4060	{
4061	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp pPhysPage=%R[pgmpage] GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4062	GCPtr + off, HCPhysShw, pPhysPage, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4063	cErrors++;
4064	continue;
4065	}
4066
4067	/* flags */
4068	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
4069	{
4070	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
4071	{
4072	if (PGM_PAGE_GET_HNDL_PHYS_STATE(pPhysPage) != PGM_PAGE_HNDL_PHYS_STATE_DISABLED)
4073	{
4074	if (PteDst.n.u1Write)
4075	{
4076	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! pPhysPage=%R[pgmpage] PdeSrc=%#RX64 PteDst=%#RX64\n",
4077	GCPtr + off, pPhysPage, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4078	cErrors++;
4079	continue;
4080	}
4081	fIgnoreFlags \|= X86_PTE_RW;
4082	}
4083	}
4084	else
4085	{
4086	if (PteDst.n.u1Present)
4087	{
4088	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! pPhysPage=%R[pgmpage] PdeSrc=%#RX64 PteDst=%#RX64\n",
4089	GCPtr + off, pPhysPage, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4090	cErrors++;
4091	continue;
4092	}
4093	fIgnoreFlags \|= X86_PTE_P;
4094	}
4095	}
4096
4097	if ( (PdeSrc.u & ~fIgnoreFlags) != (PteDst.u & ~fIgnoreFlags)
4098	&& (PdeSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (PteDst.u & ~fIgnoreFlags) /* lazy phys handler dereg. */
4099	)
4100	{
4101	AssertMsgFailed(("Flags mismatch (BT) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PteDst=%#RX64\n",
4102	GCPtr + off, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PteDst.u & ~fIgnoreFlags,
4103	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4104	cErrors++;
4105	continue;
4106	}
4107	} /* for each PTE */
4108	}
4109	}
4110	/* not present */
4111
4112	} /* for each PDE */
4113
4114	} /* for each PDPTE */
4115
4116	} /* for each PML4E */
4117
4118	# ifdef DEBUG
4119	if (cErrors)
4120	LogFlow(("AssertCR3: cErrors=%d\n", cErrors));
4121	# endif
4122
4123	#endif /* GST == 32BIT, PAE or AMD64 */
4124	return cErrors;
4125
4126	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT */
4127	}
4128	#endif /* VBOX_STRICT */
4129
4130
4131	/**
4132	* Sets up the CR3 for shadow paging
4133	*
4134	* @returns Strict VBox status code.
4135	* @retval VINF_SUCCESS.
4136	*
4137	* @param pVM VM handle.
4138	* @param GCPhysCR3 The physical address in the CR3 register.
4139	*/
4140	PGM_BTH_DECL(int, MapCR3)(PVM pVM, RTGCPHYS GCPhysCR3)
4141	{
4142	/* Update guest paging info. */
4143	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
4144	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
4145	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
4146
4147	LogFlow(("MapCR3: %RGp\n", GCPhysCR3));
4148
4149	/*
4150	* Map the page CR3 points at.
4151	*/
4152	RTHCPTR HCPtrGuestCR3;
4153	RTHCPHYS HCPhysGuestCR3;
4154	# ifdef VBOX_WITH_NEW_PHYS_CODE
4155	pgmLock(pVM);
4156	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, GCPhysCR3);
4157	AssertReturn(pPage, VERR_INTERNAL_ERROR_2);
4158	HCPhysGuestCR3 = PGM_PAGE_GET_HCPHYS(pPage);
4159	/** @todo this needs some reworking wrt. locking. */
4160	# if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
4161	HCPtrGuestCR3 = NIL_RTHCPTR;
4162	int rc = VINF_SUCCESS;
4163	# else
4164	int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhysCR3 & GST_CR3_PAGE_MASK, (void **)&HCPtrGuestCR3);
4165	# endif
4166	pgmUnlock(pVM);
4167	# else /* !VBOX_WITH_NEW_PHYS_CODE */
4168	int rc = pgmRamGCPhys2HCPtrAndHCPhys(&pVM->pgm.s, GCPhysCR3 & GST_CR3_PAGE_MASK, &HCPtrGuestCR3, &HCPhysGuestCR3);
4169	# endif /* !VBOX_WITH_NEW_PHYS_CODE */
4170	if (RT_SUCCESS(rc))
4171	{
4172	rc = PGMMap(pVM, (RTGCPTR)pVM->pgm.s.GCPtrCR3Mapping, HCPhysGuestCR3, PAGE_SIZE, 0);
4173	if (RT_SUCCESS(rc))
4174	{
4175	# ifdef IN_RC
4176	PGM_INVL_PG(pVM->pgm.s.GCPtrCR3Mapping);
4177	# endif
4178	# if PGM_GST_TYPE == PGM_TYPE_32BIT
4179	pVM->pgm.s.pGst32BitPdR3 = (R3PTRTYPE(PX86PD))HCPtrGuestCR3;
4180	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4181	pVM->pgm.s.pGst32BitPdR0 = (R0PTRTYPE(PX86PD))HCPtrGuestCR3;
4182	# endif
4183	pVM->pgm.s.pGst32BitPdRC = (RCPTRTYPE(PX86PD))pVM->pgm.s.GCPtrCR3Mapping;
4184
4185	# elif PGM_GST_TYPE == PGM_TYPE_PAE
4186	unsigned off = GCPhysCR3 & GST_CR3_PAGE_MASK & PAGE_OFFSET_MASK;
4187	pVM->pgm.s.pGstPaePdptR3 = (R3PTRTYPE(PX86PDPT))HCPtrGuestCR3;
4188	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4189	pVM->pgm.s.pGstPaePdptR0 = (R0PTRTYPE(PX86PDPT))HCPtrGuestCR3;
4190	# endif
4191	pVM->pgm.s.pGstPaePdptRC = (RCPTRTYPE(PX86PDPT))((RCPTRTYPE(uint8_t *))pVM->pgm.s.GCPtrCR3Mapping + off);
4192	Log(("Cached mapping %RRv\n", pVM->pgm.s.pGstPaePdptRC));
4193
4194	/*
4195	* Map the 4 PDs too.
4196	*/
4197	PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(&pVM->pgm.s);
4198	RTGCPTR GCPtr = pVM->pgm.s.GCPtrCR3Mapping + PAGE_SIZE;
4199	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++, GCPtr += PAGE_SIZE)
4200	{
4201	if (pGuestPDPT->a[i].n.u1Present)
4202	{
4203	RTHCPTR HCPtr;
4204	RTHCPHYS HCPhys;
4205	RTGCPHYS GCPhys = pGuestPDPT->a[i].u & X86_PDPE_PG_MASK;
4206	# ifdef VBOX_WITH_NEW_PHYS_CODE
4207	pgmLock(pVM);
4208	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, GCPhys);
4209	AssertReturn(pPage, VERR_INTERNAL_ERROR_2);
4210	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
4211	# if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
4212	HCPtr = NIL_RTHCPTR;
4213	int rc2 = VINF_SUCCESS;
4214	# else
4215	int rc2 = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, (void **)&HCPtr);
4216	# endif
4217	pgmUnlock(pVM);
4218	# else /* !VBOX_WITH_NEW_PHYS_CODE */
4219	int rc2 = pgmRamGCPhys2HCPtrAndHCPhys(&pVM->pgm.s, GCPhys, &HCPtr, &HCPhys);
4220	# endif /* !VBOX_WITH_NEW_PHYS_CODE */
4221	if (RT_SUCCESS(rc2))
4222	{
4223	rc = PGMMap(pVM, GCPtr, HCPhys, PAGE_SIZE, 0);
4224	AssertRCReturn(rc, rc);
4225
4226	pVM->pgm.s.apGstPaePDsR3[i] = (R3PTRTYPE(PX86PDPAE))HCPtr;
4227	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4228	pVM->pgm.s.apGstPaePDsR0[i] = (R0PTRTYPE(PX86PDPAE))HCPtr;
4229	# endif
4230	pVM->pgm.s.apGstPaePDsRC[i] = (RCPTRTYPE(PX86PDPAE))GCPtr;
4231	pVM->pgm.s.aGCPhysGstPaePDs[i] = GCPhys;
4232	PGM_INVL_PG(GCPtr); /** @todo This ends up calling HWACCMInvalidatePage, is that correct? */
4233	continue;
4234	}
4235	AssertMsgFailed(("pgmR3Gst32BitMapCR3: rc2=%d GCPhys=%RGp i=%d\n", rc2, GCPhys, i));
4236	}
4237
4238	pVM->pgm.s.apGstPaePDsR3[i] = 0;
4239	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4240	pVM->pgm.s.apGstPaePDsR0[i] = 0;
4241	# endif
4242	pVM->pgm.s.apGstPaePDsRC[i] = 0;
4243	pVM->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
4244	PGM_INVL_PG(GCPtr); /** @todo this shouldn't be necessary? */
4245	}
4246
4247	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
4248	pVM->pgm.s.pGstAmd64Pml4R3 = (R3PTRTYPE(PX86PML4))HCPtrGuestCR3;
4249	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4250	pVM->pgm.s.pGstAmd64Pml4R0 = (R0PTRTYPE(PX86PML4))HCPtrGuestCR3;
4251	# endif
4252	# endif
4253	}
4254	else
4255	AssertMsgFailed(("rc=%Rrc GCPhysGuestPD=%RGp\n", rc, GCPhysCR3));
4256	}
4257	else
4258	AssertMsgFailed(("rc=%Rrc GCPhysGuestPD=%RGp\n", rc, GCPhysCR3));
4259
4260	#else /* prot/real stub */
4261	int rc = VINF_SUCCESS;
4262	#endif
4263
4264	/* Update shadow paging info for guest modes with paging (32, pae, 64). */
4265	# if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
4266	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
4267	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64) \
4268	&& ( PGM_GST_TYPE != PGM_TYPE_REAL \
4269	&& PGM_GST_TYPE != PGM_TYPE_PROT))
4270
4271	Assert(!HWACCMIsNestedPagingActive(pVM));
4272
4273	/*
4274	* Update the shadow root page as well since that's not fixed.
4275	*/
4276	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4277	PPGMPOOLPAGE pOldShwPageCR3 = pVM->pgm.s.CTX_SUFF(pShwPageCR3);
4278	uint32_t iOldShwUserTable = pVM->pgm.s.iShwUserTable;
4279	uint32_t iOldShwUser = pVM->pgm.s.iShwUser;
4280	PPGMPOOLPAGE pNewShwPageCR3;
4281
4282	Assert(!(GCPhysCR3 >> (PAGE_SHIFT + 32)));
4283	rc = pgmPoolAlloc(pVM, GCPhysCR3 & GST_CR3_PAGE_MASK, BTH_PGMPOOLKIND_ROOT, SHW_POOL_ROOT_IDX, GCPhysCR3 >> PAGE_SHIFT, &pNewShwPageCR3);
4284	AssertFatalRC(rc);
4285	rc = VINF_SUCCESS;
4286
4287	/* Mark the page as locked; disallow flushing. */
4288	pgmPoolLockPage(pPool, pNewShwPageCR3);
4289
4290	# ifdef IN_RC
4291	/* NOTE: We can't deal with jumps to ring 3 here as we're now in an inconsistent state! */
4292	bool fLog = VMMGCLogDisable(pVM);
4293	# endif
4294
4295	pVM->pgm.s.iShwUser = SHW_POOL_ROOT_IDX;
4296	pVM->pgm.s.iShwUserTable = GCPhysCR3 >> PAGE_SHIFT;
4297	pVM->pgm.s.CTX_SUFF(pShwPageCR3) = pNewShwPageCR3;
4298	# ifdef IN_RING0
4299	pVM->pgm.s.pShwPageCR3R3 = MMHyperCCToR3(pVM, pVM->pgm.s.CTX_SUFF(pShwPageCR3));
4300	pVM->pgm.s.pShwPageCR3RC = MMHyperCCToRC(pVM, pVM->pgm.s.CTX_SUFF(pShwPageCR3));
4301	# elif defined(IN_RC)
4302	pVM->pgm.s.pShwPageCR3R3 = MMHyperCCToR3(pVM, pVM->pgm.s.CTX_SUFF(pShwPageCR3));
4303	pVM->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVM->pgm.s.CTX_SUFF(pShwPageCR3));
4304	# else
4305	pVM->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVM->pgm.s.CTX_SUFF(pShwPageCR3));
4306	pVM->pgm.s.pShwPageCR3RC = MMHyperCCToRC(pVM, pVM->pgm.s.CTX_SUFF(pShwPageCR3));
4307	# endif
4308
4309	# ifndef PGM_WITHOUT_MAPPINGS
4310	/*
4311	* Apply all hypervisor mappings to the new CR3.
4312	* Note that SyncCR3 will be executed in case CR3 is changed in a guest paging mode; this will
4313	* make sure we check for conflicts in the new CR3 root.
4314	*/
4315	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
4316	Assert(VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL) \|\| VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
4317	# endif
4318	rc = pgmMapActivateCR3(pVM, pNewShwPageCR3);
4319	AssertRCReturn(rc, rc);
4320	# endif
4321
4322	/* Set the current hypervisor CR3. */
4323	CPUMSetHyperCR3(pVM, PGMGetHyperCR3(pVM));
4324	SELMShadowCR3Changed(pVM);
4325
4326	# ifdef IN_RC
4327	VMMGCLogRestore(pVM, fLog);
4328	# endif
4329
4330	/* Clean up the old CR3 root. */
4331	if (pOldShwPageCR3)
4332	{
4333	Assert(pOldShwPageCR3->enmKind != PGMPOOLKIND_FREE);
4334	# ifndef PGM_WITHOUT_MAPPINGS
4335	/* Remove the hypervisor mappings from the shadow page table. */
4336	pgmMapDeactivateCR3(pVM, pOldShwPageCR3);
4337	# endif
4338	/* Mark the page as unlocked; allow flushing again. */
4339	pgmPoolUnlockPage(pPool, pOldShwPageCR3);
4340
4341	pgmPoolFreeByPage(pPool, pOldShwPageCR3, iOldShwUser, iOldShwUserTable);
4342	}
4343
4344	# endif
4345
4346	return rc;
4347	}
4348
4349	/**
4350	* Unmaps the shadow CR3.
4351	*
4352	* @returns VBox status, no specials.
4353	* @param pVM VM handle.
4354	*/
4355	PGM_BTH_DECL(int, UnmapCR3)(PVM pVM)
4356	{
4357	LogFlow(("UnmapCR3\n"));
4358
4359	int rc = VINF_SUCCESS;
4360
4361	/* Update guest paging info. */
4362	#if PGM_GST_TYPE == PGM_TYPE_32BIT
4363	pVM->pgm.s.pGst32BitPdR3 = 0;
4364	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4365	pVM->pgm.s.pGst32BitPdR0 = 0;
4366	#endif
4367	pVM->pgm.s.pGst32BitPdRC = 0;
4368
4369	#elif PGM_GST_TYPE == PGM_TYPE_PAE
4370	pVM->pgm.s.pGstPaePdptR3 = 0;
4371	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4372	pVM->pgm.s.pGstPaePdptR0 = 0;
4373	# endif
4374	pVM->pgm.s.pGstPaePdptRC = 0;
4375	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
4376	{
4377	pVM->pgm.s.apGstPaePDsR3[i] = 0;
4378	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4379	pVM->pgm.s.apGstPaePDsR0[i] = 0;
4380	# endif
4381	pVM->pgm.s.apGstPaePDsRC[i] = 0;
4382	pVM->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
4383	}
4384
4385	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
4386	pVM->pgm.s.pGstAmd64Pml4R3 = 0;
4387	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4388	pVM->pgm.s.pGstAmd64Pml4R0 = 0;
4389	# endif
4390
4391	#else /* prot/real mode stub */
4392	/* nothing to do */
4393	#endif
4394
4395	#if !defined(IN_RC) /* In RC we rely on MapCR3 to do the shadow part for us at a safe time */
4396	/* Update shadow paging info. */
4397	# if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
4398	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
4399	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64))
4400
4401	# if PGM_GST_TYPE != PGM_TYPE_REAL
4402	Assert(!HWACCMIsNestedPagingActive(pVM));
4403	# endif
4404
4405	# ifndef PGM_WITHOUT_MAPPINGS
4406	if (pVM->pgm.s.CTX_SUFF(pShwPageCR3))
4407	/* Remove the hypervisor mappings from the shadow page table. */
4408	pgmMapDeactivateCR3(pVM, pVM->pgm.s.CTX_SUFF(pShwPageCR3));
4409	# endif
4410
4411	if (pVM->pgm.s.CTX_SUFF(pShwPageCR3))
4412	{
4413	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4414
4415	Assert(pVM->pgm.s.iShwUser != PGMPOOL_IDX_NESTED_ROOT);
4416
4417	/* Mark the page as unlocked; allow flushing again. */
4418	pgmPoolUnlockPage(pPool, pVM->pgm.s.CTX_SUFF(pShwPageCR3));
4419
4420	pgmPoolFreeByPage(pPool, pVM->pgm.s.CTX_SUFF(pShwPageCR3), pVM->pgm.s.iShwUser, pVM->pgm.s.iShwUserTable);
4421	pVM->pgm.s.pShwPageCR3R3 = 0;
4422	pVM->pgm.s.pShwPageCR3R0 = 0;
4423	pVM->pgm.s.pShwPageCR3RC = 0;
4424	pVM->pgm.s.iShwUser = 0;
4425	pVM->pgm.s.iShwUserTable = 0;
4426	}
4427	# endif
4428	#endif /* !IN_RC*/
4429
4430	return rc;
4431	}
4432

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllBth.h@ 18646

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