PGMAllBth.h@ 25468

Last change on this file since 25468 was 25245, checked in by vboxsync, 15 years ago
PGMAllShw.h: -Wshadow
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1	/* $Id: PGMAllBth.h 25245 2009-12-08 13:53:59Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Shadow+Guest Paging Template - All context code.
4	*
5	* This file is a big challenge!
6	*/
7
8	/*
9	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
10	*
11	* This file is part of VirtualBox Open Source Edition (OSE), as
12	* available from http://www.virtualbox.org. This file is free software;
13	* you can redistribute it and/or modify it under the terms of the GNU
14	* General Public License (GPL) as published by the Free Software
15	* Foundation, in version 2 as it comes in the "COPYING" file of the
16	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
17	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
18	*
19	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
20	* Clara, CA 95054 USA or visit http://www.sun.com if you need
21	* additional information or have any questions.
22	*/
23
24	/*******************************************************************************
25	* Internal Functions *
26	*******************************************************************************/
27	RT_C_DECLS_BEGIN
28	PGM_BTH_DECL(int, Trap0eHandler)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
29	PGM_BTH_DECL(int, InvalidatePage)(PVMCPU pVCpu, RTGCPTR GCPtrPage);
30	PGM_BTH_DECL(int, SyncPage)(PVMCPU pVCpu, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr);
31	PGM_BTH_DECL(int, CheckPageFault)(PVMCPU pVCpu, uint32_t uErr, PSHWPDE pPdeDst, PGSTPDE pPdeSrc, RTGCPTR GCPtrPage);
32	PGM_BTH_DECL(int, SyncPT)(PVMCPU pVCpu, unsigned iPD, PGSTPD pPDSrc, RTGCPTR GCPtrPage);
33	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVMCPU pVCpu, RTGCPTR Addr, unsigned fPage, unsigned uErr);
34	PGM_BTH_DECL(int, PrefetchPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage);
35	PGM_BTH_DECL(int, SyncCR3)(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
36	#ifdef VBOX_STRICT
37	PGM_BTH_DECL(unsigned, AssertCR3)(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr = 0, RTGCPTR cb = ~(RTGCPTR)0);
38	#endif
39	#ifdef PGMPOOL_WITH_USER_TRACKING
40	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVMCPU pVCpu, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys);
41	#endif
42	PGM_BTH_DECL(int, MapCR3)(PVMCPU pVCpu, RTGCPHYS GCPhysCR3);
43	PGM_BTH_DECL(int, UnmapCR3)(PVMCPU pVCpu);
44	RT_C_DECLS_END
45
46
47	/* Filter out some illegal combinations of guest and shadow paging, so we can remove redundant checks inside functions. */
48	#if PGM_GST_TYPE == PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
49	# error "Invalid combination; PAE guest implies PAE shadow"
50	#endif
51
52	#if (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
53	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT)
54	# error "Invalid combination; real or protected mode without paging implies 32 bits or PAE shadow paging."
55	#endif
56
57	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) \
58	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT)
59	# error "Invalid combination; 32 bits guest paging or PAE implies 32 bits or PAE shadow paging."
60	#endif
61
62	#if (PGM_GST_TYPE == PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT) \
63	\|\| (PGM_SHW_TYPE == PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PROT)
64	# error "Invalid combination; AMD64 guest implies AMD64 shadow and vice versa"
65	#endif
66
67	#ifdef IN_RING0 /* no mappings in VT-x and AMD-V mode */
68	# define PGM_WITHOUT_MAPPINGS
69	#endif
70
71
72	#ifndef IN_RING3
73	/**
74	* #PF Handler for raw-mode guest execution.
75	*
76	* @returns VBox status code (appropriate for trap handling and GC return).
77	*
78	* @param pVCpu VMCPU Handle.
79	* @param uErr The trap error code.
80	* @param pRegFrame Trap register frame.
81	* @param pvFault The fault address.
82	*/
83	PGM_BTH_DECL(int, Trap0eHandler)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
84	{
85	PVM pVM = pVCpu->CTX_SUFF(pVM);
86
87	# if defined(IN_RC) && defined(VBOX_STRICT)
88	PGMDynCheckLocks(pVM);
89	# endif
90
91	# if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
92	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
93	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT)
94
95	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE != PGM_TYPE_PAE
96	/*
97	* Hide the instruction fetch trap indicator for now.
98	*/
99	/** @todo NXE will change this and we must fix NXE in the switcher too! */
100	if (uErr & X86_TRAP_PF_ID)
101	{
102	uErr &= ~X86_TRAP_PF_ID;
103	TRPMSetErrorCode(pVCpu, uErr);
104	}
105	# endif
106
107	/*
108	* Get PDs.
109	*/
110	int rc;
111	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
112	# if PGM_GST_TYPE == PGM_TYPE_32BIT
113	const unsigned iPDSrc = pvFault >> GST_PD_SHIFT;
114	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(&pVCpu->pgm.s);
115
116	# elif PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
117
118	# if PGM_GST_TYPE == PGM_TYPE_PAE
119	unsigned iPDSrc = 0; /* initialized to shut up gcc */
120	X86PDPE PdpeSrc;
121	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVCpu->pgm.s, pvFault, &iPDSrc, &PdpeSrc);
122
123	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
124	unsigned iPDSrc = 0; /* initialized to shut up gcc */
125	PX86PML4E pPml4eSrc;
126	X86PDPE PdpeSrc;
127	PGSTPD pPDSrc;
128
129	pPDSrc = pgmGstGetLongModePDPtr(&pVCpu->pgm.s, pvFault, &pPml4eSrc, &PdpeSrc, &iPDSrc);
130	Assert(pPml4eSrc);
131	# endif
132
133	/* Quick check for a valid guest trap. (PAE & AMD64) */
134	if (!pPDSrc)
135	{
136	# if PGM_GST_TYPE == PGM_TYPE_AMD64 && GC_ARCH_BITS == 64
137	LogFlow(("Trap0eHandler: guest PML4 %d not present CR3=%RGp\n", (int)((pvFault >> X86_PML4_SHIFT) & X86_PML4_MASK), CPUMGetGuestCR3(pVCpu) & X86_CR3_PAGE_MASK));
138	# else
139	LogFlow(("Trap0eHandler: guest iPDSrc=%u not present CR3=%RGp\n", iPDSrc, CPUMGetGuestCR3(pVCpu) & X86_CR3_PAGE_MASK));
140	# endif
141	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2GuestTrap; });
142	TRPMSetErrorCode(pVCpu, uErr);
143	return VINF_EM_RAW_GUEST_TRAP;
144	}
145	# endif
146
147	# else /* !PGM_WITH_PAGING */
148	PGSTPD pPDSrc = NULL;
149	const unsigned iPDSrc = 0;
150	# endif /* !PGM_WITH_PAGING */
151
152	/* Fetch the guest PDE */
153	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
154	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
155	# else
156	GSTPDE PdeSrc;
157	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
158	PdeSrc.n.u1Present = 1;
159	PdeSrc.n.u1Write = 1;
160	PdeSrc.n.u1Accessed = 1;
161	PdeSrc.n.u1User = 1;
162	# endif
163
164	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
165	const unsigned iPDDst = pvFault >> SHW_PD_SHIFT;
166	PX86PD pPDDst = pgmShwGet32BitPDPtr(&pVCpu->pgm.s);
167
168	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
169	const unsigned iPDDst = (pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK; /* pPDDst index, not used with the pool. */
170
171	PX86PDPAE pPDDst;
172	# if PGM_GST_TYPE != PGM_TYPE_PAE
173	X86PDPE PdpeSrc;
174
175	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
176	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
177	# endif
178	rc = pgmShwSyncPaePDPtr(pVCpu, pvFault, &PdpeSrc, &pPDDst);
179	if (rc != VINF_SUCCESS)
180	{
181	AssertRC(rc);
182	return rc;
183	}
184	Assert(pPDDst);
185
186	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
187	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
188	PX86PDPAE pPDDst;
189	# if PGM_GST_TYPE == PGM_TYPE_PROT
190	/* AMD-V nested paging */
191	X86PML4E Pml4eSrc;
192	X86PDPE PdpeSrc;
193	PX86PML4E pPml4eSrc = &Pml4eSrc;
194
195	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
196	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A;
197	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A;
198	# endif
199
200	rc = pgmShwSyncLongModePDPtr(pVCpu, pvFault, pPml4eSrc, &PdpeSrc, &pPDDst);
201	if (rc != VINF_SUCCESS)
202	{
203	AssertRC(rc);
204	return rc;
205	}
206	Assert(pPDDst);
207
208	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
209	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
210	PEPTPD pPDDst;
211
212	rc = pgmShwGetEPTPDPtr(pVCpu, pvFault, NULL, &pPDDst);
213	if (rc != VINF_SUCCESS)
214	{
215	AssertRC(rc);
216	return rc;
217	}
218	Assert(pPDDst);
219	# endif
220
221	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
222	/*
223	* If we successfully correct the write protection fault due to dirty bit
224	* tracking, or this page fault is a genuine one, then return immediately.
225	*/
226	STAM_PROFILE_START(&pVCpu->pgm.s.StatRZTrap0eTimeCheckPageFault, e);
227	rc = PGM_BTH_NAME(CheckPageFault)(pVCpu, uErr, &pPDDst->a[iPDDst], &pPDSrc->a[iPDSrc], pvFault);
228	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeCheckPageFault, e);
229	if ( rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT
230	\|\| rc == VINF_EM_RAW_GUEST_TRAP)
231	{
232	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution)
233	= rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? &pVCpu->pgm.s.StatRZTrap0eTime2DirtyAndAccessed : &pVCpu->pgm.s.StatRZTrap0eTime2GuestTrap; });
234	LogBird(("Trap0eHandler: returns %s\n", rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? "VINF_SUCCESS" : "VINF_EM_RAW_GUEST_TRAP"));
235	return rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? VINF_SUCCESS : rc;
236	}
237
238	# if 0 /* rarely useful; leave for debugging. */
239	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0ePD[iPDSrc]);
240	# endif
241	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
242
243	/*
244	* A common case is the not-present error caused by lazy page table syncing.
245	*
246	* It is IMPORTANT that we weed out any access to non-present shadow PDEs here
247	* so we can safely assume that the shadow PT is present when calling SyncPage later.
248	*
249	* On failure, we ASSUME that SyncPT is out of memory or detected some kind
250	* of mapping conflict and defer to SyncCR3 in R3.
251	* (Again, we do NOT support access handlers for non-present guest pages.)
252	*
253	*/
254	if ( !(uErr & X86_TRAP_PF_P) /* not set means page not present instead of page protection violation */
255	&& !pPDDst->a[iPDDst].n.u1Present
256	&& PdeSrc.n.u1Present
257	)
258	{
259	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2SyncPT; });
260	STAM_PROFILE_START(&pVCpu->pgm.s.StatRZTrap0eTimeSyncPT, f);
261	LogFlow(("=>SyncPT %04x = %08x\n", iPDSrc, PdeSrc.au32[0]));
262	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, pvFault);
263	if (RT_SUCCESS(rc))
264	{
265	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeSyncPT, f);
266	return rc;
267	}
268	Log(("SyncPT: %d failed!! rc=%d\n", iPDSrc, rc));
269	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync, right? */
270	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeSyncPT, f);
271	return VINF_PGM_SYNC_CR3;
272	}
273
274	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(PGM_WITHOUT_MAPPINGS)
275	/*
276	* Check if this address is within any of our mappings.
277	*
278	* This is very fast and it's gonna save us a bit of effort below and prevent
279	* us from screwing ourself with MMIO2 pages which have a GC Mapping (VRam).
280	* (BTW, it's impossible to have physical access handlers in a mapping.)
281	*/
282	if (pgmMapAreMappingsEnabled(&pVM->pgm.s))
283	{
284	STAM_PROFILE_START(&pVCpu->pgm.s.StatRZTrap0eTimeMapping, a);
285	PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
286	for ( ; pMapping; pMapping = pMapping->CTX_SUFF(pNext))
287	{
288	if (pvFault < pMapping->GCPtr)
289	break;
290	if (pvFault - pMapping->GCPtr < pMapping->cb)
291	{
292	/*
293	* The first thing we check is if we've got an undetected conflict.
294	*/
295	if (!pVM->pgm.s.fMappingsFixed)
296	{
297	unsigned iPT = pMapping->cb >> GST_PD_SHIFT;
298	while (iPT-- > 0)
299	if (pPDSrc->a[iPDSrc + iPT].n.u1Present)
300	{
301	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eConflicts);
302	Log(("Trap0e: Detected Conflict %RGv-%RGv\n", pMapping->GCPtr, pMapping->GCPtrLast));
303	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync,right? */
304	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeMapping, a);
305	return VINF_PGM_SYNC_CR3;
306	}
307	}
308
309	/*
310	* Check if the fault address is in a virtual page access handler range.
311	*/
312	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->HyperVirtHandlers, pvFault);
313	if ( pCur
314	&& pvFault - pCur->Core.Key < pCur->cb
315	&& uErr & X86_TRAP_PF_RW)
316	{
317	# ifdef IN_RC
318	STAM_PROFILE_START(&pCur->Stat, h);
319	pgmUnlock(pVM);
320	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
321	pgmLock(pVM);
322	STAM_PROFILE_STOP(&pCur->Stat, h);
323	# else
324	AssertFailed();
325	rc = VINF_EM_RAW_EMULATE_INSTR; /* can't happen with VMX */
326	# endif
327	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersMapping);
328	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeMapping, a);
329	return rc;
330	}
331
332	/*
333	* Pretend we're not here and let the guest handle the trap.
334	*/
335	TRPMSetErrorCode(pVCpu, uErr & ~X86_TRAP_PF_P);
336	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eGuestPFMapping);
337	LogFlow(("PGM: Mapping access -> route trap to recompiler!\n"));
338	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeMapping, a);
339	return VINF_EM_RAW_GUEST_TRAP;
340	}
341	}
342	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeMapping, a);
343	} /* pgmAreMappingsEnabled(&pVM->pgm.s) */
344	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
345
346	/*
347	* Check if this fault address is flagged for special treatment,
348	* which means we'll have to figure out the physical address and
349	* check flags associated with it.
350	*
351	* ASSUME that we can limit any special access handling to pages
352	* in page tables which the guest believes to be present.
353	*/
354	if (PdeSrc.n.u1Present)
355	{
356	RTGCPHYS GCPhys = NIL_RTGCPHYS;
357
358	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
359	# if PGM_GST_TYPE == PGM_TYPE_AMD64
360	bool fBigPagesSupported = true;
361	# else
362	bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PSE);
363	# endif
364	if ( PdeSrc.b.u1Size
365	&& fBigPagesSupported)
366	GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc)
367	\| ((RTGCPHYS)pvFault & (GST_BIG_PAGE_OFFSET_MASK ^ PAGE_OFFSET_MASK));
368	else
369	{
370	PGSTPT pPTSrc;
371	rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
372	if (RT_SUCCESS(rc))
373	{
374	unsigned iPTESrc = (pvFault >> GST_PT_SHIFT) & GST_PT_MASK;
375	if (pPTSrc->a[iPTESrc].n.u1Present)
376	GCPhys = pPTSrc->a[iPTESrc].u & GST_PTE_PG_MASK;
377	}
378	}
379	# else
380	/* No paging so the fault address is the physical address */
381	GCPhys = (RTGCPHYS)(pvFault & ~PAGE_OFFSET_MASK);
382	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
383
384	/*
385	* If we have a GC address we'll check if it has any flags set.
386	*/
387	if (GCPhys != NIL_RTGCPHYS)
388	{
389	STAM_PROFILE_START(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
390
391	PPGMPAGE pPage;
392	rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
393	if (RT_SUCCESS(rc)) /** just handle the failure immediate (it returns) and make things easier to read. */
394	{
395	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
396	{
397	if (PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage))
398	{
399	/*
400	* Physical page access handler.
401	*/
402	const RTGCPHYS GCPhysFault = GCPhys \| (pvFault & PAGE_OFFSET_MASK);
403	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)RTAvlroGCPhysRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->PhysHandlers, GCPhysFault);
404	if (pCur)
405	{
406	# ifdef PGM_SYNC_N_PAGES
407	/*
408	* If the region is write protected and we got a page not present fault, then sync
409	* the pages. If the fault was caused by a read, then restart the instruction.
410	* In case of write access continue to the GC write handler.
411	*
412	* ASSUMES that there is only one handler per page or that they have similar write properties.
413	*/
414	if ( pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
415	&& !(uErr & X86_TRAP_PF_P))
416	{
417	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, pvFault, PGM_SYNC_NR_PAGES, uErr);
418	if ( RT_FAILURE(rc)
419	\|\| !(uErr & X86_TRAP_PF_RW)
420	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
421	{
422	AssertRC(rc);
423	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersOutOfSync);
424	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
425	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2OutOfSyncHndPhys; });
426	return rc;
427	}
428	}
429	# endif
430
431	AssertMsg( pCur->enmType != PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
432	\|\| (pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE && (uErr & X86_TRAP_PF_RW)),
433	("Unexpected trap for physical handler: %08X (phys=%08x) pPage=%R[pgmpage] uErr=%X, enum=%d\n", pvFault, GCPhys, pPage, uErr, pCur->enmType));
434
435	# if defined(IN_RC) \|\| defined(IN_RING0)
436	if (pCur->CTX_SUFF(pfnHandler))
437	{
438	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
439	# ifdef IN_RING0
440	PFNPGMR0PHYSHANDLER pfnHandler = pCur->CTX_SUFF(pfnHandler);
441	# else
442	PFNPGMRCPHYSHANDLER pfnHandler = pCur->CTX_SUFF(pfnHandler);
443	# endif
444	bool fLeaveLock = (pfnHandler != pPool->CTX_SUFF(pfnAccessHandler));
445	void *pvUser = pCur->CTX_SUFF(pvUser);
446
447	STAM_PROFILE_START(&pCur->Stat, h);
448	if (fLeaveLock)
449	pgmUnlock(pVM); /* @todo: Not entirely safe. */
450
451	rc = pfnHandler(pVM, uErr, pRegFrame, pvFault, GCPhysFault, pvUser);
452	if (fLeaveLock)
453	pgmLock(pVM);
454	# ifdef VBOX_WITH_STATISTICS
455	pCur = (PPGMPHYSHANDLER)RTAvlroGCPhysRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->PhysHandlers, GCPhysFault);
456	if (pCur)
457	STAM_PROFILE_STOP(&pCur->Stat, h);
458	# else
459	pCur = NULL; /* might be invalid by now. */
460	# endif
461
462	}
463	else
464	# endif
465	rc = VINF_EM_RAW_EMULATE_INSTR;
466
467	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersPhysical);
468	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
469	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2HndPhys; });
470	return rc;
471	}
472	}
473	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
474	else
475	{
476	# ifdef PGM_SYNC_N_PAGES
477	/*
478	* If the region is write protected and we got a page not present fault, then sync
479	* the pages. If the fault was caused by a read, then restart the instruction.
480	* In case of write access continue to the GC write handler.
481	*/
482	if ( PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) < PGM_PAGE_HNDL_PHYS_STATE_ALL
483	&& !(uErr & X86_TRAP_PF_P))
484	{
485	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, pvFault, PGM_SYNC_NR_PAGES, uErr);
486	if ( RT_FAILURE(rc)
487	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
488	\|\| !(uErr & X86_TRAP_PF_RW))
489	{
490	AssertRC(rc);
491	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersOutOfSync);
492	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
493	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2OutOfSyncHndVirt; });
494	return rc;
495	}
496	}
497	# endif
498	/*
499	* Ok, it's an virtual page access handler.
500	*
501	* Since it's faster to search by address, we'll do that first
502	* and then retry by GCPhys if that fails.
503	*/
504	/** @todo r=bird: perhaps we should consider looking up by physical address directly now? */
505	/** @note r=svl: true, but lookup on virtual address should remain as a fallback as phys & virt trees might be out of sync, because the
506	* page was changed without us noticing it (not-present -> present without invlpg or mov cr3, xxx)
507	*/
508	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
509	if (pCur)
510	{
511	AssertMsg(!(pvFault - pCur->Core.Key < pCur->cb)
512	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
513	\|\| !(uErr & X86_TRAP_PF_P)
514	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
515	("Unexpected trap for virtual handler: %RGv (phys=%RGp) pPage=%R[pgmpage] uErr=%X, enum=%d\n", pvFault, GCPhys, pPage, uErr, pCur->enmType));
516
517	if ( pvFault - pCur->Core.Key < pCur->cb
518	&& ( uErr & X86_TRAP_PF_RW
519	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
520	{
521	# ifdef IN_RC
522	STAM_PROFILE_START(&pCur->Stat, h);
523	pgmUnlock(pVM);
524	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
525	pgmLock(pVM);
526	STAM_PROFILE_STOP(&pCur->Stat, h);
527	# else
528	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
529	# endif
530	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersVirtual);
531	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
532	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2HndVirt; });
533	return rc;
534	}
535	/* Unhandled part of a monitored page */
536	}
537	else
538	{
539	/* Check by physical address. */
540	unsigned iPage;
541	rc = pgmHandlerVirtualFindByPhysAddr(pVM, GCPhys + (pvFault & PAGE_OFFSET_MASK),
542	&pCur, &iPage);
543	Assert(RT_SUCCESS(rc) \|\| !pCur);
544	if ( pCur
545	&& ( uErr & X86_TRAP_PF_RW
546	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
547	{
548	Assert((pCur->aPhysToVirt[iPage].Core.Key & X86_PTE_PAE_PG_MASK) == GCPhys);
549	# ifdef IN_RC
550	RTGCPTR off = (iPage << PAGE_SHIFT) + (pvFault & PAGE_OFFSET_MASK) - (pCur->Core.Key & PAGE_OFFSET_MASK);
551	Assert(off < pCur->cb);
552	STAM_PROFILE_START(&pCur->Stat, h);
553	pgmUnlock(pVM);
554	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, off);
555	pgmLock(pVM);
556	STAM_PROFILE_STOP(&pCur->Stat, h);
557	# else
558	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
559	# endif
560	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersVirtualByPhys);
561	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
562	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2HndVirt; });
563	return rc;
564	}
565	}
566	}
567	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
568
569	/*
570	* There is a handled area of the page, but this fault doesn't belong to it.
571	* We must emulate the instruction.
572	*
573	* To avoid crashing (non-fatal) in the interpreter and go back to the recompiler
574	* we first check if this was a page-not-present fault for a page with only
575	* write access handlers. Restart the instruction if it wasn't a write access.
576	*/
577	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersUnhandled);
578
579	if ( !PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
580	&& !(uErr & X86_TRAP_PF_P))
581	{
582	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, pvFault, PGM_SYNC_NR_PAGES, uErr);
583	if ( RT_FAILURE(rc)
584	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
585	\|\| !(uErr & X86_TRAP_PF_RW))
586	{
587	AssertRC(rc);
588	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersOutOfSync);
589	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
590	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2OutOfSyncHndPhys; });
591	return rc;
592	}
593	}
594
595	/** @todo This particular case can cause quite a lot of overhead. E.g. early stage of kernel booting in Ubuntu 6.06
596	* It's writing to an unhandled part of the LDT page several million times.
597	*/
598	rc = PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault);
599	LogFlow(("PGM: PGMInterpretInstruction -> rc=%d pPage=%R[pgmpage]\n", rc, pPage));
600	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
601	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2HndUnhandled; });
602	return rc;
603	} /* if any kind of handler */
604
605	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
606	if (uErr & X86_TRAP_PF_P)
607	{
608	/*
609	* The page isn't marked, but it might still be monitored by a virtual page access handler.
610	* (ASSUMES no temporary disabling of virtual handlers.)
611	*/
612	/** @todo r=bird: Since the purpose is to catch out of sync pages with virtual handler(s) here,
613	* we should correct both the shadow page table and physical memory flags, and not only check for
614	* accesses within the handler region but for access to pages with virtual handlers. */
615	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
616	if (pCur)
617	{
618	AssertMsg( !(pvFault - pCur->Core.Key < pCur->cb)
619	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
620	\|\| !(uErr & X86_TRAP_PF_P)
621	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
622	("Unexpected trap for virtual handler: %08X (phys=%08x) %R[pgmpage] uErr=%X, enum=%d\n", pvFault, GCPhys, pPage, uErr, pCur->enmType));
623
624	if ( pvFault - pCur->Core.Key < pCur->cb
625	&& ( uErr & X86_TRAP_PF_RW
626	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
627	{
628	# ifdef IN_RC
629	STAM_PROFILE_START(&pCur->Stat, h);
630	pgmUnlock(pVM);
631	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
632	pgmLock(pVM);
633	STAM_PROFILE_STOP(&pCur->Stat, h);
634	# else
635	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
636	# endif
637	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersVirtualUnmarked);
638	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
639	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2HndVirt; });
640	return rc;
641	}
642	}
643	}
644	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
645	}
646	else
647	{
648	/*
649	* When the guest accesses invalid physical memory (e.g. probing
650	* of RAM or accessing a remapped MMIO range), then we'll fall
651	* back to the recompiler to emulate the instruction.
652	*/
653	LogFlow(("PGM #PF: pgmPhysGetPageEx(%RGp) failed with %Rrc\n", GCPhys, rc));
654	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersInvalid);
655	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
656	return VINF_EM_RAW_EMULATE_INSTR;
657	}
658
659	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
660
661	# ifdef PGM_OUT_OF_SYNC_IN_GC /** @todo remove this bugger. */
662	/*
663	* We are here only if page is present in Guest page tables and
664	* trap is not handled by our handlers.
665	*
666	* Check it for page out-of-sync situation.
667	*/
668	STAM_PROFILE_START(&pVCpu->pgm.s.StatRZTrap0eTimeOutOfSync, c);
669
670	if (!(uErr & X86_TRAP_PF_P))
671	{
672	/*
673	* Page is not present in our page tables.
674	* Try to sync it!
675	* BTW, fPageShw is invalid in this branch!
676	*/
677	if (uErr & X86_TRAP_PF_US)
678	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncUser));
679	else /* supervisor */
680	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
681
682	# if defined(LOG_ENABLED) && !defined(IN_RING0)
683	RTGCPHYS GCPhys2;
684	uint64_t fPageGst2;
685	PGMGstGetPage(pVCpu, pvFault, &fPageGst2, &GCPhys2);
686	Log(("Page out of sync: %RGv eip=%08x PdeSrc.n.u1User=%d fPageGst2=%08llx GCPhys2=%RGp scan=%d\n",
687	pvFault, pRegFrame->eip, PdeSrc.n.u1User, fPageGst2, GCPhys2, CSAMDoesPageNeedScanning(pVM, (RTRCPTR)pRegFrame->eip)));
688	# endif /* LOG_ENABLED */
689
690	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0)
691	if (CPUMGetGuestCPL(pVCpu, pRegFrame) == 0)
692	{
693	uint64_t fPageGst;
694	rc = PGMGstGetPage(pVCpu, pvFault, &fPageGst, NULL);
695	if ( RT_SUCCESS(rc)
696	&& !(fPageGst & X86_PTE_US))
697	{
698	/* Note: can't check for X86_TRAP_ID bit, because that requires execute disable support on the CPU */
699	if ( pvFault == (RTGCPTR)pRegFrame->eip
700	\|\| pvFault - pRegFrame->eip < 8 /* instruction crossing a page boundary */
701	# ifdef CSAM_DETECT_NEW_CODE_PAGES
702	\|\| ( !PATMIsPatchGCAddr(pVM, (RTGCPTR)pRegFrame->eip)
703	&& CSAMDoesPageNeedScanning(pVM, (RTRCPTR)pRegFrame->eip)) /* any new code we encounter here */
704	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
705	)
706	{
707	LogFlow(("CSAMExecFault %RX32\n", pRegFrame->eip));
708	rc = CSAMExecFault(pVM, (RTRCPTR)pRegFrame->eip);
709	if (rc != VINF_SUCCESS)
710	{
711	/*
712	* CSAM needs to perform a job in ring 3.
713	*
714	* Sync the page before going to the host context; otherwise we'll end up in a loop if
715	* CSAM fails (e.g. instruction crosses a page boundary and the next page is not present)
716	*/
717	LogFlow(("CSAM ring 3 job\n"));
718	int rc2 = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, pvFault, 1, uErr);
719	AssertRC(rc2);
720
721	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeOutOfSync, c);
722	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2CSAM; });
723	return rc;
724	}
725	}
726	# ifdef CSAM_DETECT_NEW_CODE_PAGES
727	else if ( uErr == X86_TRAP_PF_RW
728	&& pRegFrame->ecx >= 0x100 /* early check for movswd count */
729	&& pRegFrame->ecx < 0x10000)
730	{
731	/* In case of a write to a non-present supervisor shadow page, we'll take special precautions
732	* to detect loading of new code pages.
733	*/
734
735	/*
736	* Decode the instruction.
737	*/
738	RTGCPTR PC;
739	rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->eip, &PC);
740	if (rc == VINF_SUCCESS)
741	{
742	PDISCPUSTATE pDis = &pVCpu->pgm.s.DisState;
743	uint32_t cbOp;
744	rc = EMInterpretDisasOneEx(pVM, pVCpu, PC, pRegFrame, pDis, &cbOp);
745
746	/* For now we'll restrict this to rep movsw/d instructions */
747	if ( rc == VINF_SUCCESS
748	&& pDis->pCurInstr->opcode == OP_MOVSWD
749	&& (pDis->prefix & PREFIX_REP))
750	{
751	CSAMMarkPossibleCodePage(pVM, pvFault);
752	}
753	}
754	}
755	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
756
757	/*
758	* Mark this page as safe.
759	*/
760	/** @todo not correct for pages that contain both code and data!! */
761	Log2(("CSAMMarkPage %RGv; scanned=%d\n", pvFault, true));
762	CSAMMarkPage(pVM, (RTRCPTR)pvFault, true);
763	}
764	}
765	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0) */
766	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, pvFault, PGM_SYNC_NR_PAGES, uErr);
767	if (RT_SUCCESS(rc))
768	{
769	/* The page was successfully synced, return to the guest. */
770	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeOutOfSync, c);
771	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2OutOfSync; });
772	return VINF_SUCCESS;
773	}
774	}
775	else /* uErr & X86_TRAP_PF_P: */
776	{
777	/*
778	* Write protected pages are make writable when the guest makes the first
779	* write to it. This happens for pages that are shared, write monitored
780	* and not yet allocated.
781	*
782	* Also, a side effect of not flushing global PDEs are out of sync pages due
783	* to physical monitored regions, that are no longer valid.
784	* Assume for now it only applies to the read/write flag.
785	*/
786	if (RT_SUCCESS(rc) && (uErr & X86_TRAP_PF_RW))
787	{
788	if (PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
789	{
790	Log(("PGM #PF: Make writable: %RGp %R[pgmpage] pvFault=%RGp uErr=%#x\n",
791	GCPhys, pPage, pvFault, uErr));
792	rc = pgmPhysPageMakeWritableUnlocked(pVM, pPage, GCPhys);
793	if (rc != VINF_SUCCESS)
794	{
795	AssertMsg(rc == VINF_PGM_SYNC_CR3 \|\| RT_FAILURE(rc), ("%Rrc\n", rc));
796	return rc;
797	}
798	if (RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)))
799	return VINF_EM_NO_MEMORY;
800	}
801
802	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
803	/* Check to see if we need to emulate the instruction as X86_CR0_WP has been cleared. */
804	if ( CPUMGetGuestCPL(pVCpu, pRegFrame) == 0
805	&& ((CPUMGetGuestCR0(pVCpu) & (X86_CR0_WP \| X86_CR0_PG)) == X86_CR0_PG))
806	{
807	Assert((uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RW \| X86_TRAP_PF_P));
808	uint64_t fPageGst;
809	rc = PGMGstGetPage(pVCpu, pvFault, &fPageGst, NULL);
810	if ( RT_SUCCESS(rc)
811	&& !(fPageGst & X86_PTE_RW))
812	{
813	rc = PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault);
814	if (RT_SUCCESS(rc))
815	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eWPEmulInRZ);
816	else
817	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eWPEmulToR3);
818	return rc;
819	}
820	AssertMsg(RT_SUCCESS(rc), ("Unexpected r/w page %RGv flag=%x rc=%Rrc\n", pvFault, (uint32_t)fPageGst, rc));
821	}
822	# endif
823	/// @todo count the above case; else
824	if (uErr & X86_TRAP_PF_US)
825	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncUserWrite));
826	else /* supervisor */
827	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncSupervisorWrite));
828
829	/*
830	* Note: Do NOT use PGM_SYNC_NR_PAGES here. That only works if the
831	* page is not present, which is not true in this case.
832	*/
833	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, pvFault, 1, uErr);
834	if (RT_SUCCESS(rc))
835	{
836	/*
837	* Page was successfully synced, return to guest.
838	* First invalidate the page as it might be in the TLB.
839	*/
840	# if PGM_SHW_TYPE == PGM_TYPE_EPT
841	HWACCMInvalidatePhysPage(pVM, (RTGCPHYS)pvFault);
842	# else
843	PGM_INVL_PG_ALL_VCPU(pVM, pvFault);
844	# endif
845	# ifdef VBOX_STRICT
846	RTGCPHYS GCPhys2;
847	uint64_t fPageGst;
848	if (!HWACCMIsNestedPagingActive(pVM))
849	{
850	rc = PGMGstGetPage(pVCpu, pvFault, &fPageGst, &GCPhys2);
851	AssertMsg(RT_SUCCESS(rc) && (fPageGst & X86_PTE_RW), ("rc=%d fPageGst=%RX64\n"));
852	LogFlow(("Obsolete physical monitor page out of sync %RGv - phys %RGp flags=%08llx\n", pvFault, GCPhys2, (uint64_t)fPageGst));
853	}
854	uint64_t fPageShw;
855	rc = PGMShwGetPage(pVCpu, pvFault, &fPageShw, NULL);
856	AssertMsg((RT_SUCCESS(rc) && (fPageShw & X86_PTE_RW)) \|\| pVM->cCpus > 1 /* new monitor can be installed/page table flushed between the trap exit and PGMTrap0eHandler */, ("rc=%Rrc fPageShw=%RX64\n", rc, fPageShw));
857	# endif /* VBOX_STRICT */
858	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeOutOfSync, c);
859	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2OutOfSyncHndObs; });
860	return VINF_SUCCESS;
861	}
862	}
863
864	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
865	# ifdef VBOX_STRICT
866	/*
867	* Check for VMM page flags vs. Guest page flags consistency.
868	* Currently only for debug purposes.
869	*/
870	if (RT_SUCCESS(rc))
871	{
872	/* Get guest page flags. */
873	uint64_t fPageGst;
874	rc = PGMGstGetPage(pVCpu, pvFault, &fPageGst, NULL);
875	if (RT_SUCCESS(rc))
876	{
877	uint64_t fPageShw;
878	rc = PGMShwGetPage(pVCpu, pvFault, &fPageShw, NULL);
879
880	/*
881	* Compare page flags.
882	* Note: we have AVL, A, D bits desynched.
883	*/
884	AssertMsg((fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)) == (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)),
885	("Page flags mismatch! pvFault=%RGv uErr=%x GCPhys=%RGp fPageShw=%RX64 fPageGst=%RX64\n", pvFault, (uint32_t)uErr, GCPhys, fPageShw, fPageGst));
886	}
887	else
888	AssertMsgFailed(("PGMGstGetPage rc=%Rrc\n", rc));
889	}
890	else
891	AssertMsgFailed(("PGMGCGetPage rc=%Rrc\n", rc));
892	# endif /* VBOX_STRICT */
893	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
894	}
895	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeOutOfSync, c);
896	# endif /* PGM_OUT_OF_SYNC_IN_GC */
897	}
898	else /* GCPhys == NIL_RTGCPHYS */
899	{
900	/*
901	* Page not present in Guest OS or invalid page table address.
902	* This is potential virtual page access handler food.
903	*
904	* For the present we'll say that our access handlers don't
905	* work for this case - we've already discarded the page table
906	* not present case which is identical to this.
907	*
908	* When we perchance find we need this, we will probably have AVL
909	* trees (offset based) to operate on and we can measure their speed
910	* agains mapping a page table and probably rearrange this handling
911	* a bit. (Like, searching virtual ranges before checking the
912	* physical address.)
913	*/
914	}
915	}
916	/* else: !present (guest) */
917
918
919	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
920	/*
921	* Conclusion, this is a guest trap.
922	*/
923	LogFlow(("PGM: Unhandled #PF -> route trap to recompiler!\n"));
924	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eGuestPFUnh);
925	return VINF_EM_RAW_GUEST_TRAP;
926	# else
927	/* present, but not a monitored page; perhaps the guest is probing physical memory */
928	return VINF_EM_RAW_EMULATE_INSTR;
929	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
930
931
932	# else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
933
934	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
935	return VERR_INTERNAL_ERROR;
936	# endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
937	}
938	#endif /* !IN_RING3 */
939
940
941	/**
942	* Emulation of the invlpg instruction.
943	*
944	*
945	* @returns VBox status code.
946	*
947	* @param pVCpu The VMCPU handle.
948	* @param GCPtrPage Page to invalidate.
949	*
950	* @remark ASSUMES that the guest is updating before invalidating. This order
951	* isn't required by the CPU, so this is speculative and could cause
952	* trouble.
953	* @remark No TLB shootdown is done on any other VCPU as we assume that
954	* invlpg emulation is the only reason for calling this function.
955	* (The guest has to shoot down TLB entries on other CPUs itself)
956	* Currently true, but keep in mind!
957	*
958	* @todo Flush page or page directory only if necessary!
959	* @todo Add a #define for simply invalidating the page.
960	*/
961	PGM_BTH_DECL(int, InvalidatePage)(PVMCPU pVCpu, RTGCPTR GCPtrPage)
962	{
963	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
964	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
965	&& PGM_SHW_TYPE != PGM_TYPE_EPT
966	int rc;
967	PVM pVM = pVCpu->CTX_SUFF(pVM);
968	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
969
970	Assert(PGMIsLockOwner(pVM));
971
972	LogFlow(("InvalidatePage %RGv\n", GCPtrPage));
973
974	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
975	if (pPool->cDirtyPages)
976	pgmPoolResetDirtyPages(pVM);
977	# endif
978
979	/*
980	* Get the shadow PD entry and skip out if this PD isn't present.
981	* (Guessing that it is frequent for a shadow PDE to not be present, do this first.)
982	*/
983	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
984	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
985	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(&pVCpu->pgm.s, GCPtrPage);
986
987	/* Fetch the pgm pool shadow descriptor. */
988	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
989	Assert(pShwPde);
990
991	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
992	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT);
993	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(&pVCpu->pgm.s);
994
995	/* If the shadow PDPE isn't present, then skip the invalidate. */
996	if (!pPdptDst->a[iPdpt].n.u1Present)
997	{
998	Assert(!(pPdptDst->a[iPdpt].u & PGM_PLXFLAGS_MAPPING));
999	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
1000	return VINF_SUCCESS;
1001	}
1002
1003	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1004	PPGMPOOLPAGE pShwPde = NULL;
1005	PX86PDPAE pPDDst;
1006
1007	/* Fetch the pgm pool shadow descriptor. */
1008	rc = pgmShwGetPaePoolPagePD(&pVCpu->pgm.s, GCPtrPage, &pShwPde);
1009	AssertRCSuccessReturn(rc, rc);
1010	Assert(pShwPde);
1011
1012	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPde);
1013	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1014
1015	# else /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
1016	/* PML4 */
1017	const unsigned iPml4 = (GCPtrPage >> X86_PML4_SHIFT) & X86_PML4_MASK;
1018	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1019	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1020	PX86PDPAE pPDDst;
1021	PX86PDPT pPdptDst;
1022	PX86PML4E pPml4eDst;
1023	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eDst, &pPdptDst, &pPDDst);
1024	if (rc != VINF_SUCCESS)
1025	{
1026	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT \|\| rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
1027	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
1028	if (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3))
1029	PGM_INVL_VCPU_TLBS(pVCpu);
1030	return VINF_SUCCESS;
1031	}
1032	Assert(pPDDst);
1033
1034	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1035	PX86PDPE pPdpeDst = &pPdptDst->a[iPdpt];
1036
1037	if (!pPdpeDst->n.u1Present)
1038	{
1039	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
1040	if (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3))
1041	PGM_INVL_VCPU_TLBS(pVCpu);
1042	return VINF_SUCCESS;
1043	}
1044
1045	# endif /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
1046
1047	const SHWPDE PdeDst = *pPdeDst;
1048	if (!PdeDst.n.u1Present)
1049	{
1050	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
1051	return VINF_SUCCESS;
1052	}
1053
1054	# if defined(IN_RC)
1055	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
1056	PGMDynLockHCPage(pVM, (uint8_t *)pPdeDst);
1057	# endif
1058
1059	/*
1060	* Get the guest PD entry and calc big page.
1061	*/
1062	# if PGM_GST_TYPE == PGM_TYPE_32BIT
1063	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(&pVCpu->pgm.s);
1064	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
1065	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
1066	# else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1067	unsigned iPDSrc = 0;
1068	# if PGM_GST_TYPE == PGM_TYPE_PAE
1069	X86PDPE PdpeSrc;
1070	PX86PDPAE pPDSrc = pgmGstGetPaePDPtr(&pVCpu->pgm.s, GCPtrPage, &iPDSrc, &PdpeSrc);
1071	# else /* AMD64 */
1072	PX86PML4E pPml4eSrc;
1073	X86PDPE PdpeSrc;
1074	PX86PDPAE pPDSrc = pgmGstGetLongModePDPtr(&pVCpu->pgm.s, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
1075	# endif
1076	GSTPDE PdeSrc;
1077
1078	if (pPDSrc)
1079	PdeSrc = pPDSrc->a[iPDSrc];
1080	else
1081	PdeSrc.u = 0;
1082	# endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1083
1084	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1085	const bool fIsBigPage = PdeSrc.b.u1Size;
1086	# else
1087	const bool fIsBigPage = PdeSrc.b.u1Size && (CPUMGetGuestCR4(pVCpu) & X86_CR4_PSE);
1088	# endif
1089
1090	# ifdef IN_RING3
1091	/*
1092	* If a CR3 Sync is pending we may ignore the invalidate page operation
1093	* depending on the kind of sync and if it's a global page or not.
1094	* This doesn't make sense in GC/R0 so we'll skip it entirely there.
1095	*/
1096	# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
1097	if ( VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3)
1098	\|\| ( VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
1099	&& fIsBigPage
1100	&& PdeSrc.b.u1Global
1101	)
1102	)
1103	# else
1104	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL) )
1105	# endif
1106	{
1107	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
1108	return VINF_SUCCESS;
1109	}
1110	# endif /* IN_RING3 */
1111
1112	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1113	/* Fetch the pgm pool shadow descriptor. */
1114	PPGMPOOLPAGE pShwPdpt = pgmPoolGetPage(pPool, pPml4eDst->u & X86_PML4E_PG_MASK);
1115	Assert(pShwPdpt);
1116
1117	/* Fetch the pgm pool shadow descriptor. */
1118	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & SHW_PDPE_PG_MASK);
1119	Assert(pShwPde);
1120
1121	Assert(pPml4eDst->n.u1Present && (pPml4eDst->u & SHW_PDPT_MASK));
1122	RTGCPHYS GCPhysPdpt = pPml4eSrc->u & X86_PML4E_PG_MASK;
1123
1124	if ( !pPml4eSrc->n.u1Present
1125	\|\| pShwPdpt->GCPhys != GCPhysPdpt)
1126	{
1127	LogFlow(("InvalidatePage: Out-of-sync PML4E (P/GCPhys) at %RGv GCPhys=%RGp vs %RGp Pml4eSrc=%RX64 Pml4eDst=%RX64\n",
1128	GCPtrPage, pShwPdpt->GCPhys, GCPhysPdpt, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
1129	pgmPoolFreeByPage(pPool, pShwPdpt, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPml4);
1130	ASMAtomicWriteSize(pPml4eDst, 0);
1131	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNPs));
1132	PGM_INVL_VCPU_TLBS(pVCpu);
1133	return VINF_SUCCESS;
1134	}
1135	if ( pPml4eSrc->n.u1User != pPml4eDst->n.u1User
1136	\|\| (!pPml4eSrc->n.u1Write && pPml4eDst->n.u1Write))
1137	{
1138	/*
1139	* Mark not present so we can resync the PML4E when it's used.
1140	*/
1141	LogFlow(("InvalidatePage: Out-of-sync PML4E at %RGv Pml4eSrc=%RX64 Pml4eDst=%RX64\n",
1142	GCPtrPage, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
1143	pgmPoolFreeByPage(pPool, pShwPdpt, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPml4);
1144	ASMAtomicWriteSize(pPml4eDst, 0);
1145	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1146	PGM_INVL_VCPU_TLBS(pVCpu);
1147	}
1148	else if (!pPml4eSrc->n.u1Accessed)
1149	{
1150	/*
1151	* Mark not present so we can set the accessed bit.
1152	*/
1153	LogFlow(("InvalidatePage: Out-of-sync PML4E (A) at %RGv Pml4eSrc=%RX64 Pml4eDst=%RX64\n",
1154	GCPtrPage, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
1155	pgmPoolFreeByPage(pPool, pShwPdpt, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPml4);
1156	ASMAtomicWriteSize(pPml4eDst, 0);
1157	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNAs));
1158	PGM_INVL_VCPU_TLBS(pVCpu);
1159	}
1160
1161	/* Check if the PDPT entry has changed. */
1162	Assert(pPdpeDst->n.u1Present && pPdpeDst->u & SHW_PDPT_MASK);
1163	RTGCPHYS GCPhysPd = PdpeSrc.u & GST_PDPE_PG_MASK;
1164	if ( !PdpeSrc.n.u1Present
1165	\|\| pShwPde->GCPhys != GCPhysPd)
1166	{
1167	LogFlow(("InvalidatePage: Out-of-sync PDPE (P/GCPhys) at %RGv GCPhys=%RGp vs %RGp PdpeSrc=%RX64 PdpeDst=%RX64\n",
1168	GCPtrPage, pShwPde->GCPhys, GCPhysPd, (uint64_t)PdpeSrc.u, (uint64_t)pPdpeDst->u));
1169	pgmPoolFreeByPage(pPool, pShwPde, pShwPdpt->idx, iPdpt);
1170	ASMAtomicWriteSize(pPdpeDst, 0);
1171	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNPs));
1172	PGM_INVL_VCPU_TLBS(pVCpu);
1173	return VINF_SUCCESS;
1174	}
1175	if ( PdpeSrc.lm.u1User != pPdpeDst->lm.u1User
1176	\|\| (!PdpeSrc.lm.u1Write && pPdpeDst->lm.u1Write))
1177	{
1178	/*
1179	* Mark not present so we can resync the PDPTE when it's used.
1180	*/
1181	LogFlow(("InvalidatePage: Out-of-sync PDPE at %RGv PdpeSrc=%RX64 PdpeDst=%RX64\n",
1182	GCPtrPage, (uint64_t)PdpeSrc.u, (uint64_t)pPdpeDst->u));
1183	pgmPoolFreeByPage(pPool, pShwPde, pShwPdpt->idx, iPdpt);
1184	ASMAtomicWriteSize(pPdpeDst, 0);
1185	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1186	PGM_INVL_VCPU_TLBS(pVCpu);
1187	}
1188	else if (!PdpeSrc.lm.u1Accessed)
1189	{
1190	/*
1191	* Mark not present so we can set the accessed bit.
1192	*/
1193	LogFlow(("InvalidatePage: Out-of-sync PDPE (A) at %RGv PdpeSrc=%RX64 PdpeDst=%RX64\n",
1194	GCPtrPage, (uint64_t)PdpeSrc.u, (uint64_t)pPdpeDst->u));
1195	pgmPoolFreeByPage(pPool, pShwPde, pShwPdpt->idx, iPdpt);
1196	ASMAtomicWriteSize(pPdpeDst, 0);
1197	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNAs));
1198	PGM_INVL_VCPU_TLBS(pVCpu);
1199	}
1200	# endif /* PGM_GST_TYPE == PGM_TYPE_AMD64 */
1201
1202	/*
1203	* Deal with the Guest PDE.
1204	*/
1205	rc = VINF_SUCCESS;
1206	if (PdeSrc.n.u1Present)
1207	{
1208	# ifndef PGM_WITHOUT_MAPPING
1209	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
1210	{
1211	/*
1212	* Conflict - Let SyncPT deal with it to avoid duplicate code.
1213	*/
1214	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1215	Assert(PGMGetGuestMode(pVCpu) <= PGMMODE_PAE);
1216	pgmLock(pVM);
1217	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
1218	pgmUnlock(pVM);
1219	}
1220	else
1221	# endif /* !PGM_WITHOUT_MAPPING */
1222	if ( PdeSrc.n.u1User != PdeDst.n.u1User
1223	\|\| (!PdeSrc.n.u1Write && PdeDst.n.u1Write))
1224	{
1225	/*
1226	* Mark not present so we can resync the PDE when it's used.
1227	*/
1228	LogFlow(("InvalidatePage: Out-of-sync at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
1229	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1230	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1231	ASMAtomicWriteSize(pPdeDst, 0);
1232	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1233	PGM_INVL_VCPU_TLBS(pVCpu);
1234	}
1235	else if (!PdeSrc.n.u1Accessed)
1236	{
1237	/*
1238	* Mark not present so we can set the accessed bit.
1239	*/
1240	LogFlow(("InvalidatePage: Out-of-sync (A) at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
1241	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1242	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1243	ASMAtomicWriteSize(pPdeDst, 0);
1244	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNAs));
1245	PGM_INVL_VCPU_TLBS(pVCpu);
1246	}
1247	else if (!fIsBigPage)
1248	{
1249	/*
1250	* 4KB - page.
1251	*/
1252	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1253	RTGCPHYS GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
1254
1255	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
1256	/* Reset the modification counter (OpenSolaris trashes tlb entries very often) */
1257	if (pShwPage->cModifications)
1258	pShwPage->cModifications = 1;
1259	# endif
1260
1261	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1262	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1263	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE/2);
1264	# endif
1265	if (pShwPage->GCPhys == GCPhys)
1266	{
1267	# if 0 /* likely cause of a major performance regression; must be SyncPageWorkerTrackDeref then */
1268	const unsigned iPTEDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1269	PSHWPT pPT = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1270	if (pPT->a[iPTEDst].n.u1Present)
1271	{
1272	# ifdef PGMPOOL_WITH_USER_TRACKING
1273	/* This is very unlikely with caching/monitoring enabled. */
1274	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pShwPage, pPT->a[iPTEDst].u & SHW_PTE_PG_MASK);
1275	# endif
1276	ASMAtomicWriteSize(&pPT->a[iPTEDst], 0);
1277	}
1278	# else /* Syncing it here isn't 100% safe and it's probably not worth spending time syncing it. */
1279	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
1280	if (RT_SUCCESS(rc))
1281	rc = VINF_SUCCESS;
1282	# endif
1283	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePage4KBPages));
1284	PGM_INVL_PG(pVCpu, GCPtrPage);
1285	}
1286	else
1287	{
1288	/*
1289	* The page table address changed.
1290	*/
1291	LogFlow(("InvalidatePage: Out-of-sync at %RGp PdeSrc=%RX64 PdeDst=%RX64 ShwGCPhys=%RGp iPDDst=%#x\n",
1292	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, iPDDst));
1293	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1294	ASMAtomicWriteSize(pPdeDst, 0);
1295	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1296	PGM_INVL_VCPU_TLBS(pVCpu);
1297	}
1298	}
1299	else
1300	{
1301	/*
1302	* 2/4MB - page.
1303	*/
1304	/* Before freeing the page, check if anything really changed. */
1305	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1306	RTGCPHYS GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
1307	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1308	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1309	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
1310	# endif
1311	if ( pShwPage->GCPhys == GCPhys
1312	&& pShwPage->enmKind == BTH_PGMPOOLKIND_PT_FOR_BIG)
1313	{
1314	/* ASSUMES a the given bits are identical for 4M and normal PDEs */
1315	/** @todo PAT */
1316	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD))
1317	== (PdeDst.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD))
1318	&& ( PdeSrc.b.u1Dirty /** @todo rainy day: What about read-only 4M pages? not very common, but still... */
1319	\|\| (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)))
1320	{
1321	LogFlow(("Skipping flush for big page containing %RGv (PD=%X .u=%RX64)-> nothing has changed!\n", GCPtrPage, iPDSrc, PdeSrc.u));
1322	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePage4MBPagesSkip));
1323	# if defined(IN_RC)
1324	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
1325	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
1326	# endif
1327	return VINF_SUCCESS;
1328	}
1329	}
1330
1331	/*
1332	* Ok, the page table is present and it's been changed in the guest.
1333	* If we're in host context, we'll just mark it as not present taking the lazy approach.
1334	* We could do this for some flushes in GC too, but we need an algorithm for
1335	* deciding which 4MB pages containing code likely to be executed very soon.
1336	*/
1337	LogFlow(("InvalidatePage: Out-of-sync PD at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
1338	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1339	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1340	ASMAtomicWriteSize(pPdeDst, 0);
1341	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePage4MBPages));
1342	PGM_INVL_BIG_PG(pVCpu, GCPtrPage);
1343	}
1344	}
1345	else
1346	{
1347	/*
1348	* Page directory is not present, mark shadow PDE not present.
1349	*/
1350	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
1351	{
1352	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1353	ASMAtomicWriteSize(pPdeDst, 0);
1354	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNPs));
1355	PGM_INVL_PG(pVCpu, GCPtrPage);
1356	}
1357	else
1358	{
1359	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1360	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDMappings));
1361	}
1362	}
1363	# if defined(IN_RC)
1364	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
1365	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
1366	# endif
1367	return rc;
1368
1369	#else /* guest real and protected mode */
1370	/* There's no such thing as InvalidatePage when paging is disabled, so just ignore. */
1371	return VINF_SUCCESS;
1372	#endif
1373	}
1374
1375
1376	#ifdef PGMPOOL_WITH_USER_TRACKING
1377	/**
1378	* Update the tracking of shadowed pages.
1379	*
1380	* @param pVCpu The VMCPU handle.
1381	* @param pShwPage The shadow page.
1382	* @param HCPhys The physical page we is being dereferenced.
1383	*/
1384	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVMCPU pVCpu, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys)
1385	{
1386	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1387	PVM pVM = pVCpu->CTX_SUFF(pVM);
1388
1389	STAM_PROFILE_START(&pVM->pgm.s.StatTrackDeref, a);
1390	LogFlow(("SyncPageWorkerTrackDeref: Damn HCPhys=%RHp pShwPage->idx=%#x!!!\n", HCPhys, pShwPage->idx));
1391
1392	/** @todo If this turns out to be a bottle neck (very likely) two things can be done:
1393	* 1. have a medium sized HCPhys -> GCPhys TLB (hash?)
1394	* 2. write protect all shadowed pages. I.e. implement caching.
1395	*/
1396	/*
1397	* Find the guest address.
1398	*/
1399	for (PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
1400	pRam;
1401	pRam = pRam->CTX_SUFF(pNext))
1402	{
1403	unsigned iPage = pRam->cb >> PAGE_SHIFT;
1404	while (iPage-- > 0)
1405	{
1406	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
1407	{
1408	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1409	pgmTrackDerefGCPhys(pPool, pShwPage, &pRam->aPages[iPage]);
1410	pShwPage->cPresent--;
1411	pPool->cPresent--;
1412	STAM_PROFILE_STOP(&pVM->pgm.s.StatTrackDeref, a);
1413	return;
1414	}
1415	}
1416	}
1417
1418	for (;;)
1419	AssertReleaseMsgFailed(("HCPhys=%RHp wasn't found!\n", HCPhys));
1420	# else /* !PGMPOOL_WITH_GCPHYS_TRACKING */
1421	pShwPage->cPresent--;
1422	pVM->pgm.s.CTX_SUFF(pPool)->cPresent--;
1423	# endif /* !PGMPOOL_WITH_GCPHYS_TRACKING */
1424	}
1425
1426
1427	/**
1428	* Update the tracking of shadowed pages.
1429	*
1430	* @param pVCpu The VMCPU handle.
1431	* @param pShwPage The shadow page.
1432	* @param u16 The top 16-bit of the pPage->HCPhys.
1433	* @param pPage Pointer to the guest page. this will be modified.
1434	* @param iPTDst The index into the shadow table.
1435	*/
1436	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackAddref)(PVMCPU pVCpu, PPGMPOOLPAGE pShwPage, uint16_t u16, PPGMPAGE pPage, const unsigned iPTDst)
1437	{
1438	PVM pVM = pVCpu->CTX_SUFF(pVM);
1439	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1440	/*
1441	* Just deal with the simple first time here.
1442	*/
1443	if (!u16)
1444	{
1445	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackVirgin);
1446	u16 = PGMPOOL_TD_MAKE(1, pShwPage->idx);
1447	}
1448	else
1449	u16 = pgmPoolTrackPhysExtAddref(pVM, u16, pShwPage->idx);
1450
1451	/* write back */
1452	Log2(("SyncPageWorkerTrackAddRef: u16=%#x->%#x iPTDst=%#x\n", u16, PGM_PAGE_GET_TRACKING(pPage), iPTDst));
1453	PGM_PAGE_SET_TRACKING(pPage, u16);
1454
1455	# endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
1456
1457	/* update statistics. */
1458	pVM->pgm.s.CTX_SUFF(pPool)->cPresent++;
1459	pShwPage->cPresent++;
1460	if (pShwPage->iFirstPresent > iPTDst)
1461	pShwPage->iFirstPresent = iPTDst;
1462	}
1463	#endif /* PGMPOOL_WITH_USER_TRACKING */
1464
1465
1466	/**
1467	* Creates a 4K shadow page for a guest page.
1468	*
1469	* For 4M pages the caller must convert the PDE4M to a PTE, this includes adjusting the
1470	* physical address. The PdeSrc argument only the flags are used. No page structured
1471	* will be mapped in this function.
1472	*
1473	* @param pVCpu The VMCPU handle.
1474	* @param pPteDst Destination page table entry.
1475	* @param PdeSrc Source page directory entry (i.e. Guest OS page directory entry).
1476	* Can safely assume that only the flags are being used.
1477	* @param PteSrc Source page table entry (i.e. Guest OS page table entry).
1478	* @param pShwPage Pointer to the shadow page.
1479	* @param iPTDst The index into the shadow table.
1480	*
1481	* @remark Not used for 2/4MB pages!
1482	*/
1483	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorker)(PVMCPU pVCpu, PSHWPTE pPteDst, GSTPDE PdeSrc, GSTPTE PteSrc, PPGMPOOLPAGE pShwPage, unsigned iPTDst)
1484	{
1485	if (PteSrc.n.u1Present)
1486	{
1487	PVM pVM = pVCpu->CTX_SUFF(pVM);
1488
1489	# if defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT) \
1490	&& PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
1491	&& (PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64)
1492	if (pShwPage->fDirty)
1493	{
1494	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1495	PX86PTPAE pGstPT;
1496
1497	pGstPT = (PX86PTPAE)&pPool->aDirtyPages[pShwPage->idxDirty][0];
1498	pGstPT->a[iPTDst].u = PteSrc.u;
1499	}
1500	# endif
1501	/*
1502	* Find the ram range.
1503	*/
1504	PPGMPAGE pPage;
1505	int rc = pgmPhysGetPageEx(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK, &pPage);
1506	if (RT_SUCCESS(rc))
1507	{
1508	#ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
1509	/* Try make the page writable if necessary. */
1510	if ( PteSrc.n.u1Write
1511	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
1512	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
1513	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
1514	# endif
1515	&& PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
1516	{
1517	rc = pgmPhysPageMakeWritableUnlocked(pVM, pPage, PteSrc.u & GST_PTE_PG_MASK);
1518	AssertRC(rc);
1519	}
1520	#endif
1521
1522	/** @todo investiage PWT, PCD and PAT. */
1523	/*
1524	* Make page table entry.
1525	*/
1526	SHWPTE PteDst;
1527	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1528	{
1529	/** @todo r=bird: Are we actually handling dirty and access bits for pages with access handlers correctly? No. */
1530	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1531	{
1532	#if PGM_SHW_TYPE == PGM_TYPE_EPT
1533	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage);
1534	PteDst.n.u1Present = 1;
1535	PteDst.n.u1Execute = 1;
1536	PteDst.n.u1IgnorePAT = 1;
1537	PteDst.n.u3EMT = VMX_EPT_MEMTYPE_WB;
1538	/* PteDst.n.u1Write = 0 && PteDst.n.u1Size = 0 */
1539	#else
1540	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT \| X86_PTE_RW))
1541	\| PGM_PAGE_GET_HCPHYS(pPage);
1542	#endif
1543	}
1544	else
1545	{
1546	LogFlow(("SyncPageWorker: monitored page (%RHp) -> mark not present\n", PGM_PAGE_GET_HCPHYS(pPage)));
1547	PteDst.u = 0;
1548	}
1549	/** @todo count these two kinds. */
1550	}
1551	else
1552	{
1553	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1554	/*
1555	* If the page or page directory entry is not marked accessed,
1556	* we mark the page not present.
1557	*/
1558	if (!PteSrc.n.u1Accessed \|\| !PdeSrc.n.u1Accessed)
1559	{
1560	LogFlow(("SyncPageWorker: page and or page directory not accessed -> mark not present\n"));
1561	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,AccessedPage));
1562	PteDst.u = 0;
1563	}
1564	else
1565	/*
1566	* If the page is not flagged as dirty and is writable, then make it read-only, so we can set the dirty bit
1567	* when the page is modified.
1568	*/
1569	if (!PteSrc.n.u1Dirty && (PdeSrc.n.u1Write & PteSrc.n.u1Write))
1570	{
1571	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPage));
1572	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT \| X86_PTE_RW))
1573	\| PGM_PAGE_GET_HCPHYS(pPage)
1574	\| PGM_PTFLAGS_TRACK_DIRTY;
1575	}
1576	else
1577	#endif
1578	{
1579	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageSkipped));
1580	#if PGM_SHW_TYPE == PGM_TYPE_EPT
1581	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage);
1582	PteDst.n.u1Present = 1;
1583	PteDst.n.u1Write = 1;
1584	PteDst.n.u1Execute = 1;
1585	PteDst.n.u1IgnorePAT = 1;
1586	PteDst.n.u3EMT = VMX_EPT_MEMTYPE_WB;
1587	/* PteDst.n.u1Size = 0 */
1588	#else
1589	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT))
1590	\| PGM_PAGE_GET_HCPHYS(pPage);
1591	#endif
1592	}
1593	}
1594
1595	/*
1596	* Make sure only allocated pages are mapped writable.
1597	*/
1598	if ( PteDst.n.u1Write
1599	&& PteDst.n.u1Present
1600	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
1601	{
1602	PteDst.n.u1Write = 0; /** @todo this isn't quite working yet. */
1603	Log3(("SyncPageWorker: write-protecting %RGp pPage=%R[pgmpage]at iPTDst=%d\n", (RTGCPHYS)(PteSrc.u & X86_PTE_PAE_PG_MASK), pPage, iPTDst));
1604	}
1605
1606	#ifdef PGMPOOL_WITH_USER_TRACKING
1607	/*
1608	* Keep user track up to date.
1609	*/
1610	if (PteDst.n.u1Present)
1611	{
1612	if (!pPteDst->n.u1Present)
1613	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1614	else if ((pPteDst->u & SHW_PTE_PG_MASK) != (PteDst.u & SHW_PTE_PG_MASK))
1615	{
1616	Log2(("SyncPageWorker: deref! *pPteDst=%RX64 PteDst=%RX64\n", (uint64_t)pPteDst->u, (uint64_t)PteDst.u));
1617	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1618	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1619	}
1620	}
1621	else if (pPteDst->n.u1Present)
1622	{
1623	Log2(("SyncPageWorker: deref! *pPteDst=%RX64\n", (uint64_t)pPteDst->u));
1624	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1625	}
1626	#endif /* PGMPOOL_WITH_USER_TRACKING */
1627
1628	/*
1629	* Update statistics and commit the entry.
1630	*/
1631	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1632	if (!PteSrc.n.u1Global)
1633	pShwPage->fSeenNonGlobal = true;
1634	#endif
1635	ASMAtomicWriteSize(pPteDst, PteDst.u);
1636	}
1637	/* else MMIO or invalid page, we must handle them manually in the #PF handler. */
1638	/** @todo count these. */
1639	}
1640	else
1641	{
1642	/*
1643	* Page not-present.
1644	*/
1645	Log2(("SyncPageWorker: page not present in Pte\n"));
1646	#ifdef PGMPOOL_WITH_USER_TRACKING
1647	/* Keep user track up to date. */
1648	if (pPteDst->n.u1Present)
1649	{
1650	Log2(("SyncPageWorker: deref! *pPteDst=%RX64\n", (uint64_t)pPteDst->u));
1651	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1652	}
1653	#endif /* PGMPOOL_WITH_USER_TRACKING */
1654	ASMAtomicWriteSize(pPteDst, 0);
1655	/** @todo count these. */
1656	}
1657	}
1658
1659
1660	/**
1661	* Syncs a guest OS page.
1662	*
1663	* There are no conflicts at this point, neither is there any need for
1664	* page table allocations.
1665	*
1666	* @returns VBox status code.
1667	* @returns VINF_PGM_SYNCPAGE_MODIFIED_PDE if it modifies the PDE in any way.
1668	* @param pVCpu The VMCPU handle.
1669	* @param PdeSrc Page directory entry of the guest.
1670	* @param GCPtrPage Guest context page address.
1671	* @param cPages Number of pages to sync (PGM_SYNC_N_PAGES) (default=1).
1672	* @param uErr Fault error (X86_TRAP_PF_*).
1673	*/
1674	PGM_BTH_DECL(int, SyncPage)(PVMCPU pVCpu, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr)
1675	{
1676	PVM pVM = pVCpu->CTX_SUFF(pVM);
1677	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1678	LogFlow(("SyncPage: GCPtrPage=%RGv cPages=%u uErr=%#x\n", GCPtrPage, cPages, uErr));
1679
1680	Assert(PGMIsLockOwner(pVM));
1681
1682	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
1683	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
1684	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
1685	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
1686	&& PGM_SHW_TYPE != PGM_TYPE_EPT
1687
1688	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
1689	bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVCpu) & MSR_K6_EFER_NXE);
1690	# endif
1691
1692	/*
1693	* Assert preconditions.
1694	*/
1695	Assert(PdeSrc.n.u1Present);
1696	Assert(cPages);
1697	# if 0 /* rarely useful; leave for debugging. */
1698	STAM_COUNTER_INC(&pVCpu->pgm.s.StatSyncPagePD[(GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK]);
1699	# endif
1700
1701	/*
1702	* Get the shadow PDE, find the shadow page table in the pool.
1703	*/
1704	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1705	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1706	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(&pVCpu->pgm.s, GCPtrPage);
1707
1708	/* Fetch the pgm pool shadow descriptor. */
1709	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
1710	Assert(pShwPde);
1711
1712	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1713	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1714	PPGMPOOLPAGE pShwPde = NULL;
1715	PX86PDPAE pPDDst;
1716
1717	/* Fetch the pgm pool shadow descriptor. */
1718	int rc2 = pgmShwGetPaePoolPagePD(&pVCpu->pgm.s, GCPtrPage, &pShwPde);
1719	AssertRCSuccessReturn(rc2, rc2);
1720	Assert(pShwPde);
1721
1722	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPde);
1723	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1724
1725	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1726	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1727	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1728	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
1729	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
1730
1731	int rc2 = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
1732	AssertRCSuccessReturn(rc2, rc2);
1733	Assert(pPDDst && pPdptDst);
1734	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1735	# endif
1736	SHWPDE PdeDst = *pPdeDst;
1737	if (!PdeDst.n.u1Present)
1738	{
1739	AssertMsg(pVM->cCpus > 1, ("Unexpected missing PDE p=%p/%RX64\n", pPdeDst, (uint64_t)PdeDst.u));
1740	Log(("CPU%d: SyncPage: Pde at %RGv changed behind our back!\n", GCPtrPage));
1741	return VINF_SUCCESS; /* force the instruction to be executed again. */
1742	}
1743
1744	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1745	Assert(pShwPage);
1746
1747	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1748	/* Fetch the pgm pool shadow descriptor. */
1749	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
1750	Assert(pShwPde);
1751	# endif
1752
1753	# if defined(IN_RC)
1754	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
1755	PGMDynLockHCPage(pVM, (uint8_t *)pPdeDst);
1756	# endif
1757
1758	/*
1759	* Check that the page is present and that the shadow PDE isn't out of sync.
1760	*/
1761	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1762	const bool fBigPage = PdeSrc.b.u1Size;
1763	# else
1764	const bool fBigPage = PdeSrc.b.u1Size && (CPUMGetGuestCR4(pVCpu) & X86_CR4_PSE);
1765	# endif
1766	RTGCPHYS GCPhys;
1767	if (!fBigPage)
1768	{
1769	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
1770	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1771	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1772	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE / 2);
1773	# endif
1774	}
1775	else
1776	{
1777	GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
1778	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1779	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1780	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
1781	# endif
1782	}
1783	if ( pShwPage->GCPhys == GCPhys
1784	&& PdeSrc.n.u1Present
1785	&& (PdeSrc.n.u1User == PdeDst.n.u1User)
1786	&& (PdeSrc.n.u1Write == PdeDst.n.u1Write \|\| !PdeDst.n.u1Write)
1787	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
1788	&& (!fNoExecuteBitValid \|\| PdeSrc.n.u1NoExecute == PdeDst.n.u1NoExecute)
1789	# endif
1790	)
1791	{
1792	/*
1793	* Check that the PDE is marked accessed already.
1794	* Since we set the accessed bit before getting here on a #PF, this
1795	* check is only meant for dealing with non-#PF'ing paths.
1796	*/
1797	if (PdeSrc.n.u1Accessed)
1798	{
1799	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1800	if (!fBigPage)
1801	{
1802	/*
1803	* 4KB Page - Map the guest page table.
1804	*/
1805	PGSTPT pPTSrc;
1806	int rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
1807	if (RT_SUCCESS(rc))
1808	{
1809	# ifdef PGM_SYNC_N_PAGES
1810	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
1811	if ( cPages > 1
1812	&& !(uErr & X86_TRAP_PF_P)
1813	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1814	{
1815	/*
1816	* This code path is currently only taken when the caller is PGMTrap0eHandler
1817	* for non-present pages!
1818	*
1819	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
1820	* deal with locality.
1821	*/
1822	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1823	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1824	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1825	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
1826	# else
1827	const unsigned offPTSrc = 0;
1828	# endif
1829	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
1830	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
1831	iPTDst = 0;
1832	else
1833	iPTDst -= PGM_SYNC_NR_PAGES / 2;
1834	for (; iPTDst < iPTDstEnd; iPTDst++)
1835	{
1836	if (!pPTDst->a[iPTDst].n.u1Present)
1837	{
1838	GSTPTE PteSrc = pPTSrc->a[offPTSrc + iPTDst];
1839	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(GST_PT_MASK << GST_PT_SHIFT)) \| ((offPTSrc + iPTDst) << PAGE_SHIFT);
1840	NOREF(GCPtrCurPage);
1841	#ifndef IN_RING0
1842	/*
1843	* Assuming kernel code will be marked as supervisor - and not as user level
1844	* and executed using a conforming code selector - And marked as readonly.
1845	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
1846	*/
1847	PPGMPAGE pPage;
1848	if ( ((PdeSrc.u & PteSrc.u) & (X86_PTE_RW \| X86_PTE_US))
1849	\|\| iPTDst == ((GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK) /* always sync GCPtrPage */
1850	\|\| !CSAMDoesPageNeedScanning(pVM, (RTRCPTR)GCPtrCurPage)
1851	\|\| ( (pPage = pgmPhysGetPage(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK))
1852	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1853	)
1854	#endif /* else: CSAM not active */
1855	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1856	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
1857	GCPtrCurPage, PteSrc.n.u1Present,
1858	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1859	PteSrc.n.u1User & PdeSrc.n.u1User,
1860	(uint64_t)PteSrc.u,
1861	(uint64_t)pPTDst->a[iPTDst].u,
1862	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1863	}
1864	}
1865	}
1866	else
1867	# endif /* PGM_SYNC_N_PAGES */
1868	{
1869	const unsigned iPTSrc = (GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK;
1870	GSTPTE PteSrc = pPTSrc->a[iPTSrc];
1871	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1872	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1873	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx %s\n",
1874	GCPtrPage, PteSrc.n.u1Present,
1875	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1876	PteSrc.n.u1User & PdeSrc.n.u1User,
1877	(uint64_t)PteSrc.u,
1878	(uint64_t)pPTDst->a[iPTDst].u,
1879	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1880	}
1881	}
1882	else /* MMIO or invalid page: emulated in #PF handler. */
1883	{
1884	LogFlow(("PGM_GCPHYS_2_PTR %RGp failed with %Rrc\n", GCPhys, rc));
1885	Assert(!pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK].n.u1Present);
1886	}
1887	}
1888	else
1889	{
1890	/*
1891	* 4/2MB page - lazy syncing shadow 4K pages.
1892	* (There are many causes of getting here, it's no longer only CSAM.)
1893	*/
1894	/* Calculate the GC physical address of this 4KB shadow page. */
1895	GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc) \| (GCPtrPage & GST_BIG_PAGE_OFFSET_MASK);
1896	/* Find ram range. */
1897	PPGMPAGE pPage;
1898	int rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
1899	if (RT_SUCCESS(rc))
1900	{
1901	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
1902	/* Try make the page writable if necessary. */
1903	if ( PdeSrc.n.u1Write
1904	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
1905	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
1906	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
1907	# endif
1908	&& PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
1909	{
1910	rc = pgmPhysPageMakeWritableUnlocked(pVM, pPage, GCPhys);
1911	AssertRC(rc);
1912	}
1913	# endif
1914
1915	/*
1916	* Make shadow PTE entry.
1917	*/
1918	SHWPTE PteDst;
1919	PteDst.u = (PdeSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT))
1920	\| PGM_PAGE_GET_HCPHYS(pPage);
1921	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1922	{
1923	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1924	PteDst.n.u1Write = 0;
1925	else
1926	PteDst.u = 0;
1927	}
1928	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1929	# ifdef PGMPOOL_WITH_USER_TRACKING
1930	if (PteDst.n.u1Present && !pPTDst->a[iPTDst].n.u1Present)
1931	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1932	# endif
1933	/* Make sure only allocated pages are mapped writable. */
1934	if ( PteDst.n.u1Write
1935	&& PteDst.n.u1Present
1936	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
1937	{
1938	PteDst.n.u1Write = 0; /** @todo this isn't quite working yet... */
1939	Log3(("SyncPage: write-protecting %RGp pPage=%R[pgmpage] at %RGv\n", GCPhys, pPage, GCPtrPage));
1940	}
1941
1942	ASMAtomicWriteSize(&pPTDst->a[iPTDst], PteDst.u);
1943
1944	/*
1945	* If the page is not flagged as dirty and is writable, then make it read-only
1946	* at PD level, so we can set the dirty bit when the page is modified.
1947	*
1948	* ASSUMES that page access handlers are implemented on page table entry level.
1949	* Thus we will first catch the dirty access and set PDE.D and restart. If
1950	* there is an access handler, we'll trap again and let it work on the problem.
1951	*/
1952	/** @todo r=bird: figure out why we need this here, SyncPT should've taken care of this already.
1953	* As for invlpg, it simply frees the whole shadow PT.
1954	* ...It's possibly because the guest clears it and the guest doesn't really tell us... */
1955	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
1956	{
1957	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageBig));
1958	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
1959	PdeDst.n.u1Write = 0;
1960	}
1961	else
1962	{
1963	PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
1964	PdeDst.n.u1Write = PdeSrc.n.u1Write;
1965	}
1966	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
1967	Log2(("SyncPage: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} GCPhys=%RGp%s\n",
1968	GCPtrPage, PdeSrc.n.u1Present, PdeSrc.n.u1Write, PdeSrc.n.u1User, (uint64_t)PdeSrc.u, GCPhys,
1969	PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1970	}
1971	else
1972	LogFlow(("PGM_GCPHYS_2_PTR %RGp (big) failed with %Rrc\n", GCPhys, rc));
1973	}
1974	# if defined(IN_RC)
1975	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
1976	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
1977	# endif
1978	return VINF_SUCCESS;
1979	}
1980	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPagePDNAs));
1981	}
1982	else
1983	{
1984	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPagePDOutOfSync));
1985	Log2(("SyncPage: Out-Of-Sync PDE at %RGp PdeSrc=%RX64 PdeDst=%RX64 (GCPhys %RGp vs %RGp)\n",
1986	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, GCPhys));
1987	}
1988
1989	/*
1990	* Mark the PDE not present. Restart the instruction and let #PF call SyncPT.
1991	* Yea, I'm lazy.
1992	*/
1993	pgmPoolFreeByPage(pPool, pShwPage, pShwPde->idx, iPDDst);
1994	ASMAtomicWriteSize(pPdeDst, 0);
1995
1996	# if defined(IN_RC)
1997	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
1998	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
1999	# endif
2000	PGM_INVL_VCPU_TLBS(pVCpu);
2001	return VINF_PGM_SYNCPAGE_MODIFIED_PDE;
2002
2003	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2004	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2005	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2006	&& !defined(IN_RC)
2007
2008	# ifdef PGM_SYNC_N_PAGES
2009	/*
2010	* Get the shadow PDE, find the shadow page table in the pool.
2011	*/
2012	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2013	X86PDE PdeDst = pgmShwGet32BitPDE(&pVCpu->pgm.s, GCPtrPage);
2014
2015	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2016	X86PDEPAE PdeDst = pgmShwGetPaePDE(&pVCpu->pgm.s, GCPtrPage);
2017
2018	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2019	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2020	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64; NOREF(iPdpt);
2021	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
2022	X86PDEPAE PdeDst;
2023	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
2024
2025	int rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2026	AssertRCSuccessReturn(rc, rc);
2027	Assert(pPDDst && pPdptDst);
2028	PdeDst = pPDDst->a[iPDDst];
2029	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
2030	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2031	PEPTPD pPDDst;
2032	EPTPDE PdeDst;
2033
2034	int rc = pgmShwGetEPTPDPtr(pVCpu, GCPtrPage, NULL, &pPDDst);
2035	if (rc != VINF_SUCCESS)
2036	{
2037	AssertRC(rc);
2038	return rc;
2039	}
2040	Assert(pPDDst);
2041	PdeDst = pPDDst->a[iPDDst];
2042	# endif
2043	AssertMsg(PdeDst.n.u1Present, ("%#llx\n", (uint64_t)PdeDst.u));
2044	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
2045	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2046
2047	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
2048	if ( cPages > 1
2049	&& !(uErr & X86_TRAP_PF_P)
2050	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
2051	{
2052	/*
2053	* This code path is currently only taken when the caller is PGMTrap0eHandler
2054	* for non-present pages!
2055	*
2056	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
2057	* deal with locality.
2058	*/
2059	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2060	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2061	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
2062	iPTDst = 0;
2063	else
2064	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2065	for (; iPTDst < iPTDstEnd; iPTDst++)
2066	{
2067	if (!pPTDst->a[iPTDst].n.u1Present)
2068	{
2069	GSTPTE PteSrc;
2070
2071	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT);
2072
2073	/* Fake the page table entry */
2074	PteSrc.u = GCPtrCurPage;
2075	PteSrc.n.u1Present = 1;
2076	PteSrc.n.u1Dirty = 1;
2077	PteSrc.n.u1Accessed = 1;
2078	PteSrc.n.u1Write = 1;
2079	PteSrc.n.u1User = 1;
2080
2081	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2082
2083	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
2084	GCPtrCurPage, PteSrc.n.u1Present,
2085	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2086	PteSrc.n.u1User & PdeSrc.n.u1User,
2087	(uint64_t)PteSrc.u,
2088	(uint64_t)pPTDst->a[iPTDst].u,
2089	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2090
2091	if (RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)))
2092	break;
2093	}
2094	else
2095	Log4(("%RGv iPTDst=%x pPTDst->a[iPTDst] %RX64\n", (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT), iPTDst, pPTDst->a[iPTDst].u));
2096	}
2097	}
2098	else
2099	# endif /* PGM_SYNC_N_PAGES */
2100	{
2101	GSTPTE PteSrc;
2102	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2103	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT);
2104
2105	/* Fake the page table entry */
2106	PteSrc.u = GCPtrCurPage;
2107	PteSrc.n.u1Present = 1;
2108	PteSrc.n.u1Dirty = 1;
2109	PteSrc.n.u1Accessed = 1;
2110	PteSrc.n.u1Write = 1;
2111	PteSrc.n.u1User = 1;
2112	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2113
2114	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}PteDst=%08llx%s\n",
2115	GCPtrPage, PteSrc.n.u1Present,
2116	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2117	PteSrc.n.u1User & PdeSrc.n.u1User,
2118	(uint64_t)PteSrc.u,
2119	(uint64_t)pPTDst->a[iPTDst].u,
2120	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2121	}
2122	return VINF_SUCCESS;
2123
2124	#else
2125	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
2126	return VERR_INTERNAL_ERROR;
2127	#endif
2128	}
2129
2130
2131	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
2132	/**
2133	* Investigate page fault and handle write protection page faults caused by
2134	* dirty bit tracking.
2135	*
2136	* @returns VBox status code.
2137	* @param pVCpu The VMCPU handle.
2138	* @param uErr Page fault error code.
2139	* @param pPdeDst Shadow page directory entry.
2140	* @param pPdeSrc Guest page directory entry.
2141	* @param GCPtrPage Guest context page address.
2142	*/
2143	PGM_BTH_DECL(int, CheckPageFault)(PVMCPU pVCpu, uint32_t uErr, PSHWPDE pPdeDst, PGSTPDE pPdeSrc, RTGCPTR GCPtrPage)
2144	{
2145	bool fWriteProtect = !!(CPUMGetGuestCR0(pVCpu) & X86_CR0_WP);
2146	bool fUserLevelFault = !!(uErr & X86_TRAP_PF_US);
2147	bool fWriteFault = !!(uErr & X86_TRAP_PF_RW);
2148	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2149	bool fBigPagesSupported = true;
2150	# else
2151	bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PSE);
2152	# endif
2153	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2154	bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVCpu) & MSR_K6_EFER_NXE);
2155	# endif
2156	unsigned uPageFaultLevel;
2157	int rc;
2158	PVM pVM = pVCpu->CTX_SUFF(pVM);
2159	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2160
2161	Assert(PGMIsLockOwner(pVM));
2162
2163	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2164	LogFlow(("CheckPageFault: GCPtrPage=%RGv uErr=%#x PdeSrc=%08x\n", GCPtrPage, uErr, pPdeSrc->u));
2165
2166	# if PGM_GST_TYPE == PGM_TYPE_PAE \
2167	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
2168
2169	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2170	PX86PML4E pPml4eSrc;
2171	PX86PDPE pPdpeSrc;
2172
2173	pPdpeSrc = pgmGstGetLongModePDPTPtr(&pVCpu->pgm.s, GCPtrPage, &pPml4eSrc);
2174	Assert(pPml4eSrc);
2175
2176	/*
2177	* Real page fault? (PML4E level)
2178	*/
2179	if ( (uErr & X86_TRAP_PF_RSVD)
2180	\|\| !pPml4eSrc->n.u1Present
2181	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPml4eSrc->n.u1NoExecute)
2182	\|\| (fWriteFault && !pPml4eSrc->n.u1Write && (fUserLevelFault \|\| fWriteProtect))
2183	\|\| (fUserLevelFault && !pPml4eSrc->n.u1User)
2184	)
2185	{
2186	uPageFaultLevel = 0;
2187	goto l_UpperLevelPageFault;
2188	}
2189	Assert(pPdpeSrc);
2190
2191	# else /* PAE */
2192	PX86PDPE pPdpeSrc = pgmGstGetPaePDPEPtr(&pVCpu->pgm.s, GCPtrPage);
2193	# endif /* PAE */
2194
2195	/*
2196	* Real page fault? (PDPE level)
2197	*/
2198	if ( (uErr & X86_TRAP_PF_RSVD)
2199	\|\| !pPdpeSrc->n.u1Present
2200	# if PGM_GST_TYPE == PGM_TYPE_AMD64 /* NX, r/w, u/s bits in the PDPE are long mode only */
2201	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPdpeSrc->lm.u1NoExecute)
2202	\|\| (fWriteFault && !pPdpeSrc->lm.u1Write && (fUserLevelFault \|\| fWriteProtect))
2203	\|\| (fUserLevelFault && !pPdpeSrc->lm.u1User)
2204	# endif
2205	)
2206	{
2207	uPageFaultLevel = 1;
2208	goto l_UpperLevelPageFault;
2209	}
2210	# endif
2211
2212	/*
2213	* Real page fault? (PDE level)
2214	*/
2215	if ( (uErr & X86_TRAP_PF_RSVD)
2216	\|\| !pPdeSrc->n.u1Present
2217	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2218	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPdeSrc->n.u1NoExecute)
2219	# endif
2220	\|\| (fWriteFault && !pPdeSrc->n.u1Write && (fUserLevelFault \|\| fWriteProtect))
2221	\|\| (fUserLevelFault && !pPdeSrc->n.u1User) )
2222	{
2223	uPageFaultLevel = 2;
2224	goto l_UpperLevelPageFault;
2225	}
2226
2227	/*
2228	* First check the easy case where the page directory has been marked read-only to track
2229	* the dirty bit of an emulated BIG page
2230	*/
2231	if (pPdeSrc->b.u1Size && fBigPagesSupported)
2232	{
2233	/* Mark guest page directory as accessed */
2234	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2235	pPml4eSrc->n.u1Accessed = 1;
2236	pPdpeSrc->lm.u1Accessed = 1;
2237	# endif
2238	pPdeSrc->b.u1Accessed = 1;
2239
2240	/*
2241	* Only write protection page faults are relevant here.
2242	*/
2243	if (fWriteFault)
2244	{
2245	/* Mark guest page directory as dirty (BIG page only). */
2246	pPdeSrc->b.u1Dirty = 1;
2247
2248	if (pPdeDst->n.u1Present)
2249	{
2250	if (pPdeDst->u & PGM_PDFLAGS_TRACK_DIRTY)
2251	{
2252	SHWPDE PdeDst = *pPdeDst;
2253
2254	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageTrap));
2255	Assert(pPdeSrc->b.u1Write);
2256
2257	/* Note: No need to invalidate this entry on other VCPUs as a stale TLB entry will not harm; write access will simply
2258	* fault again and take this path to only invalidate the entry.
2259	*/
2260	PdeDst.n.u1Write = 1;
2261	PdeDst.n.u1Accessed = 1;
2262	PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
2263	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2264	PGM_INVL_BIG_PG(pVCpu, GCPtrPage);
2265	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2266	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2267	}
2268	# ifdef IN_RING0
2269	else
2270	/* Check for stale TLB entry; only applies to the SMP guest case. */
2271	if ( pVM->cCpus > 1
2272	&& pPdeDst->n.u1Write
2273	&& pPdeDst->n.u1Accessed)
2274	{
2275	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPdeDst->u & SHW_PDE_PG_MASK);
2276	if (pShwPage)
2277	{
2278	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2279	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2280	if ( pPteDst->n.u1Present
2281	&& pPteDst->n.u1Write)
2282	{
2283	/* Stale TLB entry. */
2284	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageStale));
2285	PGM_INVL_PG(pVCpu, GCPtrPage);
2286
2287	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2288	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2289	}
2290	}
2291	}
2292	# endif /* IN_RING0 */
2293	}
2294	}
2295	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2296	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2297	}
2298	/* else: 4KB page table */
2299
2300	/*
2301	* Map the guest page table.
2302	*/
2303	PGSTPT pPTSrc;
2304	rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & GST_PDE_PG_MASK, &pPTSrc);
2305	if (RT_SUCCESS(rc))
2306	{
2307	/*
2308	* Real page fault?
2309	*/
2310	PGSTPTE pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
2311	const GSTPTE PteSrc = *pPteSrc;
2312	if ( !PteSrc.n.u1Present
2313	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2314	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && PteSrc.n.u1NoExecute)
2315	# endif
2316	\|\| (fWriteFault && !PteSrc.n.u1Write && (fUserLevelFault \|\| fWriteProtect))
2317	\|\| (fUserLevelFault && !PteSrc.n.u1User)
2318	)
2319	{
2320	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyTrackRealPF));
2321	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2322	LogFlow(("CheckPageFault: real page fault at %RGv PteSrc.u=%08x (2)\n", GCPtrPage, PteSrc.u));
2323
2324	/* Check the present bit as the shadow tables can cause different error codes by being out of sync.
2325	* See the 2nd case above as well.
2326	*/
2327	if (pPdeSrc->n.u1Present && pPteSrc->n.u1Present)
2328	TRPMSetErrorCode(pVCpu, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
2329
2330	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2331	return VINF_EM_RAW_GUEST_TRAP;
2332	}
2333	LogFlow(("CheckPageFault: page fault at %RGv PteSrc.u=%08x\n", GCPtrPage, PteSrc.u));
2334
2335	/*
2336	* Set the accessed bits in the page directory and the page table.
2337	*/
2338	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2339	pPml4eSrc->n.u1Accessed = 1;
2340	pPdpeSrc->lm.u1Accessed = 1;
2341	# endif
2342	pPdeSrc->n.u1Accessed = 1;
2343	pPteSrc->n.u1Accessed = 1;
2344
2345	/*
2346	* Only write protection page faults are relevant here.
2347	*/
2348	if (fWriteFault)
2349	{
2350	/* Write access, so mark guest entry as dirty. */
2351	# ifdef VBOX_WITH_STATISTICS
2352	if (!pPteSrc->n.u1Dirty)
2353	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtiedPage));
2354	else
2355	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageAlreadyDirty));
2356	# endif
2357
2358	pPteSrc->n.u1Dirty = 1;
2359
2360	if (pPdeDst->n.u1Present)
2361	{
2362	#ifndef IN_RING0
2363	/* Bail out here as pgmPoolGetPageByHCPhys will return NULL and we'll crash below.
2364	* Our individual shadow handlers will provide more information and force a fatal exit.
2365	*/
2366	if (MMHyperIsInsideArea(pVM, (RTGCPTR)GCPtrPage))
2367	{
2368	LogRel(("CheckPageFault: write to hypervisor region %RGv\n", GCPtrPage));
2369	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2370	return VINF_SUCCESS;
2371	}
2372	#endif
2373	/*
2374	* Map shadow page table.
2375	*/
2376	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPdeDst->u & SHW_PDE_PG_MASK);
2377	if (pShwPage)
2378	{
2379	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2380	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2381	if (pPteDst->n.u1Present) /** @todo Optimize accessed bit emulation? */
2382	{
2383	if (pPteDst->u & PGM_PTFLAGS_TRACK_DIRTY)
2384	{
2385	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, pPteSrc->u & GST_PTE_PG_MASK);
2386	SHWPTE PteDst = *pPteDst;
2387
2388	LogFlow(("DIRTY page trap addr=%RGv\n", GCPtrPage));
2389	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageTrap));
2390
2391	Assert(pPteSrc->n.u1Write);
2392
2393	/* Note: No need to invalidate this entry on other VCPUs as a stale TLB entry will not harm; write access will simply
2394	* fault again and take this path to only invalidate the entry.
2395	*/
2396	if (RT_LIKELY(pPage))
2397	{
2398	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2399	/* Assuming write handlers here as the PTE is present (otherwise we wouldn't be here). */
2400	PteDst.n.u1Write = 0;
2401	else
2402	{
2403	if ( PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED
2404	&& PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
2405	{
2406	rc = pgmPhysPageMakeWritableUnlocked(pVM, pPage, pPteSrc->u & GST_PTE_PG_MASK);
2407	AssertRC(rc);
2408	}
2409	if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED)
2410	PteDst.n.u1Write = 1;
2411	else
2412	PteDst.n.u1Write = 0;
2413	}
2414	}
2415	else
2416	PteDst.n.u1Write = 1;
2417
2418	PteDst.n.u1Dirty = 1;
2419	PteDst.n.u1Accessed = 1;
2420	PteDst.au32[0] &= ~PGM_PTFLAGS_TRACK_DIRTY;
2421	ASMAtomicWriteSize(pPteDst, PteDst.u);
2422	PGM_INVL_PG(pVCpu, GCPtrPage);
2423
2424	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2425	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2426	}
2427	# ifdef IN_RING0
2428	else
2429	/* Check for stale TLB entry; only applies to the SMP guest case. */
2430	if ( pVM->cCpus > 1
2431	&& pPteDst->n.u1Write == 1
2432	&& pPteDst->n.u1Accessed == 1)
2433	{
2434	/* Stale TLB entry. */
2435	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageStale));
2436	PGM_INVL_PG(pVCpu, GCPtrPage);
2437
2438	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2439	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2440	}
2441	# endif
2442	}
2443	}
2444	else
2445	AssertMsgFailed(("pgmPoolGetPageByHCPhys %RGp failed!\n", pPdeDst->u & SHW_PDE_PG_MASK));
2446	}
2447	}
2448	/** @todo Optimize accessed bit emulation? */
2449	# ifdef VBOX_STRICT
2450	/*
2451	* Sanity check.
2452	*/
2453	else if ( !pPteSrc->n.u1Dirty
2454	&& (pPdeSrc->n.u1Write & pPteSrc->n.u1Write)
2455	&& pPdeDst->n.u1Present)
2456	{
2457	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPdeDst->u & SHW_PDE_PG_MASK);
2458	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2459	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2460	if ( pPteDst->n.u1Present
2461	&& pPteDst->n.u1Write)
2462	LogFlow(("Writable present page %RGv not marked for dirty bit tracking!!!\n", GCPtrPage));
2463	}
2464	# endif /* VBOX_STRICT */
2465	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2466	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2467	}
2468	AssertRC(rc);
2469	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2470	return rc;
2471
2472
2473	l_UpperLevelPageFault:
2474	/*
2475	* Pagefault detected while checking the PML4E, PDPE or PDE.
2476	* Single exit handler to get rid of duplicate code paths.
2477	*/
2478	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyTrackRealPF));
2479	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2480	Log(("CheckPageFault: real page fault at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2481
2482	if (
2483	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2484	pPml4eSrc->n.u1Present &&
2485	# endif
2486	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
2487	pPdpeSrc->n.u1Present &&
2488	# endif
2489	pPdeSrc->n.u1Present)
2490	{
2491	/* Check the present bit as the shadow tables can cause different error codes by being out of sync. */
2492	if (pPdeSrc->b.u1Size && fBigPagesSupported)
2493	{
2494	TRPMSetErrorCode(pVCpu, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
2495	}
2496	else
2497	{
2498	/*
2499	* Map the guest page table.
2500	*/
2501	PGSTPT pPTSrc2;
2502	rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & GST_PDE_PG_MASK, &pPTSrc2);
2503	if (RT_SUCCESS(rc))
2504	{
2505	PGSTPTE pPteSrc = &pPTSrc2->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
2506	const GSTPTE PteSrc = *pPteSrc;
2507	if (pPteSrc->n.u1Present)
2508	TRPMSetErrorCode(pVCpu, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
2509	}
2510	AssertRC(rc);
2511	}
2512	}
2513	return VINF_EM_RAW_GUEST_TRAP;
2514	}
2515	#endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
2516
2517
2518	/**
2519	* Sync a shadow page table.
2520	*
2521	* The shadow page table is not present. This includes the case where
2522	* there is a conflict with a mapping.
2523	*
2524	* @returns VBox status code.
2525	* @param pVCpu The VMCPU handle.
2526	* @param iPD Page directory index.
2527	* @param pPDSrc Source page directory (i.e. Guest OS page directory).
2528	* Assume this is a temporary mapping.
2529	* @param GCPtrPage GC Pointer of the page that caused the fault
2530	*/
2531	PGM_BTH_DECL(int, SyncPT)(PVMCPU pVCpu, unsigned iPDSrc, PGSTPD pPDSrc, RTGCPTR GCPtrPage)
2532	{
2533	PVM pVM = pVCpu->CTX_SUFF(pVM);
2534	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2535
2536	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2537	#if 0 /* rarely useful; leave for debugging. */
2538	STAM_COUNTER_INC(&pVCpu->pgm.s.StatSyncPtPD[iPDSrc]);
2539	#endif
2540	LogFlow(("SyncPT: GCPtrPage=%RGv\n", GCPtrPage));
2541
2542	Assert(PGMIsLocked(pVM));
2543
2544	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
2545	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
2546	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
2547	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2548	&& PGM_SHW_TYPE != PGM_TYPE_EPT
2549
2550	int rc = VINF_SUCCESS;
2551
2552	/*
2553	* Validate input a little bit.
2554	*/
2555	AssertMsg(iPDSrc == ((GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK), ("iPDSrc=%x GCPtrPage=%RGv\n", iPDSrc, GCPtrPage));
2556	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2557	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
2558	PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(&pVCpu->pgm.s, GCPtrPage);
2559
2560	/* Fetch the pgm pool shadow descriptor. */
2561	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
2562	Assert(pShwPde);
2563
2564	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2565	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2566	PPGMPOOLPAGE pShwPde = NULL;
2567	PX86PDPAE pPDDst;
2568	PSHWPDE pPdeDst;
2569
2570	/* Fetch the pgm pool shadow descriptor. */
2571	rc = pgmShwGetPaePoolPagePD(&pVCpu->pgm.s, GCPtrPage, &pShwPde);
2572	AssertRCSuccessReturn(rc, rc);
2573	Assert(pShwPde);
2574
2575	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPde);
2576	pPdeDst = &pPDDst->a[iPDDst];
2577
2578	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2579	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
2580	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2581	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
2582	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
2583	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2584	AssertRCSuccessReturn(rc, rc);
2585	Assert(pPDDst);
2586	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2587	# endif
2588	SHWPDE PdeDst = *pPdeDst;
2589
2590	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2591	/* Fetch the pgm pool shadow descriptor. */
2592	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
2593	Assert(pShwPde);
2594	# endif
2595
2596	# ifndef PGM_WITHOUT_MAPPINGS
2597	/*
2598	* Check for conflicts.
2599	* GC: In case of a conflict we'll go to Ring-3 and do a full SyncCR3.
2600	* HC: Simply resolve the conflict.
2601	*/
2602	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
2603	{
2604	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
2605	# ifndef IN_RING3
2606	Log(("SyncPT: Conflict at %RGv\n", GCPtrPage));
2607	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2608	return VERR_ADDRESS_CONFLICT;
2609	# else
2610	PPGMMAPPING pMapping = pgmGetMapping(pVM, (RTGCPTR)GCPtrPage);
2611	Assert(pMapping);
2612	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2613	rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2614	# elif PGM_GST_TYPE == PGM_TYPE_PAE
2615	rc = pgmR3SyncPTResolveConflictPAE(pVM, pMapping, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2616	# else
2617	AssertFailed(); /* can't happen for amd64 */
2618	# endif
2619	if (RT_FAILURE(rc))
2620	{
2621	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2622	return rc;
2623	}
2624	PdeDst = *pPdeDst;
2625	# endif
2626	}
2627	# else /* PGM_WITHOUT_MAPPINGS */
2628	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
2629	# endif /* PGM_WITHOUT_MAPPINGS */
2630	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
2631
2632	# if defined(IN_RC)
2633	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
2634	PGMDynLockHCPage(pVM, (uint8_t *)pPdeDst);
2635	# endif
2636
2637	/*
2638	* Sync page directory entry.
2639	*/
2640	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
2641	if (PdeSrc.n.u1Present)
2642	{
2643	/*
2644	* Allocate & map the page table.
2645	*/
2646	PSHWPT pPTDst;
2647	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2648	const bool fPageTable = !PdeSrc.b.u1Size;
2649	# else
2650	const bool fPageTable = !PdeSrc.b.u1Size \|\| !(CPUMGetGuestCR4(pVCpu) & X86_CR4_PSE);
2651	# endif
2652	PPGMPOOLPAGE pShwPage;
2653	RTGCPHYS GCPhys;
2654	if (fPageTable)
2655	{
2656	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
2657	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2658	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2659	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE / 2);
2660	# endif
2661	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, pShwPde->idx, iPDDst, &pShwPage);
2662	}
2663	else
2664	{
2665	PGMPOOLACCESS enmAccess;
2666
2667	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2668	const bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVCpu) & MSR_K6_EFER_NXE);
2669	const bool fNoExecute = fNoExecuteBitValid && PdeSrc.n.u1NoExecute;
2670	# else
2671	const bool fNoExecute = false;
2672	# endif
2673
2674	GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
2675	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2676	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
2677	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
2678	# endif
2679	/* Determine the right kind of large page to avoid incorrect cached entry reuse. */
2680	if (PdeSrc.n.u1User)
2681	{
2682	if (PdeSrc.n.u1Write)
2683	enmAccess = (fNoExecute) ? PGMPOOLACCESS_USER_RW_NX : PGMPOOLACCESS_USER_RW;
2684	else
2685	enmAccess = (fNoExecute) ? PGMPOOLACCESS_USER_R_NX : PGMPOOLACCESS_USER_R;
2686	}
2687	else
2688	{
2689	if (PdeSrc.n.u1Write)
2690	enmAccess = (fNoExecute) ? PGMPOOLACCESS_SUPERVISOR_RW_NX : PGMPOOLACCESS_SUPERVISOR_RW;
2691	else
2692	enmAccess = (fNoExecute) ? PGMPOOLACCESS_SUPERVISOR_R_NX : PGMPOOLACCESS_SUPERVISOR_R;
2693	}
2694	rc = pgmPoolAllocEx(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_BIG, enmAccess, pShwPde->idx, iPDDst, &pShwPage);
2695	}
2696	if (rc == VINF_SUCCESS)
2697	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2698	else if (rc == VINF_PGM_CACHED_PAGE)
2699	{
2700	/*
2701	* The PT was cached, just hook it up.
2702	*/
2703	if (fPageTable)
2704	PdeDst.u = pShwPage->Core.Key
2705	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2706	else
2707	{
2708	PdeDst.u = pShwPage->Core.Key
2709	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2710	/* (see explanation and assumptions further down.) */
2711	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
2712	{
2713	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageBig));
2714	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2715	PdeDst.b.u1Write = 0;
2716	}
2717	}
2718	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2719	# if defined(IN_RC)
2720	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
2721	# endif
2722	return VINF_SUCCESS;
2723	}
2724	else if (rc == VERR_PGM_POOL_FLUSHED)
2725	{
2726	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2727	# if defined(IN_RC)
2728	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
2729	# endif
2730	return VINF_PGM_SYNC_CR3;
2731	}
2732	else
2733	AssertMsgFailedReturn(("rc=%Rrc\n", rc), VERR_INTERNAL_ERROR);
2734	PdeDst.u &= X86_PDE_AVL_MASK;
2735	PdeDst.u \|= pShwPage->Core.Key;
2736
2737	/*
2738	* Page directory has been accessed (this is a fault situation, remember).
2739	*/
2740	pPDSrc->a[iPDSrc].n.u1Accessed = 1;
2741	if (fPageTable)
2742	{
2743	/*
2744	* Page table - 4KB.
2745	*
2746	* Sync all or just a few entries depending on PGM_SYNC_N_PAGES.
2747	*/
2748	Log2(("SyncPT: 4K %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx}\n",
2749	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u));
2750	PGSTPT pPTSrc;
2751	rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
2752	if (RT_SUCCESS(rc))
2753	{
2754	/*
2755	* Start by syncing the page directory entry so CSAM's TLB trick works.
2756	*/
2757	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| X86_PDE_AVL_MASK))
2758	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2759	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2760	# if defined(IN_RC)
2761	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
2762	# endif
2763
2764	/*
2765	* Directory/page user or supervisor privilege: (same goes for read/write)
2766	*
2767	* Directory Page Combined
2768	* U/S U/S U/S
2769	* 0 0 0
2770	* 0 1 0
2771	* 1 0 0
2772	* 1 1 1
2773	*
2774	* Simple AND operation. Table listed for completeness.
2775	*
2776	*/
2777	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT4K));
2778	# ifdef PGM_SYNC_N_PAGES
2779	unsigned iPTBase = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2780	unsigned iPTDst = iPTBase;
2781	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2782	if (iPTDst <= PGM_SYNC_NR_PAGES / 2)
2783	iPTDst = 0;
2784	else
2785	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2786	# else /* !PGM_SYNC_N_PAGES */
2787	unsigned iPTDst = 0;
2788	const unsigned iPTDstEnd = RT_ELEMENTS(pPTDst->a);
2789	# endif /* !PGM_SYNC_N_PAGES */
2790	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2791	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2792	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
2793	# else
2794	const unsigned offPTSrc = 0;
2795	# endif
2796	for (; iPTDst < iPTDstEnd; iPTDst++)
2797	{
2798	const unsigned iPTSrc = iPTDst + offPTSrc;
2799	const GSTPTE PteSrc = pPTSrc->a[iPTSrc];
2800
2801	if (PteSrc.n.u1Present) /* we've already cleared it above */
2802	{
2803	# ifndef IN_RING0
2804	/*
2805	* Assuming kernel code will be marked as supervisor - and not as user level
2806	* and executed using a conforming code selector - And marked as readonly.
2807	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
2808	*/
2809	PPGMPAGE pPage;
2810	if ( ((PdeSrc.u & pPTSrc->a[iPTSrc].u) & (X86_PTE_RW \| X86_PTE_US))
2811	\|\| !CSAMDoesPageNeedScanning(pVM, (RTRCPTR)((iPDSrc << GST_PD_SHIFT) \| (iPTSrc << PAGE_SHIFT)))
2812	\|\| ( (pPage = pgmPhysGetPage(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK))
2813	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2814	)
2815	# endif
2816	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2817	Log2(("SyncPT: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s dst.raw=%08llx iPTSrc=%x PdeSrc.u=%x physpte=%RGp\n",
2818	(RTGCPTR)(((RTGCPTR)iPDSrc << GST_PD_SHIFT) \| ((RTGCPTR)iPTSrc << PAGE_SHIFT)),
2819	PteSrc.n.u1Present,
2820	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2821	PteSrc.n.u1User & PdeSrc.n.u1User,
2822	(uint64_t)PteSrc.u,
2823	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : "", pPTDst->a[iPTDst].u, iPTSrc, PdeSrc.au32[0],
2824	(RTGCPHYS)((PdeSrc.u & GST_PDE_PG_MASK) + iPTSrc*sizeof(PteSrc)) ));
2825	}
2826	} /* for PTEs */
2827	}
2828	}
2829	else
2830	{
2831	/*
2832	* Big page - 2/4MB.
2833	*
2834	* We'll walk the ram range list in parallel and optimize lookups.
2835	* We will only sync on shadow page table at a time.
2836	*/
2837	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT4M));
2838
2839	/**
2840	* @todo It might be more efficient to sync only a part of the 4MB page (similar to what we do for 4kb PDs).
2841	*/
2842
2843	/*
2844	* Start by syncing the page directory entry.
2845	*/
2846	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| (X86_PDE_AVL_MASK & ~PGM_PDFLAGS_TRACK_DIRTY)))
2847	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2848
2849	/*
2850	* If the page is not flagged as dirty and is writable, then make it read-only
2851	* at PD level, so we can set the dirty bit when the page is modified.
2852	*
2853	* ASSUMES that page access handlers are implemented on page table entry level.
2854	* Thus we will first catch the dirty access and set PDE.D and restart. If
2855	* there is an access handler, we'll trap again and let it work on the problem.
2856	*/
2857	/** @todo move the above stuff to a section in the PGM documentation. */
2858	Assert(!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY));
2859	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
2860	{
2861	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageBig));
2862	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2863	PdeDst.b.u1Write = 0;
2864	}
2865	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2866	# if defined(IN_RC)
2867	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
2868	# endif
2869
2870	/*
2871	* Fill the shadow page table.
2872	*/
2873	/* Get address and flags from the source PDE. */
2874	SHWPTE PteDstBase;
2875	PteDstBase.u = PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT);
2876
2877	/* Loop thru the entries in the shadow PT. */
2878	const RTGCPTR GCPtr = (GCPtrPage >> SHW_PD_SHIFT) << SHW_PD_SHIFT; NOREF(GCPtr);
2879	Log2(("SyncPT: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} Shw=%RGv GCPhys=%RGp %s\n",
2880	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u, GCPtr,
2881	GCPhys, PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2882	PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
2883	unsigned iPTDst = 0;
2884	while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2885	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
2886	{
2887	/* Advance ram range list. */
2888	while (pRam && GCPhys > pRam->GCPhysLast)
2889	pRam = pRam->CTX_SUFF(pNext);
2890	if (pRam && GCPhys >= pRam->GCPhys)
2891	{
2892	unsigned iHCPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
2893	do
2894	{
2895	/* Make shadow PTE. */
2896	PPGMPAGE pPage = &pRam->aPages[iHCPage];
2897	SHWPTE PteDst;
2898
2899	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
2900	/* Try make the page writable if necessary. */
2901	if ( PteDstBase.n.u1Write
2902	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
2903	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
2904	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
2905	# endif
2906	&& PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
2907	{
2908	rc = pgmPhysPageMakeWritableUnlocked(pVM, pPage, GCPhys);
2909	AssertRCReturn(rc, rc);
2910	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
2911	break;
2912	}
2913	# endif
2914
2915	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2916	{
2917	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
2918	{
2919	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage) \| PteDstBase.u;
2920	PteDst.n.u1Write = 0;
2921	}
2922	else
2923	PteDst.u = 0;
2924	}
2925	# ifndef IN_RING0
2926	/*
2927	* Assuming kernel code will be marked as supervisor and not as user level and executed
2928	* using a conforming code selector. Don't check for readonly, as that implies the whole
2929	* 4MB can be code or readonly data. Linux enables write access for its large pages.
2930	*/
2931	else if ( !PdeSrc.n.u1User
2932	&& CSAMDoesPageNeedScanning(pVM, (RTRCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT))))
2933	PteDst.u = 0;
2934	# endif
2935	else
2936	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage) \| PteDstBase.u;
2937
2938	/* Only map writable pages writable. */
2939	if ( PteDst.n.u1Write
2940	&& PteDst.n.u1Present
2941	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
2942	{
2943	PteDst.n.u1Write = 0; /** @todo this isn't quite working yet... */
2944	Log3(("SyncPT: write-protecting %RGp pPage=%R[pgmpage] at %RGv\n", GCPhys, pPage, (RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT))));
2945	}
2946
2947	# ifdef PGMPOOL_WITH_USER_TRACKING
2948	if (PteDst.n.u1Present)
2949	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
2950	# endif
2951	/* commit it */
2952	pPTDst->a[iPTDst] = PteDst;
2953	Log4(("SyncPT: BIG %RGv PteDst:{P=%d RW=%d U=%d raw=%08llx}%s\n",
2954	(RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT)), PteDst.n.u1Present, PteDst.n.u1Write, PteDst.n.u1User, (uint64_t)PteDst.u,
2955	PteDst.u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2956
2957	/* advance */
2958	GCPhys += PAGE_SIZE;
2959	iHCPage++;
2960	iPTDst++;
2961	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2962	&& GCPhys <= pRam->GCPhysLast);
2963	}
2964	else if (pRam)
2965	{
2966	Log(("Invalid pages at %RGp\n", GCPhys));
2967	do
2968	{
2969	pPTDst->a[iPTDst].u = 0; /* MMIO or invalid page, we must handle them manually. */
2970	GCPhys += PAGE_SIZE;
2971	iPTDst++;
2972	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2973	&& GCPhys < pRam->GCPhys);
2974	}
2975	else
2976	{
2977	Log(("Invalid pages at %RGp (2)\n", GCPhys));
2978	for ( ; iPTDst < RT_ELEMENTS(pPTDst->a); iPTDst++)
2979	pPTDst->a[iPTDst].u = 0; /* MMIO or invalid page, we must handle them manually. */
2980	}
2981	} /* while more PTEs */
2982	} /* 4KB / 4MB */
2983	}
2984	else
2985	AssertRelease(!PdeDst.n.u1Present);
2986
2987	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2988	if (RT_FAILURE(rc))
2989	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPTFailed));
2990	return rc;
2991
2992	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2993	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2994	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2995	&& !defined(IN_RC)
2996
2997	/*
2998	* Validate input a little bit.
2999	*/
3000	int rc = VINF_SUCCESS;
3001	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3002	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
3003	PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(&pVCpu->pgm.s, GCPtrPage);
3004
3005	/* Fetch the pgm pool shadow descriptor. */
3006	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
3007	Assert(pShwPde);
3008
3009	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3010	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
3011	PPGMPOOLPAGE pShwPde = NULL; /* initialized to shut up gcc */
3012	PX86PDPAE pPDDst;
3013	PSHWPDE pPdeDst;
3014
3015	/* Fetch the pgm pool shadow descriptor. */
3016	rc = pgmShwGetPaePoolPagePD(&pVCpu->pgm.s, GCPtrPage, &pShwPde);
3017	AssertRCSuccessReturn(rc, rc);
3018	Assert(pShwPde);
3019
3020	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPde);
3021	pPdeDst = &pPDDst->a[iPDDst];
3022
3023	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3024	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3025	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
3026	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
3027	PX86PDPT pPdptDst= NULL; /* initialized to shut up gcc */
3028	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
3029	AssertRCSuccessReturn(rc, rc);
3030	Assert(pPDDst);
3031	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
3032
3033	/* Fetch the pgm pool shadow descriptor. */
3034	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
3035	Assert(pShwPde);
3036
3037	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
3038	const unsigned iPdpt = (GCPtrPage >> EPT_PDPT_SHIFT) & EPT_PDPT_MASK;
3039	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3040	PEPTPD pPDDst;
3041	PEPTPDPT pPdptDst;
3042
3043	rc = pgmShwGetEPTPDPtr(pVCpu, GCPtrPage, &pPdptDst, &pPDDst);
3044	if (rc != VINF_SUCCESS)
3045	{
3046	AssertRC(rc);
3047	return rc;
3048	}
3049	Assert(pPDDst);
3050	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
3051
3052	/* Fetch the pgm pool shadow descriptor. */
3053	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & EPT_PDPTE_PG_MASK);
3054	Assert(pShwPde);
3055	# endif
3056	SHWPDE PdeDst = *pPdeDst;
3057
3058	Assert(!(PdeDst.u & PGM_PDFLAGS_MAPPING));
3059	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
3060
3061	GSTPDE PdeSrc;
3062	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
3063	PdeSrc.n.u1Present = 1;
3064	PdeSrc.n.u1Write = 1;
3065	PdeSrc.n.u1Accessed = 1;
3066	PdeSrc.n.u1User = 1;
3067
3068	/*
3069	* Allocate & map the page table.
3070	*/
3071	PSHWPT pPTDst;
3072	PPGMPOOLPAGE pShwPage;
3073	RTGCPHYS GCPhys;
3074
3075	/* Virtual address = physical address */
3076	GCPhys = GCPtrPage & X86_PAGE_4K_BASE_MASK;
3077	rc = pgmPoolAlloc(pVM, GCPhys & ~(RT_BIT_64(SHW_PD_SHIFT) - 1), BTH_PGMPOOLKIND_PT_FOR_PT, pShwPde->idx, iPDDst, &pShwPage);
3078
3079	if ( rc == VINF_SUCCESS
3080	\|\| rc == VINF_PGM_CACHED_PAGE)
3081	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
3082	else
3083	AssertMsgFailedReturn(("rc=%Rrc\n", rc), VERR_INTERNAL_ERROR);
3084
3085	PdeDst.u &= X86_PDE_AVL_MASK;
3086	PdeDst.u \|= pShwPage->Core.Key;
3087	PdeDst.n.u1Present = 1;
3088	PdeDst.n.u1Write = 1;
3089	# if PGM_SHW_TYPE == PGM_TYPE_EPT
3090	PdeDst.n.u1Execute = 1;
3091	# else
3092	PdeDst.n.u1User = 1;
3093	PdeDst.n.u1Accessed = 1;
3094	# endif
3095	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
3096
3097	pgmLock(pVM);
3098	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, PGM_SYNC_NR_PAGES, 0 /* page not present */);
3099	pgmUnlock(pVM);
3100	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
3101	return rc;
3102
3103	#else
3104	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_SHW_TYPE, PGM_GST_TYPE));
3105	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
3106	return VERR_INTERNAL_ERROR;
3107	#endif
3108	}
3109
3110
3111
3112	/**
3113	* Prefetch a page/set of pages.
3114	*
3115	* Typically used to sync commonly used pages before entering raw mode
3116	* after a CR3 reload.
3117	*
3118	* @returns VBox status code.
3119	* @param pVCpu The VMCPU handle.
3120	* @param GCPtrPage Page to invalidate.
3121	*/
3122	PGM_BTH_DECL(int, PrefetchPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage)
3123	{
3124	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
3125	&& PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
3126	/*
3127	* Check that all Guest levels thru the PDE are present, getting the
3128	* PD and PDE in the processes.
3129	*/
3130	int rc = VINF_SUCCESS;
3131	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3132	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3133	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
3134	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(&pVCpu->pgm.s);
3135	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3136	unsigned iPDSrc;
3137	X86PDPE PdpeSrc;
3138	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVCpu->pgm.s, GCPtrPage, &iPDSrc, &PdpeSrc);
3139	if (!pPDSrc)
3140	return VINF_SUCCESS; /* not present */
3141	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
3142	unsigned iPDSrc;
3143	PX86PML4E pPml4eSrc;
3144	X86PDPE PdpeSrc;
3145	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVCpu->pgm.s, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3146	if (!pPDSrc)
3147	return VINF_SUCCESS; /* not present */
3148	# endif
3149	const GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
3150	# else
3151	PGSTPD pPDSrc = NULL;
3152	const unsigned iPDSrc = 0;
3153	GSTPDE PdeSrc;
3154
3155	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
3156	PdeSrc.n.u1Present = 1;
3157	PdeSrc.n.u1Write = 1;
3158	PdeSrc.n.u1Accessed = 1;
3159	PdeSrc.n.u1User = 1;
3160	# endif
3161
3162	if (PdeSrc.n.u1Present && PdeSrc.n.u1Accessed)
3163	{
3164	PVM pVM = pVCpu->CTX_SUFF(pVM);
3165	pgmLock(pVM);
3166
3167	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3168	const X86PDE PdeDst = pgmShwGet32BitPDE(&pVCpu->pgm.s, GCPtrPage);
3169	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3170	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3171	PX86PDPAE pPDDst;
3172	X86PDEPAE PdeDst;
3173	# if PGM_GST_TYPE != PGM_TYPE_PAE
3174	X86PDPE PdpeSrc;
3175
3176	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
3177	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
3178	# endif
3179	rc = pgmShwSyncPaePDPtr(pVCpu, GCPtrPage, &PdpeSrc, &pPDDst);
3180	if (rc != VINF_SUCCESS)
3181	{
3182	pgmUnlock(pVM);
3183	AssertRC(rc);
3184	return rc;
3185	}
3186	Assert(pPDDst);
3187	PdeDst = pPDDst->a[iPDDst];
3188
3189	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3190	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3191	PX86PDPAE pPDDst;
3192	X86PDEPAE PdeDst;
3193
3194	# if PGM_GST_TYPE == PGM_TYPE_PROT
3195	/* AMD-V nested paging */
3196	X86PML4E Pml4eSrc;
3197	X86PDPE PdpeSrc;
3198	PX86PML4E pPml4eSrc = &Pml4eSrc;
3199
3200	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
3201	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_NX \| X86_PML4E_A;
3202	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_NX \| X86_PDPE_A;
3203	# endif
3204
3205	rc = pgmShwSyncLongModePDPtr(pVCpu, GCPtrPage, pPml4eSrc, &PdpeSrc, &pPDDst);
3206	if (rc != VINF_SUCCESS)
3207	{
3208	pgmUnlock(pVM);
3209	AssertRC(rc);
3210	return rc;
3211	}
3212	Assert(pPDDst);
3213	PdeDst = pPDDst->a[iPDDst];
3214	# endif
3215	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
3216	{
3217	if (!PdeDst.n.u1Present)
3218	{
3219	/** r=bird: This guy will set the A bit on the PDE, probably harmless. */
3220	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
3221	}
3222	else
3223	{
3224	/** @note We used to sync PGM_SYNC_NR_PAGES pages, which triggered assertions in CSAM, because
3225	* R/W attributes of nearby pages were reset. Not sure how that could happen. Anyway, it
3226	* makes no sense to prefetch more than one page.
3227	*/
3228	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
3229	if (RT_SUCCESS(rc))
3230	rc = VINF_SUCCESS;
3231	}
3232	}
3233	pgmUnlock(pVM);
3234	}
3235	return rc;
3236
3237	#elif PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3238	return VINF_SUCCESS; /* ignore */
3239	#endif
3240	}
3241
3242
3243
3244
3245	/**
3246	* Syncs a page during a PGMVerifyAccess() call.
3247	*
3248	* @returns VBox status code (informational included).
3249	* @param pVCpu The VMCPU handle.
3250	* @param GCPtrPage The address of the page to sync.
3251	* @param fPage The effective guest page flags.
3252	* @param uErr The trap error code.
3253	*/
3254	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fPage, unsigned uErr)
3255	{
3256	PVM pVM = pVCpu->CTX_SUFF(pVM);
3257
3258	LogFlow(("VerifyAccessSyncPage: GCPtrPage=%RGv fPage=%#x uErr=%#x\n", GCPtrPage, fPage, uErr));
3259
3260	Assert(!HWACCMIsNestedPagingActive(pVM));
3261	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_TYPE_AMD64) \
3262	&& PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
3263
3264	# ifndef IN_RING0
3265	if (!(fPage & X86_PTE_US))
3266	{
3267	/*
3268	* Mark this page as safe.
3269	*/
3270	/** @todo not correct for pages that contain both code and data!! */
3271	Log(("CSAMMarkPage %RGv; scanned=%d\n", GCPtrPage, true));
3272	CSAMMarkPage(pVM, (RTRCPTR)GCPtrPage, true);
3273	}
3274	# endif
3275
3276	/*
3277	* Get guest PD and index.
3278	*/
3279	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3280	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3281	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
3282	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(&pVCpu->pgm.s);
3283	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3284	unsigned iPDSrc = 0;
3285	X86PDPE PdpeSrc;
3286	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVCpu->pgm.s, GCPtrPage, &iPDSrc, &PdpeSrc);
3287
3288	if (pPDSrc)
3289	{
3290	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
3291	return VINF_EM_RAW_GUEST_TRAP;
3292	}
3293	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
3294	unsigned iPDSrc;
3295	PX86PML4E pPml4eSrc;
3296	X86PDPE PdpeSrc;
3297	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVCpu->pgm.s, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3298	if (!pPDSrc)
3299	{
3300	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
3301	return VINF_EM_RAW_GUEST_TRAP;
3302	}
3303	# endif
3304	# else
3305	PGSTPD pPDSrc = NULL;
3306	const unsigned iPDSrc = 0;
3307	# endif
3308	int rc = VINF_SUCCESS;
3309
3310	pgmLock(pVM);
3311
3312	/*
3313	* First check if the shadow pd is present.
3314	*/
3315	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3316	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(&pVCpu->pgm.s, GCPtrPage);
3317	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3318	PX86PDEPAE pPdeDst;
3319	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3320	PX86PDPAE pPDDst;
3321	# if PGM_GST_TYPE != PGM_TYPE_PAE
3322	X86PDPE PdpeSrc;
3323
3324	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
3325	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
3326	# endif
3327	rc = pgmShwSyncPaePDPtr(pVCpu, GCPtrPage, &PdpeSrc, &pPDDst);
3328	if (rc != VINF_SUCCESS)
3329	{
3330	pgmUnlock(pVM);
3331	AssertRC(rc);
3332	return rc;
3333	}
3334	Assert(pPDDst);
3335	pPdeDst = &pPDDst->a[iPDDst];
3336
3337	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3338	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3339	PX86PDPAE pPDDst;
3340	PX86PDEPAE pPdeDst;
3341
3342	# if PGM_GST_TYPE == PGM_TYPE_PROT
3343	/* AMD-V nested paging */
3344	X86PML4E Pml4eSrc;
3345	X86PDPE PdpeSrc;
3346	PX86PML4E pPml4eSrc = &Pml4eSrc;
3347
3348	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
3349	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_NX \| X86_PML4E_A;
3350	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_NX \| X86_PDPE_A;
3351	# endif
3352
3353	rc = pgmShwSyncLongModePDPtr(pVCpu, GCPtrPage, pPml4eSrc, &PdpeSrc, &pPDDst);
3354	if (rc != VINF_SUCCESS)
3355	{
3356	pgmUnlock(pVM);
3357	AssertRC(rc);
3358	return rc;
3359	}
3360	Assert(pPDDst);
3361	pPdeDst = &pPDDst->a[iPDDst];
3362	# endif
3363
3364	# if defined(IN_RC)
3365	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
3366	PGMDynLockHCPage(pVM, (uint8_t *)pPdeDst);
3367	# endif
3368
3369	if (!pPdeDst->n.u1Present)
3370	{
3371	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
3372	if (rc != VINF_SUCCESS)
3373	{
3374	# if defined(IN_RC)
3375	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
3376	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
3377	# endif
3378	pgmUnlock(pVM);
3379	AssertRC(rc);
3380	return rc;
3381	}
3382	}
3383
3384	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3385	/* Check for dirty bit fault */
3386	rc = PGM_BTH_NAME(CheckPageFault)(pVCpu, uErr, pPdeDst, &pPDSrc->a[iPDSrc], GCPtrPage);
3387	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
3388	Log(("PGMVerifyAccess: success (dirty)\n"));
3389	else
3390	{
3391	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
3392	# else
3393	{
3394	GSTPDE PdeSrc;
3395	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
3396	PdeSrc.n.u1Present = 1;
3397	PdeSrc.n.u1Write = 1;
3398	PdeSrc.n.u1Accessed = 1;
3399	PdeSrc.n.u1User = 1;
3400
3401	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
3402	Assert(rc != VINF_EM_RAW_GUEST_TRAP);
3403	if (uErr & X86_TRAP_PF_US)
3404	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncUser));
3405	else /* supervisor */
3406	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
3407
3408	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
3409	if (RT_SUCCESS(rc))
3410	{
3411	/* Page was successfully synced */
3412	Log2(("PGMVerifyAccess: success (sync)\n"));
3413	rc = VINF_SUCCESS;
3414	}
3415	else
3416	{
3417	Log(("PGMVerifyAccess: access violation for %RGv rc=%d\n", GCPtrPage, rc));
3418	rc = VINF_EM_RAW_GUEST_TRAP;
3419	}
3420	}
3421	# if defined(IN_RC)
3422	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
3423	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
3424	# endif
3425	pgmUnlock(pVM);
3426	return rc;
3427
3428	#else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
3429
3430	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
3431	return VERR_INTERNAL_ERROR;
3432	#endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
3433	}
3434
3435	#undef MY_STAM_COUNTER_INC
3436	#define MY_STAM_COUNTER_INC(a) do { } while (0)
3437
3438
3439	/**
3440	* Syncs the paging hierarchy starting at CR3.
3441	*
3442	* @returns VBox status code, no specials.
3443	* @param pVCpu The VMCPU handle.
3444	* @param cr0 Guest context CR0 register
3445	* @param cr3 Guest context CR3 register
3446	* @param cr4 Guest context CR4 register
3447	* @param fGlobal Including global page directories or not
3448	*/
3449	PGM_BTH_DECL(int, SyncCR3)(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
3450	{
3451	PVM pVM = pVCpu->CTX_SUFF(pVM);
3452
3453	if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3))
3454	fGlobal = true; /* Change this CR3 reload to be a global one. */
3455
3456	LogFlow(("SyncCR3 %d\n", fGlobal));
3457
3458	#if PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
3459
3460	pgmLock(pVM);
3461	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
3462	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3463	if (pPool->cDirtyPages)
3464	pgmPoolResetDirtyPages(pVM);
3465	# endif
3466
3467	/*
3468	* Update page access handlers.
3469	* The virtual are always flushed, while the physical are only on demand.
3470	* WARNING: We are incorrectly not doing global flushing on Virtual Handler updates. We'll
3471	* have to look into that later because it will have a bad influence on the performance.
3472	* @note SvL: There's no need for that. Just invalidate the virtual range(s).
3473	* bird: Yes, but that won't work for aliases.
3474	*/
3475	/** @todo this MUST go away. See #1557. */
3476	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncCR3Handlers), h);
3477	PGM_GST_NAME(HandlerVirtualUpdate)(pVM, cr4);
3478	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncCR3Handlers), h);
3479	pgmUnlock(pVM);
3480	#endif
3481
3482	#if PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3483	/*
3484	* Nested / EPT - almost no work.
3485	*/
3486	/** @todo check if this is really necessary; the call does it as well... */
3487	HWACCMFlushTLB(pVCpu);
3488	return VINF_SUCCESS;
3489
3490	#elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3491	/*
3492	* AMD64 (Shw & Gst) - No need to check all paging levels; we zero
3493	* out the shadow parts when the guest modifies its tables.
3494	*/
3495	return VINF_SUCCESS;
3496
3497	#else /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
3498
3499	# ifdef PGM_WITHOUT_MAPPINGS
3500	Assert(pVM->pgm.s.fMappingsFixed);
3501	return VINF_SUCCESS;
3502	# else
3503	/* Nothing to do when mappings are fixed. */
3504	if (pVM->pgm.s.fMappingsFixed)
3505	return VINF_SUCCESS;
3506
3507	int rc = PGMMapResolveConflicts(pVM);
3508	Assert(rc == VINF_SUCCESS \|\| rc == VINF_PGM_SYNC_CR3);
3509	if (rc == VINF_PGM_SYNC_CR3)
3510	{
3511	LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
3512	return VINF_PGM_SYNC_CR3;
3513	}
3514	# endif
3515	return VINF_SUCCESS;
3516	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
3517	}
3518
3519
3520
3521
3522	#ifdef VBOX_STRICT
3523	#ifdef IN_RC
3524	# undef AssertMsgFailed
3525	# define AssertMsgFailed Log
3526	#endif
3527	#ifdef IN_RING3
3528	# include <VBox/dbgf.h>
3529
3530	/**
3531	* Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
3532	*
3533	* @returns VBox status code (VINF_SUCCESS).
3534	* @param cr3 The root of the hierarchy.
3535	* @param crr The cr4, only PAE and PSE is currently used.
3536	* @param fLongMode Set if long mode, false if not long mode.
3537	* @param cMaxDepth Number of levels to dump.
3538	* @param pHlp Pointer to the output functions.
3539	*/
3540	RT_C_DECLS_BEGIN
3541	VMMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint32_t cr3, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp);
3542	RT_C_DECLS_END
3543
3544	#endif
3545
3546	/**
3547	* Checks that the shadow page table is in sync with the guest one.
3548	*
3549	* @returns The number of errors.
3550	* @param pVM The virtual machine.
3551	* @param pVCpu The VMCPU handle.
3552	* @param cr3 Guest context CR3 register
3553	* @param cr4 Guest context CR4 register
3554	* @param GCPtr Where to start. Defaults to 0.
3555	* @param cb How much to check. Defaults to everything.
3556	*/
3557	PGM_BTH_DECL(unsigned, AssertCR3)(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb)
3558	{
3559	#if PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3560	return 0;
3561	#else
3562	unsigned cErrors = 0;
3563	PVM pVM = pVCpu->CTX_SUFF(pVM);
3564	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3565
3566	#if PGM_GST_TYPE == PGM_TYPE_PAE
3567	/** @todo currently broken; crashes below somewhere */
3568	AssertFailed();
3569	#endif
3570
3571	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
3572	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3573	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
3574
3575	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3576	bool fBigPagesSupported = true;
3577	# else
3578	bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PSE);
3579	# endif
3580	PPGMCPU pPGM = &pVCpu->pgm.s;
3581	RTGCPHYS GCPhysGst; /* page address derived from the guest page tables. */
3582	RTHCPHYS HCPhysShw; /* page address derived from the shadow page tables. */
3583	# ifndef IN_RING0
3584	RTHCPHYS HCPhys; /* general usage. */
3585	# endif
3586	int rc;
3587
3588	/*
3589	* Check that the Guest CR3 and all its mappings are correct.
3590	*/
3591	AssertMsgReturn(pPGM->GCPhysCR3 == (cr3 & GST_CR3_PAGE_MASK),
3592	("Invalid GCPhysCR3=%RGp cr3=%RGp\n", pPGM->GCPhysCR3, (RTGCPHYS)cr3),
3593	false);
3594	# if !defined(IN_RING0) && PGM_GST_TYPE != PGM_TYPE_AMD64
3595	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3596	rc = PGMShwGetPage(pVCpu, (RTGCPTR)pPGM->pGst32BitPdRC, NULL, &HCPhysShw);
3597	# else
3598	rc = PGMShwGetPage(pVCpu, (RTGCPTR)pPGM->pGstPaePdptRC, NULL, &HCPhysShw);
3599	# endif
3600	AssertRCReturn(rc, 1);
3601	HCPhys = NIL_RTHCPHYS;
3602	rc = pgmRamGCPhys2HCPhys(&pVM->pgm.s, cr3 & GST_CR3_PAGE_MASK, &HCPhys);
3603	AssertMsgReturn(HCPhys == HCPhysShw, ("HCPhys=%RHp HCPhyswShw=%RHp (cr3)\n", HCPhys, HCPhysShw), false);
3604	# if PGM_GST_TYPE == PGM_TYPE_32BIT && defined(IN_RING3)
3605	pgmGstGet32bitPDPtr(pPGM);
3606	RTGCPHYS GCPhys;
3607	rc = PGMR3DbgR3Ptr2GCPhys(pVM, pPGM->pGst32BitPdR3, &GCPhys);
3608	AssertRCReturn(rc, 1);
3609	AssertMsgReturn((cr3 & GST_CR3_PAGE_MASK) == GCPhys, ("GCPhys=%RGp cr3=%RGp\n", GCPhys, (RTGCPHYS)cr3), false);
3610	# endif
3611	# endif /* !IN_RING0 */
3612
3613	/*
3614	* Get and check the Shadow CR3.
3615	*/
3616	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3617	unsigned cPDEs = X86_PG_ENTRIES;
3618	unsigned cIncrement = X86_PG_ENTRIES * PAGE_SIZE;
3619	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3620	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3621	unsigned cPDEs = X86_PG_PAE_ENTRIES * 4; /* treat it as a 2048 entry table. */
3622	# else
3623	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3624	# endif
3625	unsigned cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3626	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3627	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3628	unsigned cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3629	# endif
3630	if (cb != ~(RTGCPTR)0)
3631	cPDEs = RT_MIN(cb >> SHW_PD_SHIFT, 1);
3632
3633	/** @todo call the other two PGMAssert() functions. /
3634
3635	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3636	unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3637
3638	for (; iPml4 < X86_PG_PAE_ENTRIES; iPml4++)
3639	{
3640	PPGMPOOLPAGE pShwPdpt = NULL;
3641	PX86PML4E pPml4eSrc;
3642	PX86PML4E pPml4eDst;
3643	RTGCPHYS GCPhysPdptSrc;
3644
3645	pPml4eSrc = pgmGstGetLongModePML4EPtr(&pVCpu->pgm.s, iPml4);
3646	pPml4eDst = pgmShwGetLongModePML4EPtr(&pVCpu->pgm.s, iPml4);
3647
3648	/* Fetch the pgm pool shadow descriptor if the shadow pml4e is present. */
3649	if (!pPml4eDst->n.u1Present)
3650	{
3651	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3652	continue;
3653	}
3654
3655	pShwPdpt = pgmPoolGetPage(pPool, pPml4eDst->u & X86_PML4E_PG_MASK);
3656	GCPhysPdptSrc = pPml4eSrc->u & X86_PML4E_PG_MASK_FULL;
3657
3658	if (pPml4eSrc->n.u1Present != pPml4eDst->n.u1Present)
3659	{
3660	AssertMsgFailed(("Present bit doesn't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3661	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3662	cErrors++;
3663	continue;
3664	}
3665
3666	if (GCPhysPdptSrc != pShwPdpt->GCPhys)
3667	{
3668	AssertMsgFailed(("Physical address doesn't match! iPml4 %d pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, pPml4eDst->u, pPml4eSrc->u, pShwPdpt->GCPhys, GCPhysPdptSrc));
3669	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3670	cErrors++;
3671	continue;
3672	}
3673
3674	if ( pPml4eDst->n.u1User != pPml4eSrc->n.u1User
3675	\|\| pPml4eDst->n.u1Write != pPml4eSrc->n.u1Write
3676	\|\| pPml4eDst->n.u1NoExecute != pPml4eSrc->n.u1NoExecute)
3677	{
3678	AssertMsgFailed(("User/Write/NoExec bits don't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3679	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3680	cErrors++;
3681	continue;
3682	}
3683	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
3684	{
3685	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
3686
3687	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
3688	/*
3689	* Check the PDPTEs too.
3690	*/
3691	unsigned iPdpt = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
3692
3693	for (;iPdpt <= SHW_PDPT_MASK; iPdpt++)
3694	{
3695	unsigned iPDSrc = 0; /* initialized to shut up gcc */
3696	PPGMPOOLPAGE pShwPde = NULL;
3697	PX86PDPE pPdpeDst;
3698	RTGCPHYS GCPhysPdeSrc;
3699	# if PGM_GST_TYPE == PGM_TYPE_PAE
3700	X86PDPE PdpeSrc;
3701	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVCpu->pgm.s, GCPtr, &iPDSrc, &PdpeSrc);
3702	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(&pVCpu->pgm.s);
3703	# else
3704	PX86PML4E pPml4eSrcIgn;
3705	X86PDPE PdpeSrc;
3706	PX86PDPT pPdptDst;
3707	PX86PDPAE pPDDst;
3708	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVCpu->pgm.s, GCPtr, &pPml4eSrcIgn, &PdpeSrc, &iPDSrc);
3709
3710	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtr, NULL, &pPdptDst, &pPDDst);
3711	if (rc != VINF_SUCCESS)
3712	{
3713	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
3714	GCPtr += 512 * _2M;
3715	continue; /* next PDPTE */
3716	}
3717	Assert(pPDDst);
3718	# endif
3719	Assert(iPDSrc == 0);
3720
3721	pPdpeDst = &pPdptDst->a[iPdpt];
3722
3723	if (!pPdpeDst->n.u1Present)
3724	{
3725	GCPtr += 512 * _2M;
3726	continue; /* next PDPTE */
3727	}
3728
3729	pShwPde = pgmPoolGetPage(pPool, pPdpeDst->u & X86_PDPE_PG_MASK);
3730	GCPhysPdeSrc = PdpeSrc.u & X86_PDPE_PG_MASK;
3731
3732	if (pPdpeDst->n.u1Present != PdpeSrc.n.u1Present)
3733	{
3734	AssertMsgFailed(("Present bit doesn't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3735	GCPtr += 512 * _2M;
3736	cErrors++;
3737	continue;
3738	}
3739
3740	if (GCPhysPdeSrc != pShwPde->GCPhys)
3741	{
3742	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3743	AssertMsgFailed(("Physical address doesn't match! iPml4 %d iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3744	# else
3745	AssertMsgFailed(("Physical address doesn't match! iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3746	# endif
3747	GCPtr += 512 * _2M;
3748	cErrors++;
3749	continue;
3750	}
3751
3752	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3753	if ( pPdpeDst->lm.u1User != PdpeSrc.lm.u1User
3754	\|\| pPdpeDst->lm.u1Write != PdpeSrc.lm.u1Write
3755	\|\| pPdpeDst->lm.u1NoExecute != PdpeSrc.lm.u1NoExecute)
3756	{
3757	AssertMsgFailed(("User/Write/NoExec bits don't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3758	GCPtr += 512 * _2M;
3759	cErrors++;
3760	continue;
3761	}
3762	# endif
3763
3764	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
3765	{
3766	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
3767	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3768	GSTPD const *pPDSrc = pgmGstGet32bitPDPtr(&pVCpu->pgm.s);
3769	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3770	PCX86PD pPDDst = pgmShwGet32BitPDPtr(&pVCpu->pgm.s);
3771	# endif
3772	# endif /* PGM_GST_TYPE == PGM_TYPE_32BIT */
3773	/*
3774	* Iterate the shadow page directory.
3775	*/
3776	GCPtr = (GCPtr >> SHW_PD_SHIFT) << SHW_PD_SHIFT;
3777	unsigned iPDDst = (GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK;
3778
3779	for (;
3780	iPDDst < cPDEs;
3781	iPDDst++, GCPtr += cIncrement)
3782	{
3783	# if PGM_SHW_TYPE == PGM_TYPE_PAE
3784	const SHWPDE PdeDst = *pgmShwGetPaePDEPtr(pPGM, GCPtr);
3785	# else
3786	const SHWPDE PdeDst = pPDDst->a[iPDDst];
3787	# endif
3788	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
3789	{
3790	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
3791	if ((PdeDst.u & X86_PDE_AVL_MASK) != PGM_PDFLAGS_MAPPING)
3792	{
3793	AssertMsgFailed(("Mapping shall only have PGM_PDFLAGS_MAPPING set! PdeDst.u=%#RX64\n", (uint64_t)PdeDst.u));
3794	cErrors++;
3795	continue;
3796	}
3797	}
3798	else if ( (PdeDst.u & X86_PDE_P)
3799	\|\| ((PdeDst.u & (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY)) == (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY))
3800	)
3801	{
3802	HCPhysShw = PdeDst.u & SHW_PDE_PG_MASK;
3803	PPGMPOOLPAGE pPoolPage = pgmPoolGetPage(pPool, HCPhysShw);
3804	if (!pPoolPage)
3805	{
3806	AssertMsgFailed(("Invalid page table address %RHp at %RGv! PdeDst=%#RX64\n",
3807	HCPhysShw, GCPtr, (uint64_t)PdeDst.u));
3808	cErrors++;
3809	continue;
3810	}
3811	const SHWPT pPTDst = (const SHWPT )PGMPOOL_PAGE_2_PTR(pVM, pPoolPage);
3812
3813	if (PdeDst.u & (X86_PDE4M_PWT \| X86_PDE4M_PCD))
3814	{
3815	AssertMsgFailed(("PDE flags PWT and/or PCD is set at %RGv! These flags are not virtualized! PdeDst=%#RX64\n",
3816	GCPtr, (uint64_t)PdeDst.u));
3817	cErrors++;
3818	}
3819
3820	if (PdeDst.u & (X86_PDE4M_G \| X86_PDE4M_D))
3821	{
3822	AssertMsgFailed(("4K PDE reserved flags at %RGv! PdeDst=%#RX64\n",
3823	GCPtr, (uint64_t)PdeDst.u));
3824	cErrors++;
3825	}
3826
3827	const GSTPDE PdeSrc = pPDSrc->a[(iPDDst >> (GST_PD_SHIFT - SHW_PD_SHIFT)) & GST_PD_MASK];
3828	if (!PdeSrc.n.u1Present)
3829	{
3830	AssertMsgFailed(("Guest PDE at %RGv is not present! PdeDst=%#RX64 PdeSrc=%#RX64\n",
3831	GCPtr, (uint64_t)PdeDst.u, (uint64_t)PdeSrc.u));
3832	cErrors++;
3833	continue;
3834	}
3835
3836	if ( !PdeSrc.b.u1Size
3837	\|\| !fBigPagesSupported)
3838	{
3839	GCPhysGst = PdeSrc.u & GST_PDE_PG_MASK;
3840	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3841	GCPhysGst \|= (iPDDst & 1) * (PAGE_SIZE / 2);
3842	# endif
3843	}
3844	else
3845	{
3846	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3847	if (PdeSrc.u & X86_PDE4M_PG_HIGH_MASK)
3848	{
3849	AssertMsgFailed(("Guest PDE at %RGv is using PSE36 or similar! PdeSrc=%#RX64\n",
3850	GCPtr, (uint64_t)PdeSrc.u));
3851	cErrors++;
3852	continue;
3853	}
3854	# endif
3855	GCPhysGst = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
3856	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3857	GCPhysGst \|= GCPtr & RT_BIT(X86_PAGE_2M_SHIFT);
3858	# endif
3859	}
3860
3861	if ( pPoolPage->enmKind
3862	!= (!PdeSrc.b.u1Size \|\| !fBigPagesSupported ? BTH_PGMPOOLKIND_PT_FOR_PT : BTH_PGMPOOLKIND_PT_FOR_BIG))
3863	{
3864	AssertMsgFailed(("Invalid shadow page table kind %d at %RGv! PdeSrc=%#RX64\n",
3865	pPoolPage->enmKind, GCPtr, (uint64_t)PdeSrc.u));
3866	cErrors++;
3867	}
3868
3869	PPGMPAGE pPhysPage = pgmPhysGetPage(&pVM->pgm.s, GCPhysGst);
3870	if (!pPhysPage)
3871	{
3872	AssertMsgFailed(("Cannot find guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
3873	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3874	cErrors++;
3875	continue;
3876	}
3877
3878	if (GCPhysGst != pPoolPage->GCPhys)
3879	{
3880	AssertMsgFailed(("GCPhysGst=%RGp != pPage->GCPhys=%RGp at %RGv\n",
3881	GCPhysGst, pPoolPage->GCPhys, GCPtr));
3882	cErrors++;
3883	continue;
3884	}
3885
3886	if ( !PdeSrc.b.u1Size
3887	\|\| !fBigPagesSupported)
3888	{
3889	/*
3890	* Page Table.
3891	*/
3892	const GSTPT *pPTSrc;
3893	rc = PGM_GCPHYS_2_PTR(pVM, GCPhysGst & ~(RTGCPHYS)(PAGE_SIZE - 1), &pPTSrc);
3894	if (RT_FAILURE(rc))
3895	{
3896	AssertMsgFailed(("Cannot map/convert guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
3897	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3898	cErrors++;
3899	continue;
3900	}
3901	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/))
3902	!= (PdeDst.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/)))
3903	{
3904	/// @todo We get here a lot on out-of-sync CR3 entries. The access handler should zap them to avoid false alarms here!
3905	// (This problem will go away when/if we shadow multiple CR3s.)
3906	AssertMsgFailed(("4K PDE flags mismatch at %RGv! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3907	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3908	cErrors++;
3909	continue;
3910	}
3911	if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
3912	{
3913	AssertMsgFailed(("4K PDEs cannot have PGM_PDFLAGS_TRACK_DIRTY set! GCPtr=%RGv PdeDst=%#RX64\n",
3914	GCPtr, (uint64_t)PdeDst.u));
3915	cErrors++;
3916	continue;
3917	}
3918
3919	/* iterate the page table. */
3920	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3921	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
3922	const unsigned offPTSrc = ((GCPtr >> SHW_PD_SHIFT) & 1) * 512;
3923	# else
3924	const unsigned offPTSrc = 0;
3925	# endif
3926	for (unsigned iPT = 0, off = 0;
3927	iPT < RT_ELEMENTS(pPTDst->a);
3928	iPT++, off += PAGE_SIZE)
3929	{
3930	const SHWPTE PteDst = pPTDst->a[iPT];
3931
3932	/* skip not-present entries. */
3933	if (!(PteDst.u & (X86_PTE_P \| PGM_PTFLAGS_TRACK_DIRTY))) /** @todo deal with ALL handlers and CSAM !P pages! */
3934	continue;
3935	Assert(PteDst.n.u1Present);
3936
3937	const GSTPTE PteSrc = pPTSrc->a[iPT + offPTSrc];
3938	if (!PteSrc.n.u1Present)
3939	{
3940	# ifdef IN_RING3
3941	PGMAssertHandlerAndFlagsInSync(pVM);
3942	PGMR3DumpHierarchyGC(pVM, cr3, cr4, (PdeSrc.u & GST_PDE_PG_MASK));
3943	# endif
3944	AssertMsgFailed(("Out of sync (!P) PTE at %RGv! PteSrc=%#RX64 PteDst=%#RX64 pPTSrc=%RGv iPTSrc=%x PdeSrc=%x physpte=%RGp\n",
3945	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u, pPTSrc, iPT + offPTSrc, PdeSrc.au32[0],
3946	(PdeSrc.u & GST_PDE_PG_MASK) + (iPT + offPTSrc)*sizeof(PteSrc)));
3947	cErrors++;
3948	continue;
3949	}
3950
3951	uint64_t fIgnoreFlags = GST_PTE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_G \| X86_PTE_D \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT;
3952	# if 1 /** @todo sync accessed bit properly... */
3953	fIgnoreFlags \|= X86_PTE_A;
3954	# endif
3955
3956	/* match the physical addresses */
3957	HCPhysShw = PteDst.u & SHW_PTE_PG_MASK;
3958	GCPhysGst = PteSrc.u & GST_PTE_PG_MASK;
3959
3960	# ifdef IN_RING3
3961	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
3962	if (RT_FAILURE(rc))
3963	{
3964	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
3965	{
3966	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
3967	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3968	cErrors++;
3969	continue;
3970	}
3971	}
3972	else if (HCPhysShw != (HCPhys & SHW_PTE_PG_MASK))
3973	{
3974	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
3975	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3976	cErrors++;
3977	continue;
3978	}
3979	# endif
3980
3981	pPhysPage = pgmPhysGetPage(&pVM->pgm.s, GCPhysGst);
3982	if (!pPhysPage)
3983	{
3984	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
3985	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
3986	{
3987	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
3988	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3989	cErrors++;
3990	continue;
3991	}
3992	# endif
3993	if (PteDst.n.u1Write)
3994	{
3995	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
3996	GCPtr + off, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3997	cErrors++;
3998	}
3999	fIgnoreFlags \|= X86_PTE_RW;
4000	}
4001	else if (HCPhysShw != PGM_PAGE_GET_HCPHYS(pPhysPage))
4002	{
4003	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp pPhysPage:%R[pgmpage] GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4004	GCPtr + off, HCPhysShw, pPhysPage, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4005	cErrors++;
4006	continue;
4007	}
4008
4009	/* flags */
4010	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
4011	{
4012	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
4013	{
4014	if (PteDst.n.u1Write)
4015	{
4016	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! pPhysPage=%R[pgmpage] PteSrc=%#RX64 PteDst=%#RX64\n",
4017	GCPtr + off, pPhysPage, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4018	cErrors++;
4019	continue;
4020	}
4021	fIgnoreFlags \|= X86_PTE_RW;
4022	}
4023	else
4024	{
4025	if (PteDst.n.u1Present)
4026	{
4027	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! pPhysPage=%R[pgmpage] PteSrc=%#RX64 PteDst=%#RX64\n",
4028	GCPtr + off, pPhysPage, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4029	cErrors++;
4030	continue;
4031	}
4032	fIgnoreFlags \|= X86_PTE_P;
4033	}
4034	}
4035	else
4036	{
4037	if (!PteSrc.n.u1Dirty && PteSrc.n.u1Write)
4038	{
4039	if (PteDst.n.u1Write)
4040	{
4041	AssertMsgFailed(("!DIRTY page at %RGv is writable! PteSrc=%#RX64 PteDst=%#RX64\n",
4042	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4043	cErrors++;
4044	continue;
4045	}
4046	if (!(PteDst.u & PGM_PTFLAGS_TRACK_DIRTY))
4047	{
4048	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4049	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4050	cErrors++;
4051	continue;
4052	}
4053	if (PteDst.n.u1Dirty)
4054	{
4055	AssertMsgFailed(("!DIRTY page at %RGv is marked DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4056	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4057	cErrors++;
4058	}
4059	# if 0 /** @todo sync access bit properly... */
4060	if (PteDst.n.u1Accessed != PteSrc.n.u1Accessed)
4061	{
4062	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4063	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4064	cErrors++;
4065	}
4066	fIgnoreFlags \|= X86_PTE_RW;
4067	# else
4068	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4069	# endif
4070	}
4071	else if (PteDst.u & PGM_PTFLAGS_TRACK_DIRTY)
4072	{
4073	/* access bit emulation (not implemented). */
4074	if (PteSrc.n.u1Accessed \|\| PteDst.n.u1Present)
4075	{
4076	AssertMsgFailed(("PGM_PTFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PteSrc=%#RX64 PteDst=%#RX64\n",
4077	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4078	cErrors++;
4079	continue;
4080	}
4081	if (!PteDst.n.u1Accessed)
4082	{
4083	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PteSrc=%#RX64 PteDst=%#RX64\n",
4084	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4085	cErrors++;
4086	}
4087	fIgnoreFlags \|= X86_PTE_P;
4088	}
4089	# ifdef DEBUG_sandervl
4090	fIgnoreFlags \|= X86_PTE_D \| X86_PTE_A;
4091	# endif
4092	}
4093
4094	if ( (PteSrc.u & ~fIgnoreFlags) != (PteDst.u & ~fIgnoreFlags)
4095	&& (PteSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (PteDst.u & ~fIgnoreFlags)
4096	)
4097	{
4098	AssertMsgFailed(("Flags mismatch at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PteSrc=%#RX64 PteDst=%#RX64\n",
4099	GCPtr + off, (uint64_t)PteSrc.u & ~fIgnoreFlags, (uint64_t)PteDst.u & ~fIgnoreFlags,
4100	fIgnoreFlags, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4101	cErrors++;
4102	continue;
4103	}
4104	} /* foreach PTE */
4105	}
4106	else
4107	{
4108	/*
4109	* Big Page.
4110	*/
4111	uint64_t fIgnoreFlags = X86_PDE_AVL_MASK \| GST_PDE_PG_MASK \| X86_PDE4M_G \| X86_PDE4M_D \| X86_PDE4M_PS \| X86_PDE4M_PWT \| X86_PDE4M_PCD;
4112	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
4113	{
4114	if (PdeDst.n.u1Write)
4115	{
4116	AssertMsgFailed(("!DIRTY page at %RGv is writable! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4117	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4118	cErrors++;
4119	continue;
4120	}
4121	if (!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY))
4122	{
4123	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4124	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4125	cErrors++;
4126	continue;
4127	}
4128	# if 0 /** @todo sync access bit properly... */
4129	if (PdeDst.n.u1Accessed != PdeSrc.b.u1Accessed)
4130	{
4131	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4132	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4133	cErrors++;
4134	}
4135	fIgnoreFlags \|= X86_PTE_RW;
4136	# else
4137	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4138	# endif
4139	}
4140	else if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
4141	{
4142	/* access bit emulation (not implemented). */
4143	if (PdeSrc.b.u1Accessed \|\| PdeDst.n.u1Present)
4144	{
4145	AssertMsgFailed(("PGM_PDFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4146	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4147	cErrors++;
4148	continue;
4149	}
4150	if (!PdeDst.n.u1Accessed)
4151	{
4152	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4153	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4154	cErrors++;
4155	}
4156	fIgnoreFlags \|= X86_PTE_P;
4157	}
4158
4159	if ((PdeSrc.u & ~fIgnoreFlags) != (PdeDst.u & ~fIgnoreFlags))
4160	{
4161	AssertMsgFailed(("Flags mismatch (B) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PdeDst=%#RX64\n",
4162	GCPtr, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PdeDst.u & ~fIgnoreFlags,
4163	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4164	cErrors++;
4165	}
4166
4167	/* iterate the page table. */
4168	for (unsigned iPT = 0, off = 0;
4169	iPT < RT_ELEMENTS(pPTDst->a);
4170	iPT++, off += PAGE_SIZE, GCPhysGst += PAGE_SIZE)
4171	{
4172	const SHWPTE PteDst = pPTDst->a[iPT];
4173
4174	if (PteDst.u & PGM_PTFLAGS_TRACK_DIRTY)
4175	{
4176	AssertMsgFailed(("The PTE at %RGv emulating a 2/4M page is marked TRACK_DIRTY! PdeSrc=%#RX64 PteDst=%#RX64\n",
4177	GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4178	cErrors++;
4179	}
4180
4181	/* skip not-present entries. */
4182	if (!PteDst.n.u1Present) /** @todo deal with ALL handlers and CSAM !P pages! */
4183	continue;
4184
4185	fIgnoreFlags = X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT \| X86_PTE_D \| X86_PTE_A \| X86_PTE_G \| X86_PTE_PAE_NX;
4186
4187	/* match the physical addresses */
4188	HCPhysShw = PteDst.u & X86_PTE_PAE_PG_MASK;
4189
4190	# ifdef IN_RING3
4191	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
4192	if (RT_FAILURE(rc))
4193	{
4194	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4195	{
4196	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4197	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4198	cErrors++;
4199	}
4200	}
4201	else if (HCPhysShw != (HCPhys & X86_PTE_PAE_PG_MASK))
4202	{
4203	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4204	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4205	cErrors++;
4206	continue;
4207	}
4208	# endif
4209	pPhysPage = pgmPhysGetPage(&pVM->pgm.s, GCPhysGst);
4210	if (!pPhysPage)
4211	{
4212	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
4213	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4214	{
4215	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4216	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4217	cErrors++;
4218	continue;
4219	}
4220	# endif
4221	if (PteDst.n.u1Write)
4222	{
4223	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4224	GCPtr + off, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4225	cErrors++;
4226	}
4227	fIgnoreFlags \|= X86_PTE_RW;
4228	}
4229	else if (HCPhysShw != PGM_PAGE_GET_HCPHYS(pPhysPage))
4230	{
4231	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp pPhysPage=%R[pgmpage] GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4232	GCPtr + off, HCPhysShw, pPhysPage, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4233	cErrors++;
4234	continue;
4235	}
4236
4237	/* flags */
4238	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
4239	{
4240	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
4241	{
4242	if (PGM_PAGE_GET_HNDL_PHYS_STATE(pPhysPage) != PGM_PAGE_HNDL_PHYS_STATE_DISABLED)
4243	{
4244	if (PteDst.n.u1Write)
4245	{
4246	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! pPhysPage=%R[pgmpage] PdeSrc=%#RX64 PteDst=%#RX64\n",
4247	GCPtr + off, pPhysPage, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4248	cErrors++;
4249	continue;
4250	}
4251	fIgnoreFlags \|= X86_PTE_RW;
4252	}
4253	}
4254	else
4255	{
4256	if (PteDst.n.u1Present)
4257	{
4258	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! pPhysPage=%R[pgmpage] PdeSrc=%#RX64 PteDst=%#RX64\n",
4259	GCPtr + off, pPhysPage, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4260	cErrors++;
4261	continue;
4262	}
4263	fIgnoreFlags \|= X86_PTE_P;
4264	}
4265	}
4266
4267	if ( (PdeSrc.u & ~fIgnoreFlags) != (PteDst.u & ~fIgnoreFlags)
4268	&& (PdeSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (PteDst.u & ~fIgnoreFlags) /* lazy phys handler dereg. */
4269	)
4270	{
4271	AssertMsgFailed(("Flags mismatch (BT) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PteDst=%#RX64\n",
4272	GCPtr + off, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PteDst.u & ~fIgnoreFlags,
4273	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4274	cErrors++;
4275	continue;
4276	}
4277	} /* for each PTE */
4278	}
4279	}
4280	/* not present */
4281
4282	} /* for each PDE */
4283
4284	} /* for each PDPTE */
4285
4286	} /* for each PML4E */
4287
4288	# ifdef DEBUG
4289	if (cErrors)
4290	LogFlow(("AssertCR3: cErrors=%d\n", cErrors));
4291	# endif
4292
4293	#endif /* GST == 32BIT, PAE or AMD64 */
4294	return cErrors;
4295
4296	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT */
4297	}
4298	#endif /* VBOX_STRICT */
4299
4300
4301	/**
4302	* Sets up the CR3 for shadow paging
4303	*
4304	* @returns Strict VBox status code.
4305	* @retval VINF_SUCCESS.
4306	*
4307	* @param pVCpu The VMCPU handle.
4308	* @param GCPhysCR3 The physical address in the CR3 register.
4309	*/
4310	PGM_BTH_DECL(int, MapCR3)(PVMCPU pVCpu, RTGCPHYS GCPhysCR3)
4311	{
4312	PVM pVM = pVCpu->CTX_SUFF(pVM);
4313
4314	/* Update guest paging info. */
4315	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
4316	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
4317	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
4318
4319	LogFlow(("MapCR3: %RGp\n", GCPhysCR3));
4320
4321	/*
4322	* Map the page CR3 points at.
4323	*/
4324	RTHCPTR HCPtrGuestCR3;
4325	RTHCPHYS HCPhysGuestCR3;
4326	pgmLock(pVM);
4327	PPGMPAGE pPageCR3 = pgmPhysGetPage(&pVM->pgm.s, GCPhysCR3);
4328	AssertReturn(pPageCR3, VERR_INTERNAL_ERROR_2);
4329	HCPhysGuestCR3 = PGM_PAGE_GET_HCPHYS(pPageCR3);
4330	/** @todo this needs some reworking wrt. locking. */
4331	# if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
4332	HCPtrGuestCR3 = NIL_RTHCPTR;
4333	int rc = VINF_SUCCESS;
4334	# else
4335	int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPageCR3, GCPhysCR3 & GST_CR3_PAGE_MASK, (void )&HCPtrGuestCR3); / @todo r=bird: This GCPhysCR3 masking isn't necessary. */
4336	# endif
4337	pgmUnlock(pVM);
4338	if (RT_SUCCESS(rc))
4339	{
4340	rc = PGMMap(pVM, (RTGCPTR)pVM->pgm.s.GCPtrCR3Mapping, HCPhysGuestCR3, PAGE_SIZE, 0);
4341	if (RT_SUCCESS(rc))
4342	{
4343	# ifdef IN_RC
4344	PGM_INVL_PG(pVCpu, pVM->pgm.s.GCPtrCR3Mapping);
4345	# endif
4346	# if PGM_GST_TYPE == PGM_TYPE_32BIT
4347	pVCpu->pgm.s.pGst32BitPdR3 = (R3PTRTYPE(PX86PD))HCPtrGuestCR3;
4348	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4349	pVCpu->pgm.s.pGst32BitPdR0 = (R0PTRTYPE(PX86PD))HCPtrGuestCR3;
4350	# endif
4351	pVCpu->pgm.s.pGst32BitPdRC = (RCPTRTYPE(PX86PD))pVM->pgm.s.GCPtrCR3Mapping;
4352
4353	# elif PGM_GST_TYPE == PGM_TYPE_PAE
4354	unsigned off = GCPhysCR3 & GST_CR3_PAGE_MASK & PAGE_OFFSET_MASK;
4355	pVCpu->pgm.s.pGstPaePdptR3 = (R3PTRTYPE(PX86PDPT))HCPtrGuestCR3;
4356	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4357	pVCpu->pgm.s.pGstPaePdptR0 = (R0PTRTYPE(PX86PDPT))HCPtrGuestCR3;
4358	# endif
4359	pVCpu->pgm.s.pGstPaePdptRC = (RCPTRTYPE(PX86PDPT))((RCPTRTYPE(uint8_t *))pVM->pgm.s.GCPtrCR3Mapping + off);
4360	Log(("Cached mapping %RRv\n", pVCpu->pgm.s.pGstPaePdptRC));
4361
4362	/*
4363	* Map the 4 PDs too.
4364	*/
4365	PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(&pVCpu->pgm.s);
4366	RTGCPTR GCPtr = pVM->pgm.s.GCPtrCR3Mapping + PAGE_SIZE;
4367	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++, GCPtr += PAGE_SIZE)
4368	{
4369	if (pGuestPDPT->a[i].n.u1Present)
4370	{
4371	RTHCPTR HCPtr;
4372	RTHCPHYS HCPhys;
4373	RTGCPHYS GCPhys = pGuestPDPT->a[i].u & X86_PDPE_PG_MASK;
4374	pgmLock(pVM);
4375	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, GCPhys);
4376	AssertReturn(pPage, VERR_INTERNAL_ERROR_2);
4377	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
4378	# if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
4379	HCPtr = NIL_RTHCPTR;
4380	int rc2 = VINF_SUCCESS;
4381	# else
4382	int rc2 = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, (void **)&HCPtr);
4383	# endif
4384	pgmUnlock(pVM);
4385	if (RT_SUCCESS(rc2))
4386	{
4387	rc = PGMMap(pVM, GCPtr, HCPhys, PAGE_SIZE, 0);
4388	AssertRCReturn(rc, rc);
4389
4390	pVCpu->pgm.s.apGstPaePDsR3[i] = (R3PTRTYPE(PX86PDPAE))HCPtr;
4391	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4392	pVCpu->pgm.s.apGstPaePDsR0[i] = (R0PTRTYPE(PX86PDPAE))HCPtr;
4393	# endif
4394	pVCpu->pgm.s.apGstPaePDsRC[i] = (RCPTRTYPE(PX86PDPAE))GCPtr;
4395	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = GCPhys;
4396	# ifdef IN_RC
4397	PGM_INVL_PG(pVCpu, GCPtr);
4398	# endif
4399	continue;
4400	}
4401	AssertMsgFailed(("pgmR3Gst32BitMapCR3: rc2=%d GCPhys=%RGp i=%d\n", rc2, GCPhys, i));
4402	}
4403
4404	pVCpu->pgm.s.apGstPaePDsR3[i] = 0;
4405	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4406	pVCpu->pgm.s.apGstPaePDsR0[i] = 0;
4407	# endif
4408	pVCpu->pgm.s.apGstPaePDsRC[i] = 0;
4409	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
4410	# ifdef IN_RC
4411	PGM_INVL_PG(pVCpu, GCPtr); /** @todo this shouldn't be necessary? */
4412	# endif
4413	}
4414
4415	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
4416	pVCpu->pgm.s.pGstAmd64Pml4R3 = (R3PTRTYPE(PX86PML4))HCPtrGuestCR3;
4417	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4418	pVCpu->pgm.s.pGstAmd64Pml4R0 = (R0PTRTYPE(PX86PML4))HCPtrGuestCR3;
4419	# endif
4420	# endif
4421	}
4422	else
4423	AssertMsgFailed(("rc=%Rrc GCPhysGuestPD=%RGp\n", rc, GCPhysCR3));
4424	}
4425	else
4426	AssertMsgFailed(("rc=%Rrc GCPhysGuestPD=%RGp\n", rc, GCPhysCR3));
4427
4428	#else /* prot/real stub */
4429	int rc = VINF_SUCCESS;
4430	#endif
4431
4432	/* Update shadow paging info for guest modes with paging (32, pae, 64). */
4433	# if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
4434	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
4435	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64) \
4436	&& ( PGM_GST_TYPE != PGM_TYPE_REAL \
4437	&& PGM_GST_TYPE != PGM_TYPE_PROT))
4438
4439	Assert(!HWACCMIsNestedPagingActive(pVM));
4440
4441	/*
4442	* Update the shadow root page as well since that's not fixed.
4443	*/
4444	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4445	PPGMPOOLPAGE pOldShwPageCR3 = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
4446	uint32_t iOldShwUserTable = pVCpu->pgm.s.iShwUserTable;
4447	uint32_t iOldShwUser = pVCpu->pgm.s.iShwUser;
4448	PPGMPOOLPAGE pNewShwPageCR3;
4449
4450	pgmLock(pVM);
4451
4452	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
4453	if (pPool->cDirtyPages)
4454	pgmPoolResetDirtyPages(pVM);
4455	# endif
4456
4457	Assert(!(GCPhysCR3 >> (PAGE_SHIFT + 32)));
4458	rc = pgmPoolAlloc(pVM, GCPhysCR3 & GST_CR3_PAGE_MASK, BTH_PGMPOOLKIND_ROOT, SHW_POOL_ROOT_IDX, GCPhysCR3 >> PAGE_SHIFT, &pNewShwPageCR3, true /* lock page */);
4459	AssertFatalRC(rc);
4460	rc = VINF_SUCCESS;
4461
4462	# ifdef IN_RC
4463	/*
4464	* WARNING! We can't deal with jumps to ring 3 in the code below as the
4465	* state will be inconsistent! Flush important things now while
4466	* we still can and then make sure there are no ring-3 calls.
4467	*/
4468	REMNotifyHandlerPhysicalFlushIfAlmostFull(pVM, pVCpu);
4469	VMMRZCallRing3Disable(pVCpu);
4470	# endif
4471
4472	pVCpu->pgm.s.iShwUser = SHW_POOL_ROOT_IDX;
4473	pVCpu->pgm.s.iShwUserTable = GCPhysCR3 >> PAGE_SHIFT;
4474	pVCpu->pgm.s.CTX_SUFF(pShwPageCR3) = pNewShwPageCR3;
4475	# ifdef IN_RING0
4476	pVCpu->pgm.s.pShwPageCR3R3 = MMHyperCCToR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4477	pVCpu->pgm.s.pShwPageCR3RC = MMHyperCCToRC(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4478	# elif defined(IN_RC)
4479	pVCpu->pgm.s.pShwPageCR3R3 = MMHyperCCToR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4480	pVCpu->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4481	# else
4482	pVCpu->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4483	pVCpu->pgm.s.pShwPageCR3RC = MMHyperCCToRC(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4484	# endif
4485
4486	# ifndef PGM_WITHOUT_MAPPINGS
4487	/*
4488	* Apply all hypervisor mappings to the new CR3.
4489	* Note that SyncCR3 will be executed in case CR3 is changed in a guest paging mode; this will
4490	* make sure we check for conflicts in the new CR3 root.
4491	*/
4492	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
4493	Assert(VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL) \|\| VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
4494	# endif
4495	rc = pgmMapActivateCR3(pVM, pNewShwPageCR3);
4496	AssertRCReturn(rc, rc);
4497	# endif
4498
4499	/* Set the current hypervisor CR3. */
4500	CPUMSetHyperCR3(pVCpu, PGMGetHyperCR3(pVCpu));
4501	SELMShadowCR3Changed(pVM, pVCpu);
4502
4503	# ifdef IN_RC
4504	/* NOTE: The state is consistent again. */
4505	VMMRZCallRing3Enable(pVCpu);
4506	# endif
4507
4508	/* Clean up the old CR3 root. */
4509	if ( pOldShwPageCR3
4510	&& pOldShwPageCR3 != pNewShwPageCR3 /* @todo can happen due to incorrect syncing between REM & PGM; find the real cause */)
4511	{
4512	Assert(pOldShwPageCR3->enmKind != PGMPOOLKIND_FREE);
4513	# ifndef PGM_WITHOUT_MAPPINGS
4514	/* Remove the hypervisor mappings from the shadow page table. */
4515	pgmMapDeactivateCR3(pVM, pOldShwPageCR3);
4516	# endif
4517	/* Mark the page as unlocked; allow flushing again. */
4518	pgmPoolUnlockPage(pPool, pOldShwPageCR3);
4519
4520	pgmPoolFreeByPage(pPool, pOldShwPageCR3, iOldShwUser, iOldShwUserTable);
4521	}
4522	pgmUnlock(pVM);
4523	# endif
4524
4525	return rc;
4526	}
4527
4528	/**
4529	* Unmaps the shadow CR3.
4530	*
4531	* @returns VBox status, no specials.
4532	* @param pVCpu The VMCPU handle.
4533	*/
4534	PGM_BTH_DECL(int, UnmapCR3)(PVMCPU pVCpu)
4535	{
4536	LogFlow(("UnmapCR3\n"));
4537
4538	int rc = VINF_SUCCESS;
4539	PVM pVM = pVCpu->CTX_SUFF(pVM);
4540
4541	/*
4542	* Update guest paging info.
4543	*/
4544	#if PGM_GST_TYPE == PGM_TYPE_32BIT
4545	pVCpu->pgm.s.pGst32BitPdR3 = 0;
4546	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4547	pVCpu->pgm.s.pGst32BitPdR0 = 0;
4548	# endif
4549	pVCpu->pgm.s.pGst32BitPdRC = 0;
4550
4551	#elif PGM_GST_TYPE == PGM_TYPE_PAE
4552	pVCpu->pgm.s.pGstPaePdptR3 = 0;
4553	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4554	pVCpu->pgm.s.pGstPaePdptR0 = 0;
4555	# endif
4556	pVCpu->pgm.s.pGstPaePdptRC = 0;
4557	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
4558	{
4559	pVCpu->pgm.s.apGstPaePDsR3[i] = 0;
4560	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4561	pVCpu->pgm.s.apGstPaePDsR0[i] = 0;
4562	# endif
4563	pVCpu->pgm.s.apGstPaePDsRC[i] = 0;
4564	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
4565	}
4566
4567	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
4568	pVCpu->pgm.s.pGstAmd64Pml4R3 = 0;
4569	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4570	pVCpu->pgm.s.pGstAmd64Pml4R0 = 0;
4571	# endif
4572
4573	#else /* prot/real mode stub */
4574	/* nothing to do */
4575	#endif
4576
4577	#if !defined(IN_RC) /* In RC we rely on MapCR3 to do the shadow part for us at a safe time */
4578	/*
4579	* Update shadow paging info.
4580	*/
4581	# if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
4582	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
4583	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64))
4584
4585	# if PGM_GST_TYPE != PGM_TYPE_REAL
4586	Assert(!HWACCMIsNestedPagingActive(pVM));
4587	# endif
4588
4589	pgmLock(pVM);
4590
4591	# ifndef PGM_WITHOUT_MAPPINGS
4592	if (pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
4593	/* Remove the hypervisor mappings from the shadow page table. */
4594	pgmMapDeactivateCR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4595	# endif
4596
4597	if (pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
4598	{
4599	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4600
4601	Assert(pVCpu->pgm.s.iShwUser != PGMPOOL_IDX_NESTED_ROOT);
4602
4603	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
4604	if (pPool->cDirtyPages)
4605	pgmPoolResetDirtyPages(pVM);
4606	# endif
4607
4608	/* Mark the page as unlocked; allow flushing again. */
4609	pgmPoolUnlockPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4610
4611	pgmPoolFreeByPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3), pVCpu->pgm.s.iShwUser, pVCpu->pgm.s.iShwUserTable);
4612	pVCpu->pgm.s.pShwPageCR3R3 = 0;
4613	pVCpu->pgm.s.pShwPageCR3R0 = 0;
4614	pVCpu->pgm.s.pShwPageCR3RC = 0;
4615	pVCpu->pgm.s.iShwUser = 0;
4616	pVCpu->pgm.s.iShwUserTable = 0;
4617	}
4618	pgmUnlock(pVM);
4619	# endif
4620	#endif /* !IN_RC*/
4621
4622	return rc;
4623	}
4624

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllBth.h@ 25468

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