PGMAllBth.h@ 45548

Last change on this file since 45548 was 45407, checked in by vboxsync, 12 years ago
VMM: Invalidate page even when it's not present now.
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File size: 204.9 KB

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1	/* $Id: PGMAllBth.h 45407 2013-04-08 13:45:38Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Shadow+Guest Paging Template - All context code.
4	*
5	* @remarks The nested page tables on AMD makes use of PGM_SHW_TYPE in
6	* {PGM_TYPE_AMD64, PGM_TYPE_PAE and PGM_TYPE_32BIT} and PGM_GST_TYPE
7	* set to PGM_TYPE_PROT. Half of the code in this file is not
8	* exercised with PGM_SHW_TYPE set to PGM_TYPE_NESTED.
9	*
10	* @remarks Extended page tables (intel) are built with PGM_GST_TYPE set to
11	* PGM_TYPE_PROT (and PGM_SHW_TYPE set to PGM_TYPE_EPT).
12	*
13	* @remarks This file is one big \#ifdef-orgy!
14	*
15	*/
16
17	/*
18	* Copyright (C) 2006-2013 Oracle Corporation
19	*
20	* This file is part of VirtualBox Open Source Edition (OSE), as
21	* available from http://www.virtualbox.org. This file is free software;
22	* you can redistribute it and/or modify it under the terms of the GNU
23	* General Public License (GPL) as published by the Free Software
24	* Foundation, in version 2 as it comes in the "COPYING" file of the
25	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
26	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
27	*/
28
29	#ifdef _MSC_VER
30	/** @todo we're generating unnecessary code in nested/ept shadow mode and for
31	* real/prot-guest+RC mode. */
32	# pragma warning(disable: 4505)
33	#endif
34
35	/*******************************************************************************
36	* Internal Functions *
37	*******************************************************************************/
38	RT_C_DECLS_BEGIN
39	PGM_BTH_DECL(int, Trap0eHandler)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken);
40	PGM_BTH_DECL(int, InvalidatePage)(PVMCPU pVCpu, RTGCPTR GCPtrPage);
41	static int PGM_BTH_NAME(SyncPage)(PVMCPU pVCpu, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr);
42	static int PGM_BTH_NAME(CheckDirtyPageFault)(PVMCPU pVCpu, uint32_t uErr, PSHWPDE pPdeDst, GSTPDE const *pPdeSrc, RTGCPTR GCPtrPage);
43	static int PGM_BTH_NAME(SyncPT)(PVMCPU pVCpu, unsigned iPD, PGSTPD pPDSrc, RTGCPTR GCPtrPage);
44	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
45	static void PGM_BTH_NAME(SyncPageWorker)(PVMCPU pVCpu, PSHWPTE pPteDst, GSTPDE PdeSrc, GSTPTE PteSrc, PPGMPOOLPAGE pShwPage, unsigned iPTDst);
46	# else
47	static void PGM_BTH_NAME(SyncPageWorker)(PVMCPU pVCpu, PSHWPTE pPteDst, RTGCPHYS GCPhysPage, PPGMPOOLPAGE pShwPage, unsigned iPTDst);
48	#endif
49	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVMCPU pVCpu, RTGCPTR Addr, unsigned fPage, unsigned uErr);
50	PGM_BTH_DECL(int, PrefetchPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage);
51	PGM_BTH_DECL(int, SyncCR3)(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
52	#ifdef VBOX_STRICT
53	PGM_BTH_DECL(unsigned, AssertCR3)(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr = 0, RTGCPTR cb = ~(RTGCPTR)0);
54	#endif
55	PGM_BTH_DECL(int, MapCR3)(PVMCPU pVCpu, RTGCPHYS GCPhysCR3);
56	PGM_BTH_DECL(int, UnmapCR3)(PVMCPU pVCpu);
57	RT_C_DECLS_END
58
59
60	/*
61	* Filter out some illegal combinations of guest and shadow paging, so we can
62	* remove redundant checks inside functions.
63	*/
64	#if PGM_GST_TYPE == PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
65	# error "Invalid combination; PAE guest implies PAE shadow"
66	#endif
67
68	#if (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
69	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT)
70	# error "Invalid combination; real or protected mode without paging implies 32 bits or PAE shadow paging."
71	#endif
72
73	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) \
74	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT)
75	# error "Invalid combination; 32 bits guest paging or PAE implies 32 bits or PAE shadow paging."
76	#endif
77
78	#if (PGM_GST_TYPE == PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT) \
79	\|\| (PGM_SHW_TYPE == PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PROT)
80	# error "Invalid combination; AMD64 guest implies AMD64 shadow and vice versa"
81	#endif
82
83	#ifndef IN_RING3
84
85	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
86	/**
87	* Deal with a guest page fault.
88	*
89	* @returns Strict VBox status code.
90	* @retval VINF_EM_RAW_GUEST_TRAP
91	* @retval VINF_EM_RAW_EMULATE_INSTR
92	*
93	* @param pVCpu The current CPU.
94	* @param pGstWalk The guest page table walk result.
95	* @param uErr The error code.
96	*/
97	PGM_BTH_DECL(VBOXSTRICTRC, Trap0eHandlerGuestFault)(PVMCPU pVCpu, PGSTPTWALK pGstWalk, RTGCUINT uErr)
98	{
99	# if !defined(PGM_WITHOUT_MAPPINGS) && (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE)
100	/*
101	* Check for write conflicts with our hypervisor mapping.
102	*
103	* If the guest happens to access a non-present page, where our hypervisor
104	* is currently mapped, then we'll create a #PF storm in the guest.
105	*/
106	if ( (uErr & (X86_TRAP_PF_P \| X86_TRAP_PF_RW)) == (X86_TRAP_PF_P \| X86_TRAP_PF_RW)
107	&& MMHyperIsInsideArea(pVCpu->CTX_SUFF(pVM), pGstWalk->Core.GCPtr))
108	{
109	/* Force a CR3 sync to check for conflicts and emulate the instruction. */
110	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
111	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2GuestTrap; });
112	return VINF_EM_RAW_EMULATE_INSTR;
113	}
114	# endif
115
116	/*
117	* Calc the error code for the guest trap.
118	*/
119	uint32_t uNewErr = GST_IS_NX_ACTIVE(pVCpu)
120	? uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US \| X86_TRAP_PF_ID)
121	: uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US);
122	if (pGstWalk->Core.fBadPhysAddr)
123	{
124	uNewErr \|= X86_TRAP_PF_RSVD \| X86_TRAP_PF_P;
125	Assert(!pGstWalk->Core.fNotPresent);
126	}
127	else if (!pGstWalk->Core.fNotPresent)
128	uNewErr \|= X86_TRAP_PF_P;
129	TRPMSetErrorCode(pVCpu, uNewErr);
130
131	LogFlow(("Guest trap; cr2=%RGv uErr=%RGv lvl=%d\n", pGstWalk->Core.GCPtr, uErr, pGstWalk->Core.uLevel));
132	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2GuestTrap; });
133	return VINF_EM_RAW_GUEST_TRAP;
134	}
135	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
136
137
138	/**
139	* Deal with a guest page fault.
140	*
141	* The caller has taken the PGM lock.
142	*
143	* @returns Strict VBox status code.
144	*
145	* @param pVCpu The current CPU.
146	* @param uErr The error code.
147	* @param pRegFrame The register frame.
148	* @param pvFault The fault address.
149	* @param pPage The guest page at @a pvFault.
150	* @param pGstWalk The guest page table walk result.
151	* @param pfLockTaken PGM lock taken here or not (out). This is true
152	* when we're called.
153	*/
154	static VBOXSTRICTRC PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame,
155	RTGCPTR pvFault, PPGMPAGE pPage, bool *pfLockTaken
156	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
157	, PGSTPTWALK pGstWalk
158	# endif
159	)
160	{
161	# if !PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
162	GSTPDE const PdeSrcDummy = { X86_PDE_P \| X86_PDE_US \| X86_PDE_RW \| X86_PDE_A };
163	#endif
164	PVM pVM = pVCpu->CTX_SUFF(pVM);
165	int rc;
166
167	if (PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage))
168	{
169	/*
170	* Physical page access handler.
171	*/
172	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
173	const RTGCPHYS GCPhysFault = pGstWalk->Core.GCPhys;
174	# else
175	const RTGCPHYS GCPhysFault = PGM_A20_APPLY(pVCpu, (RTGCPHYS)pvFault);
176	# endif
177	PPGMPHYSHANDLER pCur = pgmHandlerPhysicalLookup(pVM, GCPhysFault);
178	if (pCur)
179	{
180	# ifdef PGM_SYNC_N_PAGES
181	/*
182	* If the region is write protected and we got a page not present fault, then sync
183	* the pages. If the fault was caused by a read, then restart the instruction.
184	* In case of write access continue to the GC write handler.
185	*
186	* ASSUMES that there is only one handler per page or that they have similar write properties.
187	*/
188	if ( !(uErr & X86_TRAP_PF_P)
189	&& pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE)
190	{
191	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
192	rc = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
193	# else
194	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
195	# endif
196	if ( RT_FAILURE(rc)
197	\|\| !(uErr & X86_TRAP_PF_RW)
198	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
199	{
200	AssertRC(rc);
201	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersOutOfSync);
202	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndPhys; });
203	return rc;
204	}
205	}
206	# endif
207	# ifdef PGM_WITH_MMIO_OPTIMIZATIONS
208	/*
209	* If the access was not thru a #PF(RSVD\|...) resync the page.
210	*/
211	if ( !(uErr & X86_TRAP_PF_RSVD)
212	&& pCur->enmType != PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
213	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
214	&& pGstWalk->Core.fEffectiveRW
215	&& !pGstWalk->Core.fEffectiveUS /** @todo Remove pGstWalk->Core.fEffectiveUS and X86_PTE_US further down in the sync code. */
216	# endif
217	)
218	{
219	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
220	rc = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
221	# else
222	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
223	# endif
224	if ( RT_FAILURE(rc)
225	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
226	{
227	AssertRC(rc);
228	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersOutOfSync);
229	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndPhys; });
230	return rc;
231	}
232	}
233	# endif
234
235	AssertMsg( pCur->enmType != PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
236	\|\| (pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE && (uErr & X86_TRAP_PF_RW)),
237	("Unexpected trap for physical handler: %08X (phys=%08x) pPage=%R[pgmpage] uErr=%X, enum=%d\n",
238	pvFault, GCPhysFault, pPage, uErr, pCur->enmType));
239	if (pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE)
240	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersPhysWrite);
241	else
242	{
243	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersPhysAll);
244	if (uErr & X86_TRAP_PF_RSVD) STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersPhysAllOpt);
245	}
246
247	if (pCur->CTX_SUFF(pfnHandler))
248	{
249	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
250	void *pvUser = pCur->CTX_SUFF(pvUser);
251	# ifdef IN_RING0
252	PFNPGMR0PHYSHANDLER pfnHandler = pCur->CTX_SUFF(pfnHandler);
253	# else
254	PFNPGMRCPHYSHANDLER pfnHandler = pCur->CTX_SUFF(pfnHandler);
255	# endif
256
257	STAM_PROFILE_START(&pCur->Stat, h);
258	if (pfnHandler != pPool->CTX_SUFF(pfnAccessHandler))
259	{
260	pgmUnlock(pVM);
261	*pfLockTaken = false;
262	}
263
264	rc = pfnHandler(pVM, uErr, pRegFrame, pvFault, GCPhysFault, pvUser);
265
266	# ifdef VBOX_WITH_STATISTICS
267	pgmLock(pVM);
268	pCur = pgmHandlerPhysicalLookup(pVM, GCPhysFault);
269	if (pCur)
270	STAM_PROFILE_STOP(&pCur->Stat, h);
271	pgmUnlock(pVM);
272	# endif
273	}
274	else
275	rc = VINF_EM_RAW_EMULATE_INSTR;
276
277	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndPhys; });
278	return rc;
279	}
280	}
281	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0)
282	else
283	{
284	# ifdef PGM_SYNC_N_PAGES
285	/*
286	* If the region is write protected and we got a page not present fault, then sync
287	* the pages. If the fault was caused by a read, then restart the instruction.
288	* In case of write access continue to the GC write handler.
289	*/
290	if ( PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) < PGM_PAGE_HNDL_PHYS_STATE_ALL
291	&& !(uErr & X86_TRAP_PF_P))
292	{
293	rc = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
294	if ( RT_FAILURE(rc)
295	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
296	\|\| !(uErr & X86_TRAP_PF_RW))
297	{
298	AssertRC(rc);
299	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersOutOfSync);
300	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndVirt; });
301	return rc;
302	}
303	}
304	# endif
305	/*
306	* Ok, it's an virtual page access handler.
307	*
308	* Since it's faster to search by address, we'll do that first
309	* and then retry by GCPhys if that fails.
310	*/
311	/** @todo r=bird: perhaps we should consider looking up by physical address directly now?
312	* r=svl: true, but lookup on virtual address should remain as a fallback as phys & virt trees might be
313	* out of sync, because the page was changed without us noticing it (not-present -> present
314	* without invlpg or mov cr3, xxx).
315	*/
316	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
317	if (pCur)
318	{
319	AssertMsg(!(pvFault - pCur->Core.Key < pCur->cb)
320	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
321	\|\| !(uErr & X86_TRAP_PF_P)
322	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
323	("Unexpected trap for virtual handler: %RGv (phys=%RGp) pPage=%R[pgmpage] uErr=%X, enum=%d\n",
324	pvFault, pGstWalk->Core.GCPhys, pPage, uErr, pCur->enmType));
325
326	if ( pvFault - pCur->Core.Key < pCur->cb
327	&& ( uErr & X86_TRAP_PF_RW
328	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
329	{
330	# ifdef IN_RC
331	STAM_PROFILE_START(&pCur->Stat, h);
332	RTGCPTR GCPtrStart = pCur->Core.Key;
333	CTX_MID(PFNPGM,VIRTHANDLER) pfnHandler = pCur->CTX_SUFF(pfnHandler);
334	pgmUnlock(pVM);
335	*pfLockTaken = false;
336
337	rc = pfnHandler(pVM, uErr, pRegFrame, pvFault, GCPtrStart, pvFault - GCPtrStart);
338
339	# ifdef VBOX_WITH_STATISTICS
340	pgmLock(pVM);
341	pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
342	if (pCur)
343	STAM_PROFILE_STOP(&pCur->Stat, h);
344	pgmUnlock(pVM);
345	# endif
346	# else
347	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
348	# endif
349	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersVirtual);
350	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndVirt; });
351	return rc;
352	}
353	/* Unhandled part of a monitored page */
354	Log(("Unhandled part of monitored page %RGv\n", pvFault));
355	}
356	else
357	{
358	/* Check by physical address. */
359	unsigned iPage;
360	rc = pgmHandlerVirtualFindByPhysAddr(pVM, pGstWalk->Core.GCPhys, &pCur, &iPage);
361	Assert(RT_SUCCESS(rc) \|\| !pCur);
362	if ( pCur
363	&& ( uErr & X86_TRAP_PF_RW
364	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
365	{
366	Assert((pCur->aPhysToVirt[iPage].Core.Key & X86_PTE_PAE_PG_MASK) == (pGstWalk->Core.GCPhys & X86_PTE_PAE_PG_MASK));
367	# ifdef IN_RC
368	STAM_PROFILE_START(&pCur->Stat, h);
369	RTGCPTR GCPtrStart = pCur->Core.Key;
370	CTX_MID(PFNPGM,VIRTHANDLER) pfnHandler = pCur->CTX_SUFF(pfnHandler);
371	pgmUnlock(pVM);
372	*pfLockTaken = false;
373
374	RTGCPTR off = (iPage << PAGE_SHIFT)
375	+ (pvFault & PAGE_OFFSET_MASK)
376	- (GCPtrStart & PAGE_OFFSET_MASK);
377	Assert(off < pCur->cb);
378	rc = pfnHandler(pVM, uErr, pRegFrame, pvFault, GCPtrStart, off);
379
380	# ifdef VBOX_WITH_STATISTICS
381	pgmLock(pVM);
382	pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, GCPtrStart);
383	if (pCur)
384	STAM_PROFILE_STOP(&pCur->Stat, h);
385	pgmUnlock(pVM);
386	# endif
387	# else
388	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
389	# endif
390	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersVirtualByPhys);
391	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndVirt; });
392	return rc;
393	}
394	}
395	}
396	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
397
398	/*
399	* There is a handled area of the page, but this fault doesn't belong to it.
400	* We must emulate the instruction.
401	*
402	* To avoid crashing (non-fatal) in the interpreter and go back to the recompiler
403	* we first check if this was a page-not-present fault for a page with only
404	* write access handlers. Restart the instruction if it wasn't a write access.
405	*/
406	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersUnhandled);
407
408	if ( !PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
409	&& !(uErr & X86_TRAP_PF_P))
410	{
411	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
412	rc = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
413	# else
414	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
415	# endif
416	if ( RT_FAILURE(rc)
417	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
418	\|\| !(uErr & X86_TRAP_PF_RW))
419	{
420	AssertRC(rc);
421	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersOutOfSync);
422	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndPhys; });
423	return rc;
424	}
425	}
426
427	/** @todo This particular case can cause quite a lot of overhead. E.g. early stage of kernel booting in Ubuntu 6.06
428	* It's writing to an unhandled part of the LDT page several million times.
429	*/
430	rc = VBOXSTRICTRC_TODO(PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault));
431	LogFlow(("PGM: PGMInterpretInstruction -> rc=%d pPage=%R[pgmpage]\n", rc, pPage));
432	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndUnhandled; });
433	return rc;
434	} /* if any kind of handler */
435
436
437	/**
438	* #PF Handler for raw-mode guest execution.
439	*
440	* @returns VBox status code (appropriate for trap handling and GC return).
441	*
442	* @param pVCpu Pointer to the VMCPU.
443	* @param uErr The trap error code.
444	* @param pRegFrame Trap register frame.
445	* @param pvFault The fault address.
446	* @param pfLockTaken PGM lock taken here or not (out)
447	*/
448	PGM_BTH_DECL(int, Trap0eHandler)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken)
449	{
450	PVM pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
451
452	*pfLockTaken = false;
453
454	# if ( PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \
455	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
456	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
457	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT)
458	int rc;
459
460	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
461	/*
462	* Walk the guest page translation tables and check if it's a guest fault.
463	*/
464	GSTPTWALK GstWalk;
465	rc = PGM_GST_NAME(Walk)(pVCpu, pvFault, &GstWalk);
466	if (RT_FAILURE_NP(rc))
467	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerGuestFault)(pVCpu, &GstWalk, uErr));
468
469	/* assert some GstWalk sanity. */
470	# if PGM_GST_TYPE == PGM_TYPE_AMD64
471	/AssertMsg(GstWalk.Pml4e.u == GstWalk.pPml4e->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pml4e.u, (uint64_t)GstWalk.pPml4e->u)); - not always true with SMP guests. /
472	# endif
473	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
474	/AssertMsg(GstWalk.Pdpe.u == GstWalk.pPdpe->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pdpe.u, (uint64_t)GstWalk.pPdpe->u)); - ditto /
475	# endif
476	/AssertMsg(GstWalk.Pde.u == GstWalk.pPde->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pde.u, (uint64_t)GstWalk.pPde->u)); - ditto /
477	/AssertMsg(GstWalk.Core.fBigPage \|\| GstWalk.Pte.u == GstWalk.pPte->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pte.u, (uint64_t)GstWalk.pPte->u)); - ditto /
478	Assert(GstWalk.Core.fSucceeded);
479
480	if (uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US \| X86_TRAP_PF_ID))
481	{
482	if ( ( (uErr & X86_TRAP_PF_RW)
483	&& !GstWalk.Core.fEffectiveRW
484	&& ( (uErr & X86_TRAP_PF_US)
485	\|\| CPUMIsGuestR0WriteProtEnabled(pVCpu)) )
486	\|\| ((uErr & X86_TRAP_PF_US) && !GstWalk.Core.fEffectiveUS)
487	\|\| ((uErr & X86_TRAP_PF_ID) && GstWalk.Core.fEffectiveNX)
488	)
489	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerGuestFault)(pVCpu, &GstWalk, uErr));
490	}
491
492	/*
493	* Set the accessed and dirty flags.
494	*/
495	# if PGM_GST_TYPE == PGM_TYPE_AMD64
496	GstWalk.Pml4e.u \|= X86_PML4E_A;
497	GstWalk.pPml4e->u \|= X86_PML4E_A;
498	GstWalk.Pdpe.u \|= X86_PDPE_A;
499	GstWalk.pPdpe->u \|= X86_PDPE_A;
500	# endif
501	if (GstWalk.Core.fBigPage)
502	{
503	Assert(GstWalk.Pde.b.u1Size);
504	if (uErr & X86_TRAP_PF_RW)
505	{
506	GstWalk.Pde.u \|= X86_PDE4M_A \| X86_PDE4M_D;
507	GstWalk.pPde->u \|= X86_PDE4M_A \| X86_PDE4M_D;
508	}
509	else
510	{
511	GstWalk.Pde.u \|= X86_PDE4M_A;
512	GstWalk.pPde->u \|= X86_PDE4M_A;
513	}
514	}
515	else
516	{
517	Assert(!GstWalk.Pde.b.u1Size);
518	GstWalk.Pde.u \|= X86_PDE_A;
519	GstWalk.pPde->u \|= X86_PDE_A;
520	if (uErr & X86_TRAP_PF_RW)
521	{
522	# ifdef VBOX_WITH_STATISTICS
523	if (!GstWalk.Pte.n.u1Dirty)
524	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtiedPage));
525	else
526	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageAlreadyDirty));
527	# endif
528	GstWalk.Pte.u \|= X86_PTE_A \| X86_PTE_D;
529	GstWalk.pPte->u \|= X86_PTE_A \| X86_PTE_D;
530	}
531	else
532	{
533	GstWalk.Pte.u \|= X86_PTE_A;
534	GstWalk.pPte->u \|= X86_PTE_A;
535	}
536	Assert(GstWalk.Pte.u == GstWalk.pPte->u);
537	}
538	AssertMsg(GstWalk.Pde.u == GstWalk.pPde->u \|\| GstWalk.pPte->u == GstWalk.pPde->u,
539	("%RX64 %RX64 pPte=%p pPde=%p Pte=%RX64\n", (uint64_t)GstWalk.Pde.u, (uint64_t)GstWalk.pPde->u, GstWalk.pPte, GstWalk.pPde, (uint64_t)GstWalk.pPte->u));
540	# else /* !PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
541	GSTPDE const PdeSrcDummy = { X86_PDE_P \| X86_PDE_US \| X86_PDE_RW \| X86_PDE_A}; /** @todo eliminate this */
542	# endif /* !PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
543
544	/* Take the big lock now. */
545	*pfLockTaken = true;
546	pgmLock(pVM);
547
548	# ifdef PGM_WITH_MMIO_OPTIMIZATIONS
549	/*
550	* If it is a reserved bit fault we know that it is an MMIO (access
551	* handler) related fault and can skip some 200 lines of code.
552	*/
553	if (uErr & X86_TRAP_PF_RSVD)
554	{
555	Assert(uErr & X86_TRAP_PF_P);
556	PPGMPAGE pPage;
557	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
558	rc = pgmPhysGetPageEx(pVM, GstWalk.Core.GCPhys, &pPage);
559	if (RT_SUCCESS(rc) && PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
560	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage,
561	pfLockTaken, &GstWalk));
562	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
563	# else
564	rc = pgmPhysGetPageEx(pVM, PGM_A20_APPLY(pVCpu, (RTGCPHYS)pvFault), &pPage);
565	if (RT_SUCCESS(rc) && PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
566	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage,
567	pfLockTaken));
568	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, 1, uErr);
569	# endif
570	AssertRC(rc);
571	PGM_INVL_PG(pVCpu, pvFault);
572	return rc; /* Restart with the corrected entry. */
573	}
574	# endif /* PGM_WITH_MMIO_OPTIMIZATIONS */
575
576	/*
577	* Fetch the guest PDE, PDPE and PML4E.
578	*/
579	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
580	const unsigned iPDDst = pvFault >> SHW_PD_SHIFT;
581	PX86PD pPDDst = pgmShwGet32BitPDPtr(pVCpu);
582
583	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
584	const unsigned iPDDst = (pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK; /* pPDDst index, not used with the pool. */
585	PX86PDPAE pPDDst;
586	# if PGM_GST_TYPE == PGM_TYPE_PAE
587	rc = pgmShwSyncPaePDPtr(pVCpu, pvFault, GstWalk.Pdpe.u, &pPDDst);
588	# else
589	rc = pgmShwSyncPaePDPtr(pVCpu, pvFault, X86_PDPE_P, &pPDDst); /* RW, US and A are reserved in PAE mode. */
590	# endif
591	AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
592
593	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
594	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
595	PX86PDPAE pPDDst;
596	# if PGM_GST_TYPE == PGM_TYPE_PROT /* (AMD-V nested paging) */
597	rc = pgmShwSyncLongModePDPtr(pVCpu, pvFault, X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A,
598	X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A, &pPDDst);
599	# else
600	rc = pgmShwSyncLongModePDPtr(pVCpu, pvFault, GstWalk.Pml4e.u, GstWalk.Pdpe.u, &pPDDst);
601	# endif
602	AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
603
604	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
605	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
606	PEPTPD pPDDst;
607	rc = pgmShwGetEPTPDPtr(pVCpu, pvFault, NULL, &pPDDst);
608	AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
609	# endif
610	Assert(pPDDst);
611
612	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
613	/*
614	* Dirty page handling.
615	*
616	* If we successfully correct the write protection fault due to dirty bit
617	* tracking, then return immediately.
618	*/
619	if (uErr & X86_TRAP_PF_RW) /* write fault? */
620	{
621	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyBitTracking), a);
622	rc = PGM_BTH_NAME(CheckDirtyPageFault)(pVCpu, uErr, &pPDDst->a[iPDDst], GstWalk.pPde, pvFault);
623	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyBitTracking), a);
624	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
625	{
626	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution)
627	= rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT
628	? &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2DirtyAndAccessed
629	: &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2GuestTrap; });
630	LogBird(("Trap0eHandler: returns VINF_SUCCESS\n"));
631	return VINF_SUCCESS;
632	}
633	//AssertMsg(GstWalk.Pde.u == GstWalk.pPde->u \|\| GstWalk.pPte->u == GstWalk.pPde->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pde.u, (uint64_t)GstWalk.pPde->u)); - triggers with smp w7 guests.
634	//AssertMsg(GstWalk.Core.fBigPage \|\| GstWalk.Pte.u == GstWalk.pPte->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pte.u, (uint64_t)GstWalk.pPte->u)); - ditto.
635	}
636
637	# if 0 /* rarely useful; leave for debugging. */
638	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0ePD[iPDSrc]);
639	# endif
640	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
641
642	/*
643	* A common case is the not-present error caused by lazy page table syncing.
644	*
645	* It is IMPORTANT that we weed out any access to non-present shadow PDEs
646	* here so we can safely assume that the shadow PT is present when calling
647	* SyncPage later.
648	*
649	* On failure, we ASSUME that SyncPT is out of memory or detected some kind
650	* of mapping conflict and defer to SyncCR3 in R3.
651	* (Again, we do NOT support access handlers for non-present guest pages.)
652	*
653	*/
654	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
655	Assert(GstWalk.Pde.n.u1Present);
656	# endif
657	if ( !(uErr & X86_TRAP_PF_P) /* not set means page not present instead of page protection violation */
658	&& !pPDDst->a[iPDDst].n.u1Present)
659	{
660	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2SyncPT; });
661	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
662	LogFlow(("=>SyncPT %04x = %08RX64\n", (pvFault >> GST_PD_SHIFT) & GST_PD_MASK, (uint64_t)GstWalk.Pde.u));
663	rc = PGM_BTH_NAME(SyncPT)(pVCpu, (pvFault >> GST_PD_SHIFT) & GST_PD_MASK, GstWalk.pPd, pvFault);
664	# else
665	LogFlow(("=>SyncPT pvFault=%RGv\n", pvFault));
666	rc = PGM_BTH_NAME(SyncPT)(pVCpu, 0, NULL, pvFault);
667	# endif
668	if (RT_SUCCESS(rc))
669	return rc;
670	Log(("SyncPT: %RGv failed!! rc=%Rrc\n", pvFault, rc));
671	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync, right? */
672	return VINF_PGM_SYNC_CR3;
673	}
674
675	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(PGM_WITHOUT_MAPPINGS)
676	/*
677	* Check if this address is within any of our mappings.
678	*
679	* This is very fast and it's gonna save us a bit of effort below and prevent
680	* us from screwing ourself with MMIO2 pages which have a GC Mapping (VRam).
681	* (BTW, it's impossible to have physical access handlers in a mapping.)
682	*/
683	if (pgmMapAreMappingsEnabled(pVM))
684	{
685	PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
686	for ( ; pMapping; pMapping = pMapping->CTX_SUFF(pNext))
687	{
688	if (pvFault < pMapping->GCPtr)
689	break;
690	if (pvFault - pMapping->GCPtr < pMapping->cb)
691	{
692	/*
693	* The first thing we check is if we've got an undetected conflict.
694	*/
695	if (pgmMapAreMappingsFloating(pVM))
696	{
697	unsigned iPT = pMapping->cb >> GST_PD_SHIFT;
698	while (iPT-- > 0)
699	if (GstWalk.pPde[iPT].n.u1Present)
700	{
701	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eConflicts);
702	Log(("Trap0e: Detected Conflict %RGv-%RGv\n", pMapping->GCPtr, pMapping->GCPtrLast));
703	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync,right? */
704	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Mapping; });
705	return VINF_PGM_SYNC_CR3;
706	}
707	}
708
709	/*
710	* Check if the fault address is in a virtual page access handler range.
711	*/
712	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->HyperVirtHandlers, pvFault);
713	if ( pCur
714	&& pvFault - pCur->Core.Key < pCur->cb
715	&& uErr & X86_TRAP_PF_RW)
716	{
717	# ifdef IN_RC
718	STAM_PROFILE_START(&pCur->Stat, h);
719	pgmUnlock(pVM);
720	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
721	pgmLock(pVM);
722	STAM_PROFILE_STOP(&pCur->Stat, h);
723	# else
724	AssertFailed();
725	rc = VINF_EM_RAW_EMULATE_INSTR; /* can't happen with VMX */
726	# endif
727	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersMapping);
728	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Mapping; });
729	return rc;
730	}
731
732	/*
733	* Pretend we're not here and let the guest handle the trap.
734	*/
735	TRPMSetErrorCode(pVCpu, uErr & ~X86_TRAP_PF_P);
736	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eGuestPFMapping);
737	LogFlow(("PGM: Mapping access -> route trap to recompiler!\n"));
738	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Mapping; });
739	return VINF_EM_RAW_GUEST_TRAP;
740	}
741	}
742	} /* pgmAreMappingsEnabled(&pVM->pgm.s) */
743	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
744
745	/*
746	* Check if this fault address is flagged for special treatment,
747	* which means we'll have to figure out the physical address and
748	* check flags associated with it.
749	*
750	* ASSUME that we can limit any special access handling to pages
751	* in page tables which the guest believes to be present.
752	*/
753	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
754	RTGCPHYS GCPhys = GstWalk.Core.GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK;
755	# else
756	RTGCPHYS GCPhys = PGM_A20_APPLY(pVCpu, (RTGCPHYS)pvFault & ~(RTGCPHYS)PAGE_OFFSET_MASK);
757	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
758	PPGMPAGE pPage;
759	rc = pgmPhysGetPageEx(pVM, GCPhys, &pPage);
760	if (RT_FAILURE(rc))
761	{
762	/*
763	* When the guest accesses invalid physical memory (e.g. probing
764	* of RAM or accessing a remapped MMIO range), then we'll fall
765	* back to the recompiler to emulate the instruction.
766	*/
767	LogFlow(("PGM #PF: pgmPhysGetPageEx(%RGp) failed with %Rrc\n", GCPhys, rc));
768	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersInvalid);
769	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2InvalidPhys; });
770	return VINF_EM_RAW_EMULATE_INSTR;
771	}
772
773	/*
774	* Any handlers for this page?
775	*/
776	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
777	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
778	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage, pfLockTaken,
779	&GstWalk));
780	# else
781	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage, pfLockTaken));
782	# endif
783
784	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTimeOutOfSync, c);
785
786	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0)
787	if (uErr & X86_TRAP_PF_P)
788	{
789	/*
790	* The page isn't marked, but it might still be monitored by a virtual page access handler.
791	* (ASSUMES no temporary disabling of virtual handlers.)
792	*/
793	/** @todo r=bird: Since the purpose is to catch out of sync pages with virtual handler(s) here,
794	* we should correct both the shadow page table and physical memory flags, and not only check for
795	* accesses within the handler region but for access to pages with virtual handlers. */
796	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
797	if (pCur)
798	{
799	AssertMsg( !(pvFault - pCur->Core.Key < pCur->cb)
800	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
801	\|\| !(uErr & X86_TRAP_PF_P)
802	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
803	("Unexpected trap for virtual handler: %08X (phys=%08x) %R[pgmpage] uErr=%X, enum=%d\n", pvFault, GCPhys, pPage, uErr, pCur->enmType));
804
805	if ( pvFault - pCur->Core.Key < pCur->cb
806	&& ( uErr & X86_TRAP_PF_RW
807	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
808	{
809	# ifdef IN_RC
810	STAM_PROFILE_START(&pCur->Stat, h);
811	pgmUnlock(pVM);
812	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
813	pgmLock(pVM);
814	STAM_PROFILE_STOP(&pCur->Stat, h);
815	# else
816	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
817	# endif
818	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndVirt; });
819	return rc;
820	}
821	}
822	}
823	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
824
825	/*
826	* We are here only if page is present in Guest page tables and
827	* trap is not handled by our handlers.
828	*
829	* Check it for page out-of-sync situation.
830	*/
831	if (!(uErr & X86_TRAP_PF_P))
832	{
833	/*
834	* Page is not present in our page tables. Try to sync it!
835	*/
836	if (uErr & X86_TRAP_PF_US)
837	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncUser));
838	else /* supervisor */
839	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
840
841	if (PGM_PAGE_IS_BALLOONED(pPage))
842	{
843	/* Emulate reads from ballooned pages as they are not present in
844	our shadow page tables. (Required for e.g. Solaris guests; soft
845	ecc, random nr generator.) */
846	rc = VBOXSTRICTRC_TODO(PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault));
847	LogFlow(("PGM: PGMInterpretInstruction balloon -> rc=%d pPage=%R[pgmpage]\n", rc, pPage));
848	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncBallloon));
849	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Ballooned; });
850	return rc;
851	}
852
853	# if defined(LOG_ENABLED) && !defined(IN_RING0)
854	RTGCPHYS GCPhys2;
855	uint64_t fPageGst2;
856	PGMGstGetPage(pVCpu, pvFault, &fPageGst2, &GCPhys2);
857	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
858	Log(("Page out of sync: %RGv eip=%08x PdeSrc.US=%d fPageGst2=%08llx GCPhys2=%RGp scan=%d\n",
859	pvFault, pRegFrame->eip, GstWalk.Pde.n.u1User, fPageGst2, GCPhys2, CSAMDoesPageNeedScanning(pVM, pRegFrame->eip)));
860	# else
861	Log(("Page out of sync: %RGv eip=%08x fPageGst2=%08llx GCPhys2=%RGp scan=%d\n",
862	pvFault, pRegFrame->eip, fPageGst2, GCPhys2, CSAMDoesPageNeedScanning(pVM, pRegFrame->eip)));
863	# endif
864	# endif /* LOG_ENABLED */
865
866	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0)
867	if ( !GstWalk.Core.fEffectiveUS
868	&& CPUMGetGuestCPL(pVCpu) == 0)
869	{
870	/* Note: Can't check for X86_TRAP_ID bit, because that requires execute disable support on the CPU. */
871	if ( pvFault == (RTGCPTR)pRegFrame->eip
872	\|\| pvFault - pRegFrame->eip < 8 /* instruction crossing a page boundary */
873	# ifdef CSAM_DETECT_NEW_CODE_PAGES
874	\|\| ( !PATMIsPatchGCAddr(pVM, pRegFrame->eip)
875	&& CSAMDoesPageNeedScanning(pVM, pRegFrame->eip)) /* any new code we encounter here */
876	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
877	)
878	{
879	LogFlow(("CSAMExecFault %RX32\n", pRegFrame->eip));
880	rc = CSAMExecFault(pVM, (RTRCPTR)pRegFrame->eip);
881	if (rc != VINF_SUCCESS)
882	{
883	/*
884	* CSAM needs to perform a job in ring 3.
885	*
886	* Sync the page before going to the host context; otherwise we'll end up in a loop if
887	* CSAM fails (e.g. instruction crosses a page boundary and the next page is not present)
888	*/
889	LogFlow(("CSAM ring 3 job\n"));
890	int rc2 = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
891	AssertRC(rc2);
892
893	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2CSAM; });
894	return rc;
895	}
896	}
897	# ifdef CSAM_DETECT_NEW_CODE_PAGES
898	else if ( uErr == X86_TRAP_PF_RW
899	&& pRegFrame->ecx >= 0x100 /* early check for movswd count */
900	&& pRegFrame->ecx < 0x10000)
901	{
902	/* In case of a write to a non-present supervisor shadow page, we'll take special precautions
903	* to detect loading of new code pages.
904	*/
905
906	/*
907	* Decode the instruction.
908	*/
909	PDISCPUSTATE pDis = &pVCpu->pgm.s.DisState;
910	uint32_t cbOp;
911	rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
912
913	/* For now we'll restrict this to rep movsw/d instructions */
914	if ( rc == VINF_SUCCESS
915	&& pDis->pCurInstr->opcode == OP_MOVSWD
916	&& (pDis->prefix & DISPREFIX_REP))
917	{
918	CSAMMarkPossibleCodePage(pVM, pvFault);
919	}
920	}
921	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
922
923	/*
924	* Mark this page as safe.
925	*/
926	/** @todo not correct for pages that contain both code and data!! */
927	Log2(("CSAMMarkPage %RGv; scanned=%d\n", pvFault, true));
928	CSAMMarkPage(pVM, pvFault, true);
929	}
930	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0) */
931	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
932	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
933	# else
934	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
935	# endif
936	if (RT_SUCCESS(rc))
937	{
938	/* The page was successfully synced, return to the guest. */
939	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSync; });
940	return VINF_SUCCESS;
941	}
942	}
943	else /* uErr & X86_TRAP_PF_P: */
944	{
945	/*
946	* Write protected pages are made writable when the guest makes the
947	* first write to it. This happens for pages that are shared, write
948	* monitored or not yet allocated.
949	*
950	* We may also end up here when CR0.WP=0 in the guest.
951	*
952	* Also, a side effect of not flushing global PDEs are out of sync
953	* pages due to physical monitored regions, that are no longer valid.
954	* Assume for now it only applies to the read/write flag.
955	*/
956	if (uErr & X86_TRAP_PF_RW)
957	{
958	/*
959	* Check if it is a read-only page.
960	*/
961	if (PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
962	{
963	Log(("PGM #PF: Make writable: %RGp %R[pgmpage] pvFault=%RGp uErr=%#x\n", GCPhys, pPage, pvFault, uErr));
964	Assert(!PGM_PAGE_IS_ZERO(pPage));
965	AssertFatalMsg(!PGM_PAGE_IS_BALLOONED(pPage), ("Unexpected ballooned page at %RGp\n", GCPhys));
966	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2MakeWritable; });
967
968	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
969	if (rc != VINF_SUCCESS)
970	{
971	AssertMsg(rc == VINF_PGM_SYNC_CR3 \|\| RT_FAILURE(rc), ("%Rrc\n", rc));
972	return rc;
973	}
974	if (RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)))
975	return VINF_EM_NO_MEMORY;
976	}
977
978	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
979	/*
980	* Check to see if we need to emulate the instruction if CR0.WP=0.
981	*/
982	if ( !GstWalk.Core.fEffectiveRW
983	&& (CPUMGetGuestCR0(pVCpu) & (X86_CR0_WP \| X86_CR0_PG)) == X86_CR0_PG
984	&& CPUMGetGuestCPL(pVCpu) == 0)
985	{
986	Assert((uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RW \| X86_TRAP_PF_P));
987	rc = VBOXSTRICTRC_TODO(PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault));
988	if (RT_SUCCESS(rc))
989	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eWPEmulInRZ);
990	else
991	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eWPEmulToR3);
992	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2WPEmulation; });
993	return rc;
994	}
995	# endif
996	/// @todo count the above case; else
997	if (uErr & X86_TRAP_PF_US)
998	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncUserWrite));
999	else /* supervisor */
1000	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncSupervisorWrite));
1001
1002	/*
1003	* Sync the page.
1004	*
1005	* Note: Do NOT use PGM_SYNC_NR_PAGES here. That only works if the
1006	* page is not present, which is not true in this case.
1007	*/
1008	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1009	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
1010	# else
1011	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, 1, uErr);
1012	# endif
1013	if (RT_SUCCESS(rc))
1014	{
1015	/*
1016	* Page was successfully synced, return to guest but invalidate
1017	* the TLB first as the page is very likely to be in it.
1018	*/
1019	# if PGM_SHW_TYPE == PGM_TYPE_EPT
1020	HMInvalidatePhysPage(pVM, (RTGCPHYS)pvFault);
1021	# else
1022	PGM_INVL_PG(pVCpu, pvFault);
1023	# endif
1024	# ifdef VBOX_STRICT
1025	RTGCPHYS GCPhys2;
1026	uint64_t fPageGst;
1027	if (!pVM->pgm.s.fNestedPaging)
1028	{
1029	rc = PGMGstGetPage(pVCpu, pvFault, &fPageGst, &GCPhys2);
1030	AssertMsg(RT_SUCCESS(rc) && (fPageGst & X86_PTE_RW), ("rc=%Rrc fPageGst=%RX64\n", rc, fPageGst));
1031	LogFlow(("Obsolete physical monitor page out of sync %RGv - phys %RGp flags=%08llx\n", pvFault, GCPhys2, (uint64_t)fPageGst));
1032	}
1033	uint64_t fPageShw;
1034	rc = PGMShwGetPage(pVCpu, pvFault, &fPageShw, NULL);
1035	AssertMsg((RT_SUCCESS(rc) && (fPageShw & X86_PTE_RW)) \|\| pVM->cCpus > 1 /* new monitor can be installed/page table flushed between the trap exit and PGMTrap0eHandler */,
1036	("rc=%Rrc fPageShw=%RX64\n", rc, fPageShw));
1037	# endif /* VBOX_STRICT */
1038	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndObs; });
1039	return VINF_SUCCESS;
1040	}
1041	}
1042	/** @todo else: why are we here? */
1043
1044	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && defined(VBOX_STRICT)
1045	/*
1046	* Check for VMM page flags vs. Guest page flags consistency.
1047	* Currently only for debug purposes.
1048	*/
1049	if (RT_SUCCESS(rc))
1050	{
1051	/* Get guest page flags. */
1052	uint64_t fPageGst;
1053	rc = PGMGstGetPage(pVCpu, pvFault, &fPageGst, NULL);
1054	if (RT_SUCCESS(rc))
1055	{
1056	uint64_t fPageShw;
1057	rc = PGMShwGetPage(pVCpu, pvFault, &fPageShw, NULL);
1058
1059	/*
1060	* Compare page flags.
1061	* Note: we have AVL, A, D bits desynced.
1062	*/
1063	AssertMsg( (fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK))
1064	== (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)),
1065	("Page flags mismatch! pvFault=%RGv uErr=%x GCPhys=%RGp fPageShw=%RX64 fPageGst=%RX64\n",
1066	pvFault, (uint32_t)uErr, GCPhys, fPageShw, fPageGst));
1067	}
1068	else
1069	AssertMsgFailed(("PGMGstGetPage rc=%Rrc\n", rc));
1070	}
1071	else
1072	AssertMsgFailed(("PGMGCGetPage rc=%Rrc\n", rc));
1073	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && VBOX_STRICT */
1074	}
1075
1076
1077	/*
1078	* If we get here it is because something failed above, i.e. most like guru
1079	* meditiation time.
1080	*/
1081	LogRel(("%s: returns rc=%Rrc pvFault=%RGv uErr=%RX64 cs:rip=%04x:%08RX64\n",
1082	__PRETTY_FUNCTION__, rc, pvFault, (uint64_t)uErr, pRegFrame->cs.Sel, pRegFrame->rip));
1083	return rc;
1084
1085	# else /* Nested paging, EPT except PGM_GST_TYPE = PROT */
1086	NOREF(uErr); NOREF(pRegFrame); NOREF(pvFault);
1087	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
1088	return VERR_PGM_NOT_USED_IN_MODE;
1089	# endif
1090	}
1091	#endif /* !IN_RING3 */
1092
1093
1094	/**
1095	* Emulation of the invlpg instruction.
1096	*
1097	*
1098	* @returns VBox status code.
1099	*
1100	* @param pVCpu Pointer to the VMCPU.
1101	* @param GCPtrPage Page to invalidate.
1102	*
1103	* @remark ASSUMES that the guest is updating before invalidating. This order
1104	* isn't required by the CPU, so this is speculative and could cause
1105	* trouble.
1106	* @remark No TLB shootdown is done on any other VCPU as we assume that
1107	* invlpg emulation is the only reason for calling this function.
1108	* (The guest has to shoot down TLB entries on other CPUs itself)
1109	* Currently true, but keep in mind!
1110	*
1111	* @todo Clean this up! Most of it is (or should be) no longer necessary as we catch all page table accesses.
1112	* Should only be required when PGMPOOL_WITH_OPTIMIZED_DIRTY_PT is active (PAE or AMD64 (for now))
1113	*/
1114	PGM_BTH_DECL(int, InvalidatePage)(PVMCPU pVCpu, RTGCPTR GCPtrPage)
1115	{
1116	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
1117	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
1118	&& PGM_SHW_TYPE != PGM_TYPE_EPT
1119	int rc;
1120	PVM pVM = pVCpu->CTX_SUFF(pVM);
1121	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1122
1123	PGM_LOCK_ASSERT_OWNER(pVM);
1124
1125	LogFlow(("InvalidatePage %RGv\n", GCPtrPage));
1126
1127	/*
1128	* Get the shadow PD entry and skip out if this PD isn't present.
1129	* (Guessing that it is frequent for a shadow PDE to not be present, do this first.)
1130	*/
1131	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1132	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1133	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
1134
1135	/* Fetch the pgm pool shadow descriptor. */
1136	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
1137	Assert(pShwPde);
1138
1139	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1140	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT);
1141	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(pVCpu);
1142
1143	/* If the shadow PDPE isn't present, then skip the invalidate. */
1144	if (!pPdptDst->a[iPdpt].n.u1Present)
1145	{
1146	Assert(!(pPdptDst->a[iPdpt].u & PGM_PLXFLAGS_MAPPING));
1147	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1148	return VINF_SUCCESS;
1149	}
1150
1151	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1152	PPGMPOOLPAGE pShwPde = NULL;
1153	PX86PDPAE pPDDst;
1154
1155	/* Fetch the pgm pool shadow descriptor. */
1156	rc = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
1157	AssertRCSuccessReturn(rc, rc);
1158	Assert(pShwPde);
1159
1160	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
1161	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1162
1163	# else /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
1164	/* PML4 */
1165	/const unsigned iPml4 = (GCPtrPage >> X86_PML4_SHIFT) & X86_PML4_MASK;/
1166	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1167	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1168	PX86PDPAE pPDDst;
1169	PX86PDPT pPdptDst;
1170	PX86PML4E pPml4eDst;
1171	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eDst, &pPdptDst, &pPDDst);
1172	if (rc != VINF_SUCCESS)
1173	{
1174	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT \|\| rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
1175	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1176	return VINF_SUCCESS;
1177	}
1178	Assert(pPDDst);
1179
1180	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1181	PX86PDPE pPdpeDst = &pPdptDst->a[iPdpt];
1182
1183	if (!pPdpeDst->n.u1Present)
1184	{
1185	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1186	return VINF_SUCCESS;
1187	}
1188
1189	/* Fetch the pgm pool shadow descriptor. */
1190	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & SHW_PDPE_PG_MASK);
1191	Assert(pShwPde);
1192
1193	# endif /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
1194
1195	const SHWPDE PdeDst = *pPdeDst;
1196	if (!PdeDst.n.u1Present)
1197	{
1198	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1199	PGM_INVL_PG(pVCpu, GCPtrPage);
1200	return VINF_SUCCESS;
1201	}
1202
1203	/*
1204	* Get the guest PD entry and calc big page.
1205	*/
1206	# if PGM_GST_TYPE == PGM_TYPE_32BIT
1207	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
1208	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
1209	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
1210	# else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1211	unsigned iPDSrc = 0;
1212	# if PGM_GST_TYPE == PGM_TYPE_PAE
1213	X86PDPE PdpeSrcIgn;
1214	PX86PDPAE pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtrPage, &iPDSrc, &PdpeSrcIgn);
1215	# else /* AMD64 */
1216	PX86PML4E pPml4eSrcIgn;
1217	X86PDPE PdpeSrcIgn;
1218	PX86PDPAE pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eSrcIgn, &PdpeSrcIgn, &iPDSrc);
1219	# endif
1220	GSTPDE PdeSrc;
1221
1222	if (pPDSrc)
1223	PdeSrc = pPDSrc->a[iPDSrc];
1224	else
1225	PdeSrc.u = 0;
1226	# endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1227	const bool fIsBigPage = PdeSrc.b.u1Size && GST_IS_PSE_ACTIVE(pVCpu);
1228
1229	# ifdef IN_RING3
1230	/*
1231	* If a CR3 Sync is pending we may ignore the invalidate page operation
1232	* depending on the kind of sync and if it's a global page or not.
1233	* This doesn't make sense in GC/R0 so we'll skip it entirely there.
1234	*/
1235	# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
1236	if ( VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3)
1237	\|\| ( VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
1238	&& fIsBigPage
1239	&& PdeSrc.b.u1Global
1240	)
1241	)
1242	# else
1243	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL) )
1244	# endif
1245	{
1246	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1247	return VINF_SUCCESS;
1248	}
1249	# endif /* IN_RING3 */
1250
1251	/*
1252	* Deal with the Guest PDE.
1253	*/
1254	rc = VINF_SUCCESS;
1255	if (PdeSrc.n.u1Present)
1256	{
1257	Assert( PdeSrc.n.u1User == PdeDst.n.u1User
1258	&& (PdeSrc.n.u1Write \|\| !PdeDst.n.u1Write));
1259	# ifndef PGM_WITHOUT_MAPPING
1260	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
1261	{
1262	/*
1263	* Conflict - Let SyncPT deal with it to avoid duplicate code.
1264	*/
1265	Assert(pgmMapAreMappingsEnabled(pVM));
1266	Assert(PGMGetGuestMode(pVCpu) <= PGMMODE_PAE);
1267	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
1268	}
1269	else
1270	# endif /* !PGM_WITHOUT_MAPPING */
1271	if (!fIsBigPage)
1272	{
1273	/*
1274	* 4KB - page.
1275	*/
1276	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1277	RTGCPHYS GCPhys = GST_GET_PDE_GCPHYS(PdeSrc);
1278
1279	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1280	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1281	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| ((iPDDst & 1) * (PAGE_SIZE / 2)));
1282	# endif
1283	if (pShwPage->GCPhys == GCPhys)
1284	{
1285	/* Syncing it here isn't 100% safe and it's probably not worth spending time syncing it. */
1286	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1287
1288	PGSTPT pPTSrc;
1289	rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GST_GET_PDE_GCPHYS(PdeSrc), &pPTSrc);
1290	if (RT_SUCCESS(rc))
1291	{
1292	const unsigned iPTSrc = (GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK;
1293	GSTPTE PteSrc = pPTSrc->a[iPTSrc];
1294	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1295	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1296	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx %s\n",
1297	GCPtrPage, PteSrc.n.u1Present,
1298	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1299	PteSrc.n.u1User & PdeSrc.n.u1User,
1300	(uint64_t)PteSrc.u,
1301	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
1302	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
1303	}
1304	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePage4KBPages));
1305	PGM_INVL_PG(pVCpu, GCPtrPage);
1306	}
1307	else
1308	{
1309	/*
1310	* The page table address changed.
1311	*/
1312	LogFlow(("InvalidatePage: Out-of-sync at %RGp PdeSrc=%RX64 PdeDst=%RX64 ShwGCPhys=%RGp iPDDst=%#x\n",
1313	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, iPDDst));
1314	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1315	ASMAtomicWriteSize(pPdeDst, 0);
1316	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1317	PGM_INVL_VCPU_TLBS(pVCpu);
1318	}
1319	}
1320	else
1321	{
1322	/*
1323	* 2/4MB - page.
1324	*/
1325	/* Before freeing the page, check if anything really changed. */
1326	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1327	RTGCPHYS GCPhys = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
1328	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1329	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1330	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| (GCPtrPage & (1 << X86_PD_PAE_SHIFT)));
1331	# endif
1332	if ( pShwPage->GCPhys == GCPhys
1333	&& pShwPage->enmKind == BTH_PGMPOOLKIND_PT_FOR_BIG)
1334	{
1335	/* ASSUMES a the given bits are identical for 4M and normal PDEs */
1336	/** @todo This test is wrong as it cannot check the G bit!
1337	* FIXME */
1338	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US))
1339	== (PdeDst.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US))
1340	&& ( PdeSrc.b.u1Dirty /** @todo rainy day: What about read-only 4M pages? not very common, but still... */
1341	\|\| (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)))
1342	{
1343	LogFlow(("Skipping flush for big page containing %RGv (PD=%X .u=%RX64)-> nothing has changed!\n", GCPtrPage, iPDSrc, PdeSrc.u));
1344	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePage4MBPagesSkip));
1345	return VINF_SUCCESS;
1346	}
1347	}
1348
1349	/*
1350	* Ok, the page table is present and it's been changed in the guest.
1351	* If we're in host context, we'll just mark it as not present taking the lazy approach.
1352	* We could do this for some flushes in GC too, but we need an algorithm for
1353	* deciding which 4MB pages containing code likely to be executed very soon.
1354	*/
1355	LogFlow(("InvalidatePage: Out-of-sync PD at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
1356	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1357	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1358	ASMAtomicWriteSize(pPdeDst, 0);
1359	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePage4MBPages));
1360	PGM_INVL_BIG_PG(pVCpu, GCPtrPage);
1361	}
1362	}
1363	else
1364	{
1365	/*
1366	* Page directory is not present, mark shadow PDE not present.
1367	*/
1368	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
1369	{
1370	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1371	ASMAtomicWriteSize(pPdeDst, 0);
1372	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePagePDNPs));
1373	PGM_INVL_PG(pVCpu, GCPtrPage);
1374	}
1375	else
1376	{
1377	Assert(pgmMapAreMappingsEnabled(pVM));
1378	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePagePDMappings));
1379	}
1380	}
1381	return rc;
1382
1383	#else /* guest real and protected mode */
1384	/* There's no such thing as InvalidatePage when paging is disabled, so just ignore. */
1385	NOREF(pVCpu); NOREF(GCPtrPage);
1386	return VINF_SUCCESS;
1387	#endif
1388	}
1389
1390
1391	/**
1392	* Update the tracking of shadowed pages.
1393	*
1394	* @param pVCpu Pointer to the VMCPU.
1395	* @param pShwPage The shadow page.
1396	* @param HCPhys The physical page we is being dereferenced.
1397	* @param iPte Shadow PTE index
1398	* @param GCPhysPage Guest physical address (only valid if pShwPage->fDirty is set)
1399	*/
1400	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVMCPU pVCpu, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys, uint16_t iPte,
1401	RTGCPHYS GCPhysPage)
1402	{
1403	PVM pVM = pVCpu->CTX_SUFF(pVM);
1404
1405	# if defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT) \
1406	&& PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
1407	&& (PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_PAE /* pae/32bit combo */)
1408
1409	/* Use the hint we retrieved from the cached guest PT. */
1410	if (pShwPage->fDirty)
1411	{
1412	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1413
1414	Assert(pShwPage->cPresent);
1415	Assert(pPool->cPresent);
1416	pShwPage->cPresent--;
1417	pPool->cPresent--;
1418
1419	PPGMPAGE pPhysPage = pgmPhysGetPage(pVM, GCPhysPage);
1420	AssertRelease(pPhysPage);
1421	pgmTrackDerefGCPhys(pPool, pShwPage, pPhysPage, iPte);
1422	return;
1423	}
1424	# else
1425	NOREF(GCPhysPage);
1426	# endif
1427
1428	STAM_PROFILE_START(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackDeref, a);
1429	LogFlow(("SyncPageWorkerTrackDeref: Damn HCPhys=%RHp pShwPage->idx=%#x!!!\n", HCPhys, pShwPage->idx));
1430
1431	/** @todo If this turns out to be a bottle neck (very likely) two things can be done:
1432	* 1. have a medium sized HCPhys -> GCPhys TLB (hash?)
1433	* 2. write protect all shadowed pages. I.e. implement caching.
1434	*/
1435	/** @todo duplicated in the 2nd half of pgmPoolTracDerefGCPhysHint */
1436
1437	/*
1438	* Find the guest address.
1439	*/
1440	for (PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRangesX);
1441	pRam;
1442	pRam = pRam->CTX_SUFF(pNext))
1443	{
1444	unsigned iPage = pRam->cb >> PAGE_SHIFT;
1445	while (iPage-- > 0)
1446	{
1447	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
1448	{
1449	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1450
1451	Assert(pShwPage->cPresent);
1452	Assert(pPool->cPresent);
1453	pShwPage->cPresent--;
1454	pPool->cPresent--;
1455
1456	pgmTrackDerefGCPhys(pPool, pShwPage, &pRam->aPages[iPage], iPte);
1457	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackDeref, a);
1458	return;
1459	}
1460	}
1461	}
1462
1463	for (;;)
1464	AssertReleaseMsgFailed(("HCPhys=%RHp wasn't found!\n", HCPhys));
1465	}
1466
1467
1468	/**
1469	* Update the tracking of shadowed pages.
1470	*
1471	* @param pVCpu Pointer to the VMCPU.
1472	* @param pShwPage The shadow page.
1473	* @param u16 The top 16-bit of the pPage->HCPhys.
1474	* @param pPage Pointer to the guest page. this will be modified.
1475	* @param iPTDst The index into the shadow table.
1476	*/
1477	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackAddref)(PVMCPU pVCpu, PPGMPOOLPAGE pShwPage, uint16_t u16, PPGMPAGE pPage, const unsigned iPTDst)
1478	{
1479	PVM pVM = pVCpu->CTX_SUFF(pVM);
1480
1481	/*
1482	* Just deal with the simple first time here.
1483	*/
1484	if (!u16)
1485	{
1486	STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackVirgin);
1487	u16 = PGMPOOL_TD_MAKE(1, pShwPage->idx);
1488	/* Save the page table index. */
1489	PGM_PAGE_SET_PTE_INDEX(pVM, pPage, iPTDst);
1490	}
1491	else
1492	u16 = pgmPoolTrackPhysExtAddref(pVM, pPage, u16, pShwPage->idx, iPTDst);
1493
1494	/* write back */
1495	Log2(("SyncPageWorkerTrackAddRef: u16=%#x->%#x iPTDst=%#x\n", u16, PGM_PAGE_GET_TRACKING(pPage), iPTDst));
1496	PGM_PAGE_SET_TRACKING(pVM, pPage, u16);
1497
1498	/* update statistics. */
1499	pVM->pgm.s.CTX_SUFF(pPool)->cPresent++;
1500	pShwPage->cPresent++;
1501	if (pShwPage->iFirstPresent > iPTDst)
1502	pShwPage->iFirstPresent = iPTDst;
1503	}
1504
1505
1506	/**
1507	* Modifies a shadow PTE to account for access handlers.
1508	*
1509	* @param pVM Pointer to the VM.
1510	* @param pPage The page in question.
1511	* @param fPteSrc The shadowed flags of the source PTE. Must include the
1512	* A (accessed) bit so it can be emulated correctly.
1513	* @param pPteDst The shadow PTE (output). This is temporary storage and
1514	* does not need to be set atomically.
1515	*/
1516	DECLINLINE(void) PGM_BTH_NAME(SyncHandlerPte)(PVM pVM, PCPGMPAGE pPage, uint64_t fPteSrc, PSHWPTE pPteDst)
1517	{
1518	NOREF(pVM);
1519	/** @todo r=bird: Are we actually handling dirty and access bits for pages with access handlers correctly? No.
1520	* Update: \#PF should deal with this before or after calling the handlers. It has all the info to do the job efficiently. */
1521	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1522	{
1523	LogFlow(("SyncHandlerPte: monitored page (%R[pgmpage]) -> mark read-only\n", pPage));
1524	#if PGM_SHW_TYPE == PGM_TYPE_EPT
1525	pPteDst->u = PGM_PAGE_GET_HCPHYS(pPage);
1526	pPteDst->n.u1Present = 1;
1527	pPteDst->n.u1Execute = 1;
1528	pPteDst->n.u1IgnorePAT = 1;
1529	pPteDst->n.u3EMT = VMX_EPT_MEMTYPE_WB;
1530	/* PteDst.n.u1Write = 0 && PteDst.n.u1Size = 0 */
1531	#else
1532	if (fPteSrc & X86_PTE_A)
1533	{
1534	SHW_PTE_SET(*pPteDst, fPteSrc \| PGM_PAGE_GET_HCPHYS(pPage));
1535	SHW_PTE_SET_RO(*pPteDst);
1536	}
1537	else
1538	SHW_PTE_SET(*pPteDst, 0);
1539	#endif
1540	}
1541	#ifdef PGM_WITH_MMIO_OPTIMIZATIONS
1542	# if PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
1543	else if ( PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
1544	&& ( BTH_IS_NP_ACTIVE(pVM)
1545	\|\| (fPteSrc & (X86_PTE_RW \| X86_PTE_US)) == X86_PTE_RW) /** @todo Remove X86_PTE_US here and pGstWalk->Core.fEffectiveUS before the sync page test. */
1546	# if PGM_SHW_TYPE == PGM_TYPE_AMD64
1547	&& pVM->pgm.s.fLessThan52PhysicalAddressBits
1548	# endif
1549	)
1550	{
1551	LogFlow(("SyncHandlerPte: MMIO page -> invalid \n"));
1552	# if PGM_SHW_TYPE == PGM_TYPE_EPT
1553	/* 25.2.3.1: Reserved physical address bit -> EPT Misconfiguration (exit 49) */
1554	pPteDst->u = pVM->pgm.s.HCPhysInvMmioPg;
1555	/* 25.2.3.1: bits 2:0 = 010b -> EPT Misconfiguration (exit 49) */
1556	pPteDst->n.u1Present = 0;
1557	pPteDst->n.u1Write = 1;
1558	pPteDst->n.u1Execute = 0;
1559	/* 25.2.3.1: leaf && 2:0 != 0 && u3Emt in {2, 3, 7} -> EPT Misconfiguration */
1560	pPteDst->n.u3EMT = 7;
1561	# else
1562	/* Set high page frame bits that MBZ (bankers on PAE, CPU dependent on AMD64). */
1563	SHW_PTE_SET(*pPteDst, pVM->pgm.s.HCPhysInvMmioPg \| X86_PTE_PAE_MBZ_MASK_NO_NX \| X86_PTE_P);
1564	# endif
1565	}
1566	# endif
1567	#endif /* PGM_WITH_MMIO_OPTIMIZATIONS */
1568	else
1569	{
1570	LogFlow(("SyncHandlerPte: monitored page (%R[pgmpage]) -> mark not present\n", pPage));
1571	SHW_PTE_SET(*pPteDst, 0);
1572	}
1573	/** @todo count these kinds of entries. */
1574	}
1575
1576
1577	/**
1578	* Creates a 4K shadow page for a guest page.
1579	*
1580	* For 4M pages the caller must convert the PDE4M to a PTE, this includes adjusting the
1581	* physical address. The PdeSrc argument only the flags are used. No page
1582	* structured will be mapped in this function.
1583	*
1584	* @param pVCpu Pointer to the VMCPU.
1585	* @param pPteDst Destination page table entry.
1586	* @param PdeSrc Source page directory entry (i.e. Guest OS page directory entry).
1587	* Can safely assume that only the flags are being used.
1588	* @param PteSrc Source page table entry (i.e. Guest OS page table entry).
1589	* @param pShwPage Pointer to the shadow page.
1590	* @param iPTDst The index into the shadow table.
1591	*
1592	* @remark Not used for 2/4MB pages!
1593	*/
1594	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1595	static void PGM_BTH_NAME(SyncPageWorker)(PVMCPU pVCpu, PSHWPTE pPteDst, GSTPDE PdeSrc, GSTPTE PteSrc,
1596	PPGMPOOLPAGE pShwPage, unsigned iPTDst)
1597	#else
1598	static void PGM_BTH_NAME(SyncPageWorker)(PVMCPU pVCpu, PSHWPTE pPteDst, RTGCPHYS GCPhysPage, PPGMPOOLPAGE pShwPage, unsigned iPTDst)
1599	#endif
1600	{
1601	PVM pVM = pVCpu->CTX_SUFF(pVM);
1602	RTGCPHYS GCPhysOldPage = NIL_RTGCPHYS;
1603
1604	#if defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT) \
1605	&& PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
1606	&& (PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_PAE /* pae/32bit combo */)
1607
1608	if (pShwPage->fDirty)
1609	{
1610	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1611	PGSTPT pGstPT;
1612
1613	/* Note that iPTDst can be used to index the guest PT even in the pae/32bit combo as we copy only half the table; see pgmPoolAddDirtyPage. */
1614	pGstPT = (PGSTPT)&pPool->aDirtyPages[pShwPage->idxDirtyEntry].aPage[0];
1615	GCPhysOldPage = GST_GET_PTE_GCPHYS(pGstPT->a[iPTDst]);
1616	pGstPT->a[iPTDst].u = PteSrc.u;
1617	}
1618	#else
1619	Assert(!pShwPage->fDirty);
1620	#endif
1621
1622	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1623	if ( PteSrc.n.u1Present
1624	&& GST_IS_PTE_VALID(pVCpu, PteSrc))
1625	#endif
1626	{
1627	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1628	RTGCPHYS GCPhysPage = GST_GET_PTE_GCPHYS(PteSrc);
1629	# endif
1630	PGM_A20_ASSERT_MASKED(pVCpu, GCPhysPage);
1631
1632	/*
1633	* Find the ram range.
1634	*/
1635	PPGMPAGE pPage;
1636	int rc = pgmPhysGetPageEx(pVM, GCPhysPage, &pPage);
1637	if (RT_SUCCESS(rc))
1638	{
1639	/* Ignore ballooned pages.
1640	Don't return errors or use a fatal assert here as part of a
1641	shadow sync range might included ballooned pages. */
1642	if (PGM_PAGE_IS_BALLOONED(pPage))
1643	{
1644	Assert(!SHW_PTE_IS_P(pPteDst)); /* @todo user tracking needs updating if this triggers. */
1645	return;
1646	}
1647
1648	#ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
1649	/* Make the page writable if necessary. */
1650	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
1651	&& ( PGM_PAGE_IS_ZERO(pPage)
1652	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1653	\|\| ( PteSrc.n.u1Write
1654	# else
1655	\|\| ( 1
1656	# endif
1657	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
1658	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
1659	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
1660	# endif
1661	# ifdef VBOX_WITH_PAGE_SHARING
1662	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
1663	# endif
1664	)
1665	)
1666	)
1667	{
1668	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhysPage);
1669	AssertRC(rc);
1670	}
1671	#endif
1672
1673	/*
1674	* Make page table entry.
1675	*/
1676	SHWPTE PteDst;
1677	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1678	uint64_t fGstShwPteFlags = GST_GET_PTE_SHW_FLAGS(pVCpu, PteSrc);
1679	# else
1680	uint64_t fGstShwPteFlags = X86_PTE_P \| X86_PTE_RW \| X86_PTE_US \| X86_PTE_A \| X86_PTE_D;
1681	# endif
1682	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1683	PGM_BTH_NAME(SyncHandlerPte)(pVM, pPage, fGstShwPteFlags, &PteDst);
1684	else
1685	{
1686	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1687	/*
1688	* If the page or page directory entry is not marked accessed,
1689	* we mark the page not present.
1690	*/
1691	if (!PteSrc.n.u1Accessed \|\| !PdeSrc.n.u1Accessed)
1692	{
1693	LogFlow(("SyncPageWorker: page and or page directory not accessed -> mark not present\n"));
1694	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,AccessedPage));
1695	SHW_PTE_SET(PteDst, 0);
1696	}
1697	/*
1698	* If the page is not flagged as dirty and is writable, then make it read-only, so we can set the dirty bit
1699	* when the page is modified.
1700	*/
1701	else if (!PteSrc.n.u1Dirty && (PdeSrc.n.u1Write & PteSrc.n.u1Write))
1702	{
1703	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPage));
1704	SHW_PTE_SET(PteDst,
1705	fGstShwPteFlags
1706	\| PGM_PAGE_GET_HCPHYS(pPage)
1707	\| PGM_PTFLAGS_TRACK_DIRTY);
1708	SHW_PTE_SET_RO(PteDst);
1709	}
1710	else
1711	#endif
1712	{
1713	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageSkipped));
1714	#if PGM_SHW_TYPE == PGM_TYPE_EPT
1715	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage);
1716	PteDst.n.u1Present = 1;
1717	PteDst.n.u1Write = 1;
1718	PteDst.n.u1Execute = 1;
1719	PteDst.n.u1IgnorePAT = 1;
1720	PteDst.n.u3EMT = VMX_EPT_MEMTYPE_WB;
1721	/* PteDst.n.u1Size = 0 */
1722	#else
1723	SHW_PTE_SET(PteDst, fGstShwPteFlags \| PGM_PAGE_GET_HCPHYS(pPage));
1724	#endif
1725	}
1726
1727	/*
1728	* Make sure only allocated pages are mapped writable.
1729	*/
1730	if ( SHW_PTE_IS_P_RW(PteDst)
1731	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
1732	{
1733	/* Still applies to shared pages. */
1734	Assert(!PGM_PAGE_IS_ZERO(pPage));
1735	SHW_PTE_SET_RO(PteDst); /** @todo this isn't quite working yet. Why, isn't it? */
1736	Log3(("SyncPageWorker: write-protecting %RGp pPage=%R[pgmpage]at iPTDst=%d\n", GCPhysPage, pPage, iPTDst));
1737	}
1738	}
1739
1740	/*
1741	* Keep user track up to date.
1742	*/
1743	if (SHW_PTE_IS_P(PteDst))
1744	{
1745	if (!SHW_PTE_IS_P(*pPteDst))
1746	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1747	else if (SHW_PTE_GET_HCPHYS(*pPteDst) != SHW_PTE_GET_HCPHYS(PteDst))
1748	{
1749	Log2(("SyncPageWorker: deref! pPteDst=%RX64 PteDst=%RX64\n", SHW_PTE_LOG64(pPteDst), SHW_PTE_LOG64(PteDst)));
1750	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPteDst), iPTDst, GCPhysOldPage);
1751	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1752	}
1753	}
1754	else if (SHW_PTE_IS_P(*pPteDst))
1755	{
1756	Log2(("SyncPageWorker: deref! pPteDst=%RX64\n", SHW_PTE_LOG64(pPteDst)));
1757	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPteDst), iPTDst, GCPhysOldPage);
1758	}
1759
1760	/*
1761	* Update statistics and commit the entry.
1762	*/
1763	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1764	if (!PteSrc.n.u1Global)
1765	pShwPage->fSeenNonGlobal = true;
1766	#endif
1767	SHW_PTE_ATOMIC_SET2(*pPteDst, PteDst);
1768	return;
1769	}
1770
1771	/** @todo count these three different kinds. */
1772	Log2(("SyncPageWorker: invalid address in Pte\n"));
1773	}
1774	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1775	else if (!PteSrc.n.u1Present)
1776	Log2(("SyncPageWorker: page not present in Pte\n"));
1777	else
1778	Log2(("SyncPageWorker: invalid Pte\n"));
1779	#endif
1780
1781	/*
1782	* The page is not present or the PTE is bad. Replace the shadow PTE by
1783	* an empty entry, making sure to keep the user tracking up to date.
1784	*/
1785	if (SHW_PTE_IS_P(*pPteDst))
1786	{
1787	Log2(("SyncPageWorker: deref! pPteDst=%RX64\n", SHW_PTE_LOG64(pPteDst)));
1788	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPteDst), iPTDst, GCPhysOldPage);
1789	}
1790	SHW_PTE_ATOMIC_SET(*pPteDst, 0);
1791	}
1792
1793
1794	/**
1795	* Syncs a guest OS page.
1796	*
1797	* There are no conflicts at this point, neither is there any need for
1798	* page table allocations.
1799	*
1800	* When called in PAE or AMD64 guest mode, the guest PDPE shall be valid.
1801	* When called in AMD64 guest mode, the guest PML4E shall be valid.
1802	*
1803	* @returns VBox status code.
1804	* @returns VINF_PGM_SYNCPAGE_MODIFIED_PDE if it modifies the PDE in any way.
1805	* @param pVCpu Pointer to the VMCPU.
1806	* @param PdeSrc Page directory entry of the guest.
1807	* @param GCPtrPage Guest context page address.
1808	* @param cPages Number of pages to sync (PGM_SYNC_N_PAGES) (default=1).
1809	* @param uErr Fault error (X86_TRAP_PF_*).
1810	*/
1811	static int PGM_BTH_NAME(SyncPage)(PVMCPU pVCpu, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr)
1812	{
1813	PVM pVM = pVCpu->CTX_SUFF(pVM);
1814	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool); NOREF(pPool);
1815	LogFlow(("SyncPage: GCPtrPage=%RGv cPages=%u uErr=%#x\n", GCPtrPage, cPages, uErr));
1816
1817	PGM_LOCK_ASSERT_OWNER(pVM);
1818
1819	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
1820	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
1821	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
1822	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
1823	&& PGM_SHW_TYPE != PGM_TYPE_EPT
1824
1825	/*
1826	* Assert preconditions.
1827	*/
1828	Assert(PdeSrc.n.u1Present);
1829	Assert(cPages);
1830	# if 0 /* rarely useful; leave for debugging. */
1831	STAM_COUNTER_INC(&pVCpu->pgm.s.StatSyncPagePD[(GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK]);
1832	# endif
1833
1834	/*
1835	* Get the shadow PDE, find the shadow page table in the pool.
1836	*/
1837	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1838	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1839	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
1840
1841	/* Fetch the pgm pool shadow descriptor. */
1842	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
1843	Assert(pShwPde);
1844
1845	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1846	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1847	PPGMPOOLPAGE pShwPde = NULL;
1848	PX86PDPAE pPDDst;
1849
1850	/* Fetch the pgm pool shadow descriptor. */
1851	int rc2 = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
1852	AssertRCSuccessReturn(rc2, rc2);
1853	Assert(pShwPde);
1854
1855	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
1856	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1857
1858	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1859	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1860	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1861	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
1862	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
1863
1864	int rc2 = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
1865	AssertRCSuccessReturn(rc2, rc2);
1866	Assert(pPDDst && pPdptDst);
1867	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1868	# endif
1869	SHWPDE PdeDst = *pPdeDst;
1870
1871	/*
1872	* - In the guest SMP case we could have blocked while another VCPU reused
1873	* this page table.
1874	* - With W7-64 we may also take this path when the A bit is cleared on
1875	* higher level tables (PDPE/PML4E). The guest does not invalidate the
1876	* relevant TLB entries. If we're write monitoring any page mapped by
1877	* the modified entry, we may end up here with a "stale" TLB entry.
1878	*/
1879	if (!PdeDst.n.u1Present)
1880	{
1881	Log(("CPU%u: SyncPage: Pde at %RGv changed behind our back? (pPdeDst=%p/%RX64) uErr=%#x\n", pVCpu->idCpu, GCPtrPage, pPdeDst, (uint64_t)PdeDst.u, (uint32_t)uErr));
1882	AssertMsg(pVM->cCpus > 1 \|\| (uErr & (X86_TRAP_PF_P \| X86_TRAP_PF_RW)) == (X86_TRAP_PF_P \| X86_TRAP_PF_RW),
1883	("Unexpected missing PDE p=%p/%RX64 uErr=%#x\n", pPdeDst, (uint64_t)PdeDst.u, (uint32_t)uErr));
1884	if (uErr & X86_TRAP_PF_P)
1885	PGM_INVL_PG(pVCpu, GCPtrPage);
1886	return VINF_SUCCESS; /* force the instruction to be executed again. */
1887	}
1888
1889	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1890	Assert(pShwPage);
1891
1892	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1893	/* Fetch the pgm pool shadow descriptor. */
1894	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
1895	Assert(pShwPde);
1896	# endif
1897
1898	/*
1899	* Check that the page is present and that the shadow PDE isn't out of sync.
1900	*/
1901	const bool fBigPage = PdeSrc.b.u1Size && GST_IS_PSE_ACTIVE(pVCpu);
1902	const bool fPdeValid = !fBigPage ? GST_IS_PDE_VALID(pVCpu, PdeSrc) : GST_IS_BIG_PDE_VALID(pVCpu, PdeSrc);
1903	RTGCPHYS GCPhys;
1904	if (!fBigPage)
1905	{
1906	GCPhys = GST_GET_PDE_GCPHYS(PdeSrc);
1907	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1908	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1909	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| ((iPDDst & 1) * (PAGE_SIZE / 2)));
1910	# endif
1911	}
1912	else
1913	{
1914	GCPhys = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
1915	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1916	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1917	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| (GCPtrPage & (1 << X86_PD_PAE_SHIFT)));
1918	# endif
1919	}
1920	/** @todo This doesn't check the G bit of 2/4MB pages. FIXME */
1921	if ( fPdeValid
1922	&& pShwPage->GCPhys == GCPhys
1923	&& PdeSrc.n.u1Present
1924	&& PdeSrc.n.u1User == PdeDst.n.u1User
1925	&& (PdeSrc.n.u1Write == PdeDst.n.u1Write \|\| !PdeDst.n.u1Write)
1926	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
1927	&& (PdeSrc.n.u1NoExecute == PdeDst.n.u1NoExecute \|\| !GST_IS_NX_ACTIVE(pVCpu))
1928	# endif
1929	)
1930	{
1931	/*
1932	* Check that the PDE is marked accessed already.
1933	* Since we set the accessed bit before getting here on a #PF, this
1934	* check is only meant for dealing with non-#PF'ing paths.
1935	*/
1936	if (PdeSrc.n.u1Accessed)
1937	{
1938	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1939	if (!fBigPage)
1940	{
1941	/*
1942	* 4KB Page - Map the guest page table.
1943	*/
1944	PGSTPT pPTSrc;
1945	int rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GST_GET_PDE_GCPHYS(PdeSrc), &pPTSrc);
1946	if (RT_SUCCESS(rc))
1947	{
1948	# ifdef PGM_SYNC_N_PAGES
1949	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
1950	if ( cPages > 1
1951	&& !(uErr & X86_TRAP_PF_P)
1952	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1953	{
1954	/*
1955	* This code path is currently only taken when the caller is PGMTrap0eHandler
1956	* for non-present pages!
1957	*
1958	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
1959	* deal with locality.
1960	*/
1961	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1962	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1963	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1964	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
1965	# else
1966	const unsigned offPTSrc = 0;
1967	# endif
1968	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
1969	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
1970	iPTDst = 0;
1971	else
1972	iPTDst -= PGM_SYNC_NR_PAGES / 2;
1973
1974	for (; iPTDst < iPTDstEnd; iPTDst++)
1975	{
1976	const PGSTPTE pPteSrc = &pPTSrc->a[offPTSrc + iPTDst];
1977
1978	if ( pPteSrc->n.u1Present
1979	&& !SHW_PTE_IS_P(pPTDst->a[iPTDst]))
1980	{
1981	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(GST_PT_MASK << GST_PT_SHIFT)) \| ((offPTSrc + iPTDst) << PAGE_SHIFT);
1982	NOREF(GCPtrCurPage);
1983	# ifdef VBOX_WITH_RAW_MODE_NOT_R0
1984	/*
1985	* Assuming kernel code will be marked as supervisor - and not as user level
1986	* and executed using a conforming code selector - And marked as readonly.
1987	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
1988	*/
1989	PPGMPAGE pPage;
1990	if ( ((PdeSrc.u & pPteSrc->u) & (X86_PTE_RW \| X86_PTE_US))
1991	\|\| iPTDst == ((GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK) /* always sync GCPtrPage */
1992	\|\| !CSAMDoesPageNeedScanning(pVM, GCPtrCurPage)
1993	\|\| ( (pPage = pgmPhysGetPage(pVM, pPteSrc->u & GST_PTE_PG_MASK))
1994	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1995	)
1996	# endif /* else: CSAM not active */
1997	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, *pPteSrc, pShwPage, iPTDst);
1998	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
1999	GCPtrCurPage, pPteSrc->n.u1Present,
2000	pPteSrc->n.u1Write & PdeSrc.n.u1Write,
2001	pPteSrc->n.u1User & PdeSrc.n.u1User,
2002	(uint64_t)pPteSrc->u,
2003	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2004	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2005	}
2006	}
2007	}
2008	else
2009	# endif /* PGM_SYNC_N_PAGES */
2010	{
2011	const unsigned iPTSrc = (GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK;
2012	GSTPTE PteSrc = pPTSrc->a[iPTSrc];
2013	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2014	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2015	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx %s\n",
2016	GCPtrPage, PteSrc.n.u1Present,
2017	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2018	PteSrc.n.u1User & PdeSrc.n.u1User,
2019	(uint64_t)PteSrc.u,
2020	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2021	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2022	}
2023	}
2024	else /* MMIO or invalid page: emulated in #PF handler. */
2025	{
2026	LogFlow(("PGM_GCPHYS_2_PTR %RGp failed with %Rrc\n", GCPhys, rc));
2027	Assert(!SHW_PTE_IS_P(pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK]));
2028	}
2029	}
2030	else
2031	{
2032	/*
2033	* 4/2MB page - lazy syncing shadow 4K pages.
2034	* (There are many causes of getting here, it's no longer only CSAM.)
2035	*/
2036	/* Calculate the GC physical address of this 4KB shadow page. */
2037	GCPhys = PGM_A20_APPLY(pVCpu, GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc) \| (GCPtrPage & GST_BIG_PAGE_OFFSET_MASK));
2038	/* Find ram range. */
2039	PPGMPAGE pPage;
2040	int rc = pgmPhysGetPageEx(pVM, GCPhys, &pPage);
2041	if (RT_SUCCESS(rc))
2042	{
2043	AssertFatalMsg(!PGM_PAGE_IS_BALLOONED(pPage), ("Unexpected ballooned page at %RGp\n", GCPhys));
2044
2045	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
2046	/* Try to make the page writable if necessary. */
2047	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
2048	&& ( PGM_PAGE_IS_ZERO(pPage)
2049	\|\| ( PdeSrc.n.u1Write
2050	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
2051	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
2052	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
2053	# endif
2054	# ifdef VBOX_WITH_PAGE_SHARING
2055	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
2056	# endif
2057	)
2058	)
2059	)
2060	{
2061	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
2062	AssertRC(rc);
2063	}
2064	# endif
2065
2066	/*
2067	* Make shadow PTE entry.
2068	*/
2069	SHWPTE PteDst;
2070	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2071	PGM_BTH_NAME(SyncHandlerPte)(pVM, pPage, GST_GET_BIG_PDE_SHW_FLAGS_4_PTE(pVCpu, PdeSrc), &PteDst);
2072	else
2073	SHW_PTE_SET(PteDst, GST_GET_BIG_PDE_SHW_FLAGS_4_PTE(pVCpu, PdeSrc) \| PGM_PAGE_GET_HCPHYS(pPage));
2074
2075	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2076	if ( SHW_PTE_IS_P(PteDst)
2077	&& !SHW_PTE_IS_P(pPTDst->a[iPTDst]))
2078	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
2079
2080	/* Make sure only allocated pages are mapped writable. */
2081	if ( SHW_PTE_IS_P_RW(PteDst)
2082	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
2083	{
2084	/* Still applies to shared pages. */
2085	Assert(!PGM_PAGE_IS_ZERO(pPage));
2086	SHW_PTE_SET_RO(PteDst); /** @todo this isn't quite working yet... */
2087	Log3(("SyncPage: write-protecting %RGp pPage=%R[pgmpage] at %RGv\n", GCPhys, pPage, GCPtrPage));
2088	}
2089
2090	SHW_PTE_ATOMIC_SET2(pPTDst->a[iPTDst], PteDst);
2091
2092	/*
2093	* If the page is not flagged as dirty and is writable, then make it read-only
2094	* at PD level, so we can set the dirty bit when the page is modified.
2095	*
2096	* ASSUMES that page access handlers are implemented on page table entry level.
2097	* Thus we will first catch the dirty access and set PDE.D and restart. If
2098	* there is an access handler, we'll trap again and let it work on the problem.
2099	*/
2100	/** @todo r=bird: figure out why we need this here, SyncPT should've taken care of this already.
2101	* As for invlpg, it simply frees the whole shadow PT.
2102	* ...It's possibly because the guest clears it and the guest doesn't really tell us... */
2103	if ( !PdeSrc.b.u1Dirty
2104	&& PdeSrc.b.u1Write)
2105	{
2106	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageBig));
2107	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2108	PdeDst.n.u1Write = 0;
2109	}
2110	else
2111	{
2112	PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
2113	PdeDst.n.u1Write = PdeSrc.n.u1Write;
2114	}
2115	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2116	Log2(("SyncPage: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} GCPhys=%RGp%s\n",
2117	GCPtrPage, PdeSrc.n.u1Present, PdeSrc.n.u1Write, PdeSrc.n.u1User, (uint64_t)PdeSrc.u, GCPhys,
2118	PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2119	}
2120	else
2121	{
2122	LogFlow(("PGM_GCPHYS_2_PTR %RGp (big) failed with %Rrc\n", GCPhys, rc));
2123	/** @todo must wipe the shadow page table entry in this
2124	* case. */
2125	}
2126	}
2127	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2128	return VINF_SUCCESS;
2129	}
2130
2131	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPagePDNAs));
2132	}
2133	else if (fPdeValid)
2134	{
2135	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPagePDOutOfSync));
2136	Log2(("SyncPage: Out-Of-Sync PDE at %RGp PdeSrc=%RX64 PdeDst=%RX64 (GCPhys %RGp vs %RGp)\n",
2137	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, GCPhys));
2138	}
2139	else
2140	{
2141	/// @todo STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPagePDOutOfSyncAndInvalid));
2142	Log2(("SyncPage: Bad PDE at %RGp PdeSrc=%RX64 PdeDst=%RX64 (GCPhys %RGp vs %RGp)\n",
2143	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, GCPhys));
2144	}
2145
2146	/*
2147	* Mark the PDE not present. Restart the instruction and let #PF call SyncPT.
2148	* Yea, I'm lazy.
2149	*/
2150	pgmPoolFreeByPage(pPool, pShwPage, pShwPde->idx, iPDDst);
2151	ASMAtomicWriteSize(pPdeDst, 0);
2152
2153	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2154	PGM_INVL_VCPU_TLBS(pVCpu);
2155	return VINF_PGM_SYNCPAGE_MODIFIED_PDE;
2156
2157
2158	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2159	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2160	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2161	&& !defined(IN_RC)
2162	NOREF(PdeSrc);
2163
2164	# ifdef PGM_SYNC_N_PAGES
2165	/*
2166	* Get the shadow PDE, find the shadow page table in the pool.
2167	*/
2168	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2169	X86PDE PdeDst = pgmShwGet32BitPDE(pVCpu, GCPtrPage);
2170
2171	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2172	X86PDEPAE PdeDst = pgmShwGetPaePDE(pVCpu, GCPtrPage);
2173
2174	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2175	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2176	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64; NOREF(iPdpt);
2177	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
2178	X86PDEPAE PdeDst;
2179	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
2180
2181	int rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2182	AssertRCSuccessReturn(rc, rc);
2183	Assert(pPDDst && pPdptDst);
2184	PdeDst = pPDDst->a[iPDDst];
2185	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
2186	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2187	PEPTPD pPDDst;
2188	EPTPDE PdeDst;
2189
2190	int rc = pgmShwGetEPTPDPtr(pVCpu, GCPtrPage, NULL, &pPDDst);
2191	if (rc != VINF_SUCCESS)
2192	{
2193	AssertRC(rc);
2194	return rc;
2195	}
2196	Assert(pPDDst);
2197	PdeDst = pPDDst->a[iPDDst];
2198	# endif
2199	/* In the guest SMP case we could have blocked while another VCPU reused this page table. */
2200	if (!PdeDst.n.u1Present)
2201	{
2202	AssertMsg(pVM->cCpus > 1, ("Unexpected missing PDE %RX64\n", (uint64_t)PdeDst.u));
2203	Log(("CPU%d: SyncPage: Pde at %RGv changed behind our back!\n", pVCpu->idCpu, GCPtrPage));
2204	return VINF_SUCCESS; /* force the instruction to be executed again. */
2205	}
2206
2207	/* Can happen in the guest SMP case; other VCPU activated this PDE while we were blocking to handle the page fault. */
2208	if (PdeDst.n.u1Size)
2209	{
2210	Assert(pVM->pgm.s.fNestedPaging);
2211	Log(("CPU%d: SyncPage: Pde (big:%RX64) at %RGv changed behind our back!\n", pVCpu->idCpu, PdeDst.u, GCPtrPage));
2212	return VINF_SUCCESS;
2213	}
2214
2215	/* Mask away the page offset. */
2216	GCPtrPage &= ~((RTGCPTR)0xfff);
2217
2218	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
2219	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2220
2221	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
2222	if ( cPages > 1
2223	&& !(uErr & X86_TRAP_PF_P)
2224	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
2225	{
2226	/*
2227	* This code path is currently only taken when the caller is PGMTrap0eHandler
2228	* for non-present pages!
2229	*
2230	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
2231	* deal with locality.
2232	*/
2233	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2234	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2235	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
2236	iPTDst = 0;
2237	else
2238	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2239	for (; iPTDst < iPTDstEnd; iPTDst++)
2240	{
2241	if (!SHW_PTE_IS_P(pPTDst->a[iPTDst]))
2242	{
2243	RTGCPTR GCPtrCurPage = PGM_A20_APPLY(pVCpu, (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT))
2244	\| (iPTDst << PAGE_SHIFT));
2245
2246	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], GCPtrCurPage, pShwPage, iPTDst);
2247	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=1 RW=1 U=1} PteDst=%08llx%s\n",
2248	GCPtrCurPage,
2249	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2250	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2251
2252	if (RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)))
2253	break;
2254	}
2255	else
2256	Log4(("%RGv iPTDst=%x pPTDst->a[iPTDst] %RX64\n", (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT), iPTDst, SHW_PTE_LOG64(pPTDst->a[iPTDst]) ));
2257	}
2258	}
2259	else
2260	# endif /* PGM_SYNC_N_PAGES */
2261	{
2262	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2263	RTGCPTR GCPtrCurPage = PGM_A20_APPLY(pVCpu, (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT))
2264	\| (iPTDst << PAGE_SHIFT));
2265
2266	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], GCPtrCurPage, pShwPage, iPTDst);
2267
2268	Log2(("SyncPage: 4K %RGv PteSrc:{P=1 RW=1 U=1}PteDst=%08llx%s\n",
2269	GCPtrPage,
2270	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2271	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2272	}
2273	return VINF_SUCCESS;
2274
2275	#else
2276	NOREF(PdeSrc);
2277	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
2278	return VERR_PGM_NOT_USED_IN_MODE;
2279	#endif
2280	}
2281
2282
2283	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
2284
2285	/**
2286	* CheckPageFault helper for returning a page fault indicating a non-present
2287	* (NP) entry in the page translation structures.
2288	*
2289	* @returns VINF_EM_RAW_GUEST_TRAP.
2290	* @param pVCpu Pointer to the VMCPU.
2291	* @param uErr The error code of the shadow fault. Corrections to
2292	* TRPM's copy will be made if necessary.
2293	* @param GCPtrPage For logging.
2294	* @param uPageFaultLevel For logging.
2295	*/
2296	DECLINLINE(int) PGM_BTH_NAME(CheckPageFaultReturnNP)(PVMCPU pVCpu, uint32_t uErr, RTGCPTR GCPtrPage, unsigned uPageFaultLevel)
2297	{
2298	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyTrackRealPF));
2299	AssertMsg(!(uErr & X86_TRAP_PF_P), ("%#x\n", uErr));
2300	AssertMsg(!(uErr & X86_TRAP_PF_RSVD), ("%#x\n", uErr));
2301	if (uErr & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P))
2302	TRPMSetErrorCode(pVCpu, uErr & ~(X86_TRAP_PF_RSVD \| X86_TRAP_PF_P));
2303
2304	Log(("CheckPageFault: real page fault (notp) at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2305	return VINF_EM_RAW_GUEST_TRAP;
2306	}
2307
2308
2309	/**
2310	* CheckPageFault helper for returning a page fault indicating a reserved bit
2311	* (RSVD) error in the page translation structures.
2312	*
2313	* @returns VINF_EM_RAW_GUEST_TRAP.
2314	* @param pVCpu Pointer to the VMCPU.
2315	* @param uErr The error code of the shadow fault. Corrections to
2316	* TRPM's copy will be made if necessary.
2317	* @param GCPtrPage For logging.
2318	* @param uPageFaultLevel For logging.
2319	*/
2320	DECLINLINE(int) PGM_BTH_NAME(CheckPageFaultReturnRSVD)(PVMCPU pVCpu, uint32_t uErr, RTGCPTR GCPtrPage, unsigned uPageFaultLevel)
2321	{
2322	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyTrackRealPF));
2323	if ((uErr & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) != (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P))
2324	TRPMSetErrorCode(pVCpu, uErr \| X86_TRAP_PF_RSVD \| X86_TRAP_PF_P);
2325
2326	Log(("CheckPageFault: real page fault (rsvd) at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2327	return VINF_EM_RAW_GUEST_TRAP;
2328	}
2329
2330
2331	/**
2332	* CheckPageFault helper for returning a page protection fault (P).
2333	*
2334	* @returns VINF_EM_RAW_GUEST_TRAP.
2335	* @param pVCpu Pointer to the VMCPU.
2336	* @param uErr The error code of the shadow fault. Corrections to
2337	* TRPM's copy will be made if necessary.
2338	* @param GCPtrPage For logging.
2339	* @param uPageFaultLevel For logging.
2340	*/
2341	DECLINLINE(int) PGM_BTH_NAME(CheckPageFaultReturnProt)(PVMCPU pVCpu, uint32_t uErr, RTGCPTR GCPtrPage, unsigned uPageFaultLevel)
2342	{
2343	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyTrackRealPF));
2344	AssertMsg(uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US \| X86_TRAP_PF_ID), ("%#x\n", uErr));
2345	if ((uErr & (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD)) != X86_TRAP_PF_P)
2346	TRPMSetErrorCode(pVCpu, (uErr & ~X86_TRAP_PF_RSVD) \| X86_TRAP_PF_P);
2347
2348	Log(("CheckPageFault: real page fault (prot) at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2349	return VINF_EM_RAW_GUEST_TRAP;
2350	}
2351
2352
2353	/**
2354	* Handle dirty bit tracking faults.
2355	*
2356	* @returns VBox status code.
2357	* @param pVCpu Pointer to the VMCPU.
2358	* @param uErr Page fault error code.
2359	* @param pPdeSrc Guest page directory entry.
2360	* @param pPdeDst Shadow page directory entry.
2361	* @param GCPtrPage Guest context page address.
2362	*/
2363	static int PGM_BTH_NAME(CheckDirtyPageFault)(PVMCPU pVCpu, uint32_t uErr, PSHWPDE pPdeDst, GSTPDE const *pPdeSrc,
2364	RTGCPTR GCPtrPage)
2365	{
2366	PVM pVM = pVCpu->CTX_SUFF(pVM);
2367	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2368	NOREF(uErr);
2369
2370	PGM_LOCK_ASSERT_OWNER(pVM);
2371
2372	/*
2373	* Handle big page.
2374	*/
2375	if (pPdeSrc->b.u1Size && GST_IS_PSE_ACTIVE(pVCpu))
2376	{
2377	if ( pPdeDst->n.u1Present
2378	&& (pPdeDst->u & PGM_PDFLAGS_TRACK_DIRTY))
2379	{
2380	SHWPDE PdeDst = *pPdeDst;
2381
2382	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageTrap));
2383	Assert(pPdeSrc->b.u1Write);
2384
2385	/* Note: No need to invalidate this entry on other VCPUs as a stale TLB entry will not harm; write access will simply
2386	* fault again and take this path to only invalidate the entry (see below).
2387	*/
2388	PdeDst.n.u1Write = 1;
2389	PdeDst.n.u1Accessed = 1;
2390	PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
2391	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2392	PGM_INVL_BIG_PG(pVCpu, GCPtrPage);
2393	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2394	}
2395
2396	# ifdef IN_RING0
2397	/* Check for stale TLB entry; only applies to the SMP guest case. */
2398	if ( pVM->cCpus > 1
2399	&& pPdeDst->n.u1Write
2400	&& pPdeDst->n.u1Accessed)
2401	{
2402	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPdeDst->u & SHW_PDE_PG_MASK);
2403	if (pShwPage)
2404	{
2405	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2406	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2407	if (SHW_PTE_IS_P_RW(*pPteDst))
2408	{
2409	/* Stale TLB entry. */
2410	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageStale));
2411	PGM_INVL_PG(pVCpu, GCPtrPage);
2412	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2413	}
2414	}
2415	}
2416	# endif /* IN_RING0 */
2417	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2418	}
2419
2420	/*
2421	* Map the guest page table.
2422	*/
2423	PGSTPT pPTSrc;
2424	int rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GST_GET_PDE_GCPHYS(*pPdeSrc), &pPTSrc);
2425	if (RT_FAILURE(rc))
2426	{
2427	AssertRC(rc);
2428	return rc;
2429	}
2430
2431	if (pPdeDst->n.u1Present)
2432	{
2433	GSTPTE const *pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
2434	const GSTPTE PteSrc = *pPteSrc;
2435
2436	#ifdef VBOX_WITH_RAW_MODE_NOT_R0
2437	/* Bail out here as pgmPoolGetPage will return NULL and we'll crash below.
2438	* Our individual shadow handlers will provide more information and force a fatal exit.
2439	*/
2440	if (MMHyperIsInsideArea(pVM, (RTGCPTR)GCPtrPage))
2441	{
2442	LogRel(("CheckPageFault: write to hypervisor region %RGv\n", GCPtrPage));
2443	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2444	}
2445	#endif
2446	/*
2447	* Map shadow page table.
2448	*/
2449	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPdeDst->u & SHW_PDE_PG_MASK);
2450	if (pShwPage)
2451	{
2452	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2453	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2454	if (SHW_PTE_IS_P(pPteDst)) /* @todo Optimize accessed bit emulation? */
2455	{
2456	if (SHW_PTE_IS_TRACK_DIRTY(*pPteDst))
2457	{
2458	PPGMPAGE pPage = pgmPhysGetPage(pVM, GST_GET_PTE_GCPHYS(PteSrc));
2459	SHWPTE PteDst = *pPteDst;
2460
2461	LogFlow(("DIRTY page trap addr=%RGv\n", GCPtrPage));
2462	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageTrap));
2463
2464	Assert(PteSrc.n.u1Write);
2465
2466	/* Note: No need to invalidate this entry on other VCPUs as a stale TLB
2467	* entry will not harm; write access will simply fault again and
2468	* take this path to only invalidate the entry.
2469	*/
2470	if (RT_LIKELY(pPage))
2471	{
2472	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2473	{
2474	//AssertMsgFailed(("%R[pgmpage] - we don't set PGM_PTFLAGS_TRACK_DIRTY for these pages\n", pPage));
2475	Assert(!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage));
2476	/* Assuming write handlers here as the PTE is present (otherwise we wouldn't be here). */
2477	SHW_PTE_SET_RO(PteDst);
2478	}
2479	else
2480	{
2481	if ( PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED
2482	&& PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
2483	{
2484	rc = pgmPhysPageMakeWritable(pVM, pPage, GST_GET_PTE_GCPHYS(PteSrc));
2485	AssertRC(rc);
2486	}
2487	if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED)
2488	SHW_PTE_SET_RW(PteDst);
2489	else
2490	{
2491	/* Still applies to shared pages. */
2492	Assert(!PGM_PAGE_IS_ZERO(pPage));
2493	SHW_PTE_SET_RO(PteDst);
2494	}
2495	}
2496	}
2497	else
2498	SHW_PTE_SET_RW(PteDst); /** @todo r=bird: This doesn't make sense to me. */
2499
2500	SHW_PTE_SET(PteDst, (SHW_PTE_GET_U(PteDst) \| X86_PTE_D \| X86_PTE_A) & ~(uint64_t)PGM_PTFLAGS_TRACK_DIRTY);
2501	SHW_PTE_ATOMIC_SET2(*pPteDst, PteDst);
2502	PGM_INVL_PG(pVCpu, GCPtrPage);
2503	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2504	}
2505
2506	# ifdef IN_RING0
2507	/* Check for stale TLB entry; only applies to the SMP guest case. */
2508	if ( pVM->cCpus > 1
2509	&& SHW_PTE_IS_RW(*pPteDst)
2510	&& SHW_PTE_IS_A(*pPteDst))
2511	{
2512	/* Stale TLB entry. */
2513	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageStale));
2514	PGM_INVL_PG(pVCpu, GCPtrPage);
2515	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2516	}
2517	# endif
2518	}
2519	}
2520	else
2521	AssertMsgFailed(("pgmPoolGetPageByHCPhys %RGp failed!\n", pPdeDst->u & SHW_PDE_PG_MASK));
2522	}
2523
2524	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2525	}
2526
2527	#endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
2528
2529
2530	/**
2531	* Sync a shadow page table.
2532	*
2533	* The shadow page table is not present in the shadow PDE.
2534	*
2535	* Handles mapping conflicts.
2536	*
2537	* This is called by VerifyAccessSyncPage, PrefetchPage, InvalidatePage (on
2538	* conflict), and Trap0eHandler.
2539	*
2540	* A precondition for this method is that the shadow PDE is not present. The
2541	* caller must take the PGM lock before checking this and continue to hold it
2542	* when calling this method.
2543	*
2544	* @returns VBox status code.
2545	* @param pVCpu Pointer to the VMCPU.
2546	* @param iPD Page directory index.
2547	* @param pPDSrc Source page directory (i.e. Guest OS page directory).
2548	* Assume this is a temporary mapping.
2549	* @param GCPtrPage GC Pointer of the page that caused the fault
2550	*/
2551	static int PGM_BTH_NAME(SyncPT)(PVMCPU pVCpu, unsigned iPDSrc, PGSTPD pPDSrc, RTGCPTR GCPtrPage)
2552	{
2553	PVM pVM = pVCpu->CTX_SUFF(pVM);
2554	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool); NOREF(pPool);
2555
2556	#if 0 /* rarely useful; leave for debugging. */
2557	STAM_COUNTER_INC(&pVCpu->pgm.s.StatSyncPtPD[iPDSrc]);
2558	#endif
2559	LogFlow(("SyncPT: GCPtrPage=%RGv\n", GCPtrPage));
2560
2561	PGM_LOCK_ASSERT_OWNER(pVM);
2562
2563	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
2564	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
2565	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
2566	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2567	&& PGM_SHW_TYPE != PGM_TYPE_EPT
2568
2569	int rc = VINF_SUCCESS;
2570
2571	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
2572
2573	/*
2574	* Some input validation first.
2575	*/
2576	AssertMsg(iPDSrc == ((GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK), ("iPDSrc=%x GCPtrPage=%RGv\n", iPDSrc, GCPtrPage));
2577
2578	/*
2579	* Get the relevant shadow PDE entry.
2580	*/
2581	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2582	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
2583	PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
2584
2585	/* Fetch the pgm pool shadow descriptor. */
2586	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
2587	Assert(pShwPde);
2588
2589	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2590	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2591	PPGMPOOLPAGE pShwPde = NULL;
2592	PX86PDPAE pPDDst;
2593	PSHWPDE pPdeDst;
2594
2595	/* Fetch the pgm pool shadow descriptor. */
2596	rc = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
2597	AssertRCSuccessReturn(rc, rc);
2598	Assert(pShwPde);
2599
2600	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
2601	pPdeDst = &pPDDst->a[iPDDst];
2602
2603	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2604	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
2605	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2606	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
2607	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
2608	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2609	AssertRCSuccessReturn(rc, rc);
2610	Assert(pPDDst);
2611	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2612	# endif
2613	SHWPDE PdeDst = *pPdeDst;
2614
2615	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2616	/* Fetch the pgm pool shadow descriptor. */
2617	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
2618	Assert(pShwPde);
2619	# endif
2620
2621	# ifndef PGM_WITHOUT_MAPPINGS
2622	/*
2623	* Check for conflicts.
2624	* RC: In case of a conflict we'll go to Ring-3 and do a full SyncCR3.
2625	* R3: Simply resolve the conflict.
2626	*/
2627	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
2628	{
2629	Assert(pgmMapAreMappingsEnabled(pVM));
2630	# ifndef IN_RING3
2631	Log(("SyncPT: Conflict at %RGv\n", GCPtrPage));
2632	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
2633	return VERR_ADDRESS_CONFLICT;
2634
2635	# else /* IN_RING3 */
2636	PPGMMAPPING pMapping = pgmGetMapping(pVM, (RTGCPTR)GCPtrPage);
2637	Assert(pMapping);
2638	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2639	rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2640	# elif PGM_GST_TYPE == PGM_TYPE_PAE
2641	rc = pgmR3SyncPTResolveConflictPAE(pVM, pMapping, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2642	# else
2643	AssertFailed(); NOREF(pMapping); /* can't happen for amd64 */
2644	# endif
2645	if (RT_FAILURE(rc))
2646	{
2647	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
2648	return rc;
2649	}
2650	PdeDst = *pPdeDst;
2651	# endif /* IN_RING3 */
2652	}
2653	# endif /* !PGM_WITHOUT_MAPPINGS */
2654	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
2655
2656	/*
2657	* Sync the page directory entry.
2658	*/
2659	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
2660	const bool fPageTable = !PdeSrc.b.u1Size \|\| !GST_IS_PSE_ACTIVE(pVCpu);
2661	if ( PdeSrc.n.u1Present
2662	&& (fPageTable ? GST_IS_PDE_VALID(pVCpu, PdeSrc) : GST_IS_BIG_PDE_VALID(pVCpu, PdeSrc)) )
2663	{
2664	/*
2665	* Allocate & map the page table.
2666	*/
2667	PSHWPT pPTDst;
2668	PPGMPOOLPAGE pShwPage;
2669	RTGCPHYS GCPhys;
2670	if (fPageTable)
2671	{
2672	GCPhys = GST_GET_PDE_GCPHYS(PdeSrc);
2673	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2674	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2675	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| ((iPDDst & 1) * (PAGE_SIZE / 2)));
2676	# endif
2677	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
2678	pShwPde->idx, iPDDst, false /fLockPage/,
2679	&pShwPage);
2680	}
2681	else
2682	{
2683	PGMPOOLACCESS enmAccess;
2684	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2685	const bool fNoExecute = PdeSrc.n.u1NoExecute && GST_IS_NX_ACTIVE(pVCpu);
2686	# else
2687	const bool fNoExecute = false;
2688	# endif
2689
2690	GCPhys = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
2691	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2692	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
2693	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| (GCPtrPage & (1 << X86_PD_PAE_SHIFT)));
2694	# endif
2695	/* Determine the right kind of large page to avoid incorrect cached entry reuse. */
2696	if (PdeSrc.n.u1User)
2697	{
2698	if (PdeSrc.n.u1Write)
2699	enmAccess = (fNoExecute) ? PGMPOOLACCESS_USER_RW_NX : PGMPOOLACCESS_USER_RW;
2700	else
2701	enmAccess = (fNoExecute) ? PGMPOOLACCESS_USER_R_NX : PGMPOOLACCESS_USER_R;
2702	}
2703	else
2704	{
2705	if (PdeSrc.n.u1Write)
2706	enmAccess = (fNoExecute) ? PGMPOOLACCESS_SUPERVISOR_RW_NX : PGMPOOLACCESS_SUPERVISOR_RW;
2707	else
2708	enmAccess = (fNoExecute) ? PGMPOOLACCESS_SUPERVISOR_R_NX : PGMPOOLACCESS_SUPERVISOR_R;
2709	}
2710	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_BIG, enmAccess, PGM_A20_IS_ENABLED(pVCpu),
2711	pShwPde->idx, iPDDst, false /fLockPage/,
2712	&pShwPage);
2713	}
2714	if (rc == VINF_SUCCESS)
2715	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2716	else if (rc == VINF_PGM_CACHED_PAGE)
2717	{
2718	/*
2719	* The PT was cached, just hook it up.
2720	*/
2721	if (fPageTable)
2722	PdeDst.u = pShwPage->Core.Key \| GST_GET_PDE_SHW_FLAGS(pVCpu, PdeSrc);
2723	else
2724	{
2725	PdeDst.u = pShwPage->Core.Key \| GST_GET_BIG_PDE_SHW_FLAGS(pVCpu, PdeSrc);
2726	/* (see explanation and assumptions further down.) */
2727	if ( !PdeSrc.b.u1Dirty
2728	&& PdeSrc.b.u1Write)
2729	{
2730	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageBig));
2731	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2732	PdeDst.b.u1Write = 0;
2733	}
2734	}
2735	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2736	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2737	return VINF_SUCCESS;
2738	}
2739	else if (rc == VERR_PGM_POOL_FLUSHED)
2740	{
2741	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2742	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2743	return VINF_PGM_SYNC_CR3;
2744	}
2745	else
2746	AssertMsgFailedReturn(("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
2747	/** @todo Why do we bother preserving X86_PDE_AVL_MASK here?
2748	* Both PGM_PDFLAGS_MAPPING and PGM_PDFLAGS_TRACK_DIRTY should be
2749	* irrelevant at this point. */
2750	PdeDst.u &= X86_PDE_AVL_MASK;
2751	PdeDst.u \|= pShwPage->Core.Key;
2752
2753	/*
2754	* Page directory has been accessed (this is a fault situation, remember).
2755	*/
2756	/** @todo
2757	* Well, when the caller is PrefetchPage or InvalidatePage is isn't a
2758	* fault situation. What's more, the Trap0eHandler has already set the
2759	* accessed bit. So, it's actually just VerifyAccessSyncPage which
2760	* might need setting the accessed flag.
2761	*
2762	* The best idea is to leave this change to the caller and add an
2763	* assertion that it's set already. */
2764	pPDSrc->a[iPDSrc].n.u1Accessed = 1;
2765	if (fPageTable)
2766	{
2767	/*
2768	* Page table - 4KB.
2769	*
2770	* Sync all or just a few entries depending on PGM_SYNC_N_PAGES.
2771	*/
2772	Log2(("SyncPT: 4K %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx}\n",
2773	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u));
2774	PGSTPT pPTSrc;
2775	rc = PGM_GCPHYS_2_PTR(pVM, GST_GET_PDE_GCPHYS(PdeSrc), &pPTSrc);
2776	if (RT_SUCCESS(rc))
2777	{
2778	/*
2779	* Start by syncing the page directory entry so CSAM's TLB trick works.
2780	*/
2781	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| X86_PDE_AVL_MASK))
2782	\| GST_GET_PDE_SHW_FLAGS(pVCpu, PdeSrc);
2783	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2784	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2785
2786	/*
2787	* Directory/page user or supervisor privilege: (same goes for read/write)
2788	*
2789	* Directory Page Combined
2790	* U/S U/S U/S
2791	* 0 0 0
2792	* 0 1 0
2793	* 1 0 0
2794	* 1 1 1
2795	*
2796	* Simple AND operation. Table listed for completeness.
2797	*
2798	*/
2799	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT4K));
2800	# ifdef PGM_SYNC_N_PAGES
2801	unsigned iPTBase = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2802	unsigned iPTDst = iPTBase;
2803	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2804	if (iPTDst <= PGM_SYNC_NR_PAGES / 2)
2805	iPTDst = 0;
2806	else
2807	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2808	# else /* !PGM_SYNC_N_PAGES */
2809	unsigned iPTDst = 0;
2810	const unsigned iPTDstEnd = RT_ELEMENTS(pPTDst->a);
2811	# endif /* !PGM_SYNC_N_PAGES */
2812	RTGCPTR GCPtrCur = (GCPtrPage & ~(RTGCPTR)((1 << SHW_PD_SHIFT) - 1))
2813	\| ((RTGCPTR)iPTDst << PAGE_SHIFT);
2814	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2815	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2816	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
2817	# else
2818	const unsigned offPTSrc = 0;
2819	# endif
2820	for (; iPTDst < iPTDstEnd; iPTDst++, GCPtrCur += PAGE_SIZE)
2821	{
2822	const unsigned iPTSrc = iPTDst + offPTSrc;
2823	const GSTPTE PteSrc = pPTSrc->a[iPTSrc];
2824
2825	if (PteSrc.n.u1Present)
2826	{
2827	# ifdef VBOX_WITH_RAW_MODE_NOT_R0
2828	/*
2829	* Assuming kernel code will be marked as supervisor - and not as user level
2830	* and executed using a conforming code selector - And marked as readonly.
2831	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
2832	*/
2833	PPGMPAGE pPage;
2834	if ( ((PdeSrc.u & pPTSrc->a[iPTSrc].u) & (X86_PTE_RW \| X86_PTE_US))
2835	\|\| !CSAMDoesPageNeedScanning(pVM, GCPtrCur)
2836	\|\| ( (pPage = pgmPhysGetPage(pVM, GST_GET_PTE_GCPHYS(PteSrc)))
2837	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2838	)
2839	# endif
2840	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2841	Log2(("SyncPT: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s dst.raw=%08llx iPTSrc=%x PdeSrc.u=%x physpte=%RGp\n",
2842	GCPtrCur,
2843	PteSrc.n.u1Present,
2844	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2845	PteSrc.n.u1User & PdeSrc.n.u1User,
2846	(uint64_t)PteSrc.u,
2847	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : "", SHW_PTE_LOG64(pPTDst->a[iPTDst]), iPTSrc, PdeSrc.au32[0],
2848	(RTGCPHYS)(GST_GET_PDE_GCPHYS(PdeSrc) + iPTSrc*sizeof(PteSrc)) ));
2849	}
2850	/* else: the page table was cleared by the pool */
2851	} /* for PTEs */
2852	}
2853	}
2854	else
2855	{
2856	/*
2857	* Big page - 2/4MB.
2858	*
2859	* We'll walk the ram range list in parallel and optimize lookups.
2860	* We will only sync one shadow page table at a time.
2861	*/
2862	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT4M));
2863
2864	/**
2865	* @todo It might be more efficient to sync only a part of the 4MB
2866	* page (similar to what we do for 4KB PDs).
2867	*/
2868
2869	/*
2870	* Start by syncing the page directory entry.
2871	*/
2872	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| (X86_PDE_AVL_MASK & ~PGM_PDFLAGS_TRACK_DIRTY)))
2873	\| GST_GET_BIG_PDE_SHW_FLAGS(pVCpu, PdeSrc);
2874
2875	/*
2876	* If the page is not flagged as dirty and is writable, then make it read-only
2877	* at PD level, so we can set the dirty bit when the page is modified.
2878	*
2879	* ASSUMES that page access handlers are implemented on page table entry level.
2880	* Thus we will first catch the dirty access and set PDE.D and restart. If
2881	* there is an access handler, we'll trap again and let it work on the problem.
2882	*/
2883	/** @todo move the above stuff to a section in the PGM documentation. */
2884	Assert(!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY));
2885	if ( !PdeSrc.b.u1Dirty
2886	&& PdeSrc.b.u1Write)
2887	{
2888	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageBig));
2889	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2890	PdeDst.b.u1Write = 0;
2891	}
2892	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2893	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2894
2895	/*
2896	* Fill the shadow page table.
2897	*/
2898	/* Get address and flags from the source PDE. */
2899	SHWPTE PteDstBase;
2900	SHW_PTE_SET(PteDstBase, GST_GET_BIG_PDE_SHW_FLAGS_4_PTE(pVCpu, PdeSrc));
2901
2902	/* Loop thru the entries in the shadow PT. */
2903	const RTGCPTR GCPtr = (GCPtrPage >> SHW_PD_SHIFT) << SHW_PD_SHIFT; NOREF(GCPtr);
2904	Log2(("SyncPT: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} Shw=%RGv GCPhys=%RGp %s\n",
2905	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u, GCPtr,
2906	GCPhys, PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2907	PPGMRAMRANGE pRam = pgmPhysGetRangeAtOrAbove(pVM, GCPhys);
2908	unsigned iPTDst = 0;
2909	while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2910	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
2911	{
2912	if (pRam && GCPhys >= pRam->GCPhys)
2913	{
2914	# ifndef PGM_WITH_A20
2915	unsigned iHCPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
2916	# endif
2917	do
2918	{
2919	/* Make shadow PTE. */
2920	# ifdef PGM_WITH_A20
2921	PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
2922	# else
2923	PPGMPAGE pPage = &pRam->aPages[iHCPage];
2924	# endif
2925	SHWPTE PteDst;
2926
2927	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
2928	/* Try to make the page writable if necessary. */
2929	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
2930	&& ( PGM_PAGE_IS_ZERO(pPage)
2931	\|\| ( SHW_PTE_IS_RW(PteDstBase)
2932	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
2933	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
2934	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
2935	# endif
2936	# ifdef VBOX_WITH_PAGE_SHARING
2937	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
2938	# endif
2939	&& !PGM_PAGE_IS_BALLOONED(pPage))
2940	)
2941	)
2942	{
2943	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
2944	AssertRCReturn(rc, rc);
2945	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
2946	break;
2947	}
2948	# endif
2949
2950	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2951	PGM_BTH_NAME(SyncHandlerPte)(pVM, pPage, SHW_PTE_GET_U(PteDstBase), &PteDst);
2952	else if (PGM_PAGE_IS_BALLOONED(pPage))
2953	SHW_PTE_SET(PteDst, 0); /* Handle ballooned pages at #PF time. */
2954	# ifdef VBOX_WITH_RAW_MODE_NOT_R0
2955	/*
2956	* Assuming kernel code will be marked as supervisor and not as user level and executed
2957	* using a conforming code selector. Don't check for readonly, as that implies the whole
2958	* 4MB can be code or readonly data. Linux enables write access for its large pages.
2959	*/
2960	else if ( !PdeSrc.n.u1User
2961	&& CSAMDoesPageNeedScanning(pVM, GCPtr \| (iPTDst << SHW_PT_SHIFT)))
2962	SHW_PTE_SET(PteDst, 0);
2963	# endif
2964	else
2965	SHW_PTE_SET(PteDst, PGM_PAGE_GET_HCPHYS(pPage) \| SHW_PTE_GET_U(PteDstBase));
2966
2967	/* Only map writable pages writable. */
2968	if ( SHW_PTE_IS_P_RW(PteDst)
2969	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
2970	{
2971	/* Still applies to shared pages. */
2972	Assert(!PGM_PAGE_IS_ZERO(pPage));
2973	SHW_PTE_SET_RO(PteDst); /** @todo this isn't quite working yet... */
2974	Log3(("SyncPT: write-protecting %RGp pPage=%R[pgmpage] at %RGv\n", GCPhys, pPage, (RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT))));
2975	}
2976
2977	if (SHW_PTE_IS_P(PteDst))
2978	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
2979
2980	/* commit it (not atomic, new table) */
2981	pPTDst->a[iPTDst] = PteDst;
2982	Log4(("SyncPT: BIG %RGv PteDst:{P=%d RW=%d U=%d raw=%08llx}%s\n",
2983	(RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT)), SHW_PTE_IS_P(PteDst), SHW_PTE_IS_RW(PteDst), SHW_PTE_IS_US(PteDst), SHW_PTE_LOG64(PteDst),
2984	SHW_PTE_IS_TRACK_DIRTY(PteDst) ? " Track-Dirty" : ""));
2985
2986	/* advance */
2987	GCPhys += PAGE_SIZE;
2988	PGM_A20_APPLY_TO_VAR(pVCpu, GCPhys);
2989	# ifndef PGM_WITH_A20
2990	iHCPage++;
2991	# endif
2992	iPTDst++;
2993	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2994	&& GCPhys <= pRam->GCPhysLast);
2995
2996	/* Advance ram range list. */
2997	while (pRam && GCPhys > pRam->GCPhysLast)
2998	pRam = pRam->CTX_SUFF(pNext);
2999	}
3000	else if (pRam)
3001	{
3002	Log(("Invalid pages at %RGp\n", GCPhys));
3003	do
3004	{
3005	SHW_PTE_SET(pPTDst->a[iPTDst], 0); /* Invalid page, we must handle them manually. */
3006	GCPhys += PAGE_SIZE;
3007	iPTDst++;
3008	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
3009	&& GCPhys < pRam->GCPhys);
3010	PGM_A20_APPLY_TO_VAR(pVCpu,GCPhys);
3011	}
3012	else
3013	{
3014	Log(("Invalid pages at %RGp (2)\n", GCPhys));
3015	for ( ; iPTDst < RT_ELEMENTS(pPTDst->a); iPTDst++)
3016	SHW_PTE_SET(pPTDst->a[iPTDst], 0); /* Invalid page, we must handle them manually. */
3017	}
3018	} /* while more PTEs */
3019	} /* 4KB / 4MB */
3020	}
3021	else
3022	AssertRelease(!PdeDst.n.u1Present);
3023
3024	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3025	if (RT_FAILURE(rc))
3026	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPTFailed));
3027	return rc;
3028
3029	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
3030	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
3031	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
3032	&& !defined(IN_RC)
3033	NOREF(iPDSrc); NOREF(pPDSrc);
3034
3035	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3036
3037	/*
3038	* Validate input a little bit.
3039	*/
3040	int rc = VINF_SUCCESS;
3041	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3042	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
3043	PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
3044
3045	/* Fetch the pgm pool shadow descriptor. */
3046	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
3047	Assert(pShwPde);
3048
3049	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3050	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
3051	PPGMPOOLPAGE pShwPde = NULL; /* initialized to shut up gcc */
3052	PX86PDPAE pPDDst;
3053	PSHWPDE pPdeDst;
3054
3055	/* Fetch the pgm pool shadow descriptor. */
3056	rc = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
3057	AssertRCSuccessReturn(rc, rc);
3058	Assert(pShwPde);
3059
3060	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
3061	pPdeDst = &pPDDst->a[iPDDst];
3062
3063	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3064	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3065	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
3066	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
3067	PX86PDPT pPdptDst= NULL; /* initialized to shut up gcc */
3068	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
3069	AssertRCSuccessReturn(rc, rc);
3070	Assert(pPDDst);
3071	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
3072
3073	/* Fetch the pgm pool shadow descriptor. */
3074	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
3075	Assert(pShwPde);
3076
3077	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
3078	const unsigned iPdpt = (GCPtrPage >> EPT_PDPT_SHIFT) & EPT_PDPT_MASK;
3079	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3080	PEPTPD pPDDst;
3081	PEPTPDPT pPdptDst;
3082
3083	rc = pgmShwGetEPTPDPtr(pVCpu, GCPtrPage, &pPdptDst, &pPDDst);
3084	if (rc != VINF_SUCCESS)
3085	{
3086	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3087	AssertRC(rc);
3088	return rc;
3089	}
3090	Assert(pPDDst);
3091	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
3092
3093	/* Fetch the pgm pool shadow descriptor. */
3094	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & EPT_PDPTE_PG_MASK);
3095	Assert(pShwPde);
3096	# endif
3097	SHWPDE PdeDst = *pPdeDst;
3098
3099	Assert(!(PdeDst.u & PGM_PDFLAGS_MAPPING));
3100	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
3101
3102	# if defined(PGM_WITH_LARGE_PAGES) && PGM_SHW_TYPE != PGM_TYPE_32BIT && PGM_SHW_TYPE != PGM_TYPE_PAE
3103	if (BTH_IS_NP_ACTIVE(pVM))
3104	{
3105	/* Check if we allocated a big page before for this 2 MB range. */
3106	PPGMPAGE pPage;
3107	rc = pgmPhysGetPageEx(pVM, PGM_A20_APPLY(pVCpu, GCPtrPage & X86_PDE2M_PAE_PG_MASK), &pPage);
3108	if (RT_SUCCESS(rc))
3109	{
3110	RTHCPHYS HCPhys = NIL_RTHCPHYS;
3111	if (PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE)
3112	{
3113	if (PGM_A20_IS_ENABLED(pVCpu))
3114	{
3115	STAM_REL_COUNTER_INC(&pVM->pgm.s.StatLargePageReused);
3116	AssertRelease(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
3117	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3118	}
3119	else
3120	{
3121	PGM_PAGE_SET_PDE_TYPE(pVM, pPage, PGM_PAGE_PDE_TYPE_PDE_DISABLED);
3122	pVM->pgm.s.cLargePagesDisabled++;
3123	}
3124	}
3125	else if ( PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE_DISABLED
3126	&& PGM_A20_IS_ENABLED(pVCpu))
3127	{
3128	/* Recheck the entire 2 MB range to see if we can use it again as a large page. */
3129	rc = pgmPhysRecheckLargePage(pVM, GCPtrPage, pPage);
3130	if (RT_SUCCESS(rc))
3131	{
3132	Assert(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
3133	Assert(PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE);
3134	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3135	}
3136	}
3137	else if ( PGMIsUsingLargePages(pVM)
3138	&& PGM_A20_IS_ENABLED(pVCpu))
3139	{
3140	rc = pgmPhysAllocLargePage(pVM, GCPtrPage);
3141	if (RT_SUCCESS(rc))
3142	{
3143	Assert(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
3144	Assert(PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE);
3145	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3146	}
3147	else
3148	LogFlow(("pgmPhysAllocLargePage failed with %Rrc\n", rc));
3149	}
3150
3151	if (HCPhys != NIL_RTHCPHYS)
3152	{
3153	PdeDst.u &= X86_PDE_AVL_MASK;
3154	PdeDst.u \|= HCPhys;
3155	PdeDst.n.u1Present = 1;
3156	PdeDst.n.u1Write = 1;
3157	PdeDst.b.u1Size = 1;
3158	# if PGM_SHW_TYPE == PGM_TYPE_EPT
3159	PdeDst.n.u1Execute = 1;
3160	PdeDst.b.u1IgnorePAT = 1;
3161	PdeDst.b.u3EMT = VMX_EPT_MEMTYPE_WB;
3162	# else
3163	PdeDst.n.u1User = 1;
3164	# endif
3165	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
3166
3167	Log(("SyncPT: Use large page at %RGp PDE=%RX64\n", GCPtrPage, PdeDst.u));
3168	/* Add a reference to the first page only. */
3169	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPde, PGM_PAGE_GET_TRACKING(pPage), pPage, iPDDst);
3170
3171	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3172	return VINF_SUCCESS;
3173	}
3174	}
3175	}
3176	# endif /* HC_ARCH_BITS == 64 */
3177
3178	/*
3179	* Allocate & map the page table.
3180	*/
3181	PSHWPT pPTDst;
3182	PPGMPOOLPAGE pShwPage;
3183	RTGCPHYS GCPhys;
3184
3185	/* Virtual address = physical address */
3186	GCPhys = PGM_A20_APPLY(pVCpu, GCPtrPage & X86_PAGE_4K_BASE_MASK);
3187	rc = pgmPoolAlloc(pVM, GCPhys & ~(RT_BIT_64(SHW_PD_SHIFT) - 1), BTH_PGMPOOLKIND_PT_FOR_PT, PGMPOOLACCESS_DONTCARE,
3188	PGM_A20_IS_ENABLED(pVCpu), pShwPde->idx, iPDDst, false /fLockPage/,
3189	&pShwPage);
3190	if ( rc == VINF_SUCCESS
3191	\|\| rc == VINF_PGM_CACHED_PAGE)
3192	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
3193	else
3194	{
3195	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3196	AssertMsgFailedReturn(("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
3197	}
3198
3199	if (rc == VINF_SUCCESS)
3200	{
3201	/* New page table; fully set it up. */
3202	Assert(pPTDst);
3203
3204	/* Mask away the page offset. */
3205	GCPtrPage &= ~(RTGCPTR)PAGE_OFFSET_MASK;
3206
3207	for (unsigned iPTDst = 0; iPTDst < RT_ELEMENTS(pPTDst->a); iPTDst++)
3208	{
3209	RTGCPTR GCPtrCurPage = PGM_A20_APPLY(pVCpu, (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT))
3210	\| (iPTDst << PAGE_SHIFT));
3211
3212	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], GCPtrCurPage, pShwPage, iPTDst);
3213	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=1 RW=1 U=1} PteDst=%08llx%s\n",
3214	GCPtrCurPage,
3215	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
3216	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
3217
3218	if (RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)))
3219	break;
3220	}
3221	}
3222	else
3223	rc = VINF_SUCCESS; /* Cached entry; assume it's still fully valid. */
3224
3225	/* Save the new PDE. */
3226	PdeDst.u &= X86_PDE_AVL_MASK;
3227	PdeDst.u \|= pShwPage->Core.Key;
3228	PdeDst.n.u1Present = 1;
3229	PdeDst.n.u1Write = 1;
3230	# if PGM_SHW_TYPE == PGM_TYPE_EPT
3231	PdeDst.n.u1Execute = 1;
3232	# else
3233	PdeDst.n.u1User = 1;
3234	PdeDst.n.u1Accessed = 1;
3235	# endif
3236	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
3237
3238	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3239	if (RT_FAILURE(rc))
3240	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPTFailed));
3241	return rc;
3242
3243	#else
3244	NOREF(iPDSrc); NOREF(pPDSrc);
3245	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_SHW_TYPE, PGM_GST_TYPE));
3246	return VERR_PGM_NOT_USED_IN_MODE;
3247	#endif
3248	}
3249
3250
3251
3252	/**
3253	* Prefetch a page/set of pages.
3254	*
3255	* Typically used to sync commonly used pages before entering raw mode
3256	* after a CR3 reload.
3257	*
3258	* @returns VBox status code.
3259	* @param pVCpu Pointer to the VMCPU.
3260	* @param GCPtrPage Page to invalidate.
3261	*/
3262	PGM_BTH_DECL(int, PrefetchPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage)
3263	{
3264	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
3265	\|\| PGM_GST_TYPE == PGM_TYPE_REAL \
3266	\|\| PGM_GST_TYPE == PGM_TYPE_PROT \
3267	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3268	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64 ) \
3269	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
3270	&& PGM_SHW_TYPE != PGM_TYPE_EPT
3271
3272	/*
3273	* Check that all Guest levels thru the PDE are present, getting the
3274	* PD and PDE in the processes.
3275	*/
3276	int rc = VINF_SUCCESS;
3277	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3278	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3279	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
3280	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
3281	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3282	unsigned iPDSrc;
3283	X86PDPE PdpeSrc;
3284	PGSTPD pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtrPage, &iPDSrc, &PdpeSrc);
3285	if (!pPDSrc)
3286	return VINF_SUCCESS; /* not present */
3287	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
3288	unsigned iPDSrc;
3289	PX86PML4E pPml4eSrc;
3290	X86PDPE PdpeSrc;
3291	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3292	if (!pPDSrc)
3293	return VINF_SUCCESS; /* not present */
3294	# endif
3295	const GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
3296	# else
3297	PGSTPD pPDSrc = NULL;
3298	const unsigned iPDSrc = 0;
3299	GSTPDE PdeSrc;
3300
3301	PdeSrc.u = 0; /* faked so we don't have to #ifdef everything */
3302	PdeSrc.n.u1Present = 1;
3303	PdeSrc.n.u1Write = 1;
3304	PdeSrc.n.u1Accessed = 1;
3305	PdeSrc.n.u1User = 1;
3306	# endif
3307
3308	if (PdeSrc.n.u1Present && PdeSrc.n.u1Accessed)
3309	{
3310	PVM pVM = pVCpu->CTX_SUFF(pVM);
3311	pgmLock(pVM);
3312
3313	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3314	const X86PDE PdeDst = pgmShwGet32BitPDE(pVCpu, GCPtrPage);
3315	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3316	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3317	PX86PDPAE pPDDst;
3318	X86PDEPAE PdeDst;
3319	# if PGM_GST_TYPE != PGM_TYPE_PAE
3320	X86PDPE PdpeSrc;
3321
3322	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
3323	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
3324	# endif
3325	rc = pgmShwSyncPaePDPtr(pVCpu, GCPtrPage, PdpeSrc.u, &pPDDst);
3326	if (rc != VINF_SUCCESS)
3327	{
3328	pgmUnlock(pVM);
3329	AssertRC(rc);
3330	return rc;
3331	}
3332	Assert(pPDDst);
3333	PdeDst = pPDDst->a[iPDDst];
3334
3335	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3336	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3337	PX86PDPAE pPDDst;
3338	X86PDEPAE PdeDst;
3339
3340	# if PGM_GST_TYPE == PGM_TYPE_PROT
3341	/* AMD-V nested paging */
3342	X86PML4E Pml4eSrc;
3343	X86PDPE PdpeSrc;
3344	PX86PML4E pPml4eSrc = &Pml4eSrc;
3345
3346	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
3347	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A;
3348	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A;
3349	# endif
3350
3351	rc = pgmShwSyncLongModePDPtr(pVCpu, GCPtrPage, pPml4eSrc->u, PdpeSrc.u, &pPDDst);
3352	if (rc != VINF_SUCCESS)
3353	{
3354	pgmUnlock(pVM);
3355	AssertRC(rc);
3356	return rc;
3357	}
3358	Assert(pPDDst);
3359	PdeDst = pPDDst->a[iPDDst];
3360	# endif
3361	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
3362	{
3363	if (!PdeDst.n.u1Present)
3364	{
3365	/** @todo r=bird: This guy will set the A bit on the PDE,
3366	* probably harmless. */
3367	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
3368	}
3369	else
3370	{
3371	/* Note! We used to sync PGM_SYNC_NR_PAGES pages, which triggered assertions in CSAM, because
3372	* R/W attributes of nearby pages were reset. Not sure how that could happen. Anyway, it
3373	* makes no sense to prefetch more than one page.
3374	*/
3375	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
3376	if (RT_SUCCESS(rc))
3377	rc = VINF_SUCCESS;
3378	}
3379	}
3380	pgmUnlock(pVM);
3381	}
3382	return rc;
3383
3384	#elif PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3385	NOREF(pVCpu); NOREF(GCPtrPage);
3386	return VINF_SUCCESS; /* ignore */
3387	#else
3388	AssertCompile(0);
3389	#endif
3390	}
3391
3392
3393
3394
3395	/**
3396	* Syncs a page during a PGMVerifyAccess() call.
3397	*
3398	* @returns VBox status code (informational included).
3399	* @param pVCpu Pointer to the VMCPU.
3400	* @param GCPtrPage The address of the page to sync.
3401	* @param fPage The effective guest page flags.
3402	* @param uErr The trap error code.
3403	* @remarks This will normally never be called on invalid guest page
3404	* translation entries.
3405	*/
3406	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fPage, unsigned uErr)
3407	{
3408	PVM pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
3409
3410	LogFlow(("VerifyAccessSyncPage: GCPtrPage=%RGv fPage=%#x uErr=%#x\n", GCPtrPage, fPage, uErr));
3411
3412	Assert(!pVM->pgm.s.fNestedPaging);
3413	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
3414	\|\| PGM_GST_TYPE == PGM_TYPE_REAL \
3415	\|\| PGM_GST_TYPE == PGM_TYPE_PROT \
3416	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3417	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64 ) \
3418	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
3419	&& PGM_SHW_TYPE != PGM_TYPE_EPT
3420
3421	# ifdef VBOX_WITH_RAW_MODE_NOT_R0
3422	if (!(fPage & X86_PTE_US))
3423	{
3424	/*
3425	* Mark this page as safe.
3426	*/
3427	/** @todo not correct for pages that contain both code and data!! */
3428	Log(("CSAMMarkPage %RGv; scanned=%d\n", GCPtrPage, true));
3429	CSAMMarkPage(pVM, GCPtrPage, true);
3430	}
3431	# endif
3432
3433	/*
3434	* Get guest PD and index.
3435	*/
3436	/** @todo Performance: We've done all this a jiffy ago in the
3437	* PGMGstGetPage call. */
3438	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3439	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3440	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
3441	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
3442
3443	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3444	unsigned iPDSrc = 0;
3445	X86PDPE PdpeSrc;
3446	PGSTPD pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtrPage, &iPDSrc, &PdpeSrc);
3447	if (RT_UNLIKELY(!pPDSrc))
3448	{
3449	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
3450	return VINF_EM_RAW_GUEST_TRAP;
3451	}
3452
3453	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
3454	unsigned iPDSrc = 0; /* shut up gcc */
3455	PX86PML4E pPml4eSrc = NULL; /* ditto */
3456	X86PDPE PdpeSrc;
3457	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3458	if (RT_UNLIKELY(!pPDSrc))
3459	{
3460	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
3461	return VINF_EM_RAW_GUEST_TRAP;
3462	}
3463	# endif
3464
3465	# else /* !PGM_WITH_PAGING */
3466	PGSTPD pPDSrc = NULL;
3467	const unsigned iPDSrc = 0;
3468	# endif /* !PGM_WITH_PAGING */
3469	int rc = VINF_SUCCESS;
3470
3471	pgmLock(pVM);
3472
3473	/*
3474	* First check if the shadow pd is present.
3475	*/
3476	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3477	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
3478
3479	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3480	PX86PDEPAE pPdeDst;
3481	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3482	PX86PDPAE pPDDst;
3483	# if PGM_GST_TYPE != PGM_TYPE_PAE
3484	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
3485	X86PDPE PdpeSrc;
3486	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
3487	# endif
3488	rc = pgmShwSyncPaePDPtr(pVCpu, GCPtrPage, PdpeSrc.u, &pPDDst);
3489	if (rc != VINF_SUCCESS)
3490	{
3491	pgmUnlock(pVM);
3492	AssertRC(rc);
3493	return rc;
3494	}
3495	Assert(pPDDst);
3496	pPdeDst = &pPDDst->a[iPDDst];
3497
3498	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3499	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3500	PX86PDPAE pPDDst;
3501	PX86PDEPAE pPdeDst;
3502
3503	# if PGM_GST_TYPE == PGM_TYPE_PROT
3504	/* AMD-V nested paging: Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
3505	X86PML4E Pml4eSrc;
3506	X86PDPE PdpeSrc;
3507	PX86PML4E pPml4eSrc = &Pml4eSrc;
3508	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A;
3509	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A;
3510	# endif
3511
3512	rc = pgmShwSyncLongModePDPtr(pVCpu, GCPtrPage, pPml4eSrc->u, PdpeSrc.u, &pPDDst);
3513	if (rc != VINF_SUCCESS)
3514	{
3515	pgmUnlock(pVM);
3516	AssertRC(rc);
3517	return rc;
3518	}
3519	Assert(pPDDst);
3520	pPdeDst = &pPDDst->a[iPDDst];
3521	# endif
3522
3523	if (!pPdeDst->n.u1Present)
3524	{
3525	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
3526	if (rc != VINF_SUCCESS)
3527	{
3528	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
3529	pgmUnlock(pVM);
3530	AssertRC(rc);
3531	return rc;
3532	}
3533	}
3534
3535	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3536	/* Check for dirty bit fault */
3537	rc = PGM_BTH_NAME(CheckDirtyPageFault)(pVCpu, uErr, pPdeDst, &pPDSrc->a[iPDSrc], GCPtrPage);
3538	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
3539	Log(("PGMVerifyAccess: success (dirty)\n"));
3540	else
3541	# endif
3542	{
3543	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3544	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
3545	# else
3546	GSTPDE PdeSrc;
3547	PdeSrc.u = 0; /* faked so we don't have to #ifdef everything */
3548	PdeSrc.n.u1Present = 1;
3549	PdeSrc.n.u1Write = 1;
3550	PdeSrc.n.u1Accessed = 1;
3551	PdeSrc.n.u1User = 1;
3552	# endif
3553
3554	Assert(rc != VINF_EM_RAW_GUEST_TRAP);
3555	if (uErr & X86_TRAP_PF_US)
3556	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncUser));
3557	else /* supervisor */
3558	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
3559
3560	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
3561	if (RT_SUCCESS(rc))
3562	{
3563	/* Page was successfully synced */
3564	Log2(("PGMVerifyAccess: success (sync)\n"));
3565	rc = VINF_SUCCESS;
3566	}
3567	else
3568	{
3569	Log(("PGMVerifyAccess: access violation for %RGv rc=%Rrc\n", GCPtrPage, rc));
3570	rc = VINF_EM_RAW_GUEST_TRAP;
3571	}
3572	}
3573	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
3574	pgmUnlock(pVM);
3575	return rc;
3576
3577	#else /* PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED */
3578
3579	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
3580	return VERR_PGM_NOT_USED_IN_MODE;
3581	#endif /* PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED */
3582	}
3583
3584
3585	/**
3586	* Syncs the paging hierarchy starting at CR3.
3587	*
3588	* @returns VBox status code, no specials.
3589	* @param pVCpu Pointer to the VMCPU.
3590	* @param cr0 Guest context CR0 register.
3591	* @param cr3 Guest context CR3 register. Not subjected to the A20
3592	* mask.
3593	* @param cr4 Guest context CR4 register.
3594	* @param fGlobal Including global page directories or not
3595	*/
3596	PGM_BTH_DECL(int, SyncCR3)(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
3597	{
3598	PVM pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
3599	NOREF(cr0); NOREF(cr3); NOREF(cr4); NOREF(fGlobal);
3600
3601	LogFlow(("SyncCR3 FF=%d fGlobal=%d\n", !!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3), fGlobal));
3602
3603	#if PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
3604
3605	pgmLock(pVM);
3606
3607	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
3608	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3609	if (pPool->cDirtyPages)
3610	pgmPoolResetDirtyPages(pVM);
3611	# endif
3612
3613	/*
3614	* Update page access handlers.
3615	* The virtual are always flushed, while the physical are only on demand.
3616	* WARNING: We are incorrectly not doing global flushing on Virtual Handler updates. We'll
3617	* have to look into that later because it will have a bad influence on the performance.
3618	* @note SvL: There's no need for that. Just invalidate the virtual range(s).
3619	* bird: Yes, but that won't work for aliases.
3620	*/
3621	/** @todo this MUST go away. See @bugref{1557}. */
3622	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3Handlers), h);
3623	PGM_GST_NAME(HandlerVirtualUpdate)(pVM, cr4);
3624	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3Handlers), h);
3625	pgmUnlock(pVM);
3626	#endif /* !NESTED && !EPT */
3627
3628	#if PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3629	/*
3630	* Nested / EPT - almost no work.
3631	*/
3632	Assert(!pgmMapAreMappingsEnabled(pVM));
3633	return VINF_SUCCESS;
3634
3635	#elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3636	/*
3637	* AMD64 (Shw & Gst) - No need to check all paging levels; we zero
3638	* out the shadow parts when the guest modifies its tables.
3639	*/
3640	Assert(!pgmMapAreMappingsEnabled(pVM));
3641	return VINF_SUCCESS;
3642
3643	#else /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
3644
3645	# ifndef PGM_WITHOUT_MAPPINGS
3646	/*
3647	* Check for and resolve conflicts with our guest mappings if they
3648	* are enabled and not fixed.
3649	*/
3650	if (pgmMapAreMappingsFloating(pVM))
3651	{
3652	int rc = pgmMapResolveConflicts(pVM);
3653	Assert(rc == VINF_SUCCESS \|\| rc == VINF_PGM_SYNC_CR3);
3654	if (rc == VINF_PGM_SYNC_CR3)
3655	{
3656	LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
3657	return VINF_PGM_SYNC_CR3;
3658	}
3659	}
3660	# else
3661	Assert(!pgmMapAreMappingsEnabled(pVM));
3662	# endif
3663	return VINF_SUCCESS;
3664	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
3665	}
3666
3667
3668
3669
3670	#ifdef VBOX_STRICT
3671	# ifdef IN_RC
3672	# undef AssertMsgFailed
3673	# define AssertMsgFailed Log
3674	# endif
3675
3676	/**
3677	* Checks that the shadow page table is in sync with the guest one.
3678	*
3679	* @returns The number of errors.
3680	* @param pVM The virtual machine.
3681	* @param pVCpu Pointer to the VMCPU.
3682	* @param cr3 Guest context CR3 register.
3683	* @param cr4 Guest context CR4 register.
3684	* @param GCPtr Where to start. Defaults to 0.
3685	* @param cb How much to check. Defaults to everything.
3686	*/
3687	PGM_BTH_DECL(unsigned, AssertCR3)(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb)
3688	{
3689	NOREF(pVCpu); NOREF(cr3); NOREF(cr4); NOREF(GCPtr); NOREF(cb);
3690	#if PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3691	return 0;
3692	#else
3693	unsigned cErrors = 0;
3694	PVM pVM = pVCpu->CTX_SUFF(pVM);
3695	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool); NOREF(pPool);
3696
3697	# if PGM_GST_TYPE == PGM_TYPE_PAE
3698	/** @todo currently broken; crashes below somewhere */
3699	AssertFailed();
3700	# endif
3701
3702	# if PGM_GST_TYPE == PGM_TYPE_32BIT \
3703	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3704	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
3705
3706	bool fBigPagesSupported = GST_IS_PSE_ACTIVE(pVCpu);
3707	PPGMCPU pPGM = &pVCpu->pgm.s;
3708	RTGCPHYS GCPhysGst; /* page address derived from the guest page tables. */
3709	RTHCPHYS HCPhysShw; /* page address derived from the shadow page tables. */
3710	# ifndef IN_RING0
3711	RTHCPHYS HCPhys; /* general usage. */
3712	# endif
3713	int rc;
3714
3715	/*
3716	* Check that the Guest CR3 and all its mappings are correct.
3717	*/
3718	AssertMsgReturn(pPGM->GCPhysCR3 == PGM_A20_APPLY(pVCpu, cr3 & GST_CR3_PAGE_MASK),
3719	("Invalid GCPhysCR3=%RGp cr3=%RGp\n", pPGM->GCPhysCR3, (RTGCPHYS)cr3),
3720	false);
3721	# if !defined(IN_RING0) && PGM_GST_TYPE != PGM_TYPE_AMD64
3722	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3723	rc = PGMShwGetPage(pVCpu, (RTRCUINTPTR)pPGM->pGst32BitPdRC, NULL, &HCPhysShw);
3724	# else
3725	rc = PGMShwGetPage(pVCpu, (RTRCUINTPTR)pPGM->pGstPaePdptRC, NULL, &HCPhysShw);
3726	# endif
3727	AssertRCReturn(rc, 1);
3728	HCPhys = NIL_RTHCPHYS;
3729	rc = pgmRamGCPhys2HCPhys(pVM, PGM_A20_APPLY(pVCpu, cr3 & GST_CR3_PAGE_MASK), &HCPhys);
3730	AssertMsgReturn(HCPhys == HCPhysShw, ("HCPhys=%RHp HCPhyswShw=%RHp (cr3)\n", HCPhys, HCPhysShw), false);
3731	# if PGM_GST_TYPE == PGM_TYPE_32BIT && defined(IN_RING3)
3732	pgmGstGet32bitPDPtr(pVCpu);
3733	RTGCPHYS GCPhys;
3734	rc = PGMR3DbgR3Ptr2GCPhys(pVM->pUVM, pPGM->pGst32BitPdR3, &GCPhys);
3735	AssertRCReturn(rc, 1);
3736	AssertMsgReturn(PGM_A20_APPLY(pVCpu, cr3 & GST_CR3_PAGE_MASK) == GCPhys, ("GCPhys=%RGp cr3=%RGp\n", GCPhys, (RTGCPHYS)cr3), false);
3737	# endif
3738	# endif /* !IN_RING0 */
3739
3740	/*
3741	* Get and check the Shadow CR3.
3742	*/
3743	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3744	unsigned cPDEs = X86_PG_ENTRIES;
3745	unsigned cIncrement = X86_PG_ENTRIES * PAGE_SIZE;
3746	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3747	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3748	unsigned cPDEs = X86_PG_PAE_ENTRIES * 4; /* treat it as a 2048 entry table. */
3749	# else
3750	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3751	# endif
3752	unsigned cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3753	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3754	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3755	unsigned cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3756	# endif
3757	if (cb != ~(RTGCPTR)0)
3758	cPDEs = RT_MIN(cb >> SHW_PD_SHIFT, 1);
3759
3760	/** @todo call the other two PGMAssert() functions. /
3761
3762	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3763	unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3764
3765	for (; iPml4 < X86_PG_PAE_ENTRIES; iPml4++)
3766	{
3767	PPGMPOOLPAGE pShwPdpt = NULL;
3768	PX86PML4E pPml4eSrc;
3769	PX86PML4E pPml4eDst;
3770	RTGCPHYS GCPhysPdptSrc;
3771
3772	pPml4eSrc = pgmGstGetLongModePML4EPtr(pVCpu, iPml4);
3773	pPml4eDst = pgmShwGetLongModePML4EPtr(pVCpu, iPml4);
3774
3775	/* Fetch the pgm pool shadow descriptor if the shadow pml4e is present. */
3776	if (!pPml4eDst->n.u1Present)
3777	{
3778	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3779	continue;
3780	}
3781
3782	pShwPdpt = pgmPoolGetPage(pPool, pPml4eDst->u & X86_PML4E_PG_MASK);
3783	GCPhysPdptSrc = PGM_A20_APPLY(pVCpu, pPml4eSrc->u & X86_PML4E_PG_MASK);
3784
3785	if (pPml4eSrc->n.u1Present != pPml4eDst->n.u1Present)
3786	{
3787	AssertMsgFailed(("Present bit doesn't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3788	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3789	cErrors++;
3790	continue;
3791	}
3792
3793	if (GCPhysPdptSrc != pShwPdpt->GCPhys)
3794	{
3795	AssertMsgFailed(("Physical address doesn't match! iPml4 %d pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, pPml4eDst->u, pPml4eSrc->u, pShwPdpt->GCPhys, GCPhysPdptSrc));
3796	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3797	cErrors++;
3798	continue;
3799	}
3800
3801	if ( pPml4eDst->n.u1User != pPml4eSrc->n.u1User
3802	\|\| pPml4eDst->n.u1Write != pPml4eSrc->n.u1Write
3803	\|\| pPml4eDst->n.u1NoExecute != pPml4eSrc->n.u1NoExecute)
3804	{
3805	AssertMsgFailed(("User/Write/NoExec bits don't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3806	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3807	cErrors++;
3808	continue;
3809	}
3810	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
3811	{
3812	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
3813
3814	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
3815	/*
3816	* Check the PDPTEs too.
3817	*/
3818	unsigned iPdpt = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
3819
3820	for (;iPdpt <= SHW_PDPT_MASK; iPdpt++)
3821	{
3822	unsigned iPDSrc = 0; /* initialized to shut up gcc */
3823	PPGMPOOLPAGE pShwPde = NULL;
3824	PX86PDPE pPdpeDst;
3825	RTGCPHYS GCPhysPdeSrc;
3826	X86PDPE PdpeSrc;
3827	PdpeSrc.u = 0; /* initialized to shut up gcc 4.5 */
3828	# if PGM_GST_TYPE == PGM_TYPE_PAE
3829	PGSTPD pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtr, &iPDSrc, &PdpeSrc);
3830	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(pVCpu);
3831	# else
3832	PX86PML4E pPml4eSrcIgn;
3833	PX86PDPT pPdptDst;
3834	PX86PDPAE pPDDst;
3835	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtr, &pPml4eSrcIgn, &PdpeSrc, &iPDSrc);
3836
3837	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtr, NULL, &pPdptDst, &pPDDst);
3838	if (rc != VINF_SUCCESS)
3839	{
3840	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
3841	GCPtr += 512 * _2M;
3842	continue; /* next PDPTE */
3843	}
3844	Assert(pPDDst);
3845	# endif
3846	Assert(iPDSrc == 0);
3847
3848	pPdpeDst = &pPdptDst->a[iPdpt];
3849
3850	if (!pPdpeDst->n.u1Present)
3851	{
3852	GCPtr += 512 * _2M;
3853	continue; /* next PDPTE */
3854	}
3855
3856	pShwPde = pgmPoolGetPage(pPool, pPdpeDst->u & X86_PDPE_PG_MASK);
3857	GCPhysPdeSrc = PGM_A20_APPLY(pVCpu, PdpeSrc.u & X86_PDPE_PG_MASK);
3858
3859	if (pPdpeDst->n.u1Present != PdpeSrc.n.u1Present)
3860	{
3861	AssertMsgFailed(("Present bit doesn't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3862	GCPtr += 512 * _2M;
3863	cErrors++;
3864	continue;
3865	}
3866
3867	if (GCPhysPdeSrc != pShwPde->GCPhys)
3868	{
3869	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3870	AssertMsgFailed(("Physical address doesn't match! iPml4 %d iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3871	# else
3872	AssertMsgFailed(("Physical address doesn't match! iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3873	# endif
3874	GCPtr += 512 * _2M;
3875	cErrors++;
3876	continue;
3877	}
3878
3879	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3880	if ( pPdpeDst->lm.u1User != PdpeSrc.lm.u1User
3881	\|\| pPdpeDst->lm.u1Write != PdpeSrc.lm.u1Write
3882	\|\| pPdpeDst->lm.u1NoExecute != PdpeSrc.lm.u1NoExecute)
3883	{
3884	AssertMsgFailed(("User/Write/NoExec bits don't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3885	GCPtr += 512 * _2M;
3886	cErrors++;
3887	continue;
3888	}
3889	# endif
3890
3891	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
3892	{
3893	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
3894	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3895	GSTPD const *pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
3896	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3897	PCX86PD pPDDst = pgmShwGet32BitPDPtr(pVCpu);
3898	# endif
3899	# endif /* PGM_GST_TYPE == PGM_TYPE_32BIT */
3900	/*
3901	* Iterate the shadow page directory.
3902	*/
3903	GCPtr = (GCPtr >> SHW_PD_SHIFT) << SHW_PD_SHIFT;
3904	unsigned iPDDst = (GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK;
3905
3906	for (;
3907	iPDDst < cPDEs;
3908	iPDDst++, GCPtr += cIncrement)
3909	{
3910	# if PGM_SHW_TYPE == PGM_TYPE_PAE
3911	const SHWPDE PdeDst = *pgmShwGetPaePDEPtr(pVCpu, GCPtr);
3912	# else
3913	const SHWPDE PdeDst = pPDDst->a[iPDDst];
3914	# endif
3915	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
3916	{
3917	Assert(pgmMapAreMappingsEnabled(pVM));
3918	if ((PdeDst.u & X86_PDE_AVL_MASK) != PGM_PDFLAGS_MAPPING)
3919	{
3920	AssertMsgFailed(("Mapping shall only have PGM_PDFLAGS_MAPPING set! PdeDst.u=%#RX64\n", (uint64_t)PdeDst.u));
3921	cErrors++;
3922	continue;
3923	}
3924	}
3925	else if ( (PdeDst.u & X86_PDE_P)
3926	\|\| ((PdeDst.u & (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY)) == (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY))
3927	)
3928	{
3929	HCPhysShw = PdeDst.u & SHW_PDE_PG_MASK;
3930	PPGMPOOLPAGE pPoolPage = pgmPoolGetPage(pPool, HCPhysShw);
3931	if (!pPoolPage)
3932	{
3933	AssertMsgFailed(("Invalid page table address %RHp at %RGv! PdeDst=%#RX64\n",
3934	HCPhysShw, GCPtr, (uint64_t)PdeDst.u));
3935	cErrors++;
3936	continue;
3937	}
3938	const SHWPT pPTDst = (const SHWPT )PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pPoolPage);
3939
3940	if (PdeDst.u & (X86_PDE4M_PWT \| X86_PDE4M_PCD))
3941	{
3942	AssertMsgFailed(("PDE flags PWT and/or PCD is set at %RGv! These flags are not virtualized! PdeDst=%#RX64\n",
3943	GCPtr, (uint64_t)PdeDst.u));
3944	cErrors++;
3945	}
3946
3947	if (PdeDst.u & (X86_PDE4M_G \| X86_PDE4M_D))
3948	{
3949	AssertMsgFailed(("4K PDE reserved flags at %RGv! PdeDst=%#RX64\n",
3950	GCPtr, (uint64_t)PdeDst.u));
3951	cErrors++;
3952	}
3953
3954	const GSTPDE PdeSrc = pPDSrc->a[(iPDDst >> (GST_PD_SHIFT - SHW_PD_SHIFT)) & GST_PD_MASK];
3955	if (!PdeSrc.n.u1Present)
3956	{
3957	AssertMsgFailed(("Guest PDE at %RGv is not present! PdeDst=%#RX64 PdeSrc=%#RX64\n",
3958	GCPtr, (uint64_t)PdeDst.u, (uint64_t)PdeSrc.u));
3959	cErrors++;
3960	continue;
3961	}
3962
3963	if ( !PdeSrc.b.u1Size
3964	\|\| !fBigPagesSupported)
3965	{
3966	GCPhysGst = GST_GET_PDE_GCPHYS(PdeSrc);
3967	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3968	GCPhysGst = PGM_A20_APPLY(pVCpu, GCPhysGst \| ((iPDDst & 1) * (PAGE_SIZE / 2)));
3969	# endif
3970	}
3971	else
3972	{
3973	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3974	if (PdeSrc.u & X86_PDE4M_PG_HIGH_MASK)
3975	{
3976	AssertMsgFailed(("Guest PDE at %RGv is using PSE36 or similar! PdeSrc=%#RX64\n",
3977	GCPtr, (uint64_t)PdeSrc.u));
3978	cErrors++;
3979	continue;
3980	}
3981	# endif
3982	GCPhysGst = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
3983	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3984	GCPhysGst = PGM_A20_APPLY(pVCpu, GCPhysGst \| (GCPtr & RT_BIT(X86_PAGE_2M_SHIFT)));
3985	# endif
3986	}
3987
3988	if ( pPoolPage->enmKind
3989	!= (!PdeSrc.b.u1Size \|\| !fBigPagesSupported ? BTH_PGMPOOLKIND_PT_FOR_PT : BTH_PGMPOOLKIND_PT_FOR_BIG))
3990	{
3991	AssertMsgFailed(("Invalid shadow page table kind %d at %RGv! PdeSrc=%#RX64\n",
3992	pPoolPage->enmKind, GCPtr, (uint64_t)PdeSrc.u));
3993	cErrors++;
3994	}
3995
3996	PPGMPAGE pPhysPage = pgmPhysGetPage(pVM, GCPhysGst);
3997	if (!pPhysPage)
3998	{
3999	AssertMsgFailed(("Cannot find guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
4000	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
4001	cErrors++;
4002	continue;
4003	}
4004
4005	if (GCPhysGst != pPoolPage->GCPhys)
4006	{
4007	AssertMsgFailed(("GCPhysGst=%RGp != pPage->GCPhys=%RGp at %RGv\n",
4008	GCPhysGst, pPoolPage->GCPhys, GCPtr));
4009	cErrors++;
4010	continue;
4011	}
4012
4013	if ( !PdeSrc.b.u1Size
4014	\|\| !fBigPagesSupported)
4015	{
4016	/*
4017	* Page Table.
4018	*/
4019	const GSTPT *pPTSrc;
4020	rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, PGM_A20_APPLY(pVCpu, GCPhysGst & ~(RTGCPHYS)(PAGE_SIZE - 1)),
4021	&pPTSrc);
4022	if (RT_FAILURE(rc))
4023	{
4024	AssertMsgFailed(("Cannot map/convert guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
4025	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
4026	cErrors++;
4027	continue;
4028	}
4029	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/))
4030	!= (PdeDst.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/)))
4031	{
4032	/// @todo We get here a lot on out-of-sync CR3 entries. The access handler should zap them to avoid false alarms here!
4033	// (This problem will go away when/if we shadow multiple CR3s.)
4034	AssertMsgFailed(("4K PDE flags mismatch at %RGv! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4035	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4036	cErrors++;
4037	continue;
4038	}
4039	if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
4040	{
4041	AssertMsgFailed(("4K PDEs cannot have PGM_PDFLAGS_TRACK_DIRTY set! GCPtr=%RGv PdeDst=%#RX64\n",
4042	GCPtr, (uint64_t)PdeDst.u));
4043	cErrors++;
4044	continue;
4045	}
4046
4047	/* iterate the page table. */
4048	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
4049	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
4050	const unsigned offPTSrc = ((GCPtr >> SHW_PD_SHIFT) & 1) * 512;
4051	# else
4052	const unsigned offPTSrc = 0;
4053	# endif
4054	for (unsigned iPT = 0, off = 0;
4055	iPT < RT_ELEMENTS(pPTDst->a);
4056	iPT++, off += PAGE_SIZE)
4057	{
4058	const SHWPTE PteDst = pPTDst->a[iPT];
4059
4060	/* skip not-present and dirty tracked entries. */
4061	if (!(SHW_PTE_GET_U(PteDst) & (X86_PTE_P \| PGM_PTFLAGS_TRACK_DIRTY))) /** @todo deal with ALL handlers and CSAM !P pages! */
4062	continue;
4063	Assert(SHW_PTE_IS_P(PteDst));
4064
4065	const GSTPTE PteSrc = pPTSrc->a[iPT + offPTSrc];
4066	if (!PteSrc.n.u1Present)
4067	{
4068	# ifdef IN_RING3
4069	PGMAssertHandlerAndFlagsInSync(pVM);
4070	DBGFR3PagingDumpEx(pVM->pUVM, pVCpu->idCpu, DBGFPGDMP_FLAGS_CURRENT_CR3 \| DBGFPGDMP_FLAGS_CURRENT_MODE
4071	\| DBGFPGDMP_FLAGS_GUEST \| DBGFPGDMP_FLAGS_HEADER \| DBGFPGDMP_FLAGS_PRINT_CR3,
4072	0, 0, UINT64_MAX, 99, NULL);
4073	# endif
4074	AssertMsgFailed(("Out of sync (!P) PTE at %RGv! PteSrc=%#RX64 PteDst=%#RX64 pPTSrc=%RGv iPTSrc=%x PdeSrc=%x physpte=%RGp\n",
4075	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst), pPTSrc, iPT + offPTSrc, PdeSrc.au32[0],
4076	(uint64_t)GST_GET_PDE_GCPHYS(PdeSrc) + (iPT + offPTSrc) * sizeof(PteSrc)));
4077	cErrors++;
4078	continue;
4079	}
4080
4081	uint64_t fIgnoreFlags = GST_PTE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_G \| X86_PTE_D \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT;
4082	# if 1 /** @todo sync accessed bit properly... */
4083	fIgnoreFlags \|= X86_PTE_A;
4084	# endif
4085
4086	/* match the physical addresses */
4087	HCPhysShw = SHW_PTE_GET_HCPHYS(PteDst);
4088	GCPhysGst = GST_GET_PTE_GCPHYS(PteSrc);
4089
4090	# ifdef IN_RING3
4091	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
4092	if (RT_FAILURE(rc))
4093	{
4094	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4095	{
4096	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
4097	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4098	cErrors++;
4099	continue;
4100	}
4101	}
4102	else if (HCPhysShw != (HCPhys & SHW_PTE_PG_MASK))
4103	{
4104	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4105	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4106	cErrors++;
4107	continue;
4108	}
4109	# endif
4110
4111	pPhysPage = pgmPhysGetPage(pVM, GCPhysGst);
4112	if (!pPhysPage)
4113	{
4114	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
4115	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4116	{
4117	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
4118	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4119	cErrors++;
4120	continue;
4121	}
4122	# endif
4123	if (SHW_PTE_IS_RW(PteDst))
4124	{
4125	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4126	GCPtr + off, GCPhysGst, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4127	cErrors++;
4128	}
4129	fIgnoreFlags \|= X86_PTE_RW;
4130	}
4131	else if (HCPhysShw != PGM_PAGE_GET_HCPHYS(pPhysPage))
4132	{
4133	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp pPhysPage:%R[pgmpage] GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4134	GCPtr + off, HCPhysShw, pPhysPage, GCPhysGst, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4135	cErrors++;
4136	continue;
4137	}
4138
4139	/* flags */
4140	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
4141	{
4142	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
4143	{
4144	if (SHW_PTE_IS_RW(PteDst))
4145	{
4146	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! pPhysPage=%R[pgmpage] PteSrc=%#RX64 PteDst=%#RX64\n",
4147	GCPtr + off, pPhysPage, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4148	cErrors++;
4149	continue;
4150	}
4151	fIgnoreFlags \|= X86_PTE_RW;
4152	}
4153	else
4154	{
4155	if ( SHW_PTE_IS_P(PteDst)
4156	# if PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
4157	&& !PGM_PAGE_IS_MMIO(pPhysPage)
4158	# endif
4159	)
4160	{
4161	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! pPhysPage=%R[pgmpage] PteSrc=%#RX64 PteDst=%#RX64\n",
4162	GCPtr + off, pPhysPage, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4163	cErrors++;
4164	continue;
4165	}
4166	fIgnoreFlags \|= X86_PTE_P;
4167	}
4168	}
4169	else
4170	{
4171	if (!PteSrc.n.u1Dirty && PteSrc.n.u1Write)
4172	{
4173	if (SHW_PTE_IS_RW(PteDst))
4174	{
4175	AssertMsgFailed(("!DIRTY page at %RGv is writable! PteSrc=%#RX64 PteDst=%#RX64\n",
4176	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4177	cErrors++;
4178	continue;
4179	}
4180	if (!SHW_PTE_IS_TRACK_DIRTY(PteDst))
4181	{
4182	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4183	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4184	cErrors++;
4185	continue;
4186	}
4187	if (SHW_PTE_IS_D(PteDst))
4188	{
4189	AssertMsgFailed(("!DIRTY page at %RGv is marked DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4190	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4191	cErrors++;
4192	}
4193	# if 0 /** @todo sync access bit properly... */
4194	if (PteDst.n.u1Accessed != PteSrc.n.u1Accessed)
4195	{
4196	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4197	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4198	cErrors++;
4199	}
4200	fIgnoreFlags \|= X86_PTE_RW;
4201	# else
4202	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4203	# endif
4204	}
4205	else if (SHW_PTE_IS_TRACK_DIRTY(PteDst))
4206	{
4207	/* access bit emulation (not implemented). */
4208	if (PteSrc.n.u1Accessed \|\| SHW_PTE_IS_P(PteDst))
4209	{
4210	AssertMsgFailed(("PGM_PTFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PteSrc=%#RX64 PteDst=%#RX64\n",
4211	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4212	cErrors++;
4213	continue;
4214	}
4215	if (!SHW_PTE_IS_A(PteDst))
4216	{
4217	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PteSrc=%#RX64 PteDst=%#RX64\n",
4218	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4219	cErrors++;
4220	}
4221	fIgnoreFlags \|= X86_PTE_P;
4222	}
4223	# ifdef DEBUG_sandervl
4224	fIgnoreFlags \|= X86_PTE_D \| X86_PTE_A;
4225	# endif
4226	}
4227
4228	if ( (PteSrc.u & ~fIgnoreFlags) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags)
4229	&& (PteSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags)
4230	)
4231	{
4232	AssertMsgFailed(("Flags mismatch at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PteSrc=%#RX64 PteDst=%#RX64\n",
4233	GCPtr + off, (uint64_t)PteSrc.u & ~fIgnoreFlags, SHW_PTE_LOG64(PteDst) & ~fIgnoreFlags,
4234	fIgnoreFlags, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4235	cErrors++;
4236	continue;
4237	}
4238	} /* foreach PTE */
4239	}
4240	else
4241	{
4242	/*
4243	* Big Page.
4244	*/
4245	uint64_t fIgnoreFlags = X86_PDE_AVL_MASK \| GST_PDE_PG_MASK \| X86_PDE4M_G \| X86_PDE4M_D \| X86_PDE4M_PS \| X86_PDE4M_PWT \| X86_PDE4M_PCD;
4246	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
4247	{
4248	if (PdeDst.n.u1Write)
4249	{
4250	AssertMsgFailed(("!DIRTY page at %RGv is writable! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4251	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4252	cErrors++;
4253	continue;
4254	}
4255	if (!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY))
4256	{
4257	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4258	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4259	cErrors++;
4260	continue;
4261	}
4262	# if 0 /** @todo sync access bit properly... */
4263	if (PdeDst.n.u1Accessed != PdeSrc.b.u1Accessed)
4264	{
4265	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4266	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4267	cErrors++;
4268	}
4269	fIgnoreFlags \|= X86_PTE_RW;
4270	# else
4271	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4272	# endif
4273	}
4274	else if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
4275	{
4276	/* access bit emulation (not implemented). */
4277	if (PdeSrc.b.u1Accessed \|\| PdeDst.n.u1Present)
4278	{
4279	AssertMsgFailed(("PGM_PDFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4280	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4281	cErrors++;
4282	continue;
4283	}
4284	if (!PdeDst.n.u1Accessed)
4285	{
4286	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4287	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4288	cErrors++;
4289	}
4290	fIgnoreFlags \|= X86_PTE_P;
4291	}
4292
4293	if ((PdeSrc.u & ~fIgnoreFlags) != (PdeDst.u & ~fIgnoreFlags))
4294	{
4295	AssertMsgFailed(("Flags mismatch (B) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PdeDst=%#RX64\n",
4296	GCPtr, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PdeDst.u & ~fIgnoreFlags,
4297	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4298	cErrors++;
4299	}
4300
4301	/* iterate the page table. */
4302	for (unsigned iPT = 0, off = 0;
4303	iPT < RT_ELEMENTS(pPTDst->a);
4304	iPT++, off += PAGE_SIZE, GCPhysGst = PGM_A20_APPLY(pVCpu, GCPhysGst + PAGE_SIZE))
4305	{
4306	const SHWPTE PteDst = pPTDst->a[iPT];
4307
4308	if (SHW_PTE_IS_TRACK_DIRTY(PteDst))
4309	{
4310	AssertMsgFailed(("The PTE at %RGv emulating a 2/4M page is marked TRACK_DIRTY! PdeSrc=%#RX64 PteDst=%#RX64\n",
4311	GCPtr + off, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4312	cErrors++;
4313	}
4314
4315	/* skip not-present entries. */
4316	if (!SHW_PTE_IS_P(PteDst)) /** @todo deal with ALL handlers and CSAM !P pages! */
4317	continue;
4318
4319	fIgnoreFlags = X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT \| X86_PTE_D \| X86_PTE_A \| X86_PTE_G \| X86_PTE_PAE_NX;
4320
4321	/* match the physical addresses */
4322	HCPhysShw = SHW_PTE_GET_HCPHYS(PteDst);
4323
4324	# ifdef IN_RING3
4325	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
4326	if (RT_FAILURE(rc))
4327	{
4328	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4329	{
4330	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4331	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4332	cErrors++;
4333	}
4334	}
4335	else if (HCPhysShw != (HCPhys & X86_PTE_PAE_PG_MASK))
4336	{
4337	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4338	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4339	cErrors++;
4340	continue;
4341	}
4342	# endif
4343	pPhysPage = pgmPhysGetPage(pVM, GCPhysGst);
4344	if (!pPhysPage)
4345	{
4346	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
4347	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4348	{
4349	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4350	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4351	cErrors++;
4352	continue;
4353	}
4354	# endif
4355	if (SHW_PTE_IS_RW(PteDst))
4356	{
4357	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4358	GCPtr + off, GCPhysGst, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4359	cErrors++;
4360	}
4361	fIgnoreFlags \|= X86_PTE_RW;
4362	}
4363	else if (HCPhysShw != PGM_PAGE_GET_HCPHYS(pPhysPage))
4364	{
4365	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp pPhysPage=%R[pgmpage] GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4366	GCPtr + off, HCPhysShw, pPhysPage, GCPhysGst, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4367	cErrors++;
4368	continue;
4369	}
4370
4371	/* flags */
4372	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
4373	{
4374	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
4375	{
4376	if (PGM_PAGE_GET_HNDL_PHYS_STATE(pPhysPage) != PGM_PAGE_HNDL_PHYS_STATE_DISABLED)
4377	{
4378	if (SHW_PTE_IS_RW(PteDst))
4379	{
4380	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! pPhysPage=%R[pgmpage] PdeSrc=%#RX64 PteDst=%#RX64\n",
4381	GCPtr + off, pPhysPage, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4382	cErrors++;
4383	continue;
4384	}
4385	fIgnoreFlags \|= X86_PTE_RW;
4386	}
4387	}
4388	else
4389	{
4390	if ( SHW_PTE_IS_P(PteDst)
4391	# if PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
4392	&& !PGM_PAGE_IS_MMIO(pPhysPage)
4393	# endif
4394	)
4395	{
4396	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! pPhysPage=%R[pgmpage] PdeSrc=%#RX64 PteDst=%#RX64\n",
4397	GCPtr + off, pPhysPage, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4398	cErrors++;
4399	continue;
4400	}
4401	fIgnoreFlags \|= X86_PTE_P;
4402	}
4403	}
4404
4405	if ( (PdeSrc.u & ~fIgnoreFlags) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags)
4406	&& (PdeSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags) /* lazy phys handler dereg. */
4407	)
4408	{
4409	AssertMsgFailed(("Flags mismatch (BT) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PteDst=%#RX64\n",
4410	GCPtr + off, (uint64_t)PdeSrc.u & ~fIgnoreFlags, SHW_PTE_LOG64(PteDst) & ~fIgnoreFlags,
4411	fIgnoreFlags, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4412	cErrors++;
4413	continue;
4414	}
4415	} /* for each PTE */
4416	}
4417	}
4418	/* not present */
4419
4420	} /* for each PDE */
4421
4422	} /* for each PDPTE */
4423
4424	} /* for each PML4E */
4425
4426	# ifdef DEBUG
4427	if (cErrors)
4428	LogFlow(("AssertCR3: cErrors=%d\n", cErrors));
4429	# endif
4430	# endif /* GST is in {32BIT, PAE, AMD64} */
4431	return cErrors;
4432	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT */
4433	}
4434	#endif /* VBOX_STRICT */
4435
4436
4437	/**
4438	* Sets up the CR3 for shadow paging
4439	*
4440	* @returns Strict VBox status code.
4441	* @retval VINF_SUCCESS.
4442	*
4443	* @param pVCpu Pointer to the VMCPU.
4444	* @param GCPhysCR3 The physical address in the CR3 register. (A20
4445	* mask already applied.)
4446	*/
4447	PGM_BTH_DECL(int, MapCR3)(PVMCPU pVCpu, RTGCPHYS GCPhysCR3)
4448	{
4449	PVM pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
4450
4451	/* Update guest paging info. */
4452	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
4453	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
4454	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
4455
4456	LogFlow(("MapCR3: %RGp\n", GCPhysCR3));
4457	PGM_A20_ASSERT_MASKED(pVCpu, GCPhysCR3);
4458
4459	/*
4460	* Map the page CR3 points at.
4461	*/
4462	RTHCPTR HCPtrGuestCR3;
4463	RTHCPHYS HCPhysGuestCR3;
4464	pgmLock(pVM);
4465	PPGMPAGE pPageCR3 = pgmPhysGetPage(pVM, GCPhysCR3);
4466	AssertReturn(pPageCR3, VERR_PGM_INVALID_CR3_ADDR);
4467	HCPhysGuestCR3 = PGM_PAGE_GET_HCPHYS(pPageCR3);
4468	/** @todo this needs some reworking wrt. locking? */
4469	# if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
4470	HCPtrGuestCR3 = NIL_RTHCPTR;
4471	int rc = VINF_SUCCESS;
4472	# else
4473	int rc = pgmPhysGCPhys2CCPtrInternalDepr(pVM, pPageCR3, GCPhysCR3 & GST_CR3_PAGE_MASK, (void )&HCPtrGuestCR3); / @todo r=bird: This GCPhysCR3 masking isn't necessary. */
4474	# endif
4475	pgmUnlock(pVM);
4476	if (RT_SUCCESS(rc))
4477	{
4478	rc = PGMMap(pVM, (RTGCPTR)pVM->pgm.s.GCPtrCR3Mapping, HCPhysGuestCR3, PAGE_SIZE, 0);
4479	if (RT_SUCCESS(rc))
4480	{
4481	# ifdef IN_RC
4482	PGM_INVL_PG(pVCpu, pVM->pgm.s.GCPtrCR3Mapping);
4483	# endif
4484	# if PGM_GST_TYPE == PGM_TYPE_32BIT
4485	pVCpu->pgm.s.pGst32BitPdR3 = (R3PTRTYPE(PX86PD))HCPtrGuestCR3;
4486	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4487	pVCpu->pgm.s.pGst32BitPdR0 = (R0PTRTYPE(PX86PD))HCPtrGuestCR3;
4488	# endif
4489	pVCpu->pgm.s.pGst32BitPdRC = (RCPTRTYPE(PX86PD))(RTRCUINTPTR)pVM->pgm.s.GCPtrCR3Mapping;
4490
4491	# elif PGM_GST_TYPE == PGM_TYPE_PAE
4492	unsigned off = GCPhysCR3 & GST_CR3_PAGE_MASK & PAGE_OFFSET_MASK;
4493	pVCpu->pgm.s.pGstPaePdptR3 = (R3PTRTYPE(PX86PDPT))HCPtrGuestCR3;
4494	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4495	pVCpu->pgm.s.pGstPaePdptR0 = (R0PTRTYPE(PX86PDPT))HCPtrGuestCR3;
4496	# endif
4497	pVCpu->pgm.s.pGstPaePdptRC = (RCPTRTYPE(PX86PDPT))((RTRCUINTPTR)pVM->pgm.s.GCPtrCR3Mapping + off);
4498	LogFlow(("Cached mapping %RRv\n", pVCpu->pgm.s.pGstPaePdptRC));
4499
4500	/*
4501	* Map the 4 PDs too.
4502	*/
4503	PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pVCpu);
4504	RTGCPTR GCPtr = pVM->pgm.s.GCPtrCR3Mapping + PAGE_SIZE;
4505	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++, GCPtr += PAGE_SIZE)
4506	{
4507	pVCpu->pgm.s.aGstPaePdpeRegs[i].u = pGuestPDPT->a[i].u;
4508	if (pGuestPDPT->a[i].n.u1Present)
4509	{
4510	RTHCPTR HCPtr;
4511	RTHCPHYS HCPhys;
4512	RTGCPHYS GCPhys = PGM_A20_APPLY(pVCpu, pGuestPDPT->a[i].u & X86_PDPE_PG_MASK);
4513	pgmLock(pVM);
4514	PPGMPAGE pPage = pgmPhysGetPage(pVM, GCPhys);
4515	AssertReturn(pPage, VERR_PGM_INVALID_PDPE_ADDR);
4516	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
4517	# if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
4518	HCPtr = NIL_RTHCPTR;
4519	int rc2 = VINF_SUCCESS;
4520	# else
4521	int rc2 = pgmPhysGCPhys2CCPtrInternalDepr(pVM, pPage, GCPhys, (void **)&HCPtr);
4522	# endif
4523	pgmUnlock(pVM);
4524	if (RT_SUCCESS(rc2))
4525	{
4526	rc = PGMMap(pVM, GCPtr, HCPhys, PAGE_SIZE, 0);
4527	AssertRCReturn(rc, rc);
4528
4529	pVCpu->pgm.s.apGstPaePDsR3[i] = (R3PTRTYPE(PX86PDPAE))HCPtr;
4530	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4531	pVCpu->pgm.s.apGstPaePDsR0[i] = (R0PTRTYPE(PX86PDPAE))HCPtr;
4532	# endif
4533	pVCpu->pgm.s.apGstPaePDsRC[i] = (RCPTRTYPE(PX86PDPAE))(RTRCUINTPTR)GCPtr;
4534	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = GCPhys;
4535	# ifdef IN_RC
4536	PGM_INVL_PG(pVCpu, GCPtr);
4537	# endif
4538	continue;
4539	}
4540	AssertMsgFailed(("pgmR3Gst32BitMapCR3: rc2=%d GCPhys=%RGp i=%d\n", rc2, GCPhys, i));
4541	}
4542
4543	pVCpu->pgm.s.apGstPaePDsR3[i] = 0;
4544	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4545	pVCpu->pgm.s.apGstPaePDsR0[i] = 0;
4546	# endif
4547	pVCpu->pgm.s.apGstPaePDsRC[i] = 0;
4548	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
4549	# ifdef IN_RC
4550	PGM_INVL_PG(pVCpu, GCPtr); /** @todo this shouldn't be necessary? */
4551	# endif
4552	}
4553
4554	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
4555	pVCpu->pgm.s.pGstAmd64Pml4R3 = (R3PTRTYPE(PX86PML4))HCPtrGuestCR3;
4556	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4557	pVCpu->pgm.s.pGstAmd64Pml4R0 = (R0PTRTYPE(PX86PML4))HCPtrGuestCR3;
4558	# endif
4559	# endif
4560	}
4561	else
4562	AssertMsgFailed(("rc=%Rrc GCPhysGuestPD=%RGp\n", rc, GCPhysCR3));
4563	}
4564	else
4565	AssertMsgFailed(("rc=%Rrc GCPhysGuestPD=%RGp\n", rc, GCPhysCR3));
4566
4567	#else /* prot/real stub */
4568	int rc = VINF_SUCCESS;
4569	#endif
4570
4571	/* Update shadow paging info for guest modes with paging (32, pae, 64). */
4572	# if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
4573	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
4574	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64) \
4575	&& ( PGM_GST_TYPE != PGM_TYPE_REAL \
4576	&& PGM_GST_TYPE != PGM_TYPE_PROT))
4577
4578	Assert(!pVM->pgm.s.fNestedPaging);
4579	PGM_A20_ASSERT_MASKED(pVCpu, GCPhysCR3);
4580
4581	/*
4582	* Update the shadow root page as well since that's not fixed.
4583	*/
4584	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4585	PPGMPOOLPAGE pOldShwPageCR3 = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
4586	PPGMPOOLPAGE pNewShwPageCR3;
4587
4588	pgmLock(pVM);
4589
4590	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
4591	if (pPool->cDirtyPages)
4592	pgmPoolResetDirtyPages(pVM);
4593	# endif
4594
4595	Assert(!(GCPhysCR3 >> (PAGE_SHIFT + 32)));
4596	rc = pgmPoolAlloc(pVM, GCPhysCR3 & GST_CR3_PAGE_MASK, BTH_PGMPOOLKIND_ROOT, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
4597	NIL_PGMPOOL_IDX, UINT32_MAX, true /fLockPage/,
4598	&pNewShwPageCR3);
4599	AssertFatalRC(rc);
4600	rc = VINF_SUCCESS;
4601
4602	# ifdef IN_RC
4603	/*
4604	* WARNING! We can't deal with jumps to ring 3 in the code below as the
4605	* state will be inconsistent! Flush important things now while
4606	* we still can and then make sure there are no ring-3 calls.
4607	*/
4608	# ifdef VBOX_WITH_REM
4609	REMNotifyHandlerPhysicalFlushIfAlmostFull(pVM, pVCpu);
4610	# endif
4611	VMMRZCallRing3Disable(pVCpu);
4612	# endif
4613
4614	pVCpu->pgm.s.CTX_SUFF(pShwPageCR3) = pNewShwPageCR3;
4615	# ifdef IN_RING0
4616	pVCpu->pgm.s.pShwPageCR3R3 = MMHyperCCToR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4617	pVCpu->pgm.s.pShwPageCR3RC = MMHyperCCToRC(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4618	# elif defined(IN_RC)
4619	pVCpu->pgm.s.pShwPageCR3R3 = MMHyperCCToR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4620	pVCpu->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4621	# else
4622	pVCpu->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4623	pVCpu->pgm.s.pShwPageCR3RC = MMHyperCCToRC(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4624	# endif
4625
4626	# ifndef PGM_WITHOUT_MAPPINGS
4627	/*
4628	* Apply all hypervisor mappings to the new CR3.
4629	* Note that SyncCR3 will be executed in case CR3 is changed in a guest paging mode; this will
4630	* make sure we check for conflicts in the new CR3 root.
4631	*/
4632	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
4633	Assert(VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL) \|\| VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
4634	# endif
4635	rc = pgmMapActivateCR3(pVM, pNewShwPageCR3);
4636	AssertRCReturn(rc, rc);
4637	# endif
4638
4639	/* Set the current hypervisor CR3. */
4640	CPUMSetHyperCR3(pVCpu, PGMGetHyperCR3(pVCpu));
4641	SELMShadowCR3Changed(pVM, pVCpu);
4642
4643	# ifdef IN_RC
4644	/* NOTE: The state is consistent again. */
4645	VMMRZCallRing3Enable(pVCpu);
4646	# endif
4647
4648	/* Clean up the old CR3 root. */
4649	if ( pOldShwPageCR3
4650	&& pOldShwPageCR3 != pNewShwPageCR3 /* @todo can happen due to incorrect syncing between REM & PGM; find the real cause */)
4651	{
4652	Assert(pOldShwPageCR3->enmKind != PGMPOOLKIND_FREE);
4653	# ifndef PGM_WITHOUT_MAPPINGS
4654	/* Remove the hypervisor mappings from the shadow page table. */
4655	pgmMapDeactivateCR3(pVM, pOldShwPageCR3);
4656	# endif
4657	/* Mark the page as unlocked; allow flushing again. */
4658	pgmPoolUnlockPage(pPool, pOldShwPageCR3);
4659
4660	pgmPoolFreeByPage(pPool, pOldShwPageCR3, NIL_PGMPOOL_IDX, UINT32_MAX);
4661	}
4662	pgmUnlock(pVM);
4663	# else
4664	NOREF(GCPhysCR3);
4665	# endif
4666
4667	return rc;
4668	}
4669
4670	/**
4671	* Unmaps the shadow CR3.
4672	*
4673	* @returns VBox status, no specials.
4674	* @param pVCpu Pointer to the VMCPU.
4675	*/
4676	PGM_BTH_DECL(int, UnmapCR3)(PVMCPU pVCpu)
4677	{
4678	LogFlow(("UnmapCR3\n"));
4679
4680	int rc = VINF_SUCCESS;
4681	PVM pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
4682
4683	/*
4684	* Update guest paging info.
4685	*/
4686	#if PGM_GST_TYPE == PGM_TYPE_32BIT
4687	pVCpu->pgm.s.pGst32BitPdR3 = 0;
4688	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4689	pVCpu->pgm.s.pGst32BitPdR0 = 0;
4690	# endif
4691	pVCpu->pgm.s.pGst32BitPdRC = 0;
4692
4693	#elif PGM_GST_TYPE == PGM_TYPE_PAE
4694	pVCpu->pgm.s.pGstPaePdptR3 = 0;
4695	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4696	pVCpu->pgm.s.pGstPaePdptR0 = 0;
4697	# endif
4698	pVCpu->pgm.s.pGstPaePdptRC = 0;
4699	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
4700	{
4701	pVCpu->pgm.s.apGstPaePDsR3[i] = 0;
4702	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4703	pVCpu->pgm.s.apGstPaePDsR0[i] = 0;
4704	# endif
4705	pVCpu->pgm.s.apGstPaePDsRC[i] = 0;
4706	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
4707	}
4708
4709	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
4710	pVCpu->pgm.s.pGstAmd64Pml4R3 = 0;
4711	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4712	pVCpu->pgm.s.pGstAmd64Pml4R0 = 0;
4713	# endif
4714
4715	#else /* prot/real mode stub */
4716	/* nothing to do */
4717	#endif
4718
4719	#if !defined(IN_RC) /* In RC we rely on MapCR3 to do the shadow part for us at a safe time */
4720	/*
4721	* Update shadow paging info.
4722	*/
4723	# if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
4724	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
4725	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64))
4726
4727	# if PGM_GST_TYPE != PGM_TYPE_REAL
4728	Assert(!pVM->pgm.s.fNestedPaging);
4729	# endif
4730
4731	pgmLock(pVM);
4732
4733	# ifndef PGM_WITHOUT_MAPPINGS
4734	if (pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
4735	/* Remove the hypervisor mappings from the shadow page table. */
4736	pgmMapDeactivateCR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4737	# endif
4738
4739	if (pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
4740	{
4741	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4742
4743	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
4744	if (pPool->cDirtyPages)
4745	pgmPoolResetDirtyPages(pVM);
4746	# endif
4747
4748	/* Mark the page as unlocked; allow flushing again. */
4749	pgmPoolUnlockPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4750
4751	pgmPoolFreeByPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3), NIL_PGMPOOL_IDX, UINT32_MAX);
4752	pVCpu->pgm.s.pShwPageCR3R3 = 0;
4753	pVCpu->pgm.s.pShwPageCR3R0 = 0;
4754	pVCpu->pgm.s.pShwPageCR3RC = 0;
4755	}
4756	pgmUnlock(pVM);
4757	# endif
4758	#endif /* !IN_RC*/
4759
4760	return rc;
4761	}

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllBth.h@ 45548

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