VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllBth.h@ 47996

Last change on this file since 47996 was 46420, checked in by vboxsync, 12 years ago

VMM, recompiler: Purge deprecated macros.

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1/* $Id: PGMAllBth.h 46420 2013-06-06 16:27:25Z vboxsync $ */
2/** @file
3 * VBox - Page Manager, Shadow+Guest Paging Template - All context code.
4 *
5 * @remarks The nested page tables on AMD makes use of PGM_SHW_TYPE in
6 * {PGM_TYPE_AMD64, PGM_TYPE_PAE and PGM_TYPE_32BIT} and PGM_GST_TYPE
7 * set to PGM_TYPE_PROT. Half of the code in this file is not
8 * exercised with PGM_SHW_TYPE set to PGM_TYPE_NESTED.
9 *
10 * @remarks Extended page tables (intel) are built with PGM_GST_TYPE set to
11 * PGM_TYPE_PROT (and PGM_SHW_TYPE set to PGM_TYPE_EPT).
12 *
13 * @remarks This file is one big \#ifdef-orgy!
14 *
15 */
16
17/*
18 * Copyright (C) 2006-2013 Oracle Corporation
19 *
20 * This file is part of VirtualBox Open Source Edition (OSE), as
21 * available from http://www.virtualbox.org. This file is free software;
22 * you can redistribute it and/or modify it under the terms of the GNU
23 * General Public License (GPL) as published by the Free Software
24 * Foundation, in version 2 as it comes in the "COPYING" file of the
25 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
26 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
27 */
28
29#ifdef _MSC_VER
30/** @todo we're generating unnecessary code in nested/ept shadow mode and for
31 * real/prot-guest+RC mode. */
32# pragma warning(disable: 4505)
33#endif
34
35/*******************************************************************************
36* Internal Functions *
37*******************************************************************************/
38RT_C_DECLS_BEGIN
39PGM_BTH_DECL(int, Trap0eHandler)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken);
40PGM_BTH_DECL(int, InvalidatePage)(PVMCPU pVCpu, RTGCPTR GCPtrPage);
41static int PGM_BTH_NAME(SyncPage)(PVMCPU pVCpu, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr);
42static int PGM_BTH_NAME(CheckDirtyPageFault)(PVMCPU pVCpu, uint32_t uErr, PSHWPDE pPdeDst, GSTPDE const *pPdeSrc, RTGCPTR GCPtrPage);
43static int PGM_BTH_NAME(SyncPT)(PVMCPU pVCpu, unsigned iPD, PGSTPD pPDSrc, RTGCPTR GCPtrPage);
44# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
45static void PGM_BTH_NAME(SyncPageWorker)(PVMCPU pVCpu, PSHWPTE pPteDst, GSTPDE PdeSrc, GSTPTE PteSrc, PPGMPOOLPAGE pShwPage, unsigned iPTDst);
46# else
47static void PGM_BTH_NAME(SyncPageWorker)(PVMCPU pVCpu, PSHWPTE pPteDst, RTGCPHYS GCPhysPage, PPGMPOOLPAGE pShwPage, unsigned iPTDst);
48#endif
49PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVMCPU pVCpu, RTGCPTR Addr, unsigned fPage, unsigned uErr);
50PGM_BTH_DECL(int, PrefetchPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage);
51PGM_BTH_DECL(int, SyncCR3)(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
52#ifdef VBOX_STRICT
53PGM_BTH_DECL(unsigned, AssertCR3)(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr = 0, RTGCPTR cb = ~(RTGCPTR)0);
54#endif
55PGM_BTH_DECL(int, MapCR3)(PVMCPU pVCpu, RTGCPHYS GCPhysCR3);
56PGM_BTH_DECL(int, UnmapCR3)(PVMCPU pVCpu);
57RT_C_DECLS_END
58
59
60/*
61 * Filter out some illegal combinations of guest and shadow paging, so we can
62 * remove redundant checks inside functions.
63 */
64#if PGM_GST_TYPE == PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
65# error "Invalid combination; PAE guest implies PAE shadow"
66#endif
67
68#if (PGM_GST_TYPE == PGM_TYPE_REAL || PGM_GST_TYPE == PGM_TYPE_PROT) \
69 && !(PGM_SHW_TYPE == PGM_TYPE_32BIT || PGM_SHW_TYPE == PGM_TYPE_PAE || PGM_SHW_TYPE == PGM_TYPE_AMD64 || PGM_SHW_TYPE == PGM_TYPE_NESTED || PGM_SHW_TYPE == PGM_TYPE_EPT)
70# error "Invalid combination; real or protected mode without paging implies 32 bits or PAE shadow paging."
71#endif
72
73#if (PGM_GST_TYPE == PGM_TYPE_32BIT || PGM_GST_TYPE == PGM_TYPE_PAE) \
74 && !(PGM_SHW_TYPE == PGM_TYPE_32BIT || PGM_SHW_TYPE == PGM_TYPE_PAE || PGM_SHW_TYPE == PGM_TYPE_NESTED || PGM_SHW_TYPE == PGM_TYPE_EPT)
75# error "Invalid combination; 32 bits guest paging or PAE implies 32 bits or PAE shadow paging."
76#endif
77
78#if (PGM_GST_TYPE == PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT) \
79 || (PGM_SHW_TYPE == PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PROT)
80# error "Invalid combination; AMD64 guest implies AMD64 shadow and vice versa"
81#endif
82
83#ifndef IN_RING3
84
85# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
86/**
87 * Deal with a guest page fault.
88 *
89 * @returns Strict VBox status code.
90 * @retval VINF_EM_RAW_GUEST_TRAP
91 * @retval VINF_EM_RAW_EMULATE_INSTR
92 *
93 * @param pVCpu The current CPU.
94 * @param pGstWalk The guest page table walk result.
95 * @param uErr The error code.
96 */
97PGM_BTH_DECL(VBOXSTRICTRC, Trap0eHandlerGuestFault)(PVMCPU pVCpu, PGSTPTWALK pGstWalk, RTGCUINT uErr)
98{
99# if !defined(PGM_WITHOUT_MAPPINGS) && (PGM_GST_TYPE == PGM_TYPE_32BIT || PGM_GST_TYPE == PGM_TYPE_PAE)
100 /*
101 * Check for write conflicts with our hypervisor mapping.
102 *
103 * If the guest happens to access a non-present page, where our hypervisor
104 * is currently mapped, then we'll create a #PF storm in the guest.
105 */
106 if ( (uErr & (X86_TRAP_PF_P | X86_TRAP_PF_RW)) == (X86_TRAP_PF_P | X86_TRAP_PF_RW)
107 && pgmMapAreMappingsEnabled(pVCpu->CTX_SUFF(pVM))
108 && MMHyperIsInsideArea(pVCpu->CTX_SUFF(pVM), pGstWalk->Core.GCPtr))
109 {
110 /* Force a CR3 sync to check for conflicts and emulate the instruction. */
111 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
112 STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2GuestTrap; });
113 return VINF_EM_RAW_EMULATE_INSTR;
114 }
115# endif
116
117 /*
118 * Calc the error code for the guest trap.
119 */
120 uint32_t uNewErr = GST_IS_NX_ACTIVE(pVCpu)
121 ? uErr & (X86_TRAP_PF_RW | X86_TRAP_PF_US | X86_TRAP_PF_ID)
122 : uErr & (X86_TRAP_PF_RW | X86_TRAP_PF_US);
123 if (pGstWalk->Core.fBadPhysAddr)
124 {
125 uNewErr |= X86_TRAP_PF_RSVD | X86_TRAP_PF_P;
126 Assert(!pGstWalk->Core.fNotPresent);
127 }
128 else if (!pGstWalk->Core.fNotPresent)
129 uNewErr |= X86_TRAP_PF_P;
130 TRPMSetErrorCode(pVCpu, uNewErr);
131
132 LogFlow(("Guest trap; cr2=%RGv uErr=%RGv lvl=%d\n", pGstWalk->Core.GCPtr, uErr, pGstWalk->Core.uLevel));
133 STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2GuestTrap; });
134 return VINF_EM_RAW_GUEST_TRAP;
135}
136# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
137
138
139/**
140 * Deal with a guest page fault.
141 *
142 * The caller has taken the PGM lock.
143 *
144 * @returns Strict VBox status code.
145 *
146 * @param pVCpu The current CPU.
147 * @param uErr The error code.
148 * @param pRegFrame The register frame.
149 * @param pvFault The fault address.
150 * @param pPage The guest page at @a pvFault.
151 * @param pGstWalk The guest page table walk result.
152 * @param pfLockTaken PGM lock taken here or not (out). This is true
153 * when we're called.
154 */
155static VBOXSTRICTRC PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame,
156 RTGCPTR pvFault, PPGMPAGE pPage, bool *pfLockTaken
157# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
158 , PGSTPTWALK pGstWalk
159# endif
160 )
161{
162# if !PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
163 GSTPDE const PdeSrcDummy = { X86_PDE_P | X86_PDE_US | X86_PDE_RW | X86_PDE_A };
164#endif
165 PVM pVM = pVCpu->CTX_SUFF(pVM);
166 int rc;
167
168 if (PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage))
169 {
170 /*
171 * Physical page access handler.
172 */
173# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
174 const RTGCPHYS GCPhysFault = pGstWalk->Core.GCPhys;
175# else
176 const RTGCPHYS GCPhysFault = PGM_A20_APPLY(pVCpu, (RTGCPHYS)pvFault);
177# endif
178 PPGMPHYSHANDLER pCur = pgmHandlerPhysicalLookup(pVM, GCPhysFault);
179 if (pCur)
180 {
181# ifdef PGM_SYNC_N_PAGES
182 /*
183 * If the region is write protected and we got a page not present fault, then sync
184 * the pages. If the fault was caused by a read, then restart the instruction.
185 * In case of write access continue to the GC write handler.
186 *
187 * ASSUMES that there is only one handler per page or that they have similar write properties.
188 */
189 if ( !(uErr & X86_TRAP_PF_P)
190 && pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE)
191 {
192# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
193 rc = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
194# else
195 rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
196# endif
197 if ( RT_FAILURE(rc)
198 || !(uErr & X86_TRAP_PF_RW)
199 || rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
200 {
201 AssertRC(rc);
202 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersOutOfSync);
203 STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndPhys; });
204 return rc;
205 }
206 }
207# endif
208# ifdef PGM_WITH_MMIO_OPTIMIZATIONS
209 /*
210 * If the access was not thru a #PF(RSVD|...) resync the page.
211 */
212 if ( !(uErr & X86_TRAP_PF_RSVD)
213 && pCur->enmType != PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
214# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
215 && pGstWalk->Core.fEffectiveRW
216 && !pGstWalk->Core.fEffectiveUS /** @todo Remove pGstWalk->Core.fEffectiveUS and X86_PTE_US further down in the sync code. */
217# endif
218 )
219 {
220# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
221 rc = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
222# else
223 rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
224# endif
225 if ( RT_FAILURE(rc)
226 || rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
227 {
228 AssertRC(rc);
229 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersOutOfSync);
230 STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndPhys; });
231 return rc;
232 }
233 }
234# endif
235
236 AssertMsg( pCur->enmType != PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
237 || (pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE && (uErr & X86_TRAP_PF_RW)),
238 ("Unexpected trap for physical handler: %08X (phys=%08x) pPage=%R[pgmpage] uErr=%X, enum=%d\n",
239 pvFault, GCPhysFault, pPage, uErr, pCur->enmType));
240 if (pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE)
241 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersPhysWrite);
242 else
243 {
244 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersPhysAll);
245 if (uErr & X86_TRAP_PF_RSVD) STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersPhysAllOpt);
246 }
247
248 if (pCur->CTX_SUFF(pfnHandler))
249 {
250 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
251 void *pvUser = pCur->CTX_SUFF(pvUser);
252# ifdef IN_RING0
253 PFNPGMR0PHYSHANDLER pfnHandler = pCur->CTX_SUFF(pfnHandler);
254# else
255 PFNPGMRCPHYSHANDLER pfnHandler = pCur->CTX_SUFF(pfnHandler);
256# endif
257
258 STAM_PROFILE_START(&pCur->Stat, h);
259 if (pfnHandler != pPool->CTX_SUFF(pfnAccessHandler))
260 {
261 pgmUnlock(pVM);
262 *pfLockTaken = false;
263 }
264
265 rc = pfnHandler(pVM, uErr, pRegFrame, pvFault, GCPhysFault, pvUser);
266
267# ifdef VBOX_WITH_STATISTICS
268 pgmLock(pVM);
269 pCur = pgmHandlerPhysicalLookup(pVM, GCPhysFault);
270 if (pCur)
271 STAM_PROFILE_STOP(&pCur->Stat, h);
272 pgmUnlock(pVM);
273# endif
274 }
275 else
276 rc = VINF_EM_RAW_EMULATE_INSTR;
277
278 STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndPhys; });
279 return rc;
280 }
281 }
282# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0)
283 else
284 {
285# ifdef PGM_SYNC_N_PAGES
286 /*
287 * If the region is write protected and we got a page not present fault, then sync
288 * the pages. If the fault was caused by a read, then restart the instruction.
289 * In case of write access continue to the GC write handler.
290 */
291 if ( PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) < PGM_PAGE_HNDL_PHYS_STATE_ALL
292 && !(uErr & X86_TRAP_PF_P))
293 {
294 rc = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
295 if ( RT_FAILURE(rc)
296 || rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
297 || !(uErr & X86_TRAP_PF_RW))
298 {
299 AssertRC(rc);
300 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersOutOfSync);
301 STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndVirt; });
302 return rc;
303 }
304 }
305# endif
306 /*
307 * Ok, it's an virtual page access handler.
308 *
309 * Since it's faster to search by address, we'll do that first
310 * and then retry by GCPhys if that fails.
311 */
312 /** @todo r=bird: perhaps we should consider looking up by physical address directly now?
313 * r=svl: true, but lookup on virtual address should remain as a fallback as phys & virt trees might be
314 * out of sync, because the page was changed without us noticing it (not-present -> present
315 * without invlpg or mov cr3, xxx).
316 */
317 PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
318 if (pCur)
319 {
320 AssertMsg(!(pvFault - pCur->Core.Key < pCur->cb)
321 || ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
322 || !(uErr & X86_TRAP_PF_P)
323 || (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
324 ("Unexpected trap for virtual handler: %RGv (phys=%RGp) pPage=%R[pgmpage] uErr=%X, enum=%d\n",
325 pvFault, pGstWalk->Core.GCPhys, pPage, uErr, pCur->enmType));
326
327 if ( pvFault - pCur->Core.Key < pCur->cb
328 && ( uErr & X86_TRAP_PF_RW
329 || pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
330 {
331# ifdef IN_RC
332 STAM_PROFILE_START(&pCur->Stat, h);
333 RTGCPTR GCPtrStart = pCur->Core.Key;
334 CTX_MID(PFNPGM,VIRTHANDLER) pfnHandler = pCur->CTX_SUFF(pfnHandler);
335 pgmUnlock(pVM);
336 *pfLockTaken = false;
337
338 rc = pfnHandler(pVM, uErr, pRegFrame, pvFault, GCPtrStart, pvFault - GCPtrStart);
339
340# ifdef VBOX_WITH_STATISTICS
341 pgmLock(pVM);
342 pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
343 if (pCur)
344 STAM_PROFILE_STOP(&pCur->Stat, h);
345 pgmUnlock(pVM);
346# endif
347# else
348 rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
349# endif
350 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersVirtual);
351 STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndVirt; });
352 return rc;
353 }
354 /* Unhandled part of a monitored page */
355 Log(("Unhandled part of monitored page %RGv\n", pvFault));
356 }
357 else
358 {
359 /* Check by physical address. */
360 unsigned iPage;
361 rc = pgmHandlerVirtualFindByPhysAddr(pVM, pGstWalk->Core.GCPhys, &pCur, &iPage);
362 Assert(RT_SUCCESS(rc) || !pCur);
363 if ( pCur
364 && ( uErr & X86_TRAP_PF_RW
365 || pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
366 {
367 Assert((pCur->aPhysToVirt[iPage].Core.Key & X86_PTE_PAE_PG_MASK) == (pGstWalk->Core.GCPhys & X86_PTE_PAE_PG_MASK));
368# ifdef IN_RC
369 STAM_PROFILE_START(&pCur->Stat, h);
370 RTGCPTR GCPtrStart = pCur->Core.Key;
371 CTX_MID(PFNPGM,VIRTHANDLER) pfnHandler = pCur->CTX_SUFF(pfnHandler);
372 pgmUnlock(pVM);
373 *pfLockTaken = false;
374
375 RTGCPTR off = (iPage << PAGE_SHIFT)
376 + (pvFault & PAGE_OFFSET_MASK)
377 - (GCPtrStart & PAGE_OFFSET_MASK);
378 Assert(off < pCur->cb);
379 rc = pfnHandler(pVM, uErr, pRegFrame, pvFault, GCPtrStart, off);
380
381# ifdef VBOX_WITH_STATISTICS
382 pgmLock(pVM);
383 pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, GCPtrStart);
384 if (pCur)
385 STAM_PROFILE_STOP(&pCur->Stat, h);
386 pgmUnlock(pVM);
387# endif
388# else
389 rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
390# endif
391 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersVirtualByPhys);
392 STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndVirt; });
393 return rc;
394 }
395 }
396 }
397# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
398
399 /*
400 * There is a handled area of the page, but this fault doesn't belong to it.
401 * We must emulate the instruction.
402 *
403 * To avoid crashing (non-fatal) in the interpreter and go back to the recompiler
404 * we first check if this was a page-not-present fault for a page with only
405 * write access handlers. Restart the instruction if it wasn't a write access.
406 */
407 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersUnhandled);
408
409 if ( !PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
410 && !(uErr & X86_TRAP_PF_P))
411 {
412# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
413 rc = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
414# else
415 rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
416# endif
417 if ( RT_FAILURE(rc)
418 || rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
419 || !(uErr & X86_TRAP_PF_RW))
420 {
421 AssertRC(rc);
422 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersOutOfSync);
423 STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndPhys; });
424 return rc;
425 }
426 }
427
428 /** @todo This particular case can cause quite a lot of overhead. E.g. early stage of kernel booting in Ubuntu 6.06
429 * It's writing to an unhandled part of the LDT page several million times.
430 */
431 rc = VBOXSTRICTRC_TODO(PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault));
432 LogFlow(("PGM: PGMInterpretInstruction -> rc=%d pPage=%R[pgmpage]\n", rc, pPage));
433 STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndUnhandled; });
434 return rc;
435} /* if any kind of handler */
436
437
438/**
439 * #PF Handler for raw-mode guest execution.
440 *
441 * @returns VBox status code (appropriate for trap handling and GC return).
442 *
443 * @param pVCpu Pointer to the VMCPU.
444 * @param uErr The trap error code.
445 * @param pRegFrame Trap register frame.
446 * @param pvFault The fault address.
447 * @param pfLockTaken PGM lock taken here or not (out)
448 */
449PGM_BTH_DECL(int, Trap0eHandler)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken)
450{
451 PVM pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
452
453 *pfLockTaken = false;
454
455# if ( PGM_GST_TYPE == PGM_TYPE_32BIT || PGM_GST_TYPE == PGM_TYPE_REAL || PGM_GST_TYPE == PGM_TYPE_PROT \
456 || PGM_GST_TYPE == PGM_TYPE_PAE || PGM_GST_TYPE == PGM_TYPE_AMD64) \
457 && PGM_SHW_TYPE != PGM_TYPE_NESTED \
458 && (PGM_SHW_TYPE != PGM_TYPE_EPT || PGM_GST_TYPE == PGM_TYPE_PROT)
459 int rc;
460
461# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
462 /*
463 * Walk the guest page translation tables and check if it's a guest fault.
464 */
465 GSTPTWALK GstWalk;
466 rc = PGM_GST_NAME(Walk)(pVCpu, pvFault, &GstWalk);
467 if (RT_FAILURE_NP(rc))
468 return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerGuestFault)(pVCpu, &GstWalk, uErr));
469
470 /* assert some GstWalk sanity. */
471# if PGM_GST_TYPE == PGM_TYPE_AMD64
472 /*AssertMsg(GstWalk.Pml4e.u == GstWalk.pPml4e->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pml4e.u, (uint64_t)GstWalk.pPml4e->u)); - not always true with SMP guests. */
473# endif
474# if PGM_GST_TYPE == PGM_TYPE_AMD64 || PGM_GST_TYPE == PGM_TYPE_PAE
475 /*AssertMsg(GstWalk.Pdpe.u == GstWalk.pPdpe->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pdpe.u, (uint64_t)GstWalk.pPdpe->u)); - ditto */
476# endif
477 /*AssertMsg(GstWalk.Pde.u == GstWalk.pPde->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pde.u, (uint64_t)GstWalk.pPde->u)); - ditto */
478 /*AssertMsg(GstWalk.Core.fBigPage || GstWalk.Pte.u == GstWalk.pPte->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pte.u, (uint64_t)GstWalk.pPte->u)); - ditto */
479 Assert(GstWalk.Core.fSucceeded);
480
481 if (uErr & (X86_TRAP_PF_RW | X86_TRAP_PF_US | X86_TRAP_PF_ID))
482 {
483 if ( ( (uErr & X86_TRAP_PF_RW)
484 && !GstWalk.Core.fEffectiveRW
485 && ( (uErr & X86_TRAP_PF_US)
486 || CPUMIsGuestR0WriteProtEnabled(pVCpu)) )
487 || ((uErr & X86_TRAP_PF_US) && !GstWalk.Core.fEffectiveUS)
488 || ((uErr & X86_TRAP_PF_ID) && GstWalk.Core.fEffectiveNX)
489 )
490 return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerGuestFault)(pVCpu, &GstWalk, uErr));
491 }
492
493 /*
494 * Set the accessed and dirty flags.
495 */
496# if PGM_GST_TYPE == PGM_TYPE_AMD64
497 GstWalk.Pml4e.u |= X86_PML4E_A;
498 GstWalk.pPml4e->u |= X86_PML4E_A;
499 GstWalk.Pdpe.u |= X86_PDPE_A;
500 GstWalk.pPdpe->u |= X86_PDPE_A;
501# endif
502 if (GstWalk.Core.fBigPage)
503 {
504 Assert(GstWalk.Pde.b.u1Size);
505 if (uErr & X86_TRAP_PF_RW)
506 {
507 GstWalk.Pde.u |= X86_PDE4M_A | X86_PDE4M_D;
508 GstWalk.pPde->u |= X86_PDE4M_A | X86_PDE4M_D;
509 }
510 else
511 {
512 GstWalk.Pde.u |= X86_PDE4M_A;
513 GstWalk.pPde->u |= X86_PDE4M_A;
514 }
515 }
516 else
517 {
518 Assert(!GstWalk.Pde.b.u1Size);
519 GstWalk.Pde.u |= X86_PDE_A;
520 GstWalk.pPde->u |= X86_PDE_A;
521 if (uErr & X86_TRAP_PF_RW)
522 {
523# ifdef VBOX_WITH_STATISTICS
524 if (!GstWalk.Pte.n.u1Dirty)
525 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtiedPage));
526 else
527 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageAlreadyDirty));
528# endif
529 GstWalk.Pte.u |= X86_PTE_A | X86_PTE_D;
530 GstWalk.pPte->u |= X86_PTE_A | X86_PTE_D;
531 }
532 else
533 {
534 GstWalk.Pte.u |= X86_PTE_A;
535 GstWalk.pPte->u |= X86_PTE_A;
536 }
537 Assert(GstWalk.Pte.u == GstWalk.pPte->u);
538 }
539 AssertMsg(GstWalk.Pde.u == GstWalk.pPde->u || GstWalk.pPte->u == GstWalk.pPde->u,
540 ("%RX64 %RX64 pPte=%p pPde=%p Pte=%RX64\n", (uint64_t)GstWalk.Pde.u, (uint64_t)GstWalk.pPde->u, GstWalk.pPte, GstWalk.pPde, (uint64_t)GstWalk.pPte->u));
541# else /* !PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
542 GSTPDE const PdeSrcDummy = { X86_PDE_P | X86_PDE_US | X86_PDE_RW | X86_PDE_A}; /** @todo eliminate this */
543# endif /* !PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
544
545 /* Take the big lock now. */
546 *pfLockTaken = true;
547 pgmLock(pVM);
548
549# ifdef PGM_WITH_MMIO_OPTIMIZATIONS
550 /*
551 * If it is a reserved bit fault we know that it is an MMIO (access
552 * handler) related fault and can skip some 200 lines of code.
553 */
554 if (uErr & X86_TRAP_PF_RSVD)
555 {
556 Assert(uErr & X86_TRAP_PF_P);
557 PPGMPAGE pPage;
558# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
559 rc = pgmPhysGetPageEx(pVM, GstWalk.Core.GCPhys, &pPage);
560 if (RT_SUCCESS(rc) && PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
561 return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage,
562 pfLockTaken, &GstWalk));
563 rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
564# else
565 rc = pgmPhysGetPageEx(pVM, PGM_A20_APPLY(pVCpu, (RTGCPHYS)pvFault), &pPage);
566 if (RT_SUCCESS(rc) && PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
567 return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage,
568 pfLockTaken));
569 rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, 1, uErr);
570# endif
571 AssertRC(rc);
572 PGM_INVL_PG(pVCpu, pvFault);
573 return rc; /* Restart with the corrected entry. */
574 }
575# endif /* PGM_WITH_MMIO_OPTIMIZATIONS */
576
577 /*
578 * Fetch the guest PDE, PDPE and PML4E.
579 */
580# if PGM_SHW_TYPE == PGM_TYPE_32BIT
581 const unsigned iPDDst = pvFault >> SHW_PD_SHIFT;
582 PX86PD pPDDst = pgmShwGet32BitPDPtr(pVCpu);
583
584# elif PGM_SHW_TYPE == PGM_TYPE_PAE
585 const unsigned iPDDst = (pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK; /* pPDDst index, not used with the pool. */
586 PX86PDPAE pPDDst;
587# if PGM_GST_TYPE == PGM_TYPE_PAE
588 rc = pgmShwSyncPaePDPtr(pVCpu, pvFault, GstWalk.Pdpe.u, &pPDDst);
589# else
590 rc = pgmShwSyncPaePDPtr(pVCpu, pvFault, X86_PDPE_P, &pPDDst); /* RW, US and A are reserved in PAE mode. */
591# endif
592 AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
593
594# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
595 const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
596 PX86PDPAE pPDDst;
597# if PGM_GST_TYPE == PGM_TYPE_PROT /* (AMD-V nested paging) */
598 rc = pgmShwSyncLongModePDPtr(pVCpu, pvFault, X86_PML4E_P | X86_PML4E_RW | X86_PML4E_US | X86_PML4E_A,
599 X86_PDPE_P | X86_PDPE_RW | X86_PDPE_US | X86_PDPE_A, &pPDDst);
600# else
601 rc = pgmShwSyncLongModePDPtr(pVCpu, pvFault, GstWalk.Pml4e.u, GstWalk.Pdpe.u, &pPDDst);
602# endif
603 AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
604
605# elif PGM_SHW_TYPE == PGM_TYPE_EPT
606 const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
607 PEPTPD pPDDst;
608 rc = pgmShwGetEPTPDPtr(pVCpu, pvFault, NULL, &pPDDst);
609 AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
610# endif
611 Assert(pPDDst);
612
613# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
614 /*
615 * Dirty page handling.
616 *
617 * If we successfully correct the write protection fault due to dirty bit
618 * tracking, then return immediately.
619 */
620 if (uErr & X86_TRAP_PF_RW) /* write fault? */
621 {
622 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyBitTracking), a);
623 rc = PGM_BTH_NAME(CheckDirtyPageFault)(pVCpu, uErr, &pPDDst->a[iPDDst], GstWalk.pPde, pvFault);
624 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyBitTracking), a);
625 if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
626 {
627 STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution)
628 = rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT
629 ? &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2DirtyAndAccessed
630 : &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2GuestTrap; });
631 LogBird(("Trap0eHandler: returns VINF_SUCCESS\n"));
632 return VINF_SUCCESS;
633 }
634 //AssertMsg(GstWalk.Pde.u == GstWalk.pPde->u || GstWalk.pPte->u == GstWalk.pPde->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pde.u, (uint64_t)GstWalk.pPde->u)); - triggers with smp w7 guests.
635 //AssertMsg(GstWalk.Core.fBigPage || GstWalk.Pte.u == GstWalk.pPte->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pte.u, (uint64_t)GstWalk.pPte->u)); - ditto.
636 }
637
638# if 0 /* rarely useful; leave for debugging. */
639 STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0ePD[iPDSrc]);
640# endif
641# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
642
643 /*
644 * A common case is the not-present error caused by lazy page table syncing.
645 *
646 * It is IMPORTANT that we weed out any access to non-present shadow PDEs
647 * here so we can safely assume that the shadow PT is present when calling
648 * SyncPage later.
649 *
650 * On failure, we ASSUME that SyncPT is out of memory or detected some kind
651 * of mapping conflict and defer to SyncCR3 in R3.
652 * (Again, we do NOT support access handlers for non-present guest pages.)
653 *
654 */
655# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
656 Assert(GstWalk.Pde.n.u1Present);
657# endif
658 if ( !(uErr & X86_TRAP_PF_P) /* not set means page not present instead of page protection violation */
659 && !pPDDst->a[iPDDst].n.u1Present)
660 {
661 STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2SyncPT; });
662# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
663 LogFlow(("=>SyncPT %04x = %08RX64\n", (pvFault >> GST_PD_SHIFT) & GST_PD_MASK, (uint64_t)GstWalk.Pde.u));
664 rc = PGM_BTH_NAME(SyncPT)(pVCpu, (pvFault >> GST_PD_SHIFT) & GST_PD_MASK, GstWalk.pPd, pvFault);
665# else
666 LogFlow(("=>SyncPT pvFault=%RGv\n", pvFault));
667 rc = PGM_BTH_NAME(SyncPT)(pVCpu, 0, NULL, pvFault);
668# endif
669 if (RT_SUCCESS(rc))
670 return rc;
671 Log(("SyncPT: %RGv failed!! rc=%Rrc\n", pvFault, rc));
672 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync, right? */
673 return VINF_PGM_SYNC_CR3;
674 }
675
676# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(PGM_WITHOUT_MAPPINGS)
677 /*
678 * Check if this address is within any of our mappings.
679 *
680 * This is *very* fast and it's gonna save us a bit of effort below and prevent
681 * us from screwing ourself with MMIO2 pages which have a GC Mapping (VRam).
682 * (BTW, it's impossible to have physical access handlers in a mapping.)
683 */
684 if (pgmMapAreMappingsEnabled(pVM))
685 {
686 PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
687 for ( ; pMapping; pMapping = pMapping->CTX_SUFF(pNext))
688 {
689 if (pvFault < pMapping->GCPtr)
690 break;
691 if (pvFault - pMapping->GCPtr < pMapping->cb)
692 {
693 /*
694 * The first thing we check is if we've got an undetected conflict.
695 */
696 if (pgmMapAreMappingsFloating(pVM))
697 {
698 unsigned iPT = pMapping->cb >> GST_PD_SHIFT;
699 while (iPT-- > 0)
700 if (GstWalk.pPde[iPT].n.u1Present)
701 {
702 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eConflicts);
703 Log(("Trap0e: Detected Conflict %RGv-%RGv\n", pMapping->GCPtr, pMapping->GCPtrLast));
704 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync,right? */
705 STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Mapping; });
706 return VINF_PGM_SYNC_CR3;
707 }
708 }
709
710 /*
711 * Check if the fault address is in a virtual page access handler range.
712 */
713 PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->HyperVirtHandlers, pvFault);
714 if ( pCur
715 && pvFault - pCur->Core.Key < pCur->cb
716 && uErr & X86_TRAP_PF_RW)
717 {
718# ifdef IN_RC
719 STAM_PROFILE_START(&pCur->Stat, h);
720 pgmUnlock(pVM);
721 rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
722 pgmLock(pVM);
723 STAM_PROFILE_STOP(&pCur->Stat, h);
724# else
725 AssertFailed();
726 rc = VINF_EM_RAW_EMULATE_INSTR; /* can't happen with VMX */
727# endif
728 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersMapping);
729 STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Mapping; });
730 return rc;
731 }
732
733 /*
734 * Pretend we're not here and let the guest handle the trap.
735 */
736 TRPMSetErrorCode(pVCpu, uErr & ~X86_TRAP_PF_P);
737 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eGuestPFMapping);
738 LogFlow(("PGM: Mapping access -> route trap to recompiler!\n"));
739 STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Mapping; });
740 return VINF_EM_RAW_GUEST_TRAP;
741 }
742 }
743 } /* pgmAreMappingsEnabled(&pVM->pgm.s) */
744# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
745
746 /*
747 * Check if this fault address is flagged for special treatment,
748 * which means we'll have to figure out the physical address and
749 * check flags associated with it.
750 *
751 * ASSUME that we can limit any special access handling to pages
752 * in page tables which the guest believes to be present.
753 */
754# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
755 RTGCPHYS GCPhys = GstWalk.Core.GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK;
756# else
757 RTGCPHYS GCPhys = PGM_A20_APPLY(pVCpu, (RTGCPHYS)pvFault & ~(RTGCPHYS)PAGE_OFFSET_MASK);
758# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
759 PPGMPAGE pPage;
760 rc = pgmPhysGetPageEx(pVM, GCPhys, &pPage);
761 if (RT_FAILURE(rc))
762 {
763 /*
764 * When the guest accesses invalid physical memory (e.g. probing
765 * of RAM or accessing a remapped MMIO range), then we'll fall
766 * back to the recompiler to emulate the instruction.
767 */
768 LogFlow(("PGM #PF: pgmPhysGetPageEx(%RGp) failed with %Rrc\n", GCPhys, rc));
769 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersInvalid);
770 STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2InvalidPhys; });
771 return VINF_EM_RAW_EMULATE_INSTR;
772 }
773
774 /*
775 * Any handlers for this page?
776 */
777 if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
778# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
779 return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage, pfLockTaken,
780 &GstWalk));
781# else
782 return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage, pfLockTaken));
783# endif
784
785 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTimeOutOfSync, c);
786
787# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0)
788 if (uErr & X86_TRAP_PF_P)
789 {
790 /*
791 * The page isn't marked, but it might still be monitored by a virtual page access handler.
792 * (ASSUMES no temporary disabling of virtual handlers.)
793 */
794 /** @todo r=bird: Since the purpose is to catch out of sync pages with virtual handler(s) here,
795 * we should correct both the shadow page table and physical memory flags, and not only check for
796 * accesses within the handler region but for access to pages with virtual handlers. */
797 PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
798 if (pCur)
799 {
800 AssertMsg( !(pvFault - pCur->Core.Key < pCur->cb)
801 || ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
802 || !(uErr & X86_TRAP_PF_P)
803 || (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
804 ("Unexpected trap for virtual handler: %08X (phys=%08x) %R[pgmpage] uErr=%X, enum=%d\n", pvFault, GCPhys, pPage, uErr, pCur->enmType));
805
806 if ( pvFault - pCur->Core.Key < pCur->cb
807 && ( uErr & X86_TRAP_PF_RW
808 || pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
809 {
810# ifdef IN_RC
811 STAM_PROFILE_START(&pCur->Stat, h);
812 pgmUnlock(pVM);
813 rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
814 pgmLock(pVM);
815 STAM_PROFILE_STOP(&pCur->Stat, h);
816# else
817 rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
818# endif
819 STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndVirt; });
820 return rc;
821 }
822 }
823 }
824# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
825
826 /*
827 * We are here only if page is present in Guest page tables and
828 * trap is not handled by our handlers.
829 *
830 * Check it for page out-of-sync situation.
831 */
832 if (!(uErr & X86_TRAP_PF_P))
833 {
834 /*
835 * Page is not present in our page tables. Try to sync it!
836 */
837 if (uErr & X86_TRAP_PF_US)
838 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncUser));
839 else /* supervisor */
840 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
841
842 if (PGM_PAGE_IS_BALLOONED(pPage))
843 {
844 /* Emulate reads from ballooned pages as they are not present in
845 our shadow page tables. (Required for e.g. Solaris guests; soft
846 ecc, random nr generator.) */
847 rc = VBOXSTRICTRC_TODO(PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault));
848 LogFlow(("PGM: PGMInterpretInstruction balloon -> rc=%d pPage=%R[pgmpage]\n", rc, pPage));
849 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncBallloon));
850 STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Ballooned; });
851 return rc;
852 }
853
854# if defined(LOG_ENABLED) && !defined(IN_RING0)
855 RTGCPHYS GCPhys2;
856 uint64_t fPageGst2;
857 PGMGstGetPage(pVCpu, pvFault, &fPageGst2, &GCPhys2);
858# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
859 Log(("Page out of sync: %RGv eip=%08x PdeSrc.US=%d fPageGst2=%08llx GCPhys2=%RGp scan=%d\n",
860 pvFault, pRegFrame->eip, GstWalk.Pde.n.u1User, fPageGst2, GCPhys2, CSAMDoesPageNeedScanning(pVM, pRegFrame->eip)));
861# else
862 Log(("Page out of sync: %RGv eip=%08x fPageGst2=%08llx GCPhys2=%RGp scan=%d\n",
863 pvFault, pRegFrame->eip, fPageGst2, GCPhys2, CSAMDoesPageNeedScanning(pVM, pRegFrame->eip)));
864# endif
865# endif /* LOG_ENABLED */
866
867# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0)
868 if ( !GstWalk.Core.fEffectiveUS
869 && CSAMIsEnabled(pVM)
870 && CPUMGetGuestCPL(pVCpu) == 0)
871 {
872 /* Note: Can't check for X86_TRAP_ID bit, because that requires execute disable support on the CPU. */
873 if ( pvFault == (RTGCPTR)pRegFrame->eip
874 || pvFault - pRegFrame->eip < 8 /* instruction crossing a page boundary */
875# ifdef CSAM_DETECT_NEW_CODE_PAGES
876 || ( !PATMIsPatchGCAddr(pVM, pRegFrame->eip)
877 && CSAMDoesPageNeedScanning(pVM, pRegFrame->eip)) /* any new code we encounter here */
878# endif /* CSAM_DETECT_NEW_CODE_PAGES */
879 )
880 {
881 LogFlow(("CSAMExecFault %RX32\n", pRegFrame->eip));
882 rc = CSAMExecFault(pVM, (RTRCPTR)pRegFrame->eip);
883 if (rc != VINF_SUCCESS)
884 {
885 /*
886 * CSAM needs to perform a job in ring 3.
887 *
888 * Sync the page before going to the host context; otherwise we'll end up in a loop if
889 * CSAM fails (e.g. instruction crosses a page boundary and the next page is not present)
890 */
891 LogFlow(("CSAM ring 3 job\n"));
892 int rc2 = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
893 AssertRC(rc2);
894
895 STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2CSAM; });
896 return rc;
897 }
898 }
899# ifdef CSAM_DETECT_NEW_CODE_PAGES
900 else if ( uErr == X86_TRAP_PF_RW
901 && pRegFrame->ecx >= 0x100 /* early check for movswd count */
902 && pRegFrame->ecx < 0x10000)
903 {
904 /* In case of a write to a non-present supervisor shadow page, we'll take special precautions
905 * to detect loading of new code pages.
906 */
907
908 /*
909 * Decode the instruction.
910 */
911 PDISCPUSTATE pDis = &pVCpu->pgm.s.DisState;
912 uint32_t cbOp;
913 rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
914
915 /* For now we'll restrict this to rep movsw/d instructions */
916 if ( rc == VINF_SUCCESS
917 && pDis->pCurInstr->opcode == OP_MOVSWD
918 && (pDis->prefix & DISPREFIX_REP))
919 {
920 CSAMMarkPossibleCodePage(pVM, pvFault);
921 }
922 }
923# endif /* CSAM_DETECT_NEW_CODE_PAGES */
924
925 /*
926 * Mark this page as safe.
927 */
928 /** @todo not correct for pages that contain both code and data!! */
929 Log2(("CSAMMarkPage %RGv; scanned=%d\n", pvFault, true));
930 CSAMMarkPage(pVM, pvFault, true);
931 }
932# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0) */
933# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
934 rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
935# else
936 rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
937# endif
938 if (RT_SUCCESS(rc))
939 {
940 /* The page was successfully synced, return to the guest. */
941 STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSync; });
942 return VINF_SUCCESS;
943 }
944 }
945 else /* uErr & X86_TRAP_PF_P: */
946 {
947 /*
948 * Write protected pages are made writable when the guest makes the
949 * first write to it. This happens for pages that are shared, write
950 * monitored or not yet allocated.
951 *
952 * We may also end up here when CR0.WP=0 in the guest.
953 *
954 * Also, a side effect of not flushing global PDEs are out of sync
955 * pages due to physical monitored regions, that are no longer valid.
956 * Assume for now it only applies to the read/write flag.
957 */
958 if (uErr & X86_TRAP_PF_RW)
959 {
960 /*
961 * Check if it is a read-only page.
962 */
963 if (PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
964 {
965 Log(("PGM #PF: Make writable: %RGp %R[pgmpage] pvFault=%RGp uErr=%#x\n", GCPhys, pPage, pvFault, uErr));
966 Assert(!PGM_PAGE_IS_ZERO(pPage));
967 AssertFatalMsg(!PGM_PAGE_IS_BALLOONED(pPage), ("Unexpected ballooned page at %RGp\n", GCPhys));
968 STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2MakeWritable; });
969
970 rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
971 if (rc != VINF_SUCCESS)
972 {
973 AssertMsg(rc == VINF_PGM_SYNC_CR3 || RT_FAILURE(rc), ("%Rrc\n", rc));
974 return rc;
975 }
976 if (RT_UNLIKELY(VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY)))
977 return VINF_EM_NO_MEMORY;
978 }
979
980# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
981 /*
982 * Check to see if we need to emulate the instruction if CR0.WP=0.
983 */
984 if ( !GstWalk.Core.fEffectiveRW
985 && (CPUMGetGuestCR0(pVCpu) & (X86_CR0_WP | X86_CR0_PG)) == X86_CR0_PG
986 && CPUMGetGuestCPL(pVCpu) < 3)
987 {
988 Assert((uErr & (X86_TRAP_PF_RW | X86_TRAP_PF_P)) == (X86_TRAP_PF_RW | X86_TRAP_PF_P));
989
990 /*
991 * The Netware WP0+RO+US hack.
992 *
993 * Netware sometimes(/always?) runs with WP0. It has been observed doing
994 * excessive write accesses to pages which are mapped with US=1 and RW=0
995 * while WP=0. This causes a lot of exits and extremely slow execution.
996 * To avoid trapping and emulating every write here, we change the shadow
997 * page table entry to map it as US=0 and RW=1 until user mode tries to
998 * access it again (see further below). We count these shadow page table
999 * changes so we can avoid having to clear the page pool every time the WP
1000 * bit changes to 1 (see PGMCr0WpEnabled()).
1001 */
1002# if (PGM_GST_TYPE == PGM_TYPE_32BIT || PGM_GST_TYPE == PGM_TYPE_PAE) && 1
1003 if ( GstWalk.Core.fEffectiveUS
1004 && !GstWalk.Core.fEffectiveRW
1005 && (GstWalk.Core.fBigPage || GstWalk.Pde.n.u1Write)
1006 && pVM->cCpus == 1 /* Sorry, no go on SMP. Add CFGM option? */)
1007 {
1008 Log(("PGM #PF: Netware WP0+RO+US hack: pvFault=%RGp uErr=%#x (big=%d)\n", pvFault, uErr, GstWalk.Core.fBigPage));
1009 rc = pgmShwMakePageSupervisorAndWritable(pVCpu, pvFault, GstWalk.Core.fBigPage, PGM_MK_PG_IS_WRITE_FAULT);
1010 if (rc == VINF_SUCCESS || rc == VINF_PGM_SYNC_CR3)
1011 {
1012 PGM_INVL_PG(pVCpu, pvFault);
1013 pVCpu->pgm.s.cNetwareWp0Hacks++;
1014 STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Wp0RoUsHack; });
1015 return rc;
1016 }
1017 AssertMsg(RT_FAILURE_NP(rc), ("%Rrc\n", rc));
1018 Log(("pgmShwMakePageSupervisorAndWritable(%RGv) failed with rc=%Rrc - ignored\n", pvFault, rc));
1019 }
1020# endif
1021
1022 /* Interpret the access. */
1023 rc = VBOXSTRICTRC_TODO(PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault));
1024 Log(("PGM #PF: WP0 emulation (pvFault=%RGp uErr=%#x cpl=%d fBig=%d fEffUs=%d)\n", pvFault, uErr, CPUMGetGuestCPL(pVCpu), GstWalk.Core.fBigPage, GstWalk.Core.fEffectiveUS));
1025 if (RT_SUCCESS(rc))
1026 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eWPEmulInRZ);
1027 else
1028 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eWPEmulToR3);
1029 STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2WPEmulation; });
1030 return rc;
1031 }
1032# endif
1033 /// @todo count the above case; else
1034 if (uErr & X86_TRAP_PF_US)
1035 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncUserWrite));
1036 else /* supervisor */
1037 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncSupervisorWrite));
1038
1039 /*
1040 * Sync the page.
1041 *
1042 * Note: Do NOT use PGM_SYNC_NR_PAGES here. That only works if the
1043 * page is not present, which is not true in this case.
1044 */
1045# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1046 rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
1047# else
1048 rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, 1, uErr);
1049# endif
1050 if (RT_SUCCESS(rc))
1051 {
1052 /*
1053 * Page was successfully synced, return to guest but invalidate
1054 * the TLB first as the page is very likely to be in it.
1055 */
1056# if PGM_SHW_TYPE == PGM_TYPE_EPT
1057 HMInvalidatePhysPage(pVM, (RTGCPHYS)pvFault);
1058# else
1059 PGM_INVL_PG(pVCpu, pvFault);
1060# endif
1061# ifdef VBOX_STRICT
1062 RTGCPHYS GCPhys2;
1063 uint64_t fPageGst;
1064 if (!pVM->pgm.s.fNestedPaging)
1065 {
1066 rc = PGMGstGetPage(pVCpu, pvFault, &fPageGst, &GCPhys2);
1067 AssertMsg(RT_SUCCESS(rc) && ((fPageGst & X86_PTE_RW) || ((CPUMGetGuestCR0(pVCpu) & (X86_CR0_WP | X86_CR0_PG)) == X86_CR0_PG && CPUMGetGuestCPL(pVCpu) < 3)), ("rc=%Rrc fPageGst=%RX64\n", rc, fPageGst));
1068 LogFlow(("Obsolete physical monitor page out of sync %RGv - phys %RGp flags=%08llx\n", pvFault, GCPhys2, (uint64_t)fPageGst));
1069 }
1070 uint64_t fPageShw;
1071 rc = PGMShwGetPage(pVCpu, pvFault, &fPageShw, NULL);
1072 AssertMsg((RT_SUCCESS(rc) && (fPageShw & X86_PTE_RW)) || pVM->cCpus > 1 /* new monitor can be installed/page table flushed between the trap exit and PGMTrap0eHandler */,
1073 ("rc=%Rrc fPageShw=%RX64\n", rc, fPageShw));
1074# endif /* VBOX_STRICT */
1075 STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndObs; });
1076 return VINF_SUCCESS;
1077 }
1078 }
1079# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1080 /*
1081 * Check for Netware WP0+RO+US hack from above and undo it when user
1082 * mode accesses the page again.
1083 */
1084 else if ( GstWalk.Core.fEffectiveUS
1085 && !GstWalk.Core.fEffectiveRW
1086 && (GstWalk.Core.fBigPage || GstWalk.Pde.n.u1Write)
1087 && pVCpu->pgm.s.cNetwareWp0Hacks > 0
1088 && (CPUMGetGuestCR0(pVCpu) & (X86_CR0_WP | X86_CR0_PG)) == X86_CR0_PG
1089 && CPUMGetGuestCPL(pVCpu) == 3
1090 && pVM->cCpus == 1
1091 )
1092 {
1093 Log(("PGM #PF: Undo netware WP0+RO+US hack: pvFault=%RGp uErr=%#x\n", pvFault, uErr));
1094 rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
1095 if (RT_SUCCESS(rc))
1096 {
1097 PGM_INVL_PG(pVCpu, pvFault);
1098 pVCpu->pgm.s.cNetwareWp0Hacks--;
1099 STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Wp0RoUsUnhack; });
1100 return VINF_SUCCESS;
1101 }
1102 }
1103# endif /* PGM_WITH_PAGING */
1104
1105 /** @todo else: why are we here? */
1106
1107# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && defined(VBOX_STRICT)
1108 /*
1109 * Check for VMM page flags vs. Guest page flags consistency.
1110 * Currently only for debug purposes.
1111 */
1112 if (RT_SUCCESS(rc))
1113 {
1114 /* Get guest page flags. */
1115 uint64_t fPageGst;
1116 rc = PGMGstGetPage(pVCpu, pvFault, &fPageGst, NULL);
1117 if (RT_SUCCESS(rc))
1118 {
1119 uint64_t fPageShw;
1120 rc = PGMShwGetPage(pVCpu, pvFault, &fPageShw, NULL);
1121
1122 /*
1123 * Compare page flags.
1124 * Note: we have AVL, A, D bits desynced.
1125 */
1126 AssertMsg( (fPageShw & ~(X86_PTE_A | X86_PTE_D | X86_PTE_AVL_MASK))
1127 == (fPageGst & ~(X86_PTE_A | X86_PTE_D | X86_PTE_AVL_MASK))
1128 || ( pVCpu->pgm.s.cNetwareWp0Hacks > 0
1129 && (fPageShw & ~(X86_PTE_A | X86_PTE_D | X86_PTE_AVL_MASK | X86_PTE_RW | X86_PTE_US))
1130 == (fPageGst & ~(X86_PTE_A | X86_PTE_D | X86_PTE_AVL_MASK | X86_PTE_RW | X86_PTE_US))
1131 && (fPageShw & (X86_PTE_RW | X86_PTE_US)) == X86_PTE_RW
1132 && (fPageGst & (X86_PTE_RW | X86_PTE_US)) == X86_PTE_US),
1133 ("Page flags mismatch! pvFault=%RGv uErr=%x GCPhys=%RGp fPageShw=%RX64 fPageGst=%RX64\n",
1134 pvFault, (uint32_t)uErr, GCPhys, fPageShw, fPageGst));
1135 }
1136 else
1137 AssertMsgFailed(("PGMGstGetPage rc=%Rrc\n", rc));
1138 }
1139 else
1140 AssertMsgFailed(("PGMGCGetPage rc=%Rrc\n", rc));
1141# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && VBOX_STRICT */
1142 }
1143
1144
1145 /*
1146 * If we get here it is because something failed above, i.e. most like guru
1147 * meditiation time.
1148 */
1149 LogRel(("%s: returns rc=%Rrc pvFault=%RGv uErr=%RX64 cs:rip=%04x:%08RX64\n",
1150 __PRETTY_FUNCTION__, rc, pvFault, (uint64_t)uErr, pRegFrame->cs.Sel, pRegFrame->rip));
1151 return rc;
1152
1153# else /* Nested paging, EPT except PGM_GST_TYPE = PROT */
1154 NOREF(uErr); NOREF(pRegFrame); NOREF(pvFault);
1155 AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
1156 return VERR_PGM_NOT_USED_IN_MODE;
1157# endif
1158}
1159#endif /* !IN_RING3 */
1160
1161
1162/**
1163 * Emulation of the invlpg instruction.
1164 *
1165 *
1166 * @returns VBox status code.
1167 *
1168 * @param pVCpu Pointer to the VMCPU.
1169 * @param GCPtrPage Page to invalidate.
1170 *
1171 * @remark ASSUMES that the guest is updating before invalidating. This order
1172 * isn't required by the CPU, so this is speculative and could cause
1173 * trouble.
1174 * @remark No TLB shootdown is done on any other VCPU as we assume that
1175 * invlpg emulation is the *only* reason for calling this function.
1176 * (The guest has to shoot down TLB entries on other CPUs itself)
1177 * Currently true, but keep in mind!
1178 *
1179 * @todo Clean this up! Most of it is (or should be) no longer necessary as we catch all page table accesses.
1180 * Should only be required when PGMPOOL_WITH_OPTIMIZED_DIRTY_PT is active (PAE or AMD64 (for now))
1181 */
1182PGM_BTH_DECL(int, InvalidatePage)(PVMCPU pVCpu, RTGCPTR GCPtrPage)
1183{
1184#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
1185 && PGM_SHW_TYPE != PGM_TYPE_NESTED \
1186 && PGM_SHW_TYPE != PGM_TYPE_EPT
1187 int rc;
1188 PVM pVM = pVCpu->CTX_SUFF(pVM);
1189 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1190
1191 PGM_LOCK_ASSERT_OWNER(pVM);
1192
1193 LogFlow(("InvalidatePage %RGv\n", GCPtrPage));
1194
1195 /*
1196 * Get the shadow PD entry and skip out if this PD isn't present.
1197 * (Guessing that it is frequent for a shadow PDE to not be present, do this first.)
1198 */
1199# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1200 const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1201 PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
1202
1203 /* Fetch the pgm pool shadow descriptor. */
1204 PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
1205 Assert(pShwPde);
1206
1207# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1208 const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT);
1209 PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(pVCpu);
1210
1211 /* If the shadow PDPE isn't present, then skip the invalidate. */
1212 if (!pPdptDst->a[iPdpt].n.u1Present)
1213 {
1214 Assert(!(pPdptDst->a[iPdpt].u & PGM_PLXFLAGS_MAPPING));
1215 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1216 PGM_INVL_PG(pVCpu, GCPtrPage);
1217 return VINF_SUCCESS;
1218 }
1219
1220 const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1221 PPGMPOOLPAGE pShwPde = NULL;
1222 PX86PDPAE pPDDst;
1223
1224 /* Fetch the pgm pool shadow descriptor. */
1225 rc = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
1226 AssertRCSuccessReturn(rc, rc);
1227 Assert(pShwPde);
1228
1229 pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
1230 PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1231
1232# else /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
1233 /* PML4 */
1234 /*const unsigned iPml4 = (GCPtrPage >> X86_PML4_SHIFT) & X86_PML4_MASK;*/
1235 const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1236 const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1237 PX86PDPAE pPDDst;
1238 PX86PDPT pPdptDst;
1239 PX86PML4E pPml4eDst;
1240 rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eDst, &pPdptDst, &pPDDst);
1241 if (rc != VINF_SUCCESS)
1242 {
1243 AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT || rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
1244 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1245 PGM_INVL_PG(pVCpu, GCPtrPage);
1246 return VINF_SUCCESS;
1247 }
1248 Assert(pPDDst);
1249
1250 PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1251 PX86PDPE pPdpeDst = &pPdptDst->a[iPdpt];
1252
1253 if (!pPdpeDst->n.u1Present)
1254 {
1255 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1256 PGM_INVL_PG(pVCpu, GCPtrPage);
1257 return VINF_SUCCESS;
1258 }
1259
1260 /* Fetch the pgm pool shadow descriptor. */
1261 PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & SHW_PDPE_PG_MASK);
1262 Assert(pShwPde);
1263
1264# endif /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
1265
1266 const SHWPDE PdeDst = *pPdeDst;
1267 if (!PdeDst.n.u1Present)
1268 {
1269 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1270 PGM_INVL_PG(pVCpu, GCPtrPage);
1271 return VINF_SUCCESS;
1272 }
1273
1274 /*
1275 * Get the guest PD entry and calc big page.
1276 */
1277# if PGM_GST_TYPE == PGM_TYPE_32BIT
1278 PGSTPD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
1279 const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
1280 GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
1281# else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1282 unsigned iPDSrc = 0;
1283# if PGM_GST_TYPE == PGM_TYPE_PAE
1284 X86PDPE PdpeSrcIgn;
1285 PX86PDPAE pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtrPage, &iPDSrc, &PdpeSrcIgn);
1286# else /* AMD64 */
1287 PX86PML4E pPml4eSrcIgn;
1288 X86PDPE PdpeSrcIgn;
1289 PX86PDPAE pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eSrcIgn, &PdpeSrcIgn, &iPDSrc);
1290# endif
1291 GSTPDE PdeSrc;
1292
1293 if (pPDSrc)
1294 PdeSrc = pPDSrc->a[iPDSrc];
1295 else
1296 PdeSrc.u = 0;
1297# endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1298 const bool fIsBigPage = PdeSrc.b.u1Size && GST_IS_PSE_ACTIVE(pVCpu);
1299
1300# ifdef IN_RING3
1301 /*
1302 * If a CR3 Sync is pending we may ignore the invalidate page operation
1303 * depending on the kind of sync and if it's a global page or not.
1304 * This doesn't make sense in GC/R0 so we'll skip it entirely there.
1305 */
1306# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
1307 if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3)
1308 || ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
1309 && fIsBigPage
1310 && PdeSrc.b.u1Global
1311 )
1312 )
1313# else
1314 if (VM_FF_IS_PENDING(pVM, VM_FF_PGM_SYNC_CR3 | VM_FF_PGM_SYNC_CR3_NON_GLOBAL) )
1315# endif
1316 {
1317 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1318 return VINF_SUCCESS;
1319 }
1320# endif /* IN_RING3 */
1321
1322 /*
1323 * Deal with the Guest PDE.
1324 */
1325 rc = VINF_SUCCESS;
1326 if (PdeSrc.n.u1Present)
1327 {
1328 Assert( PdeSrc.n.u1User == PdeDst.n.u1User
1329 && (PdeSrc.n.u1Write || !PdeDst.n.u1Write || pVCpu->pgm.s.cNetwareWp0Hacks > 0));
1330# ifndef PGM_WITHOUT_MAPPING
1331 if (PdeDst.u & PGM_PDFLAGS_MAPPING)
1332 {
1333 /*
1334 * Conflict - Let SyncPT deal with it to avoid duplicate code.
1335 */
1336 Assert(pgmMapAreMappingsEnabled(pVM));
1337 Assert(PGMGetGuestMode(pVCpu) <= PGMMODE_PAE);
1338 rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
1339 }
1340 else
1341# endif /* !PGM_WITHOUT_MAPPING */
1342 if (!fIsBigPage)
1343 {
1344 /*
1345 * 4KB - page.
1346 */
1347 PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1348 RTGCPHYS GCPhys = GST_GET_PDE_GCPHYS(PdeSrc);
1349
1350# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1351 /* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1352 GCPhys = PGM_A20_APPLY(pVCpu, GCPhys | ((iPDDst & 1) * (PAGE_SIZE / 2)));
1353# endif
1354 if (pShwPage->GCPhys == GCPhys)
1355 {
1356 /* Syncing it here isn't 100% safe and it's probably not worth spending time syncing it. */
1357 PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1358
1359 PGSTPT pPTSrc;
1360 rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GST_GET_PDE_GCPHYS(PdeSrc), &pPTSrc);
1361 if (RT_SUCCESS(rc))
1362 {
1363 const unsigned iPTSrc = (GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK;
1364 GSTPTE PteSrc = pPTSrc->a[iPTSrc];
1365 const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1366 PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1367 Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx %s\n",
1368 GCPtrPage, PteSrc.n.u1Present,
1369 PteSrc.n.u1Write & PdeSrc.n.u1Write,
1370 PteSrc.n.u1User & PdeSrc.n.u1User,
1371 (uint64_t)PteSrc.u,
1372 SHW_PTE_LOG64(pPTDst->a[iPTDst]),
1373 SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
1374 }
1375 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePage4KBPages));
1376 PGM_INVL_PG(pVCpu, GCPtrPage);
1377 }
1378 else
1379 {
1380 /*
1381 * The page table address changed.
1382 */
1383 LogFlow(("InvalidatePage: Out-of-sync at %RGp PdeSrc=%RX64 PdeDst=%RX64 ShwGCPhys=%RGp iPDDst=%#x\n",
1384 GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, iPDDst));
1385 pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1386 ASMAtomicWriteSize(pPdeDst, 0);
1387 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1388 PGM_INVL_VCPU_TLBS(pVCpu);
1389 }
1390 }
1391 else
1392 {
1393 /*
1394 * 2/4MB - page.
1395 */
1396 /* Before freeing the page, check if anything really changed. */
1397 PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1398 RTGCPHYS GCPhys = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
1399# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1400 /* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1401 GCPhys = PGM_A20_APPLY(pVCpu, GCPhys | (GCPtrPage & (1 << X86_PD_PAE_SHIFT)));
1402# endif
1403 if ( pShwPage->GCPhys == GCPhys
1404 && pShwPage->enmKind == BTH_PGMPOOLKIND_PT_FOR_BIG)
1405 {
1406 /* ASSUMES a the given bits are identical for 4M and normal PDEs */
1407 /** @todo This test is wrong as it cannot check the G bit!
1408 * FIXME */
1409 if ( (PdeSrc.u & (X86_PDE_P | X86_PDE_RW | X86_PDE_US))
1410 == (PdeDst.u & (X86_PDE_P | X86_PDE_RW | X86_PDE_US))
1411 && ( PdeSrc.b.u1Dirty /** @todo rainy day: What about read-only 4M pages? not very common, but still... */
1412 || (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)))
1413 {
1414 LogFlow(("Skipping flush for big page containing %RGv (PD=%X .u=%RX64)-> nothing has changed!\n", GCPtrPage, iPDSrc, PdeSrc.u));
1415 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePage4MBPagesSkip));
1416 return VINF_SUCCESS;
1417 }
1418 }
1419
1420 /*
1421 * Ok, the page table is present and it's been changed in the guest.
1422 * If we're in host context, we'll just mark it as not present taking the lazy approach.
1423 * We could do this for some flushes in GC too, but we need an algorithm for
1424 * deciding which 4MB pages containing code likely to be executed very soon.
1425 */
1426 LogFlow(("InvalidatePage: Out-of-sync PD at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
1427 GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1428 pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1429 ASMAtomicWriteSize(pPdeDst, 0);
1430 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePage4MBPages));
1431 PGM_INVL_BIG_PG(pVCpu, GCPtrPage);
1432 }
1433 }
1434 else
1435 {
1436 /*
1437 * Page directory is not present, mark shadow PDE not present.
1438 */
1439 if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
1440 {
1441 pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1442 ASMAtomicWriteSize(pPdeDst, 0);
1443 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePagePDNPs));
1444 PGM_INVL_PG(pVCpu, GCPtrPage);
1445 }
1446 else
1447 {
1448 Assert(pgmMapAreMappingsEnabled(pVM));
1449 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePagePDMappings));
1450 }
1451 }
1452 return rc;
1453
1454#else /* guest real and protected mode */
1455 /* There's no such thing as InvalidatePage when paging is disabled, so just ignore. */
1456 NOREF(pVCpu); NOREF(GCPtrPage);
1457 return VINF_SUCCESS;
1458#endif
1459}
1460
1461
1462/**
1463 * Update the tracking of shadowed pages.
1464 *
1465 * @param pVCpu Pointer to the VMCPU.
1466 * @param pShwPage The shadow page.
1467 * @param HCPhys The physical page we is being dereferenced.
1468 * @param iPte Shadow PTE index
1469 * @param GCPhysPage Guest physical address (only valid if pShwPage->fDirty is set)
1470 */
1471DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVMCPU pVCpu, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys, uint16_t iPte,
1472 RTGCPHYS GCPhysPage)
1473{
1474 PVM pVM = pVCpu->CTX_SUFF(pVM);
1475
1476# if defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT) \
1477 && PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
1478 && (PGM_GST_TYPE == PGM_TYPE_PAE || PGM_GST_TYPE == PGM_TYPE_AMD64 || PGM_SHW_TYPE == PGM_TYPE_PAE /* pae/32bit combo */)
1479
1480 /* Use the hint we retrieved from the cached guest PT. */
1481 if (pShwPage->fDirty)
1482 {
1483 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1484
1485 Assert(pShwPage->cPresent);
1486 Assert(pPool->cPresent);
1487 pShwPage->cPresent--;
1488 pPool->cPresent--;
1489
1490 PPGMPAGE pPhysPage = pgmPhysGetPage(pVM, GCPhysPage);
1491 AssertRelease(pPhysPage);
1492 pgmTrackDerefGCPhys(pPool, pShwPage, pPhysPage, iPte);
1493 return;
1494 }
1495# else
1496 NOREF(GCPhysPage);
1497# endif
1498
1499 STAM_PROFILE_START(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackDeref, a);
1500 LogFlow(("SyncPageWorkerTrackDeref: Damn HCPhys=%RHp pShwPage->idx=%#x!!!\n", HCPhys, pShwPage->idx));
1501
1502 /** @todo If this turns out to be a bottle neck (*very* likely) two things can be done:
1503 * 1. have a medium sized HCPhys -> GCPhys TLB (hash?)
1504 * 2. write protect all shadowed pages. I.e. implement caching.
1505 */
1506 /** @todo duplicated in the 2nd half of pgmPoolTracDerefGCPhysHint */
1507
1508 /*
1509 * Find the guest address.
1510 */
1511 for (PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRangesX);
1512 pRam;
1513 pRam = pRam->CTX_SUFF(pNext))
1514 {
1515 unsigned iPage = pRam->cb >> PAGE_SHIFT;
1516 while (iPage-- > 0)
1517 {
1518 if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
1519 {
1520 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1521
1522 Assert(pShwPage->cPresent);
1523 Assert(pPool->cPresent);
1524 pShwPage->cPresent--;
1525 pPool->cPresent--;
1526
1527 pgmTrackDerefGCPhys(pPool, pShwPage, &pRam->aPages[iPage], iPte);
1528 STAM_PROFILE_STOP(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackDeref, a);
1529 return;
1530 }
1531 }
1532 }
1533
1534 for (;;)
1535 AssertReleaseMsgFailed(("HCPhys=%RHp wasn't found!\n", HCPhys));
1536}
1537
1538
1539/**
1540 * Update the tracking of shadowed pages.
1541 *
1542 * @param pVCpu Pointer to the VMCPU.
1543 * @param pShwPage The shadow page.
1544 * @param u16 The top 16-bit of the pPage->HCPhys.
1545 * @param pPage Pointer to the guest page. this will be modified.
1546 * @param iPTDst The index into the shadow table.
1547 */
1548DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackAddref)(PVMCPU pVCpu, PPGMPOOLPAGE pShwPage, uint16_t u16, PPGMPAGE pPage, const unsigned iPTDst)
1549{
1550 PVM pVM = pVCpu->CTX_SUFF(pVM);
1551
1552 /*
1553 * Just deal with the simple first time here.
1554 */
1555 if (!u16)
1556 {
1557 STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackVirgin);
1558 u16 = PGMPOOL_TD_MAKE(1, pShwPage->idx);
1559 /* Save the page table index. */
1560 PGM_PAGE_SET_PTE_INDEX(pVM, pPage, iPTDst);
1561 }
1562 else
1563 u16 = pgmPoolTrackPhysExtAddref(pVM, pPage, u16, pShwPage->idx, iPTDst);
1564
1565 /* write back */
1566 Log2(("SyncPageWorkerTrackAddRef: u16=%#x->%#x iPTDst=%#x\n", u16, PGM_PAGE_GET_TRACKING(pPage), iPTDst));
1567 PGM_PAGE_SET_TRACKING(pVM, pPage, u16);
1568
1569 /* update statistics. */
1570 pVM->pgm.s.CTX_SUFF(pPool)->cPresent++;
1571 pShwPage->cPresent++;
1572 if (pShwPage->iFirstPresent > iPTDst)
1573 pShwPage->iFirstPresent = iPTDst;
1574}
1575
1576
1577/**
1578 * Modifies a shadow PTE to account for access handlers.
1579 *
1580 * @param pVM Pointer to the VM.
1581 * @param pPage The page in question.
1582 * @param fPteSrc The shadowed flags of the source PTE. Must include the
1583 * A (accessed) bit so it can be emulated correctly.
1584 * @param pPteDst The shadow PTE (output). This is temporary storage and
1585 * does not need to be set atomically.
1586 */
1587DECLINLINE(void) PGM_BTH_NAME(SyncHandlerPte)(PVM pVM, PCPGMPAGE pPage, uint64_t fPteSrc, PSHWPTE pPteDst)
1588{
1589 NOREF(pVM);
1590 /** @todo r=bird: Are we actually handling dirty and access bits for pages with access handlers correctly? No.
1591 * Update: \#PF should deal with this before or after calling the handlers. It has all the info to do the job efficiently. */
1592 if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1593 {
1594 LogFlow(("SyncHandlerPte: monitored page (%R[pgmpage]) -> mark read-only\n", pPage));
1595#if PGM_SHW_TYPE == PGM_TYPE_EPT
1596 pPteDst->u = PGM_PAGE_GET_HCPHYS(pPage);
1597 pPteDst->n.u1Present = 1;
1598 pPteDst->n.u1Execute = 1;
1599 pPteDst->n.u1IgnorePAT = 1;
1600 pPteDst->n.u3EMT = VMX_EPT_MEMTYPE_WB;
1601 /* PteDst.n.u1Write = 0 && PteDst.n.u1Size = 0 */
1602#else
1603 if (fPteSrc & X86_PTE_A)
1604 {
1605 SHW_PTE_SET(*pPteDst, fPteSrc | PGM_PAGE_GET_HCPHYS(pPage));
1606 SHW_PTE_SET_RO(*pPteDst);
1607 }
1608 else
1609 SHW_PTE_SET(*pPteDst, 0);
1610#endif
1611 }
1612#ifdef PGM_WITH_MMIO_OPTIMIZATIONS
1613# if PGM_SHW_TYPE == PGM_TYPE_EPT || PGM_SHW_TYPE == PGM_TYPE_PAE || PGM_SHW_TYPE == PGM_TYPE_AMD64
1614 else if ( PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
1615 && ( BTH_IS_NP_ACTIVE(pVM)
1616 || (fPteSrc & (X86_PTE_RW | X86_PTE_US)) == X86_PTE_RW) /** @todo Remove X86_PTE_US here and pGstWalk->Core.fEffectiveUS before the sync page test. */
1617# if PGM_SHW_TYPE == PGM_TYPE_AMD64
1618 && pVM->pgm.s.fLessThan52PhysicalAddressBits
1619# endif
1620 )
1621 {
1622 LogFlow(("SyncHandlerPte: MMIO page -> invalid \n"));
1623# if PGM_SHW_TYPE == PGM_TYPE_EPT
1624 /* 25.2.3.1: Reserved physical address bit -> EPT Misconfiguration (exit 49) */
1625 pPteDst->u = pVM->pgm.s.HCPhysInvMmioPg;
1626 /* 25.2.3.1: bits 2:0 = 010b -> EPT Misconfiguration (exit 49) */
1627 pPteDst->n.u1Present = 0;
1628 pPteDst->n.u1Write = 1;
1629 pPteDst->n.u1Execute = 0;
1630 /* 25.2.3.1: leaf && 2:0 != 0 && u3Emt in {2, 3, 7} -> EPT Misconfiguration */
1631 pPteDst->n.u3EMT = 7;
1632# else
1633 /* Set high page frame bits that MBZ (bankers on PAE, CPU dependent on AMD64). */
1634 SHW_PTE_SET(*pPteDst, pVM->pgm.s.HCPhysInvMmioPg | X86_PTE_PAE_MBZ_MASK_NO_NX | X86_PTE_P);
1635# endif
1636 }
1637# endif
1638#endif /* PGM_WITH_MMIO_OPTIMIZATIONS */
1639 else
1640 {
1641 LogFlow(("SyncHandlerPte: monitored page (%R[pgmpage]) -> mark not present\n", pPage));
1642 SHW_PTE_SET(*pPteDst, 0);
1643 }
1644 /** @todo count these kinds of entries. */
1645}
1646
1647
1648/**
1649 * Creates a 4K shadow page for a guest page.
1650 *
1651 * For 4M pages the caller must convert the PDE4M to a PTE, this includes adjusting the
1652 * physical address. The PdeSrc argument only the flags are used. No page
1653 * structured will be mapped in this function.
1654 *
1655 * @param pVCpu Pointer to the VMCPU.
1656 * @param pPteDst Destination page table entry.
1657 * @param PdeSrc Source page directory entry (i.e. Guest OS page directory entry).
1658 * Can safely assume that only the flags are being used.
1659 * @param PteSrc Source page table entry (i.e. Guest OS page table entry).
1660 * @param pShwPage Pointer to the shadow page.
1661 * @param iPTDst The index into the shadow table.
1662 *
1663 * @remark Not used for 2/4MB pages!
1664 */
1665#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1666static void PGM_BTH_NAME(SyncPageWorker)(PVMCPU pVCpu, PSHWPTE pPteDst, GSTPDE PdeSrc, GSTPTE PteSrc,
1667 PPGMPOOLPAGE pShwPage, unsigned iPTDst)
1668#else
1669static void PGM_BTH_NAME(SyncPageWorker)(PVMCPU pVCpu, PSHWPTE pPteDst, RTGCPHYS GCPhysPage, PPGMPOOLPAGE pShwPage, unsigned iPTDst)
1670#endif
1671{
1672 PVM pVM = pVCpu->CTX_SUFF(pVM);
1673 RTGCPHYS GCPhysOldPage = NIL_RTGCPHYS;
1674
1675#if defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT) \
1676 && PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
1677 && (PGM_GST_TYPE == PGM_TYPE_PAE || PGM_GST_TYPE == PGM_TYPE_AMD64 || PGM_SHW_TYPE == PGM_TYPE_PAE /* pae/32bit combo */)
1678
1679 if (pShwPage->fDirty)
1680 {
1681 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1682 PGSTPT pGstPT;
1683
1684 /* Note that iPTDst can be used to index the guest PT even in the pae/32bit combo as we copy only half the table; see pgmPoolAddDirtyPage. */
1685 pGstPT = (PGSTPT)&pPool->aDirtyPages[pShwPage->idxDirtyEntry].aPage[0];
1686 GCPhysOldPage = GST_GET_PTE_GCPHYS(pGstPT->a[iPTDst]);
1687 pGstPT->a[iPTDst].u = PteSrc.u;
1688 }
1689#else
1690 Assert(!pShwPage->fDirty);
1691#endif
1692
1693#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1694 if ( PteSrc.n.u1Present
1695 && GST_IS_PTE_VALID(pVCpu, PteSrc))
1696#endif
1697 {
1698# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1699 RTGCPHYS GCPhysPage = GST_GET_PTE_GCPHYS(PteSrc);
1700# endif
1701 PGM_A20_ASSERT_MASKED(pVCpu, GCPhysPage);
1702
1703 /*
1704 * Find the ram range.
1705 */
1706 PPGMPAGE pPage;
1707 int rc = pgmPhysGetPageEx(pVM, GCPhysPage, &pPage);
1708 if (RT_SUCCESS(rc))
1709 {
1710 /* Ignore ballooned pages.
1711 Don't return errors or use a fatal assert here as part of a
1712 shadow sync range might included ballooned pages. */
1713 if (PGM_PAGE_IS_BALLOONED(pPage))
1714 {
1715 Assert(!SHW_PTE_IS_P(*pPteDst)); /** @todo user tracking needs updating if this triggers. */
1716 return;
1717 }
1718
1719#ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
1720 /* Make the page writable if necessary. */
1721 if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
1722 && ( PGM_PAGE_IS_ZERO(pPage)
1723# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1724 || ( PteSrc.n.u1Write
1725# else
1726 || ( 1
1727# endif
1728 && PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
1729# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
1730 && PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
1731# endif
1732# ifdef VBOX_WITH_PAGE_SHARING
1733 && PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
1734# endif
1735 )
1736 )
1737 )
1738 {
1739 rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhysPage);
1740 AssertRC(rc);
1741 }
1742#endif
1743
1744 /*
1745 * Make page table entry.
1746 */
1747 SHWPTE PteDst;
1748# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1749 uint64_t fGstShwPteFlags = GST_GET_PTE_SHW_FLAGS(pVCpu, PteSrc);
1750# else
1751 uint64_t fGstShwPteFlags = X86_PTE_P | X86_PTE_RW | X86_PTE_US | X86_PTE_A | X86_PTE_D;
1752# endif
1753 if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1754 PGM_BTH_NAME(SyncHandlerPte)(pVM, pPage, fGstShwPteFlags, &PteDst);
1755 else
1756 {
1757#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1758 /*
1759 * If the page or page directory entry is not marked accessed,
1760 * we mark the page not present.
1761 */
1762 if (!PteSrc.n.u1Accessed || !PdeSrc.n.u1Accessed)
1763 {
1764 LogFlow(("SyncPageWorker: page and or page directory not accessed -> mark not present\n"));
1765 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,AccessedPage));
1766 SHW_PTE_SET(PteDst, 0);
1767 }
1768 /*
1769 * If the page is not flagged as dirty and is writable, then make it read-only, so we can set the dirty bit
1770 * when the page is modified.
1771 */
1772 else if (!PteSrc.n.u1Dirty && (PdeSrc.n.u1Write & PteSrc.n.u1Write))
1773 {
1774 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPage));
1775 SHW_PTE_SET(PteDst,
1776 fGstShwPteFlags
1777 | PGM_PAGE_GET_HCPHYS(pPage)
1778 | PGM_PTFLAGS_TRACK_DIRTY);
1779 SHW_PTE_SET_RO(PteDst);
1780 }
1781 else
1782#endif
1783 {
1784 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageSkipped));
1785#if PGM_SHW_TYPE == PGM_TYPE_EPT
1786 PteDst.u = PGM_PAGE_GET_HCPHYS(pPage);
1787 PteDst.n.u1Present = 1;
1788 PteDst.n.u1Write = 1;
1789 PteDst.n.u1Execute = 1;
1790 PteDst.n.u1IgnorePAT = 1;
1791 PteDst.n.u3EMT = VMX_EPT_MEMTYPE_WB;
1792 /* PteDst.n.u1Size = 0 */
1793#else
1794 SHW_PTE_SET(PteDst, fGstShwPteFlags | PGM_PAGE_GET_HCPHYS(pPage));
1795#endif
1796 }
1797
1798 /*
1799 * Make sure only allocated pages are mapped writable.
1800 */
1801 if ( SHW_PTE_IS_P_RW(PteDst)
1802 && PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
1803 {
1804 /* Still applies to shared pages. */
1805 Assert(!PGM_PAGE_IS_ZERO(pPage));
1806 SHW_PTE_SET_RO(PteDst); /** @todo this isn't quite working yet. Why, isn't it? */
1807 Log3(("SyncPageWorker: write-protecting %RGp pPage=%R[pgmpage]at iPTDst=%d\n", GCPhysPage, pPage, iPTDst));
1808 }
1809 }
1810
1811 /*
1812 * Keep user track up to date.
1813 */
1814 if (SHW_PTE_IS_P(PteDst))
1815 {
1816 if (!SHW_PTE_IS_P(*pPteDst))
1817 PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1818 else if (SHW_PTE_GET_HCPHYS(*pPteDst) != SHW_PTE_GET_HCPHYS(PteDst))
1819 {
1820 Log2(("SyncPageWorker: deref! *pPteDst=%RX64 PteDst=%RX64\n", SHW_PTE_LOG64(*pPteDst), SHW_PTE_LOG64(PteDst)));
1821 PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPteDst), iPTDst, GCPhysOldPage);
1822 PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1823 }
1824 }
1825 else if (SHW_PTE_IS_P(*pPteDst))
1826 {
1827 Log2(("SyncPageWorker: deref! *pPteDst=%RX64\n", SHW_PTE_LOG64(*pPteDst)));
1828 PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPteDst), iPTDst, GCPhysOldPage);
1829 }
1830
1831 /*
1832 * Update statistics and commit the entry.
1833 */
1834#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1835 if (!PteSrc.n.u1Global)
1836 pShwPage->fSeenNonGlobal = true;
1837#endif
1838 SHW_PTE_ATOMIC_SET2(*pPteDst, PteDst);
1839 return;
1840 }
1841
1842/** @todo count these three different kinds. */
1843 Log2(("SyncPageWorker: invalid address in Pte\n"));
1844 }
1845#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1846 else if (!PteSrc.n.u1Present)
1847 Log2(("SyncPageWorker: page not present in Pte\n"));
1848 else
1849 Log2(("SyncPageWorker: invalid Pte\n"));
1850#endif
1851
1852 /*
1853 * The page is not present or the PTE is bad. Replace the shadow PTE by
1854 * an empty entry, making sure to keep the user tracking up to date.
1855 */
1856 if (SHW_PTE_IS_P(*pPteDst))
1857 {
1858 Log2(("SyncPageWorker: deref! *pPteDst=%RX64\n", SHW_PTE_LOG64(*pPteDst)));
1859 PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPteDst), iPTDst, GCPhysOldPage);
1860 }
1861 SHW_PTE_ATOMIC_SET(*pPteDst, 0);
1862}
1863
1864
1865/**
1866 * Syncs a guest OS page.
1867 *
1868 * There are no conflicts at this point, neither is there any need for
1869 * page table allocations.
1870 *
1871 * When called in PAE or AMD64 guest mode, the guest PDPE shall be valid.
1872 * When called in AMD64 guest mode, the guest PML4E shall be valid.
1873 *
1874 * @returns VBox status code.
1875 * @returns VINF_PGM_SYNCPAGE_MODIFIED_PDE if it modifies the PDE in any way.
1876 * @param pVCpu Pointer to the VMCPU.
1877 * @param PdeSrc Page directory entry of the guest.
1878 * @param GCPtrPage Guest context page address.
1879 * @param cPages Number of pages to sync (PGM_SYNC_N_PAGES) (default=1).
1880 * @param uErr Fault error (X86_TRAP_PF_*).
1881 */
1882static int PGM_BTH_NAME(SyncPage)(PVMCPU pVCpu, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr)
1883{
1884 PVM pVM = pVCpu->CTX_SUFF(pVM);
1885 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool); NOREF(pPool);
1886 LogFlow(("SyncPage: GCPtrPage=%RGv cPages=%u uErr=%#x\n", GCPtrPage, cPages, uErr));
1887
1888 PGM_LOCK_ASSERT_OWNER(pVM);
1889
1890#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
1891 || PGM_GST_TYPE == PGM_TYPE_PAE \
1892 || PGM_GST_TYPE == PGM_TYPE_AMD64) \
1893 && PGM_SHW_TYPE != PGM_TYPE_NESTED \
1894 && PGM_SHW_TYPE != PGM_TYPE_EPT
1895
1896 /*
1897 * Assert preconditions.
1898 */
1899 Assert(PdeSrc.n.u1Present);
1900 Assert(cPages);
1901# if 0 /* rarely useful; leave for debugging. */
1902 STAM_COUNTER_INC(&pVCpu->pgm.s.StatSyncPagePD[(GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK]);
1903# endif
1904
1905 /*
1906 * Get the shadow PDE, find the shadow page table in the pool.
1907 */
1908# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1909 const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1910 PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
1911
1912 /* Fetch the pgm pool shadow descriptor. */
1913 PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
1914 Assert(pShwPde);
1915
1916# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1917 const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1918 PPGMPOOLPAGE pShwPde = NULL;
1919 PX86PDPAE pPDDst;
1920
1921 /* Fetch the pgm pool shadow descriptor. */
1922 int rc2 = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
1923 AssertRCSuccessReturn(rc2, rc2);
1924 Assert(pShwPde);
1925
1926 pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
1927 PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1928
1929# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1930 const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1931 const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1932 PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
1933 PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
1934
1935 int rc2 = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
1936 AssertRCSuccessReturn(rc2, rc2);
1937 Assert(pPDDst && pPdptDst);
1938 PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1939# endif
1940 SHWPDE PdeDst = *pPdeDst;
1941
1942 /*
1943 * - In the guest SMP case we could have blocked while another VCPU reused
1944 * this page table.
1945 * - With W7-64 we may also take this path when the A bit is cleared on
1946 * higher level tables (PDPE/PML4E). The guest does not invalidate the
1947 * relevant TLB entries. If we're write monitoring any page mapped by
1948 * the modified entry, we may end up here with a "stale" TLB entry.
1949 */
1950 if (!PdeDst.n.u1Present)
1951 {
1952 Log(("CPU%u: SyncPage: Pde at %RGv changed behind our back? (pPdeDst=%p/%RX64) uErr=%#x\n", pVCpu->idCpu, GCPtrPage, pPdeDst, (uint64_t)PdeDst.u, (uint32_t)uErr));
1953 AssertMsg(pVM->cCpus > 1 || (uErr & (X86_TRAP_PF_P | X86_TRAP_PF_RW)) == (X86_TRAP_PF_P | X86_TRAP_PF_RW),
1954 ("Unexpected missing PDE p=%p/%RX64 uErr=%#x\n", pPdeDst, (uint64_t)PdeDst.u, (uint32_t)uErr));
1955 if (uErr & X86_TRAP_PF_P)
1956 PGM_INVL_PG(pVCpu, GCPtrPage);
1957 return VINF_SUCCESS; /* force the instruction to be executed again. */
1958 }
1959
1960 PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1961 Assert(pShwPage);
1962
1963# if PGM_GST_TYPE == PGM_TYPE_AMD64
1964 /* Fetch the pgm pool shadow descriptor. */
1965 PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
1966 Assert(pShwPde);
1967# endif
1968
1969 /*
1970 * Check that the page is present and that the shadow PDE isn't out of sync.
1971 */
1972 const bool fBigPage = PdeSrc.b.u1Size && GST_IS_PSE_ACTIVE(pVCpu);
1973 const bool fPdeValid = !fBigPage ? GST_IS_PDE_VALID(pVCpu, PdeSrc) : GST_IS_BIG_PDE_VALID(pVCpu, PdeSrc);
1974 RTGCPHYS GCPhys;
1975 if (!fBigPage)
1976 {
1977 GCPhys = GST_GET_PDE_GCPHYS(PdeSrc);
1978# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1979 /* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1980 GCPhys = PGM_A20_APPLY(pVCpu, GCPhys | ((iPDDst & 1) * (PAGE_SIZE / 2)));
1981# endif
1982 }
1983 else
1984 {
1985 GCPhys = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
1986# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1987 /* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1988 GCPhys = PGM_A20_APPLY(pVCpu, GCPhys | (GCPtrPage & (1 << X86_PD_PAE_SHIFT)));
1989# endif
1990 }
1991 /** @todo This doesn't check the G bit of 2/4MB pages. FIXME */
1992 if ( fPdeValid
1993 && pShwPage->GCPhys == GCPhys
1994 && PdeSrc.n.u1Present
1995 && PdeSrc.n.u1User == PdeDst.n.u1User
1996 && (PdeSrc.n.u1Write == PdeDst.n.u1Write || !PdeDst.n.u1Write)
1997# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
1998 && (PdeSrc.n.u1NoExecute == PdeDst.n.u1NoExecute || !GST_IS_NX_ACTIVE(pVCpu))
1999# endif
2000 )
2001 {
2002 /*
2003 * Check that the PDE is marked accessed already.
2004 * Since we set the accessed bit *before* getting here on a #PF, this
2005 * check is only meant for dealing with non-#PF'ing paths.
2006 */
2007 if (PdeSrc.n.u1Accessed)
2008 {
2009 PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2010 if (!fBigPage)
2011 {
2012 /*
2013 * 4KB Page - Map the guest page table.
2014 */
2015 PGSTPT pPTSrc;
2016 int rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GST_GET_PDE_GCPHYS(PdeSrc), &pPTSrc);
2017 if (RT_SUCCESS(rc))
2018 {
2019# ifdef PGM_SYNC_N_PAGES
2020 Assert(cPages == 1 || !(uErr & X86_TRAP_PF_P));
2021 if ( cPages > 1
2022 && !(uErr & X86_TRAP_PF_P)
2023 && !VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY))
2024 {
2025 /*
2026 * This code path is currently only taken when the caller is PGMTrap0eHandler
2027 * for non-present pages!
2028 *
2029 * We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
2030 * deal with locality.
2031 */
2032 unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2033# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2034 /* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2035 const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
2036# else
2037 const unsigned offPTSrc = 0;
2038# endif
2039 const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2040 if (iPTDst < PGM_SYNC_NR_PAGES / 2)
2041 iPTDst = 0;
2042 else
2043 iPTDst -= PGM_SYNC_NR_PAGES / 2;
2044
2045 for (; iPTDst < iPTDstEnd; iPTDst++)
2046 {
2047 const PGSTPTE pPteSrc = &pPTSrc->a[offPTSrc + iPTDst];
2048
2049 if ( pPteSrc->n.u1Present
2050 && !SHW_PTE_IS_P(pPTDst->a[iPTDst]))
2051 {
2052 RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(GST_PT_MASK << GST_PT_SHIFT)) | ((offPTSrc + iPTDst) << PAGE_SHIFT);
2053 NOREF(GCPtrCurPage);
2054# ifdef VBOX_WITH_RAW_MODE_NOT_R0
2055 /*
2056 * Assuming kernel code will be marked as supervisor - and not as user level
2057 * and executed using a conforming code selector - And marked as readonly.
2058 * Also assume that if we're monitoring a page, it's of no interest to CSAM.
2059 */
2060 PPGMPAGE pPage;
2061 if ( ((PdeSrc.u & pPteSrc->u) & (X86_PTE_RW | X86_PTE_US))
2062 || iPTDst == ((GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK) /* always sync GCPtrPage */
2063 || !CSAMDoesPageNeedScanning(pVM, GCPtrCurPage)
2064 || ( (pPage = pgmPhysGetPage(pVM, pPteSrc->u & GST_PTE_PG_MASK))
2065 && PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2066 )
2067# endif /* else: CSAM not active */
2068 PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, *pPteSrc, pShwPage, iPTDst);
2069 Log2(("SyncPage: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
2070 GCPtrCurPage, pPteSrc->n.u1Present,
2071 pPteSrc->n.u1Write & PdeSrc.n.u1Write,
2072 pPteSrc->n.u1User & PdeSrc.n.u1User,
2073 (uint64_t)pPteSrc->u,
2074 SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2075 SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2076 }
2077 }
2078 }
2079 else
2080# endif /* PGM_SYNC_N_PAGES */
2081 {
2082 const unsigned iPTSrc = (GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK;
2083 GSTPTE PteSrc = pPTSrc->a[iPTSrc];
2084 const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2085 PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2086 Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx %s\n",
2087 GCPtrPage, PteSrc.n.u1Present,
2088 PteSrc.n.u1Write & PdeSrc.n.u1Write,
2089 PteSrc.n.u1User & PdeSrc.n.u1User,
2090 (uint64_t)PteSrc.u,
2091 SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2092 SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2093 }
2094 }
2095 else /* MMIO or invalid page: emulated in #PF handler. */
2096 {
2097 LogFlow(("PGM_GCPHYS_2_PTR %RGp failed with %Rrc\n", GCPhys, rc));
2098 Assert(!SHW_PTE_IS_P(pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK]));
2099 }
2100 }
2101 else
2102 {
2103 /*
2104 * 4/2MB page - lazy syncing shadow 4K pages.
2105 * (There are many causes of getting here, it's no longer only CSAM.)
2106 */
2107 /* Calculate the GC physical address of this 4KB shadow page. */
2108 GCPhys = PGM_A20_APPLY(pVCpu, GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc) | (GCPtrPage & GST_BIG_PAGE_OFFSET_MASK));
2109 /* Find ram range. */
2110 PPGMPAGE pPage;
2111 int rc = pgmPhysGetPageEx(pVM, GCPhys, &pPage);
2112 if (RT_SUCCESS(rc))
2113 {
2114 AssertFatalMsg(!PGM_PAGE_IS_BALLOONED(pPage), ("Unexpected ballooned page at %RGp\n", GCPhys));
2115
2116# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
2117 /* Try to make the page writable if necessary. */
2118 if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
2119 && ( PGM_PAGE_IS_ZERO(pPage)
2120 || ( PdeSrc.n.u1Write
2121 && PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
2122# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
2123 && PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
2124# endif
2125# ifdef VBOX_WITH_PAGE_SHARING
2126 && PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
2127# endif
2128 )
2129 )
2130 )
2131 {
2132 rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
2133 AssertRC(rc);
2134 }
2135# endif
2136
2137 /*
2138 * Make shadow PTE entry.
2139 */
2140 SHWPTE PteDst;
2141 if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2142 PGM_BTH_NAME(SyncHandlerPte)(pVM, pPage, GST_GET_BIG_PDE_SHW_FLAGS_4_PTE(pVCpu, PdeSrc), &PteDst);
2143 else
2144 SHW_PTE_SET(PteDst, GST_GET_BIG_PDE_SHW_FLAGS_4_PTE(pVCpu, PdeSrc) | PGM_PAGE_GET_HCPHYS(pPage));
2145
2146 const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2147 if ( SHW_PTE_IS_P(PteDst)
2148 && !SHW_PTE_IS_P(pPTDst->a[iPTDst]))
2149 PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
2150
2151 /* Make sure only allocated pages are mapped writable. */
2152 if ( SHW_PTE_IS_P_RW(PteDst)
2153 && PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
2154 {
2155 /* Still applies to shared pages. */
2156 Assert(!PGM_PAGE_IS_ZERO(pPage));
2157 SHW_PTE_SET_RO(PteDst); /** @todo this isn't quite working yet... */
2158 Log3(("SyncPage: write-protecting %RGp pPage=%R[pgmpage] at %RGv\n", GCPhys, pPage, GCPtrPage));
2159 }
2160
2161 SHW_PTE_ATOMIC_SET2(pPTDst->a[iPTDst], PteDst);
2162
2163 /*
2164 * If the page is not flagged as dirty and is writable, then make it read-only
2165 * at PD level, so we can set the dirty bit when the page is modified.
2166 *
2167 * ASSUMES that page access handlers are implemented on page table entry level.
2168 * Thus we will first catch the dirty access and set PDE.D and restart. If
2169 * there is an access handler, we'll trap again and let it work on the problem.
2170 */
2171 /** @todo r=bird: figure out why we need this here, SyncPT should've taken care of this already.
2172 * As for invlpg, it simply frees the whole shadow PT.
2173 * ...It's possibly because the guest clears it and the guest doesn't really tell us... */
2174 if ( !PdeSrc.b.u1Dirty
2175 && PdeSrc.b.u1Write)
2176 {
2177 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageBig));
2178 PdeDst.u |= PGM_PDFLAGS_TRACK_DIRTY;
2179 PdeDst.n.u1Write = 0;
2180 }
2181 else
2182 {
2183 PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
2184 PdeDst.n.u1Write = PdeSrc.n.u1Write;
2185 }
2186 ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2187 Log2(("SyncPage: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} GCPhys=%RGp%s\n",
2188 GCPtrPage, PdeSrc.n.u1Present, PdeSrc.n.u1Write, PdeSrc.n.u1User, (uint64_t)PdeSrc.u, GCPhys,
2189 PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2190 }
2191 else
2192 {
2193 LogFlow(("PGM_GCPHYS_2_PTR %RGp (big) failed with %Rrc\n", GCPhys, rc));
2194 /** @todo must wipe the shadow page table entry in this
2195 * case. */
2196 }
2197 }
2198 PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2199 return VINF_SUCCESS;
2200 }
2201
2202 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPagePDNAs));
2203 }
2204 else if (fPdeValid)
2205 {
2206 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPagePDOutOfSync));
2207 Log2(("SyncPage: Out-Of-Sync PDE at %RGp PdeSrc=%RX64 PdeDst=%RX64 (GCPhys %RGp vs %RGp)\n",
2208 GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, GCPhys));
2209 }
2210 else
2211 {
2212/// @todo STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPagePDOutOfSyncAndInvalid));
2213 Log2(("SyncPage: Bad PDE at %RGp PdeSrc=%RX64 PdeDst=%RX64 (GCPhys %RGp vs %RGp)\n",
2214 GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, GCPhys));
2215 }
2216
2217 /*
2218 * Mark the PDE not present. Restart the instruction and let #PF call SyncPT.
2219 * Yea, I'm lazy.
2220 */
2221 pgmPoolFreeByPage(pPool, pShwPage, pShwPde->idx, iPDDst);
2222 ASMAtomicWriteSize(pPdeDst, 0);
2223
2224 PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2225 PGM_INVL_VCPU_TLBS(pVCpu);
2226 return VINF_PGM_SYNCPAGE_MODIFIED_PDE;
2227
2228
2229#elif (PGM_GST_TYPE == PGM_TYPE_REAL || PGM_GST_TYPE == PGM_TYPE_PROT) \
2230 && PGM_SHW_TYPE != PGM_TYPE_NESTED \
2231 && (PGM_SHW_TYPE != PGM_TYPE_EPT || PGM_GST_TYPE == PGM_TYPE_PROT) \
2232 && !defined(IN_RC)
2233 NOREF(PdeSrc);
2234
2235# ifdef PGM_SYNC_N_PAGES
2236 /*
2237 * Get the shadow PDE, find the shadow page table in the pool.
2238 */
2239# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2240 X86PDE PdeDst = pgmShwGet32BitPDE(pVCpu, GCPtrPage);
2241
2242# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2243 X86PDEPAE PdeDst = pgmShwGetPaePDE(pVCpu, GCPtrPage);
2244
2245# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2246 const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2247 const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64; NOREF(iPdpt);
2248 PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
2249 X86PDEPAE PdeDst;
2250 PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
2251
2252 int rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2253 AssertRCSuccessReturn(rc, rc);
2254 Assert(pPDDst && pPdptDst);
2255 PdeDst = pPDDst->a[iPDDst];
2256# elif PGM_SHW_TYPE == PGM_TYPE_EPT
2257 const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2258 PEPTPD pPDDst;
2259 EPTPDE PdeDst;
2260
2261 int rc = pgmShwGetEPTPDPtr(pVCpu, GCPtrPage, NULL, &pPDDst);
2262 if (rc != VINF_SUCCESS)
2263 {
2264 AssertRC(rc);
2265 return rc;
2266 }
2267 Assert(pPDDst);
2268 PdeDst = pPDDst->a[iPDDst];
2269# endif
2270 /* In the guest SMP case we could have blocked while another VCPU reused this page table. */
2271 if (!PdeDst.n.u1Present)
2272 {
2273 AssertMsg(pVM->cCpus > 1, ("Unexpected missing PDE %RX64\n", (uint64_t)PdeDst.u));
2274 Log(("CPU%d: SyncPage: Pde at %RGv changed behind our back!\n", pVCpu->idCpu, GCPtrPage));
2275 return VINF_SUCCESS; /* force the instruction to be executed again. */
2276 }
2277
2278 /* Can happen in the guest SMP case; other VCPU activated this PDE while we were blocking to handle the page fault. */
2279 if (PdeDst.n.u1Size)
2280 {
2281 Assert(pVM->pgm.s.fNestedPaging);
2282 Log(("CPU%d: SyncPage: Pde (big:%RX64) at %RGv changed behind our back!\n", pVCpu->idCpu, PdeDst.u, GCPtrPage));
2283 return VINF_SUCCESS;
2284 }
2285
2286 /* Mask away the page offset. */
2287 GCPtrPage &= ~((RTGCPTR)0xfff);
2288
2289 PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
2290 PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2291
2292 Assert(cPages == 1 || !(uErr & X86_TRAP_PF_P));
2293 if ( cPages > 1
2294 && !(uErr & X86_TRAP_PF_P)
2295 && !VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY))
2296 {
2297 /*
2298 * This code path is currently only taken when the caller is PGMTrap0eHandler
2299 * for non-present pages!
2300 *
2301 * We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
2302 * deal with locality.
2303 */
2304 unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2305 const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2306 if (iPTDst < PGM_SYNC_NR_PAGES / 2)
2307 iPTDst = 0;
2308 else
2309 iPTDst -= PGM_SYNC_NR_PAGES / 2;
2310 for (; iPTDst < iPTDstEnd; iPTDst++)
2311 {
2312 if (!SHW_PTE_IS_P(pPTDst->a[iPTDst]))
2313 {
2314 RTGCPTR GCPtrCurPage = PGM_A20_APPLY(pVCpu, (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT))
2315 | (iPTDst << PAGE_SHIFT));
2316
2317 PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], GCPtrCurPage, pShwPage, iPTDst);
2318 Log2(("SyncPage: 4K+ %RGv PteSrc:{P=1 RW=1 U=1} PteDst=%08llx%s\n",
2319 GCPtrCurPage,
2320 SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2321 SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2322
2323 if (RT_UNLIKELY(VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY)))
2324 break;
2325 }
2326 else
2327 Log4(("%RGv iPTDst=%x pPTDst->a[iPTDst] %RX64\n", (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) | (iPTDst << PAGE_SHIFT), iPTDst, SHW_PTE_LOG64(pPTDst->a[iPTDst]) ));
2328 }
2329 }
2330 else
2331# endif /* PGM_SYNC_N_PAGES */
2332 {
2333 const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2334 RTGCPTR GCPtrCurPage = PGM_A20_APPLY(pVCpu, (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT))
2335 | (iPTDst << PAGE_SHIFT));
2336
2337 PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], GCPtrCurPage, pShwPage, iPTDst);
2338
2339 Log2(("SyncPage: 4K %RGv PteSrc:{P=1 RW=1 U=1}PteDst=%08llx%s\n",
2340 GCPtrPage,
2341 SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2342 SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2343 }
2344 return VINF_SUCCESS;
2345
2346#else
2347 NOREF(PdeSrc);
2348 AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
2349 return VERR_PGM_NOT_USED_IN_MODE;
2350#endif
2351}
2352
2353
2354#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
2355
2356/**
2357 * CheckPageFault helper for returning a page fault indicating a non-present
2358 * (NP) entry in the page translation structures.
2359 *
2360 * @returns VINF_EM_RAW_GUEST_TRAP.
2361 * @param pVCpu Pointer to the VMCPU.
2362 * @param uErr The error code of the shadow fault. Corrections to
2363 * TRPM's copy will be made if necessary.
2364 * @param GCPtrPage For logging.
2365 * @param uPageFaultLevel For logging.
2366 */
2367DECLINLINE(int) PGM_BTH_NAME(CheckPageFaultReturnNP)(PVMCPU pVCpu, uint32_t uErr, RTGCPTR GCPtrPage, unsigned uPageFaultLevel)
2368{
2369 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyTrackRealPF));
2370 AssertMsg(!(uErr & X86_TRAP_PF_P), ("%#x\n", uErr));
2371 AssertMsg(!(uErr & X86_TRAP_PF_RSVD), ("%#x\n", uErr));
2372 if (uErr & (X86_TRAP_PF_RSVD | X86_TRAP_PF_P))
2373 TRPMSetErrorCode(pVCpu, uErr & ~(X86_TRAP_PF_RSVD | X86_TRAP_PF_P));
2374
2375 Log(("CheckPageFault: real page fault (notp) at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2376 return VINF_EM_RAW_GUEST_TRAP;
2377}
2378
2379
2380/**
2381 * CheckPageFault helper for returning a page fault indicating a reserved bit
2382 * (RSVD) error in the page translation structures.
2383 *
2384 * @returns VINF_EM_RAW_GUEST_TRAP.
2385 * @param pVCpu Pointer to the VMCPU.
2386 * @param uErr The error code of the shadow fault. Corrections to
2387 * TRPM's copy will be made if necessary.
2388 * @param GCPtrPage For logging.
2389 * @param uPageFaultLevel For logging.
2390 */
2391DECLINLINE(int) PGM_BTH_NAME(CheckPageFaultReturnRSVD)(PVMCPU pVCpu, uint32_t uErr, RTGCPTR GCPtrPage, unsigned uPageFaultLevel)
2392{
2393 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyTrackRealPF));
2394 if ((uErr & (X86_TRAP_PF_RSVD | X86_TRAP_PF_P)) != (X86_TRAP_PF_RSVD | X86_TRAP_PF_P))
2395 TRPMSetErrorCode(pVCpu, uErr | X86_TRAP_PF_RSVD | X86_TRAP_PF_P);
2396
2397 Log(("CheckPageFault: real page fault (rsvd) at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2398 return VINF_EM_RAW_GUEST_TRAP;
2399}
2400
2401
2402/**
2403 * CheckPageFault helper for returning a page protection fault (P).
2404 *
2405 * @returns VINF_EM_RAW_GUEST_TRAP.
2406 * @param pVCpu Pointer to the VMCPU.
2407 * @param uErr The error code of the shadow fault. Corrections to
2408 * TRPM's copy will be made if necessary.
2409 * @param GCPtrPage For logging.
2410 * @param uPageFaultLevel For logging.
2411 */
2412DECLINLINE(int) PGM_BTH_NAME(CheckPageFaultReturnProt)(PVMCPU pVCpu, uint32_t uErr, RTGCPTR GCPtrPage, unsigned uPageFaultLevel)
2413{
2414 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyTrackRealPF));
2415 AssertMsg(uErr & (X86_TRAP_PF_RW | X86_TRAP_PF_US | X86_TRAP_PF_ID), ("%#x\n", uErr));
2416 if ((uErr & (X86_TRAP_PF_P | X86_TRAP_PF_RSVD)) != X86_TRAP_PF_P)
2417 TRPMSetErrorCode(pVCpu, (uErr & ~X86_TRAP_PF_RSVD) | X86_TRAP_PF_P);
2418
2419 Log(("CheckPageFault: real page fault (prot) at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2420 return VINF_EM_RAW_GUEST_TRAP;
2421}
2422
2423
2424/**
2425 * Handle dirty bit tracking faults.
2426 *
2427 * @returns VBox status code.
2428 * @param pVCpu Pointer to the VMCPU.
2429 * @param uErr Page fault error code.
2430 * @param pPdeSrc Guest page directory entry.
2431 * @param pPdeDst Shadow page directory entry.
2432 * @param GCPtrPage Guest context page address.
2433 */
2434static int PGM_BTH_NAME(CheckDirtyPageFault)(PVMCPU pVCpu, uint32_t uErr, PSHWPDE pPdeDst, GSTPDE const *pPdeSrc,
2435 RTGCPTR GCPtrPage)
2436{
2437 PVM pVM = pVCpu->CTX_SUFF(pVM);
2438 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2439 NOREF(uErr);
2440
2441 PGM_LOCK_ASSERT_OWNER(pVM);
2442
2443 /*
2444 * Handle big page.
2445 */
2446 if (pPdeSrc->b.u1Size && GST_IS_PSE_ACTIVE(pVCpu))
2447 {
2448 if ( pPdeDst->n.u1Present
2449 && (pPdeDst->u & PGM_PDFLAGS_TRACK_DIRTY))
2450 {
2451 SHWPDE PdeDst = *pPdeDst;
2452
2453 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageTrap));
2454 Assert(pPdeSrc->b.u1Write);
2455
2456 /* Note: No need to invalidate this entry on other VCPUs as a stale TLB entry will not harm; write access will simply
2457 * fault again and take this path to only invalidate the entry (see below).
2458 */
2459 PdeDst.n.u1Write = 1;
2460 PdeDst.n.u1Accessed = 1;
2461 PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
2462 ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2463 PGM_INVL_BIG_PG(pVCpu, GCPtrPage);
2464 return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2465 }
2466
2467# ifdef IN_RING0
2468 /* Check for stale TLB entry; only applies to the SMP guest case. */
2469 if ( pVM->cCpus > 1
2470 && pPdeDst->n.u1Write
2471 && pPdeDst->n.u1Accessed)
2472 {
2473 PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPdeDst->u & SHW_PDE_PG_MASK);
2474 if (pShwPage)
2475 {
2476 PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2477 PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2478 if (SHW_PTE_IS_P_RW(*pPteDst))
2479 {
2480 /* Stale TLB entry. */
2481 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageStale));
2482 PGM_INVL_PG(pVCpu, GCPtrPage);
2483 return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2484 }
2485 }
2486 }
2487# endif /* IN_RING0 */
2488 return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2489 }
2490
2491 /*
2492 * Map the guest page table.
2493 */
2494 PGSTPT pPTSrc;
2495 int rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GST_GET_PDE_GCPHYS(*pPdeSrc), &pPTSrc);
2496 if (RT_FAILURE(rc))
2497 {
2498 AssertRC(rc);
2499 return rc;
2500 }
2501
2502 if (pPdeDst->n.u1Present)
2503 {
2504 GSTPTE const *pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
2505 const GSTPTE PteSrc = *pPteSrc;
2506
2507#ifdef VBOX_WITH_RAW_MODE_NOT_R0
2508 /* Bail out here as pgmPoolGetPage will return NULL and we'll crash below.
2509 * Our individual shadow handlers will provide more information and force a fatal exit.
2510 */
2511 if ( !HMIsEnabled(pVM)
2512 && MMHyperIsInsideArea(pVM, (RTGCPTR)GCPtrPage))
2513 {
2514 LogRel(("CheckPageFault: write to hypervisor region %RGv\n", GCPtrPage));
2515 return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2516 }
2517#endif
2518 /*
2519 * Map shadow page table.
2520 */
2521 PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPdeDst->u & SHW_PDE_PG_MASK);
2522 if (pShwPage)
2523 {
2524 PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2525 PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2526 if (SHW_PTE_IS_P(*pPteDst)) /** @todo Optimize accessed bit emulation? */
2527 {
2528 if (SHW_PTE_IS_TRACK_DIRTY(*pPteDst))
2529 {
2530 PPGMPAGE pPage = pgmPhysGetPage(pVM, GST_GET_PTE_GCPHYS(PteSrc));
2531 SHWPTE PteDst = *pPteDst;
2532
2533 LogFlow(("DIRTY page trap addr=%RGv\n", GCPtrPage));
2534 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageTrap));
2535
2536 Assert(PteSrc.n.u1Write);
2537
2538 /* Note: No need to invalidate this entry on other VCPUs as a stale TLB
2539 * entry will not harm; write access will simply fault again and
2540 * take this path to only invalidate the entry.
2541 */
2542 if (RT_LIKELY(pPage))
2543 {
2544 if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2545 {
2546 //AssertMsgFailed(("%R[pgmpage] - we don't set PGM_PTFLAGS_TRACK_DIRTY for these pages\n", pPage));
2547 Assert(!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage));
2548 /* Assuming write handlers here as the PTE is present (otherwise we wouldn't be here). */
2549 SHW_PTE_SET_RO(PteDst);
2550 }
2551 else
2552 {
2553 if ( PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED
2554 && PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
2555 {
2556 rc = pgmPhysPageMakeWritable(pVM, pPage, GST_GET_PTE_GCPHYS(PteSrc));
2557 AssertRC(rc);
2558 }
2559 if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED)
2560 SHW_PTE_SET_RW(PteDst);
2561 else
2562 {
2563 /* Still applies to shared pages. */
2564 Assert(!PGM_PAGE_IS_ZERO(pPage));
2565 SHW_PTE_SET_RO(PteDst);
2566 }
2567 }
2568 }
2569 else
2570 SHW_PTE_SET_RW(PteDst); /** @todo r=bird: This doesn't make sense to me. */
2571
2572 SHW_PTE_SET(PteDst, (SHW_PTE_GET_U(PteDst) | X86_PTE_D | X86_PTE_A) & ~(uint64_t)PGM_PTFLAGS_TRACK_DIRTY);
2573 SHW_PTE_ATOMIC_SET2(*pPteDst, PteDst);
2574 PGM_INVL_PG(pVCpu, GCPtrPage);
2575 return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2576 }
2577
2578# ifdef IN_RING0
2579 /* Check for stale TLB entry; only applies to the SMP guest case. */
2580 if ( pVM->cCpus > 1
2581 && SHW_PTE_IS_RW(*pPteDst)
2582 && SHW_PTE_IS_A(*pPteDst))
2583 {
2584 /* Stale TLB entry. */
2585 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageStale));
2586 PGM_INVL_PG(pVCpu, GCPtrPage);
2587 return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2588 }
2589# endif
2590 }
2591 }
2592 else
2593 AssertMsgFailed(("pgmPoolGetPageByHCPhys %RGp failed!\n", pPdeDst->u & SHW_PDE_PG_MASK));
2594 }
2595
2596 return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2597}
2598
2599#endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
2600
2601
2602/**
2603 * Sync a shadow page table.
2604 *
2605 * The shadow page table is not present in the shadow PDE.
2606 *
2607 * Handles mapping conflicts.
2608 *
2609 * This is called by VerifyAccessSyncPage, PrefetchPage, InvalidatePage (on
2610 * conflict), and Trap0eHandler.
2611 *
2612 * A precondition for this method is that the shadow PDE is not present. The
2613 * caller must take the PGM lock before checking this and continue to hold it
2614 * when calling this method.
2615 *
2616 * @returns VBox status code.
2617 * @param pVCpu Pointer to the VMCPU.
2618 * @param iPD Page directory index.
2619 * @param pPDSrc Source page directory (i.e. Guest OS page directory).
2620 * Assume this is a temporary mapping.
2621 * @param GCPtrPage GC Pointer of the page that caused the fault
2622 */
2623static int PGM_BTH_NAME(SyncPT)(PVMCPU pVCpu, unsigned iPDSrc, PGSTPD pPDSrc, RTGCPTR GCPtrPage)
2624{
2625 PVM pVM = pVCpu->CTX_SUFF(pVM);
2626 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool); NOREF(pPool);
2627
2628#if 0 /* rarely useful; leave for debugging. */
2629 STAM_COUNTER_INC(&pVCpu->pgm.s.StatSyncPtPD[iPDSrc]);
2630#endif
2631 LogFlow(("SyncPT: GCPtrPage=%RGv\n", GCPtrPage));
2632
2633 PGM_LOCK_ASSERT_OWNER(pVM);
2634
2635#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
2636 || PGM_GST_TYPE == PGM_TYPE_PAE \
2637 || PGM_GST_TYPE == PGM_TYPE_AMD64) \
2638 && PGM_SHW_TYPE != PGM_TYPE_NESTED \
2639 && PGM_SHW_TYPE != PGM_TYPE_EPT
2640
2641 int rc = VINF_SUCCESS;
2642
2643 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
2644
2645 /*
2646 * Some input validation first.
2647 */
2648 AssertMsg(iPDSrc == ((GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK), ("iPDSrc=%x GCPtrPage=%RGv\n", iPDSrc, GCPtrPage));
2649
2650 /*
2651 * Get the relevant shadow PDE entry.
2652 */
2653# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2654 const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
2655 PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
2656
2657 /* Fetch the pgm pool shadow descriptor. */
2658 PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
2659 Assert(pShwPde);
2660
2661# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2662 const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2663 PPGMPOOLPAGE pShwPde = NULL;
2664 PX86PDPAE pPDDst;
2665 PSHWPDE pPdeDst;
2666
2667 /* Fetch the pgm pool shadow descriptor. */
2668 rc = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
2669 AssertRCSuccessReturn(rc, rc);
2670 Assert(pShwPde);
2671
2672 pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
2673 pPdeDst = &pPDDst->a[iPDDst];
2674
2675# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2676 const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
2677 const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2678 PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
2679 PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
2680 rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2681 AssertRCSuccessReturn(rc, rc);
2682 Assert(pPDDst);
2683 PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2684# endif
2685 SHWPDE PdeDst = *pPdeDst;
2686
2687# if PGM_GST_TYPE == PGM_TYPE_AMD64
2688 /* Fetch the pgm pool shadow descriptor. */
2689 PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
2690 Assert(pShwPde);
2691# endif
2692
2693# ifndef PGM_WITHOUT_MAPPINGS
2694 /*
2695 * Check for conflicts.
2696 * RC: In case of a conflict we'll go to Ring-3 and do a full SyncCR3.
2697 * R3: Simply resolve the conflict.
2698 */
2699 if (PdeDst.u & PGM_PDFLAGS_MAPPING)
2700 {
2701 Assert(pgmMapAreMappingsEnabled(pVM));
2702# ifndef IN_RING3
2703 Log(("SyncPT: Conflict at %RGv\n", GCPtrPage));
2704 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
2705 return VERR_ADDRESS_CONFLICT;
2706
2707# else /* IN_RING3 */
2708 PPGMMAPPING pMapping = pgmGetMapping(pVM, (RTGCPTR)GCPtrPage);
2709 Assert(pMapping);
2710# if PGM_GST_TYPE == PGM_TYPE_32BIT
2711 rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2712# elif PGM_GST_TYPE == PGM_TYPE_PAE
2713 rc = pgmR3SyncPTResolveConflictPAE(pVM, pMapping, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2714# else
2715 AssertFailed(); NOREF(pMapping); /* can't happen for amd64 */
2716# endif
2717 if (RT_FAILURE(rc))
2718 {
2719 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
2720 return rc;
2721 }
2722 PdeDst = *pPdeDst;
2723# endif /* IN_RING3 */
2724 }
2725# endif /* !PGM_WITHOUT_MAPPINGS */
2726 Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
2727
2728 /*
2729 * Sync the page directory entry.
2730 */
2731 GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
2732 const bool fPageTable = !PdeSrc.b.u1Size || !GST_IS_PSE_ACTIVE(pVCpu);
2733 if ( PdeSrc.n.u1Present
2734 && (fPageTable ? GST_IS_PDE_VALID(pVCpu, PdeSrc) : GST_IS_BIG_PDE_VALID(pVCpu, PdeSrc)) )
2735 {
2736 /*
2737 * Allocate & map the page table.
2738 */
2739 PSHWPT pPTDst;
2740 PPGMPOOLPAGE pShwPage;
2741 RTGCPHYS GCPhys;
2742 if (fPageTable)
2743 {
2744 GCPhys = GST_GET_PDE_GCPHYS(PdeSrc);
2745# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2746 /* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2747 GCPhys = PGM_A20_APPLY(pVCpu, GCPhys | ((iPDDst & 1) * (PAGE_SIZE / 2)));
2748# endif
2749 rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
2750 pShwPde->idx, iPDDst, false /*fLockPage*/,
2751 &pShwPage);
2752 }
2753 else
2754 {
2755 PGMPOOLACCESS enmAccess;
2756# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2757 const bool fNoExecute = PdeSrc.n.u1NoExecute && GST_IS_NX_ACTIVE(pVCpu);
2758# else
2759 const bool fNoExecute = false;
2760# endif
2761
2762 GCPhys = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
2763# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2764 /* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
2765 GCPhys = PGM_A20_APPLY(pVCpu, GCPhys | (GCPtrPage & (1 << X86_PD_PAE_SHIFT)));
2766# endif
2767 /* Determine the right kind of large page to avoid incorrect cached entry reuse. */
2768 if (PdeSrc.n.u1User)
2769 {
2770 if (PdeSrc.n.u1Write)
2771 enmAccess = (fNoExecute) ? PGMPOOLACCESS_USER_RW_NX : PGMPOOLACCESS_USER_RW;
2772 else
2773 enmAccess = (fNoExecute) ? PGMPOOLACCESS_USER_R_NX : PGMPOOLACCESS_USER_R;
2774 }
2775 else
2776 {
2777 if (PdeSrc.n.u1Write)
2778 enmAccess = (fNoExecute) ? PGMPOOLACCESS_SUPERVISOR_RW_NX : PGMPOOLACCESS_SUPERVISOR_RW;
2779 else
2780 enmAccess = (fNoExecute) ? PGMPOOLACCESS_SUPERVISOR_R_NX : PGMPOOLACCESS_SUPERVISOR_R;
2781 }
2782 rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_BIG, enmAccess, PGM_A20_IS_ENABLED(pVCpu),
2783 pShwPde->idx, iPDDst, false /*fLockPage*/,
2784 &pShwPage);
2785 }
2786 if (rc == VINF_SUCCESS)
2787 pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2788 else if (rc == VINF_PGM_CACHED_PAGE)
2789 {
2790 /*
2791 * The PT was cached, just hook it up.
2792 */
2793 if (fPageTable)
2794 PdeDst.u = pShwPage->Core.Key | GST_GET_PDE_SHW_FLAGS(pVCpu, PdeSrc);
2795 else
2796 {
2797 PdeDst.u = pShwPage->Core.Key | GST_GET_BIG_PDE_SHW_FLAGS(pVCpu, PdeSrc);
2798 /* (see explanation and assumptions further down.) */
2799 if ( !PdeSrc.b.u1Dirty
2800 && PdeSrc.b.u1Write)
2801 {
2802 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageBig));
2803 PdeDst.u |= PGM_PDFLAGS_TRACK_DIRTY;
2804 PdeDst.b.u1Write = 0;
2805 }
2806 }
2807 ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2808 PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2809 return VINF_SUCCESS;
2810 }
2811 else if (rc == VERR_PGM_POOL_FLUSHED)
2812 {
2813 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2814 PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2815 return VINF_PGM_SYNC_CR3;
2816 }
2817 else
2818 AssertMsgFailedReturn(("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
2819 /** @todo Why do we bother preserving X86_PDE_AVL_MASK here?
2820 * Both PGM_PDFLAGS_MAPPING and PGM_PDFLAGS_TRACK_DIRTY should be
2821 * irrelevant at this point. */
2822 PdeDst.u &= X86_PDE_AVL_MASK;
2823 PdeDst.u |= pShwPage->Core.Key;
2824
2825 /*
2826 * Page directory has been accessed (this is a fault situation, remember).
2827 */
2828 /** @todo
2829 * Well, when the caller is PrefetchPage or InvalidatePage is isn't a
2830 * fault situation. What's more, the Trap0eHandler has already set the
2831 * accessed bit. So, it's actually just VerifyAccessSyncPage which
2832 * might need setting the accessed flag.
2833 *
2834 * The best idea is to leave this change to the caller and add an
2835 * assertion that it's set already. */
2836 pPDSrc->a[iPDSrc].n.u1Accessed = 1;
2837 if (fPageTable)
2838 {
2839 /*
2840 * Page table - 4KB.
2841 *
2842 * Sync all or just a few entries depending on PGM_SYNC_N_PAGES.
2843 */
2844 Log2(("SyncPT: 4K %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx}\n",
2845 GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u));
2846 PGSTPT pPTSrc;
2847 rc = PGM_GCPHYS_2_PTR(pVM, GST_GET_PDE_GCPHYS(PdeSrc), &pPTSrc);
2848 if (RT_SUCCESS(rc))
2849 {
2850 /*
2851 * Start by syncing the page directory entry so CSAM's TLB trick works.
2852 */
2853 PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK | X86_PDE_AVL_MASK))
2854 | GST_GET_PDE_SHW_FLAGS(pVCpu, PdeSrc);
2855 ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2856 PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2857
2858 /*
2859 * Directory/page user or supervisor privilege: (same goes for read/write)
2860 *
2861 * Directory Page Combined
2862 * U/S U/S U/S
2863 * 0 0 0
2864 * 0 1 0
2865 * 1 0 0
2866 * 1 1 1
2867 *
2868 * Simple AND operation. Table listed for completeness.
2869 *
2870 */
2871 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT4K));
2872# ifdef PGM_SYNC_N_PAGES
2873 unsigned iPTBase = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2874 unsigned iPTDst = iPTBase;
2875 const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2876 if (iPTDst <= PGM_SYNC_NR_PAGES / 2)
2877 iPTDst = 0;
2878 else
2879 iPTDst -= PGM_SYNC_NR_PAGES / 2;
2880# else /* !PGM_SYNC_N_PAGES */
2881 unsigned iPTDst = 0;
2882 const unsigned iPTDstEnd = RT_ELEMENTS(pPTDst->a);
2883# endif /* !PGM_SYNC_N_PAGES */
2884 RTGCPTR GCPtrCur = (GCPtrPage & ~(RTGCPTR)((1 << SHW_PD_SHIFT) - 1))
2885 | ((RTGCPTR)iPTDst << PAGE_SHIFT);
2886# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2887 /* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2888 const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
2889# else
2890 const unsigned offPTSrc = 0;
2891# endif
2892 for (; iPTDst < iPTDstEnd; iPTDst++, GCPtrCur += PAGE_SIZE)
2893 {
2894 const unsigned iPTSrc = iPTDst + offPTSrc;
2895 const GSTPTE PteSrc = pPTSrc->a[iPTSrc];
2896
2897 if (PteSrc.n.u1Present)
2898 {
2899# ifdef VBOX_WITH_RAW_MODE_NOT_R0
2900 /*
2901 * Assuming kernel code will be marked as supervisor - and not as user level
2902 * and executed using a conforming code selector - And marked as readonly.
2903 * Also assume that if we're monitoring a page, it's of no interest to CSAM.
2904 */
2905 PPGMPAGE pPage;
2906 if ( ((PdeSrc.u & pPTSrc->a[iPTSrc].u) & (X86_PTE_RW | X86_PTE_US))
2907 || !CSAMDoesPageNeedScanning(pVM, GCPtrCur)
2908 || ( (pPage = pgmPhysGetPage(pVM, GST_GET_PTE_GCPHYS(PteSrc)))
2909 && PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2910 )
2911# endif
2912 PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2913 Log2(("SyncPT: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s dst.raw=%08llx iPTSrc=%x PdeSrc.u=%x physpte=%RGp\n",
2914 GCPtrCur,
2915 PteSrc.n.u1Present,
2916 PteSrc.n.u1Write & PdeSrc.n.u1Write,
2917 PteSrc.n.u1User & PdeSrc.n.u1User,
2918 (uint64_t)PteSrc.u,
2919 SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : "", SHW_PTE_LOG64(pPTDst->a[iPTDst]), iPTSrc, PdeSrc.au32[0],
2920 (RTGCPHYS)(GST_GET_PDE_GCPHYS(PdeSrc) + iPTSrc*sizeof(PteSrc)) ));
2921 }
2922 /* else: the page table was cleared by the pool */
2923 } /* for PTEs */
2924 }
2925 }
2926 else
2927 {
2928 /*
2929 * Big page - 2/4MB.
2930 *
2931 * We'll walk the ram range list in parallel and optimize lookups.
2932 * We will only sync one shadow page table at a time.
2933 */
2934 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT4M));
2935
2936 /**
2937 * @todo It might be more efficient to sync only a part of the 4MB
2938 * page (similar to what we do for 4KB PDs).
2939 */
2940
2941 /*
2942 * Start by syncing the page directory entry.
2943 */
2944 PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK | (X86_PDE_AVL_MASK & ~PGM_PDFLAGS_TRACK_DIRTY)))
2945 | GST_GET_BIG_PDE_SHW_FLAGS(pVCpu, PdeSrc);
2946
2947 /*
2948 * If the page is not flagged as dirty and is writable, then make it read-only
2949 * at PD level, so we can set the dirty bit when the page is modified.
2950 *
2951 * ASSUMES that page access handlers are implemented on page table entry level.
2952 * Thus we will first catch the dirty access and set PDE.D and restart. If
2953 * there is an access handler, we'll trap again and let it work on the problem.
2954 */
2955 /** @todo move the above stuff to a section in the PGM documentation. */
2956 Assert(!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY));
2957 if ( !PdeSrc.b.u1Dirty
2958 && PdeSrc.b.u1Write)
2959 {
2960 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageBig));
2961 PdeDst.u |= PGM_PDFLAGS_TRACK_DIRTY;
2962 PdeDst.b.u1Write = 0;
2963 }
2964 ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2965 PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2966
2967 /*
2968 * Fill the shadow page table.
2969 */
2970 /* Get address and flags from the source PDE. */
2971 SHWPTE PteDstBase;
2972 SHW_PTE_SET(PteDstBase, GST_GET_BIG_PDE_SHW_FLAGS_4_PTE(pVCpu, PdeSrc));
2973
2974 /* Loop thru the entries in the shadow PT. */
2975 const RTGCPTR GCPtr = (GCPtrPage >> SHW_PD_SHIFT) << SHW_PD_SHIFT; NOREF(GCPtr);
2976 Log2(("SyncPT: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} Shw=%RGv GCPhys=%RGp %s\n",
2977 GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u, GCPtr,
2978 GCPhys, PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2979 PPGMRAMRANGE pRam = pgmPhysGetRangeAtOrAbove(pVM, GCPhys);
2980 unsigned iPTDst = 0;
2981 while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2982 && !VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY))
2983 {
2984 if (pRam && GCPhys >= pRam->GCPhys)
2985 {
2986# ifndef PGM_WITH_A20
2987 unsigned iHCPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
2988# endif
2989 do
2990 {
2991 /* Make shadow PTE. */
2992# ifdef PGM_WITH_A20
2993 PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
2994# else
2995 PPGMPAGE pPage = &pRam->aPages[iHCPage];
2996# endif
2997 SHWPTE PteDst;
2998
2999# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
3000 /* Try to make the page writable if necessary. */
3001 if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
3002 && ( PGM_PAGE_IS_ZERO(pPage)
3003 || ( SHW_PTE_IS_RW(PteDstBase)
3004 && PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
3005# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
3006 && PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
3007# endif
3008# ifdef VBOX_WITH_PAGE_SHARING
3009 && PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
3010# endif
3011 && !PGM_PAGE_IS_BALLOONED(pPage))
3012 )
3013 )
3014 {
3015 rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
3016 AssertRCReturn(rc, rc);
3017 if (VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY))
3018 break;
3019 }
3020# endif
3021
3022 if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
3023 PGM_BTH_NAME(SyncHandlerPte)(pVM, pPage, SHW_PTE_GET_U(PteDstBase), &PteDst);
3024 else if (PGM_PAGE_IS_BALLOONED(pPage))
3025 SHW_PTE_SET(PteDst, 0); /* Handle ballooned pages at #PF time. */
3026# ifdef VBOX_WITH_RAW_MODE_NOT_R0
3027 /*
3028 * Assuming kernel code will be marked as supervisor and not as user level and executed
3029 * using a conforming code selector. Don't check for readonly, as that implies the whole
3030 * 4MB can be code or readonly data. Linux enables write access for its large pages.
3031 */
3032 else if ( !PdeSrc.n.u1User
3033 && CSAMDoesPageNeedScanning(pVM, GCPtr | (iPTDst << SHW_PT_SHIFT)))
3034 SHW_PTE_SET(PteDst, 0);
3035# endif
3036 else
3037 SHW_PTE_SET(PteDst, PGM_PAGE_GET_HCPHYS(pPage) | SHW_PTE_GET_U(PteDstBase));
3038
3039 /* Only map writable pages writable. */
3040 if ( SHW_PTE_IS_P_RW(PteDst)
3041 && PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
3042 {
3043 /* Still applies to shared pages. */
3044 Assert(!PGM_PAGE_IS_ZERO(pPage));
3045 SHW_PTE_SET_RO(PteDst); /** @todo this isn't quite working yet... */
3046 Log3(("SyncPT: write-protecting %RGp pPage=%R[pgmpage] at %RGv\n", GCPhys, pPage, (RTGCPTR)(GCPtr | (iPTDst << SHW_PT_SHIFT))));
3047 }
3048
3049 if (SHW_PTE_IS_P(PteDst))
3050 PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
3051
3052 /* commit it (not atomic, new table) */
3053 pPTDst->a[iPTDst] = PteDst;
3054 Log4(("SyncPT: BIG %RGv PteDst:{P=%d RW=%d U=%d raw=%08llx}%s\n",
3055 (RTGCPTR)(GCPtr | (iPTDst << SHW_PT_SHIFT)), SHW_PTE_IS_P(PteDst), SHW_PTE_IS_RW(PteDst), SHW_PTE_IS_US(PteDst), SHW_PTE_LOG64(PteDst),
3056 SHW_PTE_IS_TRACK_DIRTY(PteDst) ? " Track-Dirty" : ""));
3057
3058 /* advance */
3059 GCPhys += PAGE_SIZE;
3060 PGM_A20_APPLY_TO_VAR(pVCpu, GCPhys);
3061# ifndef PGM_WITH_A20
3062 iHCPage++;
3063# endif
3064 iPTDst++;
3065 } while ( iPTDst < RT_ELEMENTS(pPTDst->a)
3066 && GCPhys <= pRam->GCPhysLast);
3067
3068 /* Advance ram range list. */
3069 while (pRam && GCPhys > pRam->GCPhysLast)
3070 pRam = pRam->CTX_SUFF(pNext);
3071 }
3072 else if (pRam)
3073 {
3074 Log(("Invalid pages at %RGp\n", GCPhys));
3075 do
3076 {
3077 SHW_PTE_SET(pPTDst->a[iPTDst], 0); /* Invalid page, we must handle them manually. */
3078 GCPhys += PAGE_SIZE;
3079 iPTDst++;
3080 } while ( iPTDst < RT_ELEMENTS(pPTDst->a)
3081 && GCPhys < pRam->GCPhys);
3082 PGM_A20_APPLY_TO_VAR(pVCpu,GCPhys);
3083 }
3084 else
3085 {
3086 Log(("Invalid pages at %RGp (2)\n", GCPhys));
3087 for ( ; iPTDst < RT_ELEMENTS(pPTDst->a); iPTDst++)
3088 SHW_PTE_SET(pPTDst->a[iPTDst], 0); /* Invalid page, we must handle them manually. */
3089 }
3090 } /* while more PTEs */
3091 } /* 4KB / 4MB */
3092 }
3093 else
3094 AssertRelease(!PdeDst.n.u1Present);
3095
3096 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3097 if (RT_FAILURE(rc))
3098 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPTFailed));
3099 return rc;
3100
3101#elif (PGM_GST_TYPE == PGM_TYPE_REAL || PGM_GST_TYPE == PGM_TYPE_PROT) \
3102 && PGM_SHW_TYPE != PGM_TYPE_NESTED \
3103 && (PGM_SHW_TYPE != PGM_TYPE_EPT || PGM_GST_TYPE == PGM_TYPE_PROT) \
3104 && !defined(IN_RC)
3105 NOREF(iPDSrc); NOREF(pPDSrc);
3106
3107 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3108
3109 /*
3110 * Validate input a little bit.
3111 */
3112 int rc = VINF_SUCCESS;
3113# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3114 const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
3115 PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
3116
3117 /* Fetch the pgm pool shadow descriptor. */
3118 PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
3119 Assert(pShwPde);
3120
3121# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3122 const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
3123 PPGMPOOLPAGE pShwPde = NULL; /* initialized to shut up gcc */
3124 PX86PDPAE pPDDst;
3125 PSHWPDE pPdeDst;
3126
3127 /* Fetch the pgm pool shadow descriptor. */
3128 rc = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
3129 AssertRCSuccessReturn(rc, rc);
3130 Assert(pShwPde);
3131
3132 pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
3133 pPdeDst = &pPDDst->a[iPDDst];
3134
3135# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3136 const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3137 const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
3138 PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
3139 PX86PDPT pPdptDst= NULL; /* initialized to shut up gcc */
3140 rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
3141 AssertRCSuccessReturn(rc, rc);
3142 Assert(pPDDst);
3143 PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
3144
3145 /* Fetch the pgm pool shadow descriptor. */
3146 PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
3147 Assert(pShwPde);
3148
3149# elif PGM_SHW_TYPE == PGM_TYPE_EPT
3150 const unsigned iPdpt = (GCPtrPage >> EPT_PDPT_SHIFT) & EPT_PDPT_MASK;
3151 const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3152 PEPTPD pPDDst;
3153 PEPTPDPT pPdptDst;
3154
3155 rc = pgmShwGetEPTPDPtr(pVCpu, GCPtrPage, &pPdptDst, &pPDDst);
3156 if (rc != VINF_SUCCESS)
3157 {
3158 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3159 AssertRC(rc);
3160 return rc;
3161 }
3162 Assert(pPDDst);
3163 PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
3164
3165 /* Fetch the pgm pool shadow descriptor. */
3166 PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & EPT_PDPTE_PG_MASK);
3167 Assert(pShwPde);
3168# endif
3169 SHWPDE PdeDst = *pPdeDst;
3170
3171 Assert(!(PdeDst.u & PGM_PDFLAGS_MAPPING));
3172 Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
3173
3174# if defined(PGM_WITH_LARGE_PAGES) && PGM_SHW_TYPE != PGM_TYPE_32BIT && PGM_SHW_TYPE != PGM_TYPE_PAE
3175 if (BTH_IS_NP_ACTIVE(pVM))
3176 {
3177 /* Check if we allocated a big page before for this 2 MB range. */
3178 PPGMPAGE pPage;
3179 rc = pgmPhysGetPageEx(pVM, PGM_A20_APPLY(pVCpu, GCPtrPage & X86_PDE2M_PAE_PG_MASK), &pPage);
3180 if (RT_SUCCESS(rc))
3181 {
3182 RTHCPHYS HCPhys = NIL_RTHCPHYS;
3183 if (PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE)
3184 {
3185 if (PGM_A20_IS_ENABLED(pVCpu))
3186 {
3187 STAM_REL_COUNTER_INC(&pVM->pgm.s.StatLargePageReused);
3188 AssertRelease(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
3189 HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3190 }
3191 else
3192 {
3193 PGM_PAGE_SET_PDE_TYPE(pVM, pPage, PGM_PAGE_PDE_TYPE_PDE_DISABLED);
3194 pVM->pgm.s.cLargePagesDisabled++;
3195 }
3196 }
3197 else if ( PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE_DISABLED
3198 && PGM_A20_IS_ENABLED(pVCpu))
3199 {
3200 /* Recheck the entire 2 MB range to see if we can use it again as a large page. */
3201 rc = pgmPhysRecheckLargePage(pVM, GCPtrPage, pPage);
3202 if (RT_SUCCESS(rc))
3203 {
3204 Assert(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
3205 Assert(PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE);
3206 HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3207 }
3208 }
3209 else if ( PGMIsUsingLargePages(pVM)
3210 && PGM_A20_IS_ENABLED(pVCpu))
3211 {
3212 rc = pgmPhysAllocLargePage(pVM, GCPtrPage);
3213 if (RT_SUCCESS(rc))
3214 {
3215 Assert(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
3216 Assert(PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE);
3217 HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3218 }
3219 else
3220 LogFlow(("pgmPhysAllocLargePage failed with %Rrc\n", rc));
3221 }
3222
3223 if (HCPhys != NIL_RTHCPHYS)
3224 {
3225 PdeDst.u &= X86_PDE_AVL_MASK;
3226 PdeDst.u |= HCPhys;
3227 PdeDst.n.u1Present = 1;
3228 PdeDst.n.u1Write = 1;
3229 PdeDst.b.u1Size = 1;
3230# if PGM_SHW_TYPE == PGM_TYPE_EPT
3231 PdeDst.n.u1Execute = 1;
3232 PdeDst.b.u1IgnorePAT = 1;
3233 PdeDst.b.u3EMT = VMX_EPT_MEMTYPE_WB;
3234# else
3235 PdeDst.n.u1User = 1;
3236# endif
3237 ASMAtomicWriteSize(pPdeDst, PdeDst.u);
3238
3239 Log(("SyncPT: Use large page at %RGp PDE=%RX64\n", GCPtrPage, PdeDst.u));
3240 /* Add a reference to the first page only. */
3241 PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPde, PGM_PAGE_GET_TRACKING(pPage), pPage, iPDDst);
3242
3243 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3244 return VINF_SUCCESS;
3245 }
3246 }
3247 }
3248# endif /* HC_ARCH_BITS == 64 */
3249
3250 /*
3251 * Allocate & map the page table.
3252 */
3253 PSHWPT pPTDst;
3254 PPGMPOOLPAGE pShwPage;
3255 RTGCPHYS GCPhys;
3256
3257 /* Virtual address = physical address */
3258 GCPhys = PGM_A20_APPLY(pVCpu, GCPtrPage & X86_PAGE_4K_BASE_MASK);
3259 rc = pgmPoolAlloc(pVM, GCPhys & ~(RT_BIT_64(SHW_PD_SHIFT) - 1), BTH_PGMPOOLKIND_PT_FOR_PT, PGMPOOLACCESS_DONTCARE,
3260 PGM_A20_IS_ENABLED(pVCpu), pShwPde->idx, iPDDst, false /*fLockPage*/,
3261 &pShwPage);
3262 if ( rc == VINF_SUCCESS
3263 || rc == VINF_PGM_CACHED_PAGE)
3264 pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
3265 else
3266 {
3267 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3268 AssertMsgFailedReturn(("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
3269 }
3270
3271 if (rc == VINF_SUCCESS)
3272 {
3273 /* New page table; fully set it up. */
3274 Assert(pPTDst);
3275
3276 /* Mask away the page offset. */
3277 GCPtrPage &= ~(RTGCPTR)PAGE_OFFSET_MASK;
3278
3279 for (unsigned iPTDst = 0; iPTDst < RT_ELEMENTS(pPTDst->a); iPTDst++)
3280 {
3281 RTGCPTR GCPtrCurPage = PGM_A20_APPLY(pVCpu, (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT))
3282 | (iPTDst << PAGE_SHIFT));
3283
3284 PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], GCPtrCurPage, pShwPage, iPTDst);
3285 Log2(("SyncPage: 4K+ %RGv PteSrc:{P=1 RW=1 U=1} PteDst=%08llx%s\n",
3286 GCPtrCurPage,
3287 SHW_PTE_LOG64(pPTDst->a[iPTDst]),
3288 SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
3289
3290 if (RT_UNLIKELY(VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY)))
3291 break;
3292 }
3293 }
3294 else
3295 rc = VINF_SUCCESS; /* Cached entry; assume it's still fully valid. */
3296
3297 /* Save the new PDE. */
3298 PdeDst.u &= X86_PDE_AVL_MASK;
3299 PdeDst.u |= pShwPage->Core.Key;
3300 PdeDst.n.u1Present = 1;
3301 PdeDst.n.u1Write = 1;
3302# if PGM_SHW_TYPE == PGM_TYPE_EPT
3303 PdeDst.n.u1Execute = 1;
3304# else
3305 PdeDst.n.u1User = 1;
3306 PdeDst.n.u1Accessed = 1;
3307# endif
3308 ASMAtomicWriteSize(pPdeDst, PdeDst.u);
3309
3310 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3311 if (RT_FAILURE(rc))
3312 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPTFailed));
3313 return rc;
3314
3315#else
3316 NOREF(iPDSrc); NOREF(pPDSrc);
3317 AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_SHW_TYPE, PGM_GST_TYPE));
3318 return VERR_PGM_NOT_USED_IN_MODE;
3319#endif
3320}
3321
3322
3323
3324/**
3325 * Prefetch a page/set of pages.
3326 *
3327 * Typically used to sync commonly used pages before entering raw mode
3328 * after a CR3 reload.
3329 *
3330 * @returns VBox status code.
3331 * @param pVCpu Pointer to the VMCPU.
3332 * @param GCPtrPage Page to invalidate.
3333 */
3334PGM_BTH_DECL(int, PrefetchPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage)
3335{
3336#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
3337 || PGM_GST_TYPE == PGM_TYPE_REAL \
3338 || PGM_GST_TYPE == PGM_TYPE_PROT \
3339 || PGM_GST_TYPE == PGM_TYPE_PAE \
3340 || PGM_GST_TYPE == PGM_TYPE_AMD64 ) \
3341 && PGM_SHW_TYPE != PGM_TYPE_NESTED \
3342 && PGM_SHW_TYPE != PGM_TYPE_EPT
3343
3344 /*
3345 * Check that all Guest levels thru the PDE are present, getting the
3346 * PD and PDE in the processes.
3347 */
3348 int rc = VINF_SUCCESS;
3349# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3350# if PGM_GST_TYPE == PGM_TYPE_32BIT
3351 const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
3352 PGSTPD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
3353# elif PGM_GST_TYPE == PGM_TYPE_PAE
3354 unsigned iPDSrc;
3355 X86PDPE PdpeSrc;
3356 PGSTPD pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtrPage, &iPDSrc, &PdpeSrc);
3357 if (!pPDSrc)
3358 return VINF_SUCCESS; /* not present */
3359# elif PGM_GST_TYPE == PGM_TYPE_AMD64
3360 unsigned iPDSrc;
3361 PX86PML4E pPml4eSrc;
3362 X86PDPE PdpeSrc;
3363 PGSTPD pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3364 if (!pPDSrc)
3365 return VINF_SUCCESS; /* not present */
3366# endif
3367 const GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
3368# else
3369 PGSTPD pPDSrc = NULL;
3370 const unsigned iPDSrc = 0;
3371 GSTPDE PdeSrc;
3372
3373 PdeSrc.u = 0; /* faked so we don't have to #ifdef everything */
3374 PdeSrc.n.u1Present = 1;
3375 PdeSrc.n.u1Write = 1;
3376 PdeSrc.n.u1Accessed = 1;
3377 PdeSrc.n.u1User = 1;
3378# endif
3379
3380 if (PdeSrc.n.u1Present && PdeSrc.n.u1Accessed)
3381 {
3382 PVM pVM = pVCpu->CTX_SUFF(pVM);
3383 pgmLock(pVM);
3384
3385# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3386 const X86PDE PdeDst = pgmShwGet32BitPDE(pVCpu, GCPtrPage);
3387# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3388 const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3389 PX86PDPAE pPDDst;
3390 X86PDEPAE PdeDst;
3391# if PGM_GST_TYPE != PGM_TYPE_PAE
3392 X86PDPE PdpeSrc;
3393
3394 /* Fake PDPT entry; access control handled on the page table level, so allow everything. */
3395 PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
3396# endif
3397 rc = pgmShwSyncPaePDPtr(pVCpu, GCPtrPage, PdpeSrc.u, &pPDDst);
3398 if (rc != VINF_SUCCESS)
3399 {
3400 pgmUnlock(pVM);
3401 AssertRC(rc);
3402 return rc;
3403 }
3404 Assert(pPDDst);
3405 PdeDst = pPDDst->a[iPDDst];
3406
3407# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3408 const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3409 PX86PDPAE pPDDst;
3410 X86PDEPAE PdeDst;
3411
3412# if PGM_GST_TYPE == PGM_TYPE_PROT
3413 /* AMD-V nested paging */
3414 X86PML4E Pml4eSrc;
3415 X86PDPE PdpeSrc;
3416 PX86PML4E pPml4eSrc = &Pml4eSrc;
3417
3418 /* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
3419 Pml4eSrc.u = X86_PML4E_P | X86_PML4E_RW | X86_PML4E_US | X86_PML4E_A;
3420 PdpeSrc.u = X86_PDPE_P | X86_PDPE_RW | X86_PDPE_US | X86_PDPE_A;
3421# endif
3422
3423 rc = pgmShwSyncLongModePDPtr(pVCpu, GCPtrPage, pPml4eSrc->u, PdpeSrc.u, &pPDDst);
3424 if (rc != VINF_SUCCESS)
3425 {
3426 pgmUnlock(pVM);
3427 AssertRC(rc);
3428 return rc;
3429 }
3430 Assert(pPDDst);
3431 PdeDst = pPDDst->a[iPDDst];
3432# endif
3433 if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
3434 {
3435 if (!PdeDst.n.u1Present)
3436 {
3437 /** @todo r=bird: This guy will set the A bit on the PDE,
3438 * probably harmless. */
3439 rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
3440 }
3441 else
3442 {
3443 /* Note! We used to sync PGM_SYNC_NR_PAGES pages, which triggered assertions in CSAM, because
3444 * R/W attributes of nearby pages were reset. Not sure how that could happen. Anyway, it
3445 * makes no sense to prefetch more than one page.
3446 */
3447 rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
3448 if (RT_SUCCESS(rc))
3449 rc = VINF_SUCCESS;
3450 }
3451 }
3452 pgmUnlock(pVM);
3453 }
3454 return rc;
3455
3456#elif PGM_SHW_TYPE == PGM_TYPE_NESTED || PGM_SHW_TYPE == PGM_TYPE_EPT
3457 NOREF(pVCpu); NOREF(GCPtrPage);
3458 return VINF_SUCCESS; /* ignore */
3459#else
3460 AssertCompile(0);
3461#endif
3462}
3463
3464
3465
3466
3467/**
3468 * Syncs a page during a PGMVerifyAccess() call.
3469 *
3470 * @returns VBox status code (informational included).
3471 * @param pVCpu Pointer to the VMCPU.
3472 * @param GCPtrPage The address of the page to sync.
3473 * @param fPage The effective guest page flags.
3474 * @param uErr The trap error code.
3475 * @remarks This will normally never be called on invalid guest page
3476 * translation entries.
3477 */
3478PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fPage, unsigned uErr)
3479{
3480 PVM pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
3481
3482 LogFlow(("VerifyAccessSyncPage: GCPtrPage=%RGv fPage=%#x uErr=%#x\n", GCPtrPage, fPage, uErr));
3483
3484 Assert(!pVM->pgm.s.fNestedPaging);
3485#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
3486 || PGM_GST_TYPE == PGM_TYPE_REAL \
3487 || PGM_GST_TYPE == PGM_TYPE_PROT \
3488 || PGM_GST_TYPE == PGM_TYPE_PAE \
3489 || PGM_GST_TYPE == PGM_TYPE_AMD64 ) \
3490 && PGM_SHW_TYPE != PGM_TYPE_NESTED \
3491 && PGM_SHW_TYPE != PGM_TYPE_EPT
3492
3493# ifdef VBOX_WITH_RAW_MODE_NOT_R0
3494 if (!(fPage & X86_PTE_US))
3495 {
3496 /*
3497 * Mark this page as safe.
3498 */
3499 /** @todo not correct for pages that contain both code and data!! */
3500 Log(("CSAMMarkPage %RGv; scanned=%d\n", GCPtrPage, true));
3501 CSAMMarkPage(pVM, GCPtrPage, true);
3502 }
3503# endif
3504
3505 /*
3506 * Get guest PD and index.
3507 */
3508 /** @todo Performance: We've done all this a jiffy ago in the
3509 * PGMGstGetPage call. */
3510# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3511# if PGM_GST_TYPE == PGM_TYPE_32BIT
3512 const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
3513 PGSTPD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
3514
3515# elif PGM_GST_TYPE == PGM_TYPE_PAE
3516 unsigned iPDSrc = 0;
3517 X86PDPE PdpeSrc;
3518 PGSTPD pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtrPage, &iPDSrc, &PdpeSrc);
3519 if (RT_UNLIKELY(!pPDSrc))
3520 {
3521 Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
3522 return VINF_EM_RAW_GUEST_TRAP;
3523 }
3524
3525# elif PGM_GST_TYPE == PGM_TYPE_AMD64
3526 unsigned iPDSrc = 0; /* shut up gcc */
3527 PX86PML4E pPml4eSrc = NULL; /* ditto */
3528 X86PDPE PdpeSrc;
3529 PGSTPD pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3530 if (RT_UNLIKELY(!pPDSrc))
3531 {
3532 Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
3533 return VINF_EM_RAW_GUEST_TRAP;
3534 }
3535# endif
3536
3537# else /* !PGM_WITH_PAGING */
3538 PGSTPD pPDSrc = NULL;
3539 const unsigned iPDSrc = 0;
3540# endif /* !PGM_WITH_PAGING */
3541 int rc = VINF_SUCCESS;
3542
3543 pgmLock(pVM);
3544
3545 /*
3546 * First check if the shadow pd is present.
3547 */
3548# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3549 PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
3550
3551# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3552 PX86PDEPAE pPdeDst;
3553 const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3554 PX86PDPAE pPDDst;
3555# if PGM_GST_TYPE != PGM_TYPE_PAE
3556 /* Fake PDPT entry; access control handled on the page table level, so allow everything. */
3557 X86PDPE PdpeSrc;
3558 PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
3559# endif
3560 rc = pgmShwSyncPaePDPtr(pVCpu, GCPtrPage, PdpeSrc.u, &pPDDst);
3561 if (rc != VINF_SUCCESS)
3562 {
3563 pgmUnlock(pVM);
3564 AssertRC(rc);
3565 return rc;
3566 }
3567 Assert(pPDDst);
3568 pPdeDst = &pPDDst->a[iPDDst];
3569
3570# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3571 const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3572 PX86PDPAE pPDDst;
3573 PX86PDEPAE pPdeDst;
3574
3575# if PGM_GST_TYPE == PGM_TYPE_PROT
3576 /* AMD-V nested paging: Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
3577 X86PML4E Pml4eSrc;
3578 X86PDPE PdpeSrc;
3579 PX86PML4E pPml4eSrc = &Pml4eSrc;
3580 Pml4eSrc.u = X86_PML4E_P | X86_PML4E_RW | X86_PML4E_US | X86_PML4E_A;
3581 PdpeSrc.u = X86_PDPE_P | X86_PDPE_RW | X86_PDPE_US | X86_PDPE_A;
3582# endif
3583
3584 rc = pgmShwSyncLongModePDPtr(pVCpu, GCPtrPage, pPml4eSrc->u, PdpeSrc.u, &pPDDst);
3585 if (rc != VINF_SUCCESS)
3586 {
3587 pgmUnlock(pVM);
3588 AssertRC(rc);
3589 return rc;
3590 }
3591 Assert(pPDDst);
3592 pPdeDst = &pPDDst->a[iPDDst];
3593# endif
3594
3595 if (!pPdeDst->n.u1Present)
3596 {
3597 rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
3598 if (rc != VINF_SUCCESS)
3599 {
3600 PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
3601 pgmUnlock(pVM);
3602 AssertRC(rc);
3603 return rc;
3604 }
3605 }
3606
3607# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3608 /* Check for dirty bit fault */
3609 rc = PGM_BTH_NAME(CheckDirtyPageFault)(pVCpu, uErr, pPdeDst, &pPDSrc->a[iPDSrc], GCPtrPage);
3610 if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
3611 Log(("PGMVerifyAccess: success (dirty)\n"));
3612 else
3613# endif
3614 {
3615# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3616 GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
3617# else
3618 GSTPDE PdeSrc;
3619 PdeSrc.u = 0; /* faked so we don't have to #ifdef everything */
3620 PdeSrc.n.u1Present = 1;
3621 PdeSrc.n.u1Write = 1;
3622 PdeSrc.n.u1Accessed = 1;
3623 PdeSrc.n.u1User = 1;
3624# endif
3625
3626 Assert(rc != VINF_EM_RAW_GUEST_TRAP);
3627 if (uErr & X86_TRAP_PF_US)
3628 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncUser));
3629 else /* supervisor */
3630 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
3631
3632 rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
3633 if (RT_SUCCESS(rc))
3634 {
3635 /* Page was successfully synced */
3636 Log2(("PGMVerifyAccess: success (sync)\n"));
3637 rc = VINF_SUCCESS;
3638 }
3639 else
3640 {
3641 Log(("PGMVerifyAccess: access violation for %RGv rc=%Rrc\n", GCPtrPage, rc));
3642 rc = VINF_EM_RAW_GUEST_TRAP;
3643 }
3644 }
3645 PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
3646 pgmUnlock(pVM);
3647 return rc;
3648
3649#else /* PGM_SHW_TYPE == PGM_TYPE_EPT || PGM_SHW_TYPE == PGM_TYPE_NESTED */
3650
3651 AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
3652 return VERR_PGM_NOT_USED_IN_MODE;
3653#endif /* PGM_SHW_TYPE == PGM_TYPE_EPT || PGM_SHW_TYPE == PGM_TYPE_NESTED */
3654}
3655
3656
3657/**
3658 * Syncs the paging hierarchy starting at CR3.
3659 *
3660 * @returns VBox status code, no specials.
3661 * @param pVCpu Pointer to the VMCPU.
3662 * @param cr0 Guest context CR0 register.
3663 * @param cr3 Guest context CR3 register. Not subjected to the A20
3664 * mask.
3665 * @param cr4 Guest context CR4 register.
3666 * @param fGlobal Including global page directories or not
3667 */
3668PGM_BTH_DECL(int, SyncCR3)(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
3669{
3670 PVM pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
3671 NOREF(cr0); NOREF(cr3); NOREF(cr4); NOREF(fGlobal);
3672
3673 LogFlow(("SyncCR3 FF=%d fGlobal=%d\n", !!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3), fGlobal));
3674
3675#if PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
3676
3677 pgmLock(pVM);
3678
3679# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
3680 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3681 if (pPool->cDirtyPages)
3682 pgmPoolResetDirtyPages(pVM);
3683# endif
3684
3685 /*
3686 * Update page access handlers.
3687 * The virtual are always flushed, while the physical are only on demand.
3688 * WARNING: We are incorrectly not doing global flushing on Virtual Handler updates. We'll
3689 * have to look into that later because it will have a bad influence on the performance.
3690 * @note SvL: There's no need for that. Just invalidate the virtual range(s).
3691 * bird: Yes, but that won't work for aliases.
3692 */
3693 /** @todo this MUST go away. See @bugref{1557}. */
3694 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3Handlers), h);
3695 PGM_GST_NAME(HandlerVirtualUpdate)(pVM, cr4);
3696 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3Handlers), h);
3697 pgmUnlock(pVM);
3698#endif /* !NESTED && !EPT */
3699
3700#if PGM_SHW_TYPE == PGM_TYPE_NESTED || PGM_SHW_TYPE == PGM_TYPE_EPT
3701 /*
3702 * Nested / EPT - almost no work.
3703 */
3704 Assert(!pgmMapAreMappingsEnabled(pVM));
3705 return VINF_SUCCESS;
3706
3707#elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3708 /*
3709 * AMD64 (Shw & Gst) - No need to check all paging levels; we zero
3710 * out the shadow parts when the guest modifies its tables.
3711 */
3712 Assert(!pgmMapAreMappingsEnabled(pVM));
3713 return VINF_SUCCESS;
3714
3715#else /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
3716
3717# ifndef PGM_WITHOUT_MAPPINGS
3718 /*
3719 * Check for and resolve conflicts with our guest mappings if they
3720 * are enabled and not fixed.
3721 */
3722 if (pgmMapAreMappingsFloating(pVM))
3723 {
3724 int rc = pgmMapResolveConflicts(pVM);
3725 Assert(rc == VINF_SUCCESS || rc == VINF_PGM_SYNC_CR3);
3726 if (rc == VINF_PGM_SYNC_CR3)
3727 {
3728 LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
3729 return VINF_PGM_SYNC_CR3;
3730 }
3731 }
3732# else
3733 Assert(!pgmMapAreMappingsEnabled(pVM));
3734# endif
3735 return VINF_SUCCESS;
3736#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
3737}
3738
3739
3740
3741
3742#ifdef VBOX_STRICT
3743# ifdef IN_RC
3744# undef AssertMsgFailed
3745# define AssertMsgFailed Log
3746# endif
3747
3748/**
3749 * Checks that the shadow page table is in sync with the guest one.
3750 *
3751 * @returns The number of errors.
3752 * @param pVM The virtual machine.
3753 * @param pVCpu Pointer to the VMCPU.
3754 * @param cr3 Guest context CR3 register.
3755 * @param cr4 Guest context CR4 register.
3756 * @param GCPtr Where to start. Defaults to 0.
3757 * @param cb How much to check. Defaults to everything.
3758 */
3759PGM_BTH_DECL(unsigned, AssertCR3)(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb)
3760{
3761 NOREF(pVCpu); NOREF(cr3); NOREF(cr4); NOREF(GCPtr); NOREF(cb);
3762#if PGM_SHW_TYPE == PGM_TYPE_NESTED || PGM_SHW_TYPE == PGM_TYPE_EPT
3763 return 0;
3764#else
3765 unsigned cErrors = 0;
3766 PVM pVM = pVCpu->CTX_SUFF(pVM);
3767 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool); NOREF(pPool);
3768
3769# if PGM_GST_TYPE == PGM_TYPE_PAE
3770 /** @todo currently broken; crashes below somewhere */
3771 AssertFailed();
3772# endif
3773
3774# if PGM_GST_TYPE == PGM_TYPE_32BIT \
3775 || PGM_GST_TYPE == PGM_TYPE_PAE \
3776 || PGM_GST_TYPE == PGM_TYPE_AMD64
3777
3778 bool fBigPagesSupported = GST_IS_PSE_ACTIVE(pVCpu);
3779 PPGMCPU pPGM = &pVCpu->pgm.s;
3780 RTGCPHYS GCPhysGst; /* page address derived from the guest page tables. */
3781 RTHCPHYS HCPhysShw; /* page address derived from the shadow page tables. */
3782# ifndef IN_RING0
3783 RTHCPHYS HCPhys; /* general usage. */
3784# endif
3785 int rc;
3786
3787 /*
3788 * Check that the Guest CR3 and all its mappings are correct.
3789 */
3790 AssertMsgReturn(pPGM->GCPhysCR3 == PGM_A20_APPLY(pVCpu, cr3 & GST_CR3_PAGE_MASK),
3791 ("Invalid GCPhysCR3=%RGp cr3=%RGp\n", pPGM->GCPhysCR3, (RTGCPHYS)cr3),
3792 false);
3793# if !defined(IN_RING0) && PGM_GST_TYPE != PGM_TYPE_AMD64
3794# if PGM_GST_TYPE == PGM_TYPE_32BIT
3795 rc = PGMShwGetPage(pVCpu, (RTRCUINTPTR)pPGM->pGst32BitPdRC, NULL, &HCPhysShw);
3796# else
3797 rc = PGMShwGetPage(pVCpu, (RTRCUINTPTR)pPGM->pGstPaePdptRC, NULL, &HCPhysShw);
3798# endif
3799 AssertRCReturn(rc, 1);
3800 HCPhys = NIL_RTHCPHYS;
3801 rc = pgmRamGCPhys2HCPhys(pVM, PGM_A20_APPLY(pVCpu, cr3 & GST_CR3_PAGE_MASK), &HCPhys);
3802 AssertMsgReturn(HCPhys == HCPhysShw, ("HCPhys=%RHp HCPhyswShw=%RHp (cr3)\n", HCPhys, HCPhysShw), false);
3803# if PGM_GST_TYPE == PGM_TYPE_32BIT && defined(IN_RING3)
3804 pgmGstGet32bitPDPtr(pVCpu);
3805 RTGCPHYS GCPhys;
3806 rc = PGMR3DbgR3Ptr2GCPhys(pVM->pUVM, pPGM->pGst32BitPdR3, &GCPhys);
3807 AssertRCReturn(rc, 1);
3808 AssertMsgReturn(PGM_A20_APPLY(pVCpu, cr3 & GST_CR3_PAGE_MASK) == GCPhys, ("GCPhys=%RGp cr3=%RGp\n", GCPhys, (RTGCPHYS)cr3), false);
3809# endif
3810# endif /* !IN_RING0 */
3811
3812 /*
3813 * Get and check the Shadow CR3.
3814 */
3815# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3816 unsigned cPDEs = X86_PG_ENTRIES;
3817 unsigned cIncrement = X86_PG_ENTRIES * PAGE_SIZE;
3818# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3819# if PGM_GST_TYPE == PGM_TYPE_32BIT
3820 unsigned cPDEs = X86_PG_PAE_ENTRIES * 4; /* treat it as a 2048 entry table. */
3821# else
3822 unsigned cPDEs = X86_PG_PAE_ENTRIES;
3823# endif
3824 unsigned cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3825# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3826 unsigned cPDEs = X86_PG_PAE_ENTRIES;
3827 unsigned cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3828# endif
3829 if (cb != ~(RTGCPTR)0)
3830 cPDEs = RT_MIN(cb >> SHW_PD_SHIFT, 1);
3831
3832/** @todo call the other two PGMAssert*() functions. */
3833
3834# if PGM_GST_TYPE == PGM_TYPE_AMD64
3835 unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3836
3837 for (; iPml4 < X86_PG_PAE_ENTRIES; iPml4++)
3838 {
3839 PPGMPOOLPAGE pShwPdpt = NULL;
3840 PX86PML4E pPml4eSrc;
3841 PX86PML4E pPml4eDst;
3842 RTGCPHYS GCPhysPdptSrc;
3843
3844 pPml4eSrc = pgmGstGetLongModePML4EPtr(pVCpu, iPml4);
3845 pPml4eDst = pgmShwGetLongModePML4EPtr(pVCpu, iPml4);
3846
3847 /* Fetch the pgm pool shadow descriptor if the shadow pml4e is present. */
3848 if (!pPml4eDst->n.u1Present)
3849 {
3850 GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3851 continue;
3852 }
3853
3854 pShwPdpt = pgmPoolGetPage(pPool, pPml4eDst->u & X86_PML4E_PG_MASK);
3855 GCPhysPdptSrc = PGM_A20_APPLY(pVCpu, pPml4eSrc->u & X86_PML4E_PG_MASK);
3856
3857 if (pPml4eSrc->n.u1Present != pPml4eDst->n.u1Present)
3858 {
3859 AssertMsgFailed(("Present bit doesn't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3860 GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3861 cErrors++;
3862 continue;
3863 }
3864
3865 if (GCPhysPdptSrc != pShwPdpt->GCPhys)
3866 {
3867 AssertMsgFailed(("Physical address doesn't match! iPml4 %d pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, pPml4eDst->u, pPml4eSrc->u, pShwPdpt->GCPhys, GCPhysPdptSrc));
3868 GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3869 cErrors++;
3870 continue;
3871 }
3872
3873 if ( pPml4eDst->n.u1User != pPml4eSrc->n.u1User
3874 || pPml4eDst->n.u1Write != pPml4eSrc->n.u1Write
3875 || pPml4eDst->n.u1NoExecute != pPml4eSrc->n.u1NoExecute)
3876 {
3877 AssertMsgFailed(("User/Write/NoExec bits don't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3878 GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3879 cErrors++;
3880 continue;
3881 }
3882# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
3883 {
3884# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
3885
3886# if PGM_GST_TYPE == PGM_TYPE_AMD64 || PGM_GST_TYPE == PGM_TYPE_PAE
3887 /*
3888 * Check the PDPTEs too.
3889 */
3890 unsigned iPdpt = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
3891
3892 for (;iPdpt <= SHW_PDPT_MASK; iPdpt++)
3893 {
3894 unsigned iPDSrc = 0; /* initialized to shut up gcc */
3895 PPGMPOOLPAGE pShwPde = NULL;
3896 PX86PDPE pPdpeDst;
3897 RTGCPHYS GCPhysPdeSrc;
3898 X86PDPE PdpeSrc;
3899 PdpeSrc.u = 0; /* initialized to shut up gcc 4.5 */
3900# if PGM_GST_TYPE == PGM_TYPE_PAE
3901 PGSTPD pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtr, &iPDSrc, &PdpeSrc);
3902 PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(pVCpu);
3903# else
3904 PX86PML4E pPml4eSrcIgn;
3905 PX86PDPT pPdptDst;
3906 PX86PDPAE pPDDst;
3907 PGSTPD pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtr, &pPml4eSrcIgn, &PdpeSrc, &iPDSrc);
3908
3909 rc = pgmShwGetLongModePDPtr(pVCpu, GCPtr, NULL, &pPdptDst, &pPDDst);
3910 if (rc != VINF_SUCCESS)
3911 {
3912 AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
3913 GCPtr += 512 * _2M;
3914 continue; /* next PDPTE */
3915 }
3916 Assert(pPDDst);
3917# endif
3918 Assert(iPDSrc == 0);
3919
3920 pPdpeDst = &pPdptDst->a[iPdpt];
3921
3922 if (!pPdpeDst->n.u1Present)
3923 {
3924 GCPtr += 512 * _2M;
3925 continue; /* next PDPTE */
3926 }
3927
3928 pShwPde = pgmPoolGetPage(pPool, pPdpeDst->u & X86_PDPE_PG_MASK);
3929 GCPhysPdeSrc = PGM_A20_APPLY(pVCpu, PdpeSrc.u & X86_PDPE_PG_MASK);
3930
3931 if (pPdpeDst->n.u1Present != PdpeSrc.n.u1Present)
3932 {
3933 AssertMsgFailed(("Present bit doesn't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3934 GCPtr += 512 * _2M;
3935 cErrors++;
3936 continue;
3937 }
3938
3939 if (GCPhysPdeSrc != pShwPde->GCPhys)
3940 {
3941# if PGM_GST_TYPE == PGM_TYPE_AMD64
3942 AssertMsgFailed(("Physical address doesn't match! iPml4 %d iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3943# else
3944 AssertMsgFailed(("Physical address doesn't match! iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3945# endif
3946 GCPtr += 512 * _2M;
3947 cErrors++;
3948 continue;
3949 }
3950
3951# if PGM_GST_TYPE == PGM_TYPE_AMD64
3952 if ( pPdpeDst->lm.u1User != PdpeSrc.lm.u1User
3953 || pPdpeDst->lm.u1Write != PdpeSrc.lm.u1Write
3954 || pPdpeDst->lm.u1NoExecute != PdpeSrc.lm.u1NoExecute)
3955 {
3956 AssertMsgFailed(("User/Write/NoExec bits don't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3957 GCPtr += 512 * _2M;
3958 cErrors++;
3959 continue;
3960 }
3961# endif
3962
3963# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
3964 {
3965# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
3966# if PGM_GST_TYPE == PGM_TYPE_32BIT
3967 GSTPD const *pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
3968# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3969 PCX86PD pPDDst = pgmShwGet32BitPDPtr(pVCpu);
3970# endif
3971# endif /* PGM_GST_TYPE == PGM_TYPE_32BIT */
3972 /*
3973 * Iterate the shadow page directory.
3974 */
3975 GCPtr = (GCPtr >> SHW_PD_SHIFT) << SHW_PD_SHIFT;
3976 unsigned iPDDst = (GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK;
3977
3978 for (;
3979 iPDDst < cPDEs;
3980 iPDDst++, GCPtr += cIncrement)
3981 {
3982# if PGM_SHW_TYPE == PGM_TYPE_PAE
3983 const SHWPDE PdeDst = *pgmShwGetPaePDEPtr(pVCpu, GCPtr);
3984# else
3985 const SHWPDE PdeDst = pPDDst->a[iPDDst];
3986# endif
3987 if (PdeDst.u & PGM_PDFLAGS_MAPPING)
3988 {
3989 Assert(pgmMapAreMappingsEnabled(pVM));
3990 if ((PdeDst.u & X86_PDE_AVL_MASK) != PGM_PDFLAGS_MAPPING)
3991 {
3992 AssertMsgFailed(("Mapping shall only have PGM_PDFLAGS_MAPPING set! PdeDst.u=%#RX64\n", (uint64_t)PdeDst.u));
3993 cErrors++;
3994 continue;
3995 }
3996 }
3997 else if ( (PdeDst.u & X86_PDE_P)
3998 || ((PdeDst.u & (X86_PDE_P | PGM_PDFLAGS_TRACK_DIRTY)) == (X86_PDE_P | PGM_PDFLAGS_TRACK_DIRTY))
3999 )
4000 {
4001 HCPhysShw = PdeDst.u & SHW_PDE_PG_MASK;
4002 PPGMPOOLPAGE pPoolPage = pgmPoolGetPage(pPool, HCPhysShw);
4003 if (!pPoolPage)
4004 {
4005 AssertMsgFailed(("Invalid page table address %RHp at %RGv! PdeDst=%#RX64\n",
4006 HCPhysShw, GCPtr, (uint64_t)PdeDst.u));
4007 cErrors++;
4008 continue;
4009 }
4010 const SHWPT *pPTDst = (const SHWPT *)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pPoolPage);
4011
4012 if (PdeDst.u & (X86_PDE4M_PWT | X86_PDE4M_PCD))
4013 {
4014 AssertMsgFailed(("PDE flags PWT and/or PCD is set at %RGv! These flags are not virtualized! PdeDst=%#RX64\n",
4015 GCPtr, (uint64_t)PdeDst.u));
4016 cErrors++;
4017 }
4018
4019 if (PdeDst.u & (X86_PDE4M_G | X86_PDE4M_D))
4020 {
4021 AssertMsgFailed(("4K PDE reserved flags at %RGv! PdeDst=%#RX64\n",
4022 GCPtr, (uint64_t)PdeDst.u));
4023 cErrors++;
4024 }
4025
4026 const GSTPDE PdeSrc = pPDSrc->a[(iPDDst >> (GST_PD_SHIFT - SHW_PD_SHIFT)) & GST_PD_MASK];
4027 if (!PdeSrc.n.u1Present)
4028 {
4029 AssertMsgFailed(("Guest PDE at %RGv is not present! PdeDst=%#RX64 PdeSrc=%#RX64\n",
4030 GCPtr, (uint64_t)PdeDst.u, (uint64_t)PdeSrc.u));
4031 cErrors++;
4032 continue;
4033 }
4034
4035 if ( !PdeSrc.b.u1Size
4036 || !fBigPagesSupported)
4037 {
4038 GCPhysGst = GST_GET_PDE_GCPHYS(PdeSrc);
4039# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
4040 GCPhysGst = PGM_A20_APPLY(pVCpu, GCPhysGst | ((iPDDst & 1) * (PAGE_SIZE / 2)));
4041# endif
4042 }
4043 else
4044 {
4045# if PGM_GST_TYPE == PGM_TYPE_32BIT
4046 if (PdeSrc.u & X86_PDE4M_PG_HIGH_MASK)
4047 {
4048 AssertMsgFailed(("Guest PDE at %RGv is using PSE36 or similar! PdeSrc=%#RX64\n",
4049 GCPtr, (uint64_t)PdeSrc.u));
4050 cErrors++;
4051 continue;
4052 }
4053# endif
4054 GCPhysGst = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
4055# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
4056 GCPhysGst = PGM_A20_APPLY(pVCpu, GCPhysGst | (GCPtr & RT_BIT(X86_PAGE_2M_SHIFT)));
4057# endif
4058 }
4059
4060 if ( pPoolPage->enmKind
4061 != (!PdeSrc.b.u1Size || !fBigPagesSupported ? BTH_PGMPOOLKIND_PT_FOR_PT : BTH_PGMPOOLKIND_PT_FOR_BIG))
4062 {
4063 AssertMsgFailed(("Invalid shadow page table kind %d at %RGv! PdeSrc=%#RX64\n",
4064 pPoolPage->enmKind, GCPtr, (uint64_t)PdeSrc.u));
4065 cErrors++;
4066 }
4067
4068 PPGMPAGE pPhysPage = pgmPhysGetPage(pVM, GCPhysGst);
4069 if (!pPhysPage)
4070 {
4071 AssertMsgFailed(("Cannot find guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
4072 GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
4073 cErrors++;
4074 continue;
4075 }
4076
4077 if (GCPhysGst != pPoolPage->GCPhys)
4078 {
4079 AssertMsgFailed(("GCPhysGst=%RGp != pPage->GCPhys=%RGp at %RGv\n",
4080 GCPhysGst, pPoolPage->GCPhys, GCPtr));
4081 cErrors++;
4082 continue;
4083 }
4084
4085 if ( !PdeSrc.b.u1Size
4086 || !fBigPagesSupported)
4087 {
4088 /*
4089 * Page Table.
4090 */
4091 const GSTPT *pPTSrc;
4092 rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, PGM_A20_APPLY(pVCpu, GCPhysGst & ~(RTGCPHYS)(PAGE_SIZE - 1)),
4093 &pPTSrc);
4094 if (RT_FAILURE(rc))
4095 {
4096 AssertMsgFailed(("Cannot map/convert guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
4097 GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
4098 cErrors++;
4099 continue;
4100 }
4101 if ( (PdeSrc.u & (X86_PDE_P | X86_PDE_US | X86_PDE_RW/* | X86_PDE_A*/))
4102 != (PdeDst.u & (X86_PDE_P | X86_PDE_US | X86_PDE_RW/* | X86_PDE_A*/)))
4103 {
4104 /// @todo We get here a lot on out-of-sync CR3 entries. The access handler should zap them to avoid false alarms here!
4105 // (This problem will go away when/if we shadow multiple CR3s.)
4106 AssertMsgFailed(("4K PDE flags mismatch at %RGv! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4107 GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4108 cErrors++;
4109 continue;
4110 }
4111 if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
4112 {
4113 AssertMsgFailed(("4K PDEs cannot have PGM_PDFLAGS_TRACK_DIRTY set! GCPtr=%RGv PdeDst=%#RX64\n",
4114 GCPtr, (uint64_t)PdeDst.u));
4115 cErrors++;
4116 continue;
4117 }
4118
4119 /* iterate the page table. */
4120# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
4121 /* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
4122 const unsigned offPTSrc = ((GCPtr >> SHW_PD_SHIFT) & 1) * 512;
4123# else
4124 const unsigned offPTSrc = 0;
4125# endif
4126 for (unsigned iPT = 0, off = 0;
4127 iPT < RT_ELEMENTS(pPTDst->a);
4128 iPT++, off += PAGE_SIZE)
4129 {
4130 const SHWPTE PteDst = pPTDst->a[iPT];
4131
4132 /* skip not-present and dirty tracked entries. */
4133 if (!(SHW_PTE_GET_U(PteDst) & (X86_PTE_P | PGM_PTFLAGS_TRACK_DIRTY))) /** @todo deal with ALL handlers and CSAM !P pages! */
4134 continue;
4135 Assert(SHW_PTE_IS_P(PteDst));
4136
4137 const GSTPTE PteSrc = pPTSrc->a[iPT + offPTSrc];
4138 if (!PteSrc.n.u1Present)
4139 {
4140# ifdef IN_RING3
4141 PGMAssertHandlerAndFlagsInSync(pVM);
4142 DBGFR3PagingDumpEx(pVM->pUVM, pVCpu->idCpu, DBGFPGDMP_FLAGS_CURRENT_CR3 | DBGFPGDMP_FLAGS_CURRENT_MODE
4143 | DBGFPGDMP_FLAGS_GUEST | DBGFPGDMP_FLAGS_HEADER | DBGFPGDMP_FLAGS_PRINT_CR3,
4144 0, 0, UINT64_MAX, 99, NULL);
4145# endif
4146 AssertMsgFailed(("Out of sync (!P) PTE at %RGv! PteSrc=%#RX64 PteDst=%#RX64 pPTSrc=%RGv iPTSrc=%x PdeSrc=%x physpte=%RGp\n",
4147 GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst), pPTSrc, iPT + offPTSrc, PdeSrc.au32[0],
4148 (uint64_t)GST_GET_PDE_GCPHYS(PdeSrc) + (iPT + offPTSrc) * sizeof(PteSrc)));
4149 cErrors++;
4150 continue;
4151 }
4152
4153 uint64_t fIgnoreFlags = GST_PTE_PG_MASK | X86_PTE_AVL_MASK | X86_PTE_G | X86_PTE_D | X86_PTE_PWT | X86_PTE_PCD | X86_PTE_PAT;
4154# if 1 /** @todo sync accessed bit properly... */
4155 fIgnoreFlags |= X86_PTE_A;
4156# endif
4157
4158 /* match the physical addresses */
4159 HCPhysShw = SHW_PTE_GET_HCPHYS(PteDst);
4160 GCPhysGst = GST_GET_PTE_GCPHYS(PteSrc);
4161
4162# ifdef IN_RING3
4163 rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
4164 if (RT_FAILURE(rc))
4165 {
4166 if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4167 {
4168 AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
4169 GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4170 cErrors++;
4171 continue;
4172 }
4173 }
4174 else if (HCPhysShw != (HCPhys & SHW_PTE_PG_MASK))
4175 {
4176 AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4177 GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4178 cErrors++;
4179 continue;
4180 }
4181# endif
4182
4183 pPhysPage = pgmPhysGetPage(pVM, GCPhysGst);
4184 if (!pPhysPage)
4185 {
4186# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
4187 if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4188 {
4189 AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
4190 GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4191 cErrors++;
4192 continue;
4193 }
4194# endif
4195 if (SHW_PTE_IS_RW(PteDst))
4196 {
4197 AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4198 GCPtr + off, GCPhysGst, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4199 cErrors++;
4200 }
4201 fIgnoreFlags |= X86_PTE_RW;
4202 }
4203 else if (HCPhysShw != PGM_PAGE_GET_HCPHYS(pPhysPage))
4204 {
4205 AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp pPhysPage:%R[pgmpage] GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4206 GCPtr + off, HCPhysShw, pPhysPage, GCPhysGst, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4207 cErrors++;
4208 continue;
4209 }
4210
4211 /* flags */
4212 if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
4213 {
4214 if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
4215 {
4216 if (SHW_PTE_IS_RW(PteDst))
4217 {
4218 AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! pPhysPage=%R[pgmpage] PteSrc=%#RX64 PteDst=%#RX64\n",
4219 GCPtr + off, pPhysPage, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4220 cErrors++;
4221 continue;
4222 }
4223 fIgnoreFlags |= X86_PTE_RW;
4224 }
4225 else
4226 {
4227 if ( SHW_PTE_IS_P(PteDst)
4228# if PGM_SHW_TYPE == PGM_TYPE_EPT || PGM_SHW_TYPE == PGM_TYPE_PAE || PGM_SHW_TYPE == PGM_TYPE_AMD64
4229 && !PGM_PAGE_IS_MMIO(pPhysPage)
4230# endif
4231 )
4232 {
4233 AssertMsgFailed(("ALL access flagged at %RGv but the page is present! pPhysPage=%R[pgmpage] PteSrc=%#RX64 PteDst=%#RX64\n",
4234 GCPtr + off, pPhysPage, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4235 cErrors++;
4236 continue;
4237 }
4238 fIgnoreFlags |= X86_PTE_P;
4239 }
4240 }
4241 else
4242 {
4243 if (!PteSrc.n.u1Dirty && PteSrc.n.u1Write)
4244 {
4245 if (SHW_PTE_IS_RW(PteDst))
4246 {
4247 AssertMsgFailed(("!DIRTY page at %RGv is writable! PteSrc=%#RX64 PteDst=%#RX64\n",
4248 GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4249 cErrors++;
4250 continue;
4251 }
4252 if (!SHW_PTE_IS_TRACK_DIRTY(PteDst))
4253 {
4254 AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4255 GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4256 cErrors++;
4257 continue;
4258 }
4259 if (SHW_PTE_IS_D(PteDst))
4260 {
4261 AssertMsgFailed(("!DIRTY page at %RGv is marked DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4262 GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4263 cErrors++;
4264 }
4265# if 0 /** @todo sync access bit properly... */
4266 if (PteDst.n.u1Accessed != PteSrc.n.u1Accessed)
4267 {
4268 AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4269 GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4270 cErrors++;
4271 }
4272 fIgnoreFlags |= X86_PTE_RW;
4273# else
4274 fIgnoreFlags |= X86_PTE_RW | X86_PTE_A;
4275# endif
4276 }
4277 else if (SHW_PTE_IS_TRACK_DIRTY(PteDst))
4278 {
4279 /* access bit emulation (not implemented). */
4280 if (PteSrc.n.u1Accessed || SHW_PTE_IS_P(PteDst))
4281 {
4282 AssertMsgFailed(("PGM_PTFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PteSrc=%#RX64 PteDst=%#RX64\n",
4283 GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4284 cErrors++;
4285 continue;
4286 }
4287 if (!SHW_PTE_IS_A(PteDst))
4288 {
4289 AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PteSrc=%#RX64 PteDst=%#RX64\n",
4290 GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4291 cErrors++;
4292 }
4293 fIgnoreFlags |= X86_PTE_P;
4294 }
4295# ifdef DEBUG_sandervl
4296 fIgnoreFlags |= X86_PTE_D | X86_PTE_A;
4297# endif
4298 }
4299
4300 if ( (PteSrc.u & ~fIgnoreFlags) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags)
4301 && (PteSrc.u & ~(fIgnoreFlags | X86_PTE_RW)) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags)
4302 )
4303 {
4304 AssertMsgFailed(("Flags mismatch at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PteSrc=%#RX64 PteDst=%#RX64\n",
4305 GCPtr + off, (uint64_t)PteSrc.u & ~fIgnoreFlags, SHW_PTE_LOG64(PteDst) & ~fIgnoreFlags,
4306 fIgnoreFlags, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4307 cErrors++;
4308 continue;
4309 }
4310 } /* foreach PTE */
4311 }
4312 else
4313 {
4314 /*
4315 * Big Page.
4316 */
4317 uint64_t fIgnoreFlags = X86_PDE_AVL_MASK | GST_PDE_PG_MASK | X86_PDE4M_G | X86_PDE4M_D | X86_PDE4M_PS | X86_PDE4M_PWT | X86_PDE4M_PCD;
4318 if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
4319 {
4320 if (PdeDst.n.u1Write)
4321 {
4322 AssertMsgFailed(("!DIRTY page at %RGv is writable! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4323 GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4324 cErrors++;
4325 continue;
4326 }
4327 if (!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY))
4328 {
4329 AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4330 GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4331 cErrors++;
4332 continue;
4333 }
4334# if 0 /** @todo sync access bit properly... */
4335 if (PdeDst.n.u1Accessed != PdeSrc.b.u1Accessed)
4336 {
4337 AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4338 GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4339 cErrors++;
4340 }
4341 fIgnoreFlags |= X86_PTE_RW;
4342# else
4343 fIgnoreFlags |= X86_PTE_RW | X86_PTE_A;
4344# endif
4345 }
4346 else if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
4347 {
4348 /* access bit emulation (not implemented). */
4349 if (PdeSrc.b.u1Accessed || PdeDst.n.u1Present)
4350 {
4351 AssertMsgFailed(("PGM_PDFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4352 GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4353 cErrors++;
4354 continue;
4355 }
4356 if (!PdeDst.n.u1Accessed)
4357 {
4358 AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4359 GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4360 cErrors++;
4361 }
4362 fIgnoreFlags |= X86_PTE_P;
4363 }
4364
4365 if ((PdeSrc.u & ~fIgnoreFlags) != (PdeDst.u & ~fIgnoreFlags))
4366 {
4367 AssertMsgFailed(("Flags mismatch (B) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PdeDst=%#RX64\n",
4368 GCPtr, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PdeDst.u & ~fIgnoreFlags,
4369 fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4370 cErrors++;
4371 }
4372
4373 /* iterate the page table. */
4374 for (unsigned iPT = 0, off = 0;
4375 iPT < RT_ELEMENTS(pPTDst->a);
4376 iPT++, off += PAGE_SIZE, GCPhysGst = PGM_A20_APPLY(pVCpu, GCPhysGst + PAGE_SIZE))
4377 {
4378 const SHWPTE PteDst = pPTDst->a[iPT];
4379
4380 if (SHW_PTE_IS_TRACK_DIRTY(PteDst))
4381 {
4382 AssertMsgFailed(("The PTE at %RGv emulating a 2/4M page is marked TRACK_DIRTY! PdeSrc=%#RX64 PteDst=%#RX64\n",
4383 GCPtr + off, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4384 cErrors++;
4385 }
4386
4387 /* skip not-present entries. */
4388 if (!SHW_PTE_IS_P(PteDst)) /** @todo deal with ALL handlers and CSAM !P pages! */
4389 continue;
4390
4391 fIgnoreFlags = X86_PTE_PAE_PG_MASK | X86_PTE_AVL_MASK | X86_PTE_PWT | X86_PTE_PCD | X86_PTE_PAT | X86_PTE_D | X86_PTE_A | X86_PTE_G | X86_PTE_PAE_NX;
4392
4393 /* match the physical addresses */
4394 HCPhysShw = SHW_PTE_GET_HCPHYS(PteDst);
4395
4396# ifdef IN_RING3
4397 rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
4398 if (RT_FAILURE(rc))
4399 {
4400 if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4401 {
4402 AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4403 GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4404 cErrors++;
4405 }
4406 }
4407 else if (HCPhysShw != (HCPhys & X86_PTE_PAE_PG_MASK))
4408 {
4409 AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4410 GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4411 cErrors++;
4412 continue;
4413 }
4414# endif
4415 pPhysPage = pgmPhysGetPage(pVM, GCPhysGst);
4416 if (!pPhysPage)
4417 {
4418# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
4419 if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4420 {
4421 AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4422 GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4423 cErrors++;
4424 continue;
4425 }
4426# endif
4427 if (SHW_PTE_IS_RW(PteDst))
4428 {
4429 AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4430 GCPtr + off, GCPhysGst, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4431 cErrors++;
4432 }
4433 fIgnoreFlags |= X86_PTE_RW;
4434 }
4435 else if (HCPhysShw != PGM_PAGE_GET_HCPHYS(pPhysPage))
4436 {
4437 AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp pPhysPage=%R[pgmpage] GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4438 GCPtr + off, HCPhysShw, pPhysPage, GCPhysGst, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4439 cErrors++;
4440 continue;
4441 }
4442
4443 /* flags */
4444 if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
4445 {
4446 if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
4447 {
4448 if (PGM_PAGE_GET_HNDL_PHYS_STATE(pPhysPage) != PGM_PAGE_HNDL_PHYS_STATE_DISABLED)
4449 {
4450 if (SHW_PTE_IS_RW(PteDst))
4451 {
4452 AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! pPhysPage=%R[pgmpage] PdeSrc=%#RX64 PteDst=%#RX64\n",
4453 GCPtr + off, pPhysPage, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4454 cErrors++;
4455 continue;
4456 }
4457 fIgnoreFlags |= X86_PTE_RW;
4458 }
4459 }
4460 else
4461 {
4462 if ( SHW_PTE_IS_P(PteDst)
4463# if PGM_SHW_TYPE == PGM_TYPE_EPT || PGM_SHW_TYPE == PGM_TYPE_PAE || PGM_SHW_TYPE == PGM_TYPE_AMD64
4464 && !PGM_PAGE_IS_MMIO(pPhysPage)
4465# endif
4466 )
4467 {
4468 AssertMsgFailed(("ALL access flagged at %RGv but the page is present! pPhysPage=%R[pgmpage] PdeSrc=%#RX64 PteDst=%#RX64\n",
4469 GCPtr + off, pPhysPage, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4470 cErrors++;
4471 continue;
4472 }
4473 fIgnoreFlags |= X86_PTE_P;
4474 }
4475 }
4476
4477 if ( (PdeSrc.u & ~fIgnoreFlags) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags)
4478 && (PdeSrc.u & ~(fIgnoreFlags | X86_PTE_RW)) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags) /* lazy phys handler dereg. */
4479 )
4480 {
4481 AssertMsgFailed(("Flags mismatch (BT) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PteDst=%#RX64\n",
4482 GCPtr + off, (uint64_t)PdeSrc.u & ~fIgnoreFlags, SHW_PTE_LOG64(PteDst) & ~fIgnoreFlags,
4483 fIgnoreFlags, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4484 cErrors++;
4485 continue;
4486 }
4487 } /* for each PTE */
4488 }
4489 }
4490 /* not present */
4491
4492 } /* for each PDE */
4493
4494 } /* for each PDPTE */
4495
4496 } /* for each PML4E */
4497
4498# ifdef DEBUG
4499 if (cErrors)
4500 LogFlow(("AssertCR3: cErrors=%d\n", cErrors));
4501# endif
4502# endif /* GST is in {32BIT, PAE, AMD64} */
4503 return cErrors;
4504#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT */
4505}
4506#endif /* VBOX_STRICT */
4507
4508
4509/**
4510 * Sets up the CR3 for shadow paging
4511 *
4512 * @returns Strict VBox status code.
4513 * @retval VINF_SUCCESS.
4514 *
4515 * @param pVCpu Pointer to the VMCPU.
4516 * @param GCPhysCR3 The physical address in the CR3 register. (A20
4517 * mask already applied.)
4518 */
4519PGM_BTH_DECL(int, MapCR3)(PVMCPU pVCpu, RTGCPHYS GCPhysCR3)
4520{
4521 PVM pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
4522
4523 /* Update guest paging info. */
4524#if PGM_GST_TYPE == PGM_TYPE_32BIT \
4525 || PGM_GST_TYPE == PGM_TYPE_PAE \
4526 || PGM_GST_TYPE == PGM_TYPE_AMD64
4527
4528 LogFlow(("MapCR3: %RGp\n", GCPhysCR3));
4529 PGM_A20_ASSERT_MASKED(pVCpu, GCPhysCR3);
4530
4531 /*
4532 * Map the page CR3 points at.
4533 */
4534 RTHCPTR HCPtrGuestCR3;
4535 RTHCPHYS HCPhysGuestCR3;
4536 pgmLock(pVM);
4537 PPGMPAGE pPageCR3 = pgmPhysGetPage(pVM, GCPhysCR3);
4538 AssertReturn(pPageCR3, VERR_PGM_INVALID_CR3_ADDR);
4539 HCPhysGuestCR3 = PGM_PAGE_GET_HCPHYS(pPageCR3);
4540 /** @todo this needs some reworking wrt. locking? */
4541# if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
4542 HCPtrGuestCR3 = NIL_RTHCPTR;
4543 int rc = VINF_SUCCESS;
4544# else
4545 int rc = pgmPhysGCPhys2CCPtrInternalDepr(pVM, pPageCR3, GCPhysCR3 & GST_CR3_PAGE_MASK, (void **)&HCPtrGuestCR3); /** @todo r=bird: This GCPhysCR3 masking isn't necessary. */
4546# endif
4547 pgmUnlock(pVM);
4548 if (RT_SUCCESS(rc))
4549 {
4550 rc = PGMMap(pVM, (RTGCPTR)pVM->pgm.s.GCPtrCR3Mapping, HCPhysGuestCR3, PAGE_SIZE, 0);
4551 if (RT_SUCCESS(rc))
4552 {
4553# ifdef IN_RC
4554 PGM_INVL_PG(pVCpu, pVM->pgm.s.GCPtrCR3Mapping);
4555# endif
4556# if PGM_GST_TYPE == PGM_TYPE_32BIT
4557 pVCpu->pgm.s.pGst32BitPdR3 = (R3PTRTYPE(PX86PD))HCPtrGuestCR3;
4558# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4559 pVCpu->pgm.s.pGst32BitPdR0 = (R0PTRTYPE(PX86PD))HCPtrGuestCR3;
4560# endif
4561 pVCpu->pgm.s.pGst32BitPdRC = (RCPTRTYPE(PX86PD))(RTRCUINTPTR)pVM->pgm.s.GCPtrCR3Mapping;
4562
4563# elif PGM_GST_TYPE == PGM_TYPE_PAE
4564 unsigned off = GCPhysCR3 & GST_CR3_PAGE_MASK & PAGE_OFFSET_MASK;
4565 pVCpu->pgm.s.pGstPaePdptR3 = (R3PTRTYPE(PX86PDPT))HCPtrGuestCR3;
4566# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4567 pVCpu->pgm.s.pGstPaePdptR0 = (R0PTRTYPE(PX86PDPT))HCPtrGuestCR3;
4568# endif
4569 pVCpu->pgm.s.pGstPaePdptRC = (RCPTRTYPE(PX86PDPT))((RTRCUINTPTR)pVM->pgm.s.GCPtrCR3Mapping + off);
4570 LogFlow(("Cached mapping %RRv\n", pVCpu->pgm.s.pGstPaePdptRC));
4571
4572 /*
4573 * Map the 4 PDs too.
4574 */
4575 PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pVCpu);
4576 RTGCPTR GCPtr = pVM->pgm.s.GCPtrCR3Mapping + PAGE_SIZE;
4577 for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++, GCPtr += PAGE_SIZE)
4578 {
4579 pVCpu->pgm.s.aGstPaePdpeRegs[i].u = pGuestPDPT->a[i].u;
4580 if (pGuestPDPT->a[i].n.u1Present)
4581 {
4582 RTHCPTR HCPtr;
4583 RTHCPHYS HCPhys;
4584 RTGCPHYS GCPhys = PGM_A20_APPLY(pVCpu, pGuestPDPT->a[i].u & X86_PDPE_PG_MASK);
4585 pgmLock(pVM);
4586 PPGMPAGE pPage = pgmPhysGetPage(pVM, GCPhys);
4587 AssertReturn(pPage, VERR_PGM_INVALID_PDPE_ADDR);
4588 HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
4589# if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
4590 HCPtr = NIL_RTHCPTR;
4591 int rc2 = VINF_SUCCESS;
4592# else
4593 int rc2 = pgmPhysGCPhys2CCPtrInternalDepr(pVM, pPage, GCPhys, (void **)&HCPtr);
4594# endif
4595 pgmUnlock(pVM);
4596 if (RT_SUCCESS(rc2))
4597 {
4598 rc = PGMMap(pVM, GCPtr, HCPhys, PAGE_SIZE, 0);
4599 AssertRCReturn(rc, rc);
4600
4601 pVCpu->pgm.s.apGstPaePDsR3[i] = (R3PTRTYPE(PX86PDPAE))HCPtr;
4602# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4603 pVCpu->pgm.s.apGstPaePDsR0[i] = (R0PTRTYPE(PX86PDPAE))HCPtr;
4604# endif
4605 pVCpu->pgm.s.apGstPaePDsRC[i] = (RCPTRTYPE(PX86PDPAE))(RTRCUINTPTR)GCPtr;
4606 pVCpu->pgm.s.aGCPhysGstPaePDs[i] = GCPhys;
4607# ifdef IN_RC
4608 PGM_INVL_PG(pVCpu, GCPtr);
4609# endif
4610 continue;
4611 }
4612 AssertMsgFailed(("pgmR3Gst32BitMapCR3: rc2=%d GCPhys=%RGp i=%d\n", rc2, GCPhys, i));
4613 }
4614
4615 pVCpu->pgm.s.apGstPaePDsR3[i] = 0;
4616# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4617 pVCpu->pgm.s.apGstPaePDsR0[i] = 0;
4618# endif
4619 pVCpu->pgm.s.apGstPaePDsRC[i] = 0;
4620 pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
4621# ifdef IN_RC
4622 PGM_INVL_PG(pVCpu, GCPtr); /** @todo this shouldn't be necessary? */
4623# endif
4624 }
4625
4626# elif PGM_GST_TYPE == PGM_TYPE_AMD64
4627 pVCpu->pgm.s.pGstAmd64Pml4R3 = (R3PTRTYPE(PX86PML4))HCPtrGuestCR3;
4628# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4629 pVCpu->pgm.s.pGstAmd64Pml4R0 = (R0PTRTYPE(PX86PML4))HCPtrGuestCR3;
4630# endif
4631# endif
4632 }
4633 else
4634 AssertMsgFailed(("rc=%Rrc GCPhysGuestPD=%RGp\n", rc, GCPhysCR3));
4635 }
4636 else
4637 AssertMsgFailed(("rc=%Rrc GCPhysGuestPD=%RGp\n", rc, GCPhysCR3));
4638
4639#else /* prot/real stub */
4640 int rc = VINF_SUCCESS;
4641#endif
4642
4643 /* Update shadow paging info for guest modes with paging (32, pae, 64). */
4644# if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
4645 || PGM_SHW_TYPE == PGM_TYPE_PAE \
4646 || PGM_SHW_TYPE == PGM_TYPE_AMD64) \
4647 && ( PGM_GST_TYPE != PGM_TYPE_REAL \
4648 && PGM_GST_TYPE != PGM_TYPE_PROT))
4649
4650 Assert(!pVM->pgm.s.fNestedPaging);
4651 PGM_A20_ASSERT_MASKED(pVCpu, GCPhysCR3);
4652
4653 /*
4654 * Update the shadow root page as well since that's not fixed.
4655 */
4656 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4657 PPGMPOOLPAGE pOldShwPageCR3 = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
4658 PPGMPOOLPAGE pNewShwPageCR3;
4659
4660 pgmLock(pVM);
4661
4662# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
4663 if (pPool->cDirtyPages)
4664 pgmPoolResetDirtyPages(pVM);
4665# endif
4666
4667 Assert(!(GCPhysCR3 >> (PAGE_SHIFT + 32)));
4668 rc = pgmPoolAlloc(pVM, GCPhysCR3 & GST_CR3_PAGE_MASK, BTH_PGMPOOLKIND_ROOT, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
4669 NIL_PGMPOOL_IDX, UINT32_MAX, true /*fLockPage*/,
4670 &pNewShwPageCR3);
4671 AssertFatalRC(rc);
4672 rc = VINF_SUCCESS;
4673
4674# ifdef IN_RC
4675 /*
4676 * WARNING! We can't deal with jumps to ring 3 in the code below as the
4677 * state will be inconsistent! Flush important things now while
4678 * we still can and then make sure there are no ring-3 calls.
4679 */
4680# ifdef VBOX_WITH_REM
4681 REMNotifyHandlerPhysicalFlushIfAlmostFull(pVM, pVCpu);
4682# endif
4683 VMMRZCallRing3Disable(pVCpu);
4684# endif
4685
4686 pVCpu->pgm.s.CTX_SUFF(pShwPageCR3) = pNewShwPageCR3;
4687# ifdef IN_RING0
4688 pVCpu->pgm.s.pShwPageCR3R3 = MMHyperCCToR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4689 pVCpu->pgm.s.pShwPageCR3RC = MMHyperCCToRC(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4690# elif defined(IN_RC)
4691 pVCpu->pgm.s.pShwPageCR3R3 = MMHyperCCToR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4692 pVCpu->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4693# else
4694 pVCpu->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4695 pVCpu->pgm.s.pShwPageCR3RC = MMHyperCCToRC(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4696# endif
4697
4698# ifndef PGM_WITHOUT_MAPPINGS
4699 /*
4700 * Apply all hypervisor mappings to the new CR3.
4701 * Note that SyncCR3 will be executed in case CR3 is changed in a guest paging mode; this will
4702 * make sure we check for conflicts in the new CR3 root.
4703 */
4704# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
4705 Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL) || VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
4706# endif
4707 rc = pgmMapActivateCR3(pVM, pNewShwPageCR3);
4708 AssertRCReturn(rc, rc);
4709# endif
4710
4711 /* Set the current hypervisor CR3. */
4712 CPUMSetHyperCR3(pVCpu, PGMGetHyperCR3(pVCpu));
4713 SELMShadowCR3Changed(pVM, pVCpu);
4714
4715# ifdef IN_RC
4716 /* NOTE: The state is consistent again. */
4717 VMMRZCallRing3Enable(pVCpu);
4718# endif
4719
4720 /* Clean up the old CR3 root. */
4721 if ( pOldShwPageCR3
4722 && pOldShwPageCR3 != pNewShwPageCR3 /* @todo can happen due to incorrect syncing between REM & PGM; find the real cause */)
4723 {
4724 Assert(pOldShwPageCR3->enmKind != PGMPOOLKIND_FREE);
4725# ifndef PGM_WITHOUT_MAPPINGS
4726 /* Remove the hypervisor mappings from the shadow page table. */
4727 pgmMapDeactivateCR3(pVM, pOldShwPageCR3);
4728# endif
4729 /* Mark the page as unlocked; allow flushing again. */
4730 pgmPoolUnlockPage(pPool, pOldShwPageCR3);
4731
4732 pgmPoolFreeByPage(pPool, pOldShwPageCR3, NIL_PGMPOOL_IDX, UINT32_MAX);
4733 }
4734 pgmUnlock(pVM);
4735# else
4736 NOREF(GCPhysCR3);
4737# endif
4738
4739 return rc;
4740}
4741
4742/**
4743 * Unmaps the shadow CR3.
4744 *
4745 * @returns VBox status, no specials.
4746 * @param pVCpu Pointer to the VMCPU.
4747 */
4748PGM_BTH_DECL(int, UnmapCR3)(PVMCPU pVCpu)
4749{
4750 LogFlow(("UnmapCR3\n"));
4751
4752 int rc = VINF_SUCCESS;
4753 PVM pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
4754
4755 /*
4756 * Update guest paging info.
4757 */
4758#if PGM_GST_TYPE == PGM_TYPE_32BIT
4759 pVCpu->pgm.s.pGst32BitPdR3 = 0;
4760# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4761 pVCpu->pgm.s.pGst32BitPdR0 = 0;
4762# endif
4763 pVCpu->pgm.s.pGst32BitPdRC = 0;
4764
4765#elif PGM_GST_TYPE == PGM_TYPE_PAE
4766 pVCpu->pgm.s.pGstPaePdptR3 = 0;
4767# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4768 pVCpu->pgm.s.pGstPaePdptR0 = 0;
4769# endif
4770 pVCpu->pgm.s.pGstPaePdptRC = 0;
4771 for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
4772 {
4773 pVCpu->pgm.s.apGstPaePDsR3[i] = 0;
4774# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4775 pVCpu->pgm.s.apGstPaePDsR0[i] = 0;
4776# endif
4777 pVCpu->pgm.s.apGstPaePDsRC[i] = 0;
4778 pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
4779 }
4780
4781#elif PGM_GST_TYPE == PGM_TYPE_AMD64
4782 pVCpu->pgm.s.pGstAmd64Pml4R3 = 0;
4783# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4784 pVCpu->pgm.s.pGstAmd64Pml4R0 = 0;
4785# endif
4786
4787#else /* prot/real mode stub */
4788 /* nothing to do */
4789#endif
4790
4791#if !defined(IN_RC) /* In RC we rely on MapCR3 to do the shadow part for us at a safe time */
4792 /*
4793 * Update shadow paging info.
4794 */
4795# if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
4796 || PGM_SHW_TYPE == PGM_TYPE_PAE \
4797 || PGM_SHW_TYPE == PGM_TYPE_AMD64))
4798
4799# if PGM_GST_TYPE != PGM_TYPE_REAL
4800 Assert(!pVM->pgm.s.fNestedPaging);
4801# endif
4802
4803 pgmLock(pVM);
4804
4805# ifndef PGM_WITHOUT_MAPPINGS
4806 if (pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
4807 /* Remove the hypervisor mappings from the shadow page table. */
4808 pgmMapDeactivateCR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4809# endif
4810
4811 if (pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
4812 {
4813 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4814
4815# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
4816 if (pPool->cDirtyPages)
4817 pgmPoolResetDirtyPages(pVM);
4818# endif
4819
4820 /* Mark the page as unlocked; allow flushing again. */
4821 pgmPoolUnlockPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4822
4823 pgmPoolFreeByPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3), NIL_PGMPOOL_IDX, UINT32_MAX);
4824 pVCpu->pgm.s.pShwPageCR3R3 = 0;
4825 pVCpu->pgm.s.pShwPageCR3R0 = 0;
4826 pVCpu->pgm.s.pShwPageCR3RC = 0;
4827 }
4828 pgmUnlock(pVM);
4829# endif
4830#endif /* !IN_RC*/
4831
4832 return rc;
4833}
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