PGMAllBth.h@ 5393

Last change on this file since 5393 was 5006, checked in by vboxsync, 17 years ago

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1	/* $Id: PGMAllBth.h 5006 2007-09-24 14:21:12Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Shadow+Guest Paging Template - All context code.
4	*
5	* This file is a big challenge!
6	*/
7
8	/*
9	* Copyright (C) 2006-2007 innotek GmbH
10	*
11	* This file is part of VirtualBox Open Source Edition (OSE), as
12	* available from http://www.virtualbox.org. This file is free software;
13	* you can redistribute it and/or modify it under the terms of the GNU
14	* General Public License as published by the Free Software Foundation,
15	* in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
16	* distribution. VirtualBox OSE is distributed in the hope that it will
17	* be useful, but WITHOUT ANY WARRANTY of any kind.
18	*/
19
20	/*******************************************************************************
21	* Internal Functions *
22	*******************************************************************************/
23	__BEGIN_DECLS
24	PGM_BTH_DECL(int, Trap0eHandler)(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
25	PGM_BTH_DECL(int, InvalidatePage)(PVM pVM, RTGCUINTPTR GCPtrPage);
26	PGM_BTH_DECL(int, SyncPage)(PVM pVM, VBOXPDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uErr);
27	PGM_BTH_DECL(int, CheckPageFault)(PVM pVM, uint32_t uErr, PSHWPDE pPdeDst, PVBOXPDE pPdeSrc, RTGCUINTPTR GCPtrPage);
28	PGM_BTH_DECL(int, SyncPT)(PVM pVM, unsigned iPD, PVBOXPD pPDSrc, RTGCUINTPTR GCPtrPage);
29	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVM pVM, RTGCUINTPTR Addr, unsigned fPage, unsigned uErr);
30	PGM_BTH_DECL(int, PrefetchPage)(PVM pVM, RTGCUINTPTR GCPtrPage);
31	PGM_BTH_DECL(int, SyncCR3)(PVM pVM, uint32_t cr0, uint32_t cr3, uint32_t cr4, bool fGlobal);
32	#ifdef VBOX_STRICT
33	PGM_BTH_DECL(unsigned, AssertCR3)(PVM pVM, uint32_t cr3, uint32_t cr4, RTGCUINTPTR GCPtr = 0, RTGCUINTPTR cb = ~(RTGCUINTPTR)0);
34	#endif
35	#ifdef PGMPOOL_WITH_USER_TRACKING
36	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVM pVM, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys);
37	#endif
38	__END_DECLS
39
40
41	/**
42	* #PF Handler for raw-mode guest execution.
43	*
44	* @returns VBox status code (appropriate for trap handling and GC return).
45	* @param pVM VM Handle.
46	* @param uErr The trap error code.
47	* @param pRegFrame Trap register frame.
48	* @param pvFault The fault address.
49	*/
50	PGM_BTH_DECL(int, Trap0eHandler)(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
51	{
52	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) && PGM_SHW_TYPE != PGM_TYPE_AMD64
53
54	# if PGM_SHW_TYPE != PGM_TYPE_32BIT && PGM_SHW_TYPE != PGM_TYPE_PAE
55	# error "32-bit guest mode is only implemented for 32-bit and PAE shadow modes."
56	# endif
57
58	# if PGM_SHW_TYPE == PGM_TYPE_PAE
59	/*
60	* Hide the instruction fetch trap indicator for now.
61	*/
62	/** @todo NXE will change this and we must fix NXE in the switcher too! */
63	if (uErr & X86_TRAP_PF_ID)
64	{
65	uErr &= ~X86_TRAP_PF_ID;
66	TRPMSetErrorCode(pVM, uErr);
67	}
68	# endif
69
70	/*
71	* Get PDs.
72	*/
73	int rc;
74	# if PGM_WITH_PAGING(PGM_GST_TYPE)
75	PVBOXPD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
76	const unsigned iPDSrc = (RTGCUINTPTR)pvFault >> GST_PD_SHIFT;
77	# else
78	PVBOXPD pPDSrc = NULL;
79	const unsigned iPDSrc = 0;
80	# endif
81
82	const unsigned iPDDst = (RTGCUINTPTR)pvFault >> SHW_PD_SHIFT;
83	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
84	PX86PD pPDDst = pVM->pgm.s.CTXMID(p,32BitPD);
85	# else /* PAE */
86	PX86PDPAE pPDDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]; /* We treat this as a PD with 2048 entries. */
87	# endif
88
89	# if PGM_WITH_PAGING(PGM_GST_TYPE)
90	/* Determine current privilege level */
91	uint32_t cpl = CPUMGetGuestCPL(pVM, pRegFrame);
92
93	# ifdef PGM_SYNC_DIRTY_BIT
94	/*
95	* If we successfully correct the write protection fault due to dirty bit
96	* tracking, or this page fault is a genuine one, then return immediately.
97	*/
98	STAM_PROFILE_START(&pVM->pgm.s.StatCheckPageFault, e);
99	rc = PGM_BTH_NAME(CheckPageFault)(pVM, uErr, &pPDDst->a[iPDDst], &pPDSrc->a[iPDSrc], (RTGCUINTPTR)pvFault);
100	STAM_PROFILE_STOP(&pVM->pgm.s.StatCheckPageFault, e);
101	if ( rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT
102	\|\| rc == VINF_EM_RAW_GUEST_TRAP)
103	{
104	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution)
105	= rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? &pVM->pgm.s.StatTrap0eDirtyAndAccessedBits : &pVM->pgm.s.StatTrap0eGuestTrap; });
106	LogBird(("Trap0eHandler: returns %s\n", rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? "VINF_SUCCESS" : "VINF_EM_RAW_GUEST_TRAP"));
107	return rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? VINF_SUCCESS : rc;
108	}
109	# endif
110
111	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0ePD[iPDSrc]);
112	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
113
114	/*
115	* A common case is the not-present error caused by lazy page table syncing.
116	*
117	* It is IMPORTANT that we weed out any access to non-present shadow PDEs here
118	* so we can safely assume that the shadow PT is present when calling SyncPage later.
119	*
120	* On failure, we ASSUME that SyncPT is out of memory or detected some kind
121	* of mapping conflict and defer to SyncCR3 in R3.
122	* (Again, we do NOT support access handlers for non-present guest pages.)
123	*
124	*/
125	# if PGM_WITH_PAGING(PGM_GST_TYPE)
126	VBOXPDE PdeSrc = pPDSrc->a[iPDSrc];
127	# else
128	VBOXPDE PdeSrc;
129	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
130	PdeSrc.n.u1Present = 1;
131	PdeSrc.n.u1Write = 1;
132	PdeSrc.n.u1Accessed = 1;
133	PdeSrc.n.u1User = 1;
134	# endif
135	if ( !(uErr & X86_TRAP_PF_P) /* not set means page not present instead of page protection violation */
136	&& !pPDDst->a[iPDDst].n.u1Present
137	&& PdeSrc.n.u1Present
138	)
139
140	{
141	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eSyncPT; });
142	STAM_PROFILE_START(&pVM->pgm.s.StatLazySyncPT, f);
143	LogFlow(("=>SyncPT %04x = %08x\n", iPDSrc, PdeSrc.au32[0]));
144	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, (RTGCUINTPTR)pvFault);
145	if (VBOX_SUCCESS(rc))
146	{
147	STAM_PROFILE_STOP(&pVM->pgm.s.StatLazySyncPT, f);
148	return rc;
149	}
150	Log(("SyncPT: %d failed!! rc=%d\n", iPDSrc, rc));
151	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3); /** @todo no need to do global sync, right? */
152	STAM_PROFILE_STOP(&pVM->pgm.s.StatLazySyncPT, f);
153	return VINF_PGM_SYNC_CR3;
154	}
155
156	# if PGM_WITH_PAGING(PGM_GST_TYPE)
157	/*
158	* Check if this address is within any of our mappings.
159	*
160	* This is very fast and it's gonna save us a bit of effort below and prevent
161	* us from screwing ourself with MMIO2 pages which have a GC Mapping (VRam).
162	* (BTW, it's impossible to have physical access handlers in a mapping.)
163	*/
164	if (pgmMapAreMappingsEnabled(&pVM->pgm.s))
165	{
166	STAM_PROFILE_START(&pVM->pgm.s.StatMapping, a);
167	PPGMMAPPING pMapping = CTXALLSUFF(pVM->pgm.s.pMappings);
168	for ( ; pMapping; pMapping = CTXALLSUFF(pMapping->pNext))
169	{
170	if ((RTGCUINTPTR)pvFault < (RTGCUINTPTR)pMapping->GCPtr)
171	break;
172	if ((RTGCUINTPTR)pvFault - (RTGCUINTPTR)pMapping->GCPtr < pMapping->cb)
173	{
174	/*
175	* The first thing we check is if we've got an undetected conflict.
176	*/
177	if (!pVM->pgm.s.fMappingsFixed)
178	{
179	unsigned iPT = pMapping->cPTs;
180	while (iPT-- > 0)
181	if (pPDSrc->a[iPDSrc + iPT].n.u1Present)
182	{
183	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eConflicts);
184	Log(("Trap0e: Detected Conflict %VGv-%VGv\n", pMapping->GCPtr, pMapping->GCPtrLast));
185	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3); /** @todo no need to do global sync,right? */
186	STAM_PROFILE_STOP(&pVM->pgm.s.StatMapping, a);
187	return VINF_PGM_SYNC_CR3;
188	}
189	}
190
191	/*
192	* Check if the fault address is in a virtual page access handler range.
193	*/
194	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&CTXSUFF(pVM->pgm.s.pTrees)->VirtHandlers, pvFault);
195	if ( pCur
196	&& pCur->enmType != PGMVIRTHANDLERTYPE_EIP
197	&& (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr < pCur->cb
198	&& ( uErr & X86_TRAP_PF_RW
199	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
200	&& pCur->enmType != PGMVIRTHANDLERTYPE_HYPERVISOR) ) ) /** r=bird: <- this is probably wrong. */
201	{
202	# ifdef IN_GC
203	STAM_PROFILE_START(&pCur->Stat, h);
204	rc = CTXSUFF(pCur->pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->GCPtr, (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr);
205	STAM_PROFILE_STOP(&pCur->Stat, h);
206	# else
207	AssertFailed();
208	rc = VINF_EM_RAW_EMULATE_INSTR; /* can't happen with VMX */
209	# endif
210	STAM_COUNTER_INC(&pVM->pgm.s.StatTrap0eMapHandler);
211	STAM_PROFILE_STOP(&pVM->pgm.s.StatMapping, a);
212	return rc;
213	}
214
215	/*
216	* Check if the EIP is in a virtual page access handler range.
217	*/
218	if (cpl == 0)
219	{
220	RTGCPTR pvEIP;
221	rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->eip, &pvEIP);
222	if (VBOX_SUCCESS(rc))
223	{
224	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&CTXSUFF(pVM->pgm.s.pTrees)->VirtHandlers, pvEIP);
225	if ( pCur
226	&& pCur->enmType == PGMVIRTHANDLERTYPE_EIP
227	&& (RTGCUINTPTR)pvEIP - (RTGCUINTPTR)pCur->GCPtr < pCur->cb)
228	{
229	# ifdef IN_GC
230	STAM_PROFILE_START(&pCur->Stat, h);
231	rc = CTXSUFF(pCur->pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->GCPtr, (RTGCUINTPTR)pvEIP - (RTGCUINTPTR)pCur->GCPtr);
232	STAM_PROFILE_STOP(&pCur->Stat, h);
233	# else
234	AssertFailed();
235	rc = VINF_EM_RAW_EMULATE_INSTR; /* can't happen with VMX */
236	# endif
237	STAM_COUNTER_INC(&pVM->pgm.s.StatTrap0eMapHandler);
238	STAM_PROFILE_STOP(&pVM->pgm.s.StatMapping, a);
239	return rc;
240	}
241	}
242	}
243
244	/*
245	* Pretend we're not here and let the guest handle the trap.
246	*/
247	TRPMSetErrorCode(pVM, uErr & ~X86_TRAP_PF_P);
248	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eMap);
249	LogFlow(("PGM: Mapping access -> route trap to recompiler!\n"));
250	STAM_PROFILE_STOP(&pVM->pgm.s.StatMapping, a);
251	return VINF_EM_RAW_GUEST_TRAP;
252	}
253	}
254	STAM_PROFILE_STOP(&pVM->pgm.s.StatMapping, a);
255	} /* pgmAreMappingsEnabled(&pVM->pgm.s) */
256	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
257
258	/*
259	* Check if this fault address is flagged for special treatment,
260	* which means we'll have to figure out the physical address and
261	* check flags associated with it.
262	*
263	* ASSUME that we can limit any special access handling to pages
264	* in page tables which the guest believes to be present.
265	*/
266	if (PdeSrc.n.u1Present)
267	{
268	RTGCPHYS GCPhys = ~0U;
269
270	# if PGM_WITH_PAGING(PGM_GST_TYPE)
271	uint32_t cr4 = CPUMGetGuestCR4(pVM);
272	if ( PdeSrc.b.u1Size
273	&& (cr4 & X86_CR4_PSE))
274	GCPhys = (PdeSrc.u & X86_PDE4M_PG_MASK)
275	\| ((RTGCPHYS)pvFault & (PAGE_OFFSET_MASK_BIG ^ PAGE_OFFSET_MASK));
276	else
277	{
278	PVBOXPT pPTSrc;
279	# ifdef IN_GC
280	rc = PGMGCDynMapGCPage(pVM, PdeSrc.u & X86_PDE_PG_MASK, (void **)&pPTSrc);
281	# else
282	pPTSrc = (PVBOXPT)MMPhysGCPhys2HCVirt(pVM, PdeSrc.u & X86_PDE_PG_MASK, sizeof(*pPTSrc));
283	if (pPTSrc == 0)
284	rc = VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
285	# endif
286	if (VBOX_SUCCESS(rc))
287	{
288	unsigned iPTESrc = ((RTGCUINTPTR)pvFault >> PAGE_SHIFT) & PTE_MASK;
289	if (pPTSrc->a[iPTESrc].n.u1Present)
290	GCPhys = pPTSrc->a[iPTESrc].u & X86_PTE_PG_MASK;
291	}
292	}
293	# else
294	/* No paging so the fault address is the physical address */
295	GCPhys = (RTGCPHYS)((RTGCUINTPTR)pvFault & ~PAGE_OFFSET_MASK);
296	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
297
298	/*
299	* If we have a GC address we'll check if it has any flags set.
300	*/
301	if (GCPhys != ~0U)
302	{
303	STAM_PROFILE_START(&pVM->pgm.s.StatHandlers, b);
304
305	PPGMPAGE pPage;
306	rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
307	if (VBOX_SUCCESS(rc))
308	{
309	if (pPage->HCPhys & (MM_RAM_FLAGS_PHYSICAL_HANDLER \| MM_RAM_FLAGS_VIRTUAL_HANDLER)) /** @todo PAGE FLAGS */
310	{
311	if (pPage->HCPhys & MM_RAM_FLAGS_PHYSICAL_HANDLER) /** @todo PAGE FLAGS */
312	{
313	/*
314	* Physical page access handler.
315	*/
316	const RTGCPHYS GCPhysFault = GCPhys \| ((RTGCUINTPTR)pvFault & PAGE_OFFSET_MASK);
317	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)RTAvlroGCPhysRangeGet(&CTXSUFF(pVM->pgm.s.pTrees)->PhysHandlers, GCPhysFault);
318	if (pCur)
319	{
320	# ifdef PGM_SYNC_N_PAGES
321	/*
322	* If the region is write protected and we got a page not present fault, then sync
323	* the pages. If the fault was caused by a read, then restart the instruction.
324	* In case of write access continue to the GC write handler.
325	*
326	* ASSUMES that there is only one handler per page or that they have similar write properties.
327	*/
328	if ( pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
329	&& !(uErr & X86_TRAP_PF_P))
330	{
331	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, PGM_SYNC_NR_PAGES, uErr);
332	if ( VBOX_FAILURE(rc)
333	\|\| !(uErr & X86_TRAP_PF_RW)
334	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
335	{
336	AssertRC(rc);
337	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersOutOfSync);
338	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
339	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSyncHndPhys; });
340	return rc;
341	}
342	}
343	# endif
344
345	AssertMsg( pCur->enmType != PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
346	\|\| (pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE && (uErr & X86_TRAP_PF_RW)),
347	("Unexpected trap for physical handler: %08X (phys=%08x) HCPhys=%X uErr=%X, enum=%d\n", pvFault, GCPhys, pPage->HCPhys, uErr, pCur->enmType));
348
349	#if defined(IN_GC) \|\| defined(IN_RING0)
350	if (CTXALLSUFF(pCur->pfnHandler))
351	{
352	STAM_PROFILE_START(&pCur->Stat, h);
353	rc = pCur->CTXALLSUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, GCPhysFault, CTXALLSUFF(pCur->pvUser));
354	STAM_PROFILE_STOP(&pCur->Stat, h);
355	}
356	else
357	#endif
358	rc = VINF_EM_RAW_EMULATE_INSTR;
359	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersPhysical);
360	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
361	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndPhys; });
362	return rc;
363	}
364	}
365	# if PGM_WITH_PAGING(PGM_GST_TYPE)
366	else
367	{
368	# ifdef PGM_SYNC_N_PAGES
369	/*
370	* If the region is write protected and we got a page not present fault, then sync
371	* the pages. If the fault was caused by a read, then restart the instruction.
372	* In case of write access continue to the GC write handler.
373	*/
374	if ( (pPage->HCPhys & (MM_RAM_FLAGS_VIRTUAL_WRITE \| MM_RAM_FLAGS_VIRTUAL_ALL)) == MM_RAM_FLAGS_VIRTUAL_WRITE /** @todo PAGE FLAGS */
375	&& !(uErr & X86_TRAP_PF_P))
376	{
377	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, PGM_SYNC_NR_PAGES, uErr);
378	if ( VBOX_FAILURE(rc)
379	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
380	\|\| !(uErr & X86_TRAP_PF_RW))
381	{
382	AssertRC(rc);
383	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersOutOfSync);
384	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
385	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSyncHndVirt; });
386	return rc;
387	}
388	}
389	# endif
390	/*
391	* Ok, it's an virtual page access handler.
392	*
393	* Since it's faster to search by address, we'll do that first
394	* and then retry by GCPhys if that fails.
395	*/
396	/** @todo r=bird: perhaps we should consider looking up by physical address directly now? */
397	/** @note r=svl: true, but lookup on virtual address should remain as a fallback as phys & virt trees might be out of sync, because the
398	* page was changed without us noticing it (not-present -> present without invlpg or mov cr3, xxx)
399	*/
400	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&CTXSUFF(pVM->pgm.s.pTrees)->VirtHandlers, pvFault);
401	if (pCur)
402	{
403	AssertMsg(!((RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr < pCur->cb)
404	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
405	\|\| !(uErr & X86_TRAP_PF_P)
406	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
407	("Unexpected trap for virtual handler: %VGv (phys=%VGp) HCPhys=%HGp uErr=%X, enum=%d\n", pvFault, GCPhys, pPage->HCPhys, uErr, pCur->enmType));
408
409	if ( pCur->enmType != PGMVIRTHANDLERTYPE_EIP
410	&& (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr < pCur->cb
411	&& ( uErr & X86_TRAP_PF_RW
412	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
413	&& pCur->enmType != PGMVIRTHANDLERTYPE_HYPERVISOR) ) ) /** @todo r=bird: _HYPERVISOR is impossible here because of mapping check. */
414	{
415	# ifdef IN_GC
416	STAM_PROFILE_START(&pCur->Stat, h);
417	rc = CTXSUFF(pCur->pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->GCPtr, (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr);
418	STAM_PROFILE_STOP(&pCur->Stat, h);
419	# else
420	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
421	# endif
422	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersVirtual);
423	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
424	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndVirt; });
425	return rc;
426	}
427	/* Unhandled part of a monitored page */
428	}
429	else
430	{
431	/* Check by physical address. */
432	PPGMVIRTHANDLER pCur;
433	unsigned iPage;
434	rc = pgmHandlerVirtualFindByPhysAddr(pVM, GCPhys + ((RTGCUINTPTR)pvFault & PAGE_OFFSET_MASK),
435	&pCur, &iPage);
436	Assert(VBOX_SUCCESS(rc) \|\| !pCur);
437	if ( pCur
438	&& pCur->enmType != PGMVIRTHANDLERTYPE_EIP
439	&& ( uErr & X86_TRAP_PF_RW
440	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
441	&& pCur->enmType != PGMVIRTHANDLERTYPE_HYPERVISOR) ) )
442	{
443	Assert((pCur->aPhysToVirt[iPage].Core.Key & X86_PTE_PAE_PG_MASK) == GCPhys);
444	# ifdef IN_GC
445	RTGCUINTPTR off = (iPage << PAGE_SHIFT) + ((RTGCUINTPTR)pvFault & PAGE_OFFSET_MASK) - ((RTGCUINTPTR)pCur->GCPtr & PAGE_OFFSET_MASK);
446	Assert(off < pCur->cb);
447	STAM_PROFILE_START(&pCur->Stat, h);
448	rc = CTXSUFF(pCur->pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->GCPtr, off);
449	STAM_PROFILE_STOP(&pCur->Stat, h);
450	# else
451	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
452	# endif
453	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersVirtualByPhys);
454	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
455	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndVirt; });
456	return rc;
457	}
458	}
459	}
460	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
461
462	/*
463	* There is a handled area of the page, but this fault doesn't belong to it.
464	* We must emulate the instruction.
465	*
466	* To avoid crashing (non-fatal) in the interpreter and go back to the recompiler
467	* we first check if this was a page-not-present fault for a page with only
468	* write access handlers. Restart the instruction if it wasn't a write access.
469	*/
470	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersUnhandled);
471
472	if ( !(pPage->HCPhys & (MM_RAM_FLAGS_PHYSICAL_ALL \| MM_RAM_FLAGS_VIRTUAL_ALL)) /** @todo PAGE FLAGS */
473	&& !(uErr & X86_TRAP_PF_P))
474	{
475	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, PGM_SYNC_NR_PAGES, uErr);
476	if ( VBOX_FAILURE(rc)
477	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
478	\|\| !(uErr & X86_TRAP_PF_RW))
479	{
480	AssertRC(rc);
481	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersOutOfSync);
482	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
483	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSyncHndPhys; });
484	return rc;
485	}
486	}
487
488	/** @todo This particular case can cause quite a lot of overhead. E.g. early stage of kernel booting in Ubuntu 6.06
489	* It's writing to an unhandled part of the LDT page several million times.
490	*/
491	rc = PGMInterpretInstruction(pVM, pRegFrame, pvFault);
492	LogFlow(("PGM: PGMInterpretInstruction -> rc=%d HCPhys=%VHp%s%s\n",
493	rc, pPage->HCPhys, pPage->HCPhys & MM_RAM_FLAGS_PHYSICAL_HANDLER ? " phys" : "",
494	pPage->HCPhys & MM_RAM_FLAGS_VIRTUAL_HANDLER ? " virt" : ""));
495	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
496	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndUnhandled; });
497	return rc;
498	} /* if any kind of handler */
499
500	# if PGM_WITH_PAGING(PGM_GST_TYPE)
501	if (uErr & X86_TRAP_PF_P)
502	{
503	/*
504	* The page isn't marked, but it might still be monitored by a virtual page access handler.
505	* (ASSUMES no temporary disabling of virtual handlers.)
506	*/
507	/** @todo r=bird: Since the purpose is to catch out of sync pages with virtual handler(s) here,
508	* we should correct both the shadow page table and physical memory flags, and not only check for
509	* accesses within the handler region but for access to pages with virtual handlers. */
510	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&CTXSUFF(pVM->pgm.s.pTrees)->VirtHandlers, pvFault);
511	if (pCur)
512	{
513	AssertMsg( !((RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr < pCur->cb)
514	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
515	\|\| !(uErr & X86_TRAP_PF_P)
516	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
517	("Unexpected trap for virtual handler: %08X (phys=%08x) HCPhys=%X uErr=%X, enum=%d\n", pvFault, GCPhys, pPage->HCPhys, uErr, pCur->enmType));
518
519	if ( pCur->enmType != PGMVIRTHANDLERTYPE_EIP
520	&& (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr < pCur->cb
521	&& ( uErr & X86_TRAP_PF_RW
522	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
523	&& pCur->enmType != PGMVIRTHANDLERTYPE_HYPERVISOR) ) ) /** @todo r=bird: _HYPERVISOR is impossible here because of mapping check. */
524	{
525	# ifdef IN_GC
526	STAM_PROFILE_START(&pCur->Stat, h);
527	rc = CTXSUFF(pCur->pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->GCPtr, (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr);
528	STAM_PROFILE_STOP(&pCur->Stat, h);
529	# else
530	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
531	# endif
532	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersVirtualUnmarked);
533	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
534	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndVirt; });
535	return rc;
536	}
537	}
538	}
539	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
540	}
541	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
542
543	# ifdef PGM_OUT_OF_SYNC_IN_GC
544	/*
545	* We are here only if page is present in Guest page tables and trap is not handled
546	* by our handlers.
547	* Check it for page out-of-sync situation.
548	*/
549	STAM_PROFILE_START(&pVM->pgm.s.StatOutOfSync, c);
550
551	if (!(uErr & X86_TRAP_PF_P))
552	{
553	/*
554	* Page is not present in our page tables.
555	* Try to sync it!
556	* BTW, fPageShw is invalid in this branch!
557	*/
558	if (uErr & X86_TRAP_PF_US)
559	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncUser);
560	else /* supervisor */
561	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncSupervisor);
562
563	# if defined(LOG_ENABLED) && !defined(IN_RING0)
564	RTGCPHYS GCPhys;
565	uint64_t fPageGst;
566	PGMGstGetPage(pVM, pvFault, &fPageGst, &GCPhys);
567	Log(("Page out of sync: %p eip=%08x PdeSrc.n.u1User=%d fPageGst=%08llx GCPhys=%VGp scan=%d\n",
568	pvFault, pRegFrame->eip, PdeSrc.n.u1User, fPageGst, GCPhys, CSAMDoesPageNeedScanning(pVM, (RTGCPTR)pRegFrame->eip)));
569	# endif /* LOG_ENABLED */
570
571	# if PGM_WITH_PAGING(PGM_GST_TYPE) && !defined(IN_RING0)
572	if (cpl == 0)
573	{
574	uint64_t fPageGst;
575	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, NULL);
576	if ( VBOX_SUCCESS(rc)
577	&& !(fPageGst & X86_PTE_US))
578	{
579	/* Note: can't check for X86_TRAP_ID bit, because that requires execute disable support on the CPU */
580	if ( pvFault == (RTGCPTR)pRegFrame->eip
581	\|\| (RTGCUINTPTR)pvFault - pRegFrame->eip < 8 /* instruction crossing a page boundary */
582	# ifdef CSAM_DETECT_NEW_CODE_PAGES
583	\|\| ( !PATMIsPatchGCAddr(pVM, (RTGCPTR)pRegFrame->eip)
584	&& CSAMDoesPageNeedScanning(pVM, (RTGCPTR)pRegFrame->eip)) /* any new code we encounter here */
585	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
586	)
587	{
588	LogFlow(("CSAMExecFault %VGv\n", pRegFrame->eip));
589	rc = CSAMExecFault(pVM, (RTGCPTR)pRegFrame->eip);
590	if (rc != VINF_SUCCESS)
591	{
592	/*
593	* CSAM needs to perform a job in ring 3.
594	*
595	* Sync the page before going to the host context; otherwise we'll end up in a loop if
596	* CSAM fails (e.g. instruction crosses a page boundary and the next page is not present)
597	*/
598	LogFlow(("CSAM ring 3 job\n"));
599	int rc2 = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, 1, uErr);
600	AssertRC(rc2);
601
602	STAM_PROFILE_STOP(&pVM->pgm.s.StatOutOfSync, c);
603	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eCSAM; });
604	return rc;
605	}
606	}
607	# ifdef CSAM_DETECT_NEW_CODE_PAGES
608	else
609	if ( uErr == X86_TRAP_PF_RW
610	&& pRegFrame->ecx >= 0x100 /* early check for movswd count */
611	&& pRegFrame->ecx < 0x10000
612	)
613	{
614	/* In case of a write to a non-present supervisor shadow page, we'll take special precautions
615	* to detect loading of new code pages.
616	*/
617
618	/*
619	* Decode the instruction.
620	*/
621	RTGCPTR PC;
622	rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->eip, &PC);
623	if (rc == VINF_SUCCESS)
624	{
625	DISCPUSTATE Cpu;
626	uint32_t cbOp;
627	rc = EMInterpretDisasOneEx(pVM, (RTGCUINTPTR)PC, pRegFrame, &Cpu, &cbOp);
628
629	/* For now we'll restrict this to rep movsw/d instructions */
630	if ( rc == VINF_SUCCESS
631	&& Cpu.pCurInstr->opcode == OP_MOVSWD
632	&& (Cpu.prefix & PREFIX_REP))
633	{
634	CSAMMarkPossibleCodePage(pVM, pvFault);
635	}
636	}
637	}
638	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
639
640	/*
641	* Mark this page as safe.
642	*/
643	/** @todo not correct for pages that contain both code and data!! */
644	Log2(("CSAMMarkPage %p; scanned=%d\n", pvFault, true));
645	CSAMMarkPage(pVM, pvFault, true);
646	}
647	}
648	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
649	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, PGM_SYNC_NR_PAGES, uErr);
650	if (VBOX_SUCCESS(rc))
651	{
652	/* The page was successfully synced, return to the guest. */
653	STAM_PROFILE_STOP(&pVM->pgm.s.StatOutOfSync, c);
654	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSync; });
655	return VINF_SUCCESS;
656	}
657	}
658	else
659	{
660	/*
661	* A side effect of not flushing global PDEs are out of sync pages due
662	* to physical monitored regions, that are no longer valid.
663	* Assume for now it only applies to the read/write flag
664	*/
665	if (VBOX_SUCCESS(rc) && (uErr & X86_TRAP_PF_RW))
666	{
667	if (uErr & X86_TRAP_PF_US)
668	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncUser);
669	else /* supervisor */
670	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncSupervisor);
671
672
673	/*
674	* Note: Do NOT use PGM_SYNC_NR_PAGES here. That only works if the page is not present, which is not true in this case.
675	*/
676	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, 1, uErr);
677	if (VBOX_SUCCESS(rc))
678	{
679	/*
680	* Page was successfully synced, return to guest.
681	*/
682	# ifdef VBOX_STRICT
683	RTGCPHYS GCPhys;
684	uint64_t fPageGst;
685	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, &GCPhys);
686	Assert(VBOX_SUCCESS(rc) && fPageGst & X86_PTE_RW);
687	LogFlow(("Obsolete physical monitor page out of sync %VGv - phys %VGp flags=%08llx\n", pvFault, GCPhys, (uint64_t)fPageGst));
688
689	uint64_t fPageShw;
690	rc = PGMShwGetPage(pVM, pvFault, &fPageShw, NULL);
691	Assert(VBOX_SUCCESS(rc) && fPageShw & X86_PTE_RW);
692	# endif /* VBOX_STRICT */
693	STAM_PROFILE_STOP(&pVM->pgm.s.StatOutOfSync, c);
694	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSyncObsHnd; });
695	return VINF_SUCCESS;
696	}
697	}
698
699	# if PGM_WITH_PAGING(PGM_GST_TYPE)
700	# ifdef VBOX_STRICT
701	/*
702	* Check for VMM page flags vs. Guest page flags consistency.
703	* Currently only for debug purposes.
704	*/
705	if (VBOX_SUCCESS(rc))
706	{
707	/* Get guest page flags. */
708	uint64_t fPageGst;
709	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, NULL);
710	if (VBOX_SUCCESS(rc))
711	{
712	uint64_t fPageShw;
713	rc = PGMShwGetPage(pVM, pvFault, &fPageShw, NULL);
714
715	/*
716	* Compare page flags.
717	* Note: we have AVL, A, D bits desynched.
718	*/
719	AssertMsg((fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)) == (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)),
720	("Page flags mismatch! pvFault=%p GCPhys=%VGp fPageShw=%08llx fPageGst=%08llx\n", pvFault, GCPhys, fPageShw, fPageGst));
721	}
722	else
723	AssertMsgFailed(("PGMGstGetPage rc=%Vrc\n", rc));
724	}
725	else
726	AssertMsgFailed(("PGMGCGetPage rc=%Vrc\n", rc));
727	# endif /* VBOX_STRICT */
728	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
729	}
730	STAM_PROFILE_STOP(&pVM->pgm.s.StatOutOfSync, c);
731	# endif /* PGM_OUT_OF_SYNC_IN_GC */
732	}
733	else
734	{
735	/*
736	* Page not present in Guest OS or invalid page table address.
737	* This is potential virtual page access handler food.
738	*
739	* For the present we'll say that our access handlers don't
740	* work for this case - we've already discarded the page table
741	* not present case which is identical to this.
742	*
743	* When we perchance find we need this, we will probably have AVL
744	* trees (offset based) to operate on and we can measure their speed
745	* agains mapping a page table and probably rearrange this handling
746	* a bit. (Like, searching virtual ranges before checking the
747	* physical address.)
748	*/
749	}
750	}
751
752
753	# if PGM_WITH_PAGING(PGM_GST_TYPE)
754	/*
755	* Check if it's in a EIP based virtual page access handler range.
756	* This is only used for supervisor pages in flat mode.
757	*/
758	/** @todo this stuff is completely broken by the out-of-sync stuff. since we don't use this stuff, that's not really a problem yet. */
759	STAM_PROFILE_START(&pVM->pgm.s.StatEIPHandlers, d);
760	if (cpl == 0)
761	{
762	RTGCPTR pvEIP;
763	rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->eip, &pvEIP);
764	if ( VBOX_SUCCESS(rc)
765	&& pvEIP == (RTGCPTR)pRegFrame->eip)
766	{
767	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&CTXSUFF(pVM->pgm.s.pTrees)->VirtHandlers, pvEIP);
768	if ( pCur
769	&& pCur->enmType == PGMVIRTHANDLERTYPE_EIP
770	&& (RTGCUINTPTR)pvEIP - (RTGCUINTPTR)pCur->GCPtr < pCur->cb)
771	{
772	LogFlow(("EIP handler\n"));
773	# ifdef IN_GC
774	STAM_PROFILE_START(&pCur->Stat, h);
775	rc = CTXSUFF(pCur->pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->GCPtr, (RTGCUINTPTR)pvEIP - (RTGCUINTPTR)pCur->GCPtr);
776	STAM_PROFILE_STOP(&pCur->Stat, h);
777	# else
778	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
779	# endif
780	STAM_PROFILE_STOP(&pVM->pgm.s.StatEIPHandlers, d);
781	return rc;
782	}
783	}
784	}
785	STAM_PROFILE_STOP(&pVM->pgm.s.StatEIPHandlers, d);
786
787	/*
788	* Conclusion, this is a guest trap.
789	*/
790	LogFlow(("PGM: Unhandled #PF -> route trap to recompiler!\n"));
791	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eUnhandled);
792	return VINF_EM_RAW_GUEST_TRAP;
793	# else
794	/* present, but not a monitored page; perhaps the guest is probing physical memory */
795	return VINF_EM_RAW_EMULATE_INSTR;
796	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
797
798
799	#else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
800
801	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
802	return VERR_INTERNAL_ERROR;
803	#endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
804	}
805
806
807	/**
808	* Emulation of the invlpg instruction.
809	*
810	*
811	* @returns VBox status code.
812	*
813	* @param pVM VM handle.
814	* @param GCPtrPage Page to invalidate.
815	*
816	* @remark ASSUMES that the guest is updating before invalidating. This order
817	* isn't required by the CPU, so this is speculative and could cause
818	* trouble.
819	*
820	* @todo Flush page or page directory only if necessary!
821	* @todo Add a #define for simply invalidating the page.
822	*/
823	PGM_BTH_DECL(int, InvalidatePage)(PVM pVM, RTGCUINTPTR GCPtrPage)
824	{
825	#if PGM_GST_TYPE == PGM_TYPE_32BIT
826
827	LogFlow(("InvalidatePage %x\n", GCPtrPage));
828	# if PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE
829	/*
830	* Get the shadow PD entry and skip out if this PD isn't present.
831	* (Guessing that it is frequent for a shadow PDE to not be present, do this first.)
832	*/
833	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
834	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
835	PX86PDE pPdeDst = &pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst];
836	# else
837	PX86PDEPAE pPdeDst = &pVM->pgm.s.CTXMID(ap,PaePDs[0])->a[iPDDst];
838	# endif
839	const SHWPDE PdeDst = *pPdeDst;
840	if (!PdeDst.n.u1Present)
841	{
842	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePageSkipped));
843	return VINF_SUCCESS;
844	}
845
846	/*
847	* Get the guest PD entry and calc big page.
848	*/
849	PVBOXPD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
850	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
851	VBOXPDE PdeSrc = pPDSrc->a[iPDSrc];
852	const uint32_t cr4 = CPUMGetGuestCR4(pVM);
853	const bool fIsBigPage = PdeSrc.b.u1Size && (cr4 & X86_CR4_PSE);
854
855	# ifdef IN_RING3
856	/*
857	* If a CR3 Sync is pending we may ignore the invalidate page operation
858	* depending on the kind of sync and if it's a global page or not.
859	* This doesn't make sense in GC/R0 so we'll skip it entirely there.
860	*/
861	# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
862	if ( VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3)
863	\|\| ( VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
864	&& fIsBigPage
865	&& PdeSrc.b.u1Global
866	&& (cr4 & X86_CR4_PGE)
867	)
868	)
869	# else
870	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL) )
871	# endif
872	{
873	STAM_COUNTER_INC(&pVM->pgm.s.StatHCInvalidatePageSkipped);
874	return VINF_SUCCESS;
875	}
876	# endif /* IN_RING3 */
877
878
879	/*
880	* Deal with the Guest PDE.
881	*/
882	int rc = VINF_SUCCESS;
883	if (PdeSrc.n.u1Present)
884	{
885	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
886	{
887	/*
888	* Conflict - Let SyncPT deal with it to avoid duplicate code.
889	*/
890	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
891	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, GCPtrPage);
892	}
893	else if ( PdeSrc.n.u1User != PdeDst.n.u1User
894	\|\| (!PdeSrc.n.u1Write && PdeDst.n.u1Write))
895	{
896	/*
897	* Mark not present so we can resync the PDE when it's used.
898	*/
899	LogFlow(("InvalidatePage: Out-of-sync at %VGp PdeSrc=%RX64 PdeDst=%RX64\n",
900	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
901	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
902	pPdeDst->u = 0;
903	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDOutOfSync));
904	PGM_INVL_GUEST_TLBS();
905	}
906	# ifdef PGM_SYNC_ACCESSED_BIT
907	else if (!PdeSrc.n.u1Accessed)
908	{
909	/*
910	* Mark not present so we can set the accessed bit.
911	*/
912	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
913	pPdeDst->u = 0;
914	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDNAs));
915	PGM_INVL_GUEST_TLBS();
916	}
917	# endif
918	else if (!fIsBigPage)
919	{
920	/*
921	* 4KB - page.
922	*/
923	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
924	RTGCPHYS GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
925	# if PGM_SHW_TYPE != PGM_TYPE_32BIT
926	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE/2);
927	# endif
928	if (pShwPage->GCPhys == GCPhys)
929	{
930	#if 0 /* likely cause of a major performance regression; must be SyncPageWorkerTrackDeref then */
931	const unsigned iPTEDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
932	PSHWPT pPT = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
933	if (pPT->a[iPTEDst].n.u1Present)
934	{
935	# ifdef PGMPOOL_WITH_USER_TRACKING
936	/* This is very unlikely with caching/monitoring enabled. */
937	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPT->a[iPTEDst].u & SHW_PTE_PG_MASK);
938	# endif
939	pPT->a[iPTEDst].u = 0;
940	}
941	#else /* Syncing it here isn't 100% safe and it's probably not worth spending time syncing it. */
942	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, 1, 0);
943	if (VBOX_SUCCESS(rc))
944	rc = VINF_SUCCESS;
945	#endif
946	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePage4KBPages));
947	PGM_INVL_PG(GCPtrPage);
948	}
949	else
950	{
951	/*
952	* The page table address changed.
953	*/
954	LogFlow(("InvalidatePage: Out-of-sync at %VGp PdeSrc=%RX64 PdeDst=%RX64 ShwGCPhys=%VGp iPDDst=%#x\n",
955	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, iPDDst));
956	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
957	pPdeDst->u = 0;
958	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDOutOfSync));
959	PGM_INVL_GUEST_TLBS();
960	}
961	}
962	else
963	{
964	/*
965	* 4MB - page.
966	*/
967	/* Before freeing the page, check if anything really changed. */
968	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
969	RTGCPHYS GCPhys = PdeSrc.u & X86_PDE4M_PG_MASK;
970	# if PGM_SHW_TYPE != PGM_TYPE_32BIT
971	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
972	# endif
973	if ( pShwPage->GCPhys == GCPhys
974	&& pShwPage->enmKind == BTH_PGMPOOLKIND_PT_FOR_BIG)
975	{
976	/* ASSUMES a the given bits are identical for 4M and normal PDEs */
977	/** @todo PAT */
978	# ifdef PGM_SYNC_DIRTY_BIT
979	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD))
980	== (PdeDst.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD))
981	&& ( PdeSrc.b.u1Dirty /** @todo rainy day: What about read-only 4M pages? not very common, but still... */
982	\|\| (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)))
983	# else
984	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD))
985	== (PdeDst.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD)))
986	# endif
987	{
988	LogFlow(("Skipping flush for big page containing %VGv (PD=%X)-> nothing has changed!\n", GCPtrPage, iPDSrc));
989	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePage4MBPagesSkip));
990	return VINF_SUCCESS;
991	}
992	}
993
994	/*
995	* Ok, the page table is present and it's been changed in the guest.
996	* If we're in host context, we'll just mark it as not present taking the lazy approach.
997	* We could do this for some flushes in GC too, but we need an algorithm for
998	* deciding which 4MB pages containing code likely to be executed very soon.
999	*/
1000	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1001	pPdeDst->u = 0;
1002	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePage4MBPages));
1003	DUMP_PDE_BIG("PGMInvalidatePage", iPDSrc, PdeSrc);
1004	PGM_INVL_BIG_PG(GCPtrPage);
1005	}
1006	}
1007	else
1008	{
1009	/*
1010	* Page directory is not present, mark shadow PDE not present.
1011	*/
1012	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
1013	{
1014	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1015	pPdeDst->u = 0;
1016	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDNPs));
1017	PGM_INVL_PG(GCPtrPage);
1018	}
1019	else
1020	{
1021	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1022	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDMappings));
1023	}
1024	}
1025
1026	return rc;
1027
1028	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1029	# error "Guest 32-bit mode and shadow AMD64 mode doesn't add up!"
1030	# endif
1031	return VINF_SUCCESS;
1032
1033	#elif PGM_GST_TYPE == PGM_TYPE_PAE
1034	# if PGM_SHW_TYPE == PGM_TYPE_PAE
1035	//# error not implemented
1036	return VERR_INTERNAL_ERROR;
1037
1038	# else /* PGM_SHW_TYPE != PGM_TYPE_AMD64 */
1039	# error "Guest PAE mode, but not the shadow mode ; 32bit - maybe, but amd64 no."
1040	# endif /* PGM_SHW_TYPE != PGM_TYPE_AMD64 */
1041
1042	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
1043	# if PGM_SHW_TYPE == PGM_TYPE_AMD64
1044	//# error not implemented
1045	return VERR_INTERNAL_ERROR;
1046
1047	# else /* PGM_SHW_TYPE != PGM_TYPE_AMD64 */
1048	# error "Guest AMD64 mode, but not the shadow mode - that can't be right!"
1049	# endif /* PGM_SHW_TYPE != PGM_TYPE_AMD64 */
1050
1051	#else /* guest real and protected mode */
1052	/* There's no such thing when paging is disabled. */
1053	return VINF_SUCCESS;
1054	#endif
1055	}
1056
1057
1058	#ifdef PGMPOOL_WITH_USER_TRACKING
1059	/**
1060	* Update the tracking of shadowed pages.
1061	*
1062	* @param pVM The VM handle.
1063	* @param pShwPage The shadow page.
1064	* @param HCPhys The physical page we is being dereferenced.
1065	*/
1066	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVM pVM, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys)
1067	{
1068	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1069	STAM_PROFILE_START(&pVM->pgm.s.StatTrackDeref, a);
1070	LogFlow(("SyncPageWorkerTrackDeref: Damn HCPhys=%VHp pShwPage->idx=%#x!!!\n", HCPhys, pShwPage->idx));
1071
1072	/** @todo If this turns out to be a bottle neck (very likely) two things can be done:
1073	* 1. have a medium sized HCPhys -> GCPhys TLB (hash?)
1074	* 2. write protect all shadowed pages. I.e. implement caching.
1075	*/
1076	/*
1077	* Find the guest address.
1078	*/
1079	for (PPGMRAMRANGE pRam = pVM->pgm.s.CTXSUFF(pRamRanges);
1080	pRam;
1081	pRam = pRam->CTXSUFF(pNext))
1082	{
1083	unsigned iPage = pRam->cb >> PAGE_SHIFT;
1084	while (iPage-- > 0)
1085	{
1086	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
1087	{
1088	PPGMPOOL pPool = pVM->pgm.s.CTXSUFF(pPool);
1089	pgmTrackDerefGCPhys(pPool, pShwPage, &pRam->aPages[iPage]);
1090	pShwPage->cPresent--;
1091	pPool->cPresent--;
1092	STAM_PROFILE_STOP(&pVM->pgm.s.StatTrackDeref, a);
1093	return;
1094	}
1095	}
1096	}
1097
1098	for (;;)
1099	AssertReleaseMsgFailed(("HCPhys=%VHp wasn't found!\n", HCPhys));
1100	# else /* !PGMPOOL_WITH_GCPHYS_TRACKING */
1101	pShwPage->cPresent--;
1102	pVM->pgm.s.CTXSUFF(pPool)->cPresent--;
1103	# endif /* !PGMPOOL_WITH_GCPHYS_TRACKING */
1104	}
1105
1106
1107	/**
1108	* Update the tracking of shadowed pages.
1109	*
1110	* @param pVM The VM handle.
1111	* @param pShwPage The shadow page.
1112	* @param u16 The top 16-bit of the pPage->HCPhys.
1113	* @param pPage Pointer to the guest page. this will be modified.
1114	* @param iPTDst The index into the shadow table.
1115	*/
1116	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackAddref)(PVM pVM, PPGMPOOLPAGE pShwPage, uint16_t u16, PPGMPAGE pPage, const unsigned iPTDst)
1117	{
1118	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1119	/*
1120	* We're making certain assumptions about the placement of cRef and idx.
1121	*/
1122	Assert(MM_RAM_FLAGS_IDX_SHIFT == 48);
1123	Assert(MM_RAM_FLAGS_CREFS_SHIFT > MM_RAM_FLAGS_IDX_SHIFT);
1124
1125	/*
1126	* Just deal with the simple first time here.
1127	*/
1128	if (!u16)
1129	{
1130	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackVirgin);
1131	u16 = (1 << (MM_RAM_FLAGS_CREFS_SHIFT - MM_RAM_FLAGS_IDX_SHIFT)) \| pShwPage->idx;
1132	}
1133	else
1134	u16 = pgmPoolTrackPhysExtAddref(pVM, u16, pShwPage->idx);
1135
1136	/* write back, trying to be clever... */
1137	Log2(("SyncPageWorkerTrackAddRef: u16=%#x pPage->HCPhys=%VHp->%VHp iPTDst=%#x\n",
1138	u16, pPage->HCPhys, (pPage->HCPhys & MM_RAM_FLAGS_NO_REFS_MASK) \| ((uint64_t)u16 << MM_RAM_FLAGS_CREFS_SHIFT), iPTDst));
1139	((uint16_t )&pPage->HCPhys + 3) = u16; /** @todo PAGE FLAGS */
1140	# endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
1141
1142	/* update statistics. */
1143	pVM->pgm.s.CTXSUFF(pPool)->cPresent++;
1144	pShwPage->cPresent++;
1145	if (pShwPage->iFirstPresent > iPTDst)
1146	pShwPage->iFirstPresent = iPTDst;
1147	}
1148	#endif /* PGMPOOL_WITH_USER_TRACKING */
1149
1150
1151	/**
1152	* Creates a 4K shadow page for a guest page.
1153	*
1154	* For 4M pages the caller must convert the PDE4M to a PTE, this includes adjusting the
1155	* physical address. The PdeSrc argument only the flags are used. No page structured
1156	* will be mapped in this function.
1157	*
1158	* @param pVM VM handle.
1159	* @param pPteDst Destination page table entry.
1160	* @param PdeSrc Source page directory entry (i.e. Guest OS page directory entry).
1161	* Can safely assume that only the flags are being used.
1162	* @param PteSrc Source page table entry (i.e. Guest OS page table entry).
1163	* @param pShwPage Pointer to the shadow page.
1164	* @param iPTDst The index into the shadow table.
1165	*
1166	* @remark Not used for 2/4MB pages!
1167	*/
1168	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorker)(PVM pVM, PSHWPTE pPteDst, VBOXPDE PdeSrc, VBOXPTE PteSrc, PPGMPOOLPAGE pShwPage, unsigned iPTDst)
1169	{
1170	if (PteSrc.n.u1Present)
1171	{
1172	/*
1173	* Find the ram range.
1174	*/
1175	PPGMPAGE pPage;
1176	int rc = pgmPhysGetPageEx(&pVM->pgm.s, PteSrc.u & X86_PTE_PG_MASK, &pPage);
1177	if (VBOX_SUCCESS(rc))
1178	{
1179	/** @todo investiage PWT, PCD and PAT. */
1180	/*
1181	* Make page table entry.
1182	*/
1183	const RTHCPHYS HCPhys = pPage->HCPhys; /** @todo FLAGS */
1184	SHWPTE PteDst;
1185	if (HCPhys & (MM_RAM_FLAGS_PHYSICAL_ALL \| MM_RAM_FLAGS_VIRTUAL_ALL \| MM_RAM_FLAGS_PHYSICAL_WRITE \| MM_RAM_FLAGS_VIRTUAL_WRITE))
1186	{
1187	/** @todo r=bird: Are we actually handling dirty and access bits for pages with access handlers correctly? No. */
1188	if (!(HCPhys & (MM_RAM_FLAGS_PHYSICAL_ALL \| MM_RAM_FLAGS_VIRTUAL_ALL)))
1189	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT \| X86_PTE_RW))
1190	\| (HCPhys & X86_PTE_PAE_PG_MASK);
1191	else
1192	{
1193	LogFlow(("SyncPageWorker: monitored page (%VGp) -> mark not present\n", (HCPhys & (MM_RAM_FLAGS_PHYSICAL_ALL \| MM_RAM_FLAGS_VIRTUAL_ALL))));
1194	PteDst.u = 0;
1195	}
1196	/** @todo count these two kinds. */
1197	}
1198	else
1199	{
1200	#ifdef PGM_SYNC_DIRTY_BIT
1201	# ifdef PGM_SYNC_ACCESSED_BIT
1202	/*
1203	* If the page or page directory entry is not marked accessed,
1204	* we mark the page not present.
1205	*/
1206	if (!PteSrc.n.u1Accessed \|\| !PdeSrc.n.u1Accessed)
1207	{
1208	LogFlow(("SyncPageWorker: page and or page directory not accessed -> mark not present\n"));
1209	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,AccessedPage));
1210	PteDst.u = 0;
1211	}
1212	else
1213	# endif
1214	/*
1215	* If the page is not flagged as dirty and is writable, then make it read-only, so we can set the dirty bit
1216	* when the page is modified.
1217	*/
1218	if (!PteSrc.n.u1Dirty && (PdeSrc.n.u1Write & PteSrc.n.u1Write))
1219	{
1220	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPage));
1221	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT \| X86_PTE_RW))
1222	\| (HCPhys & X86_PTE_PAE_PG_MASK)
1223	\| PGM_PTFLAGS_TRACK_DIRTY;
1224	}
1225	else
1226	{
1227	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageSkipped));
1228	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT))
1229	\| (HCPhys & X86_PTE_PAE_PG_MASK);
1230	}
1231	#endif
1232	}
1233
1234	#ifdef PGMPOOL_WITH_USER_TRACKING
1235	/*
1236	* Keep user track up to date.
1237	*/
1238	if (PteDst.n.u1Present)
1239	{
1240	if (!pPteDst->n.u1Present)
1241	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst);
1242	else if ((pPteDst->u & SHW_PTE_PG_MASK) != (PteDst.u & SHW_PTE_PG_MASK))
1243	{
1244	Log2(("SyncPageWorker: deref! *pPteDst=%RX64 PteDst=%RX64\n", (uint64_t)pPteDst->u, (uint64_t)PteDst.u));
1245	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1246	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst);
1247	}
1248	}
1249	else if (pPteDst->n.u1Present)
1250	{
1251	Log2(("SyncPageWorker: deref! *pPteDst=%RX64\n", (uint64_t)pPteDst->u));
1252	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1253	}
1254	#endif /* PGMPOOL_WITH_USER_TRACKING */
1255
1256	/*
1257	* Update statistics and commit the entry.
1258	*/
1259	if (!PteSrc.n.u1Global)
1260	pShwPage->fSeenNonGlobal = true;
1261	*pPteDst = PteDst;
1262	}
1263	/* else MMIO or invalid page, we must handle them manually in the #PF handler. */
1264	/** @todo count these. */
1265	}
1266	else
1267	{
1268	/*
1269	* Page not-present.
1270	*/
1271	LogFlow(("SyncPageWorker: page not present in Pte\n"));
1272	#ifdef PGMPOOL_WITH_USER_TRACKING
1273	/* Keep user track up to date. */
1274	if (pPteDst->n.u1Present)
1275	{
1276	Log2(("SyncPageWorker: deref! *pPteDst=%RX64\n", (uint64_t)pPteDst->u));
1277	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1278	}
1279	#endif /* PGMPOOL_WITH_USER_TRACKING */
1280	pPteDst->u = 0;
1281	/** @todo count these. */
1282	}
1283	}
1284
1285
1286	/**
1287	* Syncs a guest OS page.
1288	*
1289	* There are no conflicts at this point, neither is there any need for
1290	* page table allocations.
1291	*
1292	* @returns VBox status code.
1293	* @returns VINF_PGM_SYNCPAGE_MODIFIED_PDE if it modifies the PDE in any way.
1294	* @param pVM VM handle.
1295	* @param PdeSrc Page directory entry of the guest.
1296	* @param GCPtrPage Guest context page address.
1297	* @param cPages Number of pages to sync (PGM_SYNC_N_PAGES) (default=1).
1298	* @param uErr Fault error (X86_TRAP_PF_*).
1299	*/
1300	PGM_BTH_DECL(int, SyncPage)(PVM pVM, VBOXPDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uErr)
1301	{
1302	LogFlow(("SyncPage: GCPtrPage=%VGv cPages=%d uErr=%#x\n", GCPtrPage, cPages, uErr));
1303
1304	#if PGM_GST_TYPE == PGM_TYPE_32BIT
1305
1306	# if PGM_SHW_TYPE != PGM_TYPE_32BIT && PGM_SHW_TYPE != PGM_TYPE_PAE
1307	# error "Invalid shadow mode for 32-bit guest mode!"
1308	# endif
1309
1310	/*
1311	* Assert preconditions.
1312	*/
1313	# if GC_ARCH_BITS != 32
1314	Assert(GCPtrPage < _4G); //???
1315	# endif
1316	STAM_COUNTER_INC(&pVM->pgm.s.StatGCSyncPagePD[(GCPtrPage >> X86_PD_SHIFT) & X86_PD_MASK]);
1317	Assert(PdeSrc.n.u1Present);
1318	Assert(cPages);
1319
1320	/*
1321	* Get the shadow PDE, find the shadow page table in the pool.
1322	*/
1323	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
1324	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1325	X86PDE PdeDst = pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst];
1326	# else /* PAE */
1327	X86PDEPAE PdeDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[iPDDst];
1328	# endif
1329	Assert(PdeDst.n.u1Present);
1330	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1331
1332	/*
1333	* Check that the page is present and that the shadow PDE isn't out of sync.
1334	*/
1335	const bool fBigPage = PdeSrc.b.u1Size && (CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
1336	RTGCPHYS GCPhys;
1337	if (!fBigPage)
1338	{
1339	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
1340	# if PGM_SHW_TYPE != PGM_TYPE_32BIT
1341	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE/2);
1342	# endif
1343	}
1344	else
1345	{
1346	GCPhys = PdeSrc.u & GST_PDE4M_PG_MASK;
1347	# if PGM_SHW_TYPE != PGM_TYPE_32BIT
1348	GCPhys \|= GCPtrPage & X86_PAGE_2M_SIZE;
1349	# endif
1350	}
1351	if ( pShwPage->GCPhys == GCPhys
1352	&& PdeSrc.n.u1Present
1353	&& (PdeSrc.n.u1User == PdeDst.n.u1User)
1354	&& (PdeSrc.n.u1Write == PdeDst.n.u1Write \|\| !PdeDst.n.u1Write)
1355	)
1356	{
1357	# ifdef PGM_SYNC_ACCESSED_BIT
1358	/*
1359	* Check that the PDE is marked accessed already.
1360	* Since we set the accessed bit before getting here on a #PF, this
1361	* check is only meant for dealing with non-#PF'ing paths.
1362	*/
1363	if (PdeSrc.n.u1Accessed)
1364	# endif
1365	{
1366	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1367	if (!fBigPage)
1368	{
1369	/*
1370	* 4KB Page - Map the guest page table.
1371	*/
1372	PVBOXPT pPTSrc;
1373	int rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & X86_PDE_PG_MASK, &pPTSrc);
1374	if (VBOX_SUCCESS(rc))
1375	{
1376	# ifdef PGM_SYNC_N_PAGES
1377	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
1378	if (cPages > 1 && !(uErr & X86_TRAP_PF_P))
1379	{
1380	/*
1381	* This code path is currently only taken when the caller is PGMTrap0eHandler
1382	* for non-present pages!
1383	*
1384	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
1385	* deal with locality.
1386	*/
1387	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1388	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1389	const unsigned offPTSrc = 0;
1390	# else
1391	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
1392	# endif
1393	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, ELEMENTS(pPTDst->a));
1394	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
1395	iPTDst = 0;
1396	else
1397	iPTDst -= PGM_SYNC_NR_PAGES / 2;
1398	for (; iPTDst < iPTDstEnd; iPTDst++)
1399	{
1400	if (!pPTDst->a[iPTDst].n.u1Present)
1401	{
1402	VBOXPTE PteSrc = pPTSrc->a[offPTSrc + iPTDst];
1403	RTGCUINTPTR GCPtrCurPage = ((RTGCUINTPTR)GCPtrPage & ~(RTGCUINTPTR)(X86_PT_MASK << X86_PT_SHIFT)) \| ((offPTSrc + iPTDst) << PAGE_SHIFT);
1404	NOREF(GCPtrCurPage);
1405	#ifndef IN_RING0
1406	/*
1407	* Assuming kernel code will be marked as supervisor - and not as user level
1408	* and executed using a conforming code selector - And marked as readonly.
1409	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
1410	*/
1411	if ( ((PdeSrc.u & PteSrc.u) & (X86_PTE_RW \| X86_PTE_US))
1412	\|\| iPTDst == ((GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK) /* always sync GCPtrPage */
1413	\|\| !CSAMDoesPageNeedScanning(pVM, (RTGCPTR)GCPtrCurPage)
1414	\|\| pgmRamTestFlags(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK,
1415	MM_RAM_FLAGS_PHYSICAL_ALL \| MM_RAM_FLAGS_VIRTUAL_ALL \| MM_RAM_FLAGS_PHYSICAL_WRITE \| MM_RAM_FLAGS_VIRTUAL_WRITE)
1416	)
1417	#endif
1418	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1419	Log2(("SyncPage: 4K+ %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
1420	GCPtrCurPage, PteSrc.n.u1Present,
1421	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1422	PteSrc.n.u1User & PdeSrc.n.u1User,
1423	(uint64_t)PteSrc.u,
1424	(uint64_t)pPTDst->a[iPTDst].u,
1425	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1426	}
1427	}
1428	}
1429	else
1430	# endif /* PGM_SYNC_N_PAGES */
1431	{
1432	const unsigned iPTSrc = (GCPtrPage >> X86_PT_SHIFT) & X86_PT_MASK;
1433	VBOXPTE PteSrc = pPTSrc->a[iPTSrc];
1434	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1435	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1436	Log2(("SyncPage: 4K %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s\n",
1437	GCPtrPage, PteSrc.n.u1Present,
1438	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1439	PteSrc.n.u1User & PdeSrc.n.u1User,
1440	(uint64_t)PteSrc.u,
1441	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1442	}
1443	}
1444	else /* MMIO or invalid page: emulated in #PF handler. */
1445	{
1446	LogFlow(("PGM_GCPHYS_2_PTR %VGp failed with %Vrc\n", GCPhys, rc));
1447	Assert(!pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK].n.u1Present);
1448	}
1449	}
1450	else
1451	{
1452	/*
1453	* 4/2MB page - lazy syncing shadow 4K pages.
1454	* (There are many causes of getting here, it's no longer only CSAM.)
1455	*/
1456	/* Calculate the GC physical address of this 4KB shadow page. */
1457	RTGCPHYS GCPhys = (PdeSrc.u & X86_PDE4M_PAE_PG_MASK) \| ((RTGCUINTPTR)GCPtrPage & PAGE_OFFSET_MASK_BIG);
1458	/* Find ram range. */
1459	PPGMPAGE pPage;
1460	int rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
1461	if (VBOX_SUCCESS(rc))
1462	{
1463	/*
1464	* Make shadow PTE entry.
1465	*/
1466	RTHCPHYS HCPhys = pPage->HCPhys; /** @todo PAGE FLAGS */
1467	SHWPTE PteDst;
1468	PteDst.u = (PdeSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT))
1469	\| (HCPhys & X86_PTE_PAE_PG_MASK);
1470	if (HCPhys & (MM_RAM_FLAGS_PHYSICAL_ALL \| MM_RAM_FLAGS_VIRTUAL_ALL \| MM_RAM_FLAGS_PHYSICAL_WRITE \| MM_RAM_FLAGS_VIRTUAL_WRITE))
1471	{
1472	if (!(HCPhys & (MM_RAM_FLAGS_PHYSICAL_ALL \| MM_RAM_FLAGS_VIRTUAL_ALL)))
1473	PteDst.n.u1Write = 0;
1474	else
1475	PteDst.u = 0;
1476	}
1477	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1478	# ifdef PGMPOOL_WITH_USER_TRACKING
1479	if (PteDst.n.u1Present && !pPTDst->a[iPTDst].n.u1Present)
1480	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst);
1481	# endif
1482	pPTDst->a[iPTDst] = PteDst;
1483
1484
1485	# ifdef PGM_SYNC_DIRTY_BIT
1486	/*
1487	* If the page is not flagged as dirty and is writable, then make it read-only
1488	* at PD level, so we can set the dirty bit when the page is modified.
1489	*
1490	* ASSUMES that page access handlers are implemented on page table entry level.
1491	* Thus we will first catch the dirty access and set PDE.D and restart. If
1492	* there is an access handler, we'll trap again and let it work on the problem.
1493	*/
1494	/** @todo r=bird: figure out why we need this here, SyncPT should've taken care of this already.
1495	* As for invlpg, it simply frees the whole shadow PT.
1496	* ...It's possibly because the guest clears it and the guest doesn't really tell us... */
1497	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
1498	{
1499	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageBig));
1500	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
1501	PdeDst.n.u1Write = 0;
1502	}
1503	else
1504	{
1505	PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
1506	PdeDst.n.u1Write = PdeSrc.n.u1Write;
1507	}
1508	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1509	pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst] = PdeDst;
1510	# else /* PAE */
1511	pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[iPDDst] = PdeDst;
1512	# endif
1513	# endif /* PGM_SYNC_DIRTY_BIT */
1514	Log2(("SyncPage: BIG %VGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} GCPhys=%VGp%s\n",
1515	GCPtrPage, PdeSrc.n.u1Present, PdeSrc.n.u1Write, PdeSrc.n.u1User, (uint64_t)PdeSrc.u, GCPhys,
1516	PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1517	}
1518	else
1519	LogFlow(("PGM_GCPHYS_2_PTR %VGp (big) failed with %Vrc\n", GCPhys, rc));
1520	}
1521	return VINF_SUCCESS;
1522	}
1523	# ifdef PGM_SYNC_ACCESSED_BIT
1524	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncPagePDNAs));
1525	#endif
1526	}
1527	else
1528	{
1529	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncPagePDOutOfSync));
1530	Log2(("SyncPage: Out-Of-Sync PDE at %VGp PdeSrc=%RX64 PdeDst=%RX64\n",
1531	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1532	}
1533
1534	/*
1535	* Mark the PDE not present. Restart the instruction and let #PF call SyncPT.
1536	* Yea, I'm lazy.
1537	*/
1538	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1539	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1540	pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst].u = 0;
1541	# else /* PAE */
1542	pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[iPDDst].u = 0;
1543	# endif
1544	PGM_INVL_GUEST_TLBS();
1545	return VINF_PGM_SYNCPAGE_MODIFIED_PDE;
1546
1547	#elif PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT
1548
1549	# ifdef PGM_SYNC_N_PAGES
1550	/*
1551	* Get the shadow PDE, find the shadow page table in the pool.
1552	*/
1553	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
1554	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1555	X86PDE PdeDst = pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst];
1556	# else /* PAE */
1557	X86PDEPAE PdeDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[iPDDst];
1558	# endif
1559	Assert(PdeDst.n.u1Present);
1560	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1561	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1562
1563	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1564	const unsigned offPTSrc = 0;
1565	# else
1566	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
1567	# endif
1568
1569	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
1570	if (cPages > 1 && !(uErr & X86_TRAP_PF_P))
1571	{
1572	/*
1573	* This code path is currently only taken when the caller is PGMTrap0eHandler
1574	* for non-present pages!
1575	*
1576	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
1577	* deal with locality.
1578	*/
1579	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1580	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, ELEMENTS(pPTDst->a));
1581	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
1582	iPTDst = 0;
1583	else
1584	iPTDst -= PGM_SYNC_NR_PAGES / 2;
1585	for (; iPTDst < iPTDstEnd; iPTDst++)
1586	{
1587	if (!pPTDst->a[iPTDst].n.u1Present)
1588	{
1589	VBOXPTE PteSrc;
1590
1591	RTGCUINTPTR GCPtrCurPage = ((RTGCUINTPTR)GCPtrPage & ~(RTGCUINTPTR)(X86_PT_MASK << X86_PT_SHIFT)) \| ((offPTSrc + iPTDst) << PAGE_SHIFT);
1592
1593	/* Fake the page table entry */
1594	PteSrc.u = GCPtrCurPage;
1595	PteSrc.n.u1Present = 1;
1596	PteSrc.n.u1Dirty = 1;
1597	PteSrc.n.u1Accessed = 1;
1598	PteSrc.n.u1Write = 1;
1599	PteSrc.n.u1User = 1;
1600
1601	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1602
1603	Log2(("SyncPage: 4K+ %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
1604	GCPtrCurPage, PteSrc.n.u1Present,
1605	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1606	PteSrc.n.u1User & PdeSrc.n.u1User,
1607	(uint64_t)PteSrc.u,
1608	(uint64_t)pPTDst->a[iPTDst].u,
1609	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1610	}
1611	}
1612	}
1613	else
1614	# endif /* PGM_SYNC_N_PAGES */
1615	{
1616	VBOXPTE PteSrc;
1617	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1618	RTGCUINTPTR GCPtrCurPage = ((RTGCUINTPTR)GCPtrPage & ~(RTGCUINTPTR)(X86_PT_MASK << X86_PT_SHIFT)) \| ((offPTSrc + iPTDst) << PAGE_SHIFT);
1619
1620	/* Fake the page table entry */
1621	PteSrc.u = GCPtrCurPage;
1622	PteSrc.n.u1Present = 1;
1623	PteSrc.n.u1Dirty = 1;
1624	PteSrc.n.u1Accessed = 1;
1625	PteSrc.n.u1Write = 1;
1626	PteSrc.n.u1User = 1;
1627	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1628
1629	Log2(("SyncPage: 4K %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s\n",
1630	GCPtrPage, PteSrc.n.u1Present,
1631	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1632	PteSrc.n.u1User & PdeSrc.n.u1User,
1633	(uint64_t)PteSrc.u,
1634	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1635	}
1636	return VINF_SUCCESS;
1637
1638	#else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1639	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
1640	return VERR_INTERNAL_ERROR;
1641	#endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1642	}
1643
1644
1645
1646	#if PGM_WITH_PAGING(PGM_GST_TYPE)
1647
1648	# ifdef PGM_SYNC_DIRTY_BIT
1649
1650	/**
1651	* Investigate page fault and handle write protection page faults caused by
1652	* dirty bit tracking.
1653	*
1654	* @returns VBox status code.
1655	* @param pVM VM handle.
1656	* @param uErr Page fault error code.
1657	* @param pPdeDst Shadow page directory entry.
1658	* @param pPdeSrc Guest page directory entry.
1659	* @param GCPtrPage Guest context page address.
1660	*/
1661	PGM_BTH_DECL(int, CheckPageFault)(PVM pVM, uint32_t uErr, PSHWPDE pPdeDst, PVBOXPDE pPdeSrc, RTGCUINTPTR GCPtrPage)
1662	{
1663	STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat, DirtyBitTracking), a);
1664	LogFlow(("CheckPageFault: GCPtrPage=%VGv uErr=%#x PdeSrc=%08x\n", GCPtrPage, uErr, pPdeSrc->u));
1665
1666	/*
1667	* Real page fault?
1668	*/
1669	if ( (uErr & X86_TRAP_PF_RSVD)
1670	\|\| !pPdeSrc->n.u1Present
1671	\|\| ((uErr & X86_TRAP_PF_RW) && !pPdeSrc->n.u1Write)
1672	\|\| ((uErr & X86_TRAP_PF_US) && !pPdeSrc->n.u1User) )
1673	{
1674	# ifdef IN_GC
1675	STAM_COUNTER_INC(&pVM->pgm.s.StatGCDirtyTrackRealPF);
1676	# endif
1677	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat, DirtyBitTracking), a);
1678	LogFlow(("CheckPageFault: real page fault at %VGv (1)\n", GCPtrPage));
1679
1680	if (pPdeSrc->n.u1Present)
1681	{
1682	/* Check the present bit as the shadow tables can cause different error codes by being out of sync.
1683	* See the 2nd case below as well.
1684	*/
1685	if (pPdeSrc->b.u1Size && (CPUMGetGuestCR4(pVM) & X86_CR4_PSE))
1686	{
1687	TRPMSetErrorCode(pVM, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
1688	}
1689	else
1690	{
1691	/*
1692	* Map the guest page table.
1693	*/
1694	PVBOXPT pPTSrc;
1695	int rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & X86_PDE_PG_MASK, &pPTSrc);
1696	if (VBOX_SUCCESS(rc))
1697	{
1698	PVBOXPTE pPteSrc = &pPTSrc->a[(GCPtrPage >> PAGE_SHIFT) & PTE_MASK];
1699	const VBOXPTE PteSrc = *pPteSrc;
1700	if (pPteSrc->n.u1Present)
1701	TRPMSetErrorCode(pVM, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
1702	}
1703	AssertRC(rc);
1704	}
1705	}
1706	return VINF_EM_RAW_GUEST_TRAP;
1707	}
1708
1709	/*
1710	* First check the easy case where the page directory has been marked read-only to track
1711	* the dirty bit of an emulated BIG page
1712	*/
1713	if (pPdeSrc->b.u1Size && (CPUMGetGuestCR4(pVM) & X86_CR4_PSE))
1714	{
1715	/* Mark guest page directory as accessed */
1716	pPdeSrc->b.u1Accessed = 1;
1717
1718	/*
1719	* Only write protection page faults are relevant here.
1720	*/
1721	if (uErr & X86_TRAP_PF_RW)
1722	{
1723	/* Mark guest page directory as dirty (BIG page only). */
1724	pPdeSrc->b.u1Dirty = 1;
1725
1726	if (pPdeDst->n.u1Present && (pPdeDst->u & PGM_PDFLAGS_TRACK_DIRTY))
1727	{
1728	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageTrap));
1729
1730	Assert(pPdeSrc->b.u1Write);
1731
1732	pPdeDst->n.u1Write = 1;
1733	pPdeDst->n.u1Accessed = 1;
1734	pPdeDst->au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
1735	PGM_INVL_BIG_PG(GCPtrPage);
1736	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1737	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT;
1738	}
1739	}
1740	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1741	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
1742	}
1743	/* else: 4KB page table */
1744
1745	/*
1746	* Map the guest page table.
1747	*/
1748	PVBOXPT pPTSrc;
1749	int rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & X86_PDE_PG_MASK, &pPTSrc);
1750	if (VBOX_SUCCESS(rc))
1751	{
1752	/*
1753	* Real page fault?
1754	*/
1755	PVBOXPTE pPteSrc = &pPTSrc->a[(GCPtrPage >> PAGE_SHIFT) & PTE_MASK];
1756	const VBOXPTE PteSrc = *pPteSrc;
1757	if ( !PteSrc.n.u1Present
1758	\|\| ((uErr & X86_TRAP_PF_RW) && !PteSrc.n.u1Write)
1759	\|\| ((uErr & X86_TRAP_PF_US) && !PteSrc.n.u1User)
1760	)
1761	{
1762	# ifdef IN_GC
1763	STAM_COUNTER_INC(&pVM->pgm.s.StatGCDirtyTrackRealPF);
1764	# endif
1765	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1766	LogFlow(("CheckPageFault: real page fault at %VGv PteSrc.u=%08x (2)\n", GCPtrPage, PteSrc.u));
1767
1768	/* Check the present bit as the shadow tables can cause different error codes by being out of sync.
1769	* See the 2nd case above as well.
1770	*/
1771	if (pPdeSrc->n.u1Present && pPteSrc->n.u1Present)
1772	TRPMSetErrorCode(pVM, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
1773
1774	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1775	return VINF_EM_RAW_GUEST_TRAP;
1776	}
1777	LogFlow(("CheckPageFault: page fault at %VGv PteSrc.u=%08x\n", GCPtrPage, PteSrc.u));
1778
1779	/*
1780	* Set the accessed bits in the page directory and the page table.
1781	*/
1782	pPdeSrc->n.u1Accessed = 1;
1783	pPteSrc->n.u1Accessed = 1;
1784
1785	/*
1786	* Only write protection page faults are relevant here.
1787	*/
1788	if (uErr & X86_TRAP_PF_RW)
1789	{
1790	/* Write access, so mark guest entry as dirty. */
1791	# if defined(IN_GC) && defined(VBOX_WITH_STATISTICS)
1792	if (!pPteSrc->n.u1Dirty)
1793	STAM_COUNTER_INC(&pVM->pgm.s.StatGCDirtiedPage);
1794	else
1795	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageAlreadyDirty);
1796	# endif
1797	pPteSrc->n.u1Dirty = 1;
1798
1799	if (pPdeDst->n.u1Present)
1800	{
1801	/* Bail out here as pgmPoolGetPageByHCPhys will return NULL and we'll crash below.
1802	* Our individual shadow handlers will provide more information and force a fatal exit.
1803	*/
1804	if (MMHyperIsInsideArea(pVM, (RTGCPTR)GCPtrPage))
1805	{
1806	LogRel(("CheckPageFault: write to hypervisor region %VGv\n", GCPtrPage));
1807	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1808	return VINF_SUCCESS;
1809	}
1810
1811	/*
1812	* Map shadow page table.
1813	*/
1814	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, pPdeDst->u & SHW_PDE_PG_MASK);
1815	if (pShwPage)
1816	{
1817	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1818	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
1819	if ( pPteDst->n.u1Present /** @todo Optimize accessed bit emulation? */
1820	&& (pPteDst->u & PGM_PTFLAGS_TRACK_DIRTY))
1821	{
1822	LogFlow(("DIRTY page trap addr=%VGv\n", GCPtrPage));
1823	# ifdef VBOX_STRICT
1824	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, pPteSrc->u & X86_PTE_PG_MASK);
1825	if (pPage)
1826	AssertMsg(!(pPage->HCPhys & (MM_RAM_FLAGS_PHYSICAL_ALL \| MM_RAM_FLAGS_VIRTUAL_ALL \| MM_RAM_FLAGS_PHYSICAL_WRITE \| MM_RAM_FLAGS_VIRTUAL_WRITE)), /** @todo PAGE FLAGS */
1827	("Unexpected dirty bit tracking on monitored page %VGv (phys %VGp)!!!!!!\n", GCPtrPage, pPteSrc->u & X86_PTE_PAE_PG_MASK));
1828	# endif
1829	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageTrap));
1830
1831	Assert(pPteSrc->n.u1Write);
1832
1833	pPteDst->n.u1Write = 1;
1834	pPteDst->n.u1Dirty = 1;
1835	pPteDst->n.u1Accessed = 1;
1836	pPteDst->au32[0] &= ~PGM_PTFLAGS_TRACK_DIRTY;
1837	PGM_INVL_PG(GCPtrPage);
1838
1839	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1840	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT;
1841	}
1842	}
1843	else
1844	AssertMsgFailed(("pgmPoolGetPageByHCPhys %VGp failed!\n", pPdeDst->u & SHW_PDE_PG_MASK));
1845	}
1846	}
1847	/** @todo Optimize accessed bit emulation? */
1848	# ifdef VBOX_STRICT
1849	/*
1850	* Sanity check.
1851	*/
1852	else if ( !pPteSrc->n.u1Dirty
1853	&& (pPdeSrc->n.u1Write & pPteSrc->n.u1Write)
1854	&& pPdeDst->n.u1Present)
1855	{
1856	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, pPdeDst->u & SHW_PDE_PG_MASK);
1857	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1858	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
1859	if ( pPteDst->n.u1Present
1860	&& pPteDst->n.u1Write)
1861	LogFlow(("Writable present page %VGv not marked for dirty bit tracking!!!\n", GCPtrPage));
1862	}
1863	# endif /* VBOX_STRICT */
1864	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1865	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
1866	}
1867	AssertRC(rc);
1868	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1869	return rc;
1870	}
1871
1872	# endif
1873
1874	#endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
1875
1876
1877	/**
1878	* Sync a shadow page table.
1879	*
1880	* The shadow page table is not present. This includes the case where
1881	* there is a conflict with a mapping.
1882	*
1883	* @returns VBox status code.
1884	* @param pVM VM handle.
1885	* @param iPD Page directory index.
1886	* @param pPDSrc Source page directory (i.e. Guest OS page directory).
1887	* Assume this is a temporary mapping.
1888	* @param GCPtrPage GC Pointer of the page that caused the fault
1889	*/
1890	PGM_BTH_DECL(int, SyncPT)(PVM pVM, unsigned iPDSrc, PVBOXPD pPDSrc, RTGCUINTPTR GCPtrPage)
1891	{
1892	STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
1893	STAM_COUNTER_INC(&pVM->pgm.s.StatGCSyncPtPD[iPDSrc]);
1894	LogFlow(("SyncPT: GCPtrPage=%VGv\n", GCPtrPage));
1895
1896	#if PGM_GST_TYPE == PGM_TYPE_32BIT
1897
1898	# if PGM_SHW_TYPE != PGM_TYPE_32BIT && PGM_SHW_TYPE != PGM_TYPE_PAE
1899	# error "Invalid shadow mode for 32-bit guest mode!"
1900	# endif
1901
1902	/*
1903	* Validate input a little bit.
1904	*/
1905	Assert(iPDSrc == (GCPtrPage >> GST_PD_SHIFT));
1906	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1907	PX86PD pPDDst = pVM->pgm.s.CTXMID(p,32BitPD);
1908	# else
1909	PX86PDPAE pPDDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0];
1910	# endif
1911	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
1912	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
1913	SHWPDE PdeDst = *pPdeDst;
1914
1915	/*
1916	* Check for conflicts.
1917	* GC: In case of a conflict we'll go to Ring-3 and do a full SyncCR3.
1918	* HC: Simply resolve the conflict.
1919	*/
1920	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
1921	{
1922	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1923	# ifndef IN_RING3
1924	Log(("SyncPT: Conflict at %VGv\n", GCPtrPage));
1925	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
1926	return VERR_ADDRESS_CONFLICT;
1927	# else
1928	PPGMMAPPING pMapping = pgmGetMapping(pVM, (RTGCPTR)GCPtrPage);
1929	Assert(pMapping);
1930	int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, iPDSrc);
1931	if (VBOX_FAILURE(rc))
1932	{
1933	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
1934	return rc;
1935	}
1936	PdeDst = *pPdeDst;
1937	# endif
1938	}
1939	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
1940
1941	/*
1942	* Sync page directory entry.
1943	*/
1944	int rc = VINF_SUCCESS;
1945	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
1946	if (PdeSrc.n.u1Present)
1947	{
1948	/*
1949	* Allocate & map the page table.
1950	*/
1951	PSHWPT pPTDst;
1952	const bool fPageTable = !PdeSrc.b.u1Size \|\| !(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
1953	PPGMPOOLPAGE pShwPage;
1954	RTGCPHYS GCPhys;
1955	if (fPageTable)
1956	{
1957	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
1958	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1959	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE / 2);
1960	# endif
1961	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, SHW_POOL_ROOT_IDX, iPDDst, &pShwPage);
1962	}
1963	else
1964	{
1965	GCPhys = PdeSrc.u & GST_PDE4M_PG_MASK;
1966	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1967	GCPhys \|= GCPtrPage & BIT(X86_PAGE_2M_SHIFT);
1968	# endif
1969	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_BIG, SHW_POOL_ROOT_IDX, iPDDst, &pShwPage);
1970	}
1971	if (rc == VINF_SUCCESS)
1972	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1973	else if (rc == VINF_PGM_CACHED_PAGE)
1974	{
1975	/*
1976	* The PT was cached, just hook it up.
1977	*/
1978	if (fPageTable)
1979	PdeDst.u = pShwPage->Core.Key
1980	\| (PdeSrc.u & ~(X86_PDE_PAE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
1981	else
1982	{
1983	PdeDst.u = pShwPage->Core.Key
1984	\| (PdeSrc.u & ~(X86_PDE_PAE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
1985	# ifdef PGM_SYNC_DIRTY_BIT /* (see explanation and assumtions further down.) */
1986	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
1987	{
1988	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageBig));
1989	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
1990	PdeDst.b.u1Write = 0;
1991	}
1992	# endif
1993	}
1994	*pPdeDst = PdeDst;
1995	return VINF_SUCCESS;
1996	}
1997	else if (rc == VERR_PGM_POOL_FLUSHED)
1998	return VINF_PGM_SYNC_CR3;
1999	else
2000	AssertMsgFailedReturn(("rc=%Vrc\n", rc), VERR_INTERNAL_ERROR);
2001	PdeDst.u &= X86_PDE_AVL_MASK;
2002	PdeDst.u \|= pShwPage->Core.Key;
2003
2004	# ifdef PGM_SYNC_DIRTY_BIT
2005	/*
2006	* Page directory has been accessed (this is a fault situation, remember).
2007	*/
2008	pPDSrc->a[iPDSrc].n.u1Accessed = 1;
2009	# endif
2010	if (fPageTable)
2011	{
2012	/*
2013	* Page table - 4KB.
2014	*
2015	* Sync all or just a few entries depending on PGM_SYNC_N_PAGES.
2016	*/
2017	Log2(("SyncPT: 4K %VGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx}\n",
2018	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u));
2019	PGSTPT pPTSrc;
2020	rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
2021	if (VBOX_SUCCESS(rc))
2022	{
2023	/*
2024	* Start by syncing the page directory entry so CSAM's TLB trick works.
2025	*/
2026	PdeDst.u = (PdeDst.u & (X86_PDE_PAE_PG_MASK \| X86_PDE_AVL_MASK))
2027	\| (PdeSrc.u & ~(X86_PDE_PAE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2028	*pPdeDst = PdeDst;
2029
2030	/*
2031	* Directory/page user or supervisor privilege: (same goes for read/write)
2032	*
2033	* Directory Page Combined
2034	* U/S U/S U/S
2035	* 0 0 0
2036	* 0 1 0
2037	* 1 0 0
2038	* 1 1 1
2039	*
2040	* Simple AND operation. Table listed for completeness.
2041	*
2042	*/
2043	STAM_COUNTER_INC(CTXSUFF(&pVM->pgm.s.StatSynPT4k));
2044	# ifdef PGM_SYNC_N_PAGES
2045	unsigned iPTBase = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2046	unsigned iPTDst = iPTBase;
2047	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, ELEMENTS(pPTDst->a));
2048	if (iPTDst <= PGM_SYNC_NR_PAGES / 2)
2049	iPTDst = 0;
2050	else
2051	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2052	# else /* !PGM_SYNC_N_PAGES */
2053	unsigned iPTDst = 0;
2054	const unsigned iPTDstEnd = ELEMENTS(pPTDst->a);
2055	# endif /* !PGM_SYNC_N_PAGES */
2056	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2057	const unsigned offPTSrc = 0;
2058	# else
2059	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
2060	# endif
2061	for (; iPTDst < iPTDstEnd; iPTDst++)
2062	{
2063	const unsigned iPTSrc = iPTDst + offPTSrc;
2064	const GSTPTE PteSrc = pPTSrc->a[iPTSrc];
2065
2066	if (PteSrc.n.u1Present) /* we've already cleared it above */
2067	{
2068	#ifndef IN_RING0
2069	/*
2070	* Assuming kernel code will be marked as supervisor - and not as user level
2071	* and executed using a conforming code selector - And marked as readonly.
2072	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
2073	*/
2074	if ( ((PdeSrc.u & pPTSrc->a[iPTSrc].u) & (X86_PTE_RW \| X86_PTE_US))
2075	\|\| !CSAMDoesPageNeedScanning(pVM, (RTGCPTR)((iPDSrc << GST_PD_SHIFT) \| (iPTSrc << PAGE_SHIFT)))
2076	\|\| pgmRamTestFlags(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK,
2077	MM_RAM_FLAGS_PHYSICAL_ALL \| MM_RAM_FLAGS_VIRTUAL_ALL \| MM_RAM_FLAGS_PHYSICAL_WRITE \| MM_RAM_FLAGS_VIRTUAL_WRITE)
2078	)
2079	#endif
2080	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2081	Log2(("SyncPT: 4K+ %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s dst.raw=%08llx iPTSrc=%x PdeSrc.u=%x physpte=%VGp\n",
2082	(RTGCPTR)((iPDSrc << GST_PD_SHIFT) \| (iPTSrc << PAGE_SHIFT)),
2083	PteSrc.n.u1Present,
2084	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2085	PteSrc.n.u1User & PdeSrc.n.u1User,
2086	(uint64_t)PteSrc.u,
2087	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : "", pPTDst->a[iPTDst].u, iPTSrc, PdeSrc.au32[0],
2088	(PdeSrc.u & GST_PDE_PG_MASK) + iPTSrc*sizeof(PteSrc)));
2089	}
2090	} /* for PTEs */
2091	}
2092	}
2093	else
2094	{
2095	/*
2096	* Big page - 2/4MB.
2097	*
2098	* We'll walk the ram range list in parallel and optimize lookups.
2099	* We will only sync on shadow page table at a time.
2100	*/
2101	STAM_COUNTER_INC(CTXSUFF(&pVM->pgm.s.StatSynPT4M));
2102
2103	/**
2104	* @todo It might be more efficient to sync only a part of the 4MB page (similar to what we do for 4kb PDs).
2105	*/
2106
2107	/*
2108	* Start by syncing the page directory entry.
2109	*/
2110	PdeDst.u = (PdeDst.u & (X86_PDE_PAE_PG_MASK \| (X86_PDE_AVL_MASK & ~PGM_PDFLAGS_TRACK_DIRTY)))
2111	\| (PdeSrc.u & ~(X86_PDE_PAE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2112
2113	# ifdef PGM_SYNC_DIRTY_BIT
2114	/*
2115	* If the page is not flagged as dirty and is writable, then make it read-only
2116	* at PD level, so we can set the dirty bit when the page is modified.
2117	*
2118	* ASSUMES that page access handlers are implemented on page table entry level.
2119	* Thus we will first catch the dirty access and set PDE.D and restart. If
2120	* there is an access handler, we'll trap again and let it work on the problem.
2121	*/
2122	/** @todo move the above stuff to a section in the PGM documentation. */
2123	Assert(!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY));
2124	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
2125	{
2126	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageBig));
2127	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2128	PdeDst.b.u1Write = 0;
2129	}
2130	# endif /* PGM_SYNC_DIRTY_BIT */
2131	*pPdeDst = PdeDst;
2132
2133	/*
2134	* Fill the shadow page table.
2135	*/
2136	/* Get address and flags from the source PDE. */
2137	SHWPTE PteDstBase;
2138	PteDstBase.u = PdeSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT);
2139
2140	/* Loop thru the entries in the shadow PT. */
2141	const RTGCUINTPTR GCPtr = (GCPtrPage >> SHW_PD_SHIFT) << SHW_PD_SHIFT; NOREF(GCPtr);
2142	Log2(("SyncPT: BIG %VGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} Shw=%VGv GCPhys=%VGp %s\n",
2143	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u, GCPtr,
2144	GCPhys, PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2145	PPGMRAMRANGE pRam = CTXSUFF(pVM->pgm.s.pRamRanges);
2146	unsigned iPTDst = 0;
2147	while (iPTDst < ELEMENTS(pPTDst->a))
2148	{
2149	/* Advance ram range list. */
2150	while (pRam && GCPhys > pRam->GCPhysLast)
2151	pRam = CTXSUFF(pRam->pNext);
2152	if (pRam && GCPhys >= pRam->GCPhys)
2153	{
2154	unsigned iHCPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
2155	do
2156	{
2157	/* Make shadow PTE. */
2158	PPGMPAGE pPage = &pRam->aPages[iHCPage];
2159	SHWPTE PteDst;
2160
2161	/* Make sure the RAM has already been allocated. */
2162	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC) /** @todo PAGE FLAGS */
2163	{
2164	if (RT_UNLIKELY(!PGM_PAGE_GET_HCPHYS(pPage)))
2165	{
2166	# ifdef IN_RING3
2167	int rc = pgmr3PhysGrowRange(pVM, GCPhys);
2168	# else
2169	int rc = CTXALLMID(VMM, CallHost)(pVM, VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
2170	# endif
2171	if (rc != VINF_SUCCESS)
2172	return rc;
2173	}
2174	}
2175
2176	if (pPage->HCPhys & (MM_RAM_FLAGS_PHYSICAL_ALL \| MM_RAM_FLAGS_VIRTUAL_ALL \| MM_RAM_FLAGS_PHYSICAL_WRITE \| MM_RAM_FLAGS_VIRTUAL_WRITE)) /** @todo PAGE FLAGS */
2177	{
2178	if (!(pPage->HCPhys & (MM_RAM_FLAGS_PHYSICAL_ALL \| MM_RAM_FLAGS_VIRTUAL_ALL))) /** @todo PAGE FLAGS */
2179	{
2180	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage) \| PteDstBase.u;
2181	PteDst.n.u1Write = 0;
2182	}
2183	else
2184	PteDst.u = 0;
2185	}
2186	# ifndef IN_RING0
2187	/*
2188	* Assuming kernel code will be marked as supervisor and not as user level and executed
2189	* using a conforming code selector. Don't check for readonly, as that implies the whole
2190	* 4MB can be code or readonly data. Linux enables write access for its large pages.
2191	*/
2192	else if ( !PdeSrc.n.u1User
2193	&& CSAMDoesPageNeedScanning(pVM, (RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT))))
2194	PteDst.u = 0;
2195	# endif
2196	else
2197	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage) \| PteDstBase.u;
2198	# ifdef PGMPOOL_WITH_USER_TRACKING
2199	if (PteDst.n.u1Present)
2200	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, pPage->HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst); /** @todo PAGE FLAGS */
2201	# endif
2202	/* commit it */
2203	pPTDst->a[iPTDst] = PteDst;
2204	Log4(("SyncPT: BIG %VGv PteDst:{P=%d RW=%d U=%d raw=%08llx}%s\n",
2205	(RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT)), PteDst.n.u1Present, PteDst.n.u1Write, PteDst.n.u1User, (uint64_t)PteDst.u,
2206	PteDst.u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2207
2208	/* advance */
2209	GCPhys += PAGE_SIZE;
2210	iHCPage++;
2211	iPTDst++;
2212	} while ( iPTDst < ELEMENTS(pPTDst->a)
2213	&& GCPhys <= pRam->GCPhysLast);
2214	}
2215	else if (pRam)
2216	{
2217	Log(("Invalid pages at %VGp\n", GCPhys));
2218	do
2219	{
2220	pPTDst->a[iPTDst].u = 0; /* MMIO or invalid page, we must handle them manually. */
2221	GCPhys += PAGE_SIZE;
2222	iPTDst++;
2223	} while ( iPTDst < ELEMENTS(pPTDst->a)
2224	&& GCPhys < pRam->GCPhys);
2225	}
2226	else
2227	{
2228	Log(("Invalid pages at %VGp (2)\n", GCPhys));
2229	for ( ; iPTDst < ELEMENTS(pPTDst->a); iPTDst++)
2230	pPTDst->a[iPTDst].u = 0; /* MMIO or invalid page, we must handle them manually. */
2231	}
2232	} /* while more PTEs */
2233	} /* 4KB / 4MB */
2234	}
2235	else
2236	AssertRelease(!PdeDst.n.u1Present);
2237
2238	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
2239	# ifdef IN_GC
2240	if (VBOX_FAILURE(rc))
2241	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncPTFailed));
2242	# endif
2243	return rc;
2244
2245	#elif PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT
2246
2247	int rc = VINF_SUCCESS;
2248
2249	/*
2250	* Validate input a little bit.
2251	*/
2252	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2253	PX86PD pPDDst = pVM->pgm.s.CTXMID(p,32BitPD);
2254	# else
2255	PX86PDPAE pPDDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0];
2256	# endif
2257	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
2258	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2259	SHWPDE PdeDst = *pPdeDst;
2260
2261	Assert(!(PdeDst.u & PGM_PDFLAGS_MAPPING));
2262	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
2263
2264	VBOXPDE PdeSrc;
2265	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
2266	PdeSrc.n.u1Present = 1;
2267	PdeSrc.n.u1Write = 1;
2268	PdeSrc.n.u1Accessed = 1;
2269	PdeSrc.n.u1User = 1;
2270
2271	/*
2272	* Allocate & map the page table.
2273	*/
2274	PSHWPT pPTDst;
2275	PPGMPOOLPAGE pShwPage;
2276	RTGCPHYS GCPhys;
2277
2278	/* Virtual address = physical address */
2279	GCPhys = GCPtrPage & X86_PAGE_4K_BASE_MASK_32;
2280	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, SHW_POOL_ROOT_IDX, iPDDst, &pShwPage);
2281
2282	if ( rc == VINF_SUCCESS
2283	\|\| rc == VINF_PGM_CACHED_PAGE)
2284	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2285	else
2286	AssertMsgFailedReturn(("rc=%Vrc\n", rc), VERR_INTERNAL_ERROR);
2287
2288	PdeDst.u &= X86_PDE_AVL_MASK;
2289	PdeDst.u \|= pShwPage->Core.Key;
2290	PdeDst.n.u1Present = 1;
2291	*pPdeDst = PdeDst;
2292
2293	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)GCPtrPage, PGM_SYNC_NR_PAGES, 0 /* page not present */);
2294	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
2295	return rc;
2296
2297	#else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
2298
2299	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
2300	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
2301	return VERR_INTERNAL_ERROR;
2302	#endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
2303	}
2304
2305
2306
2307	/**
2308	* Prefetch a page/set of pages.
2309	*
2310	* Typically used to sync commonly used pages before entering raw mode
2311	* after a CR3 reload.
2312	*
2313	* @returns VBox status code.
2314	* @param pVM VM handle.
2315	* @param GCPtrPage Page to invalidate.
2316	*/
2317	PGM_BTH_DECL(int, PrefetchPage)(PVM pVM, RTGCUINTPTR GCPtrPage)
2318	{
2319	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) && PGM_SHW_TYPE != PGM_TYPE_AMD64
2320
2321	# if PGM_SHW_TYPE != PGM_TYPE_32BIT && PGM_SHW_TYPE != PGM_TYPE_PAE
2322	# error "Invalid shadow mode for 32-bit guest mode!"
2323	# endif
2324
2325	/*
2326	* Check that all Guest levels thru the PDE are present, getting the
2327	* PD and PDE in the processes.
2328	*/
2329	int rc = VINF_SUCCESS;
2330	# if PGM_WITH_PAGING(PGM_GST_TYPE)
2331	PVBOXPD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
2332	const unsigned iPDSrc = (RTGCUINTPTR)GCPtrPage >> GST_PD_SHIFT;
2333	# else
2334	PVBOXPD pPDSrc = NULL;
2335	const unsigned iPDSrc = 0;
2336	# endif
2337
2338	# if PGM_WITH_PAGING(PGM_GST_TYPE)
2339	const VBOXPDE PdeSrc = pPDSrc->a[iPDSrc];
2340	# else
2341	VBOXPDE PdeSrc;
2342	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
2343	PdeSrc.n.u1Present = 1;
2344	PdeSrc.n.u1Write = 1;
2345	PdeSrc.n.u1Accessed = 1;
2346	PdeSrc.n.u1User = 1;
2347	# endif
2348
2349	# ifdef PGM_SYNC_ACCESSED_BIT
2350	if (PdeSrc.n.u1Present && PdeSrc.n.u1Accessed)
2351	# else
2352	if (PdeSrc.n.u1Present)
2353	# endif
2354	{
2355	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2356	const X86PDE PdeDst = pVM->pgm.s.CTXMID(p,32BitPD)->a[GCPtrPage >> X86_PD_SHIFT];
2357	# else
2358	const X86PDEPAE PdeDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[GCPtrPage >> X86_PD_PAE_SHIFT];
2359	# endif
2360	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
2361	{
2362	if (!PdeDst.n.u1Present)
2363	/** r=bird: This guy will set the A bit on the PDE, probably harmless. */
2364	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, GCPtrPage);
2365	else
2366	{
2367	/** @note We used to sync PGM_SYNC_NR_PAGES pages, which triggered assertions in CSAM, because
2368	* R/W attributes of nearby pages were reset. Not sure how that could happen. Anyway, it
2369	* makes no sense to prefetch more than one page.
2370	*/
2371	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, 1, 0);
2372	if (VBOX_SUCCESS(rc))
2373	rc = VINF_SUCCESS;
2374	}
2375	}
2376	}
2377	return rc;
2378
2379	#else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
2380
2381	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_SHW_TYPE, PGM_GST_TYPE));
2382	return VERR_INTERNAL_ERROR;
2383	#endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
2384	}
2385
2386
2387
2388
2389	/**
2390	* Syncs a page during a PGMVerifyAccess() call.
2391	*
2392	* @returns VBox status code (informational included).
2393	* @param GCPtrPage The address of the page to sync.
2394	* @param fPage The effective guest page flags.
2395	* @param uErr The trap error code.
2396	*/
2397	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fPage, unsigned uErr)
2398	{
2399	LogFlow(("VerifyAccessSyncPage: GCPtrPage=%VGv fPage=%#x uErr=%#x\n", GCPtrPage, fPage, uErr));
2400
2401	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) && PGM_SHW_TYPE != PGM_TYPE_AMD64
2402
2403	# if PGM_SHW_TYPE != PGM_TYPE_32BIT && PGM_SHW_TYPE != PGM_TYPE_PAE
2404	# error "Invalid shadow mode for 32-bit guest mode!"
2405	# endif
2406
2407	#ifndef IN_RING0
2408	if (!(fPage & X86_PTE_US))
2409	{
2410	/*
2411	* Mark this page as safe.
2412	*/
2413	/** @todo not correct for pages that contain both code and data!! */
2414	Log(("CSAMMarkPage %VGv; scanned=%d\n", GCPtrPage, true));
2415	CSAMMarkPage(pVM, (RTGCPTR)GCPtrPage, true);
2416	}
2417	#endif
2418	/*
2419	* Get guest PD and index.
2420	*/
2421	unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
2422	PVBOXPD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
2423	int rc = VINF_SUCCESS;
2424
2425	/*
2426	* First check if the shadow pd is present.
2427	*/
2428	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2429	PX86PDE pPdeDst = &pVM->pgm.s.CTXMID(p,32BitPD)->a[GCPtrPage >> X86_PD_SHIFT];
2430	# else
2431	PX86PDEPAE pPdeDst = &pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[GCPtrPage >> X86_PD_PAE_SHIFT];
2432	# endif
2433	if (!pPdeDst->n.u1Present)
2434	{
2435	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, GCPtrPage);
2436	AssertRC(rc);
2437	if (rc != VINF_SUCCESS)
2438	return rc;
2439	}
2440
2441	# if PGM_WITH_PAGING(PGM_GST_TYPE)
2442	/* Check for dirty bit fault */
2443	rc = PGM_BTH_NAME(CheckPageFault)(pVM, uErr, pPdeDst, &pPDSrc->a[iPDSrc], GCPtrPage);
2444	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
2445	Log(("PGMVerifyAccess: success (dirty)\n"));
2446	else
2447	{
2448	VBOXPDE PdeSrc = pPDSrc->a[iPDSrc];
2449	#else
2450	{
2451	VBOXPDE PdeSrc;
2452	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
2453	PdeSrc.n.u1Present = 1;
2454	PdeSrc.n.u1Write = 1;
2455	PdeSrc.n.u1Accessed = 1;
2456	PdeSrc.n.u1User = 1;
2457
2458	#endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
2459	Assert(rc != VINF_EM_RAW_GUEST_TRAP);
2460	if (uErr & X86_TRAP_PF_US)
2461	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncUser);
2462	else /* supervisor */
2463	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncSupervisor);
2464
2465	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, 1, 0);
2466	if (VBOX_SUCCESS(rc))
2467	{
2468	/* Page was successfully synced */
2469	Log2(("PGMVerifyAccess: success (sync)\n"));
2470	rc = VINF_SUCCESS;
2471	}
2472	else
2473	{
2474	Log(("PGMVerifyAccess: access violation for %VGv rc=%d\n", GCPtrPage, rc));
2475	return VINF_EM_RAW_GUEST_TRAP;
2476	}
2477	}
2478	return rc;
2479
2480	#else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
2481
2482	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
2483	return VERR_INTERNAL_ERROR;
2484	#endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
2485	}
2486
2487
2488	#if PGM_GST_TYPE == PGM_TYPE_32BIT
2489	# if PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE
2490	/**
2491	* Figures out which kind of shadow page this guest PDE warrants.
2492	*
2493	* @returns Shadow page kind.
2494	* @param pPdeSrc The guest PDE in question.
2495	* @param cr4 The current guest cr4 value.
2496	*/
2497	DECLINLINE(PGMPOOLKIND) PGM_BTH_NAME(CalcPageKind)(const VBOXPDE *pPdeSrc, uint32_t cr4)
2498	{
2499	if (!pPdeSrc->n.u1Size \|\| !(cr4 & X86_CR4_PSE))
2500	return BTH_PGMPOOLKIND_PT_FOR_PT;
2501	//switch (pPdeSrc->u & (X86_PDE4M_RW \| X86_PDE4M_US /\| X86_PDE4M_PAE_NX/))
2502	//{
2503	// case 0:
2504	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RO;
2505	// case X86_PDE4M_RW:
2506	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW;
2507	// case X86_PDE4M_US:
2508	// return BTH_PGMPOOLKIND_PT_FOR_BIG_US;
2509	// case X86_PDE4M_RW \| X86_PDE4M_US:
2510	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_US;
2511	# if 0
2512	// case X86_PDE4M_PAE_NX:
2513	// return BTH_PGMPOOLKIND_PT_FOR_BIG_NX;
2514	// case X86_PDE4M_RW \| X86_PDE4M_PAE_NX:
2515	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_NX;
2516	// case X86_PDE4M_US \| X86_PDE4M_PAE_NX:
2517	// return BTH_PGMPOOLKIND_PT_FOR_BIG_US_NX;
2518	// case X86_PDE4M_RW \| X86_PDE4M_US \| X86_PDE4M_PAE_NX:
2519	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_US_NX;
2520	# endif
2521	return BTH_PGMPOOLKIND_PT_FOR_BIG;
2522	//}
2523	}
2524	# endif
2525	#endif
2526
2527	#undef MY_STAM_COUNTER_INC
2528	#define MY_STAM_COUNTER_INC(a) do { } while (0)
2529
2530
2531	/**
2532	* Syncs the paging hierarchy starting at CR3.
2533	*
2534	* @returns VBox status code, no specials.
2535	* @param pVM The virtual machine.
2536	* @param cr0 Guest context CR0 register
2537	* @param cr3 Guest context CR3 register
2538	* @param cr4 Guest context CR4 register
2539	* @param fGlobal Including global page directories or not
2540	*/
2541	PGM_BTH_DECL(int, SyncCR3)(PVM pVM, uint32_t cr0, uint32_t cr3, uint32_t cr4, bool fGlobal)
2542	{
2543	#if PGM_GST_TYPE == PGM_TYPE_32BIT
2544	# if PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE
2545	if (VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3))
2546	fGlobal = true; /* Change this CR3 reload to be a global one. */
2547	# endif
2548	#endif
2549
2550	/*
2551	* Update page access handlers.
2552	* The virtual are always flushed, while the physical are only on demand.
2553	* WARNING: We are incorrectly not doing global flushing on Virtual Handler updates. We'll
2554	* have to look into that later because it will have a bad influence on the performance.
2555	* @note SvL: There's no need for that. Just invalidate the virtual range(s).
2556	* bird: Yes, but that won't work for aliases.
2557	*/
2558	/** @todo this MUST go away. See #1557. */
2559	STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat,SyncCR3Handlers), h);
2560	PGM_GST_NAME(HandlerVirtualUpdate)(pVM, cr4);
2561	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncCR3Handlers), h);
2562
2563	#ifdef PGMPOOL_WITH_MONITORING
2564	/*
2565	* When monitoring shadowed pages, we reset the modification counters on CR3 sync.
2566	* Occationally we will have to clear all the shadow page tables because we wanted
2567	* to monitor a page which was mapped by too many shadowed page tables. This operation
2568	* sometimes refered to as a 'lightweight flush'.
2569	*/
2570	if (!(pVM->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL))
2571	pgmPoolMonitorModifiedClearAll(pVM);
2572	else
2573	{
2574	# ifdef IN_RING3
2575	pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_CLEAR_PGM_POOL;
2576	pgmPoolClearAll(pVM);
2577	# else
2578	LogFlow(("SyncCR3: PGM_SYNC_CLEAR_PGM_POOL is set -> VINF_PGM_SYNC_CR3\n"));
2579	return VINF_PGM_SYNC_CR3;
2580	# endif
2581	}
2582	#endif
2583
2584	Assert(fGlobal \|\| (cr4 & X86_CR4_PGE));
2585	MY_STAM_COUNTER_INC(fGlobal ? &pVM->pgm.s.CTXMID(Stat,SyncCR3Global) : &pVM->pgm.s.CTXMID(Stat,SyncCR3NotGlobal));
2586
2587	#if PGM_GST_TYPE == PGM_TYPE_32BIT
2588	# if PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE
2589	/*
2590	* Get page directory addresses.
2591	*/
2592	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2593	PX86PDE pPDEDst = &pVM->pgm.s.CTXMID(p,32BitPD)->a[0];
2594	# else
2595	PX86PDEPAE pPDEDst = &pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[0];
2596	# endif
2597	PVBOXPD pPDSrc = pVM->pgm.s.CTXSUFF(pGuestPD);
2598
2599	Assert(pPDSrc);
2600	#ifndef IN_GC
2601	Assert(MMPhysGCPhys2HCVirt(pVM, (RTGCPHYS)(cr3 & X86_CR3_PAGE_MASK), sizeof(*pPDSrc)) == pPDSrc);
2602	#endif
2603
2604	/*
2605	* Iterate the page directory.
2606	*/
2607	PPGMMAPPING pMapping;
2608	unsigned iPdNoMapping;
2609	const bool fRawR0Enabled = EMIsRawRing0Enabled(pVM);
2610	PPGMPOOL pPool = pVM->pgm.s.CTXSUFF(pPool);
2611
2612	/* Only check mappings if they are supposed to be put into the shadow page table. */
2613	if (pgmMapAreMappingsEnabled(&pVM->pgm.s))
2614	{
2615	pMapping = pVM->pgm.s.CTXALLSUFF(pMappings);
2616	iPdNoMapping = (pMapping) ? pMapping->GCPtr >> PGDIR_SHIFT : ~0U;
2617	}
2618	else
2619	{
2620	pMapping = 0;
2621	iPdNoMapping = ~0U;
2622	}
2623
2624	for (unsigned iPD = 0; iPD < ELEMENTS(pPDSrc->a); iPD++)
2625	{
2626	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2627	Assert(&pVM->pgm.s.CTXMID(p,32BitPD)->a[iPD] == pPDEDst);
2628	# else
2629	Assert(&pVM->pgm.s.CTXMID(ap,PaePDs)[iPD * 2 / 512]->a[iPD * 2 % 512] == pPDEDst);
2630	# endif
2631	register VBOXPDE PdeSrc = pPDSrc->a[iPD];
2632	if ( PdeSrc.n.u1Present
2633	&& (PdeSrc.n.u1User \|\| fRawR0Enabled))
2634	{
2635	/*
2636	* Check for conflicts with GC mappings.
2637	*/
2638	if (iPD == iPdNoMapping)
2639	{
2640	if (pVM->pgm.s.fMappingsFixed)
2641	{
2642	/* It's fixed, just skip the mapping. */
2643	const unsigned cPTs = pMapping->cPTs;
2644	iPD += cPTs - 1;
2645	pPDEDst += cPTs + (PGM_SHW_TYPE != PGM_TYPE_32BIT) * cPTs;
2646	pMapping = pMapping->CTXALLSUFF(pNext);
2647	iPdNoMapping = pMapping ? pMapping->GCPtr >> PGDIR_SHIFT : ~0U;
2648	continue;
2649	}
2650
2651	#ifdef IN_RING3
2652	int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, iPD);
2653	if (VBOX_FAILURE(rc))
2654	return rc;
2655
2656	/*
2657	* Update iPdNoMapping and pMapping.
2658	*/
2659	pMapping = pVM->pgm.s.pMappingsR3;
2660	while (pMapping && pMapping->GCPtr < (iPD << PGDIR_SHIFT))
2661	pMapping = pMapping->pNextR3;
2662	iPdNoMapping = pMapping ? pMapping->GCPtr >> PGDIR_SHIFT : ~0U;
2663	#else
2664	LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
2665	return VINF_PGM_SYNC_CR3;
2666	#endif
2667	}
2668
2669	/*
2670	* Sync page directory entry.
2671	*
2672	* The current approach is to allocated the page table but to set
2673	* the entry to not-present and postpone the page table synching till
2674	* it's actually used.
2675	*/
2676	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2677	const unsigned iPdShw = iPD; NOREF(iPdShw);
2678	# else
2679	for (unsigned i = 0, iPdShw = iPD * 2; i < 2; i++, iPdShw++) /* pray that the compiler unrolls this */
2680	# endif
2681	{
2682	SHWPDE PdeDst = *pPDEDst;
2683	if (PdeDst.n.u1Present)
2684	{
2685	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
2686	RTGCPHYS GCPhys;
2687	if ( !PdeSrc.b.u1Size
2688	\|\| !(cr4 & X86_CR4_PSE))
2689	{
2690	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
2691	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2692	GCPhys \|= i * (PAGE_SIZE / 2);
2693	# endif
2694	}
2695	else
2696	{
2697	GCPhys = PdeSrc.u & GST_PDE4M_PG_MASK;
2698	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2699	GCPhys \|= i * X86_PAGE_2M_SIZE;
2700	# endif
2701	}
2702
2703	if ( pShwPage->GCPhys == GCPhys
2704	&& pShwPage->enmKind == PGM_BTH_NAME(CalcPageKind)(&PdeSrc, cr4)
2705	&& ( pShwPage->fCached
2706	\|\| ( !fGlobal
2707	&& ( false
2708	# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
2709	\|\| ( (PdeSrc.u & (X86_PDE4M_PS \| X86_PDE4M_G)) == (X86_PDE4M_PS \| X86_PDE4M_G)
2710	&& (cr4 & (X86_CR4_PGE \| X86_CR4_PSE)) == (X86_CR4_PGE \| X86_CR4_PSE)) /* global 2/4MB page. */
2711	\|\| ( !pShwPage->fSeenNonGlobal
2712	&& (cr4 & X86_CR4_PGE))
2713	# endif
2714	)
2715	)
2716	)
2717	&& ( (PdeSrc.u & (X86_PDE_US \| X86_PDE_RW)) == (PdeDst.u & (X86_PDE_US \| X86_PDE_RW))
2718	\|\| ( (cr4 & X86_CR4_PSE)
2719	&& ((PdeSrc.u & (X86_PDE_US \| X86_PDE4M_PS \| X86_PDE4M_D)) \| PGM_PDFLAGS_TRACK_DIRTY)
2720	== ((PdeDst.u & (X86_PDE_US \| X86_PDE_RW \| PGM_PDFLAGS_TRACK_DIRTY)) \| X86_PDE4M_PS))
2721	)
2722	)
2723	{
2724	# ifdef VBOX_WITH_STATISTICS
2725	if ( !fGlobal
2726	&& (PdeSrc.u & (X86_PDE4M_PS \| X86_PDE4M_G)) == (X86_PDE4M_PS \| X86_PDE4M_G)
2727	&& (cr4 & (X86_CR4_PGE \| X86_CR4_PSE)) == (X86_CR4_PGE \| X86_CR4_PSE))
2728	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstSkippedGlobalPD));
2729	else if (!fGlobal && !pShwPage->fSeenNonGlobal && (cr4 & X86_CR4_PGE))
2730	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstSkippedGlobalPT));
2731	else
2732	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstCacheHit));
2733	# endif /* VBOX_WITH_STATISTICS */
2734	/** @todo a replacement strategy isn't really needed unless we're using a very small pool < 512 pages.
2735	* The whole ageing stuff should be put in yet another set of #ifdefs. For now, let's just skip it. */
2736	//# ifdef PGMPOOL_WITH_CACHE
2737	// pgmPoolCacheUsed(pPool, pShwPage);
2738	//# endif
2739	}
2740	else
2741	{
2742	pgmPoolFreeByPage(pPool, pShwPage, SHW_POOL_ROOT_IDX, iPdShw);
2743	pPDEDst->u = 0;
2744	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstFreed));
2745	}
2746	}
2747	else
2748	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstNotPresent));
2749	pPDEDst++;
2750	}
2751	}
2752	else if (iPD != iPdNoMapping)
2753	{
2754	/*
2755	* Check if there is any page directory to mark not present here.
2756	*/
2757	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2758	const unsigned iPdShw = iPD; NOREF(iPdShw);
2759	# else
2760	for (unsigned i = 0, iPdShw = iPD * 2; i < 2; i++, iPdShw++) /* pray that the compiler unrolls this */
2761	# endif
2762	{
2763	if (pPDEDst->n.u1Present)
2764	{
2765	pgmPoolFreeByPage(pPool, pgmPoolGetPage(pPool, pPDEDst->u & SHW_PDE_PG_MASK), SHW_POOL_ROOT_IDX, iPdShw);
2766	pPDEDst->u = 0;
2767	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstFreedSrcNP));
2768	}
2769	pPDEDst++;
2770	}
2771	}
2772	else
2773	{
2774	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
2775	const unsigned cPTs = pMapping->cPTs;
2776	if (pVM->pgm.s.fMappingsFixed)
2777	{
2778	/* It's fixed, just skip the mapping. */
2779	pMapping = pMapping->CTXALLSUFF(pNext);
2780	iPdNoMapping = pMapping ? pMapping->GCPtr >> PGDIR_SHIFT : ~0U;
2781	}
2782	else
2783	{
2784	/*
2785	* Check for conflicts for subsequent pagetables
2786	* and advance to the next mapping.
2787	*/
2788	iPdNoMapping = ~0U;
2789	unsigned iPT = cPTs;
2790	while (iPT-- > 1)
2791	{
2792	if ( pPDSrc->a[iPD + iPT].n.u1Present
2793	&& (pPDSrc->a[iPD + iPT].n.u1User \|\| fRawR0Enabled))
2794	{
2795	# ifdef IN_RING3
2796	int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, iPD);
2797	if (VBOX_FAILURE(rc))
2798	return rc;
2799
2800	/*
2801	* Update iPdNoMapping and pMapping.
2802	*/
2803	pMapping = pVM->pgm.s.CTXALLSUFF(pMappings);
2804	while (pMapping && pMapping->GCPtr < (iPD << PGDIR_SHIFT))
2805	pMapping = pMapping->CTXALLSUFF(pNext);
2806	iPdNoMapping = pMapping ? pMapping->GCPtr >> PGDIR_SHIFT : ~0U;
2807	break;
2808	# else
2809	LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
2810	return VINF_PGM_SYNC_CR3;
2811	# endif
2812	}
2813	}
2814	if (iPdNoMapping == ~0U && pMapping)
2815	{
2816	pMapping = pMapping->CTXALLSUFF(pNext);
2817	if (pMapping)
2818	iPdNoMapping = pMapping->GCPtr >> PGDIR_SHIFT;
2819	}
2820	}
2821	/* advance. */
2822	iPD += cPTs - 1;
2823	pPDEDst += cPTs + (PGM_SHW_TYPE != PGM_TYPE_32BIT) * cPTs;
2824	}
2825
2826	} /* for iPD */
2827	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2828	# error "Guest 32-bit mode and shadow AMD64 mode doesn't add up!"
2829	# endif
2830
2831	return VINF_SUCCESS;
2832
2833	#elif PGM_GST_TYPE == PGM_TYPE_PAE
2834	# if PGM_SHW_TYPE == PGM_TYPE_PAE
2835	//# error not implemented
2836	return VERR_INTERNAL_ERROR;
2837
2838	# else /* PGM_SHW_TYPE != PGM_TYPE_AMD64 */
2839	# error "Guest PAE mode, but not the shadow mode ; 32bit - maybe, but amd64 no."
2840	# endif /* PGM_SHW_TYPE != PGM_TYPE_AMD64 */
2841
2842	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
2843	# if PGM_SHW_TYPE == PGM_TYPE_AMD64
2844	//# error not implemented
2845	return VERR_INTERNAL_ERROR;
2846
2847	# else /* PGM_SHW_TYPE != PGM_TYPE_AMD64 */
2848	# error "Guest AMD64 mode, but not the shadow mode - that can't be right!"
2849	# endif /* PGM_SHW_TYPE != PGM_TYPE_AMD64 */
2850
2851	#else /* guest real and protected mode */
2852
2853	return VINF_SUCCESS;
2854	#endif
2855	}
2856
2857
2858
2859
2860	#ifdef VBOX_STRICT
2861	#ifdef IN_GC
2862	# undef AssertMsgFailed
2863	# define AssertMsgFailed Log
2864	#endif
2865	#ifdef IN_RING3
2866	# include <VBox/dbgf.h>
2867
2868	/**
2869	* Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
2870	*
2871	* @returns VBox status code (VINF_SUCCESS).
2872	* @param pVM The VM handle.
2873	* @param cr3 The root of the hierarchy.
2874	* @param crr The cr4, only PAE and PSE is currently used.
2875	* @param fLongMode Set if long mode, false if not long mode.
2876	* @param cMaxDepth Number of levels to dump.
2877	* @param pHlp Pointer to the output functions.
2878	*/
2879	__BEGIN_DECLS
2880	PGMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint32_t cr3, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp);
2881	__END_DECLS
2882
2883	#endif
2884
2885	/**
2886	* Checks that the shadow page table is in sync with the guest one.
2887	*
2888	* @returns The number of errors.
2889	* @param pVM The virtual machine.
2890	* @param cr3 Guest context CR3 register
2891	* @param cr4 Guest context CR4 register
2892	* @param GCPtr Where to start. Defaults to 0.
2893	* @param cb How much to check. Defaults to everything.
2894	*/
2895	PGM_BTH_DECL(unsigned, AssertCR3)(PVM pVM, uint32_t cr3, uint32_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb)
2896	{
2897	unsigned cErrors = 0;
2898
2899	#if PGM_GST_TYPE == PGM_TYPE_32BIT
2900
2901	# if PGM_SHW_TYPE != PGM_TYPE_32BIT && PGM_SHW_TYPE != PGM_TYPE_PAE
2902	# error "Invalid shadow mode for 32-bit guest paging."
2903	# endif
2904
2905	PPGM pPGM = &pVM->pgm.s;
2906	RTHCPHYS HCPhysShw; /* page address derived from the shadow page tables. */
2907	RTGCPHYS GCPhysGst; /* page address derived from the guest page tables. */
2908	RTHCPHYS HCPhys; /* general usage. */
2909	int rc;
2910
2911	/*
2912	* Check that the Guest CR3 and all it's mappings are correct.
2913	*/
2914	AssertMsgReturn(pPGM->GCPhysCR3 == (cr3 & X86_CR3_PAGE_MASK),
2915	("Invalid GCPhysCR3=%VGp cr3=%VGp\n", pPGM->GCPhysCR3, (RTGCPHYS)cr3),
2916	false);
2917	rc = PGMShwGetPage(pVM, pPGM->pGuestPDGC, NULL, &HCPhysShw);
2918	AssertRCReturn(rc, 1);
2919	HCPhys = NIL_RTHCPHYS;
2920	rc = pgmRamGCPhys2HCPhys(pPGM, cr3 & X86_CR3_PAGE_MASK, &HCPhys);
2921	AssertMsgReturn(HCPhys == HCPhysShw, ("HCPhys=%VHp HCPhyswShw=%VHp (cr3)\n", HCPhys, HCPhysShw), false);
2922	# ifdef IN_RING3
2923	RTGCPHYS GCPhys;
2924	rc = PGMR3DbgHCPtr2GCPhys(pVM, pPGM->pGuestPDHC, &GCPhys);
2925	AssertRCReturn(rc, 1);
2926	AssertMsgReturn((cr3 & X86_CR3_PAGE_MASK) == GCPhys, ("GCPhys=%VGp cr3=%VGp\n", GCPhys, (RTGCPHYS)cr3), false);
2927	# endif
2928	const X86PD *pPDSrc = CTXSUFF(pPGM->pGuestPD);
2929
2930	/*
2931	* Get and check the Shadow CR3.
2932	*/
2933	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2934	const X86PD *pPDDst = pPGM->CTXMID(p,32BitPD);
2935	unsigned cPDEs = ELEMENTS(pPDDst->a);
2936	# else
2937	const X86PDPAE pPDDst = pPGM->CTXMID(ap,PaePDs[0]); / use it as a 2048 entry PD */
2938	unsigned cPDEs = ELEMENTS(pPDDst->a) * ELEMENTS(pPGM->apHCPaePDs);
2939	# endif
2940	if (cb != ~(RTGCUINTPTR)0)
2941	cPDEs = RT_MIN(cb >> SHW_PD_SHIFT, 1);
2942
2943	/** @todo call the other two PGMAssert() functions. /
2944
2945	/*
2946	* Iterate the shadow page directory.
2947	*/
2948	GCPtr = (GCPtr >> SHW_PD_SHIFT) << SHW_PD_SHIFT;
2949	unsigned iPDDst = GCPtr >> SHW_PD_SHIFT;
2950	cPDEs += iPDDst;
2951	for (;
2952	iPDDst < cPDEs;
2953	iPDDst++, GCPtr += _4G / cPDEs)
2954	{
2955	const SHWPDE PdeDst = pPDDst->a[iPDDst];
2956	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
2957	{
2958	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
2959	if ((PdeDst.u & X86_PDE_AVL_MASK) != PGM_PDFLAGS_MAPPING)
2960	{
2961	AssertMsgFailed(("Mapping shall only have PGM_PDFLAGS_MAPPING set! PdeDst.u=%#RX64\n", (uint64_t)PdeDst.u));
2962	cErrors++;
2963	continue;
2964	}
2965	}
2966	else if ( (PdeDst.u & X86_PDE_P)
2967	\|\| ((PdeDst.u & (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY)) == (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY))
2968	)
2969	{
2970	HCPhysShw = PdeDst.u & SHW_PDE_PG_MASK;
2971	PPGMPOOLPAGE pPoolPage = pgmPoolGetPageByHCPhys(pVM, HCPhysShw);
2972	if (!pPoolPage)
2973	{
2974	AssertMsgFailed(("Invalid page table address %VGp at %VGv! PdeDst=%#RX64\n",
2975	HCPhysShw, GCPtr, (uint64_t)PdeDst.u));
2976	cErrors++;
2977	continue;
2978	}
2979	const SHWPT pPTDst = (const SHWPT )PGMPOOL_PAGE_2_PTR(pVM, pPoolPage);
2980
2981	if (PdeDst.u & (X86_PDE4M_PWT \| X86_PDE4M_PCD))
2982	{
2983	AssertMsgFailed(("PDE flags PWT and/or PCD is set at %VGv! These flags are not virtualized! PdeDst=%#RX64\n",
2984	GCPtr, (uint64_t)PdeDst.u));
2985	cErrors++;
2986	}
2987
2988	if (PdeDst.u & (X86_PDE4M_G \| X86_PDE4M_D))
2989	{
2990	AssertMsgFailed(("4K PDE reserved flags at %VGv! PdeDst=%#RX64\n",
2991	GCPtr, (uint64_t)PdeDst.u));
2992	cErrors++;
2993	}
2994
2995	const X86PDE PdeSrc = pPDSrc->a[iPDDst >> (GST_PD_SHIFT - SHW_PD_SHIFT)];
2996	if (!PdeSrc.n.u1Present)
2997	{
2998	AssertMsgFailed(("Guest PDE at %VGv is not present! PdeDst=%#RX64 PdeSrc=%#RX64\n",
2999	GCPtr, (uint64_t)PdeDst.u, (uint64_t)PdeSrc.u));
3000	cErrors++;
3001	continue;
3002	}
3003
3004	if ( !PdeSrc.b.u1Size
3005	\|\| !(cr4 & X86_CR4_PSE))
3006	{
3007	GCPhysGst = PdeSrc.u & GST_PDE_PG_MASK;
3008	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3009	GCPhysGst \|= (iPDDst & 1) * (PAGE_SIZE / 2);
3010	# endif
3011	}
3012	else
3013	{
3014	if (PdeSrc.u & X86_PDE4M_PG_HIGH_MASK)
3015	{
3016	AssertMsgFailed(("Guest PDE at %VGv is using PSE36 or similar! PdeSrc=%#RX64\n",
3017	GCPtr, (uint64_t)PdeSrc.u));
3018	cErrors++;
3019	continue;
3020	}
3021	GCPhysGst = PdeSrc.u & GST_PDE4M_PG_MASK;
3022	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3023	GCPhysGst \|= GCPtr & BIT(X86_PAGE_2M_SHIFT);
3024	# endif
3025	}
3026
3027	if ( pPoolPage->enmKind
3028	!= (!PdeSrc.b.u1Size \|\| !(cr4 & X86_CR4_PSE) ? BTH_PGMPOOLKIND_PT_FOR_PT : BTH_PGMPOOLKIND_PT_FOR_BIG))
3029	{
3030	AssertMsgFailed(("Invalid shadow page table kind %d at %VGv! PdeSrc=%#RX64\n",
3031	pPoolPage->enmKind, GCPtr, (uint64_t)PdeSrc.u));
3032	cErrors++;
3033	}
3034
3035	PPGMPAGE pPhysPage = pgmPhysGetPage(pPGM, GCPhysGst);
3036	if (!pPhysPage)
3037	{
3038	AssertMsgFailed(("Cannot find guest physical address %VGp in the PDE at %VGv! PdeSrc=%#RX64\n",
3039	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3040	cErrors++;
3041	continue;
3042	}
3043
3044	if (GCPhysGst != pPoolPage->GCPhys)
3045	{
3046	AssertMsgFailed(("GCPhysGst=%VGp != pPage->GCPhys=%VGp at %VGv\n",
3047	GCPhysGst, pPoolPage->GCPhys, GCPtr));
3048	cErrors++;
3049	continue;
3050	}
3051
3052	if ( !PdeSrc.b.u1Size
3053	\|\| !(cr4 & X86_CR4_PSE))
3054	{
3055	/*
3056	* Page Table.
3057	*/
3058	const GSTPT *pPTSrc;
3059	rc = PGM_GCPHYS_2_PTR(pVM, GCPhysGst & ~(RTGCPHYS)(PAGE_SIZE - 1), &pPTSrc);
3060	if (VBOX_FAILURE(rc))
3061	{
3062	AssertMsgFailed(("Cannot map/convert guest physical address %VGp in the PDE at %VGv! PdeSrc=%#RX64\n",
3063	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3064	cErrors++;
3065	continue;
3066	}
3067	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/))
3068	!= (PdeDst.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/)))
3069	{
3070	/// @todo We get here a lot on out-of-sync CR3 entries. The access handler should zap them to avoid false alarms here!
3071	// (This problem will go away when/if we shadow multiple CR3s.)
3072	AssertMsgFailed(("4K PDE flags mismatch at %VGv! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3073	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3074	cErrors++;
3075	continue;
3076	}
3077	if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
3078	{
3079	AssertMsgFailed(("4K PDEs cannot have PGM_PDFLAGS_TRACK_DIRTY set! GCPtr=%VGv PdeDst=%#RX64\n",
3080	GCPtr, (uint64_t)PdeDst.u));
3081	cErrors++;
3082	continue;
3083	}
3084
3085	/* iterate the page table. */
3086	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3087	const unsigned offPTSrc = 0;
3088	# else
3089	const unsigned offPTSrc = ((GCPtr >> SHW_PD_SHIFT) & 1) * 512;
3090	# endif
3091	for (unsigned iPT = 0, off = 0;
3092	iPT < ELEMENTS(pPTDst->a);
3093	iPT++, off += PAGE_SIZE)
3094	{
3095	const SHWPTE PteDst = pPTDst->a[iPT];
3096
3097	/* skip not-present entries. */
3098	if (!(PteDst.u & (X86_PTE_P \| PGM_PTFLAGS_TRACK_DIRTY))) /** @todo deal with ALL handlers and CSAM !P pages! */
3099	continue;
3100	Assert(PteDst.n.u1Present);
3101
3102	const GSTPTE PteSrc = pPTSrc->a[iPT + offPTSrc];
3103	if (!PteSrc.n.u1Present)
3104	{
3105	#ifdef IN_RING3
3106	PGMAssertHandlerAndFlagsInSync(pVM);
3107	PGMR3DumpHierarchyGC(pVM, cr3, cr4, (PdeSrc.u & GST_PDE_PG_MASK));
3108	#endif
3109	AssertMsgFailed(("Out of sync (!P) PTE at %VGv! PteSrc=%#RX64 PteDst=%#RX64 pPTSrc=%VGv iPTSrc=%x PdeSrc=%x physpte=%VGp\n",
3110	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u, pPTSrc, iPT + offPTSrc, PdeSrc.au32[0],
3111	(PdeSrc.u & GST_PDE_PG_MASK) + (iPT + offPTSrc)*sizeof(PteSrc)));
3112	cErrors++;
3113	continue;
3114	}
3115
3116	uint64_t fIgnoreFlags = GST_PTE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_G \| X86_PTE_D \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT;
3117	# if 1 /** @todo sync accessed bit properly... */
3118	fIgnoreFlags \|= X86_PTE_A;
3119	# endif
3120
3121	/* match the physical addresses */
3122	HCPhysShw = PteDst.u & SHW_PTE_PG_MASK;
3123	GCPhysGst = PteSrc.u & GST_PTE_PG_MASK;
3124
3125	# ifdef IN_RING3
3126	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
3127	if (VBOX_FAILURE(rc))
3128	{
3129	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
3130	{
3131	AssertMsgFailed(("Cannot find guest physical address %VGp at %VGv! PteSrc=%#RX64 PteDst=%#RX64\n",
3132	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3133	cErrors++;
3134	continue;
3135	}
3136	}
3137	else if (HCPhysShw != (HCPhys & SHW_PTE_PG_MASK))
3138	{
3139	AssertMsgFailed(("Out of sync (phys) at %VGv! HCPhysShw=%VHp HCPhys=%VHp GCPhysGst=%VGp PteSrc=%#RX64 PteDst=%#RX64\n",
3140	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3141	cErrors++;
3142	continue;
3143	}
3144	# endif
3145
3146	pPhysPage = pgmPhysGetPage(pPGM, GCPhysGst);
3147	if (!pPhysPage)
3148	{
3149	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
3150	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
3151	{
3152	AssertMsgFailed(("Cannot find guest physical address %VGp at %VGv! PteSrc=%#RX64 PteDst=%#RX64\n",
3153	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3154	cErrors++;
3155	continue;
3156	}
3157	# endif
3158	if (PteDst.n.u1Write)
3159	{
3160	AssertMsgFailed(("Invalid guest page at %VGv is writable! GCPhysGst=%VGp PteSrc=%#RX64 PteDst=%#RX64\n",
3161	GCPtr + off, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3162	cErrors++;
3163	}
3164	fIgnoreFlags \|= X86_PTE_RW;
3165	}
3166	else if (HCPhysShw != (PGM_PAGE_GET_HCPHYS(pPhysPage) & SHW_PTE_PG_MASK))
3167	{
3168	AssertMsgFailed(("Out of sync (phys) at %VGv! HCPhysShw=%VHp HCPhys=%VHp GCPhysGst=%VGp PteSrc=%#RX64 PteDst=%#RX64\n",
3169	GCPtr + off, HCPhysShw, pPhysPage->HCPhys, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3170	cErrors++;
3171	continue;
3172	}
3173
3174	/* flags */
3175	if (pPhysPage->HCPhys & (MM_RAM_FLAGS_PHYSICAL_ALL \| MM_RAM_FLAGS_VIRTUAL_ALL \| MM_RAM_FLAGS_PHYSICAL_WRITE \| MM_RAM_FLAGS_VIRTUAL_WRITE)) /** @todo PAGE FLAGS */
3176	{
3177	if (pPhysPage->HCPhys & (MM_RAM_FLAGS_PHYSICAL_WRITE \| MM_RAM_FLAGS_VIRTUAL_WRITE)) /** @todo PAGE FLAGS */
3178	{
3179	if (PteDst.n.u1Write)
3180	{
3181	AssertMsgFailed(("WRITE access flagged at %VGv but the page is writable! HCPhys=%VGv PteSrc=%#RX64 PteDst=%#RX64\n",
3182	GCPtr + off, pPhysPage->HCPhys, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3183	cErrors++;
3184	continue;
3185	}
3186	fIgnoreFlags \|= X86_PTE_RW;
3187	}
3188	else
3189	{
3190	if (PteDst.n.u1Present)
3191	{
3192	AssertMsgFailed(("ALL access flagged at %VGv but the page is present! HCPhys=%VHp PteSrc=%#RX64 PteDst=%#RX64\n",
3193	GCPtr + off, pPhysPage->HCPhys, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3194	cErrors++;
3195	continue;
3196	}
3197	fIgnoreFlags \|= X86_PTE_P;
3198	}
3199	}
3200	else
3201	{
3202	if (!PteSrc.n.u1Dirty && PteSrc.n.u1Write)
3203	{
3204	if (PteDst.n.u1Write)
3205	{
3206	AssertMsgFailed(("!DIRTY page at %VGv is writable! PteSrc=%#RX64 PteDst=%#RX64\n",
3207	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3208	cErrors++;
3209	continue;
3210	}
3211	if (!(PteDst.u & PGM_PTFLAGS_TRACK_DIRTY))
3212	{
3213	AssertMsgFailed(("!DIRTY page at %VGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
3214	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3215	cErrors++;
3216	continue;
3217	}
3218	if (PteDst.n.u1Dirty)
3219	{
3220	AssertMsgFailed(("!DIRTY page at %VGv is marked DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
3221	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3222	cErrors++;
3223	}
3224	# if 0 /** @todo sync access bit properly... */
3225	if (PteDst.n.u1Accessed != PteSrc.n.u1Accessed)
3226	{
3227	AssertMsgFailed(("!DIRTY page at %VGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
3228	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3229	cErrors++;
3230	}
3231	fIgnoreFlags \|= X86_PTE_RW;
3232	# else
3233	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
3234	# endif
3235	}
3236	else if (PteDst.u & PGM_PTFLAGS_TRACK_DIRTY)
3237	{
3238	/* access bit emulation (not implemented). */
3239	if (PteSrc.n.u1Accessed \|\| PteDst.n.u1Present)
3240	{
3241	AssertMsgFailed(("PGM_PTFLAGS_TRACK_DIRTY set at %VGv but no accessed bit emulation! PteSrc=%#RX64 PteDst=%#RX64\n",
3242	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3243	cErrors++;
3244	continue;
3245	}
3246	if (!PteDst.n.u1Accessed)
3247	{
3248	AssertMsgFailed(("!ACCESSED page at %VGv is has the accessed bit set! PteSrc=%#RX64 PteDst=%#RX64\n",
3249	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3250	cErrors++;
3251	}
3252	fIgnoreFlags \|= X86_PTE_P;
3253	}
3254	# ifdef DEBUG_sandervl
3255	fIgnoreFlags \|= X86_PTE_D \| X86_PTE_A;
3256	# endif
3257	}
3258
3259	if ( (PteSrc.u & ~fIgnoreFlags) != (PteDst.u & ~fIgnoreFlags)
3260	&& (PteSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (PteDst.u & ~fIgnoreFlags)
3261	)
3262	{
3263	AssertMsgFailed(("Flags mismatch at %VGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PteSrc=%#RX64 PteDst=%#RX64\n",
3264	GCPtr + off, (uint64_t)PteSrc.u & ~fIgnoreFlags, (uint64_t)PteDst.u & ~fIgnoreFlags,
3265	fIgnoreFlags, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3266	cErrors++;
3267	continue;
3268	}
3269	} /* foreach PTE */
3270	}
3271	else
3272	{
3273	/*
3274	* Big Page.
3275	*/
3276	uint64_t fIgnoreFlags = X86_PDE_AVL_MASK \| X86_PDE_PAE_PG_MASK \| X86_PDE4M_G \| X86_PDE4M_D \| X86_PDE4M_PS \| X86_PDE4M_PWT \| X86_PDE4M_PCD;
3277	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
3278	{
3279	if (PdeDst.n.u1Write)
3280	{
3281	AssertMsgFailed(("!DIRTY page at %VGv is writable! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3282	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3283	cErrors++;
3284	continue;
3285	}
3286	if (!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY))
3287	{
3288	AssertMsgFailed(("!DIRTY page at %VGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
3289	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3290	cErrors++;
3291	continue;
3292	}
3293	# if 0 /** @todo sync access bit properly... */
3294	if (PdeDst.n.u1Accessed != PdeSrc.b.u1Accessed)
3295	{
3296	AssertMsgFailed(("!DIRTY page at %VGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
3297	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3298	cErrors++;
3299	}
3300	fIgnoreFlags \|= X86_PTE_RW;
3301	# else
3302	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
3303	# endif
3304	}
3305	else if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
3306	{
3307	/* access bit emulation (not implemented). */
3308	if (PdeSrc.b.u1Accessed \|\| PdeDst.n.u1Present)
3309	{
3310	AssertMsgFailed(("PGM_PDFLAGS_TRACK_DIRTY set at %VGv but no accessed bit emulation! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3311	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3312	cErrors++;
3313	continue;
3314	}
3315	if (!PdeDst.n.u1Accessed)
3316	{
3317	AssertMsgFailed(("!ACCESSED page at %VGv is has the accessed bit set! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3318	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3319	cErrors++;
3320	}
3321	fIgnoreFlags \|= X86_PTE_P;
3322	}
3323
3324	if ((PdeSrc.u & ~fIgnoreFlags) != (PdeDst.u & ~fIgnoreFlags))
3325	{
3326	AssertMsgFailed(("Flags mismatch (B) at %VGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PdeDst=%#RX64\n",
3327	GCPtr, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PdeDst.u & ~fIgnoreFlags,
3328	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3329	cErrors++;
3330	}
3331
3332	/* iterate the page table. */
3333	for (unsigned iPT = 0, off = 0;
3334	iPT < ELEMENTS(pPTDst->a);
3335	iPT++, off += PAGE_SIZE, GCPhysGst += PAGE_SIZE)
3336	{
3337	const SHWPTE PteDst = pPTDst->a[iPT];
3338
3339	if (PteDst.u & PGM_PTFLAGS_TRACK_DIRTY)
3340	{
3341	AssertMsgFailed(("The PTE at %VGv emulating a 2/4M page is marked TRACK_DIRTY! PdeSrc=%#RX64 PteDst=%#RX64\n",
3342	GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3343	cErrors++;
3344	}
3345
3346	/* skip not-present entries. */
3347	if (!PteDst.n.u1Present) /** @todo deal with ALL handlers and CSAM !P pages! */
3348	continue;
3349
3350	fIgnoreFlags = X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT;
3351
3352	/* match the physical addresses */
3353	HCPhysShw = PteDst.u & X86_PTE_PAE_PG_MASK;
3354
3355	# ifdef IN_RING3
3356	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
3357	if (VBOX_FAILURE(rc))
3358	{
3359	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
3360	{
3361	AssertMsgFailed(("Cannot find guest physical address %VGp at %VGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
3362	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3363	cErrors++;
3364	}
3365	}
3366	else if (HCPhysShw != (HCPhys & X86_PTE_PAE_PG_MASK))
3367	{
3368	AssertMsgFailed(("Out of sync (phys) at %VGv! HCPhysShw=%VHp HCPhys=%VHp GCPhysGst=%VGp PdeSrc=%#RX64 PteDst=%#RX64\n",
3369	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3370	cErrors++;
3371	continue;
3372	}
3373	# endif
3374
3375	pPhysPage = pgmPhysGetPage(pPGM, GCPhysGst);
3376	if (!pPhysPage)
3377	{
3378	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
3379	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
3380	{
3381	AssertMsgFailed(("Cannot find guest physical address %VGp at %VGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
3382	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3383	cErrors++;
3384	continue;
3385	}
3386	# endif
3387	if (PteDst.n.u1Write)
3388	{
3389	AssertMsgFailed(("Invalid guest page at %VGv is writable! GCPhysGst=%VGp PdeSrc=%#RX64 PteDst=%#RX64\n",
3390	GCPtr + off, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3391	cErrors++;
3392	}
3393	fIgnoreFlags \|= X86_PTE_RW;
3394	}
3395	else if (HCPhysShw != (pPhysPage->HCPhys & X86_PTE_PAE_PG_MASK))
3396	{
3397	AssertMsgFailed(("Out of sync (phys) at %VGv! HCPhysShw=%VHp HCPhys=%VHp GCPhysGst=%VGp PdeSrc=%#RX64 PteDst=%#RX64\n",
3398	GCPtr + off, HCPhysShw, pPhysPage->HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3399	cErrors++;
3400	continue;
3401	}
3402
3403	/* flags */
3404	if (pPhysPage->HCPhys & (MM_RAM_FLAGS_PHYSICAL_ALL \| MM_RAM_FLAGS_VIRTUAL_ALL \| MM_RAM_FLAGS_PHYSICAL_WRITE \| MM_RAM_FLAGS_VIRTUAL_WRITE)) /** @todo PAGE FLAGS */
3405	{
3406	if (pPhysPage->HCPhys & (MM_RAM_FLAGS_PHYSICAL_WRITE \| MM_RAM_FLAGS_VIRTUAL_WRITE)) /** @todo PAGE FLAGS */
3407	{
3408	if (!(pPhysPage->HCPhys & MM_RAM_FLAGS_PHYSICAL_TEMP_OFF)) /** @todo PAGE FLAGS */
3409	{
3410	if (PteDst.n.u1Write)
3411	{
3412	AssertMsgFailed(("WRITE access flagged at %VGv but the page is writable! HCPhys=%VGv PdeSrc=%#RX64 PteDst=%#RX64\n",
3413	GCPtr + off, pPhysPage->HCPhys, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3414	cErrors++;
3415	continue;
3416	}
3417	fIgnoreFlags \|= X86_PTE_RW;
3418	}
3419	}
3420	else
3421	{
3422	if (PteDst.n.u1Present)
3423	{
3424	AssertMsgFailed(("ALL access flagged at %VGv but the page is present! HCPhys=%VGv PdeSrc=%#RX64 PteDst=%#RX64\n",
3425	GCPtr + off, pPhysPage->HCPhys, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3426	cErrors++;
3427	continue;
3428	}
3429	fIgnoreFlags \|= X86_PTE_P;
3430	}
3431	}
3432
3433	if ( (PdeSrc.u & ~fIgnoreFlags) != (PteDst.u & ~fIgnoreFlags)
3434	&& (PdeSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (PteDst.u & ~fIgnoreFlags) /* lazy phys handler dereg. */
3435	)
3436	{
3437	AssertMsgFailed(("Flags mismatch (BT) at %VGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PteDst=%#RX64\n",
3438	GCPtr + off, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PteDst.u & ~fIgnoreFlags,
3439	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3440	cErrors++;
3441	continue;
3442	}
3443	} /* foreach PTE */
3444	}
3445	}
3446	/* not present */
3447
3448	} /* forearch PDE */
3449
3450	# ifdef DEBUG
3451	if (cErrors)
3452	LogFlow(("AssertCR3: cErrors=%d\n", cErrors));
3453	# endif
3454
3455	#elif PGM_GST_TYPE == PGM_TYPE_PAE
3456	//# error not implemented
3457
3458
3459	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
3460	//# error not implemented
3461
3462	/#else: guest real and protected mode /
3463	#endif
3464	return cErrors;
3465	}
3466	#endif /* VBOX_STRICT */
3467

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllBth.h@ 5393

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