PGMAllBth.h@ 56225

Last change on this file since 56225 was 56013, checked in by vboxsync, 10 years ago
PGM: Made the virtual handler callbacks return VBOXSTRICTRC and prepared for RC execution.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 210.3 KB

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1	/* $Id: PGMAllBth.h 56013 2015-05-21 17:04:14Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Shadow+Guest Paging Template - All context code.
4	*
5	* @remarks The nested page tables on AMD makes use of PGM_SHW_TYPE in
6	* {PGM_TYPE_AMD64, PGM_TYPE_PAE and PGM_TYPE_32BIT} and PGM_GST_TYPE
7	* set to PGM_TYPE_PROT. Half of the code in this file is not
8	* exercised with PGM_SHW_TYPE set to PGM_TYPE_NESTED.
9	*
10	* @remarks Extended page tables (intel) are built with PGM_GST_TYPE set to
11	* PGM_TYPE_PROT (and PGM_SHW_TYPE set to PGM_TYPE_EPT).
12	*
13	* @remarks This file is one big \#ifdef-orgy!
14	*
15	*/
16
17	/*
18	* Copyright (C) 2006-2015 Oracle Corporation
19	*
20	* This file is part of VirtualBox Open Source Edition (OSE), as
21	* available from http://www.virtualbox.org. This file is free software;
22	* you can redistribute it and/or modify it under the terms of the GNU
23	* General Public License (GPL) as published by the Free Software
24	* Foundation, in version 2 as it comes in the "COPYING" file of the
25	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
26	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
27	*/
28
29	#ifdef _MSC_VER
30	/** @todo we're generating unnecessary code in nested/ept shadow mode and for
31	* real/prot-guest+RC mode. */
32	# pragma warning(disable: 4505)
33	#endif
34
35	/*******************************************************************************
36	* Internal Functions *
37	*******************************************************************************/
38	RT_C_DECLS_BEGIN
39	PGM_BTH_DECL(int, Trap0eHandler)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken);
40	PGM_BTH_DECL(int, InvalidatePage)(PVMCPU pVCpu, RTGCPTR GCPtrPage);
41	static int PGM_BTH_NAME(SyncPage)(PVMCPU pVCpu, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr);
42	static int PGM_BTH_NAME(CheckDirtyPageFault)(PVMCPU pVCpu, uint32_t uErr, PSHWPDE pPdeDst, GSTPDE const *pPdeSrc, RTGCPTR GCPtrPage);
43	static int PGM_BTH_NAME(SyncPT)(PVMCPU pVCpu, unsigned iPD, PGSTPD pPDSrc, RTGCPTR GCPtrPage);
44	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
45	static void PGM_BTH_NAME(SyncPageWorker)(PVMCPU pVCpu, PSHWPTE pPteDst, GSTPDE PdeSrc, GSTPTE PteSrc, PPGMPOOLPAGE pShwPage, unsigned iPTDst);
46	# else
47	static void PGM_BTH_NAME(SyncPageWorker)(PVMCPU pVCpu, PSHWPTE pPteDst, RTGCPHYS GCPhysPage, PPGMPOOLPAGE pShwPage, unsigned iPTDst);
48	#endif
49	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVMCPU pVCpu, RTGCPTR Addr, unsigned fPage, unsigned uErr);
50	PGM_BTH_DECL(int, PrefetchPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage);
51	PGM_BTH_DECL(int, SyncCR3)(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
52	#ifdef VBOX_STRICT
53	PGM_BTH_DECL(unsigned, AssertCR3)(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr = 0, RTGCPTR cb = ~(RTGCPTR)0);
54	#endif
55	PGM_BTH_DECL(int, MapCR3)(PVMCPU pVCpu, RTGCPHYS GCPhysCR3);
56	PGM_BTH_DECL(int, UnmapCR3)(PVMCPU pVCpu);
57	RT_C_DECLS_END
58
59
60	/*
61	* Filter out some illegal combinations of guest and shadow paging, so we can
62	* remove redundant checks inside functions.
63	*/
64	#if PGM_GST_TYPE == PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
65	# error "Invalid combination; PAE guest implies PAE shadow"
66	#endif
67
68	#if (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
69	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT)
70	# error "Invalid combination; real or protected mode without paging implies 32 bits or PAE shadow paging."
71	#endif
72
73	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) \
74	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT)
75	# error "Invalid combination; 32 bits guest paging or PAE implies 32 bits or PAE shadow paging."
76	#endif
77
78	#if (PGM_GST_TYPE == PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT) \
79	\|\| (PGM_SHW_TYPE == PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PROT)
80	# error "Invalid combination; AMD64 guest implies AMD64 shadow and vice versa"
81	#endif
82
83	#ifndef IN_RING3
84
85	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
86	/**
87	* Deal with a guest page fault.
88	*
89	* @returns Strict VBox status code.
90	* @retval VINF_EM_RAW_GUEST_TRAP
91	* @retval VINF_EM_RAW_EMULATE_INSTR
92	*
93	* @param pVCpu The current CPU.
94	* @param pGstWalk The guest page table walk result.
95	* @param uErr The error code.
96	*/
97	PGM_BTH_DECL(VBOXSTRICTRC, Trap0eHandlerGuestFault)(PVMCPU pVCpu, PGSTPTWALK pGstWalk, RTGCUINT uErr)
98	{
99	# if !defined(PGM_WITHOUT_MAPPINGS) && (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE)
100	/*
101	* Check for write conflicts with our hypervisor mapping.
102	*
103	* If the guest happens to access a non-present page, where our hypervisor
104	* is currently mapped, then we'll create a #PF storm in the guest.
105	*/
106	if ( (uErr & (X86_TRAP_PF_P \| X86_TRAP_PF_RW)) == (X86_TRAP_PF_P \| X86_TRAP_PF_RW)
107	&& pgmMapAreMappingsEnabled(pVCpu->CTX_SUFF(pVM))
108	&& MMHyperIsInsideArea(pVCpu->CTX_SUFF(pVM), pGstWalk->Core.GCPtr))
109	{
110	/* Force a CR3 sync to check for conflicts and emulate the instruction. */
111	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
112	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2GuestTrap; });
113	return VINF_EM_RAW_EMULATE_INSTR;
114	}
115	# endif
116
117	/*
118	* Calc the error code for the guest trap.
119	*/
120	uint32_t uNewErr = GST_IS_NX_ACTIVE(pVCpu)
121	? uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US \| X86_TRAP_PF_ID)
122	: uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US);
123	if (pGstWalk->Core.fBadPhysAddr)
124	{
125	uNewErr \|= X86_TRAP_PF_RSVD \| X86_TRAP_PF_P;
126	Assert(!pGstWalk->Core.fNotPresent);
127	}
128	else if (!pGstWalk->Core.fNotPresent)
129	uNewErr \|= X86_TRAP_PF_P;
130	TRPMSetErrorCode(pVCpu, uNewErr);
131
132	LogFlow(("Guest trap; cr2=%RGv uErr=%RGv lvl=%d\n", pGstWalk->Core.GCPtr, uErr, pGstWalk->Core.uLevel));
133	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2GuestTrap; });
134	return VINF_EM_RAW_GUEST_TRAP;
135	}
136	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
137
138
139	/**
140	* Deal with a guest page fault.
141	*
142	* The caller has taken the PGM lock.
143	*
144	* @returns Strict VBox status code.
145	*
146	* @param pVCpu The current CPU.
147	* @param uErr The error code.
148	* @param pRegFrame The register frame.
149	* @param pvFault The fault address.
150	* @param pPage The guest page at @a pvFault.
151	* @param pGstWalk The guest page table walk result.
152	* @param pfLockTaken PGM lock taken here or not (out). This is true
153	* when we're called.
154	*/
155	static VBOXSTRICTRC PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame,
156	RTGCPTR pvFault, PPGMPAGE pPage, bool *pfLockTaken
157	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
158	, PGSTPTWALK pGstWalk
159	# endif
160	)
161	{
162	# if !PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
163	GSTPDE const PdeSrcDummy = { X86_PDE_P \| X86_PDE_US \| X86_PDE_RW \| X86_PDE_A };
164	#endif
165	PVM pVM = pVCpu->CTX_SUFF(pVM);
166	VBOXSTRICTRC rcStrict;
167
168	if (PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage))
169	{
170	/*
171	* Physical page access handler.
172	*/
173	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
174	const RTGCPHYS GCPhysFault = pGstWalk->Core.GCPhys;
175	# else
176	const RTGCPHYS GCPhysFault = PGM_A20_APPLY(pVCpu, (RTGCPHYS)pvFault);
177	# endif
178	PPGMPHYSHANDLER pCur = pgmHandlerPhysicalLookup(pVM, GCPhysFault);
179	if (pCur)
180	{
181	PPGMPHYSHANDLERTYPEINT pCurType = PGMPHYSHANDLER_GET_TYPE(pVM, pCur);
182
183	# ifdef PGM_SYNC_N_PAGES
184	/*
185	* If the region is write protected and we got a page not present fault, then sync
186	* the pages. If the fault was caused by a read, then restart the instruction.
187	* In case of write access continue to the GC write handler.
188	*
189	* ASSUMES that there is only one handler per page or that they have similar write properties.
190	*/
191	if ( !(uErr & X86_TRAP_PF_P)
192	&& pCurType->enmKind == PGMPHYSHANDLERKIND_WRITE)
193	{
194	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
195	rcStrict = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
196	# else
197	rcStrict = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
198	# endif
199	if ( RT_FAILURE(rcStrict)
200	\|\| !(uErr & X86_TRAP_PF_RW)
201	\|\| rcStrict == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
202	{
203	AssertMsgRC(rcStrict, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
204	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersOutOfSync);
205	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndPhys; });
206	return rcStrict;
207	}
208	}
209	# endif
210	# ifdef PGM_WITH_MMIO_OPTIMIZATIONS
211	/*
212	* If the access was not thru a #PF(RSVD\|...) resync the page.
213	*/
214	if ( !(uErr & X86_TRAP_PF_RSVD)
215	&& pCurType->enmKind != PGMPHYSHANDLERKIND_WRITE
216	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
217	&& pGstWalk->Core.fEffectiveRW
218	&& !pGstWalk->Core.fEffectiveUS /** @todo Remove pGstWalk->Core.fEffectiveUS and X86_PTE_US further down in the sync code. */
219	# endif
220	)
221	{
222	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
223	rcStrict = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
224	# else
225	rcStrict = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
226	# endif
227	if ( RT_FAILURE(rcStrict)
228	\|\| rcStrict == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
229	{
230	AssertMsgRC(rcStrict, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
231	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersOutOfSync);
232	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndPhys; });
233	return rcStrict;
234	}
235	}
236	# endif
237
238	AssertMsg( pCurType->enmKind != PGMPHYSHANDLERKIND_WRITE
239	\|\| (pCurType->enmKind == PGMPHYSHANDLERKIND_WRITE && (uErr & X86_TRAP_PF_RW)),
240	("Unexpected trap for physical handler: %08X (phys=%08x) pPage=%R[pgmpage] uErr=%X, enmKind=%d\n",
241	pvFault, GCPhysFault, pPage, uErr, pCurType->enmKind));
242	if (pCurType->enmKind == PGMPHYSHANDLERKIND_WRITE)
243	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersPhysWrite);
244	else
245	{
246	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersPhysAll);
247	if (uErr & X86_TRAP_PF_RSVD) STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersPhysAllOpt);
248	}
249
250	if (pCurType->CTX_SUFF(pfnPfHandler))
251	{
252	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
253	void *pvUser = pCur->CTX_SUFF(pvUser);
254
255	STAM_PROFILE_START(&pCur->Stat, h);
256	if (pCur->hType != pPool->hAccessHandlerType)
257	{
258	pgmUnlock(pVM);
259	*pfLockTaken = false;
260	}
261
262	rcStrict = pCurType->CTX_SUFF(pfnPfHandler)(pVM, pVCpu, uErr, pRegFrame, pvFault, GCPhysFault, pvUser);
263
264	# ifdef VBOX_WITH_STATISTICS
265	pgmLock(pVM);
266	pCur = pgmHandlerPhysicalLookup(pVM, GCPhysFault);
267	if (pCur)
268	STAM_PROFILE_STOP(&pCur->Stat, h);
269	pgmUnlock(pVM);
270	# endif
271	}
272	else
273	rcStrict = VINF_EM_RAW_EMULATE_INSTR;
274
275	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndPhys; });
276	return rcStrict;
277	}
278	}
279	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0)
280	else
281	{
282	# ifdef PGM_SYNC_N_PAGES
283	/*
284	* If the region is write protected and we got a page not present fault, then sync
285	* the pages. If the fault was caused by a read, then restart the instruction.
286	* In case of write access continue to the GC write handler.
287	*/
288	if ( PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) < PGM_PAGE_HNDL_PHYS_STATE_ALL
289	&& !(uErr & X86_TRAP_PF_P))
290	{
291	rcStrict = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
292	if ( RT_FAILURE(rcStrict)
293	\|\| rcStrict == VINF_PGM_SYNCPAGE_MODIFIED_PDE
294	\|\| !(uErr & X86_TRAP_PF_RW))
295	{
296	AssertRC(rcStrict);
297	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersOutOfSync);
298	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndVirt; });
299	return rcStrict;
300	}
301	}
302	# endif
303	/*
304	* Ok, it's an virtual page access handler.
305	*
306	* Since it's faster to search by address, we'll do that first
307	* and then retry by GCPhys if that fails.
308	*/
309	/** @todo r=bird: perhaps we should consider looking up by physical address directly now?
310	* r=svl: true, but lookup on virtual address should remain as a fallback as phys & virt trees might be
311	* out of sync, because the page was changed without us noticing it (not-present -> present
312	* without invlpg or mov cr3, xxx).
313	*/
314	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
315	if (pCur)
316	{
317	PPGMVIRTHANDLERTYPEINT pCurType = PGMVIRTANDLER_GET_TYPE(pVM, pCur);
318	AssertMsg(!(pvFault - pCur->Core.Key < pCur->cb)
319	\|\| ( pCurType->enmKind != PGMVIRTHANDLERKIND_WRITE
320	\|\| !(uErr & X86_TRAP_PF_P)
321	\|\| (pCurType->enmKind == PGMVIRTHANDLERKIND_WRITE && (uErr & X86_TRAP_PF_RW))),
322	("Unexpected trap for virtual handler: %RGv (phys=%RGp) pPage=%R[pgmpage] uErr=%X, enumKind=%d\n",
323	pvFault, pGstWalk->Core.GCPhys, pPage, uErr, pCurType->enmKind));
324
325	if ( pvFault - pCur->Core.Key < pCur->cb
326	&& ( uErr & X86_TRAP_PF_RW
327	\|\| pCurType->enmKind != PGMVIRTHANDLERKIND_WRITE ) )
328	{
329	# ifdef IN_RC
330	STAM_PROFILE_START(&pCur->Stat, h);
331	RTGCPTR GCPtrStart = pCur->Core.Key;
332	void *pvUser = pCur->CTX_SUFF(pvUser);
333	pgmUnlock(pVM);
334	*pfLockTaken = false;
335
336	rcStrict = pCurType->CTX_SUFF(pfnPfHandler)(pVM, pVCpu, uErr, pRegFrame, pvFault, GCPtrStart,
337	pvFault - GCPtrStart, pvUser);
338
339	# ifdef VBOX_WITH_STATISTICS
340	pgmLock(pVM);
341	pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
342	if (pCur)
343	STAM_PROFILE_STOP(&pCur->Stat, h);
344	pgmUnlock(pVM);
345	# endif
346	# else
347	rcStrict = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
348	# endif
349	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersVirtual);
350	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndVirt; });
351	return rcStrict;
352	}
353	/* Unhandled part of a monitored page */
354	Log(("Unhandled part of monitored page %RGv\n", pvFault));
355	}
356	else
357	{
358	/* Check by physical address. */
359	unsigned iPage;
360	pCur = pgmHandlerVirtualFindByPhysAddr(pVM, pGstWalk->Core.GCPhys, &iPage);
361	if (pCur)
362	{
363	PPGMVIRTHANDLERTYPEINT pCurType = PGMVIRTANDLER_GET_TYPE(pVM, pCur);
364	if ( uErr & X86_TRAP_PF_RW
365	\|\| pCurType->enmKind != PGMVIRTHANDLERKIND_WRITE )
366	{
367	Assert( (pCur->aPhysToVirt[iPage].Core.Key & X86_PTE_PAE_PG_MASK)
368	== (pGstWalk->Core.GCPhys & X86_PTE_PAE_PG_MASK));
369	# ifdef IN_RC
370	STAM_PROFILE_START(&pCur->Stat, h);
371	RTGCPTR GCPtrStart = pCur->Core.Key;
372	void *pvUser = pCur->CTX_SUFF(pvUser);
373	pgmUnlock(pVM);
374	*pfLockTaken = false;
375
376	RTGCPTR off = (iPage << PAGE_SHIFT)
377	+ (pvFault & PAGE_OFFSET_MASK)
378	- (GCPtrStart & PAGE_OFFSET_MASK);
379	Assert(off < pCur->cb);
380	rcStrict = pCurType->CTX_SUFF(pfnPfHandler)(pVM, pVCpu, uErr, pRegFrame, pvFault, GCPtrStart, off, pvUser);
381
382	# ifdef VBOX_WITH_STATISTICS
383	pgmLock(pVM);
384	pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, GCPtrStart);
385	if (pCur)
386	STAM_PROFILE_STOP(&pCur->Stat, h);
387	pgmUnlock(pVM);
388	# endif
389	# else
390	rcStrict = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
391	# endif
392	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersVirtualByPhys);
393	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndVirt; });
394	return rcStrict;
395	}
396	}
397	}
398	}
399	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
400
401	/*
402	* There is a handled area of the page, but this fault doesn't belong to it.
403	* We must emulate the instruction.
404	*
405	* To avoid crashing (non-fatal) in the interpreter and go back to the recompiler
406	* we first check if this was a page-not-present fault for a page with only
407	* write access handlers. Restart the instruction if it wasn't a write access.
408	*/
409	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersUnhandled);
410
411	if ( !PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
412	&& !(uErr & X86_TRAP_PF_P))
413	{
414	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
415	rcStrict = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
416	# else
417	rcStrict = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
418	# endif
419	if ( RT_FAILURE(rcStrict)
420	\|\| rcStrict == VINF_PGM_SYNCPAGE_MODIFIED_PDE
421	\|\| !(uErr & X86_TRAP_PF_RW))
422	{
423	AssertMsgRC(rcStrict, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
424	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersOutOfSync);
425	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndPhys; });
426	return rcStrict;
427	}
428	}
429
430	/** @todo This particular case can cause quite a lot of overhead. E.g. early stage of kernel booting in Ubuntu 6.06
431	* It's writing to an unhandled part of the LDT page several million times.
432	*/
433	rcStrict = PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault);
434	LogFlow(("PGM: PGMInterpretInstruction -> rcStrict=%d pPage=%R[pgmpage]\n", VBOXSTRICTRC_VAL(rcStrict), pPage));
435	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndUnhandled; });
436	return rcStrict;
437	} /* if any kind of handler */
438
439
440	/**
441	* #PF Handler for raw-mode guest execution.
442	*
443	* @returns VBox status code (appropriate for trap handling and GC return).
444	*
445	* @param pVCpu Pointer to the VMCPU.
446	* @param uErr The trap error code.
447	* @param pRegFrame Trap register frame.
448	* @param pvFault The fault address.
449	* @param pfLockTaken PGM lock taken here or not (out)
450	*/
451	PGM_BTH_DECL(int, Trap0eHandler)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken)
452	{
453	PVM pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
454
455	*pfLockTaken = false;
456
457	# if ( PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \
458	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
459	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
460	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT)
461	int rc;
462
463	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
464	/*
465	* Walk the guest page translation tables and check if it's a guest fault.
466	*/
467	GSTPTWALK GstWalk;
468	rc = PGM_GST_NAME(Walk)(pVCpu, pvFault, &GstWalk);
469	if (RT_FAILURE_NP(rc))
470	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerGuestFault)(pVCpu, &GstWalk, uErr));
471
472	/* assert some GstWalk sanity. */
473	# if PGM_GST_TYPE == PGM_TYPE_AMD64
474	/AssertMsg(GstWalk.Pml4e.u == GstWalk.pPml4e->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pml4e.u, (uint64_t)GstWalk.pPml4e->u)); - not always true with SMP guests. /
475	# endif
476	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
477	/AssertMsg(GstWalk.Pdpe.u == GstWalk.pPdpe->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pdpe.u, (uint64_t)GstWalk.pPdpe->u)); - ditto /
478	# endif
479	/AssertMsg(GstWalk.Pde.u == GstWalk.pPde->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pde.u, (uint64_t)GstWalk.pPde->u)); - ditto /
480	/AssertMsg(GstWalk.Core.fBigPage \|\| GstWalk.Pte.u == GstWalk.pPte->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pte.u, (uint64_t)GstWalk.pPte->u)); - ditto /
481	Assert(GstWalk.Core.fSucceeded);
482
483	if (uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US \| X86_TRAP_PF_ID))
484	{
485	if ( ( (uErr & X86_TRAP_PF_RW)
486	&& !GstWalk.Core.fEffectiveRW
487	&& ( (uErr & X86_TRAP_PF_US)
488	\|\| CPUMIsGuestR0WriteProtEnabled(pVCpu)) )
489	\|\| ((uErr & X86_TRAP_PF_US) && !GstWalk.Core.fEffectiveUS)
490	\|\| ((uErr & X86_TRAP_PF_ID) && GstWalk.Core.fEffectiveNX)
491	)
492	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerGuestFault)(pVCpu, &GstWalk, uErr));
493	}
494
495	/*
496	* Set the accessed and dirty flags.
497	*/
498	# if PGM_GST_TYPE == PGM_TYPE_AMD64
499	GstWalk.Pml4e.u \|= X86_PML4E_A;
500	GstWalk.pPml4e->u \|= X86_PML4E_A;
501	GstWalk.Pdpe.u \|= X86_PDPE_A;
502	GstWalk.pPdpe->u \|= X86_PDPE_A;
503	# endif
504	if (GstWalk.Core.fBigPage)
505	{
506	Assert(GstWalk.Pde.b.u1Size);
507	if (uErr & X86_TRAP_PF_RW)
508	{
509	GstWalk.Pde.u \|= X86_PDE4M_A \| X86_PDE4M_D;
510	GstWalk.pPde->u \|= X86_PDE4M_A \| X86_PDE4M_D;
511	}
512	else
513	{
514	GstWalk.Pde.u \|= X86_PDE4M_A;
515	GstWalk.pPde->u \|= X86_PDE4M_A;
516	}
517	}
518	else
519	{
520	Assert(!GstWalk.Pde.b.u1Size);
521	GstWalk.Pde.u \|= X86_PDE_A;
522	GstWalk.pPde->u \|= X86_PDE_A;
523	if (uErr & X86_TRAP_PF_RW)
524	{
525	# ifdef VBOX_WITH_STATISTICS
526	if (!GstWalk.Pte.n.u1Dirty)
527	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtiedPage));
528	else
529	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageAlreadyDirty));
530	# endif
531	GstWalk.Pte.u \|= X86_PTE_A \| X86_PTE_D;
532	GstWalk.pPte->u \|= X86_PTE_A \| X86_PTE_D;
533	}
534	else
535	{
536	GstWalk.Pte.u \|= X86_PTE_A;
537	GstWalk.pPte->u \|= X86_PTE_A;
538	}
539	Assert(GstWalk.Pte.u == GstWalk.pPte->u);
540	}
541	AssertMsg(GstWalk.Pde.u == GstWalk.pPde->u \|\| GstWalk.pPte->u == GstWalk.pPde->u,
542	("%RX64 %RX64 pPte=%p pPde=%p Pte=%RX64\n", (uint64_t)GstWalk.Pde.u, (uint64_t)GstWalk.pPde->u, GstWalk.pPte, GstWalk.pPde, (uint64_t)GstWalk.pPte->u));
543	# else /* !PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
544	GSTPDE const PdeSrcDummy = { X86_PDE_P \| X86_PDE_US \| X86_PDE_RW \| X86_PDE_A}; /** @todo eliminate this */
545	# endif /* !PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
546
547	/* Take the big lock now. */
548	*pfLockTaken = true;
549	pgmLock(pVM);
550
551	# ifdef PGM_WITH_MMIO_OPTIMIZATIONS
552	/*
553	* If it is a reserved bit fault we know that it is an MMIO (access
554	* handler) related fault and can skip some 200 lines of code.
555	*/
556	if (uErr & X86_TRAP_PF_RSVD)
557	{
558	Assert(uErr & X86_TRAP_PF_P);
559	PPGMPAGE pPage;
560	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
561	rc = pgmPhysGetPageEx(pVM, GstWalk.Core.GCPhys, &pPage);
562	if (RT_SUCCESS(rc) && PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
563	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage,
564	pfLockTaken, &GstWalk));
565	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
566	# else
567	rc = pgmPhysGetPageEx(pVM, PGM_A20_APPLY(pVCpu, (RTGCPHYS)pvFault), &pPage);
568	if (RT_SUCCESS(rc) && PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
569	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage,
570	pfLockTaken));
571	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, 1, uErr);
572	# endif
573	AssertRC(rc);
574	PGM_INVL_PG(pVCpu, pvFault);
575	return rc; /* Restart with the corrected entry. */
576	}
577	# endif /* PGM_WITH_MMIO_OPTIMIZATIONS */
578
579	/*
580	* Fetch the guest PDE, PDPE and PML4E.
581	*/
582	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
583	const unsigned iPDDst = pvFault >> SHW_PD_SHIFT;
584	PX86PD pPDDst = pgmShwGet32BitPDPtr(pVCpu);
585
586	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
587	const unsigned iPDDst = (pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK; /* pPDDst index, not used with the pool. */
588	PX86PDPAE pPDDst;
589	# if PGM_GST_TYPE == PGM_TYPE_PAE
590	rc = pgmShwSyncPaePDPtr(pVCpu, pvFault, GstWalk.Pdpe.u, &pPDDst);
591	# else
592	rc = pgmShwSyncPaePDPtr(pVCpu, pvFault, X86_PDPE_P, &pPDDst); /* RW, US and A are reserved in PAE mode. */
593	# endif
594	AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
595
596	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
597	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
598	PX86PDPAE pPDDst;
599	# if PGM_GST_TYPE == PGM_TYPE_PROT /* (AMD-V nested paging) */
600	rc = pgmShwSyncLongModePDPtr(pVCpu, pvFault, X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A,
601	X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A, &pPDDst);
602	# else
603	rc = pgmShwSyncLongModePDPtr(pVCpu, pvFault, GstWalk.Pml4e.u, GstWalk.Pdpe.u, &pPDDst);
604	# endif
605	AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
606
607	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
608	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
609	PEPTPD pPDDst;
610	rc = pgmShwGetEPTPDPtr(pVCpu, pvFault, NULL, &pPDDst);
611	AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
612	# endif
613	Assert(pPDDst);
614
615	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
616	/*
617	* Dirty page handling.
618	*
619	* If we successfully correct the write protection fault due to dirty bit
620	* tracking, then return immediately.
621	*/
622	if (uErr & X86_TRAP_PF_RW) /* write fault? */
623	{
624	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyBitTracking), a);
625	rc = PGM_BTH_NAME(CheckDirtyPageFault)(pVCpu, uErr, &pPDDst->a[iPDDst], GstWalk.pPde, pvFault);
626	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyBitTracking), a);
627	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
628	{
629	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution)
630	= rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT
631	? &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2DirtyAndAccessed
632	: &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2GuestTrap; });
633	Log8(("Trap0eHandler: returns VINF_SUCCESS\n"));
634	return VINF_SUCCESS;
635	}
636	//AssertMsg(GstWalk.Pde.u == GstWalk.pPde->u \|\| GstWalk.pPte->u == GstWalk.pPde->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pde.u, (uint64_t)GstWalk.pPde->u)); - triggers with smp w7 guests.
637	//AssertMsg(GstWalk.Core.fBigPage \|\| GstWalk.Pte.u == GstWalk.pPte->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pte.u, (uint64_t)GstWalk.pPte->u)); - ditto.
638	}
639
640	# if 0 /* rarely useful; leave for debugging. */
641	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0ePD[iPDSrc]);
642	# endif
643	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
644
645	/*
646	* A common case is the not-present error caused by lazy page table syncing.
647	*
648	* It is IMPORTANT that we weed out any access to non-present shadow PDEs
649	* here so we can safely assume that the shadow PT is present when calling
650	* SyncPage later.
651	*
652	* On failure, we ASSUME that SyncPT is out of memory or detected some kind
653	* of mapping conflict and defer to SyncCR3 in R3.
654	* (Again, we do NOT support access handlers for non-present guest pages.)
655	*
656	*/
657	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
658	Assert(GstWalk.Pde.n.u1Present);
659	# endif
660	if ( !(uErr & X86_TRAP_PF_P) /* not set means page not present instead of page protection violation */
661	&& !pPDDst->a[iPDDst].n.u1Present)
662	{
663	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2SyncPT; });
664	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
665	LogFlow(("=>SyncPT %04x = %08RX64\n", (pvFault >> GST_PD_SHIFT) & GST_PD_MASK, (uint64_t)GstWalk.Pde.u));
666	rc = PGM_BTH_NAME(SyncPT)(pVCpu, (pvFault >> GST_PD_SHIFT) & GST_PD_MASK, GstWalk.pPd, pvFault);
667	# else
668	LogFlow(("=>SyncPT pvFault=%RGv\n", pvFault));
669	rc = PGM_BTH_NAME(SyncPT)(pVCpu, 0, NULL, pvFault);
670	# endif
671	if (RT_SUCCESS(rc))
672	return rc;
673	Log(("SyncPT: %RGv failed!! rc=%Rrc\n", pvFault, rc));
674	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync, right? */
675	return VINF_PGM_SYNC_CR3;
676	}
677
678	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(PGM_WITHOUT_MAPPINGS)
679	/*
680	* Check if this address is within any of our mappings.
681	*
682	* This is very fast and it's gonna save us a bit of effort below and prevent
683	* us from screwing ourself with MMIO2 pages which have a GC Mapping (VRam).
684	* (BTW, it's impossible to have physical access handlers in a mapping.)
685	*/
686	if (pgmMapAreMappingsEnabled(pVM))
687	{
688	PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
689	for ( ; pMapping; pMapping = pMapping->CTX_SUFF(pNext))
690	{
691	if (pvFault < pMapping->GCPtr)
692	break;
693	if (pvFault - pMapping->GCPtr < pMapping->cb)
694	{
695	/*
696	* The first thing we check is if we've got an undetected conflict.
697	*/
698	if (pgmMapAreMappingsFloating(pVM))
699	{
700	unsigned iPT = pMapping->cb >> GST_PD_SHIFT;
701	while (iPT-- > 0)
702	if (GstWalk.pPde[iPT].n.u1Present)
703	{
704	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eConflicts);
705	Log(("Trap0e: Detected Conflict %RGv-%RGv\n", pMapping->GCPtr, pMapping->GCPtrLast));
706	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync,right? */
707	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Mapping; });
708	return VINF_PGM_SYNC_CR3;
709	}
710	}
711
712	/*
713	* Check if the fault address is in a virtual page access handler range.
714	*/
715	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->HyperVirtHandlers,
716	pvFault);
717	if ( pCur
718	&& pvFault - pCur->Core.Key < pCur->cb
719	&& uErr & X86_TRAP_PF_RW)
720	{
721	VBOXSTRICTRC rcStrict;
722	# ifdef IN_RC
723	STAM_PROFILE_START(&pCur->Stat, h);
724	PPGMVIRTHANDLERTYPEINT pCurType = PGMVIRTANDLER_GET_TYPE(pVM, pCur);
725	void *pvUser = pCur->CTX_SUFF(pvUser);
726	pgmUnlock(pVM);
727	rcStrict = pCurType->CTX_SUFF(pfnPfHandler)(pVM, pVCpu, uErr, pRegFrame, pvFault, pCur->Core.Key,
728	pvFault - pCur->Core.Key, pvUser);
729	pgmLock(pVM);
730	STAM_PROFILE_STOP(&pCur->Stat, h);
731	# else
732	AssertFailed();
733	rcStrict = VINF_EM_RAW_EMULATE_INSTR; /* can't happen with VMX */
734	# endif
735	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersMapping);
736	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Mapping; });
737	return VBOXSTRICTRC_TODO(rcStrict);
738	}
739
740	/*
741	* Pretend we're not here and let the guest handle the trap.
742	*/
743	TRPMSetErrorCode(pVCpu, uErr & ~X86_TRAP_PF_P);
744	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eGuestPFMapping);
745	LogFlow(("PGM: Mapping access -> route trap to recompiler!\n"));
746	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Mapping; });
747	return VINF_EM_RAW_GUEST_TRAP;
748	}
749	}
750	} /* pgmAreMappingsEnabled(&pVM->pgm.s) */
751	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
752
753	/*
754	* Check if this fault address is flagged for special treatment,
755	* which means we'll have to figure out the physical address and
756	* check flags associated with it.
757	*
758	* ASSUME that we can limit any special access handling to pages
759	* in page tables which the guest believes to be present.
760	*/
761	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
762	RTGCPHYS GCPhys = GstWalk.Core.GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK;
763	# else
764	RTGCPHYS GCPhys = PGM_A20_APPLY(pVCpu, (RTGCPHYS)pvFault & ~(RTGCPHYS)PAGE_OFFSET_MASK);
765	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
766	PPGMPAGE pPage;
767	rc = pgmPhysGetPageEx(pVM, GCPhys, &pPage);
768	if (RT_FAILURE(rc))
769	{
770	/*
771	* When the guest accesses invalid physical memory (e.g. probing
772	* of RAM or accessing a remapped MMIO range), then we'll fall
773	* back to the recompiler to emulate the instruction.
774	*/
775	LogFlow(("PGM #PF: pgmPhysGetPageEx(%RGp) failed with %Rrc\n", GCPhys, rc));
776	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersInvalid);
777	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2InvalidPhys; });
778	return VINF_EM_RAW_EMULATE_INSTR;
779	}
780
781	/*
782	* Any handlers for this page?
783	*/
784	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
785	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
786	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage, pfLockTaken,
787	&GstWalk));
788	# else
789	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage, pfLockTaken));
790	# endif
791
792	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTimeOutOfSync, c);
793
794	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0)
795	if (uErr & X86_TRAP_PF_P)
796	{
797	/*
798	* The page isn't marked, but it might still be monitored by a virtual page access handler.
799	* (ASSUMES no temporary disabling of virtual handlers.)
800	*/
801	/** @todo r=bird: Since the purpose is to catch out of sync pages with virtual handler(s) here,
802	* we should correct both the shadow page table and physical memory flags, and not only check for
803	* accesses within the handler region but for access to pages with virtual handlers. */
804	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
805	if (pCur)
806	{
807	PPGMVIRTHANDLERTYPEINT pCurType = PGMVIRTANDLER_GET_TYPE(pVM, pCur);
808	AssertMsg( !(pvFault - pCur->Core.Key < pCur->cb)
809	\|\| ( pCurType->enmKind != PGMVIRTHANDLERKIND_WRITE
810	\|\| !(uErr & X86_TRAP_PF_P)
811	\|\| (pCurType->enmKind == PGMVIRTHANDLERKIND_WRITE && (uErr & X86_TRAP_PF_RW))),
812	("Unexpected trap for virtual handler: %08X (phys=%08x) %R[pgmpage] uErr=%X, enumKind=%d\n",
813	pvFault, GCPhys, pPage, uErr, pCurType->enmKind));
814
815	if ( pvFault - pCur->Core.Key < pCur->cb
816	&& ( uErr & X86_TRAP_PF_RW
817	\|\| pCurType->enmKind != PGMVIRTHANDLERKIND_WRITE ) )
818	{
819	VBOXSTRICTRC rcStrict;
820	# ifdef IN_RC
821	STAM_PROFILE_START(&pCur->Stat, h);
822	void *pvUser = pCur->CTX_SUFF(pvUser);
823	pgmUnlock(pVM);
824	rcStrict = pCurType->CTX_SUFF(pfnPfHandler)(pVM, pVCpu, uErr, pRegFrame, pvFault, pCur->Core.Key,
825	pvFault - pCur->Core.Key, pvUser);
826	pgmLock(pVM);
827	STAM_PROFILE_STOP(&pCur->Stat, h);
828	# else
829	rcStrict = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
830	# endif
831	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndVirt; });
832	return VBOXSTRICTRC_TODO(rcStrict);
833	}
834	}
835	}
836	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
837
838	/*
839	* We are here only if page is present in Guest page tables and
840	* trap is not handled by our handlers.
841	*
842	* Check it for page out-of-sync situation.
843	*/
844	if (!(uErr & X86_TRAP_PF_P))
845	{
846	/*
847	* Page is not present in our page tables. Try to sync it!
848	*/
849	if (uErr & X86_TRAP_PF_US)
850	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncUser));
851	else /* supervisor */
852	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
853
854	if (PGM_PAGE_IS_BALLOONED(pPage))
855	{
856	/* Emulate reads from ballooned pages as they are not present in
857	our shadow page tables. (Required for e.g. Solaris guests; soft
858	ecc, random nr generator.) */
859	rc = VBOXSTRICTRC_TODO(PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault));
860	LogFlow(("PGM: PGMInterpretInstruction balloon -> rc=%d pPage=%R[pgmpage]\n", rc, pPage));
861	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncBallloon));
862	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Ballooned; });
863	return rc;
864	}
865
866	# if defined(LOG_ENABLED) && !defined(IN_RING0)
867	RTGCPHYS GCPhys2;
868	uint64_t fPageGst2;
869	PGMGstGetPage(pVCpu, pvFault, &fPageGst2, &GCPhys2);
870	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
871	Log(("Page out of sync: %RGv eip=%08x PdeSrc.US=%d fPageGst2=%08llx GCPhys2=%RGp scan=%d\n",
872	pvFault, pRegFrame->eip, GstWalk.Pde.n.u1User, fPageGst2, GCPhys2, CSAMDoesPageNeedScanning(pVM, pRegFrame->eip)));
873	# else
874	Log(("Page out of sync: %RGv eip=%08x fPageGst2=%08llx GCPhys2=%RGp scan=%d\n",
875	pvFault, pRegFrame->eip, fPageGst2, GCPhys2, CSAMDoesPageNeedScanning(pVM, pRegFrame->eip)));
876	# endif
877	# endif /* LOG_ENABLED */
878
879	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0)
880	if ( !GstWalk.Core.fEffectiveUS
881	&& CSAMIsEnabled(pVM)
882	&& CPUMGetGuestCPL(pVCpu) == 0)
883	{
884	/* Note: Can't check for X86_TRAP_ID bit, because that requires execute disable support on the CPU. */
885	if ( pvFault == (RTGCPTR)pRegFrame->eip
886	\|\| pvFault - pRegFrame->eip < 8 /* instruction crossing a page boundary */
887	# ifdef CSAM_DETECT_NEW_CODE_PAGES
888	\|\| ( !PATMIsPatchGCAddr(pVM, pRegFrame->eip)
889	&& CSAMDoesPageNeedScanning(pVM, pRegFrame->eip)) /* any new code we encounter here */
890	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
891	)
892	{
893	LogFlow(("CSAMExecFault %RX32\n", pRegFrame->eip));
894	rc = CSAMExecFault(pVM, (RTRCPTR)pRegFrame->eip);
895	if (rc != VINF_SUCCESS)
896	{
897	/*
898	* CSAM needs to perform a job in ring 3.
899	*
900	* Sync the page before going to the host context; otherwise we'll end up in a loop if
901	* CSAM fails (e.g. instruction crosses a page boundary and the next page is not present)
902	*/
903	LogFlow(("CSAM ring 3 job\n"));
904	int rc2 = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
905	AssertRC(rc2);
906
907	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2CSAM; });
908	return rc;
909	}
910	}
911	# ifdef CSAM_DETECT_NEW_CODE_PAGES
912	else if ( uErr == X86_TRAP_PF_RW
913	&& pRegFrame->ecx >= 0x100 /* early check for movswd count */
914	&& pRegFrame->ecx < 0x10000)
915	{
916	/* In case of a write to a non-present supervisor shadow page, we'll take special precautions
917	* to detect loading of new code pages.
918	*/
919
920	/*
921	* Decode the instruction.
922	*/
923	PDISCPUSTATE pDis = &pVCpu->pgm.s.DisState;
924	uint32_t cbOp;
925	rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
926
927	/* For now we'll restrict this to rep movsw/d instructions */
928	if ( rc == VINF_SUCCESS
929	&& pDis->pCurInstr->opcode == OP_MOVSWD
930	&& (pDis->prefix & DISPREFIX_REP))
931	{
932	CSAMMarkPossibleCodePage(pVM, pvFault);
933	}
934	}
935	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
936
937	/*
938	* Mark this page as safe.
939	*/
940	/** @todo not correct for pages that contain both code and data!! */
941	Log2(("CSAMMarkPage %RGv; scanned=%d\n", pvFault, true));
942	CSAMMarkPage(pVM, pvFault, true);
943	}
944	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0) */
945	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
946	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
947	# else
948	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
949	# endif
950	if (RT_SUCCESS(rc))
951	{
952	/* The page was successfully synced, return to the guest. */
953	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSync; });
954	return VINF_SUCCESS;
955	}
956	}
957	else /* uErr & X86_TRAP_PF_P: */
958	{
959	/*
960	* Write protected pages are made writable when the guest makes the
961	* first write to it. This happens for pages that are shared, write
962	* monitored or not yet allocated.
963	*
964	* We may also end up here when CR0.WP=0 in the guest.
965	*
966	* Also, a side effect of not flushing global PDEs are out of sync
967	* pages due to physical monitored regions, that are no longer valid.
968	* Assume for now it only applies to the read/write flag.
969	*/
970	if (uErr & X86_TRAP_PF_RW)
971	{
972	/*
973	* Check if it is a read-only page.
974	*/
975	if (PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
976	{
977	Log(("PGM #PF: Make writable: %RGp %R[pgmpage] pvFault=%RGp uErr=%#x\n", GCPhys, pPage, pvFault, uErr));
978	Assert(!PGM_PAGE_IS_ZERO(pPage));
979	AssertFatalMsg(!PGM_PAGE_IS_BALLOONED(pPage), ("Unexpected ballooned page at %RGp\n", GCPhys));
980	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2MakeWritable; });
981
982	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
983	if (rc != VINF_SUCCESS)
984	{
985	AssertMsg(rc == VINF_PGM_SYNC_CR3 \|\| RT_FAILURE(rc), ("%Rrc\n", rc));
986	return rc;
987	}
988	if (RT_UNLIKELY(VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY)))
989	return VINF_EM_NO_MEMORY;
990	}
991
992	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
993	/*
994	* Check to see if we need to emulate the instruction if CR0.WP=0.
995	*/
996	if ( !GstWalk.Core.fEffectiveRW
997	&& (CPUMGetGuestCR0(pVCpu) & (X86_CR0_WP \| X86_CR0_PG)) == X86_CR0_PG
998	&& CPUMGetGuestCPL(pVCpu) < 3)
999	{
1000	Assert((uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RW \| X86_TRAP_PF_P));
1001
1002	/*
1003	* The Netware WP0+RO+US hack.
1004	*
1005	* Netware sometimes(/always?) runs with WP0. It has been observed doing
1006	* excessive write accesses to pages which are mapped with US=1 and RW=0
1007	* while WP=0. This causes a lot of exits and extremely slow execution.
1008	* To avoid trapping and emulating every write here, we change the shadow
1009	* page table entry to map it as US=0 and RW=1 until user mode tries to
1010	* access it again (see further below). We count these shadow page table
1011	* changes so we can avoid having to clear the page pool every time the WP
1012	* bit changes to 1 (see PGMCr0WpEnabled()).
1013	*/
1014	# if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) && 1
1015	if ( GstWalk.Core.fEffectiveUS
1016	&& !GstWalk.Core.fEffectiveRW
1017	&& (GstWalk.Core.fBigPage \|\| GstWalk.Pde.n.u1Write)
1018	&& pVM->cCpus == 1 /* Sorry, no go on SMP. Add CFGM option? */)
1019	{
1020	Log(("PGM #PF: Netware WP0+RO+US hack: pvFault=%RGp uErr=%#x (big=%d)\n", pvFault, uErr, GstWalk.Core.fBigPage));
1021	rc = pgmShwMakePageSupervisorAndWritable(pVCpu, pvFault, GstWalk.Core.fBigPage, PGM_MK_PG_IS_WRITE_FAULT);
1022	if (rc == VINF_SUCCESS \|\| rc == VINF_PGM_SYNC_CR3)
1023	{
1024	PGM_INVL_PG(pVCpu, pvFault);
1025	pVCpu->pgm.s.cNetwareWp0Hacks++;
1026	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Wp0RoUsHack; });
1027	return rc;
1028	}
1029	AssertMsg(RT_FAILURE_NP(rc), ("%Rrc\n", rc));
1030	Log(("pgmShwMakePageSupervisorAndWritable(%RGv) failed with rc=%Rrc - ignored\n", pvFault, rc));
1031	}
1032	# endif
1033
1034	/* Interpret the access. */
1035	rc = VBOXSTRICTRC_TODO(PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault));
1036	Log(("PGM #PF: WP0 emulation (pvFault=%RGp uErr=%#x cpl=%d fBig=%d fEffUs=%d)\n", pvFault, uErr, CPUMGetGuestCPL(pVCpu), GstWalk.Core.fBigPage, GstWalk.Core.fEffectiveUS));
1037	if (RT_SUCCESS(rc))
1038	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eWPEmulInRZ);
1039	else
1040	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eWPEmulToR3);
1041	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2WPEmulation; });
1042	return rc;
1043	}
1044	# endif
1045	/// @todo count the above case; else
1046	if (uErr & X86_TRAP_PF_US)
1047	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncUserWrite));
1048	else /* supervisor */
1049	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncSupervisorWrite));
1050
1051	/*
1052	* Sync the page.
1053	*
1054	* Note: Do NOT use PGM_SYNC_NR_PAGES here. That only works if the
1055	* page is not present, which is not true in this case.
1056	*/
1057	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1058	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
1059	# else
1060	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, 1, uErr);
1061	# endif
1062	if (RT_SUCCESS(rc))
1063	{
1064	/*
1065	* Page was successfully synced, return to guest but invalidate
1066	* the TLB first as the page is very likely to be in it.
1067	*/
1068	# if PGM_SHW_TYPE == PGM_TYPE_EPT
1069	HMInvalidatePhysPage(pVM, (RTGCPHYS)pvFault);
1070	# else
1071	PGM_INVL_PG(pVCpu, pvFault);
1072	# endif
1073	# ifdef VBOX_STRICT
1074	RTGCPHYS GCPhys2;
1075	uint64_t fPageGst;
1076	if (!pVM->pgm.s.fNestedPaging)
1077	{
1078	rc = PGMGstGetPage(pVCpu, pvFault, &fPageGst, &GCPhys2);
1079	AssertMsg(RT_SUCCESS(rc) && ((fPageGst & X86_PTE_RW) \|\| ((CPUMGetGuestCR0(pVCpu) & (X86_CR0_WP \| X86_CR0_PG)) == X86_CR0_PG && CPUMGetGuestCPL(pVCpu) < 3)), ("rc=%Rrc fPageGst=%RX64\n", rc, fPageGst));
1080	LogFlow(("Obsolete physical monitor page out of sync %RGv - phys %RGp flags=%08llx\n", pvFault, GCPhys2, (uint64_t)fPageGst));
1081	}
1082	uint64_t fPageShw;
1083	rc = PGMShwGetPage(pVCpu, pvFault, &fPageShw, NULL);
1084	AssertMsg((RT_SUCCESS(rc) && (fPageShw & X86_PTE_RW)) \|\| pVM->cCpus > 1 /* new monitor can be installed/page table flushed between the trap exit and PGMTrap0eHandler */,
1085	("rc=%Rrc fPageShw=%RX64\n", rc, fPageShw));
1086	# endif /* VBOX_STRICT */
1087	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndObs; });
1088	return VINF_SUCCESS;
1089	}
1090	}
1091	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1092	/*
1093	* Check for Netware WP0+RO+US hack from above and undo it when user
1094	* mode accesses the page again.
1095	*/
1096	else if ( GstWalk.Core.fEffectiveUS
1097	&& !GstWalk.Core.fEffectiveRW
1098	&& (GstWalk.Core.fBigPage \|\| GstWalk.Pde.n.u1Write)
1099	&& pVCpu->pgm.s.cNetwareWp0Hacks > 0
1100	&& (CPUMGetGuestCR0(pVCpu) & (X86_CR0_WP \| X86_CR0_PG)) == X86_CR0_PG
1101	&& CPUMGetGuestCPL(pVCpu) == 3
1102	&& pVM->cCpus == 1
1103	)
1104	{
1105	Log(("PGM #PF: Undo netware WP0+RO+US hack: pvFault=%RGp uErr=%#x\n", pvFault, uErr));
1106	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
1107	if (RT_SUCCESS(rc))
1108	{
1109	PGM_INVL_PG(pVCpu, pvFault);
1110	pVCpu->pgm.s.cNetwareWp0Hacks--;
1111	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Wp0RoUsUnhack; });
1112	return VINF_SUCCESS;
1113	}
1114	}
1115	# endif /* PGM_WITH_PAGING */
1116
1117	/** @todo else: why are we here? */
1118
1119	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && defined(VBOX_STRICT)
1120	/*
1121	* Check for VMM page flags vs. Guest page flags consistency.
1122	* Currently only for debug purposes.
1123	*/
1124	if (RT_SUCCESS(rc))
1125	{
1126	/* Get guest page flags. */
1127	uint64_t fPageGst;
1128	rc = PGMGstGetPage(pVCpu, pvFault, &fPageGst, NULL);
1129	if (RT_SUCCESS(rc))
1130	{
1131	uint64_t fPageShw;
1132	rc = PGMShwGetPage(pVCpu, pvFault, &fPageShw, NULL);
1133
1134	/*
1135	* Compare page flags.
1136	* Note: we have AVL, A, D bits desynced.
1137	*/
1138	AssertMsg( (fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK))
1139	== (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK))
1140	\|\| ( pVCpu->pgm.s.cNetwareWp0Hacks > 0
1141	&& (fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK \| X86_PTE_RW \| X86_PTE_US))
1142	== (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK \| X86_PTE_RW \| X86_PTE_US))
1143	&& (fPageShw & (X86_PTE_RW \| X86_PTE_US)) == X86_PTE_RW
1144	&& (fPageGst & (X86_PTE_RW \| X86_PTE_US)) == X86_PTE_US),
1145	("Page flags mismatch! pvFault=%RGv uErr=%x GCPhys=%RGp fPageShw=%RX64 fPageGst=%RX64\n",
1146	pvFault, (uint32_t)uErr, GCPhys, fPageShw, fPageGst));
1147	}
1148	else
1149	AssertMsgFailed(("PGMGstGetPage rc=%Rrc\n", rc));
1150	}
1151	else
1152	AssertMsgFailed(("PGMGCGetPage rc=%Rrc\n", rc));
1153	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && VBOX_STRICT */
1154	}
1155
1156
1157	/*
1158	* If we get here it is because something failed above, i.e. most like guru
1159	* meditiation time.
1160	*/
1161	LogRel(("%s: returns rc=%Rrc pvFault=%RGv uErr=%RX64 cs:rip=%04x:%08RX64\n",
1162	__PRETTY_FUNCTION__, rc, pvFault, (uint64_t)uErr, pRegFrame->cs.Sel, pRegFrame->rip));
1163	return rc;
1164
1165	# else /* Nested paging, EPT except PGM_GST_TYPE = PROT */
1166	NOREF(uErr); NOREF(pRegFrame); NOREF(pvFault);
1167	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
1168	return VERR_PGM_NOT_USED_IN_MODE;
1169	# endif
1170	}
1171	#endif /* !IN_RING3 */
1172
1173
1174	/**
1175	* Emulation of the invlpg instruction.
1176	*
1177	*
1178	* @returns VBox status code.
1179	*
1180	* @param pVCpu Pointer to the VMCPU.
1181	* @param GCPtrPage Page to invalidate.
1182	*
1183	* @remark ASSUMES that the guest is updating before invalidating. This order
1184	* isn't required by the CPU, so this is speculative and could cause
1185	* trouble.
1186	* @remark No TLB shootdown is done on any other VCPU as we assume that
1187	* invlpg emulation is the only reason for calling this function.
1188	* (The guest has to shoot down TLB entries on other CPUs itself)
1189	* Currently true, but keep in mind!
1190	*
1191	* @todo Clean this up! Most of it is (or should be) no longer necessary as we catch all page table accesses.
1192	* Should only be required when PGMPOOL_WITH_OPTIMIZED_DIRTY_PT is active (PAE or AMD64 (for now))
1193	*/
1194	PGM_BTH_DECL(int, InvalidatePage)(PVMCPU pVCpu, RTGCPTR GCPtrPage)
1195	{
1196	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
1197	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
1198	&& PGM_SHW_TYPE != PGM_TYPE_EPT
1199	int rc;
1200	PVM pVM = pVCpu->CTX_SUFF(pVM);
1201	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1202
1203	PGM_LOCK_ASSERT_OWNER(pVM);
1204
1205	LogFlow(("InvalidatePage %RGv\n", GCPtrPage));
1206
1207	/*
1208	* Get the shadow PD entry and skip out if this PD isn't present.
1209	* (Guessing that it is frequent for a shadow PDE to not be present, do this first.)
1210	*/
1211	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1212	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1213	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
1214
1215	/* Fetch the pgm pool shadow descriptor. */
1216	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
1217	Assert(pShwPde);
1218
1219	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1220	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT);
1221	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(pVCpu);
1222
1223	/* If the shadow PDPE isn't present, then skip the invalidate. */
1224	if (!pPdptDst->a[iPdpt].n.u1Present)
1225	{
1226	Assert(!(pPdptDst->a[iPdpt].u & PGM_PLXFLAGS_MAPPING));
1227	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1228	PGM_INVL_PG(pVCpu, GCPtrPage);
1229	return VINF_SUCCESS;
1230	}
1231
1232	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1233	PPGMPOOLPAGE pShwPde = NULL;
1234	PX86PDPAE pPDDst;
1235
1236	/* Fetch the pgm pool shadow descriptor. */
1237	rc = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
1238	AssertRCSuccessReturn(rc, rc);
1239	Assert(pShwPde);
1240
1241	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
1242	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1243
1244	# else /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
1245	/* PML4 */
1246	/const unsigned iPml4 = (GCPtrPage >> X86_PML4_SHIFT) & X86_PML4_MASK;/
1247	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1248	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1249	PX86PDPAE pPDDst;
1250	PX86PDPT pPdptDst;
1251	PX86PML4E pPml4eDst;
1252	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eDst, &pPdptDst, &pPDDst);
1253	if (rc != VINF_SUCCESS)
1254	{
1255	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT \|\| rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
1256	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1257	PGM_INVL_PG(pVCpu, GCPtrPage);
1258	return VINF_SUCCESS;
1259	}
1260	Assert(pPDDst);
1261
1262	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1263	PX86PDPE pPdpeDst = &pPdptDst->a[iPdpt];
1264
1265	if (!pPdpeDst->n.u1Present)
1266	{
1267	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1268	PGM_INVL_PG(pVCpu, GCPtrPage);
1269	return VINF_SUCCESS;
1270	}
1271
1272	/* Fetch the pgm pool shadow descriptor. */
1273	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & SHW_PDPE_PG_MASK);
1274	Assert(pShwPde);
1275
1276	# endif /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
1277
1278	const SHWPDE PdeDst = *pPdeDst;
1279	if (!PdeDst.n.u1Present)
1280	{
1281	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1282	PGM_INVL_PG(pVCpu, GCPtrPage);
1283	return VINF_SUCCESS;
1284	}
1285
1286	/*
1287	* Get the guest PD entry and calc big page.
1288	*/
1289	# if PGM_GST_TYPE == PGM_TYPE_32BIT
1290	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
1291	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
1292	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
1293	# else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1294	unsigned iPDSrc = 0;
1295	# if PGM_GST_TYPE == PGM_TYPE_PAE
1296	X86PDPE PdpeSrcIgn;
1297	PX86PDPAE pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtrPage, &iPDSrc, &PdpeSrcIgn);
1298	# else /* AMD64 */
1299	PX86PML4E pPml4eSrcIgn;
1300	X86PDPE PdpeSrcIgn;
1301	PX86PDPAE pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eSrcIgn, &PdpeSrcIgn, &iPDSrc);
1302	# endif
1303	GSTPDE PdeSrc;
1304
1305	if (pPDSrc)
1306	PdeSrc = pPDSrc->a[iPDSrc];
1307	else
1308	PdeSrc.u = 0;
1309	# endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1310	const bool fIsBigPage = PdeSrc.b.u1Size && GST_IS_PSE_ACTIVE(pVCpu);
1311
1312	# ifdef IN_RING3
1313	/*
1314	* If a CR3 Sync is pending we may ignore the invalidate page operation
1315	* depending on the kind of sync and if it's a global page or not.
1316	* This doesn't make sense in GC/R0 so we'll skip it entirely there.
1317	*/
1318	# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
1319	if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3)
1320	\|\| ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
1321	&& fIsBigPage
1322	&& PdeSrc.b.u1Global
1323	)
1324	)
1325	# else
1326	if (VM_FF_IS_PENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL) )
1327	# endif
1328	{
1329	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1330	return VINF_SUCCESS;
1331	}
1332	# endif /* IN_RING3 */
1333
1334	/*
1335	* Deal with the Guest PDE.
1336	*/
1337	rc = VINF_SUCCESS;
1338	if (PdeSrc.n.u1Present)
1339	{
1340	Assert( PdeSrc.n.u1User == PdeDst.n.u1User
1341	&& (PdeSrc.n.u1Write \|\| !PdeDst.n.u1Write \|\| pVCpu->pgm.s.cNetwareWp0Hacks > 0));
1342	# ifndef PGM_WITHOUT_MAPPING
1343	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
1344	{
1345	/*
1346	* Conflict - Let SyncPT deal with it to avoid duplicate code.
1347	*/
1348	Assert(pgmMapAreMappingsEnabled(pVM));
1349	Assert(PGMGetGuestMode(pVCpu) <= PGMMODE_PAE);
1350	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
1351	}
1352	else
1353	# endif /* !PGM_WITHOUT_MAPPING */
1354	if (!fIsBigPage)
1355	{
1356	/*
1357	* 4KB - page.
1358	*/
1359	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1360	RTGCPHYS GCPhys = GST_GET_PDE_GCPHYS(PdeSrc);
1361
1362	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1363	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1364	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| ((iPDDst & 1) * (PAGE_SIZE / 2)));
1365	# endif
1366	if (pShwPage->GCPhys == GCPhys)
1367	{
1368	/* Syncing it here isn't 100% safe and it's probably not worth spending time syncing it. */
1369	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1370
1371	PGSTPT pPTSrc;
1372	rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GST_GET_PDE_GCPHYS(PdeSrc), &pPTSrc);
1373	if (RT_SUCCESS(rc))
1374	{
1375	const unsigned iPTSrc = (GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK;
1376	GSTPTE PteSrc = pPTSrc->a[iPTSrc];
1377	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1378	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1379	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx %s\n",
1380	GCPtrPage, PteSrc.n.u1Present,
1381	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1382	PteSrc.n.u1User & PdeSrc.n.u1User,
1383	(uint64_t)PteSrc.u,
1384	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
1385	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
1386	}
1387	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePage4KBPages));
1388	PGM_INVL_PG(pVCpu, GCPtrPage);
1389	}
1390	else
1391	{
1392	/*
1393	* The page table address changed.
1394	*/
1395	LogFlow(("InvalidatePage: Out-of-sync at %RGp PdeSrc=%RX64 PdeDst=%RX64 ShwGCPhys=%RGp iPDDst=%#x\n",
1396	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, iPDDst));
1397	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1398	ASMAtomicWriteSize(pPdeDst, 0);
1399	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1400	PGM_INVL_VCPU_TLBS(pVCpu);
1401	}
1402	}
1403	else
1404	{
1405	/*
1406	* 2/4MB - page.
1407	*/
1408	/* Before freeing the page, check if anything really changed. */
1409	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1410	RTGCPHYS GCPhys = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
1411	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1412	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1413	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| (GCPtrPage & (1 << X86_PD_PAE_SHIFT)));
1414	# endif
1415	if ( pShwPage->GCPhys == GCPhys
1416	&& pShwPage->enmKind == BTH_PGMPOOLKIND_PT_FOR_BIG)
1417	{
1418	/* ASSUMES a the given bits are identical for 4M and normal PDEs */
1419	/** @todo This test is wrong as it cannot check the G bit!
1420	* FIXME */
1421	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US))
1422	== (PdeDst.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US))
1423	&& ( PdeSrc.b.u1Dirty /** @todo rainy day: What about read-only 4M pages? not very common, but still... */
1424	\|\| (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)))
1425	{
1426	LogFlow(("Skipping flush for big page containing %RGv (PD=%X .u=%RX64)-> nothing has changed!\n", GCPtrPage, iPDSrc, PdeSrc.u));
1427	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePage4MBPagesSkip));
1428	return VINF_SUCCESS;
1429	}
1430	}
1431
1432	/*
1433	* Ok, the page table is present and it's been changed in the guest.
1434	* If we're in host context, we'll just mark it as not present taking the lazy approach.
1435	* We could do this for some flushes in GC too, but we need an algorithm for
1436	* deciding which 4MB pages containing code likely to be executed very soon.
1437	*/
1438	LogFlow(("InvalidatePage: Out-of-sync PD at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
1439	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1440	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1441	ASMAtomicWriteSize(pPdeDst, 0);
1442	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePage4MBPages));
1443	PGM_INVL_BIG_PG(pVCpu, GCPtrPage);
1444	}
1445	}
1446	else
1447	{
1448	/*
1449	* Page directory is not present, mark shadow PDE not present.
1450	*/
1451	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
1452	{
1453	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1454	ASMAtomicWriteSize(pPdeDst, 0);
1455	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePagePDNPs));
1456	PGM_INVL_PG(pVCpu, GCPtrPage);
1457	}
1458	else
1459	{
1460	Assert(pgmMapAreMappingsEnabled(pVM));
1461	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePagePDMappings));
1462	}
1463	}
1464	return rc;
1465
1466	#else /* guest real and protected mode */
1467	/* There's no such thing as InvalidatePage when paging is disabled, so just ignore. */
1468	NOREF(pVCpu); NOREF(GCPtrPage);
1469	return VINF_SUCCESS;
1470	#endif
1471	}
1472
1473
1474	/**
1475	* Update the tracking of shadowed pages.
1476	*
1477	* @param pVCpu Pointer to the VMCPU.
1478	* @param pShwPage The shadow page.
1479	* @param HCPhys The physical page we is being dereferenced.
1480	* @param iPte Shadow PTE index
1481	* @param GCPhysPage Guest physical address (only valid if pShwPage->fDirty is set)
1482	*/
1483	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVMCPU pVCpu, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys, uint16_t iPte,
1484	RTGCPHYS GCPhysPage)
1485	{
1486	PVM pVM = pVCpu->CTX_SUFF(pVM);
1487
1488	# if defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT) \
1489	&& PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
1490	&& (PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_PAE /* pae/32bit combo */)
1491
1492	/* Use the hint we retrieved from the cached guest PT. */
1493	if (pShwPage->fDirty)
1494	{
1495	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1496
1497	Assert(pShwPage->cPresent);
1498	Assert(pPool->cPresent);
1499	pShwPage->cPresent--;
1500	pPool->cPresent--;
1501
1502	PPGMPAGE pPhysPage = pgmPhysGetPage(pVM, GCPhysPage);
1503	AssertRelease(pPhysPage);
1504	pgmTrackDerefGCPhys(pPool, pShwPage, pPhysPage, iPte);
1505	return;
1506	}
1507	# else
1508	NOREF(GCPhysPage);
1509	# endif
1510
1511	STAM_PROFILE_START(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackDeref, a);
1512	LogFlow(("SyncPageWorkerTrackDeref: Damn HCPhys=%RHp pShwPage->idx=%#x!!!\n", HCPhys, pShwPage->idx));
1513
1514	/** @todo If this turns out to be a bottle neck (very likely) two things can be done:
1515	* 1. have a medium sized HCPhys -> GCPhys TLB (hash?)
1516	* 2. write protect all shadowed pages. I.e. implement caching.
1517	*/
1518	/** @todo duplicated in the 2nd half of pgmPoolTracDerefGCPhysHint */
1519
1520	/*
1521	* Find the guest address.
1522	*/
1523	for (PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRangesX);
1524	pRam;
1525	pRam = pRam->CTX_SUFF(pNext))
1526	{
1527	unsigned iPage = pRam->cb >> PAGE_SHIFT;
1528	while (iPage-- > 0)
1529	{
1530	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
1531	{
1532	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1533
1534	Assert(pShwPage->cPresent);
1535	Assert(pPool->cPresent);
1536	pShwPage->cPresent--;
1537	pPool->cPresent--;
1538
1539	pgmTrackDerefGCPhys(pPool, pShwPage, &pRam->aPages[iPage], iPte);
1540	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackDeref, a);
1541	return;
1542	}
1543	}
1544	}
1545
1546	for (;;)
1547	AssertReleaseMsgFailed(("HCPhys=%RHp wasn't found!\n", HCPhys));
1548	}
1549
1550
1551	/**
1552	* Update the tracking of shadowed pages.
1553	*
1554	* @param pVCpu Pointer to the VMCPU.
1555	* @param pShwPage The shadow page.
1556	* @param u16 The top 16-bit of the pPage->HCPhys.
1557	* @param pPage Pointer to the guest page. this will be modified.
1558	* @param iPTDst The index into the shadow table.
1559	*/
1560	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackAddref)(PVMCPU pVCpu, PPGMPOOLPAGE pShwPage, uint16_t u16, PPGMPAGE pPage, const unsigned iPTDst)
1561	{
1562	PVM pVM = pVCpu->CTX_SUFF(pVM);
1563
1564	/*
1565	* Just deal with the simple first time here.
1566	*/
1567	if (!u16)
1568	{
1569	STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackVirgin);
1570	u16 = PGMPOOL_TD_MAKE(1, pShwPage->idx);
1571	/* Save the page table index. */
1572	PGM_PAGE_SET_PTE_INDEX(pVM, pPage, iPTDst);
1573	}
1574	else
1575	u16 = pgmPoolTrackPhysExtAddref(pVM, pPage, u16, pShwPage->idx, iPTDst);
1576
1577	/* write back */
1578	Log2(("SyncPageWorkerTrackAddRef: u16=%#x->%#x iPTDst=%#x\n", u16, PGM_PAGE_GET_TRACKING(pPage), iPTDst));
1579	PGM_PAGE_SET_TRACKING(pVM, pPage, u16);
1580
1581	/* update statistics. */
1582	pVM->pgm.s.CTX_SUFF(pPool)->cPresent++;
1583	pShwPage->cPresent++;
1584	if (pShwPage->iFirstPresent > iPTDst)
1585	pShwPage->iFirstPresent = iPTDst;
1586	}
1587
1588
1589	/**
1590	* Modifies a shadow PTE to account for access handlers.
1591	*
1592	* @param pVM Pointer to the VM.
1593	* @param pPage The page in question.
1594	* @param fPteSrc The shadowed flags of the source PTE. Must include the
1595	* A (accessed) bit so it can be emulated correctly.
1596	* @param pPteDst The shadow PTE (output). This is temporary storage and
1597	* does not need to be set atomically.
1598	*/
1599	DECLINLINE(void) PGM_BTH_NAME(SyncHandlerPte)(PVM pVM, PCPGMPAGE pPage, uint64_t fPteSrc, PSHWPTE pPteDst)
1600	{
1601	NOREF(pVM);
1602	/** @todo r=bird: Are we actually handling dirty and access bits for pages with access handlers correctly? No.
1603	* Update: \#PF should deal with this before or after calling the handlers. It has all the info to do the job efficiently. */
1604	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1605	{
1606	LogFlow(("SyncHandlerPte: monitored page (%R[pgmpage]) -> mark read-only\n", pPage));
1607	#if PGM_SHW_TYPE == PGM_TYPE_EPT
1608	pPteDst->u = PGM_PAGE_GET_HCPHYS(pPage);
1609	pPteDst->n.u1Present = 1;
1610	pPteDst->n.u1Execute = 1;
1611	pPteDst->n.u1IgnorePAT = 1;
1612	pPteDst->n.u3EMT = VMX_EPT_MEMTYPE_WB;
1613	/* PteDst.n.u1Write = 0 && PteDst.n.u1Size = 0 */
1614	#else
1615	if (fPteSrc & X86_PTE_A)
1616	{
1617	SHW_PTE_SET(*pPteDst, fPteSrc \| PGM_PAGE_GET_HCPHYS(pPage));
1618	SHW_PTE_SET_RO(*pPteDst);
1619	}
1620	else
1621	SHW_PTE_SET(*pPteDst, 0);
1622	#endif
1623	}
1624	#ifdef PGM_WITH_MMIO_OPTIMIZATIONS
1625	# if PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
1626	else if ( PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
1627	&& ( BTH_IS_NP_ACTIVE(pVM)
1628	\|\| (fPteSrc & (X86_PTE_RW \| X86_PTE_US)) == X86_PTE_RW) /** @todo Remove X86_PTE_US here and pGstWalk->Core.fEffectiveUS before the sync page test. */
1629	# if PGM_SHW_TYPE == PGM_TYPE_AMD64
1630	&& pVM->pgm.s.fLessThan52PhysicalAddressBits
1631	# endif
1632	)
1633	{
1634	LogFlow(("SyncHandlerPte: MMIO page -> invalid \n"));
1635	# if PGM_SHW_TYPE == PGM_TYPE_EPT
1636	/* 25.2.3.1: Reserved physical address bit -> EPT Misconfiguration (exit 49) */
1637	pPteDst->u = pVM->pgm.s.HCPhysInvMmioPg;
1638	/* 25.2.3.1: bits 2:0 = 010b -> EPT Misconfiguration (exit 49) */
1639	pPteDst->n.u1Present = 0;
1640	pPteDst->n.u1Write = 1;
1641	pPteDst->n.u1Execute = 0;
1642	/* 25.2.3.1: leaf && 2:0 != 0 && u3Emt in {2, 3, 7} -> EPT Misconfiguration */
1643	pPteDst->n.u3EMT = 7;
1644	# else
1645	/* Set high page frame bits that MBZ (bankers on PAE, CPU dependent on AMD64). */
1646	SHW_PTE_SET(*pPteDst, pVM->pgm.s.HCPhysInvMmioPg \| X86_PTE_PAE_MBZ_MASK_NO_NX \| X86_PTE_P);
1647	# endif
1648	}
1649	# endif
1650	#endif /* PGM_WITH_MMIO_OPTIMIZATIONS */
1651	else
1652	{
1653	LogFlow(("SyncHandlerPte: monitored page (%R[pgmpage]) -> mark not present\n", pPage));
1654	SHW_PTE_SET(*pPteDst, 0);
1655	}
1656	/** @todo count these kinds of entries. */
1657	}
1658
1659
1660	/**
1661	* Creates a 4K shadow page for a guest page.
1662	*
1663	* For 4M pages the caller must convert the PDE4M to a PTE, this includes adjusting the
1664	* physical address. The PdeSrc argument only the flags are used. No page
1665	* structured will be mapped in this function.
1666	*
1667	* @param pVCpu Pointer to the VMCPU.
1668	* @param pPteDst Destination page table entry.
1669	* @param PdeSrc Source page directory entry (i.e. Guest OS page directory entry).
1670	* Can safely assume that only the flags are being used.
1671	* @param PteSrc Source page table entry (i.e. Guest OS page table entry).
1672	* @param pShwPage Pointer to the shadow page.
1673	* @param iPTDst The index into the shadow table.
1674	*
1675	* @remark Not used for 2/4MB pages!
1676	*/
1677	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1678	static void PGM_BTH_NAME(SyncPageWorker)(PVMCPU pVCpu, PSHWPTE pPteDst, GSTPDE PdeSrc, GSTPTE PteSrc,
1679	PPGMPOOLPAGE pShwPage, unsigned iPTDst)
1680	#else
1681	static void PGM_BTH_NAME(SyncPageWorker)(PVMCPU pVCpu, PSHWPTE pPteDst, RTGCPHYS GCPhysPage, PPGMPOOLPAGE pShwPage, unsigned iPTDst)
1682	#endif
1683	{
1684	PVM pVM = pVCpu->CTX_SUFF(pVM);
1685	RTGCPHYS GCPhysOldPage = NIL_RTGCPHYS;
1686
1687	#if defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT) \
1688	&& PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
1689	&& (PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_PAE /* pae/32bit combo */)
1690
1691	if (pShwPage->fDirty)
1692	{
1693	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1694	PGSTPT pGstPT;
1695
1696	/* Note that iPTDst can be used to index the guest PT even in the pae/32bit combo as we copy only half the table; see pgmPoolAddDirtyPage. */
1697	pGstPT = (PGSTPT)&pPool->aDirtyPages[pShwPage->idxDirtyEntry].aPage[0];
1698	GCPhysOldPage = GST_GET_PTE_GCPHYS(pGstPT->a[iPTDst]);
1699	pGstPT->a[iPTDst].u = PteSrc.u;
1700	}
1701	#else
1702	Assert(!pShwPage->fDirty);
1703	#endif
1704
1705	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1706	if ( PteSrc.n.u1Present
1707	&& GST_IS_PTE_VALID(pVCpu, PteSrc))
1708	#endif
1709	{
1710	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1711	RTGCPHYS GCPhysPage = GST_GET_PTE_GCPHYS(PteSrc);
1712	# endif
1713	PGM_A20_ASSERT_MASKED(pVCpu, GCPhysPage);
1714
1715	/*
1716	* Find the ram range.
1717	*/
1718	PPGMPAGE pPage;
1719	int rc = pgmPhysGetPageEx(pVM, GCPhysPage, &pPage);
1720	if (RT_SUCCESS(rc))
1721	{
1722	/* Ignore ballooned pages.
1723	Don't return errors or use a fatal assert here as part of a
1724	shadow sync range might included ballooned pages. */
1725	if (PGM_PAGE_IS_BALLOONED(pPage))
1726	{
1727	Assert(!SHW_PTE_IS_P(pPteDst)); /* @todo user tracking needs updating if this triggers. */
1728	return;
1729	}
1730
1731	#ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
1732	/* Make the page writable if necessary. */
1733	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
1734	&& ( PGM_PAGE_IS_ZERO(pPage)
1735	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1736	\|\| ( PteSrc.n.u1Write
1737	# else
1738	\|\| ( 1
1739	# endif
1740	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
1741	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
1742	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
1743	# endif
1744	# ifdef VBOX_WITH_PAGE_SHARING
1745	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
1746	# endif
1747	)
1748	)
1749	)
1750	{
1751	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhysPage);
1752	AssertRC(rc);
1753	}
1754	#endif
1755
1756	/*
1757	* Make page table entry.
1758	*/
1759	SHWPTE PteDst;
1760	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1761	uint64_t fGstShwPteFlags = GST_GET_PTE_SHW_FLAGS(pVCpu, PteSrc);
1762	# else
1763	uint64_t fGstShwPteFlags = X86_PTE_P \| X86_PTE_RW \| X86_PTE_US \| X86_PTE_A \| X86_PTE_D;
1764	# endif
1765	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1766	PGM_BTH_NAME(SyncHandlerPte)(pVM, pPage, fGstShwPteFlags, &PteDst);
1767	else
1768	{
1769	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1770	/*
1771	* If the page or page directory entry is not marked accessed,
1772	* we mark the page not present.
1773	*/
1774	if (!PteSrc.n.u1Accessed \|\| !PdeSrc.n.u1Accessed)
1775	{
1776	LogFlow(("SyncPageWorker: page and or page directory not accessed -> mark not present\n"));
1777	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,AccessedPage));
1778	SHW_PTE_SET(PteDst, 0);
1779	}
1780	/*
1781	* If the page is not flagged as dirty and is writable, then make it read-only, so we can set the dirty bit
1782	* when the page is modified.
1783	*/
1784	else if (!PteSrc.n.u1Dirty && (PdeSrc.n.u1Write & PteSrc.n.u1Write))
1785	{
1786	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPage));
1787	SHW_PTE_SET(PteDst,
1788	fGstShwPteFlags
1789	\| PGM_PAGE_GET_HCPHYS(pPage)
1790	\| PGM_PTFLAGS_TRACK_DIRTY);
1791	SHW_PTE_SET_RO(PteDst);
1792	}
1793	else
1794	#endif
1795	{
1796	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageSkipped));
1797	#if PGM_SHW_TYPE == PGM_TYPE_EPT
1798	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage);
1799	PteDst.n.u1Present = 1;
1800	PteDst.n.u1Write = 1;
1801	PteDst.n.u1Execute = 1;
1802	PteDst.n.u1IgnorePAT = 1;
1803	PteDst.n.u3EMT = VMX_EPT_MEMTYPE_WB;
1804	/* PteDst.n.u1Size = 0 */
1805	#else
1806	SHW_PTE_SET(PteDst, fGstShwPteFlags \| PGM_PAGE_GET_HCPHYS(pPage));
1807	#endif
1808	}
1809
1810	/*
1811	* Make sure only allocated pages are mapped writable.
1812	*/
1813	if ( SHW_PTE_IS_P_RW(PteDst)
1814	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
1815	{
1816	/* Still applies to shared pages. */
1817	Assert(!PGM_PAGE_IS_ZERO(pPage));
1818	SHW_PTE_SET_RO(PteDst); /** @todo this isn't quite working yet. Why, isn't it? */
1819	Log3(("SyncPageWorker: write-protecting %RGp pPage=%R[pgmpage]at iPTDst=%d\n", GCPhysPage, pPage, iPTDst));
1820	}
1821	}
1822
1823	/*
1824	* Keep user track up to date.
1825	*/
1826	if (SHW_PTE_IS_P(PteDst))
1827	{
1828	if (!SHW_PTE_IS_P(*pPteDst))
1829	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1830	else if (SHW_PTE_GET_HCPHYS(*pPteDst) != SHW_PTE_GET_HCPHYS(PteDst))
1831	{
1832	Log2(("SyncPageWorker: deref! pPteDst=%RX64 PteDst=%RX64\n", SHW_PTE_LOG64(pPteDst), SHW_PTE_LOG64(PteDst)));
1833	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPteDst), iPTDst, GCPhysOldPage);
1834	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1835	}
1836	}
1837	else if (SHW_PTE_IS_P(*pPteDst))
1838	{
1839	Log2(("SyncPageWorker: deref! pPteDst=%RX64\n", SHW_PTE_LOG64(pPteDst)));
1840	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPteDst), iPTDst, GCPhysOldPage);
1841	}
1842
1843	/*
1844	* Update statistics and commit the entry.
1845	*/
1846	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1847	if (!PteSrc.n.u1Global)
1848	pShwPage->fSeenNonGlobal = true;
1849	#endif
1850	SHW_PTE_ATOMIC_SET2(*pPteDst, PteDst);
1851	return;
1852	}
1853
1854	/** @todo count these three different kinds. */
1855	Log2(("SyncPageWorker: invalid address in Pte\n"));
1856	}
1857	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1858	else if (!PteSrc.n.u1Present)
1859	Log2(("SyncPageWorker: page not present in Pte\n"));
1860	else
1861	Log2(("SyncPageWorker: invalid Pte\n"));
1862	#endif
1863
1864	/*
1865	* The page is not present or the PTE is bad. Replace the shadow PTE by
1866	* an empty entry, making sure to keep the user tracking up to date.
1867	*/
1868	if (SHW_PTE_IS_P(*pPteDst))
1869	{
1870	Log2(("SyncPageWorker: deref! pPteDst=%RX64\n", SHW_PTE_LOG64(pPteDst)));
1871	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPteDst), iPTDst, GCPhysOldPage);
1872	}
1873	SHW_PTE_ATOMIC_SET(*pPteDst, 0);
1874	}
1875
1876
1877	/**
1878	* Syncs a guest OS page.
1879	*
1880	* There are no conflicts at this point, neither is there any need for
1881	* page table allocations.
1882	*
1883	* When called in PAE or AMD64 guest mode, the guest PDPE shall be valid.
1884	* When called in AMD64 guest mode, the guest PML4E shall be valid.
1885	*
1886	* @returns VBox status code.
1887	* @returns VINF_PGM_SYNCPAGE_MODIFIED_PDE if it modifies the PDE in any way.
1888	* @param pVCpu Pointer to the VMCPU.
1889	* @param PdeSrc Page directory entry of the guest.
1890	* @param GCPtrPage Guest context page address.
1891	* @param cPages Number of pages to sync (PGM_SYNC_N_PAGES) (default=1).
1892	* @param uErr Fault error (X86_TRAP_PF_*).
1893	*/
1894	static int PGM_BTH_NAME(SyncPage)(PVMCPU pVCpu, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr)
1895	{
1896	PVM pVM = pVCpu->CTX_SUFF(pVM);
1897	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool); NOREF(pPool);
1898	LogFlow(("SyncPage: GCPtrPage=%RGv cPages=%u uErr=%#x\n", GCPtrPage, cPages, uErr));
1899
1900	PGM_LOCK_ASSERT_OWNER(pVM);
1901
1902	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
1903	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
1904	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
1905	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
1906	&& PGM_SHW_TYPE != PGM_TYPE_EPT
1907
1908	/*
1909	* Assert preconditions.
1910	*/
1911	Assert(PdeSrc.n.u1Present);
1912	Assert(cPages);
1913	# if 0 /* rarely useful; leave for debugging. */
1914	STAM_COUNTER_INC(&pVCpu->pgm.s.StatSyncPagePD[(GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK]);
1915	# endif
1916
1917	/*
1918	* Get the shadow PDE, find the shadow page table in the pool.
1919	*/
1920	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1921	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1922	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
1923
1924	/* Fetch the pgm pool shadow descriptor. */
1925	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
1926	Assert(pShwPde);
1927
1928	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1929	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1930	PPGMPOOLPAGE pShwPde = NULL;
1931	PX86PDPAE pPDDst;
1932
1933	/* Fetch the pgm pool shadow descriptor. */
1934	int rc2 = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
1935	AssertRCSuccessReturn(rc2, rc2);
1936	Assert(pShwPde);
1937
1938	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
1939	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1940
1941	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1942	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1943	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1944	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
1945	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
1946
1947	int rc2 = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
1948	AssertRCSuccessReturn(rc2, rc2);
1949	Assert(pPDDst && pPdptDst);
1950	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1951	# endif
1952	SHWPDE PdeDst = *pPdeDst;
1953
1954	/*
1955	* - In the guest SMP case we could have blocked while another VCPU reused
1956	* this page table.
1957	* - With W7-64 we may also take this path when the A bit is cleared on
1958	* higher level tables (PDPE/PML4E). The guest does not invalidate the
1959	* relevant TLB entries. If we're write monitoring any page mapped by
1960	* the modified entry, we may end up here with a "stale" TLB entry.
1961	*/
1962	if (!PdeDst.n.u1Present)
1963	{
1964	Log(("CPU%u: SyncPage: Pde at %RGv changed behind our back? (pPdeDst=%p/%RX64) uErr=%#x\n", pVCpu->idCpu, GCPtrPage, pPdeDst, (uint64_t)PdeDst.u, (uint32_t)uErr));
1965	AssertMsg(pVM->cCpus > 1 \|\| (uErr & (X86_TRAP_PF_P \| X86_TRAP_PF_RW)) == (X86_TRAP_PF_P \| X86_TRAP_PF_RW),
1966	("Unexpected missing PDE p=%p/%RX64 uErr=%#x\n", pPdeDst, (uint64_t)PdeDst.u, (uint32_t)uErr));
1967	if (uErr & X86_TRAP_PF_P)
1968	PGM_INVL_PG(pVCpu, GCPtrPage);
1969	return VINF_SUCCESS; /* force the instruction to be executed again. */
1970	}
1971
1972	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1973	Assert(pShwPage);
1974
1975	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1976	/* Fetch the pgm pool shadow descriptor. */
1977	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
1978	Assert(pShwPde);
1979	# endif
1980
1981	/*
1982	* Check that the page is present and that the shadow PDE isn't out of sync.
1983	*/
1984	const bool fBigPage = PdeSrc.b.u1Size && GST_IS_PSE_ACTIVE(pVCpu);
1985	const bool fPdeValid = !fBigPage ? GST_IS_PDE_VALID(pVCpu, PdeSrc) : GST_IS_BIG_PDE_VALID(pVCpu, PdeSrc);
1986	RTGCPHYS GCPhys;
1987	if (!fBigPage)
1988	{
1989	GCPhys = GST_GET_PDE_GCPHYS(PdeSrc);
1990	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1991	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1992	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| ((iPDDst & 1) * (PAGE_SIZE / 2)));
1993	# endif
1994	}
1995	else
1996	{
1997	GCPhys = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
1998	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1999	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
2000	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| (GCPtrPage & (1 << X86_PD_PAE_SHIFT)));
2001	# endif
2002	}
2003	/** @todo This doesn't check the G bit of 2/4MB pages. FIXME */
2004	if ( fPdeValid
2005	&& pShwPage->GCPhys == GCPhys
2006	&& PdeSrc.n.u1Present
2007	&& PdeSrc.n.u1User == PdeDst.n.u1User
2008	&& (PdeSrc.n.u1Write == PdeDst.n.u1Write \|\| !PdeDst.n.u1Write)
2009	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2010	&& (PdeSrc.n.u1NoExecute == PdeDst.n.u1NoExecute \|\| !GST_IS_NX_ACTIVE(pVCpu))
2011	# endif
2012	)
2013	{
2014	/*
2015	* Check that the PDE is marked accessed already.
2016	* Since we set the accessed bit before getting here on a #PF, this
2017	* check is only meant for dealing with non-#PF'ing paths.
2018	*/
2019	if (PdeSrc.n.u1Accessed)
2020	{
2021	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2022	if (!fBigPage)
2023	{
2024	/*
2025	* 4KB Page - Map the guest page table.
2026	*/
2027	PGSTPT pPTSrc;
2028	int rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GST_GET_PDE_GCPHYS(PdeSrc), &pPTSrc);
2029	if (RT_SUCCESS(rc))
2030	{
2031	# ifdef PGM_SYNC_N_PAGES
2032	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
2033	if ( cPages > 1
2034	&& !(uErr & X86_TRAP_PF_P)
2035	&& !VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY))
2036	{
2037	/*
2038	* This code path is currently only taken when the caller is PGMTrap0eHandler
2039	* for non-present pages!
2040	*
2041	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
2042	* deal with locality.
2043	*/
2044	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2045	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2046	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2047	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
2048	# else
2049	const unsigned offPTSrc = 0;
2050	# endif
2051	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2052	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
2053	iPTDst = 0;
2054	else
2055	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2056
2057	for (; iPTDst < iPTDstEnd; iPTDst++)
2058	{
2059	const PGSTPTE pPteSrc = &pPTSrc->a[offPTSrc + iPTDst];
2060
2061	if ( pPteSrc->n.u1Present
2062	&& !SHW_PTE_IS_P(pPTDst->a[iPTDst]))
2063	{
2064	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(GST_PT_MASK << GST_PT_SHIFT)) \| ((offPTSrc + iPTDst) << PAGE_SHIFT);
2065	NOREF(GCPtrCurPage);
2066	# ifdef VBOX_WITH_RAW_MODE_NOT_R0
2067	/*
2068	* Assuming kernel code will be marked as supervisor - and not as user level
2069	* and executed using a conforming code selector - And marked as readonly.
2070	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
2071	*/
2072	PPGMPAGE pPage;
2073	if ( ((PdeSrc.u & pPteSrc->u) & (X86_PTE_RW \| X86_PTE_US))
2074	\|\| iPTDst == ((GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK) /* always sync GCPtrPage */
2075	\|\| !CSAMDoesPageNeedScanning(pVM, GCPtrCurPage)
2076	\|\| ( (pPage = pgmPhysGetPage(pVM, pPteSrc->u & GST_PTE_PG_MASK))
2077	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2078	)
2079	# endif /* else: CSAM not active */
2080	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, *pPteSrc, pShwPage, iPTDst);
2081	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
2082	GCPtrCurPage, pPteSrc->n.u1Present,
2083	pPteSrc->n.u1Write & PdeSrc.n.u1Write,
2084	pPteSrc->n.u1User & PdeSrc.n.u1User,
2085	(uint64_t)pPteSrc->u,
2086	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2087	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2088	}
2089	}
2090	}
2091	else
2092	# endif /* PGM_SYNC_N_PAGES */
2093	{
2094	const unsigned iPTSrc = (GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK;
2095	GSTPTE PteSrc = pPTSrc->a[iPTSrc];
2096	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2097	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2098	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx %s\n",
2099	GCPtrPage, PteSrc.n.u1Present,
2100	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2101	PteSrc.n.u1User & PdeSrc.n.u1User,
2102	(uint64_t)PteSrc.u,
2103	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2104	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2105	}
2106	}
2107	else /* MMIO or invalid page: emulated in #PF handler. */
2108	{
2109	LogFlow(("PGM_GCPHYS_2_PTR %RGp failed with %Rrc\n", GCPhys, rc));
2110	Assert(!SHW_PTE_IS_P(pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK]));
2111	}
2112	}
2113	else
2114	{
2115	/*
2116	* 4/2MB page - lazy syncing shadow 4K pages.
2117	* (There are many causes of getting here, it's no longer only CSAM.)
2118	*/
2119	/* Calculate the GC physical address of this 4KB shadow page. */
2120	GCPhys = PGM_A20_APPLY(pVCpu, GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc) \| (GCPtrPage & GST_BIG_PAGE_OFFSET_MASK));
2121	/* Find ram range. */
2122	PPGMPAGE pPage;
2123	int rc = pgmPhysGetPageEx(pVM, GCPhys, &pPage);
2124	if (RT_SUCCESS(rc))
2125	{
2126	AssertFatalMsg(!PGM_PAGE_IS_BALLOONED(pPage), ("Unexpected ballooned page at %RGp\n", GCPhys));
2127
2128	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
2129	/* Try to make the page writable if necessary. */
2130	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
2131	&& ( PGM_PAGE_IS_ZERO(pPage)
2132	\|\| ( PdeSrc.n.u1Write
2133	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
2134	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
2135	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
2136	# endif
2137	# ifdef VBOX_WITH_PAGE_SHARING
2138	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
2139	# endif
2140	)
2141	)
2142	)
2143	{
2144	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
2145	AssertRC(rc);
2146	}
2147	# endif
2148
2149	/*
2150	* Make shadow PTE entry.
2151	*/
2152	SHWPTE PteDst;
2153	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2154	PGM_BTH_NAME(SyncHandlerPte)(pVM, pPage, GST_GET_BIG_PDE_SHW_FLAGS_4_PTE(pVCpu, PdeSrc), &PteDst);
2155	else
2156	SHW_PTE_SET(PteDst, GST_GET_BIG_PDE_SHW_FLAGS_4_PTE(pVCpu, PdeSrc) \| PGM_PAGE_GET_HCPHYS(pPage));
2157
2158	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2159	if ( SHW_PTE_IS_P(PteDst)
2160	&& !SHW_PTE_IS_P(pPTDst->a[iPTDst]))
2161	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
2162
2163	/* Make sure only allocated pages are mapped writable. */
2164	if ( SHW_PTE_IS_P_RW(PteDst)
2165	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
2166	{
2167	/* Still applies to shared pages. */
2168	Assert(!PGM_PAGE_IS_ZERO(pPage));
2169	SHW_PTE_SET_RO(PteDst); /** @todo this isn't quite working yet... */
2170	Log3(("SyncPage: write-protecting %RGp pPage=%R[pgmpage] at %RGv\n", GCPhys, pPage, GCPtrPage));
2171	}
2172
2173	SHW_PTE_ATOMIC_SET2(pPTDst->a[iPTDst], PteDst);
2174
2175	/*
2176	* If the page is not flagged as dirty and is writable, then make it read-only
2177	* at PD level, so we can set the dirty bit when the page is modified.
2178	*
2179	* ASSUMES that page access handlers are implemented on page table entry level.
2180	* Thus we will first catch the dirty access and set PDE.D and restart. If
2181	* there is an access handler, we'll trap again and let it work on the problem.
2182	*/
2183	/** @todo r=bird: figure out why we need this here, SyncPT should've taken care of this already.
2184	* As for invlpg, it simply frees the whole shadow PT.
2185	* ...It's possibly because the guest clears it and the guest doesn't really tell us... */
2186	if ( !PdeSrc.b.u1Dirty
2187	&& PdeSrc.b.u1Write)
2188	{
2189	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageBig));
2190	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2191	PdeDst.n.u1Write = 0;
2192	}
2193	else
2194	{
2195	PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
2196	PdeDst.n.u1Write = PdeSrc.n.u1Write;
2197	}
2198	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2199	Log2(("SyncPage: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} GCPhys=%RGp%s\n",
2200	GCPtrPage, PdeSrc.n.u1Present, PdeSrc.n.u1Write, PdeSrc.n.u1User, (uint64_t)PdeSrc.u, GCPhys,
2201	PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2202	}
2203	else
2204	{
2205	LogFlow(("PGM_GCPHYS_2_PTR %RGp (big) failed with %Rrc\n", GCPhys, rc));
2206	/** @todo must wipe the shadow page table entry in this
2207	* case. */
2208	}
2209	}
2210	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2211	return VINF_SUCCESS;
2212	}
2213
2214	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPagePDNAs));
2215	}
2216	else if (fPdeValid)
2217	{
2218	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPagePDOutOfSync));
2219	Log2(("SyncPage: Out-Of-Sync PDE at %RGp PdeSrc=%RX64 PdeDst=%RX64 (GCPhys %RGp vs %RGp)\n",
2220	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, GCPhys));
2221	}
2222	else
2223	{
2224	/// @todo STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPagePDOutOfSyncAndInvalid));
2225	Log2(("SyncPage: Bad PDE at %RGp PdeSrc=%RX64 PdeDst=%RX64 (GCPhys %RGp vs %RGp)\n",
2226	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, GCPhys));
2227	}
2228
2229	/*
2230	* Mark the PDE not present. Restart the instruction and let #PF call SyncPT.
2231	* Yea, I'm lazy.
2232	*/
2233	pgmPoolFreeByPage(pPool, pShwPage, pShwPde->idx, iPDDst);
2234	ASMAtomicWriteSize(pPdeDst, 0);
2235
2236	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2237	PGM_INVL_VCPU_TLBS(pVCpu);
2238	return VINF_PGM_SYNCPAGE_MODIFIED_PDE;
2239
2240
2241	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2242	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2243	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2244	&& !defined(IN_RC)
2245	NOREF(PdeSrc);
2246
2247	# ifdef PGM_SYNC_N_PAGES
2248	/*
2249	* Get the shadow PDE, find the shadow page table in the pool.
2250	*/
2251	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2252	X86PDE PdeDst = pgmShwGet32BitPDE(pVCpu, GCPtrPage);
2253
2254	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2255	X86PDEPAE PdeDst = pgmShwGetPaePDE(pVCpu, GCPtrPage);
2256
2257	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2258	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2259	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64; NOREF(iPdpt);
2260	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
2261	X86PDEPAE PdeDst;
2262	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
2263
2264	int rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2265	AssertRCSuccessReturn(rc, rc);
2266	Assert(pPDDst && pPdptDst);
2267	PdeDst = pPDDst->a[iPDDst];
2268	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
2269	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2270	PEPTPD pPDDst;
2271	EPTPDE PdeDst;
2272
2273	int rc = pgmShwGetEPTPDPtr(pVCpu, GCPtrPage, NULL, &pPDDst);
2274	if (rc != VINF_SUCCESS)
2275	{
2276	AssertRC(rc);
2277	return rc;
2278	}
2279	Assert(pPDDst);
2280	PdeDst = pPDDst->a[iPDDst];
2281	# endif
2282	/* In the guest SMP case we could have blocked while another VCPU reused this page table. */
2283	if (!PdeDst.n.u1Present)
2284	{
2285	AssertMsg(pVM->cCpus > 1, ("Unexpected missing PDE %RX64\n", (uint64_t)PdeDst.u));
2286	Log(("CPU%d: SyncPage: Pde at %RGv changed behind our back!\n", pVCpu->idCpu, GCPtrPage));
2287	return VINF_SUCCESS; /* force the instruction to be executed again. */
2288	}
2289
2290	/* Can happen in the guest SMP case; other VCPU activated this PDE while we were blocking to handle the page fault. */
2291	if (PdeDst.n.u1Size)
2292	{
2293	Assert(pVM->pgm.s.fNestedPaging);
2294	Log(("CPU%d: SyncPage: Pde (big:%RX64) at %RGv changed behind our back!\n", pVCpu->idCpu, PdeDst.u, GCPtrPage));
2295	return VINF_SUCCESS;
2296	}
2297
2298	/* Mask away the page offset. */
2299	GCPtrPage &= ~((RTGCPTR)0xfff);
2300
2301	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
2302	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2303
2304	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
2305	if ( cPages > 1
2306	&& !(uErr & X86_TRAP_PF_P)
2307	&& !VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY))
2308	{
2309	/*
2310	* This code path is currently only taken when the caller is PGMTrap0eHandler
2311	* for non-present pages!
2312	*
2313	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
2314	* deal with locality.
2315	*/
2316	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2317	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2318	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
2319	iPTDst = 0;
2320	else
2321	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2322	for (; iPTDst < iPTDstEnd; iPTDst++)
2323	{
2324	if (!SHW_PTE_IS_P(pPTDst->a[iPTDst]))
2325	{
2326	RTGCPTR GCPtrCurPage = PGM_A20_APPLY(pVCpu, (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT))
2327	\| (iPTDst << PAGE_SHIFT));
2328
2329	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], GCPtrCurPage, pShwPage, iPTDst);
2330	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=1 RW=1 U=1} PteDst=%08llx%s\n",
2331	GCPtrCurPage,
2332	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2333	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2334
2335	if (RT_UNLIKELY(VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY)))
2336	break;
2337	}
2338	else
2339	Log4(("%RGv iPTDst=%x pPTDst->a[iPTDst] %RX64\n", (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT), iPTDst, SHW_PTE_LOG64(pPTDst->a[iPTDst]) ));
2340	}
2341	}
2342	else
2343	# endif /* PGM_SYNC_N_PAGES */
2344	{
2345	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2346	RTGCPTR GCPtrCurPage = PGM_A20_APPLY(pVCpu, (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT))
2347	\| (iPTDst << PAGE_SHIFT));
2348
2349	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], GCPtrCurPage, pShwPage, iPTDst);
2350
2351	Log2(("SyncPage: 4K %RGv PteSrc:{P=1 RW=1 U=1}PteDst=%08llx%s\n",
2352	GCPtrPage,
2353	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2354	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2355	}
2356	return VINF_SUCCESS;
2357
2358	#else
2359	NOREF(PdeSrc);
2360	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
2361	return VERR_PGM_NOT_USED_IN_MODE;
2362	#endif
2363	}
2364
2365
2366	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
2367
2368	/**
2369	* CheckPageFault helper for returning a page fault indicating a non-present
2370	* (NP) entry in the page translation structures.
2371	*
2372	* @returns VINF_EM_RAW_GUEST_TRAP.
2373	* @param pVCpu Pointer to the VMCPU.
2374	* @param uErr The error code of the shadow fault. Corrections to
2375	* TRPM's copy will be made if necessary.
2376	* @param GCPtrPage For logging.
2377	* @param uPageFaultLevel For logging.
2378	*/
2379	DECLINLINE(int) PGM_BTH_NAME(CheckPageFaultReturnNP)(PVMCPU pVCpu, uint32_t uErr, RTGCPTR GCPtrPage, unsigned uPageFaultLevel)
2380	{
2381	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyTrackRealPF));
2382	AssertMsg(!(uErr & X86_TRAP_PF_P), ("%#x\n", uErr));
2383	AssertMsg(!(uErr & X86_TRAP_PF_RSVD), ("%#x\n", uErr));
2384	if (uErr & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P))
2385	TRPMSetErrorCode(pVCpu, uErr & ~(X86_TRAP_PF_RSVD \| X86_TRAP_PF_P));
2386
2387	Log(("CheckPageFault: real page fault (notp) at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2388	return VINF_EM_RAW_GUEST_TRAP;
2389	}
2390
2391
2392	/**
2393	* CheckPageFault helper for returning a page fault indicating a reserved bit
2394	* (RSVD) error in the page translation structures.
2395	*
2396	* @returns VINF_EM_RAW_GUEST_TRAP.
2397	* @param pVCpu Pointer to the VMCPU.
2398	* @param uErr The error code of the shadow fault. Corrections to
2399	* TRPM's copy will be made if necessary.
2400	* @param GCPtrPage For logging.
2401	* @param uPageFaultLevel For logging.
2402	*/
2403	DECLINLINE(int) PGM_BTH_NAME(CheckPageFaultReturnRSVD)(PVMCPU pVCpu, uint32_t uErr, RTGCPTR GCPtrPage, unsigned uPageFaultLevel)
2404	{
2405	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyTrackRealPF));
2406	if ((uErr & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) != (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P))
2407	TRPMSetErrorCode(pVCpu, uErr \| X86_TRAP_PF_RSVD \| X86_TRAP_PF_P);
2408
2409	Log(("CheckPageFault: real page fault (rsvd) at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2410	return VINF_EM_RAW_GUEST_TRAP;
2411	}
2412
2413
2414	/**
2415	* CheckPageFault helper for returning a page protection fault (P).
2416	*
2417	* @returns VINF_EM_RAW_GUEST_TRAP.
2418	* @param pVCpu Pointer to the VMCPU.
2419	* @param uErr The error code of the shadow fault. Corrections to
2420	* TRPM's copy will be made if necessary.
2421	* @param GCPtrPage For logging.
2422	* @param uPageFaultLevel For logging.
2423	*/
2424	DECLINLINE(int) PGM_BTH_NAME(CheckPageFaultReturnProt)(PVMCPU pVCpu, uint32_t uErr, RTGCPTR GCPtrPage, unsigned uPageFaultLevel)
2425	{
2426	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyTrackRealPF));
2427	AssertMsg(uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US \| X86_TRAP_PF_ID), ("%#x\n", uErr));
2428	if ((uErr & (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD)) != X86_TRAP_PF_P)
2429	TRPMSetErrorCode(pVCpu, (uErr & ~X86_TRAP_PF_RSVD) \| X86_TRAP_PF_P);
2430
2431	Log(("CheckPageFault: real page fault (prot) at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2432	return VINF_EM_RAW_GUEST_TRAP;
2433	}
2434
2435
2436	/**
2437	* Handle dirty bit tracking faults.
2438	*
2439	* @returns VBox status code.
2440	* @param pVCpu Pointer to the VMCPU.
2441	* @param uErr Page fault error code.
2442	* @param pPdeSrc Guest page directory entry.
2443	* @param pPdeDst Shadow page directory entry.
2444	* @param GCPtrPage Guest context page address.
2445	*/
2446	static int PGM_BTH_NAME(CheckDirtyPageFault)(PVMCPU pVCpu, uint32_t uErr, PSHWPDE pPdeDst, GSTPDE const *pPdeSrc,
2447	RTGCPTR GCPtrPage)
2448	{
2449	PVM pVM = pVCpu->CTX_SUFF(pVM);
2450	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2451	NOREF(uErr);
2452
2453	PGM_LOCK_ASSERT_OWNER(pVM);
2454
2455	/*
2456	* Handle big page.
2457	*/
2458	if (pPdeSrc->b.u1Size && GST_IS_PSE_ACTIVE(pVCpu))
2459	{
2460	if ( pPdeDst->n.u1Present
2461	&& (pPdeDst->u & PGM_PDFLAGS_TRACK_DIRTY))
2462	{
2463	SHWPDE PdeDst = *pPdeDst;
2464
2465	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageTrap));
2466	Assert(pPdeSrc->b.u1Write);
2467
2468	/* Note: No need to invalidate this entry on other VCPUs as a stale TLB entry will not harm; write access will simply
2469	* fault again and take this path to only invalidate the entry (see below).
2470	*/
2471	PdeDst.n.u1Write = 1;
2472	PdeDst.n.u1Accessed = 1;
2473	PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
2474	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2475	PGM_INVL_BIG_PG(pVCpu, GCPtrPage);
2476	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2477	}
2478
2479	# ifdef IN_RING0
2480	/* Check for stale TLB entry; only applies to the SMP guest case. */
2481	if ( pVM->cCpus > 1
2482	&& pPdeDst->n.u1Write
2483	&& pPdeDst->n.u1Accessed)
2484	{
2485	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPdeDst->u & SHW_PDE_PG_MASK);
2486	if (pShwPage)
2487	{
2488	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2489	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2490	if (SHW_PTE_IS_P_RW(*pPteDst))
2491	{
2492	/* Stale TLB entry. */
2493	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageStale));
2494	PGM_INVL_PG(pVCpu, GCPtrPage);
2495	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2496	}
2497	}
2498	}
2499	# endif /* IN_RING0 */
2500	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2501	}
2502
2503	/*
2504	* Map the guest page table.
2505	*/
2506	PGSTPT pPTSrc;
2507	int rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GST_GET_PDE_GCPHYS(*pPdeSrc), &pPTSrc);
2508	if (RT_FAILURE(rc))
2509	{
2510	AssertRC(rc);
2511	return rc;
2512	}
2513
2514	if (pPdeDst->n.u1Present)
2515	{
2516	GSTPTE const *pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
2517	const GSTPTE PteSrc = *pPteSrc;
2518
2519	#ifdef VBOX_WITH_RAW_MODE_NOT_R0
2520	/* Bail out here as pgmPoolGetPage will return NULL and we'll crash below.
2521	* Our individual shadow handlers will provide more information and force a fatal exit.
2522	*/
2523	if ( !HMIsEnabled(pVM)
2524	&& MMHyperIsInsideArea(pVM, (RTGCPTR)GCPtrPage))
2525	{
2526	LogRel(("CheckPageFault: write to hypervisor region %RGv\n", GCPtrPage));
2527	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2528	}
2529	#endif
2530	/*
2531	* Map shadow page table.
2532	*/
2533	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPdeDst->u & SHW_PDE_PG_MASK);
2534	if (pShwPage)
2535	{
2536	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2537	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2538	if (SHW_PTE_IS_P(pPteDst)) /* @todo Optimize accessed bit emulation? */
2539	{
2540	if (SHW_PTE_IS_TRACK_DIRTY(*pPteDst))
2541	{
2542	PPGMPAGE pPage = pgmPhysGetPage(pVM, GST_GET_PTE_GCPHYS(PteSrc));
2543	SHWPTE PteDst = *pPteDst;
2544
2545	LogFlow(("DIRTY page trap addr=%RGv\n", GCPtrPage));
2546	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageTrap));
2547
2548	Assert(PteSrc.n.u1Write);
2549
2550	/* Note: No need to invalidate this entry on other VCPUs as a stale TLB
2551	* entry will not harm; write access will simply fault again and
2552	* take this path to only invalidate the entry.
2553	*/
2554	if (RT_LIKELY(pPage))
2555	{
2556	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2557	{
2558	//AssertMsgFailed(("%R[pgmpage] - we don't set PGM_PTFLAGS_TRACK_DIRTY for these pages\n", pPage));
2559	Assert(!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage));
2560	/* Assuming write handlers here as the PTE is present (otherwise we wouldn't be here). */
2561	SHW_PTE_SET_RO(PteDst);
2562	}
2563	else
2564	{
2565	if ( PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED
2566	&& PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
2567	{
2568	rc = pgmPhysPageMakeWritable(pVM, pPage, GST_GET_PTE_GCPHYS(PteSrc));
2569	AssertRC(rc);
2570	}
2571	if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED)
2572	SHW_PTE_SET_RW(PteDst);
2573	else
2574	{
2575	/* Still applies to shared pages. */
2576	Assert(!PGM_PAGE_IS_ZERO(pPage));
2577	SHW_PTE_SET_RO(PteDst);
2578	}
2579	}
2580	}
2581	else
2582	SHW_PTE_SET_RW(PteDst); /** @todo r=bird: This doesn't make sense to me. */
2583
2584	SHW_PTE_SET(PteDst, (SHW_PTE_GET_U(PteDst) \| X86_PTE_D \| X86_PTE_A) & ~(uint64_t)PGM_PTFLAGS_TRACK_DIRTY);
2585	SHW_PTE_ATOMIC_SET2(*pPteDst, PteDst);
2586	PGM_INVL_PG(pVCpu, GCPtrPage);
2587	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2588	}
2589
2590	# ifdef IN_RING0
2591	/* Check for stale TLB entry; only applies to the SMP guest case. */
2592	if ( pVM->cCpus > 1
2593	&& SHW_PTE_IS_RW(*pPteDst)
2594	&& SHW_PTE_IS_A(*pPteDst))
2595	{
2596	/* Stale TLB entry. */
2597	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageStale));
2598	PGM_INVL_PG(pVCpu, GCPtrPage);
2599	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2600	}
2601	# endif
2602	}
2603	}
2604	else
2605	AssertMsgFailed(("pgmPoolGetPageByHCPhys %RGp failed!\n", pPdeDst->u & SHW_PDE_PG_MASK));
2606	}
2607
2608	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2609	}
2610
2611	#endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
2612
2613
2614	/**
2615	* Sync a shadow page table.
2616	*
2617	* The shadow page table is not present in the shadow PDE.
2618	*
2619	* Handles mapping conflicts.
2620	*
2621	* This is called by VerifyAccessSyncPage, PrefetchPage, InvalidatePage (on
2622	* conflict), and Trap0eHandler.
2623	*
2624	* A precondition for this method is that the shadow PDE is not present. The
2625	* caller must take the PGM lock before checking this and continue to hold it
2626	* when calling this method.
2627	*
2628	* @returns VBox status code.
2629	* @param pVCpu Pointer to the VMCPU.
2630	* @param iPD Page directory index.
2631	* @param pPDSrc Source page directory (i.e. Guest OS page directory).
2632	* Assume this is a temporary mapping.
2633	* @param GCPtrPage GC Pointer of the page that caused the fault
2634	*/
2635	static int PGM_BTH_NAME(SyncPT)(PVMCPU pVCpu, unsigned iPDSrc, PGSTPD pPDSrc, RTGCPTR GCPtrPage)
2636	{
2637	PVM pVM = pVCpu->CTX_SUFF(pVM);
2638	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool); NOREF(pPool);
2639
2640	#if 0 /* rarely useful; leave for debugging. */
2641	STAM_COUNTER_INC(&pVCpu->pgm.s.StatSyncPtPD[iPDSrc]);
2642	#endif
2643	LogFlow(("SyncPT: GCPtrPage=%RGv\n", GCPtrPage));
2644
2645	PGM_LOCK_ASSERT_OWNER(pVM);
2646
2647	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
2648	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
2649	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
2650	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2651	&& PGM_SHW_TYPE != PGM_TYPE_EPT
2652
2653	int rc = VINF_SUCCESS;
2654
2655	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
2656
2657	/*
2658	* Some input validation first.
2659	*/
2660	AssertMsg(iPDSrc == ((GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK), ("iPDSrc=%x GCPtrPage=%RGv\n", iPDSrc, GCPtrPage));
2661
2662	/*
2663	* Get the relevant shadow PDE entry.
2664	*/
2665	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2666	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
2667	PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
2668
2669	/* Fetch the pgm pool shadow descriptor. */
2670	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
2671	Assert(pShwPde);
2672
2673	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2674	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2675	PPGMPOOLPAGE pShwPde = NULL;
2676	PX86PDPAE pPDDst;
2677	PSHWPDE pPdeDst;
2678
2679	/* Fetch the pgm pool shadow descriptor. */
2680	rc = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
2681	AssertRCSuccessReturn(rc, rc);
2682	Assert(pShwPde);
2683
2684	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
2685	pPdeDst = &pPDDst->a[iPDDst];
2686
2687	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2688	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
2689	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2690	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
2691	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
2692	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2693	AssertRCSuccessReturn(rc, rc);
2694	Assert(pPDDst);
2695	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2696	# endif
2697	SHWPDE PdeDst = *pPdeDst;
2698
2699	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2700	/* Fetch the pgm pool shadow descriptor. */
2701	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
2702	Assert(pShwPde);
2703	# endif
2704
2705	# ifndef PGM_WITHOUT_MAPPINGS
2706	/*
2707	* Check for conflicts.
2708	* RC: In case of a conflict we'll go to Ring-3 and do a full SyncCR3.
2709	* R3: Simply resolve the conflict.
2710	*/
2711	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
2712	{
2713	Assert(pgmMapAreMappingsEnabled(pVM));
2714	# ifndef IN_RING3
2715	Log(("SyncPT: Conflict at %RGv\n", GCPtrPage));
2716	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
2717	return VERR_ADDRESS_CONFLICT;
2718
2719	# else /* IN_RING3 */
2720	PPGMMAPPING pMapping = pgmGetMapping(pVM, (RTGCPTR)GCPtrPage);
2721	Assert(pMapping);
2722	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2723	rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2724	# elif PGM_GST_TYPE == PGM_TYPE_PAE
2725	rc = pgmR3SyncPTResolveConflictPAE(pVM, pMapping, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2726	# else
2727	AssertFailed(); NOREF(pMapping); /* can't happen for amd64 */
2728	# endif
2729	if (RT_FAILURE(rc))
2730	{
2731	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
2732	return rc;
2733	}
2734	PdeDst = *pPdeDst;
2735	# endif /* IN_RING3 */
2736	}
2737	# endif /* !PGM_WITHOUT_MAPPINGS */
2738	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
2739
2740	/*
2741	* Sync the page directory entry.
2742	*/
2743	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
2744	const bool fPageTable = !PdeSrc.b.u1Size \|\| !GST_IS_PSE_ACTIVE(pVCpu);
2745	if ( PdeSrc.n.u1Present
2746	&& (fPageTable ? GST_IS_PDE_VALID(pVCpu, PdeSrc) : GST_IS_BIG_PDE_VALID(pVCpu, PdeSrc)) )
2747	{
2748	/*
2749	* Allocate & map the page table.
2750	*/
2751	PSHWPT pPTDst;
2752	PPGMPOOLPAGE pShwPage;
2753	RTGCPHYS GCPhys;
2754	if (fPageTable)
2755	{
2756	GCPhys = GST_GET_PDE_GCPHYS(PdeSrc);
2757	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2758	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2759	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| ((iPDDst & 1) * (PAGE_SIZE / 2)));
2760	# endif
2761	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
2762	pShwPde->idx, iPDDst, false /fLockPage/,
2763	&pShwPage);
2764	}
2765	else
2766	{
2767	PGMPOOLACCESS enmAccess;
2768	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2769	const bool fNoExecute = PdeSrc.n.u1NoExecute && GST_IS_NX_ACTIVE(pVCpu);
2770	# else
2771	const bool fNoExecute = false;
2772	# endif
2773
2774	GCPhys = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
2775	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2776	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
2777	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| (GCPtrPage & (1 << X86_PD_PAE_SHIFT)));
2778	# endif
2779	/* Determine the right kind of large page to avoid incorrect cached entry reuse. */
2780	if (PdeSrc.n.u1User)
2781	{
2782	if (PdeSrc.n.u1Write)
2783	enmAccess = (fNoExecute) ? PGMPOOLACCESS_USER_RW_NX : PGMPOOLACCESS_USER_RW;
2784	else
2785	enmAccess = (fNoExecute) ? PGMPOOLACCESS_USER_R_NX : PGMPOOLACCESS_USER_R;
2786	}
2787	else
2788	{
2789	if (PdeSrc.n.u1Write)
2790	enmAccess = (fNoExecute) ? PGMPOOLACCESS_SUPERVISOR_RW_NX : PGMPOOLACCESS_SUPERVISOR_RW;
2791	else
2792	enmAccess = (fNoExecute) ? PGMPOOLACCESS_SUPERVISOR_R_NX : PGMPOOLACCESS_SUPERVISOR_R;
2793	}
2794	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_BIG, enmAccess, PGM_A20_IS_ENABLED(pVCpu),
2795	pShwPde->idx, iPDDst, false /fLockPage/,
2796	&pShwPage);
2797	}
2798	if (rc == VINF_SUCCESS)
2799	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2800	else if (rc == VINF_PGM_CACHED_PAGE)
2801	{
2802	/*
2803	* The PT was cached, just hook it up.
2804	*/
2805	if (fPageTable)
2806	PdeDst.u = pShwPage->Core.Key \| GST_GET_PDE_SHW_FLAGS(pVCpu, PdeSrc);
2807	else
2808	{
2809	PdeDst.u = pShwPage->Core.Key \| GST_GET_BIG_PDE_SHW_FLAGS(pVCpu, PdeSrc);
2810	/* (see explanation and assumptions further down.) */
2811	if ( !PdeSrc.b.u1Dirty
2812	&& PdeSrc.b.u1Write)
2813	{
2814	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageBig));
2815	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2816	PdeDst.b.u1Write = 0;
2817	}
2818	}
2819	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2820	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2821	return VINF_SUCCESS;
2822	}
2823	else if (rc == VERR_PGM_POOL_FLUSHED)
2824	{
2825	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2826	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2827	return VINF_PGM_SYNC_CR3;
2828	}
2829	else
2830	AssertMsgFailedReturn(("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
2831	/** @todo Why do we bother preserving X86_PDE_AVL_MASK here?
2832	* Both PGM_PDFLAGS_MAPPING and PGM_PDFLAGS_TRACK_DIRTY should be
2833	* irrelevant at this point. */
2834	PdeDst.u &= X86_PDE_AVL_MASK;
2835	PdeDst.u \|= pShwPage->Core.Key;
2836
2837	/*
2838	* Page directory has been accessed (this is a fault situation, remember).
2839	*/
2840	/** @todo
2841	* Well, when the caller is PrefetchPage or InvalidatePage is isn't a
2842	* fault situation. What's more, the Trap0eHandler has already set the
2843	* accessed bit. So, it's actually just VerifyAccessSyncPage which
2844	* might need setting the accessed flag.
2845	*
2846	* The best idea is to leave this change to the caller and add an
2847	* assertion that it's set already. */
2848	pPDSrc->a[iPDSrc].n.u1Accessed = 1;
2849	if (fPageTable)
2850	{
2851	/*
2852	* Page table - 4KB.
2853	*
2854	* Sync all or just a few entries depending on PGM_SYNC_N_PAGES.
2855	*/
2856	Log2(("SyncPT: 4K %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx}\n",
2857	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u));
2858	PGSTPT pPTSrc;
2859	rc = PGM_GCPHYS_2_PTR(pVM, GST_GET_PDE_GCPHYS(PdeSrc), &pPTSrc);
2860	if (RT_SUCCESS(rc))
2861	{
2862	/*
2863	* Start by syncing the page directory entry so CSAM's TLB trick works.
2864	*/
2865	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| X86_PDE_AVL_MASK))
2866	\| GST_GET_PDE_SHW_FLAGS(pVCpu, PdeSrc);
2867	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2868	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2869
2870	/*
2871	* Directory/page user or supervisor privilege: (same goes for read/write)
2872	*
2873	* Directory Page Combined
2874	* U/S U/S U/S
2875	* 0 0 0
2876	* 0 1 0
2877	* 1 0 0
2878	* 1 1 1
2879	*
2880	* Simple AND operation. Table listed for completeness.
2881	*
2882	*/
2883	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT4K));
2884	# ifdef PGM_SYNC_N_PAGES
2885	unsigned iPTBase = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2886	unsigned iPTDst = iPTBase;
2887	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2888	if (iPTDst <= PGM_SYNC_NR_PAGES / 2)
2889	iPTDst = 0;
2890	else
2891	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2892	# else /* !PGM_SYNC_N_PAGES */
2893	unsigned iPTDst = 0;
2894	const unsigned iPTDstEnd = RT_ELEMENTS(pPTDst->a);
2895	# endif /* !PGM_SYNC_N_PAGES */
2896	RTGCPTR GCPtrCur = (GCPtrPage & ~(RTGCPTR)((1 << SHW_PD_SHIFT) - 1))
2897	\| ((RTGCPTR)iPTDst << PAGE_SHIFT);
2898	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2899	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2900	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
2901	# else
2902	const unsigned offPTSrc = 0;
2903	# endif
2904	for (; iPTDst < iPTDstEnd; iPTDst++, GCPtrCur += PAGE_SIZE)
2905	{
2906	const unsigned iPTSrc = iPTDst + offPTSrc;
2907	const GSTPTE PteSrc = pPTSrc->a[iPTSrc];
2908
2909	if (PteSrc.n.u1Present)
2910	{
2911	# ifdef VBOX_WITH_RAW_MODE_NOT_R0
2912	/*
2913	* Assuming kernel code will be marked as supervisor - and not as user level
2914	* and executed using a conforming code selector - And marked as readonly.
2915	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
2916	*/
2917	PPGMPAGE pPage;
2918	if ( ((PdeSrc.u & pPTSrc->a[iPTSrc].u) & (X86_PTE_RW \| X86_PTE_US))
2919	\|\| !CSAMDoesPageNeedScanning(pVM, GCPtrCur)
2920	\|\| ( (pPage = pgmPhysGetPage(pVM, GST_GET_PTE_GCPHYS(PteSrc)))
2921	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2922	)
2923	# endif
2924	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2925	Log2(("SyncPT: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s dst.raw=%08llx iPTSrc=%x PdeSrc.u=%x physpte=%RGp\n",
2926	GCPtrCur,
2927	PteSrc.n.u1Present,
2928	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2929	PteSrc.n.u1User & PdeSrc.n.u1User,
2930	(uint64_t)PteSrc.u,
2931	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : "", SHW_PTE_LOG64(pPTDst->a[iPTDst]), iPTSrc, PdeSrc.au32[0],
2932	(RTGCPHYS)(GST_GET_PDE_GCPHYS(PdeSrc) + iPTSrc*sizeof(PteSrc)) ));
2933	}
2934	/* else: the page table was cleared by the pool */
2935	} /* for PTEs */
2936	}
2937	}
2938	else
2939	{
2940	/*
2941	* Big page - 2/4MB.
2942	*
2943	* We'll walk the ram range list in parallel and optimize lookups.
2944	* We will only sync one shadow page table at a time.
2945	*/
2946	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT4M));
2947
2948	/**
2949	* @todo It might be more efficient to sync only a part of the 4MB
2950	* page (similar to what we do for 4KB PDs).
2951	*/
2952
2953	/*
2954	* Start by syncing the page directory entry.
2955	*/
2956	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| (X86_PDE_AVL_MASK & ~PGM_PDFLAGS_TRACK_DIRTY)))
2957	\| GST_GET_BIG_PDE_SHW_FLAGS(pVCpu, PdeSrc);
2958
2959	/*
2960	* If the page is not flagged as dirty and is writable, then make it read-only
2961	* at PD level, so we can set the dirty bit when the page is modified.
2962	*
2963	* ASSUMES that page access handlers are implemented on page table entry level.
2964	* Thus we will first catch the dirty access and set PDE.D and restart. If
2965	* there is an access handler, we'll trap again and let it work on the problem.
2966	*/
2967	/** @todo move the above stuff to a section in the PGM documentation. */
2968	Assert(!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY));
2969	if ( !PdeSrc.b.u1Dirty
2970	&& PdeSrc.b.u1Write)
2971	{
2972	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageBig));
2973	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2974	PdeDst.b.u1Write = 0;
2975	}
2976	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2977	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2978
2979	/*
2980	* Fill the shadow page table.
2981	*/
2982	/* Get address and flags from the source PDE. */
2983	SHWPTE PteDstBase;
2984	SHW_PTE_SET(PteDstBase, GST_GET_BIG_PDE_SHW_FLAGS_4_PTE(pVCpu, PdeSrc));
2985
2986	/* Loop thru the entries in the shadow PT. */
2987	const RTGCPTR GCPtr = (GCPtrPage >> SHW_PD_SHIFT) << SHW_PD_SHIFT; NOREF(GCPtr);
2988	Log2(("SyncPT: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} Shw=%RGv GCPhys=%RGp %s\n",
2989	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u, GCPtr,
2990	GCPhys, PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2991	PPGMRAMRANGE pRam = pgmPhysGetRangeAtOrAbove(pVM, GCPhys);
2992	unsigned iPTDst = 0;
2993	while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2994	&& !VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY))
2995	{
2996	if (pRam && GCPhys >= pRam->GCPhys)
2997	{
2998	# ifndef PGM_WITH_A20
2999	unsigned iHCPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
3000	# endif
3001	do
3002	{
3003	/* Make shadow PTE. */
3004	# ifdef PGM_WITH_A20
3005	PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
3006	# else
3007	PPGMPAGE pPage = &pRam->aPages[iHCPage];
3008	# endif
3009	SHWPTE PteDst;
3010
3011	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
3012	/* Try to make the page writable if necessary. */
3013	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
3014	&& ( PGM_PAGE_IS_ZERO(pPage)
3015	\|\| ( SHW_PTE_IS_RW(PteDstBase)
3016	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
3017	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
3018	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
3019	# endif
3020	# ifdef VBOX_WITH_PAGE_SHARING
3021	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
3022	# endif
3023	&& !PGM_PAGE_IS_BALLOONED(pPage))
3024	)
3025	)
3026	{
3027	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
3028	AssertRCReturn(rc, rc);
3029	if (VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY))
3030	break;
3031	}
3032	# endif
3033
3034	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
3035	PGM_BTH_NAME(SyncHandlerPte)(pVM, pPage, SHW_PTE_GET_U(PteDstBase), &PteDst);
3036	else if (PGM_PAGE_IS_BALLOONED(pPage))
3037	SHW_PTE_SET(PteDst, 0); /* Handle ballooned pages at #PF time. */
3038	# ifdef VBOX_WITH_RAW_MODE_NOT_R0
3039	/*
3040	* Assuming kernel code will be marked as supervisor and not as user level and executed
3041	* using a conforming code selector. Don't check for readonly, as that implies the whole
3042	* 4MB can be code or readonly data. Linux enables write access for its large pages.
3043	*/
3044	else if ( !PdeSrc.n.u1User
3045	&& CSAMDoesPageNeedScanning(pVM, GCPtr \| (iPTDst << SHW_PT_SHIFT)))
3046	SHW_PTE_SET(PteDst, 0);
3047	# endif
3048	else
3049	SHW_PTE_SET(PteDst, PGM_PAGE_GET_HCPHYS(pPage) \| SHW_PTE_GET_U(PteDstBase));
3050
3051	/* Only map writable pages writable. */
3052	if ( SHW_PTE_IS_P_RW(PteDst)
3053	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
3054	{
3055	/* Still applies to shared pages. */
3056	Assert(!PGM_PAGE_IS_ZERO(pPage));
3057	SHW_PTE_SET_RO(PteDst); /** @todo this isn't quite working yet... */
3058	Log3(("SyncPT: write-protecting %RGp pPage=%R[pgmpage] at %RGv\n", GCPhys, pPage, (RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT))));
3059	}
3060
3061	if (SHW_PTE_IS_P(PteDst))
3062	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
3063
3064	/* commit it (not atomic, new table) */
3065	pPTDst->a[iPTDst] = PteDst;
3066	Log4(("SyncPT: BIG %RGv PteDst:{P=%d RW=%d U=%d raw=%08llx}%s\n",
3067	(RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT)), SHW_PTE_IS_P(PteDst), SHW_PTE_IS_RW(PteDst), SHW_PTE_IS_US(PteDst), SHW_PTE_LOG64(PteDst),
3068	SHW_PTE_IS_TRACK_DIRTY(PteDst) ? " Track-Dirty" : ""));
3069
3070	/* advance */
3071	GCPhys += PAGE_SIZE;
3072	PGM_A20_APPLY_TO_VAR(pVCpu, GCPhys);
3073	# ifndef PGM_WITH_A20
3074	iHCPage++;
3075	# endif
3076	iPTDst++;
3077	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
3078	&& GCPhys <= pRam->GCPhysLast);
3079
3080	/* Advance ram range list. */
3081	while (pRam && GCPhys > pRam->GCPhysLast)
3082	pRam = pRam->CTX_SUFF(pNext);
3083	}
3084	else if (pRam)
3085	{
3086	Log(("Invalid pages at %RGp\n", GCPhys));
3087	do
3088	{
3089	SHW_PTE_SET(pPTDst->a[iPTDst], 0); /* Invalid page, we must handle them manually. */
3090	GCPhys += PAGE_SIZE;
3091	iPTDst++;
3092	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
3093	&& GCPhys < pRam->GCPhys);
3094	PGM_A20_APPLY_TO_VAR(pVCpu,GCPhys);
3095	}
3096	else
3097	{
3098	Log(("Invalid pages at %RGp (2)\n", GCPhys));
3099	for ( ; iPTDst < RT_ELEMENTS(pPTDst->a); iPTDst++)
3100	SHW_PTE_SET(pPTDst->a[iPTDst], 0); /* Invalid page, we must handle them manually. */
3101	}
3102	} /* while more PTEs */
3103	} /* 4KB / 4MB */
3104	}
3105	else
3106	AssertRelease(!PdeDst.n.u1Present);
3107
3108	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3109	if (RT_FAILURE(rc))
3110	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPTFailed));
3111	return rc;
3112
3113	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
3114	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
3115	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
3116	&& !defined(IN_RC)
3117	NOREF(iPDSrc); NOREF(pPDSrc);
3118
3119	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3120
3121	/*
3122	* Validate input a little bit.
3123	*/
3124	int rc = VINF_SUCCESS;
3125	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3126	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
3127	PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
3128
3129	/* Fetch the pgm pool shadow descriptor. */
3130	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
3131	Assert(pShwPde);
3132
3133	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3134	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
3135	PPGMPOOLPAGE pShwPde = NULL; /* initialized to shut up gcc */
3136	PX86PDPAE pPDDst;
3137	PSHWPDE pPdeDst;
3138
3139	/* Fetch the pgm pool shadow descriptor. */
3140	rc = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
3141	AssertRCSuccessReturn(rc, rc);
3142	Assert(pShwPde);
3143
3144	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
3145	pPdeDst = &pPDDst->a[iPDDst];
3146
3147	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3148	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3149	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
3150	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
3151	PX86PDPT pPdptDst= NULL; /* initialized to shut up gcc */
3152	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
3153	AssertRCSuccessReturn(rc, rc);
3154	Assert(pPDDst);
3155	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
3156
3157	/* Fetch the pgm pool shadow descriptor. */
3158	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
3159	Assert(pShwPde);
3160
3161	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
3162	const unsigned iPdpt = (GCPtrPage >> EPT_PDPT_SHIFT) & EPT_PDPT_MASK;
3163	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3164	PEPTPD pPDDst;
3165	PEPTPDPT pPdptDst;
3166
3167	rc = pgmShwGetEPTPDPtr(pVCpu, GCPtrPage, &pPdptDst, &pPDDst);
3168	if (rc != VINF_SUCCESS)
3169	{
3170	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3171	AssertRC(rc);
3172	return rc;
3173	}
3174	Assert(pPDDst);
3175	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
3176
3177	/* Fetch the pgm pool shadow descriptor. */
3178	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & EPT_PDPTE_PG_MASK);
3179	Assert(pShwPde);
3180	# endif
3181	SHWPDE PdeDst = *pPdeDst;
3182
3183	Assert(!(PdeDst.u & PGM_PDFLAGS_MAPPING));
3184	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
3185
3186	# if defined(PGM_WITH_LARGE_PAGES) && PGM_SHW_TYPE != PGM_TYPE_32BIT && PGM_SHW_TYPE != PGM_TYPE_PAE
3187	if (BTH_IS_NP_ACTIVE(pVM))
3188	{
3189	/* Check if we allocated a big page before for this 2 MB range. */
3190	PPGMPAGE pPage;
3191	rc = pgmPhysGetPageEx(pVM, PGM_A20_APPLY(pVCpu, GCPtrPage & X86_PDE2M_PAE_PG_MASK), &pPage);
3192	if (RT_SUCCESS(rc))
3193	{
3194	RTHCPHYS HCPhys = NIL_RTHCPHYS;
3195	if (PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE)
3196	{
3197	if (PGM_A20_IS_ENABLED(pVCpu))
3198	{
3199	STAM_REL_COUNTER_INC(&pVM->pgm.s.StatLargePageReused);
3200	AssertRelease(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
3201	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3202	}
3203	else
3204	{
3205	PGM_PAGE_SET_PDE_TYPE(pVM, pPage, PGM_PAGE_PDE_TYPE_PDE_DISABLED);
3206	pVM->pgm.s.cLargePagesDisabled++;
3207	}
3208	}
3209	else if ( PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE_DISABLED
3210	&& PGM_A20_IS_ENABLED(pVCpu))
3211	{
3212	/* Recheck the entire 2 MB range to see if we can use it again as a large page. */
3213	rc = pgmPhysRecheckLargePage(pVM, GCPtrPage, pPage);
3214	if (RT_SUCCESS(rc))
3215	{
3216	Assert(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
3217	Assert(PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE);
3218	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3219	}
3220	}
3221	else if ( PGMIsUsingLargePages(pVM)
3222	&& PGM_A20_IS_ENABLED(pVCpu))
3223	{
3224	rc = pgmPhysAllocLargePage(pVM, GCPtrPage);
3225	if (RT_SUCCESS(rc))
3226	{
3227	Assert(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
3228	Assert(PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE);
3229	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3230	}
3231	else
3232	LogFlow(("pgmPhysAllocLargePage failed with %Rrc\n", rc));
3233	}
3234
3235	if (HCPhys != NIL_RTHCPHYS)
3236	{
3237	PdeDst.u &= X86_PDE_AVL_MASK;
3238	PdeDst.u \|= HCPhys;
3239	PdeDst.n.u1Present = 1;
3240	PdeDst.n.u1Write = 1;
3241	PdeDst.b.u1Size = 1;
3242	# if PGM_SHW_TYPE == PGM_TYPE_EPT
3243	PdeDst.n.u1Execute = 1;
3244	PdeDst.b.u1IgnorePAT = 1;
3245	PdeDst.b.u3EMT = VMX_EPT_MEMTYPE_WB;
3246	# else
3247	PdeDst.n.u1User = 1;
3248	# endif
3249	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
3250
3251	Log(("SyncPT: Use large page at %RGp PDE=%RX64\n", GCPtrPage, PdeDst.u));
3252	/* Add a reference to the first page only. */
3253	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPde, PGM_PAGE_GET_TRACKING(pPage), pPage, iPDDst);
3254
3255	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3256	return VINF_SUCCESS;
3257	}
3258	}
3259	}
3260	# endif /* HC_ARCH_BITS == 64 */
3261
3262	/*
3263	* Allocate & map the page table.
3264	*/
3265	PSHWPT pPTDst;
3266	PPGMPOOLPAGE pShwPage;
3267	RTGCPHYS GCPhys;
3268
3269	/* Virtual address = physical address */
3270	GCPhys = PGM_A20_APPLY(pVCpu, GCPtrPage & X86_PAGE_4K_BASE_MASK);
3271	rc = pgmPoolAlloc(pVM, GCPhys & ~(RT_BIT_64(SHW_PD_SHIFT) - 1), BTH_PGMPOOLKIND_PT_FOR_PT, PGMPOOLACCESS_DONTCARE,
3272	PGM_A20_IS_ENABLED(pVCpu), pShwPde->idx, iPDDst, false /fLockPage/,
3273	&pShwPage);
3274	if ( rc == VINF_SUCCESS
3275	\|\| rc == VINF_PGM_CACHED_PAGE)
3276	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
3277	else
3278	{
3279	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3280	AssertMsgFailedReturn(("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
3281	}
3282
3283	if (rc == VINF_SUCCESS)
3284	{
3285	/* New page table; fully set it up. */
3286	Assert(pPTDst);
3287
3288	/* Mask away the page offset. */
3289	GCPtrPage &= ~(RTGCPTR)PAGE_OFFSET_MASK;
3290
3291	for (unsigned iPTDst = 0; iPTDst < RT_ELEMENTS(pPTDst->a); iPTDst++)
3292	{
3293	RTGCPTR GCPtrCurPage = PGM_A20_APPLY(pVCpu, (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT))
3294	\| (iPTDst << PAGE_SHIFT));
3295
3296	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], GCPtrCurPage, pShwPage, iPTDst);
3297	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=1 RW=1 U=1} PteDst=%08llx%s\n",
3298	GCPtrCurPage,
3299	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
3300	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
3301
3302	if (RT_UNLIKELY(VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY)))
3303	break;
3304	}
3305	}
3306	else
3307	rc = VINF_SUCCESS; /* Cached entry; assume it's still fully valid. */
3308
3309	/* Save the new PDE. */
3310	PdeDst.u &= X86_PDE_AVL_MASK;
3311	PdeDst.u \|= pShwPage->Core.Key;
3312	PdeDst.n.u1Present = 1;
3313	PdeDst.n.u1Write = 1;
3314	# if PGM_SHW_TYPE == PGM_TYPE_EPT
3315	PdeDst.n.u1Execute = 1;
3316	# else
3317	PdeDst.n.u1User = 1;
3318	PdeDst.n.u1Accessed = 1;
3319	# endif
3320	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
3321
3322	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3323	if (RT_FAILURE(rc))
3324	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPTFailed));
3325	return rc;
3326
3327	#else
3328	NOREF(iPDSrc); NOREF(pPDSrc);
3329	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_SHW_TYPE, PGM_GST_TYPE));
3330	return VERR_PGM_NOT_USED_IN_MODE;
3331	#endif
3332	}
3333
3334
3335
3336	/**
3337	* Prefetch a page/set of pages.
3338	*
3339	* Typically used to sync commonly used pages before entering raw mode
3340	* after a CR3 reload.
3341	*
3342	* @returns VBox status code.
3343	* @param pVCpu Pointer to the VMCPU.
3344	* @param GCPtrPage Page to invalidate.
3345	*/
3346	PGM_BTH_DECL(int, PrefetchPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage)
3347	{
3348	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
3349	\|\| PGM_GST_TYPE == PGM_TYPE_REAL \
3350	\|\| PGM_GST_TYPE == PGM_TYPE_PROT \
3351	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3352	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64 ) \
3353	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
3354	&& PGM_SHW_TYPE != PGM_TYPE_EPT
3355
3356	/*
3357	* Check that all Guest levels thru the PDE are present, getting the
3358	* PD and PDE in the processes.
3359	*/
3360	int rc = VINF_SUCCESS;
3361	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3362	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3363	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
3364	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
3365	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3366	unsigned iPDSrc;
3367	X86PDPE PdpeSrc;
3368	PGSTPD pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtrPage, &iPDSrc, &PdpeSrc);
3369	if (!pPDSrc)
3370	return VINF_SUCCESS; /* not present */
3371	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
3372	unsigned iPDSrc;
3373	PX86PML4E pPml4eSrc;
3374	X86PDPE PdpeSrc;
3375	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3376	if (!pPDSrc)
3377	return VINF_SUCCESS; /* not present */
3378	# endif
3379	const GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
3380	# else
3381	PGSTPD pPDSrc = NULL;
3382	const unsigned iPDSrc = 0;
3383	GSTPDE PdeSrc;
3384
3385	PdeSrc.u = 0; /* faked so we don't have to #ifdef everything */
3386	PdeSrc.n.u1Present = 1;
3387	PdeSrc.n.u1Write = 1;
3388	PdeSrc.n.u1Accessed = 1;
3389	PdeSrc.n.u1User = 1;
3390	# endif
3391
3392	if (PdeSrc.n.u1Present && PdeSrc.n.u1Accessed)
3393	{
3394	PVM pVM = pVCpu->CTX_SUFF(pVM);
3395	pgmLock(pVM);
3396
3397	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3398	const X86PDE PdeDst = pgmShwGet32BitPDE(pVCpu, GCPtrPage);
3399	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3400	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3401	PX86PDPAE pPDDst;
3402	X86PDEPAE PdeDst;
3403	# if PGM_GST_TYPE != PGM_TYPE_PAE
3404	X86PDPE PdpeSrc;
3405
3406	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
3407	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
3408	# endif
3409	rc = pgmShwSyncPaePDPtr(pVCpu, GCPtrPage, PdpeSrc.u, &pPDDst);
3410	if (rc != VINF_SUCCESS)
3411	{
3412	pgmUnlock(pVM);
3413	AssertRC(rc);
3414	return rc;
3415	}
3416	Assert(pPDDst);
3417	PdeDst = pPDDst->a[iPDDst];
3418
3419	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3420	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3421	PX86PDPAE pPDDst;
3422	X86PDEPAE PdeDst;
3423
3424	# if PGM_GST_TYPE == PGM_TYPE_PROT
3425	/* AMD-V nested paging */
3426	X86PML4E Pml4eSrc;
3427	X86PDPE PdpeSrc;
3428	PX86PML4E pPml4eSrc = &Pml4eSrc;
3429
3430	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
3431	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A;
3432	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A;
3433	# endif
3434
3435	rc = pgmShwSyncLongModePDPtr(pVCpu, GCPtrPage, pPml4eSrc->u, PdpeSrc.u, &pPDDst);
3436	if (rc != VINF_SUCCESS)
3437	{
3438	pgmUnlock(pVM);
3439	AssertRC(rc);
3440	return rc;
3441	}
3442	Assert(pPDDst);
3443	PdeDst = pPDDst->a[iPDDst];
3444	# endif
3445	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
3446	{
3447	if (!PdeDst.n.u1Present)
3448	{
3449	/** @todo r=bird: This guy will set the A bit on the PDE,
3450	* probably harmless. */
3451	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
3452	}
3453	else
3454	{
3455	/* Note! We used to sync PGM_SYNC_NR_PAGES pages, which triggered assertions in CSAM, because
3456	* R/W attributes of nearby pages were reset. Not sure how that could happen. Anyway, it
3457	* makes no sense to prefetch more than one page.
3458	*/
3459	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
3460	if (RT_SUCCESS(rc))
3461	rc = VINF_SUCCESS;
3462	}
3463	}
3464	pgmUnlock(pVM);
3465	}
3466	return rc;
3467
3468	#elif PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3469	NOREF(pVCpu); NOREF(GCPtrPage);
3470	return VINF_SUCCESS; /* ignore */
3471	#else
3472	AssertCompile(0);
3473	#endif
3474	}
3475
3476
3477
3478
3479	/**
3480	* Syncs a page during a PGMVerifyAccess() call.
3481	*
3482	* @returns VBox status code (informational included).
3483	* @param pVCpu Pointer to the VMCPU.
3484	* @param GCPtrPage The address of the page to sync.
3485	* @param fPage The effective guest page flags.
3486	* @param uErr The trap error code.
3487	* @remarks This will normally never be called on invalid guest page
3488	* translation entries.
3489	*/
3490	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fPage, unsigned uErr)
3491	{
3492	PVM pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
3493
3494	LogFlow(("VerifyAccessSyncPage: GCPtrPage=%RGv fPage=%#x uErr=%#x\n", GCPtrPage, fPage, uErr));
3495
3496	Assert(!pVM->pgm.s.fNestedPaging);
3497	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
3498	\|\| PGM_GST_TYPE == PGM_TYPE_REAL \
3499	\|\| PGM_GST_TYPE == PGM_TYPE_PROT \
3500	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3501	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64 ) \
3502	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
3503	&& PGM_SHW_TYPE != PGM_TYPE_EPT
3504
3505	# ifdef VBOX_WITH_RAW_MODE_NOT_R0
3506	if (!(fPage & X86_PTE_US))
3507	{
3508	/*
3509	* Mark this page as safe.
3510	*/
3511	/** @todo not correct for pages that contain both code and data!! */
3512	Log(("CSAMMarkPage %RGv; scanned=%d\n", GCPtrPage, true));
3513	CSAMMarkPage(pVM, GCPtrPage, true);
3514	}
3515	# endif
3516
3517	/*
3518	* Get guest PD and index.
3519	*/
3520	/** @todo Performance: We've done all this a jiffy ago in the
3521	* PGMGstGetPage call. */
3522	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3523	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3524	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
3525	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
3526
3527	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3528	unsigned iPDSrc = 0;
3529	X86PDPE PdpeSrc;
3530	PGSTPD pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtrPage, &iPDSrc, &PdpeSrc);
3531	if (RT_UNLIKELY(!pPDSrc))
3532	{
3533	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
3534	return VINF_EM_RAW_GUEST_TRAP;
3535	}
3536
3537	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
3538	unsigned iPDSrc = 0; /* shut up gcc */
3539	PX86PML4E pPml4eSrc = NULL; /* ditto */
3540	X86PDPE PdpeSrc;
3541	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3542	if (RT_UNLIKELY(!pPDSrc))
3543	{
3544	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
3545	return VINF_EM_RAW_GUEST_TRAP;
3546	}
3547	# endif
3548
3549	# else /* !PGM_WITH_PAGING */
3550	PGSTPD pPDSrc = NULL;
3551	const unsigned iPDSrc = 0;
3552	# endif /* !PGM_WITH_PAGING */
3553	int rc = VINF_SUCCESS;
3554
3555	pgmLock(pVM);
3556
3557	/*
3558	* First check if the shadow pd is present.
3559	*/
3560	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3561	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
3562
3563	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3564	PX86PDEPAE pPdeDst;
3565	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3566	PX86PDPAE pPDDst;
3567	# if PGM_GST_TYPE != PGM_TYPE_PAE
3568	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
3569	X86PDPE PdpeSrc;
3570	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
3571	# endif
3572	rc = pgmShwSyncPaePDPtr(pVCpu, GCPtrPage, PdpeSrc.u, &pPDDst);
3573	if (rc != VINF_SUCCESS)
3574	{
3575	pgmUnlock(pVM);
3576	AssertRC(rc);
3577	return rc;
3578	}
3579	Assert(pPDDst);
3580	pPdeDst = &pPDDst->a[iPDDst];
3581
3582	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3583	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3584	PX86PDPAE pPDDst;
3585	PX86PDEPAE pPdeDst;
3586
3587	# if PGM_GST_TYPE == PGM_TYPE_PROT
3588	/* AMD-V nested paging: Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
3589	X86PML4E Pml4eSrc;
3590	X86PDPE PdpeSrc;
3591	PX86PML4E pPml4eSrc = &Pml4eSrc;
3592	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A;
3593	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A;
3594	# endif
3595
3596	rc = pgmShwSyncLongModePDPtr(pVCpu, GCPtrPage, pPml4eSrc->u, PdpeSrc.u, &pPDDst);
3597	if (rc != VINF_SUCCESS)
3598	{
3599	pgmUnlock(pVM);
3600	AssertRC(rc);
3601	return rc;
3602	}
3603	Assert(pPDDst);
3604	pPdeDst = &pPDDst->a[iPDDst];
3605	# endif
3606
3607	if (!pPdeDst->n.u1Present)
3608	{
3609	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
3610	if (rc != VINF_SUCCESS)
3611	{
3612	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
3613	pgmUnlock(pVM);
3614	AssertRC(rc);
3615	return rc;
3616	}
3617	}
3618
3619	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3620	/* Check for dirty bit fault */
3621	rc = PGM_BTH_NAME(CheckDirtyPageFault)(pVCpu, uErr, pPdeDst, &pPDSrc->a[iPDSrc], GCPtrPage);
3622	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
3623	Log(("PGMVerifyAccess: success (dirty)\n"));
3624	else
3625	# endif
3626	{
3627	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3628	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
3629	# else
3630	GSTPDE PdeSrc;
3631	PdeSrc.u = 0; /* faked so we don't have to #ifdef everything */
3632	PdeSrc.n.u1Present = 1;
3633	PdeSrc.n.u1Write = 1;
3634	PdeSrc.n.u1Accessed = 1;
3635	PdeSrc.n.u1User = 1;
3636	# endif
3637
3638	Assert(rc != VINF_EM_RAW_GUEST_TRAP);
3639	if (uErr & X86_TRAP_PF_US)
3640	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncUser));
3641	else /* supervisor */
3642	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
3643
3644	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
3645	if (RT_SUCCESS(rc))
3646	{
3647	/* Page was successfully synced */
3648	Log2(("PGMVerifyAccess: success (sync)\n"));
3649	rc = VINF_SUCCESS;
3650	}
3651	else
3652	{
3653	Log(("PGMVerifyAccess: access violation for %RGv rc=%Rrc\n", GCPtrPage, rc));
3654	rc = VINF_EM_RAW_GUEST_TRAP;
3655	}
3656	}
3657	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
3658	pgmUnlock(pVM);
3659	return rc;
3660
3661	#else /* PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED */
3662
3663	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
3664	return VERR_PGM_NOT_USED_IN_MODE;
3665	#endif /* PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED */
3666	}
3667
3668
3669	/**
3670	* Syncs the paging hierarchy starting at CR3.
3671	*
3672	* @returns VBox status code, no specials.
3673	* @param pVCpu Pointer to the VMCPU.
3674	* @param cr0 Guest context CR0 register.
3675	* @param cr3 Guest context CR3 register. Not subjected to the A20
3676	* mask.
3677	* @param cr4 Guest context CR4 register.
3678	* @param fGlobal Including global page directories or not
3679	*/
3680	PGM_BTH_DECL(int, SyncCR3)(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
3681	{
3682	PVM pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
3683	NOREF(cr0); NOREF(cr3); NOREF(cr4); NOREF(fGlobal);
3684
3685	LogFlow(("SyncCR3 FF=%d fGlobal=%d\n", !!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3), fGlobal));
3686
3687	#if PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
3688
3689	pgmLock(pVM);
3690
3691	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
3692	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3693	if (pPool->cDirtyPages)
3694	pgmPoolResetDirtyPages(pVM);
3695	# endif
3696
3697	/*
3698	* Update page access handlers.
3699	* The virtual are always flushed, while the physical are only on demand.
3700	* WARNING: We are incorrectly not doing global flushing on Virtual Handler updates. We'll
3701	* have to look into that later because it will have a bad influence on the performance.
3702	* @note SvL: There's no need for that. Just invalidate the virtual range(s).
3703	* bird: Yes, but that won't work for aliases.
3704	*/
3705	/** @todo this MUST go away. See @bugref{1557}. */
3706	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3Handlers), h);
3707	PGM_GST_NAME(HandlerVirtualUpdate)(pVM, cr4);
3708	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3Handlers), h);
3709	pgmUnlock(pVM);
3710	#endif /* !NESTED && !EPT */
3711
3712	#if PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3713	/*
3714	* Nested / EPT - almost no work.
3715	*/
3716	Assert(!pgmMapAreMappingsEnabled(pVM));
3717	return VINF_SUCCESS;
3718
3719	#elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3720	/*
3721	* AMD64 (Shw & Gst) - No need to check all paging levels; we zero
3722	* out the shadow parts when the guest modifies its tables.
3723	*/
3724	Assert(!pgmMapAreMappingsEnabled(pVM));
3725	return VINF_SUCCESS;
3726
3727	#else /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
3728
3729	# ifndef PGM_WITHOUT_MAPPINGS
3730	/*
3731	* Check for and resolve conflicts with our guest mappings if they
3732	* are enabled and not fixed.
3733	*/
3734	if (pgmMapAreMappingsFloating(pVM))
3735	{
3736	int rc = pgmMapResolveConflicts(pVM);
3737	Assert(rc == VINF_SUCCESS \|\| rc == VINF_PGM_SYNC_CR3);
3738	if (rc == VINF_PGM_SYNC_CR3)
3739	{
3740	LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
3741	return VINF_PGM_SYNC_CR3;
3742	}
3743	}
3744	# else
3745	Assert(!pgmMapAreMappingsEnabled(pVM));
3746	# endif
3747	return VINF_SUCCESS;
3748	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
3749	}
3750
3751
3752
3753
3754	#ifdef VBOX_STRICT
3755	# ifdef IN_RC
3756	# undef AssertMsgFailed
3757	# define AssertMsgFailed Log
3758	# endif
3759
3760	/**
3761	* Checks that the shadow page table is in sync with the guest one.
3762	*
3763	* @returns The number of errors.
3764	* @param pVM The virtual machine.
3765	* @param pVCpu Pointer to the VMCPU.
3766	* @param cr3 Guest context CR3 register.
3767	* @param cr4 Guest context CR4 register.
3768	* @param GCPtr Where to start. Defaults to 0.
3769	* @param cb How much to check. Defaults to everything.
3770	*/
3771	PGM_BTH_DECL(unsigned, AssertCR3)(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb)
3772	{
3773	NOREF(pVCpu); NOREF(cr3); NOREF(cr4); NOREF(GCPtr); NOREF(cb);
3774	#if PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3775	return 0;
3776	#else
3777	unsigned cErrors = 0;
3778	PVM pVM = pVCpu->CTX_SUFF(pVM);
3779	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool); NOREF(pPool);
3780
3781	# if PGM_GST_TYPE == PGM_TYPE_PAE
3782	/** @todo currently broken; crashes below somewhere */
3783	AssertFailed();
3784	# endif
3785
3786	# if PGM_GST_TYPE == PGM_TYPE_32BIT \
3787	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3788	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
3789
3790	bool fBigPagesSupported = GST_IS_PSE_ACTIVE(pVCpu);
3791	PPGMCPU pPGM = &pVCpu->pgm.s;
3792	RTGCPHYS GCPhysGst; /* page address derived from the guest page tables. */
3793	RTHCPHYS HCPhysShw; /* page address derived from the shadow page tables. */
3794	# ifndef IN_RING0
3795	RTHCPHYS HCPhys; /* general usage. */
3796	# endif
3797	int rc;
3798
3799	/*
3800	* Check that the Guest CR3 and all its mappings are correct.
3801	*/
3802	AssertMsgReturn(pPGM->GCPhysCR3 == PGM_A20_APPLY(pVCpu, cr3 & GST_CR3_PAGE_MASK),
3803	("Invalid GCPhysCR3=%RGp cr3=%RGp\n", pPGM->GCPhysCR3, (RTGCPHYS)cr3),
3804	false);
3805	# if !defined(IN_RING0) && PGM_GST_TYPE != PGM_TYPE_AMD64
3806	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3807	rc = PGMShwGetPage(pVCpu, (RTRCUINTPTR)pPGM->pGst32BitPdRC, NULL, &HCPhysShw);
3808	# else
3809	rc = PGMShwGetPage(pVCpu, (RTRCUINTPTR)pPGM->pGstPaePdptRC, NULL, &HCPhysShw);
3810	# endif
3811	AssertRCReturn(rc, 1);
3812	HCPhys = NIL_RTHCPHYS;
3813	rc = pgmRamGCPhys2HCPhys(pVM, PGM_A20_APPLY(pVCpu, cr3 & GST_CR3_PAGE_MASK), &HCPhys);
3814	AssertMsgReturn(HCPhys == HCPhysShw, ("HCPhys=%RHp HCPhyswShw=%RHp (cr3)\n", HCPhys, HCPhysShw), false);
3815	# if PGM_GST_TYPE == PGM_TYPE_32BIT && defined(IN_RING3)
3816	pgmGstGet32bitPDPtr(pVCpu);
3817	RTGCPHYS GCPhys;
3818	rc = PGMR3DbgR3Ptr2GCPhys(pVM->pUVM, pPGM->pGst32BitPdR3, &GCPhys);
3819	AssertRCReturn(rc, 1);
3820	AssertMsgReturn(PGM_A20_APPLY(pVCpu, cr3 & GST_CR3_PAGE_MASK) == GCPhys, ("GCPhys=%RGp cr3=%RGp\n", GCPhys, (RTGCPHYS)cr3), false);
3821	# endif
3822	# endif /* !IN_RING0 */
3823
3824	/*
3825	* Get and check the Shadow CR3.
3826	*/
3827	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3828	unsigned cPDEs = X86_PG_ENTRIES;
3829	unsigned cIncrement = X86_PG_ENTRIES * PAGE_SIZE;
3830	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3831	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3832	unsigned cPDEs = X86_PG_PAE_ENTRIES * 4; /* treat it as a 2048 entry table. */
3833	# else
3834	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3835	# endif
3836	unsigned cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3837	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3838	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3839	unsigned cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3840	# endif
3841	if (cb != ~(RTGCPTR)0)
3842	cPDEs = RT_MIN(cb >> SHW_PD_SHIFT, 1);
3843
3844	/** @todo call the other two PGMAssert() functions. /
3845
3846	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3847	unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3848
3849	for (; iPml4 < X86_PG_PAE_ENTRIES; iPml4++)
3850	{
3851	PPGMPOOLPAGE pShwPdpt = NULL;
3852	PX86PML4E pPml4eSrc;
3853	PX86PML4E pPml4eDst;
3854	RTGCPHYS GCPhysPdptSrc;
3855
3856	pPml4eSrc = pgmGstGetLongModePML4EPtr(pVCpu, iPml4);
3857	pPml4eDst = pgmShwGetLongModePML4EPtr(pVCpu, iPml4);
3858
3859	/* Fetch the pgm pool shadow descriptor if the shadow pml4e is present. */
3860	if (!pPml4eDst->n.u1Present)
3861	{
3862	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3863	continue;
3864	}
3865
3866	pShwPdpt = pgmPoolGetPage(pPool, pPml4eDst->u & X86_PML4E_PG_MASK);
3867	GCPhysPdptSrc = PGM_A20_APPLY(pVCpu, pPml4eSrc->u & X86_PML4E_PG_MASK);
3868
3869	if (pPml4eSrc->n.u1Present != pPml4eDst->n.u1Present)
3870	{
3871	AssertMsgFailed(("Present bit doesn't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3872	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3873	cErrors++;
3874	continue;
3875	}
3876
3877	if (GCPhysPdptSrc != pShwPdpt->GCPhys)
3878	{
3879	AssertMsgFailed(("Physical address doesn't match! iPml4 %d pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, pPml4eDst->u, pPml4eSrc->u, pShwPdpt->GCPhys, GCPhysPdptSrc));
3880	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3881	cErrors++;
3882	continue;
3883	}
3884
3885	if ( pPml4eDst->n.u1User != pPml4eSrc->n.u1User
3886	\|\| pPml4eDst->n.u1Write != pPml4eSrc->n.u1Write
3887	\|\| pPml4eDst->n.u1NoExecute != pPml4eSrc->n.u1NoExecute)
3888	{
3889	AssertMsgFailed(("User/Write/NoExec bits don't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3890	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3891	cErrors++;
3892	continue;
3893	}
3894	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
3895	{
3896	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
3897
3898	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
3899	/*
3900	* Check the PDPTEs too.
3901	*/
3902	unsigned iPdpt = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
3903
3904	for (;iPdpt <= SHW_PDPT_MASK; iPdpt++)
3905	{
3906	unsigned iPDSrc = 0; /* initialized to shut up gcc */
3907	PPGMPOOLPAGE pShwPde = NULL;
3908	PX86PDPE pPdpeDst;
3909	RTGCPHYS GCPhysPdeSrc;
3910	X86PDPE PdpeSrc;
3911	PdpeSrc.u = 0; /* initialized to shut up gcc 4.5 */
3912	# if PGM_GST_TYPE == PGM_TYPE_PAE
3913	PGSTPD pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtr, &iPDSrc, &PdpeSrc);
3914	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(pVCpu);
3915	# else
3916	PX86PML4E pPml4eSrcIgn;
3917	PX86PDPT pPdptDst;
3918	PX86PDPAE pPDDst;
3919	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtr, &pPml4eSrcIgn, &PdpeSrc, &iPDSrc);
3920
3921	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtr, NULL, &pPdptDst, &pPDDst);
3922	if (rc != VINF_SUCCESS)
3923	{
3924	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
3925	GCPtr += 512 * _2M;
3926	continue; /* next PDPTE */
3927	}
3928	Assert(pPDDst);
3929	# endif
3930	Assert(iPDSrc == 0);
3931
3932	pPdpeDst = &pPdptDst->a[iPdpt];
3933
3934	if (!pPdpeDst->n.u1Present)
3935	{
3936	GCPtr += 512 * _2M;
3937	continue; /* next PDPTE */
3938	}
3939
3940	pShwPde = pgmPoolGetPage(pPool, pPdpeDst->u & X86_PDPE_PG_MASK);
3941	GCPhysPdeSrc = PGM_A20_APPLY(pVCpu, PdpeSrc.u & X86_PDPE_PG_MASK);
3942
3943	if (pPdpeDst->n.u1Present != PdpeSrc.n.u1Present)
3944	{
3945	AssertMsgFailed(("Present bit doesn't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3946	GCPtr += 512 * _2M;
3947	cErrors++;
3948	continue;
3949	}
3950
3951	if (GCPhysPdeSrc != pShwPde->GCPhys)
3952	{
3953	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3954	AssertMsgFailed(("Physical address doesn't match! iPml4 %d iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3955	# else
3956	AssertMsgFailed(("Physical address doesn't match! iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3957	# endif
3958	GCPtr += 512 * _2M;
3959	cErrors++;
3960	continue;
3961	}
3962
3963	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3964	if ( pPdpeDst->lm.u1User != PdpeSrc.lm.u1User
3965	\|\| pPdpeDst->lm.u1Write != PdpeSrc.lm.u1Write
3966	\|\| pPdpeDst->lm.u1NoExecute != PdpeSrc.lm.u1NoExecute)
3967	{
3968	AssertMsgFailed(("User/Write/NoExec bits don't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3969	GCPtr += 512 * _2M;
3970	cErrors++;
3971	continue;
3972	}
3973	# endif
3974
3975	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
3976	{
3977	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
3978	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3979	GSTPD const *pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
3980	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3981	PCX86PD pPDDst = pgmShwGet32BitPDPtr(pVCpu);
3982	# endif
3983	# endif /* PGM_GST_TYPE == PGM_TYPE_32BIT */
3984	/*
3985	* Iterate the shadow page directory.
3986	*/
3987	GCPtr = (GCPtr >> SHW_PD_SHIFT) << SHW_PD_SHIFT;
3988	unsigned iPDDst = (GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK;
3989
3990	for (;
3991	iPDDst < cPDEs;
3992	iPDDst++, GCPtr += cIncrement)
3993	{
3994	# if PGM_SHW_TYPE == PGM_TYPE_PAE
3995	const SHWPDE PdeDst = *pgmShwGetPaePDEPtr(pVCpu, GCPtr);
3996	# else
3997	const SHWPDE PdeDst = pPDDst->a[iPDDst];
3998	# endif
3999	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
4000	{
4001	Assert(pgmMapAreMappingsEnabled(pVM));
4002	if ((PdeDst.u & X86_PDE_AVL_MASK) != PGM_PDFLAGS_MAPPING)
4003	{
4004	AssertMsgFailed(("Mapping shall only have PGM_PDFLAGS_MAPPING set! PdeDst.u=%#RX64\n", (uint64_t)PdeDst.u));
4005	cErrors++;
4006	continue;
4007	}
4008	}
4009	else if ( (PdeDst.u & X86_PDE_P)
4010	\|\| ((PdeDst.u & (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY)) == (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY))
4011	)
4012	{
4013	HCPhysShw = PdeDst.u & SHW_PDE_PG_MASK;
4014	PPGMPOOLPAGE pPoolPage = pgmPoolGetPage(pPool, HCPhysShw);
4015	if (!pPoolPage)
4016	{
4017	AssertMsgFailed(("Invalid page table address %RHp at %RGv! PdeDst=%#RX64\n",
4018	HCPhysShw, GCPtr, (uint64_t)PdeDst.u));
4019	cErrors++;
4020	continue;
4021	}
4022	const SHWPT pPTDst = (const SHWPT )PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pPoolPage);
4023
4024	if (PdeDst.u & (X86_PDE4M_PWT \| X86_PDE4M_PCD))
4025	{
4026	AssertMsgFailed(("PDE flags PWT and/or PCD is set at %RGv! These flags are not virtualized! PdeDst=%#RX64\n",
4027	GCPtr, (uint64_t)PdeDst.u));
4028	cErrors++;
4029	}
4030
4031	if (PdeDst.u & (X86_PDE4M_G \| X86_PDE4M_D))
4032	{
4033	AssertMsgFailed(("4K PDE reserved flags at %RGv! PdeDst=%#RX64\n",
4034	GCPtr, (uint64_t)PdeDst.u));
4035	cErrors++;
4036	}
4037
4038	const GSTPDE PdeSrc = pPDSrc->a[(iPDDst >> (GST_PD_SHIFT - SHW_PD_SHIFT)) & GST_PD_MASK];
4039	if (!PdeSrc.n.u1Present)
4040	{
4041	AssertMsgFailed(("Guest PDE at %RGv is not present! PdeDst=%#RX64 PdeSrc=%#RX64\n",
4042	GCPtr, (uint64_t)PdeDst.u, (uint64_t)PdeSrc.u));
4043	cErrors++;
4044	continue;
4045	}
4046
4047	if ( !PdeSrc.b.u1Size
4048	\|\| !fBigPagesSupported)
4049	{
4050	GCPhysGst = GST_GET_PDE_GCPHYS(PdeSrc);
4051	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
4052	GCPhysGst = PGM_A20_APPLY(pVCpu, GCPhysGst \| ((iPDDst & 1) * (PAGE_SIZE / 2)));
4053	# endif
4054	}
4055	else
4056	{
4057	# if PGM_GST_TYPE == PGM_TYPE_32BIT
4058	if (PdeSrc.u & X86_PDE4M_PG_HIGH_MASK)
4059	{
4060	AssertMsgFailed(("Guest PDE at %RGv is using PSE36 or similar! PdeSrc=%#RX64\n",
4061	GCPtr, (uint64_t)PdeSrc.u));
4062	cErrors++;
4063	continue;
4064	}
4065	# endif
4066	GCPhysGst = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
4067	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
4068	GCPhysGst = PGM_A20_APPLY(pVCpu, GCPhysGst \| (GCPtr & RT_BIT(X86_PAGE_2M_SHIFT)));
4069	# endif
4070	}
4071
4072	if ( pPoolPage->enmKind
4073	!= (!PdeSrc.b.u1Size \|\| !fBigPagesSupported ? BTH_PGMPOOLKIND_PT_FOR_PT : BTH_PGMPOOLKIND_PT_FOR_BIG))
4074	{
4075	AssertMsgFailed(("Invalid shadow page table kind %d at %RGv! PdeSrc=%#RX64\n",
4076	pPoolPage->enmKind, GCPtr, (uint64_t)PdeSrc.u));
4077	cErrors++;
4078	}
4079
4080	PPGMPAGE pPhysPage = pgmPhysGetPage(pVM, GCPhysGst);
4081	if (!pPhysPage)
4082	{
4083	AssertMsgFailed(("Cannot find guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
4084	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
4085	cErrors++;
4086	continue;
4087	}
4088
4089	if (GCPhysGst != pPoolPage->GCPhys)
4090	{
4091	AssertMsgFailed(("GCPhysGst=%RGp != pPage->GCPhys=%RGp at %RGv\n",
4092	GCPhysGst, pPoolPage->GCPhys, GCPtr));
4093	cErrors++;
4094	continue;
4095	}
4096
4097	if ( !PdeSrc.b.u1Size
4098	\|\| !fBigPagesSupported)
4099	{
4100	/*
4101	* Page Table.
4102	*/
4103	const GSTPT *pPTSrc;
4104	rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, PGM_A20_APPLY(pVCpu, GCPhysGst & ~(RTGCPHYS)(PAGE_SIZE - 1)),
4105	&pPTSrc);
4106	if (RT_FAILURE(rc))
4107	{
4108	AssertMsgFailed(("Cannot map/convert guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
4109	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
4110	cErrors++;
4111	continue;
4112	}
4113	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/))
4114	!= (PdeDst.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/)))
4115	{
4116	/// @todo We get here a lot on out-of-sync CR3 entries. The access handler should zap them to avoid false alarms here!
4117	// (This problem will go away when/if we shadow multiple CR3s.)
4118	AssertMsgFailed(("4K PDE flags mismatch at %RGv! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4119	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4120	cErrors++;
4121	continue;
4122	}
4123	if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
4124	{
4125	AssertMsgFailed(("4K PDEs cannot have PGM_PDFLAGS_TRACK_DIRTY set! GCPtr=%RGv PdeDst=%#RX64\n",
4126	GCPtr, (uint64_t)PdeDst.u));
4127	cErrors++;
4128	continue;
4129	}
4130
4131	/* iterate the page table. */
4132	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
4133	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
4134	const unsigned offPTSrc = ((GCPtr >> SHW_PD_SHIFT) & 1) * 512;
4135	# else
4136	const unsigned offPTSrc = 0;
4137	# endif
4138	for (unsigned iPT = 0, off = 0;
4139	iPT < RT_ELEMENTS(pPTDst->a);
4140	iPT++, off += PAGE_SIZE)
4141	{
4142	const SHWPTE PteDst = pPTDst->a[iPT];
4143
4144	/* skip not-present and dirty tracked entries. */
4145	if (!(SHW_PTE_GET_U(PteDst) & (X86_PTE_P \| PGM_PTFLAGS_TRACK_DIRTY))) /** @todo deal with ALL handlers and CSAM !P pages! */
4146	continue;
4147	Assert(SHW_PTE_IS_P(PteDst));
4148
4149	const GSTPTE PteSrc = pPTSrc->a[iPT + offPTSrc];
4150	if (!PteSrc.n.u1Present)
4151	{
4152	# ifdef IN_RING3
4153	PGMAssertHandlerAndFlagsInSync(pVM);
4154	DBGFR3PagingDumpEx(pVM->pUVM, pVCpu->idCpu, DBGFPGDMP_FLAGS_CURRENT_CR3 \| DBGFPGDMP_FLAGS_CURRENT_MODE
4155	\| DBGFPGDMP_FLAGS_GUEST \| DBGFPGDMP_FLAGS_HEADER \| DBGFPGDMP_FLAGS_PRINT_CR3,
4156	0, 0, UINT64_MAX, 99, NULL);
4157	# endif
4158	AssertMsgFailed(("Out of sync (!P) PTE at %RGv! PteSrc=%#RX64 PteDst=%#RX64 pPTSrc=%RGv iPTSrc=%x PdeSrc=%x physpte=%RGp\n",
4159	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst), pPTSrc, iPT + offPTSrc, PdeSrc.au32[0],
4160	(uint64_t)GST_GET_PDE_GCPHYS(PdeSrc) + (iPT + offPTSrc) * sizeof(PteSrc)));
4161	cErrors++;
4162	continue;
4163	}
4164
4165	uint64_t fIgnoreFlags = GST_PTE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_G \| X86_PTE_D \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT;
4166	# if 1 /** @todo sync accessed bit properly... */
4167	fIgnoreFlags \|= X86_PTE_A;
4168	# endif
4169
4170	/* match the physical addresses */
4171	HCPhysShw = SHW_PTE_GET_HCPHYS(PteDst);
4172	GCPhysGst = GST_GET_PTE_GCPHYS(PteSrc);
4173
4174	# ifdef IN_RING3
4175	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
4176	if (RT_FAILURE(rc))
4177	{
4178	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4179	{
4180	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
4181	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4182	cErrors++;
4183	continue;
4184	}
4185	}
4186	else if (HCPhysShw != (HCPhys & SHW_PTE_PG_MASK))
4187	{
4188	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4189	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4190	cErrors++;
4191	continue;
4192	}
4193	# endif
4194
4195	pPhysPage = pgmPhysGetPage(pVM, GCPhysGst);
4196	if (!pPhysPage)
4197	{
4198	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
4199	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4200	{
4201	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
4202	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4203	cErrors++;
4204	continue;
4205	}
4206	# endif
4207	if (SHW_PTE_IS_RW(PteDst))
4208	{
4209	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4210	GCPtr + off, GCPhysGst, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4211	cErrors++;
4212	}
4213	fIgnoreFlags \|= X86_PTE_RW;
4214	}
4215	else if (HCPhysShw != PGM_PAGE_GET_HCPHYS(pPhysPage))
4216	{
4217	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp pPhysPage:%R[pgmpage] GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4218	GCPtr + off, HCPhysShw, pPhysPage, GCPhysGst, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4219	cErrors++;
4220	continue;
4221	}
4222
4223	/* flags */
4224	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
4225	{
4226	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
4227	{
4228	if (SHW_PTE_IS_RW(PteDst))
4229	{
4230	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! pPhysPage=%R[pgmpage] PteSrc=%#RX64 PteDst=%#RX64\n",
4231	GCPtr + off, pPhysPage, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4232	cErrors++;
4233	continue;
4234	}
4235	fIgnoreFlags \|= X86_PTE_RW;
4236	}
4237	else
4238	{
4239	if ( SHW_PTE_IS_P(PteDst)
4240	# if PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
4241	&& !PGM_PAGE_IS_MMIO(pPhysPage)
4242	# endif
4243	)
4244	{
4245	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! pPhysPage=%R[pgmpage] PteSrc=%#RX64 PteDst=%#RX64\n",
4246	GCPtr + off, pPhysPage, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4247	cErrors++;
4248	continue;
4249	}
4250	fIgnoreFlags \|= X86_PTE_P;
4251	}
4252	}
4253	else
4254	{
4255	if (!PteSrc.n.u1Dirty && PteSrc.n.u1Write)
4256	{
4257	if (SHW_PTE_IS_RW(PteDst))
4258	{
4259	AssertMsgFailed(("!DIRTY page at %RGv is writable! PteSrc=%#RX64 PteDst=%#RX64\n",
4260	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4261	cErrors++;
4262	continue;
4263	}
4264	if (!SHW_PTE_IS_TRACK_DIRTY(PteDst))
4265	{
4266	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4267	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4268	cErrors++;
4269	continue;
4270	}
4271	if (SHW_PTE_IS_D(PteDst))
4272	{
4273	AssertMsgFailed(("!DIRTY page at %RGv is marked DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4274	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4275	cErrors++;
4276	}
4277	# if 0 /** @todo sync access bit properly... */
4278	if (PteDst.n.u1Accessed != PteSrc.n.u1Accessed)
4279	{
4280	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4281	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4282	cErrors++;
4283	}
4284	fIgnoreFlags \|= X86_PTE_RW;
4285	# else
4286	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4287	# endif
4288	}
4289	else if (SHW_PTE_IS_TRACK_DIRTY(PteDst))
4290	{
4291	/* access bit emulation (not implemented). */
4292	if (PteSrc.n.u1Accessed \|\| SHW_PTE_IS_P(PteDst))
4293	{
4294	AssertMsgFailed(("PGM_PTFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PteSrc=%#RX64 PteDst=%#RX64\n",
4295	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4296	cErrors++;
4297	continue;
4298	}
4299	if (!SHW_PTE_IS_A(PteDst))
4300	{
4301	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PteSrc=%#RX64 PteDst=%#RX64\n",
4302	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4303	cErrors++;
4304	}
4305	fIgnoreFlags \|= X86_PTE_P;
4306	}
4307	# ifdef DEBUG_sandervl
4308	fIgnoreFlags \|= X86_PTE_D \| X86_PTE_A;
4309	# endif
4310	}
4311
4312	if ( (PteSrc.u & ~fIgnoreFlags) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags)
4313	&& (PteSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags)
4314	)
4315	{
4316	AssertMsgFailed(("Flags mismatch at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PteSrc=%#RX64 PteDst=%#RX64\n",
4317	GCPtr + off, (uint64_t)PteSrc.u & ~fIgnoreFlags, SHW_PTE_LOG64(PteDst) & ~fIgnoreFlags,
4318	fIgnoreFlags, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4319	cErrors++;
4320	continue;
4321	}
4322	} /* foreach PTE */
4323	}
4324	else
4325	{
4326	/*
4327	* Big Page.
4328	*/
4329	uint64_t fIgnoreFlags = X86_PDE_AVL_MASK \| GST_PDE_PG_MASK \| X86_PDE4M_G \| X86_PDE4M_D \| X86_PDE4M_PS \| X86_PDE4M_PWT \| X86_PDE4M_PCD;
4330	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
4331	{
4332	if (PdeDst.n.u1Write)
4333	{
4334	AssertMsgFailed(("!DIRTY page at %RGv is writable! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4335	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4336	cErrors++;
4337	continue;
4338	}
4339	if (!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY))
4340	{
4341	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4342	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4343	cErrors++;
4344	continue;
4345	}
4346	# if 0 /** @todo sync access bit properly... */
4347	if (PdeDst.n.u1Accessed != PdeSrc.b.u1Accessed)
4348	{
4349	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4350	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4351	cErrors++;
4352	}
4353	fIgnoreFlags \|= X86_PTE_RW;
4354	# else
4355	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4356	# endif
4357	}
4358	else if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
4359	{
4360	/* access bit emulation (not implemented). */
4361	if (PdeSrc.b.u1Accessed \|\| PdeDst.n.u1Present)
4362	{
4363	AssertMsgFailed(("PGM_PDFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4364	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4365	cErrors++;
4366	continue;
4367	}
4368	if (!PdeDst.n.u1Accessed)
4369	{
4370	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4371	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4372	cErrors++;
4373	}
4374	fIgnoreFlags \|= X86_PTE_P;
4375	}
4376
4377	if ((PdeSrc.u & ~fIgnoreFlags) != (PdeDst.u & ~fIgnoreFlags))
4378	{
4379	AssertMsgFailed(("Flags mismatch (B) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PdeDst=%#RX64\n",
4380	GCPtr, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PdeDst.u & ~fIgnoreFlags,
4381	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4382	cErrors++;
4383	}
4384
4385	/* iterate the page table. */
4386	for (unsigned iPT = 0, off = 0;
4387	iPT < RT_ELEMENTS(pPTDst->a);
4388	iPT++, off += PAGE_SIZE, GCPhysGst = PGM_A20_APPLY(pVCpu, GCPhysGst + PAGE_SIZE))
4389	{
4390	const SHWPTE PteDst = pPTDst->a[iPT];
4391
4392	if (SHW_PTE_IS_TRACK_DIRTY(PteDst))
4393	{
4394	AssertMsgFailed(("The PTE at %RGv emulating a 2/4M page is marked TRACK_DIRTY! PdeSrc=%#RX64 PteDst=%#RX64\n",
4395	GCPtr + off, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4396	cErrors++;
4397	}
4398
4399	/* skip not-present entries. */
4400	if (!SHW_PTE_IS_P(PteDst)) /** @todo deal with ALL handlers and CSAM !P pages! */
4401	continue;
4402
4403	fIgnoreFlags = X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT \| X86_PTE_D \| X86_PTE_A \| X86_PTE_G \| X86_PTE_PAE_NX;
4404
4405	/* match the physical addresses */
4406	HCPhysShw = SHW_PTE_GET_HCPHYS(PteDst);
4407
4408	# ifdef IN_RING3
4409	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
4410	if (RT_FAILURE(rc))
4411	{
4412	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4413	{
4414	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4415	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4416	cErrors++;
4417	}
4418	}
4419	else if (HCPhysShw != (HCPhys & X86_PTE_PAE_PG_MASK))
4420	{
4421	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4422	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4423	cErrors++;
4424	continue;
4425	}
4426	# endif
4427	pPhysPage = pgmPhysGetPage(pVM, GCPhysGst);
4428	if (!pPhysPage)
4429	{
4430	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
4431	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4432	{
4433	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4434	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4435	cErrors++;
4436	continue;
4437	}
4438	# endif
4439	if (SHW_PTE_IS_RW(PteDst))
4440	{
4441	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4442	GCPtr + off, GCPhysGst, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4443	cErrors++;
4444	}
4445	fIgnoreFlags \|= X86_PTE_RW;
4446	}
4447	else if (HCPhysShw != PGM_PAGE_GET_HCPHYS(pPhysPage))
4448	{
4449	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp pPhysPage=%R[pgmpage] GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4450	GCPtr + off, HCPhysShw, pPhysPage, GCPhysGst, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4451	cErrors++;
4452	continue;
4453	}
4454
4455	/* flags */
4456	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
4457	{
4458	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
4459	{
4460	if (PGM_PAGE_GET_HNDL_PHYS_STATE(pPhysPage) != PGM_PAGE_HNDL_PHYS_STATE_DISABLED)
4461	{
4462	if (SHW_PTE_IS_RW(PteDst))
4463	{
4464	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! pPhysPage=%R[pgmpage] PdeSrc=%#RX64 PteDst=%#RX64\n",
4465	GCPtr + off, pPhysPage, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4466	cErrors++;
4467	continue;
4468	}
4469	fIgnoreFlags \|= X86_PTE_RW;
4470	}
4471	}
4472	else
4473	{
4474	if ( SHW_PTE_IS_P(PteDst)
4475	# if PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
4476	&& !PGM_PAGE_IS_MMIO(pPhysPage)
4477	# endif
4478	)
4479	{
4480	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! pPhysPage=%R[pgmpage] PdeSrc=%#RX64 PteDst=%#RX64\n",
4481	GCPtr + off, pPhysPage, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4482	cErrors++;
4483	continue;
4484	}
4485	fIgnoreFlags \|= X86_PTE_P;
4486	}
4487	}
4488
4489	if ( (PdeSrc.u & ~fIgnoreFlags) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags)
4490	&& (PdeSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags) /* lazy phys handler dereg. */
4491	)
4492	{
4493	AssertMsgFailed(("Flags mismatch (BT) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PteDst=%#RX64\n",
4494	GCPtr + off, (uint64_t)PdeSrc.u & ~fIgnoreFlags, SHW_PTE_LOG64(PteDst) & ~fIgnoreFlags,
4495	fIgnoreFlags, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4496	cErrors++;
4497	continue;
4498	}
4499	} /* for each PTE */
4500	}
4501	}
4502	/* not present */
4503
4504	} /* for each PDE */
4505
4506	} /* for each PDPTE */
4507
4508	} /* for each PML4E */
4509
4510	# ifdef DEBUG
4511	if (cErrors)
4512	LogFlow(("AssertCR3: cErrors=%d\n", cErrors));
4513	# endif
4514	# endif /* GST is in {32BIT, PAE, AMD64} */
4515	return cErrors;
4516	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT */
4517	}
4518	#endif /* VBOX_STRICT */
4519
4520
4521	/**
4522	* Sets up the CR3 for shadow paging
4523	*
4524	* @returns Strict VBox status code.
4525	* @retval VINF_SUCCESS.
4526	*
4527	* @param pVCpu Pointer to the VMCPU.
4528	* @param GCPhysCR3 The physical address in the CR3 register. (A20
4529	* mask already applied.)
4530	*/
4531	PGM_BTH_DECL(int, MapCR3)(PVMCPU pVCpu, RTGCPHYS GCPhysCR3)
4532	{
4533	PVM pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
4534
4535	/* Update guest paging info. */
4536	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
4537	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
4538	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
4539
4540	LogFlow(("MapCR3: %RGp\n", GCPhysCR3));
4541	PGM_A20_ASSERT_MASKED(pVCpu, GCPhysCR3);
4542
4543	/*
4544	* Map the page CR3 points at.
4545	*/
4546	RTHCPTR HCPtrGuestCR3;
4547	RTHCPHYS HCPhysGuestCR3;
4548	pgmLock(pVM);
4549	PPGMPAGE pPageCR3 = pgmPhysGetPage(pVM, GCPhysCR3);
4550	AssertReturn(pPageCR3, VERR_PGM_INVALID_CR3_ADDR);
4551	HCPhysGuestCR3 = PGM_PAGE_GET_HCPHYS(pPageCR3);
4552	/** @todo this needs some reworking wrt. locking? */
4553	# if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
4554	HCPtrGuestCR3 = NIL_RTHCPTR;
4555	int rc = VINF_SUCCESS;
4556	# else
4557	int rc = pgmPhysGCPhys2CCPtrInternalDepr(pVM, pPageCR3, GCPhysCR3 & GST_CR3_PAGE_MASK, (void )&HCPtrGuestCR3); / @todo r=bird: This GCPhysCR3 masking isn't necessary. */
4558	# endif
4559	pgmUnlock(pVM);
4560	if (RT_SUCCESS(rc))
4561	{
4562	rc = PGMMap(pVM, (RTGCPTR)pVM->pgm.s.GCPtrCR3Mapping, HCPhysGuestCR3, PAGE_SIZE, 0);
4563	if (RT_SUCCESS(rc))
4564	{
4565	# ifdef IN_RC
4566	PGM_INVL_PG(pVCpu, pVM->pgm.s.GCPtrCR3Mapping);
4567	# endif
4568	# if PGM_GST_TYPE == PGM_TYPE_32BIT
4569	pVCpu->pgm.s.pGst32BitPdR3 = (R3PTRTYPE(PX86PD))HCPtrGuestCR3;
4570	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4571	pVCpu->pgm.s.pGst32BitPdR0 = (R0PTRTYPE(PX86PD))HCPtrGuestCR3;
4572	# endif
4573	pVCpu->pgm.s.pGst32BitPdRC = (RCPTRTYPE(PX86PD))(RTRCUINTPTR)pVM->pgm.s.GCPtrCR3Mapping;
4574
4575	# elif PGM_GST_TYPE == PGM_TYPE_PAE
4576	unsigned off = GCPhysCR3 & GST_CR3_PAGE_MASK & PAGE_OFFSET_MASK;
4577	pVCpu->pgm.s.pGstPaePdptR3 = (R3PTRTYPE(PX86PDPT))HCPtrGuestCR3;
4578	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4579	pVCpu->pgm.s.pGstPaePdptR0 = (R0PTRTYPE(PX86PDPT))HCPtrGuestCR3;
4580	# endif
4581	pVCpu->pgm.s.pGstPaePdptRC = (RCPTRTYPE(PX86PDPT))((RTRCUINTPTR)pVM->pgm.s.GCPtrCR3Mapping + off);
4582	LogFlow(("Cached mapping %RRv\n", pVCpu->pgm.s.pGstPaePdptRC));
4583
4584	/*
4585	* Map the 4 PDs too.
4586	*/
4587	PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pVCpu);
4588	RTGCPTR GCPtr = pVM->pgm.s.GCPtrCR3Mapping + PAGE_SIZE;
4589	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++, GCPtr += PAGE_SIZE)
4590	{
4591	pVCpu->pgm.s.aGstPaePdpeRegs[i].u = pGuestPDPT->a[i].u;
4592	if (pGuestPDPT->a[i].n.u1Present)
4593	{
4594	RTHCPTR HCPtr;
4595	RTHCPHYS HCPhys;
4596	RTGCPHYS GCPhys = PGM_A20_APPLY(pVCpu, pGuestPDPT->a[i].u & X86_PDPE_PG_MASK);
4597	pgmLock(pVM);
4598	PPGMPAGE pPage = pgmPhysGetPage(pVM, GCPhys);
4599	AssertReturn(pPage, VERR_PGM_INVALID_PDPE_ADDR);
4600	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
4601	# if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
4602	HCPtr = NIL_RTHCPTR;
4603	int rc2 = VINF_SUCCESS;
4604	# else
4605	int rc2 = pgmPhysGCPhys2CCPtrInternalDepr(pVM, pPage, GCPhys, (void **)&HCPtr);
4606	# endif
4607	pgmUnlock(pVM);
4608	if (RT_SUCCESS(rc2))
4609	{
4610	rc = PGMMap(pVM, GCPtr, HCPhys, PAGE_SIZE, 0);
4611	AssertRCReturn(rc, rc);
4612
4613	pVCpu->pgm.s.apGstPaePDsR3[i] = (R3PTRTYPE(PX86PDPAE))HCPtr;
4614	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4615	pVCpu->pgm.s.apGstPaePDsR0[i] = (R0PTRTYPE(PX86PDPAE))HCPtr;
4616	# endif
4617	pVCpu->pgm.s.apGstPaePDsRC[i] = (RCPTRTYPE(PX86PDPAE))(RTRCUINTPTR)GCPtr;
4618	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = GCPhys;
4619	# ifdef IN_RC
4620	PGM_INVL_PG(pVCpu, GCPtr);
4621	# endif
4622	continue;
4623	}
4624	AssertMsgFailed(("pgmR3Gst32BitMapCR3: rc2=%d GCPhys=%RGp i=%d\n", rc2, GCPhys, i));
4625	}
4626
4627	pVCpu->pgm.s.apGstPaePDsR3[i] = 0;
4628	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4629	pVCpu->pgm.s.apGstPaePDsR0[i] = 0;
4630	# endif
4631	pVCpu->pgm.s.apGstPaePDsRC[i] = 0;
4632	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
4633	# ifdef IN_RC
4634	PGM_INVL_PG(pVCpu, GCPtr); /** @todo this shouldn't be necessary? */
4635	# endif
4636	}
4637
4638	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
4639	pVCpu->pgm.s.pGstAmd64Pml4R3 = (R3PTRTYPE(PX86PML4))HCPtrGuestCR3;
4640	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4641	pVCpu->pgm.s.pGstAmd64Pml4R0 = (R0PTRTYPE(PX86PML4))HCPtrGuestCR3;
4642	# endif
4643	# endif
4644	}
4645	else
4646	AssertMsgFailed(("rc=%Rrc GCPhysGuestPD=%RGp\n", rc, GCPhysCR3));
4647	}
4648	else
4649	AssertMsgFailed(("rc=%Rrc GCPhysGuestPD=%RGp\n", rc, GCPhysCR3));
4650
4651	#else /* prot/real stub */
4652	int rc = VINF_SUCCESS;
4653	#endif
4654
4655	/* Update shadow paging info for guest modes with paging (32, pae, 64). */
4656	# if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
4657	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
4658	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64) \
4659	&& ( PGM_GST_TYPE != PGM_TYPE_REAL \
4660	&& PGM_GST_TYPE != PGM_TYPE_PROT))
4661
4662	Assert(!pVM->pgm.s.fNestedPaging);
4663	PGM_A20_ASSERT_MASKED(pVCpu, GCPhysCR3);
4664
4665	/*
4666	* Update the shadow root page as well since that's not fixed.
4667	*/
4668	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4669	PPGMPOOLPAGE pOldShwPageCR3 = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
4670	PPGMPOOLPAGE pNewShwPageCR3;
4671
4672	pgmLock(pVM);
4673
4674	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
4675	if (pPool->cDirtyPages)
4676	pgmPoolResetDirtyPages(pVM);
4677	# endif
4678
4679	Assert(!(GCPhysCR3 >> (PAGE_SHIFT + 32)));
4680	rc = pgmPoolAlloc(pVM, GCPhysCR3 & GST_CR3_PAGE_MASK, BTH_PGMPOOLKIND_ROOT, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
4681	NIL_PGMPOOL_IDX, UINT32_MAX, true /fLockPage/,
4682	&pNewShwPageCR3);
4683	AssertFatalRC(rc);
4684	rc = VINF_SUCCESS;
4685
4686	# ifdef IN_RC
4687	/*
4688	* WARNING! We can't deal with jumps to ring 3 in the code below as the
4689	* state will be inconsistent! Flush important things now while
4690	* we still can and then make sure there are no ring-3 calls.
4691	*/
4692	# ifdef VBOX_WITH_REM
4693	REMNotifyHandlerPhysicalFlushIfAlmostFull(pVM, pVCpu);
4694	# endif
4695	VMMRZCallRing3Disable(pVCpu);
4696	# endif
4697
4698	pVCpu->pgm.s.CTX_SUFF(pShwPageCR3) = pNewShwPageCR3;
4699	# ifdef IN_RING0
4700	pVCpu->pgm.s.pShwPageCR3R3 = MMHyperCCToR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4701	pVCpu->pgm.s.pShwPageCR3RC = MMHyperCCToRC(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4702	# elif defined(IN_RC)
4703	pVCpu->pgm.s.pShwPageCR3R3 = MMHyperCCToR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4704	pVCpu->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4705	# else
4706	pVCpu->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4707	pVCpu->pgm.s.pShwPageCR3RC = MMHyperCCToRC(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4708	# endif
4709
4710	# ifndef PGM_WITHOUT_MAPPINGS
4711	/*
4712	* Apply all hypervisor mappings to the new CR3.
4713	* Note that SyncCR3 will be executed in case CR3 is changed in a guest paging mode; this will
4714	* make sure we check for conflicts in the new CR3 root.
4715	*/
4716	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
4717	Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL) \|\| VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
4718	# endif
4719	rc = pgmMapActivateCR3(pVM, pNewShwPageCR3);
4720	AssertRCReturn(rc, rc);
4721	# endif
4722
4723	/* Set the current hypervisor CR3. */
4724	CPUMSetHyperCR3(pVCpu, PGMGetHyperCR3(pVCpu));
4725	SELMShadowCR3Changed(pVM, pVCpu);
4726
4727	# ifdef IN_RC
4728	/* NOTE: The state is consistent again. */
4729	VMMRZCallRing3Enable(pVCpu);
4730	# endif
4731
4732	/* Clean up the old CR3 root. */
4733	if ( pOldShwPageCR3
4734	&& pOldShwPageCR3 != pNewShwPageCR3 /* @todo can happen due to incorrect syncing between REM & PGM; find the real cause */)
4735	{
4736	Assert(pOldShwPageCR3->enmKind != PGMPOOLKIND_FREE);
4737	# ifndef PGM_WITHOUT_MAPPINGS
4738	/* Remove the hypervisor mappings from the shadow page table. */
4739	pgmMapDeactivateCR3(pVM, pOldShwPageCR3);
4740	# endif
4741	/* Mark the page as unlocked; allow flushing again. */
4742	pgmPoolUnlockPage(pPool, pOldShwPageCR3);
4743
4744	pgmPoolFreeByPage(pPool, pOldShwPageCR3, NIL_PGMPOOL_IDX, UINT32_MAX);
4745	}
4746	pgmUnlock(pVM);
4747	# else
4748	NOREF(GCPhysCR3);
4749	# endif
4750
4751	return rc;
4752	}
4753
4754	/**
4755	* Unmaps the shadow CR3.
4756	*
4757	* @returns VBox status, no specials.
4758	* @param pVCpu Pointer to the VMCPU.
4759	*/
4760	PGM_BTH_DECL(int, UnmapCR3)(PVMCPU pVCpu)
4761	{
4762	LogFlow(("UnmapCR3\n"));
4763
4764	int rc = VINF_SUCCESS;
4765	PVM pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
4766
4767	/*
4768	* Update guest paging info.
4769	*/
4770	#if PGM_GST_TYPE == PGM_TYPE_32BIT
4771	pVCpu->pgm.s.pGst32BitPdR3 = 0;
4772	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4773	pVCpu->pgm.s.pGst32BitPdR0 = 0;
4774	# endif
4775	pVCpu->pgm.s.pGst32BitPdRC = 0;
4776
4777	#elif PGM_GST_TYPE == PGM_TYPE_PAE
4778	pVCpu->pgm.s.pGstPaePdptR3 = 0;
4779	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4780	pVCpu->pgm.s.pGstPaePdptR0 = 0;
4781	# endif
4782	pVCpu->pgm.s.pGstPaePdptRC = 0;
4783	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
4784	{
4785	pVCpu->pgm.s.apGstPaePDsR3[i] = 0;
4786	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4787	pVCpu->pgm.s.apGstPaePDsR0[i] = 0;
4788	# endif
4789	pVCpu->pgm.s.apGstPaePDsRC[i] = 0;
4790	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
4791	}
4792
4793	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
4794	pVCpu->pgm.s.pGstAmd64Pml4R3 = 0;
4795	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4796	pVCpu->pgm.s.pGstAmd64Pml4R0 = 0;
4797	# endif
4798
4799	#else /* prot/real mode stub */
4800	/* nothing to do */
4801	#endif
4802
4803	#if !defined(IN_RC) /* In RC we rely on MapCR3 to do the shadow part for us at a safe time */
4804	/*
4805	* Update shadow paging info.
4806	*/
4807	# if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
4808	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
4809	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64))
4810
4811	# if PGM_GST_TYPE != PGM_TYPE_REAL
4812	Assert(!pVM->pgm.s.fNestedPaging);
4813	# endif
4814
4815	pgmLock(pVM);
4816
4817	# ifndef PGM_WITHOUT_MAPPINGS
4818	if (pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
4819	/* Remove the hypervisor mappings from the shadow page table. */
4820	pgmMapDeactivateCR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4821	# endif
4822
4823	if (pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
4824	{
4825	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4826
4827	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
4828	if (pPool->cDirtyPages)
4829	pgmPoolResetDirtyPages(pVM);
4830	# endif
4831
4832	/* Mark the page as unlocked; allow flushing again. */
4833	pgmPoolUnlockPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4834
4835	pgmPoolFreeByPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3), NIL_PGMPOOL_IDX, UINT32_MAX);
4836	pVCpu->pgm.s.pShwPageCR3R3 = 0;
4837	pVCpu->pgm.s.pShwPageCR3R0 = 0;
4838	pVCpu->pgm.s.pShwPageCR3RC = 0;
4839	}
4840	pgmUnlock(pVM);
4841	# endif
4842	#endif /* !IN_RC*/
4843
4844	return rc;
4845	}

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllBth.h@ 56225

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