PGMAllBth.h@ 64468

Last change on this file since 64468 was 62606, checked in by vboxsync, 8 years ago
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1	/* $Id: PGMAllBth.h 62606 2016-07-27 16:33:40Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Shadow+Guest Paging Template - All context code.
4	*
5	* @remarks The nested page tables on AMD makes use of PGM_SHW_TYPE in
6	* {PGM_TYPE_AMD64, PGM_TYPE_PAE and PGM_TYPE_32BIT} and PGM_GST_TYPE
7	* set to PGM_TYPE_PROT. Half of the code in this file is not
8	* exercised with PGM_SHW_TYPE set to PGM_TYPE_NESTED.
9	*
10	* @remarks Extended page tables (intel) are built with PGM_GST_TYPE set to
11	* PGM_TYPE_PROT (and PGM_SHW_TYPE set to PGM_TYPE_EPT).
12	*
13	* @remarks This file is one big \#ifdef-orgy!
14	*
15	*/
16
17	/*
18	* Copyright (C) 2006-2016 Oracle Corporation
19	*
20	* This file is part of VirtualBox Open Source Edition (OSE), as
21	* available from http://www.virtualbox.org. This file is free software;
22	* you can redistribute it and/or modify it under the terms of the GNU
23	* General Public License (GPL) as published by the Free Software
24	* Foundation, in version 2 as it comes in the "COPYING" file of the
25	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
26	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
27	*/
28
29	#ifdef _MSC_VER
30	/** @todo we're generating unnecessary code in nested/ept shadow mode and for
31	* real/prot-guest+RC mode. */
32	# pragma warning(disable: 4505)
33	#endif
34
35	/*******************************************************************************
36	* Internal Functions *
37	*******************************************************************************/
38	RT_C_DECLS_BEGIN
39	PGM_BTH_DECL(int, Trap0eHandler)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken);
40	PGM_BTH_DECL(int, InvalidatePage)(PVMCPU pVCpu, RTGCPTR GCPtrPage);
41	static int PGM_BTH_NAME(SyncPage)(PVMCPU pVCpu, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr);
42	static int PGM_BTH_NAME(CheckDirtyPageFault)(PVMCPU pVCpu, uint32_t uErr, PSHWPDE pPdeDst, GSTPDE const *pPdeSrc, RTGCPTR GCPtrPage);
43	static int PGM_BTH_NAME(SyncPT)(PVMCPU pVCpu, unsigned iPD, PGSTPD pPDSrc, RTGCPTR GCPtrPage);
44	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
45	static void PGM_BTH_NAME(SyncPageWorker)(PVMCPU pVCpu, PSHWPTE pPteDst, GSTPDE PdeSrc, GSTPTE PteSrc, PPGMPOOLPAGE pShwPage, unsigned iPTDst);
46	# else
47	static void PGM_BTH_NAME(SyncPageWorker)(PVMCPU pVCpu, PSHWPTE pPteDst, RTGCPHYS GCPhysPage, PPGMPOOLPAGE pShwPage, unsigned iPTDst);
48	#endif
49	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVMCPU pVCpu, RTGCPTR Addr, unsigned fPage, unsigned uErr);
50	PGM_BTH_DECL(int, PrefetchPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage);
51	PGM_BTH_DECL(int, SyncCR3)(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
52	#ifdef VBOX_STRICT
53	PGM_BTH_DECL(unsigned, AssertCR3)(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr = 0, RTGCPTR cb = ~(RTGCPTR)0);
54	#endif
55	PGM_BTH_DECL(int, MapCR3)(PVMCPU pVCpu, RTGCPHYS GCPhysCR3);
56	PGM_BTH_DECL(int, UnmapCR3)(PVMCPU pVCpu);
57	RT_C_DECLS_END
58
59
60	/*
61	* Filter out some illegal combinations of guest and shadow paging, so we can
62	* remove redundant checks inside functions.
63	*/
64	#if PGM_GST_TYPE == PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
65	# error "Invalid combination; PAE guest implies PAE shadow"
66	#endif
67
68	#if (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
69	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT)
70	# error "Invalid combination; real or protected mode without paging implies 32 bits or PAE shadow paging."
71	#endif
72
73	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) \
74	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT)
75	# error "Invalid combination; 32 bits guest paging or PAE implies 32 bits or PAE shadow paging."
76	#endif
77
78	#if (PGM_GST_TYPE == PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT) \
79	\|\| (PGM_SHW_TYPE == PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PROT)
80	# error "Invalid combination; AMD64 guest implies AMD64 shadow and vice versa"
81	#endif
82
83	#ifndef IN_RING3
84
85	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
86	/**
87	* Deal with a guest page fault.
88	*
89	* @returns Strict VBox status code.
90	* @retval VINF_EM_RAW_GUEST_TRAP
91	* @retval VINF_EM_RAW_EMULATE_INSTR
92	*
93	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
94	* @param pGstWalk The guest page table walk result.
95	* @param uErr The error code.
96	*/
97	PGM_BTH_DECL(VBOXSTRICTRC, Trap0eHandlerGuestFault)(PVMCPU pVCpu, PGSTPTWALK pGstWalk, RTGCUINT uErr)
98	{
99	# if !defined(PGM_WITHOUT_MAPPINGS) && (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE)
100	/*
101	* Check for write conflicts with our hypervisor mapping.
102	*
103	* If the guest happens to access a non-present page, where our hypervisor
104	* is currently mapped, then we'll create a #PF storm in the guest.
105	*/
106	if ( (uErr & (X86_TRAP_PF_P \| X86_TRAP_PF_RW)) == (X86_TRAP_PF_P \| X86_TRAP_PF_RW)
107	&& pgmMapAreMappingsEnabled(pVCpu->CTX_SUFF(pVM))
108	&& MMHyperIsInsideArea(pVCpu->CTX_SUFF(pVM), pGstWalk->Core.GCPtr))
109	{
110	/* Force a CR3 sync to check for conflicts and emulate the instruction. */
111	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
112	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2GuestTrap; });
113	return VINF_EM_RAW_EMULATE_INSTR;
114	}
115	# endif
116
117	/*
118	* Calc the error code for the guest trap.
119	*/
120	uint32_t uNewErr = GST_IS_NX_ACTIVE(pVCpu)
121	? uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US \| X86_TRAP_PF_ID)
122	: uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US);
123	if (pGstWalk->Core.fBadPhysAddr)
124	{
125	uNewErr \|= X86_TRAP_PF_RSVD \| X86_TRAP_PF_P;
126	Assert(!pGstWalk->Core.fNotPresent);
127	}
128	else if (!pGstWalk->Core.fNotPresent)
129	uNewErr \|= X86_TRAP_PF_P;
130	TRPMSetErrorCode(pVCpu, uNewErr);
131
132	LogFlow(("Guest trap; cr2=%RGv uErr=%RGv lvl=%d\n", pGstWalk->Core.GCPtr, uErr, pGstWalk->Core.uLevel));
133	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2GuestTrap; });
134	return VINF_EM_RAW_GUEST_TRAP;
135	}
136	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
137
138
139	/**
140	* Deal with a guest page fault.
141	*
142	* The caller has taken the PGM lock.
143	*
144	* @returns Strict VBox status code.
145	*
146	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
147	* @param uErr The error code.
148	* @param pRegFrame The register frame.
149	* @param pvFault The fault address.
150	* @param pPage The guest page at @a pvFault.
151	* @param pGstWalk The guest page table walk result.
152	* @param pfLockTaken PGM lock taken here or not (out). This is true
153	* when we're called.
154	*/
155	static VBOXSTRICTRC PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame,
156	RTGCPTR pvFault, PPGMPAGE pPage, bool *pfLockTaken
157	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \|\| defined(DOXYGEN_RUNNING)
158	, PGSTPTWALK pGstWalk
159	# endif
160	)
161	{
162	# if !PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
163	GSTPDE const PdeSrcDummy = { X86_PDE_P \| X86_PDE_US \| X86_PDE_RW \| X86_PDE_A };
164	#endif
165	PVM pVM = pVCpu->CTX_SUFF(pVM);
166	VBOXSTRICTRC rcStrict;
167
168	if (PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage))
169	{
170	/*
171	* Physical page access handler.
172	*/
173	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
174	const RTGCPHYS GCPhysFault = pGstWalk->Core.GCPhys;
175	# else
176	const RTGCPHYS GCPhysFault = PGM_A20_APPLY(pVCpu, (RTGCPHYS)pvFault);
177	# endif
178	PPGMPHYSHANDLER pCur = pgmHandlerPhysicalLookup(pVM, GCPhysFault);
179	if (pCur)
180	{
181	PPGMPHYSHANDLERTYPEINT pCurType = PGMPHYSHANDLER_GET_TYPE(pVM, pCur);
182
183	# ifdef PGM_SYNC_N_PAGES
184	/*
185	* If the region is write protected and we got a page not present fault, then sync
186	* the pages. If the fault was caused by a read, then restart the instruction.
187	* In case of write access continue to the GC write handler.
188	*
189	* ASSUMES that there is only one handler per page or that they have similar write properties.
190	*/
191	if ( !(uErr & X86_TRAP_PF_P)
192	&& pCurType->enmKind == PGMPHYSHANDLERKIND_WRITE)
193	{
194	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
195	rcStrict = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
196	# else
197	rcStrict = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
198	# endif
199	if ( RT_FAILURE(rcStrict)
200	\|\| !(uErr & X86_TRAP_PF_RW)
201	\|\| rcStrict == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
202	{
203	AssertMsgRC(rcStrict, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
204	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersOutOfSync);
205	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndPhys; });
206	return rcStrict;
207	}
208	}
209	# endif
210	# ifdef PGM_WITH_MMIO_OPTIMIZATIONS
211	/*
212	* If the access was not thru a #PF(RSVD\|...) resync the page.
213	*/
214	if ( !(uErr & X86_TRAP_PF_RSVD)
215	&& pCurType->enmKind != PGMPHYSHANDLERKIND_WRITE
216	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
217	&& pGstWalk->Core.fEffectiveRW
218	&& !pGstWalk->Core.fEffectiveUS /** @todo Remove pGstWalk->Core.fEffectiveUS and X86_PTE_US further down in the sync code. */
219	# endif
220	)
221	{
222	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
223	rcStrict = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
224	# else
225	rcStrict = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
226	# endif
227	if ( RT_FAILURE(rcStrict)
228	\|\| rcStrict == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
229	{
230	AssertMsgRC(rcStrict, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
231	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersOutOfSync);
232	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndPhys; });
233	return rcStrict;
234	}
235	}
236	# endif
237
238	AssertMsg( pCurType->enmKind != PGMPHYSHANDLERKIND_WRITE
239	\|\| (pCurType->enmKind == PGMPHYSHANDLERKIND_WRITE && (uErr & X86_TRAP_PF_RW)),
240	("Unexpected trap for physical handler: %08X (phys=%08x) pPage=%R[pgmpage] uErr=%X, enmKind=%d\n",
241	pvFault, GCPhysFault, pPage, uErr, pCurType->enmKind));
242	if (pCurType->enmKind == PGMPHYSHANDLERKIND_WRITE)
243	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersPhysWrite);
244	else
245	{
246	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersPhysAll);
247	if (uErr & X86_TRAP_PF_RSVD) STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersPhysAllOpt);
248	}
249
250	if (pCurType->CTX_SUFF(pfnPfHandler))
251	{
252	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
253	void *pvUser = pCur->CTX_SUFF(pvUser);
254
255	STAM_PROFILE_START(&pCur->Stat, h);
256	if (pCur->hType != pPool->hAccessHandlerType)
257	{
258	pgmUnlock(pVM);
259	*pfLockTaken = false;
260	}
261
262	rcStrict = pCurType->CTX_SUFF(pfnPfHandler)(pVM, pVCpu, uErr, pRegFrame, pvFault, GCPhysFault, pvUser);
263
264	# ifdef VBOX_WITH_STATISTICS
265	pgmLock(pVM);
266	pCur = pgmHandlerPhysicalLookup(pVM, GCPhysFault);
267	if (pCur)
268	STAM_PROFILE_STOP(&pCur->Stat, h);
269	pgmUnlock(pVM);
270	# endif
271	}
272	else
273	rcStrict = VINF_EM_RAW_EMULATE_INSTR;
274
275	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndPhys; });
276	return rcStrict;
277	}
278	}
279	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0)
280	else
281	{
282	# ifdef PGM_SYNC_N_PAGES
283	/*
284	* If the region is write protected and we got a page not present fault, then sync
285	* the pages. If the fault was caused by a read, then restart the instruction.
286	* In case of write access continue to the GC write handler.
287	*/
288	if ( PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) < PGM_PAGE_HNDL_PHYS_STATE_ALL
289	&& !(uErr & X86_TRAP_PF_P))
290	{
291	rcStrict = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
292	if ( RT_FAILURE(rcStrict)
293	\|\| rcStrict == VINF_PGM_SYNCPAGE_MODIFIED_PDE
294	\|\| !(uErr & X86_TRAP_PF_RW))
295	{
296	AssertRC(rcStrict);
297	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersOutOfSync);
298	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndVirt; });
299	return rcStrict;
300	}
301	}
302	# endif
303	/*
304	* Ok, it's an virtual page access handler.
305	*
306	* Since it's faster to search by address, we'll do that first
307	* and then retry by GCPhys if that fails.
308	*/
309	/** @todo r=bird: perhaps we should consider looking up by physical address directly now?
310	* r=svl: true, but lookup on virtual address should remain as a fallback as phys & virt trees might be
311	* out of sync, because the page was changed without us noticing it (not-present -> present
312	* without invlpg or mov cr3, xxx).
313	*/
314	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
315	if (pCur)
316	{
317	PPGMVIRTHANDLERTYPEINT pCurType = PGMVIRTANDLER_GET_TYPE(pVM, pCur);
318	AssertMsg(!(pvFault - pCur->Core.Key < pCur->cb)
319	\|\| ( pCurType->enmKind != PGMVIRTHANDLERKIND_WRITE
320	\|\| !(uErr & X86_TRAP_PF_P)
321	\|\| (pCurType->enmKind == PGMVIRTHANDLERKIND_WRITE && (uErr & X86_TRAP_PF_RW))),
322	("Unexpected trap for virtual handler: %RGv (phys=%RGp) pPage=%R[pgmpage] uErr=%X, enumKind=%d\n",
323	pvFault, pGstWalk->Core.GCPhys, pPage, uErr, pCurType->enmKind));
324
325	if ( pvFault - pCur->Core.Key < pCur->cb
326	&& ( uErr & X86_TRAP_PF_RW
327	\|\| pCurType->enmKind != PGMVIRTHANDLERKIND_WRITE ) )
328	{
329	# ifdef IN_RC
330	STAM_PROFILE_START(&pCur->Stat, h);
331	RTGCPTR GCPtrStart = pCur->Core.Key;
332	void *pvUser = pCur->CTX_SUFF(pvUser);
333	pgmUnlock(pVM);
334	*pfLockTaken = false;
335
336	rcStrict = pCurType->CTX_SUFF(pfnPfHandler)(pVM, pVCpu, uErr, pRegFrame, pvFault, GCPtrStart,
337	pvFault - GCPtrStart, pvUser);
338
339	# ifdef VBOX_WITH_STATISTICS
340	pgmLock(pVM);
341	pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
342	if (pCur)
343	STAM_PROFILE_STOP(&pCur->Stat, h);
344	pgmUnlock(pVM);
345	# endif
346	# else
347	rcStrict = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
348	# endif
349	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersVirtual);
350	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndVirt; });
351	return rcStrict;
352	}
353	/* Unhandled part of a monitored page */
354	Log(("Unhandled part of monitored page %RGv\n", pvFault));
355	}
356	else
357	{
358	/* Check by physical address. */
359	unsigned iPage;
360	pCur = pgmHandlerVirtualFindByPhysAddr(pVM, pGstWalk->Core.GCPhys, &iPage);
361	if (pCur)
362	{
363	PPGMVIRTHANDLERTYPEINT pCurType = PGMVIRTANDLER_GET_TYPE(pVM, pCur);
364	if ( uErr & X86_TRAP_PF_RW
365	\|\| pCurType->enmKind != PGMVIRTHANDLERKIND_WRITE )
366	{
367	Assert( (pCur->aPhysToVirt[iPage].Core.Key & X86_PTE_PAE_PG_MASK)
368	== (pGstWalk->Core.GCPhys & X86_PTE_PAE_PG_MASK));
369	# ifdef IN_RC
370	STAM_PROFILE_START(&pCur->Stat, h);
371	RTGCPTR GCPtrStart = pCur->Core.Key;
372	void *pvUser = pCur->CTX_SUFF(pvUser);
373	pgmUnlock(pVM);
374	*pfLockTaken = false;
375
376	RTGCPTR off = (iPage << PAGE_SHIFT)
377	+ (pvFault & PAGE_OFFSET_MASK)
378	- (GCPtrStart & PAGE_OFFSET_MASK);
379	Assert(off < pCur->cb);
380	rcStrict = pCurType->CTX_SUFF(pfnPfHandler)(pVM, pVCpu, uErr, pRegFrame, pvFault, GCPtrStart, off, pvUser);
381
382	# ifdef VBOX_WITH_STATISTICS
383	pgmLock(pVM);
384	pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, GCPtrStart);
385	if (pCur)
386	STAM_PROFILE_STOP(&pCur->Stat, h);
387	pgmUnlock(pVM);
388	# endif
389	# else
390	rcStrict = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
391	# endif
392	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersVirtualByPhys);
393	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndVirt; });
394	return rcStrict;
395	}
396	}
397	}
398	}
399	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
400
401	/*
402	* There is a handled area of the page, but this fault doesn't belong to it.
403	* We must emulate the instruction.
404	*
405	* To avoid crashing (non-fatal) in the interpreter and go back to the recompiler
406	* we first check if this was a page-not-present fault for a page with only
407	* write access handlers. Restart the instruction if it wasn't a write access.
408	*/
409	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersUnhandled);
410
411	if ( !PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
412	&& !(uErr & X86_TRAP_PF_P))
413	{
414	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
415	rcStrict = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
416	# else
417	rcStrict = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
418	# endif
419	if ( RT_FAILURE(rcStrict)
420	\|\| rcStrict == VINF_PGM_SYNCPAGE_MODIFIED_PDE
421	\|\| !(uErr & X86_TRAP_PF_RW))
422	{
423	AssertMsgRC(rcStrict, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
424	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersOutOfSync);
425	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndPhys; });
426	return rcStrict;
427	}
428	}
429
430	/** @todo This particular case can cause quite a lot of overhead. E.g. early stage of kernel booting in Ubuntu 6.06
431	* It's writing to an unhandled part of the LDT page several million times.
432	*/
433	rcStrict = PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault);
434	LogFlow(("PGM: PGMInterpretInstruction -> rcStrict=%d pPage=%R[pgmpage]\n", VBOXSTRICTRC_VAL(rcStrict), pPage));
435	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndUnhandled; });
436	return rcStrict;
437	} /* if any kind of handler */
438
439
440	/**
441	* \#PF Handler for raw-mode guest execution.
442	*
443	* @returns VBox status code (appropriate for trap handling and GC return).
444	*
445	* @param pVCpu The cross context virtual CPU structure.
446	* @param uErr The trap error code.
447	* @param pRegFrame Trap register frame.
448	* @param pvFault The fault address.
449	* @param pfLockTaken PGM lock taken here or not (out)
450	*/
451	PGM_BTH_DECL(int, Trap0eHandler)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken)
452	{
453	PVM pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
454
455	*pfLockTaken = false;
456
457	# if ( PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \
458	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
459	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
460	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT)
461	int rc;
462
463	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
464	/*
465	* Walk the guest page translation tables and check if it's a guest fault.
466	*/
467	GSTPTWALK GstWalk;
468	rc = PGM_GST_NAME(Walk)(pVCpu, pvFault, &GstWalk);
469	if (RT_FAILURE_NP(rc))
470	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerGuestFault)(pVCpu, &GstWalk, uErr));
471
472	/* assert some GstWalk sanity. */
473	# if PGM_GST_TYPE == PGM_TYPE_AMD64
474	/AssertMsg(GstWalk.Pml4e.u == GstWalk.pPml4e->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pml4e.u, (uint64_t)GstWalk.pPml4e->u)); - not always true with SMP guests. /
475	# endif
476	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
477	/AssertMsg(GstWalk.Pdpe.u == GstWalk.pPdpe->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pdpe.u, (uint64_t)GstWalk.pPdpe->u)); - ditto /
478	# endif
479	/AssertMsg(GstWalk.Pde.u == GstWalk.pPde->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pde.u, (uint64_t)GstWalk.pPde->u)); - ditto /
480	/AssertMsg(GstWalk.Core.fBigPage \|\| GstWalk.Pte.u == GstWalk.pPte->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pte.u, (uint64_t)GstWalk.pPte->u)); - ditto /
481	Assert(GstWalk.Core.fSucceeded);
482
483	if (uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US \| X86_TRAP_PF_ID))
484	{
485	if ( ( (uErr & X86_TRAP_PF_RW)
486	&& !GstWalk.Core.fEffectiveRW
487	&& ( (uErr & X86_TRAP_PF_US)
488	\|\| CPUMIsGuestR0WriteProtEnabled(pVCpu)) )
489	\|\| ((uErr & X86_TRAP_PF_US) && !GstWalk.Core.fEffectiveUS)
490	\|\| ((uErr & X86_TRAP_PF_ID) && GstWalk.Core.fEffectiveNX)
491	)
492	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerGuestFault)(pVCpu, &GstWalk, uErr));
493	}
494
495	/*
496	* Set the accessed and dirty flags.
497	*/
498	# if PGM_GST_TYPE == PGM_TYPE_AMD64
499	GstWalk.Pml4e.u \|= X86_PML4E_A;
500	GstWalk.pPml4e->u \|= X86_PML4E_A;
501	GstWalk.Pdpe.u \|= X86_PDPE_A;
502	GstWalk.pPdpe->u \|= X86_PDPE_A;
503	# endif
504	if (GstWalk.Core.fBigPage)
505	{
506	Assert(GstWalk.Pde.b.u1Size);
507	if (uErr & X86_TRAP_PF_RW)
508	{
509	GstWalk.Pde.u \|= X86_PDE4M_A \| X86_PDE4M_D;
510	GstWalk.pPde->u \|= X86_PDE4M_A \| X86_PDE4M_D;
511	}
512	else
513	{
514	GstWalk.Pde.u \|= X86_PDE4M_A;
515	GstWalk.pPde->u \|= X86_PDE4M_A;
516	}
517	}
518	else
519	{
520	Assert(!GstWalk.Pde.b.u1Size);
521	GstWalk.Pde.u \|= X86_PDE_A;
522	GstWalk.pPde->u \|= X86_PDE_A;
523	if (uErr & X86_TRAP_PF_RW)
524	{
525	# ifdef VBOX_WITH_STATISTICS
526	if (!GstWalk.Pte.n.u1Dirty)
527	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtiedPage));
528	else
529	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageAlreadyDirty));
530	# endif
531	GstWalk.Pte.u \|= X86_PTE_A \| X86_PTE_D;
532	GstWalk.pPte->u \|= X86_PTE_A \| X86_PTE_D;
533	}
534	else
535	{
536	GstWalk.Pte.u \|= X86_PTE_A;
537	GstWalk.pPte->u \|= X86_PTE_A;
538	}
539	Assert(GstWalk.Pte.u == GstWalk.pPte->u);
540	}
541	AssertMsg(GstWalk.Pde.u == GstWalk.pPde->u \|\| GstWalk.pPte->u == GstWalk.pPde->u,
542	("%RX64 %RX64 pPte=%p pPde=%p Pte=%RX64\n", (uint64_t)GstWalk.Pde.u, (uint64_t)GstWalk.pPde->u, GstWalk.pPte, GstWalk.pPde, (uint64_t)GstWalk.pPte->u));
543	# else /* !PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
544	GSTPDE const PdeSrcDummy = { X86_PDE_P \| X86_PDE_US \| X86_PDE_RW \| X86_PDE_A}; /** @todo eliminate this */
545	# endif /* !PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
546
547	/* Take the big lock now. */
548	*pfLockTaken = true;
549	pgmLock(pVM);
550
551	# ifdef PGM_WITH_MMIO_OPTIMIZATIONS
552	/*
553	* If it is a reserved bit fault we know that it is an MMIO (access
554	* handler) related fault and can skip some 200 lines of code.
555	*/
556	if (uErr & X86_TRAP_PF_RSVD)
557	{
558	Assert(uErr & X86_TRAP_PF_P);
559	PPGMPAGE pPage;
560	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
561	rc = pgmPhysGetPageEx(pVM, GstWalk.Core.GCPhys, &pPage);
562	if (RT_SUCCESS(rc) && PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
563	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage,
564	pfLockTaken, &GstWalk));
565	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
566	# else
567	rc = pgmPhysGetPageEx(pVM, PGM_A20_APPLY(pVCpu, (RTGCPHYS)pvFault), &pPage);
568	if (RT_SUCCESS(rc) && PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
569	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage,
570	pfLockTaken));
571	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, 1, uErr);
572	#endif
573	AssertRC(rc);
574	PGM_INVL_PG(pVCpu, pvFault);
575	return rc; /* Restart with the corrected entry. */
576	}
577	# endif /* PGM_WITH_MMIO_OPTIMIZATIONS */
578
579	/*
580	* Fetch the guest PDE, PDPE and PML4E.
581	*/
582	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
583	const unsigned iPDDst = pvFault >> SHW_PD_SHIFT;
584	PX86PD pPDDst = pgmShwGet32BitPDPtr(pVCpu);
585
586	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
587	const unsigned iPDDst = (pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK; /* pPDDst index, not used with the pool. */
588	PX86PDPAE pPDDst;
589	# if PGM_GST_TYPE == PGM_TYPE_PAE
590	rc = pgmShwSyncPaePDPtr(pVCpu, pvFault, GstWalk.Pdpe.u, &pPDDst);
591	# else
592	rc = pgmShwSyncPaePDPtr(pVCpu, pvFault, X86_PDPE_P, &pPDDst); /* RW, US and A are reserved in PAE mode. */
593	# endif
594	AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
595
596	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
597	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
598	PX86PDPAE pPDDst;
599	# if PGM_GST_TYPE == PGM_TYPE_PROT /* (AMD-V nested paging) */
600	rc = pgmShwSyncLongModePDPtr(pVCpu, pvFault, X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A,
601	X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A, &pPDDst);
602	# else
603	rc = pgmShwSyncLongModePDPtr(pVCpu, pvFault, GstWalk.Pml4e.u, GstWalk.Pdpe.u, &pPDDst);
604	# endif
605	AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
606
607	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
608	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
609	PEPTPD pPDDst;
610	rc = pgmShwGetEPTPDPtr(pVCpu, pvFault, NULL, &pPDDst);
611	AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
612	# endif
613	Assert(pPDDst);
614
615	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
616	/*
617	* Dirty page handling.
618	*
619	* If we successfully correct the write protection fault due to dirty bit
620	* tracking, then return immediately.
621	*/
622	if (uErr & X86_TRAP_PF_RW) /* write fault? */
623	{
624	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyBitTracking), a);
625	rc = PGM_BTH_NAME(CheckDirtyPageFault)(pVCpu, uErr, &pPDDst->a[iPDDst], GstWalk.pPde, pvFault);
626	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyBitTracking), a);
627	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
628	{
629	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution)
630	= rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT
631	? &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2DirtyAndAccessed
632	: &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2GuestTrap; });
633	Log8(("Trap0eHandler: returns VINF_SUCCESS\n"));
634	return VINF_SUCCESS;
635	}
636	//AssertMsg(GstWalk.Pde.u == GstWalk.pPde->u \|\| GstWalk.pPte->u == GstWalk.pPde->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pde.u, (uint64_t)GstWalk.pPde->u)); - triggers with smp w7 guests.
637	//AssertMsg(GstWalk.Core.fBigPage \|\| GstWalk.Pte.u == GstWalk.pPte->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pte.u, (uint64_t)GstWalk.pPte->u)); - ditto.
638	}
639
640	# if 0 /* rarely useful; leave for debugging. */
641	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0ePD[iPDSrc]);
642	# endif
643	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
644
645	/*
646	* A common case is the not-present error caused by lazy page table syncing.
647	*
648	* It is IMPORTANT that we weed out any access to non-present shadow PDEs
649	* here so we can safely assume that the shadow PT is present when calling
650	* SyncPage later.
651	*
652	* On failure, we ASSUME that SyncPT is out of memory or detected some kind
653	* of mapping conflict and defer to SyncCR3 in R3.
654	* (Again, we do NOT support access handlers for non-present guest pages.)
655	*
656	*/
657	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
658	Assert(GstWalk.Pde.n.u1Present);
659	# endif
660	if ( !(uErr & X86_TRAP_PF_P) /* not set means page not present instead of page protection violation */
661	&& !pPDDst->a[iPDDst].n.u1Present)
662	{
663	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2SyncPT; });
664	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
665	LogFlow(("=>SyncPT %04x = %08RX64\n", (pvFault >> GST_PD_SHIFT) & GST_PD_MASK, (uint64_t)GstWalk.Pde.u));
666	rc = PGM_BTH_NAME(SyncPT)(pVCpu, (pvFault >> GST_PD_SHIFT) & GST_PD_MASK, GstWalk.pPd, pvFault);
667	# else
668	LogFlow(("=>SyncPT pvFault=%RGv\n", pvFault));
669	rc = PGM_BTH_NAME(SyncPT)(pVCpu, 0, NULL, pvFault);
670	# endif
671	if (RT_SUCCESS(rc))
672	return rc;
673	Log(("SyncPT: %RGv failed!! rc=%Rrc\n", pvFault, rc));
674	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync, right? */
675	return VINF_PGM_SYNC_CR3;
676	}
677
678	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(PGM_WITHOUT_MAPPINGS)
679	/*
680	* Check if this address is within any of our mappings.
681	*
682	* This is very fast and it's gonna save us a bit of effort below and prevent
683	* us from screwing ourself with MMIO2 pages which have a GC Mapping (VRam).
684	* (BTW, it's impossible to have physical access handlers in a mapping.)
685	*/
686	if (pgmMapAreMappingsEnabled(pVM))
687	{
688	PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
689	for ( ; pMapping; pMapping = pMapping->CTX_SUFF(pNext))
690	{
691	if (pvFault < pMapping->GCPtr)
692	break;
693	if (pvFault - pMapping->GCPtr < pMapping->cb)
694	{
695	/*
696	* The first thing we check is if we've got an undetected conflict.
697	*/
698	if (pgmMapAreMappingsFloating(pVM))
699	{
700	unsigned iPT = pMapping->cb >> GST_PD_SHIFT;
701	while (iPT-- > 0)
702	if (GstWalk.pPde[iPT].n.u1Present)
703	{
704	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eConflicts);
705	Log(("Trap0e: Detected Conflict %RGv-%RGv\n", pMapping->GCPtr, pMapping->GCPtrLast));
706	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync,right? */
707	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Mapping; });
708	return VINF_PGM_SYNC_CR3;
709	}
710	}
711
712	/*
713	* Check if the fault address is in a virtual page access handler range.
714	*/
715	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->HyperVirtHandlers,
716	pvFault);
717	if ( pCur
718	&& pvFault - pCur->Core.Key < pCur->cb
719	&& uErr & X86_TRAP_PF_RW)
720	{
721	VBOXSTRICTRC rcStrict;
722	# ifdef IN_RC
723	STAM_PROFILE_START(&pCur->Stat, h);
724	PPGMVIRTHANDLERTYPEINT pCurType = PGMVIRTANDLER_GET_TYPE(pVM, pCur);
725	void *pvUser = pCur->CTX_SUFF(pvUser);
726	pgmUnlock(pVM);
727	rcStrict = pCurType->CTX_SUFF(pfnPfHandler)(pVM, pVCpu, uErr, pRegFrame, pvFault, pCur->Core.Key,
728	pvFault - pCur->Core.Key, pvUser);
729	pgmLock(pVM);
730	STAM_PROFILE_STOP(&pCur->Stat, h);
731	# else
732	AssertFailed();
733	rcStrict = VINF_EM_RAW_EMULATE_INSTR; /* can't happen with VMX */
734	# endif
735	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersMapping);
736	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Mapping; });
737	return VBOXSTRICTRC_TODO(rcStrict);
738	}
739
740	/*
741	* Pretend we're not here and let the guest handle the trap.
742	*/
743	TRPMSetErrorCode(pVCpu, uErr & ~X86_TRAP_PF_P);
744	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eGuestPFMapping);
745	LogFlow(("PGM: Mapping access -> route trap to recompiler!\n"));
746	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Mapping; });
747	return VINF_EM_RAW_GUEST_TRAP;
748	}
749	}
750	} /* pgmAreMappingsEnabled(&pVM->pgm.s) */
751	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
752
753	/*
754	* Check if this fault address is flagged for special treatment,
755	* which means we'll have to figure out the physical address and
756	* check flags associated with it.
757	*
758	* ASSUME that we can limit any special access handling to pages
759	* in page tables which the guest believes to be present.
760	*/
761	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
762	RTGCPHYS GCPhys = GstWalk.Core.GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK;
763	# else
764	RTGCPHYS GCPhys = PGM_A20_APPLY(pVCpu, (RTGCPHYS)pvFault & ~(RTGCPHYS)PAGE_OFFSET_MASK);
765	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
766	PPGMPAGE pPage;
767	rc = pgmPhysGetPageEx(pVM, GCPhys, &pPage);
768	if (RT_FAILURE(rc))
769	{
770	/*
771	* When the guest accesses invalid physical memory (e.g. probing
772	* of RAM or accessing a remapped MMIO range), then we'll fall
773	* back to the recompiler to emulate the instruction.
774	*/
775	LogFlow(("PGM #PF: pgmPhysGetPageEx(%RGp) failed with %Rrc\n", GCPhys, rc));
776	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersInvalid);
777	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2InvalidPhys; });
778	return VINF_EM_RAW_EMULATE_INSTR;
779	}
780
781	/*
782	* Any handlers for this page?
783	*/
784	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
785	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
786	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage, pfLockTaken,
787	&GstWalk));
788	# else
789	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage, pfLockTaken));
790	# endif
791
792	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0)
793	if (uErr & X86_TRAP_PF_P)
794	{
795	/*
796	* The page isn't marked, but it might still be monitored by a virtual page access handler.
797	* (ASSUMES no temporary disabling of virtual handlers.)
798	*/
799	/** @todo r=bird: Since the purpose is to catch out of sync pages with virtual handler(s) here,
800	* we should correct both the shadow page table and physical memory flags, and not only check for
801	* accesses within the handler region but for access to pages with virtual handlers. */
802	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
803	if (pCur)
804	{
805	PPGMVIRTHANDLERTYPEINT pCurType = PGMVIRTANDLER_GET_TYPE(pVM, pCur);
806	AssertMsg( !(pvFault - pCur->Core.Key < pCur->cb)
807	\|\| ( pCurType->enmKind != PGMVIRTHANDLERKIND_WRITE
808	\|\| !(uErr & X86_TRAP_PF_P)
809	\|\| (pCurType->enmKind == PGMVIRTHANDLERKIND_WRITE && (uErr & X86_TRAP_PF_RW))),
810	("Unexpected trap for virtual handler: %08X (phys=%08x) %R[pgmpage] uErr=%X, enumKind=%d\n",
811	pvFault, GCPhys, pPage, uErr, pCurType->enmKind));
812
813	if ( pvFault - pCur->Core.Key < pCur->cb
814	&& ( uErr & X86_TRAP_PF_RW
815	\|\| pCurType->enmKind != PGMVIRTHANDLERKIND_WRITE ) )
816	{
817	VBOXSTRICTRC rcStrict;
818	# ifdef IN_RC
819	STAM_PROFILE_START(&pCur->Stat, h);
820	void *pvUser = pCur->CTX_SUFF(pvUser);
821	pgmUnlock(pVM);
822	rcStrict = pCurType->CTX_SUFF(pfnPfHandler)(pVM, pVCpu, uErr, pRegFrame, pvFault, pCur->Core.Key,
823	pvFault - pCur->Core.Key, pvUser);
824	pgmLock(pVM);
825	STAM_PROFILE_STOP(&pCur->Stat, h);
826	# else
827	rcStrict = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
828	# endif
829	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndVirt; });
830	return VBOXSTRICTRC_TODO(rcStrict);
831	}
832	}
833	}
834	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
835
836	/*
837	* We are here only if page is present in Guest page tables and
838	* trap is not handled by our handlers.
839	*
840	* Check it for page out-of-sync situation.
841	*/
842	if (!(uErr & X86_TRAP_PF_P))
843	{
844	/*
845	* Page is not present in our page tables. Try to sync it!
846	*/
847	if (uErr & X86_TRAP_PF_US)
848	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncUser));
849	else /* supervisor */
850	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
851
852	if (PGM_PAGE_IS_BALLOONED(pPage))
853	{
854	/* Emulate reads from ballooned pages as they are not present in
855	our shadow page tables. (Required for e.g. Solaris guests; soft
856	ecc, random nr generator.) */
857	rc = VBOXSTRICTRC_TODO(PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault));
858	LogFlow(("PGM: PGMInterpretInstruction balloon -> rc=%d pPage=%R[pgmpage]\n", rc, pPage));
859	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncBallloon));
860	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Ballooned; });
861	return rc;
862	}
863
864	# if defined(LOG_ENABLED) && !defined(IN_RING0)
865	RTGCPHYS GCPhys2;
866	uint64_t fPageGst2;
867	PGMGstGetPage(pVCpu, pvFault, &fPageGst2, &GCPhys2);
868	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
869	Log(("Page out of sync: %RGv eip=%08x PdeSrc.US=%d fPageGst2=%08llx GCPhys2=%RGp scan=%d\n",
870	pvFault, pRegFrame->eip, GstWalk.Pde.n.u1User, fPageGst2, GCPhys2, CSAMDoesPageNeedScanning(pVM, pRegFrame->eip)));
871	# else
872	Log(("Page out of sync: %RGv eip=%08x fPageGst2=%08llx GCPhys2=%RGp scan=%d\n",
873	pvFault, pRegFrame->eip, fPageGst2, GCPhys2, CSAMDoesPageNeedScanning(pVM, pRegFrame->eip)));
874	# endif
875	# endif /* LOG_ENABLED */
876
877	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0)
878	if ( !GstWalk.Core.fEffectiveUS
879	&& CSAMIsEnabled(pVM)
880	&& CPUMGetGuestCPL(pVCpu) == 0)
881	{
882	/* Note: Can't check for X86_TRAP_ID bit, because that requires execute disable support on the CPU. */
883	if ( pvFault == (RTGCPTR)pRegFrame->eip
884	\|\| pvFault - pRegFrame->eip < 8 /* instruction crossing a page boundary */
885	# ifdef CSAM_DETECT_NEW_CODE_PAGES
886	\|\| ( !PATMIsPatchGCAddr(pVM, pRegFrame->eip)
887	&& CSAMDoesPageNeedScanning(pVM, pRegFrame->eip)) /* any new code we encounter here */
888	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
889	)
890	{
891	LogFlow(("CSAMExecFault %RX32\n", pRegFrame->eip));
892	rc = CSAMExecFault(pVM, (RTRCPTR)pRegFrame->eip);
893	if (rc != VINF_SUCCESS)
894	{
895	/*
896	* CSAM needs to perform a job in ring 3.
897	*
898	* Sync the page before going to the host context; otherwise we'll end up in a loop if
899	* CSAM fails (e.g. instruction crosses a page boundary and the next page is not present)
900	*/
901	LogFlow(("CSAM ring 3 job\n"));
902	int rc2 = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
903	AssertRC(rc2);
904
905	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2CSAM; });
906	return rc;
907	}
908	}
909	# ifdef CSAM_DETECT_NEW_CODE_PAGES
910	else if ( uErr == X86_TRAP_PF_RW
911	&& pRegFrame->ecx >= 0x100 /* early check for movswd count */
912	&& pRegFrame->ecx < 0x10000)
913	{
914	/* In case of a write to a non-present supervisor shadow page, we'll take special precautions
915	* to detect loading of new code pages.
916	*/
917
918	/*
919	* Decode the instruction.
920	*/
921	PDISCPUSTATE pDis = &pVCpu->pgm.s.DisState;
922	uint32_t cbOp;
923	rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
924
925	/* For now we'll restrict this to rep movsw/d instructions */
926	if ( rc == VINF_SUCCESS
927	&& pDis->pCurInstr->opcode == OP_MOVSWD
928	&& (pDis->prefix & DISPREFIX_REP))
929	{
930	CSAMMarkPossibleCodePage(pVM, pvFault);
931	}
932	}
933	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
934
935	/*
936	* Mark this page as safe.
937	*/
938	/** @todo not correct for pages that contain both code and data!! */
939	Log2(("CSAMMarkPage %RGv; scanned=%d\n", pvFault, true));
940	CSAMMarkPage(pVM, pvFault, true);
941	}
942	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0) */
943	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
944	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
945	# else
946	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
947	# endif
948	if (RT_SUCCESS(rc))
949	{
950	/* The page was successfully synced, return to the guest. */
951	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSync; });
952	return VINF_SUCCESS;
953	}
954	}
955	else /* uErr & X86_TRAP_PF_P: */
956	{
957	/*
958	* Write protected pages are made writable when the guest makes the
959	* first write to it. This happens for pages that are shared, write
960	* monitored or not yet allocated.
961	*
962	* We may also end up here when CR0.WP=0 in the guest.
963	*
964	* Also, a side effect of not flushing global PDEs are out of sync
965	* pages due to physical monitored regions, that are no longer valid.
966	* Assume for now it only applies to the read/write flag.
967	*/
968	if (uErr & X86_TRAP_PF_RW)
969	{
970	/*
971	* Check if it is a read-only page.
972	*/
973	if (PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
974	{
975	Log(("PGM #PF: Make writable: %RGp %R[pgmpage] pvFault=%RGp uErr=%#x\n", GCPhys, pPage, pvFault, uErr));
976	Assert(!PGM_PAGE_IS_ZERO(pPage));
977	AssertFatalMsg(!PGM_PAGE_IS_BALLOONED(pPage), ("Unexpected ballooned page at %RGp\n", GCPhys));
978	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2MakeWritable; });
979
980	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
981	if (rc != VINF_SUCCESS)
982	{
983	AssertMsg(rc == VINF_PGM_SYNC_CR3 \|\| RT_FAILURE(rc), ("%Rrc\n", rc));
984	return rc;
985	}
986	if (RT_UNLIKELY(VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY)))
987	return VINF_EM_NO_MEMORY;
988	}
989
990	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
991	/*
992	* Check to see if we need to emulate the instruction if CR0.WP=0.
993	*/
994	if ( !GstWalk.Core.fEffectiveRW
995	&& (CPUMGetGuestCR0(pVCpu) & (X86_CR0_WP \| X86_CR0_PG)) == X86_CR0_PG
996	&& CPUMGetGuestCPL(pVCpu) < 3)
997	{
998	Assert((uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RW \| X86_TRAP_PF_P));
999
1000	/*
1001	* The Netware WP0+RO+US hack.
1002	*
1003	* Netware sometimes(/always?) runs with WP0. It has been observed doing
1004	* excessive write accesses to pages which are mapped with US=1 and RW=0
1005	* while WP=0. This causes a lot of exits and extremely slow execution.
1006	* To avoid trapping and emulating every write here, we change the shadow
1007	* page table entry to map it as US=0 and RW=1 until user mode tries to
1008	* access it again (see further below). We count these shadow page table
1009	* changes so we can avoid having to clear the page pool every time the WP
1010	* bit changes to 1 (see PGMCr0WpEnabled()).
1011	*/
1012	# if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) && 1
1013	if ( GstWalk.Core.fEffectiveUS
1014	&& !GstWalk.Core.fEffectiveRW
1015	&& (GstWalk.Core.fBigPage \|\| GstWalk.Pde.n.u1Write)
1016	&& pVM->cCpus == 1 /* Sorry, no go on SMP. Add CFGM option? */)
1017	{
1018	Log(("PGM #PF: Netware WP0+RO+US hack: pvFault=%RGp uErr=%#x (big=%d)\n", pvFault, uErr, GstWalk.Core.fBigPage));
1019	rc = pgmShwMakePageSupervisorAndWritable(pVCpu, pvFault, GstWalk.Core.fBigPage, PGM_MK_PG_IS_WRITE_FAULT);
1020	if (rc == VINF_SUCCESS \|\| rc == VINF_PGM_SYNC_CR3)
1021	{
1022	PGM_INVL_PG(pVCpu, pvFault);
1023	pVCpu->pgm.s.cNetwareWp0Hacks++;
1024	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Wp0RoUsHack; });
1025	return rc;
1026	}
1027	AssertMsg(RT_FAILURE_NP(rc), ("%Rrc\n", rc));
1028	Log(("pgmShwMakePageSupervisorAndWritable(%RGv) failed with rc=%Rrc - ignored\n", pvFault, rc));
1029	}
1030	# endif
1031
1032	/* Interpret the access. */
1033	rc = VBOXSTRICTRC_TODO(PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault));
1034	Log(("PGM #PF: WP0 emulation (pvFault=%RGp uErr=%#x cpl=%d fBig=%d fEffUs=%d)\n", pvFault, uErr, CPUMGetGuestCPL(pVCpu), GstWalk.Core.fBigPage, GstWalk.Core.fEffectiveUS));
1035	if (RT_SUCCESS(rc))
1036	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eWPEmulInRZ);
1037	else
1038	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eWPEmulToR3);
1039	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2WPEmulation; });
1040	return rc;
1041	}
1042	# endif
1043	/// @todo count the above case; else
1044	if (uErr & X86_TRAP_PF_US)
1045	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncUserWrite));
1046	else /* supervisor */
1047	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncSupervisorWrite));
1048
1049	/*
1050	* Sync the page.
1051	*
1052	* Note: Do NOT use PGM_SYNC_NR_PAGES here. That only works if the
1053	* page is not present, which is not true in this case.
1054	*/
1055	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1056	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
1057	# else
1058	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, 1, uErr);
1059	# endif
1060	if (RT_SUCCESS(rc))
1061	{
1062	/*
1063	* Page was successfully synced, return to guest but invalidate
1064	* the TLB first as the page is very likely to be in it.
1065	*/
1066	# if PGM_SHW_TYPE == PGM_TYPE_EPT
1067	HMInvalidatePhysPage(pVM, (RTGCPHYS)pvFault);
1068	# else
1069	PGM_INVL_PG(pVCpu, pvFault);
1070	# endif
1071	# ifdef VBOX_STRICT
1072	RTGCPHYS GCPhys2 = RTGCPHYS_MAX;
1073	uint64_t fPageGst = UINT64_MAX;
1074	if (!pVM->pgm.s.fNestedPaging)
1075	{
1076	rc = PGMGstGetPage(pVCpu, pvFault, &fPageGst, &GCPhys2);
1077	AssertMsg(RT_SUCCESS(rc) && ((fPageGst & X86_PTE_RW) \|\| ((CPUMGetGuestCR0(pVCpu) & (X86_CR0_WP \| X86_CR0_PG)) == X86_CR0_PG && CPUMGetGuestCPL(pVCpu) < 3)), ("rc=%Rrc fPageGst=%RX64\n", rc, fPageGst));
1078	LogFlow(("Obsolete physical monitor page out of sync %RGv - phys %RGp flags=%08llx\n", pvFault, GCPhys2, (uint64_t)fPageGst));
1079	}
1080	# if 0 /* Bogus! Triggers incorrectly with w7-64 and later for the SyncPage case: "Pde at %RGv changed behind our back?" */
1081	uint64_t fPageShw = 0;
1082	rc = PGMShwGetPage(pVCpu, pvFault, &fPageShw, NULL);
1083	AssertMsg((RT_SUCCESS(rc) && (fPageShw & X86_PTE_RW)) \|\| pVM->cCpus > 1 /* new monitor can be installed/page table flushed between the trap exit and PGMTrap0eHandler */,
1084	("rc=%Rrc fPageShw=%RX64 GCPhys2=%RGp fPageGst=%RX64 pvFault=%RGv\n", rc, fPageShw, GCPhys2, fPageGst, pvFault));
1085	# endif
1086	# endif /* VBOX_STRICT */
1087	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndObs; });
1088	return VINF_SUCCESS;
1089	}
1090	}
1091	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1092	/*
1093	* Check for Netware WP0+RO+US hack from above and undo it when user
1094	* mode accesses the page again.
1095	*/
1096	else if ( GstWalk.Core.fEffectiveUS
1097	&& !GstWalk.Core.fEffectiveRW
1098	&& (GstWalk.Core.fBigPage \|\| GstWalk.Pde.n.u1Write)
1099	&& pVCpu->pgm.s.cNetwareWp0Hacks > 0
1100	&& (CPUMGetGuestCR0(pVCpu) & (X86_CR0_WP \| X86_CR0_PG)) == X86_CR0_PG
1101	&& CPUMGetGuestCPL(pVCpu) == 3
1102	&& pVM->cCpus == 1
1103	)
1104	{
1105	Log(("PGM #PF: Undo netware WP0+RO+US hack: pvFault=%RGp uErr=%#x\n", pvFault, uErr));
1106	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
1107	if (RT_SUCCESS(rc))
1108	{
1109	PGM_INVL_PG(pVCpu, pvFault);
1110	pVCpu->pgm.s.cNetwareWp0Hacks--;
1111	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Wp0RoUsUnhack; });
1112	return VINF_SUCCESS;
1113	}
1114	}
1115	# endif /* PGM_WITH_PAGING */
1116
1117	/** @todo else: why are we here? */
1118
1119	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && defined(VBOX_STRICT)
1120	/*
1121	* Check for VMM page flags vs. Guest page flags consistency.
1122	* Currently only for debug purposes.
1123	*/
1124	if (RT_SUCCESS(rc))
1125	{
1126	/* Get guest page flags. */
1127	uint64_t fPageGst;
1128	int rc2 = PGMGstGetPage(pVCpu, pvFault, &fPageGst, NULL);
1129	if (RT_SUCCESS(rc2))
1130	{
1131	uint64_t fPageShw = 0;
1132	rc2 = PGMShwGetPage(pVCpu, pvFault, &fPageShw, NULL);
1133
1134	/*
1135	* Compare page flags.
1136	* Note: we have AVL, A, D bits desynced.
1137	*/
1138	AssertMsg( (fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK))
1139	== (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK))
1140	\|\| ( pVCpu->pgm.s.cNetwareWp0Hacks > 0
1141	&& (fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK \| X86_PTE_RW \| X86_PTE_US))
1142	== (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK \| X86_PTE_RW \| X86_PTE_US))
1143	&& (fPageShw & (X86_PTE_RW \| X86_PTE_US)) == X86_PTE_RW
1144	&& (fPageGst & (X86_PTE_RW \| X86_PTE_US)) == X86_PTE_US),
1145	("Page flags mismatch! pvFault=%RGv uErr=%x GCPhys=%RGp fPageShw=%RX64 fPageGst=%RX64 rc=%d\n",
1146	pvFault, (uint32_t)uErr, GCPhys, fPageShw, fPageGst, rc));
1147	}
1148	else
1149	AssertMsgFailed(("PGMGstGetPage rc=%Rrc\n", rc));
1150	}
1151	else
1152	AssertMsgFailed(("PGMGCGetPage rc=%Rrc\n", rc));
1153	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && VBOX_STRICT */
1154	}
1155
1156
1157	/*
1158	* If we get here it is because something failed above, i.e. most like guru
1159	* meditiation time.
1160	*/
1161	LogRel(("%s: returns rc=%Rrc pvFault=%RGv uErr=%RX64 cs:rip=%04x:%08RX64\n",
1162	__PRETTY_FUNCTION__, rc, pvFault, (uint64_t)uErr, pRegFrame->cs.Sel, pRegFrame->rip));
1163	return rc;
1164
1165	# else /* Nested paging, EPT except PGM_GST_TYPE = PROT */
1166	NOREF(uErr); NOREF(pRegFrame); NOREF(pvFault);
1167	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
1168	return VERR_PGM_NOT_USED_IN_MODE;
1169	# endif
1170	}
1171	#endif /* !IN_RING3 */
1172
1173
1174	/**
1175	* Emulation of the invlpg instruction.
1176	*
1177	*
1178	* @returns VBox status code.
1179	*
1180	* @param pVCpu The cross context virtual CPU structure.
1181	* @param GCPtrPage Page to invalidate.
1182	*
1183	* @remark ASSUMES that the guest is updating before invalidating. This order
1184	* isn't required by the CPU, so this is speculative and could cause
1185	* trouble.
1186	* @remark No TLB shootdown is done on any other VCPU as we assume that
1187	* invlpg emulation is the only reason for calling this function.
1188	* (The guest has to shoot down TLB entries on other CPUs itself)
1189	* Currently true, but keep in mind!
1190	*
1191	* @todo Clean this up! Most of it is (or should be) no longer necessary as we catch all page table accesses.
1192	* Should only be required when PGMPOOL_WITH_OPTIMIZED_DIRTY_PT is active (PAE or AMD64 (for now))
1193	*/
1194	PGM_BTH_DECL(int, InvalidatePage)(PVMCPU pVCpu, RTGCPTR GCPtrPage)
1195	{
1196	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
1197	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
1198	&& PGM_SHW_TYPE != PGM_TYPE_EPT
1199	int rc;
1200	PVM pVM = pVCpu->CTX_SUFF(pVM);
1201	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1202
1203	PGM_LOCK_ASSERT_OWNER(pVM);
1204
1205	LogFlow(("InvalidatePage %RGv\n", GCPtrPage));
1206
1207	/*
1208	* Get the shadow PD entry and skip out if this PD isn't present.
1209	* (Guessing that it is frequent for a shadow PDE to not be present, do this first.)
1210	*/
1211	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1212	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1213	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
1214
1215	/* Fetch the pgm pool shadow descriptor. */
1216	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
1217	Assert(pShwPde);
1218
1219	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1220	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT);
1221	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(pVCpu);
1222
1223	/* If the shadow PDPE isn't present, then skip the invalidate. */
1224	if (!pPdptDst->a[iPdpt].n.u1Present)
1225	{
1226	Assert(!(pPdptDst->a[iPdpt].u & PGM_PLXFLAGS_MAPPING));
1227	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1228	PGM_INVL_PG(pVCpu, GCPtrPage);
1229	return VINF_SUCCESS;
1230	}
1231
1232	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1233	PPGMPOOLPAGE pShwPde = NULL;
1234	PX86PDPAE pPDDst;
1235
1236	/* Fetch the pgm pool shadow descriptor. */
1237	rc = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
1238	AssertRCSuccessReturn(rc, rc);
1239	Assert(pShwPde);
1240
1241	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
1242	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1243
1244	# else /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
1245	/* PML4 */
1246	/const unsigned iPml4 = (GCPtrPage >> X86_PML4_SHIFT) & X86_PML4_MASK;/
1247	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1248	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1249	PX86PDPAE pPDDst;
1250	PX86PDPT pPdptDst;
1251	PX86PML4E pPml4eDst;
1252	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eDst, &pPdptDst, &pPDDst);
1253	if (rc != VINF_SUCCESS)
1254	{
1255	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT \|\| rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
1256	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1257	PGM_INVL_PG(pVCpu, GCPtrPage);
1258	return VINF_SUCCESS;
1259	}
1260	Assert(pPDDst);
1261
1262	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1263	PX86PDPE pPdpeDst = &pPdptDst->a[iPdpt];
1264
1265	if (!pPdpeDst->n.u1Present)
1266	{
1267	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1268	PGM_INVL_PG(pVCpu, GCPtrPage);
1269	return VINF_SUCCESS;
1270	}
1271
1272	/* Fetch the pgm pool shadow descriptor. */
1273	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & SHW_PDPE_PG_MASK);
1274	Assert(pShwPde);
1275
1276	# endif /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
1277
1278	const SHWPDE PdeDst = *pPdeDst;
1279	if (!PdeDst.n.u1Present)
1280	{
1281	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1282	PGM_INVL_PG(pVCpu, GCPtrPage);
1283	return VINF_SUCCESS;
1284	}
1285
1286	/*
1287	* Get the guest PD entry and calc big page.
1288	*/
1289	# if PGM_GST_TYPE == PGM_TYPE_32BIT
1290	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
1291	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
1292	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
1293	# else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1294	unsigned iPDSrc = 0;
1295	# if PGM_GST_TYPE == PGM_TYPE_PAE
1296	X86PDPE PdpeSrcIgn;
1297	PX86PDPAE pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtrPage, &iPDSrc, &PdpeSrcIgn);
1298	# else /* AMD64 */
1299	PX86PML4E pPml4eSrcIgn;
1300	X86PDPE PdpeSrcIgn;
1301	PX86PDPAE pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eSrcIgn, &PdpeSrcIgn, &iPDSrc);
1302	# endif
1303	GSTPDE PdeSrc;
1304
1305	if (pPDSrc)
1306	PdeSrc = pPDSrc->a[iPDSrc];
1307	else
1308	PdeSrc.u = 0;
1309	# endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1310	const bool fIsBigPage = PdeSrc.b.u1Size && GST_IS_PSE_ACTIVE(pVCpu);
1311
1312	# ifdef IN_RING3
1313	/*
1314	* If a CR3 Sync is pending we may ignore the invalidate page operation
1315	* depending on the kind of sync and if it's a global page or not.
1316	* This doesn't make sense in GC/R0 so we'll skip it entirely there.
1317	*/
1318	# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
1319	if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3)
1320	\|\| ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
1321	&& fIsBigPage
1322	&& PdeSrc.b.u1Global
1323	)
1324	)
1325	# else
1326	if (VM_FF_IS_PENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL) )
1327	# endif
1328	{
1329	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1330	return VINF_SUCCESS;
1331	}
1332	# endif /* IN_RING3 */
1333
1334	/*
1335	* Deal with the Guest PDE.
1336	*/
1337	rc = VINF_SUCCESS;
1338	if (PdeSrc.n.u1Present)
1339	{
1340	Assert( PdeSrc.n.u1User == PdeDst.n.u1User
1341	&& (PdeSrc.n.u1Write \|\| !PdeDst.n.u1Write \|\| pVCpu->pgm.s.cNetwareWp0Hacks > 0));
1342	# ifndef PGM_WITHOUT_MAPPING
1343	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
1344	{
1345	/*
1346	* Conflict - Let SyncPT deal with it to avoid duplicate code.
1347	*/
1348	Assert(pgmMapAreMappingsEnabled(pVM));
1349	Assert(PGMGetGuestMode(pVCpu) <= PGMMODE_PAE);
1350	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
1351	}
1352	else
1353	# endif /* !PGM_WITHOUT_MAPPING */
1354	if (!fIsBigPage)
1355	{
1356	/*
1357	* 4KB - page.
1358	*/
1359	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1360	RTGCPHYS GCPhys = GST_GET_PDE_GCPHYS(PdeSrc);
1361
1362	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1363	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1364	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| ((iPDDst & 1) * (PAGE_SIZE / 2)));
1365	# endif
1366	if (pShwPage->GCPhys == GCPhys)
1367	{
1368	/* Syncing it here isn't 100% safe and it's probably not worth spending time syncing it. */
1369	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1370
1371	PGSTPT pPTSrc;
1372	rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GST_GET_PDE_GCPHYS(PdeSrc), &pPTSrc);
1373	if (RT_SUCCESS(rc))
1374	{
1375	const unsigned iPTSrc = (GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK;
1376	GSTPTE PteSrc = pPTSrc->a[iPTSrc];
1377	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1378	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1379	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx %s\n",
1380	GCPtrPage, PteSrc.n.u1Present,
1381	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1382	PteSrc.n.u1User & PdeSrc.n.u1User,
1383	(uint64_t)PteSrc.u,
1384	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
1385	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
1386	}
1387	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePage4KBPages));
1388	PGM_INVL_PG(pVCpu, GCPtrPage);
1389	}
1390	else
1391	{
1392	/*
1393	* The page table address changed.
1394	*/
1395	LogFlow(("InvalidatePage: Out-of-sync at %RGp PdeSrc=%RX64 PdeDst=%RX64 ShwGCPhys=%RGp iPDDst=%#x\n",
1396	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, iPDDst));
1397	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1398	ASMAtomicWriteSize(pPdeDst, 0);
1399	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1400	PGM_INVL_VCPU_TLBS(pVCpu);
1401	}
1402	}
1403	else
1404	{
1405	/*
1406	* 2/4MB - page.
1407	*/
1408	/* Before freeing the page, check if anything really changed. */
1409	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1410	RTGCPHYS GCPhys = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
1411	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1412	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1413	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| (GCPtrPage & (1 << X86_PD_PAE_SHIFT)));
1414	# endif
1415	if ( pShwPage->GCPhys == GCPhys
1416	&& pShwPage->enmKind == BTH_PGMPOOLKIND_PT_FOR_BIG)
1417	{
1418	/* ASSUMES a the given bits are identical for 4M and normal PDEs */
1419	/** @todo This test is wrong as it cannot check the G bit!
1420	* FIXME */
1421	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US))
1422	== (PdeDst.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US))
1423	&& ( PdeSrc.b.u1Dirty /** @todo rainy day: What about read-only 4M pages? not very common, but still... */
1424	\|\| (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)))
1425	{
1426	LogFlow(("Skipping flush for big page containing %RGv (PD=%X .u=%RX64)-> nothing has changed!\n", GCPtrPage, iPDSrc, PdeSrc.u));
1427	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePage4MBPagesSkip));
1428	return VINF_SUCCESS;
1429	}
1430	}
1431
1432	/*
1433	* Ok, the page table is present and it's been changed in the guest.
1434	* If we're in host context, we'll just mark it as not present taking the lazy approach.
1435	* We could do this for some flushes in GC too, but we need an algorithm for
1436	* deciding which 4MB pages containing code likely to be executed very soon.
1437	*/
1438	LogFlow(("InvalidatePage: Out-of-sync PD at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
1439	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1440	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1441	ASMAtomicWriteSize(pPdeDst, 0);
1442	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePage4MBPages));
1443	PGM_INVL_BIG_PG(pVCpu, GCPtrPage);
1444	}
1445	}
1446	else
1447	{
1448	/*
1449	* Page directory is not present, mark shadow PDE not present.
1450	*/
1451	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
1452	{
1453	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1454	ASMAtomicWriteSize(pPdeDst, 0);
1455	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePagePDNPs));
1456	PGM_INVL_PG(pVCpu, GCPtrPage);
1457	}
1458	else
1459	{
1460	Assert(pgmMapAreMappingsEnabled(pVM));
1461	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePagePDMappings));
1462	}
1463	}
1464	return rc;
1465
1466	#else /* guest real and protected mode */
1467	/* There's no such thing as InvalidatePage when paging is disabled, so just ignore. */
1468	NOREF(pVCpu); NOREF(GCPtrPage);
1469	return VINF_SUCCESS;
1470	#endif
1471	}
1472
1473
1474	/**
1475	* Update the tracking of shadowed pages.
1476	*
1477	* @param pVCpu The cross context virtual CPU structure.
1478	* @param pShwPage The shadow page.
1479	* @param HCPhys The physical page we is being dereferenced.
1480	* @param iPte Shadow PTE index
1481	* @param GCPhysPage Guest physical address (only valid if pShwPage->fDirty is set)
1482	*/
1483	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVMCPU pVCpu, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys, uint16_t iPte,
1484	RTGCPHYS GCPhysPage)
1485	{
1486	PVM pVM = pVCpu->CTX_SUFF(pVM);
1487
1488	# if defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT) \
1489	&& PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
1490	&& (PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_PAE /* pae/32bit combo */)
1491
1492	/* Use the hint we retrieved from the cached guest PT. */
1493	if (pShwPage->fDirty)
1494	{
1495	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1496
1497	Assert(pShwPage->cPresent);
1498	Assert(pPool->cPresent);
1499	pShwPage->cPresent--;
1500	pPool->cPresent--;
1501
1502	PPGMPAGE pPhysPage = pgmPhysGetPage(pVM, GCPhysPage);
1503	AssertRelease(pPhysPage);
1504	pgmTrackDerefGCPhys(pPool, pShwPage, pPhysPage, iPte);
1505	return;
1506	}
1507	# else
1508	NOREF(GCPhysPage);
1509	# endif
1510
1511	STAM_PROFILE_START(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackDeref, a);
1512	LogFlow(("SyncPageWorkerTrackDeref: Damn HCPhys=%RHp pShwPage->idx=%#x!!!\n", HCPhys, pShwPage->idx));
1513
1514	/** @todo If this turns out to be a bottle neck (very likely) two things can be done:
1515	* 1. have a medium sized HCPhys -> GCPhys TLB (hash?)
1516	* 2. write protect all shadowed pages. I.e. implement caching.
1517	*/
1518	/** @todo duplicated in the 2nd half of pgmPoolTracDerefGCPhysHint */
1519
1520	/*
1521	* Find the guest address.
1522	*/
1523	for (PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRangesX);
1524	pRam;
1525	pRam = pRam->CTX_SUFF(pNext))
1526	{
1527	unsigned iPage = pRam->cb >> PAGE_SHIFT;
1528	while (iPage-- > 0)
1529	{
1530	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
1531	{
1532	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1533
1534	Assert(pShwPage->cPresent);
1535	Assert(pPool->cPresent);
1536	pShwPage->cPresent--;
1537	pPool->cPresent--;
1538
1539	pgmTrackDerefGCPhys(pPool, pShwPage, &pRam->aPages[iPage], iPte);
1540	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackDeref, a);
1541	return;
1542	}
1543	}
1544	}
1545
1546	for (;;)
1547	AssertReleaseMsgFailed(("HCPhys=%RHp wasn't found!\n", HCPhys));
1548	}
1549
1550
1551	/**
1552	* Update the tracking of shadowed pages.
1553	*
1554	* @param pVCpu The cross context virtual CPU structure.
1555	* @param pShwPage The shadow page.
1556	* @param u16 The top 16-bit of the pPage->HCPhys.
1557	* @param pPage Pointer to the guest page. this will be modified.
1558	* @param iPTDst The index into the shadow table.
1559	*/
1560	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackAddref)(PVMCPU pVCpu, PPGMPOOLPAGE pShwPage, uint16_t u16, PPGMPAGE pPage, const unsigned iPTDst)
1561	{
1562	PVM pVM = pVCpu->CTX_SUFF(pVM);
1563
1564	/*
1565	* Just deal with the simple first time here.
1566	*/
1567	if (!u16)
1568	{
1569	STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackVirgin);
1570	u16 = PGMPOOL_TD_MAKE(1, pShwPage->idx);
1571	/* Save the page table index. */
1572	PGM_PAGE_SET_PTE_INDEX(pVM, pPage, iPTDst);
1573	}
1574	else
1575	u16 = pgmPoolTrackPhysExtAddref(pVM, pPage, u16, pShwPage->idx, iPTDst);
1576
1577	/* write back */
1578	Log2(("SyncPageWorkerTrackAddRef: u16=%#x->%#x iPTDst=%#x\n", u16, PGM_PAGE_GET_TRACKING(pPage), iPTDst));
1579	PGM_PAGE_SET_TRACKING(pVM, pPage, u16);
1580
1581	/* update statistics. */
1582	pVM->pgm.s.CTX_SUFF(pPool)->cPresent++;
1583	pShwPage->cPresent++;
1584	if (pShwPage->iFirstPresent > iPTDst)
1585	pShwPage->iFirstPresent = iPTDst;
1586	}
1587
1588
1589	/**
1590	* Modifies a shadow PTE to account for access handlers.
1591	*
1592	* @param pVM The cross context VM structure.
1593	* @param pPage The page in question.
1594	* @param fPteSrc The shadowed flags of the source PTE. Must include the
1595	* A (accessed) bit so it can be emulated correctly.
1596	* @param pPteDst The shadow PTE (output). This is temporary storage and
1597	* does not need to be set atomically.
1598	*/
1599	DECLINLINE(void) PGM_BTH_NAME(SyncHandlerPte)(PVM pVM, PCPGMPAGE pPage, uint64_t fPteSrc, PSHWPTE pPteDst)
1600	{
1601	NOREF(pVM); RT_NOREF_PV(fPteSrc);
1602
1603	/** @todo r=bird: Are we actually handling dirty and access bits for pages with access handlers correctly? No.
1604	* Update: \#PF should deal with this before or after calling the handlers. It has all the info to do the job efficiently. */
1605	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1606	{
1607	LogFlow(("SyncHandlerPte: monitored page (%R[pgmpage]) -> mark read-only\n", pPage));
1608	#if PGM_SHW_TYPE == PGM_TYPE_EPT
1609	pPteDst->u = PGM_PAGE_GET_HCPHYS(pPage);
1610	pPteDst->n.u1Present = 1;
1611	pPteDst->n.u1Execute = 1;
1612	pPteDst->n.u1IgnorePAT = 1;
1613	pPteDst->n.u3EMT = VMX_EPT_MEMTYPE_WB;
1614	/* PteDst.n.u1Write = 0 && PteDst.n.u1Size = 0 */
1615	#else
1616	if (fPteSrc & X86_PTE_A)
1617	{
1618	SHW_PTE_SET(*pPteDst, fPteSrc \| PGM_PAGE_GET_HCPHYS(pPage));
1619	SHW_PTE_SET_RO(*pPteDst);
1620	}
1621	else
1622	SHW_PTE_SET(*pPteDst, 0);
1623	#endif
1624	}
1625	#ifdef PGM_WITH_MMIO_OPTIMIZATIONS
1626	# if PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
1627	else if ( PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
1628	&& ( BTH_IS_NP_ACTIVE(pVM)
1629	\|\| (fPteSrc & (X86_PTE_RW \| X86_PTE_US)) == X86_PTE_RW) /** @todo Remove X86_PTE_US here and pGstWalk->Core.fEffectiveUS before the sync page test. */
1630	# if PGM_SHW_TYPE == PGM_TYPE_AMD64
1631	&& pVM->pgm.s.fLessThan52PhysicalAddressBits
1632	# endif
1633	)
1634	{
1635	LogFlow(("SyncHandlerPte: MMIO page -> invalid \n"));
1636	# if PGM_SHW_TYPE == PGM_TYPE_EPT
1637	/* 25.2.3.1: Reserved physical address bit -> EPT Misconfiguration (exit 49) */
1638	pPteDst->u = pVM->pgm.s.HCPhysInvMmioPg;
1639	/* 25.2.3.1: bits 2:0 = 010b -> EPT Misconfiguration (exit 49) */
1640	pPteDst->n.u1Present = 0;
1641	pPteDst->n.u1Write = 1;
1642	pPteDst->n.u1Execute = 0;
1643	/* 25.2.3.1: leaf && 2:0 != 0 && u3Emt in {2, 3, 7} -> EPT Misconfiguration */
1644	pPteDst->n.u3EMT = 7;
1645	# else
1646	/* Set high page frame bits that MBZ (bankers on PAE, CPU dependent on AMD64). */
1647	SHW_PTE_SET(*pPteDst, pVM->pgm.s.HCPhysInvMmioPg \| X86_PTE_PAE_MBZ_MASK_NO_NX \| X86_PTE_P);
1648	# endif
1649	}
1650	# endif
1651	#endif /* PGM_WITH_MMIO_OPTIMIZATIONS */
1652	else
1653	{
1654	LogFlow(("SyncHandlerPte: monitored page (%R[pgmpage]) -> mark not present\n", pPage));
1655	SHW_PTE_SET(*pPteDst, 0);
1656	}
1657	/** @todo count these kinds of entries. */
1658	}
1659
1660
1661	/**
1662	* Creates a 4K shadow page for a guest page.
1663	*
1664	* For 4M pages the caller must convert the PDE4M to a PTE, this includes adjusting the
1665	* physical address. The PdeSrc argument only the flags are used. No page
1666	* structured will be mapped in this function.
1667	*
1668	* @param pVCpu The cross context virtual CPU structure.
1669	* @param pPteDst Destination page table entry.
1670	* @param PdeSrc Source page directory entry (i.e. Guest OS page directory entry).
1671	* Can safely assume that only the flags are being used.
1672	* @param PteSrc Source page table entry (i.e. Guest OS page table entry).
1673	* @param pShwPage Pointer to the shadow page.
1674	* @param iPTDst The index into the shadow table.
1675	*
1676	* @remark Not used for 2/4MB pages!
1677	*/
1678	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \|\| defined(DOXYGEN_RUNNING)
1679	static void PGM_BTH_NAME(SyncPageWorker)(PVMCPU pVCpu, PSHWPTE pPteDst, GSTPDE PdeSrc, GSTPTE PteSrc,
1680	PPGMPOOLPAGE pShwPage, unsigned iPTDst)
1681	#else
1682	static void PGM_BTH_NAME(SyncPageWorker)(PVMCPU pVCpu, PSHWPTE pPteDst, RTGCPHYS GCPhysPage,
1683	PPGMPOOLPAGE pShwPage, unsigned iPTDst)
1684	#endif
1685	{
1686	PVM pVM = pVCpu->CTX_SUFF(pVM);
1687	RTGCPHYS GCPhysOldPage = NIL_RTGCPHYS;
1688
1689	#if defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT) \
1690	&& PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
1691	&& (PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_PAE /* pae/32bit combo */)
1692
1693	if (pShwPage->fDirty)
1694	{
1695	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1696	PGSTPT pGstPT;
1697
1698	/* Note that iPTDst can be used to index the guest PT even in the pae/32bit combo as we copy only half the table; see pgmPoolAddDirtyPage. */
1699	pGstPT = (PGSTPT)&pPool->aDirtyPages[pShwPage->idxDirtyEntry].aPage[0];
1700	GCPhysOldPage = GST_GET_PTE_GCPHYS(pGstPT->a[iPTDst]);
1701	pGstPT->a[iPTDst].u = PteSrc.u;
1702	}
1703	#else
1704	Assert(!pShwPage->fDirty);
1705	#endif
1706
1707	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1708	if ( PteSrc.n.u1Present
1709	&& GST_IS_PTE_VALID(pVCpu, PteSrc))
1710	#endif
1711	{
1712	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1713	RTGCPHYS GCPhysPage = GST_GET_PTE_GCPHYS(PteSrc);
1714	# endif
1715	PGM_A20_ASSERT_MASKED(pVCpu, GCPhysPage);
1716
1717	/*
1718	* Find the ram range.
1719	*/
1720	PPGMPAGE pPage;
1721	int rc = pgmPhysGetPageEx(pVM, GCPhysPage, &pPage);
1722	if (RT_SUCCESS(rc))
1723	{
1724	/* Ignore ballooned pages.
1725	Don't return errors or use a fatal assert here as part of a
1726	shadow sync range might included ballooned pages. */
1727	if (PGM_PAGE_IS_BALLOONED(pPage))
1728	{
1729	Assert(!SHW_PTE_IS_P(pPteDst)); /* @todo user tracking needs updating if this triggers. */
1730	return;
1731	}
1732
1733	#ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
1734	/* Make the page writable if necessary. */
1735	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
1736	&& ( PGM_PAGE_IS_ZERO(pPage)
1737	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1738	\|\| ( PteSrc.n.u1Write
1739	# else
1740	\|\| ( 1
1741	# endif
1742	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
1743	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
1744	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
1745	# endif
1746	# ifdef VBOX_WITH_PAGE_SHARING
1747	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
1748	# endif
1749	)
1750	)
1751	)
1752	{
1753	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhysPage);
1754	AssertRC(rc);
1755	}
1756	#endif
1757
1758	/*
1759	* Make page table entry.
1760	*/
1761	SHWPTE PteDst;
1762	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1763	uint64_t fGstShwPteFlags = GST_GET_PTE_SHW_FLAGS(pVCpu, PteSrc);
1764	# else
1765	uint64_t fGstShwPteFlags = X86_PTE_P \| X86_PTE_RW \| X86_PTE_US \| X86_PTE_A \| X86_PTE_D;
1766	# endif
1767	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1768	PGM_BTH_NAME(SyncHandlerPte)(pVM, pPage, fGstShwPteFlags, &PteDst);
1769	else
1770	{
1771	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1772	/*
1773	* If the page or page directory entry is not marked accessed,
1774	* we mark the page not present.
1775	*/
1776	if (!PteSrc.n.u1Accessed \|\| !PdeSrc.n.u1Accessed)
1777	{
1778	LogFlow(("SyncPageWorker: page and or page directory not accessed -> mark not present\n"));
1779	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,AccessedPage));
1780	SHW_PTE_SET(PteDst, 0);
1781	}
1782	/*
1783	* If the page is not flagged as dirty and is writable, then make it read-only, so we can set the dirty bit
1784	* when the page is modified.
1785	*/
1786	else if (!PteSrc.n.u1Dirty && (PdeSrc.n.u1Write & PteSrc.n.u1Write))
1787	{
1788	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPage));
1789	SHW_PTE_SET(PteDst,
1790	fGstShwPteFlags
1791	\| PGM_PAGE_GET_HCPHYS(pPage)
1792	\| PGM_PTFLAGS_TRACK_DIRTY);
1793	SHW_PTE_SET_RO(PteDst);
1794	}
1795	else
1796	#endif
1797	{
1798	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageSkipped));
1799	#if PGM_SHW_TYPE == PGM_TYPE_EPT
1800	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage);
1801	PteDst.n.u1Present = 1;
1802	PteDst.n.u1Write = 1;
1803	PteDst.n.u1Execute = 1;
1804	PteDst.n.u1IgnorePAT = 1;
1805	PteDst.n.u3EMT = VMX_EPT_MEMTYPE_WB;
1806	/* PteDst.n.u1Size = 0 */
1807	#else
1808	SHW_PTE_SET(PteDst, fGstShwPteFlags \| PGM_PAGE_GET_HCPHYS(pPage));
1809	#endif
1810	}
1811
1812	/*
1813	* Make sure only allocated pages are mapped writable.
1814	*/
1815	if ( SHW_PTE_IS_P_RW(PteDst)
1816	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
1817	{
1818	/* Still applies to shared pages. */
1819	Assert(!PGM_PAGE_IS_ZERO(pPage));
1820	SHW_PTE_SET_RO(PteDst); /** @todo this isn't quite working yet. Why, isn't it? */
1821	Log3(("SyncPageWorker: write-protecting %RGp pPage=%R[pgmpage]at iPTDst=%d\n", GCPhysPage, pPage, iPTDst));
1822	}
1823	}
1824
1825	/*
1826	* Keep user track up to date.
1827	*/
1828	if (SHW_PTE_IS_P(PteDst))
1829	{
1830	if (!SHW_PTE_IS_P(*pPteDst))
1831	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1832	else if (SHW_PTE_GET_HCPHYS(*pPteDst) != SHW_PTE_GET_HCPHYS(PteDst))
1833	{
1834	Log2(("SyncPageWorker: deref! pPteDst=%RX64 PteDst=%RX64\n", SHW_PTE_LOG64(pPteDst), SHW_PTE_LOG64(PteDst)));
1835	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPteDst), iPTDst, GCPhysOldPage);
1836	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1837	}
1838	}
1839	else if (SHW_PTE_IS_P(*pPteDst))
1840	{
1841	Log2(("SyncPageWorker: deref! pPteDst=%RX64\n", SHW_PTE_LOG64(pPteDst)));
1842	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPteDst), iPTDst, GCPhysOldPage);
1843	}
1844
1845	/*
1846	* Update statistics and commit the entry.
1847	*/
1848	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1849	if (!PteSrc.n.u1Global)
1850	pShwPage->fSeenNonGlobal = true;
1851	#endif
1852	SHW_PTE_ATOMIC_SET2(*pPteDst, PteDst);
1853	return;
1854	}
1855
1856	/** @todo count these three different kinds. */
1857	Log2(("SyncPageWorker: invalid address in Pte\n"));
1858	}
1859	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1860	else if (!PteSrc.n.u1Present)
1861	Log2(("SyncPageWorker: page not present in Pte\n"));
1862	else
1863	Log2(("SyncPageWorker: invalid Pte\n"));
1864	#endif
1865
1866	/*
1867	* The page is not present or the PTE is bad. Replace the shadow PTE by
1868	* an empty entry, making sure to keep the user tracking up to date.
1869	*/
1870	if (SHW_PTE_IS_P(*pPteDst))
1871	{
1872	Log2(("SyncPageWorker: deref! pPteDst=%RX64\n", SHW_PTE_LOG64(pPteDst)));
1873	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPteDst), iPTDst, GCPhysOldPage);
1874	}
1875	SHW_PTE_ATOMIC_SET(*pPteDst, 0);
1876	}
1877
1878
1879	/**
1880	* Syncs a guest OS page.
1881	*
1882	* There are no conflicts at this point, neither is there any need for
1883	* page table allocations.
1884	*
1885	* When called in PAE or AMD64 guest mode, the guest PDPE shall be valid.
1886	* When called in AMD64 guest mode, the guest PML4E shall be valid.
1887	*
1888	* @returns VBox status code.
1889	* @returns VINF_PGM_SYNCPAGE_MODIFIED_PDE if it modifies the PDE in any way.
1890	* @param pVCpu The cross context virtual CPU structure.
1891	* @param PdeSrc Page directory entry of the guest.
1892	* @param GCPtrPage Guest context page address.
1893	* @param cPages Number of pages to sync (PGM_SYNC_N_PAGES) (default=1).
1894	* @param uErr Fault error (X86_TRAP_PF_*).
1895	*/
1896	static int PGM_BTH_NAME(SyncPage)(PVMCPU pVCpu, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr)
1897	{
1898	PVM pVM = pVCpu->CTX_SUFF(pVM);
1899	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool); NOREF(pPool);
1900	LogFlow(("SyncPage: GCPtrPage=%RGv cPages=%u uErr=%#x\n", GCPtrPage, cPages, uErr));
1901	RT_NOREF_PV(uErr); RT_NOREF_PV(cPages); RT_NOREF_PV(GCPtrPage);
1902
1903	PGM_LOCK_ASSERT_OWNER(pVM);
1904
1905	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
1906	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
1907	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
1908	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
1909	&& PGM_SHW_TYPE != PGM_TYPE_EPT
1910
1911	/*
1912	* Assert preconditions.
1913	*/
1914	Assert(PdeSrc.n.u1Present);
1915	Assert(cPages);
1916	# if 0 /* rarely useful; leave for debugging. */
1917	STAM_COUNTER_INC(&pVCpu->pgm.s.StatSyncPagePD[(GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK]);
1918	# endif
1919
1920	/*
1921	* Get the shadow PDE, find the shadow page table in the pool.
1922	*/
1923	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1924	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1925	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
1926
1927	/* Fetch the pgm pool shadow descriptor. */
1928	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
1929	Assert(pShwPde);
1930
1931	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1932	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1933	PPGMPOOLPAGE pShwPde = NULL;
1934	PX86PDPAE pPDDst;
1935
1936	/* Fetch the pgm pool shadow descriptor. */
1937	int rc2 = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
1938	AssertRCSuccessReturn(rc2, rc2);
1939	Assert(pShwPde);
1940
1941	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
1942	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1943
1944	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1945	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1946	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1947	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
1948	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
1949
1950	int rc2 = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
1951	AssertRCSuccessReturn(rc2, rc2);
1952	Assert(pPDDst && pPdptDst);
1953	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1954	# endif
1955	SHWPDE PdeDst = *pPdeDst;
1956
1957	/*
1958	* - In the guest SMP case we could have blocked while another VCPU reused
1959	* this page table.
1960	* - With W7-64 we may also take this path when the A bit is cleared on
1961	* higher level tables (PDPE/PML4E). The guest does not invalidate the
1962	* relevant TLB entries. If we're write monitoring any page mapped by
1963	* the modified entry, we may end up here with a "stale" TLB entry.
1964	*/
1965	if (!PdeDst.n.u1Present)
1966	{
1967	Log(("CPU%u: SyncPage: Pde at %RGv changed behind our back? (pPdeDst=%p/%RX64) uErr=%#x\n", pVCpu->idCpu, GCPtrPage, pPdeDst, (uint64_t)PdeDst.u, (uint32_t)uErr));
1968	AssertMsg(pVM->cCpus > 1 \|\| (uErr & (X86_TRAP_PF_P \| X86_TRAP_PF_RW)) == (X86_TRAP_PF_P \| X86_TRAP_PF_RW),
1969	("Unexpected missing PDE p=%p/%RX64 uErr=%#x\n", pPdeDst, (uint64_t)PdeDst.u, (uint32_t)uErr));
1970	if (uErr & X86_TRAP_PF_P)
1971	PGM_INVL_PG(pVCpu, GCPtrPage);
1972	return VINF_SUCCESS; /* force the instruction to be executed again. */
1973	}
1974
1975	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1976	Assert(pShwPage);
1977
1978	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1979	/* Fetch the pgm pool shadow descriptor. */
1980	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
1981	Assert(pShwPde);
1982	# endif
1983
1984	/*
1985	* Check that the page is present and that the shadow PDE isn't out of sync.
1986	*/
1987	const bool fBigPage = PdeSrc.b.u1Size && GST_IS_PSE_ACTIVE(pVCpu);
1988	const bool fPdeValid = !fBigPage ? GST_IS_PDE_VALID(pVCpu, PdeSrc) : GST_IS_BIG_PDE_VALID(pVCpu, PdeSrc);
1989	RTGCPHYS GCPhys;
1990	if (!fBigPage)
1991	{
1992	GCPhys = GST_GET_PDE_GCPHYS(PdeSrc);
1993	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1994	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1995	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| ((iPDDst & 1) * (PAGE_SIZE / 2)));
1996	# endif
1997	}
1998	else
1999	{
2000	GCPhys = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
2001	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2002	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
2003	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| (GCPtrPage & (1 << X86_PD_PAE_SHIFT)));
2004	# endif
2005	}
2006	/** @todo This doesn't check the G bit of 2/4MB pages. FIXME */
2007	if ( fPdeValid
2008	&& pShwPage->GCPhys == GCPhys
2009	&& PdeSrc.n.u1Present
2010	&& PdeSrc.n.u1User == PdeDst.n.u1User
2011	&& (PdeSrc.n.u1Write == PdeDst.n.u1Write \|\| !PdeDst.n.u1Write)
2012	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2013	&& (PdeSrc.n.u1NoExecute == PdeDst.n.u1NoExecute \|\| !GST_IS_NX_ACTIVE(pVCpu))
2014	# endif
2015	)
2016	{
2017	/*
2018	* Check that the PDE is marked accessed already.
2019	* Since we set the accessed bit before getting here on a #PF, this
2020	* check is only meant for dealing with non-#PF'ing paths.
2021	*/
2022	if (PdeSrc.n.u1Accessed)
2023	{
2024	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2025	if (!fBigPage)
2026	{
2027	/*
2028	* 4KB Page - Map the guest page table.
2029	*/
2030	PGSTPT pPTSrc;
2031	int rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GST_GET_PDE_GCPHYS(PdeSrc), &pPTSrc);
2032	if (RT_SUCCESS(rc))
2033	{
2034	# ifdef PGM_SYNC_N_PAGES
2035	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
2036	if ( cPages > 1
2037	&& !(uErr & X86_TRAP_PF_P)
2038	&& !VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY))
2039	{
2040	/*
2041	* This code path is currently only taken when the caller is PGMTrap0eHandler
2042	* for non-present pages!
2043	*
2044	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
2045	* deal with locality.
2046	*/
2047	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2048	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2049	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2050	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
2051	# else
2052	const unsigned offPTSrc = 0;
2053	# endif
2054	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2055	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
2056	iPTDst = 0;
2057	else
2058	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2059
2060	for (; iPTDst < iPTDstEnd; iPTDst++)
2061	{
2062	const PGSTPTE pPteSrc = &pPTSrc->a[offPTSrc + iPTDst];
2063
2064	if ( pPteSrc->n.u1Present
2065	&& !SHW_PTE_IS_P(pPTDst->a[iPTDst]))
2066	{
2067	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(GST_PT_MASK << GST_PT_SHIFT)) \| ((offPTSrc + iPTDst) << PAGE_SHIFT);
2068	NOREF(GCPtrCurPage);
2069	# ifdef VBOX_WITH_RAW_MODE_NOT_R0
2070	/*
2071	* Assuming kernel code will be marked as supervisor - and not as user level
2072	* and executed using a conforming code selector - And marked as readonly.
2073	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
2074	*/
2075	PPGMPAGE pPage;
2076	if ( ((PdeSrc.u & pPteSrc->u) & (X86_PTE_RW \| X86_PTE_US))
2077	\|\| iPTDst == ((GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK) /* always sync GCPtrPage */
2078	\|\| !CSAMDoesPageNeedScanning(pVM, GCPtrCurPage)
2079	\|\| ( (pPage = pgmPhysGetPage(pVM, pPteSrc->u & GST_PTE_PG_MASK))
2080	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2081	)
2082	# endif /* else: CSAM not active */
2083	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, *pPteSrc, pShwPage, iPTDst);
2084	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
2085	GCPtrCurPage, pPteSrc->n.u1Present,
2086	pPteSrc->n.u1Write & PdeSrc.n.u1Write,
2087	pPteSrc->n.u1User & PdeSrc.n.u1User,
2088	(uint64_t)pPteSrc->u,
2089	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2090	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2091	}
2092	}
2093	}
2094	else
2095	# endif /* PGM_SYNC_N_PAGES */
2096	{
2097	const unsigned iPTSrc = (GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK;
2098	GSTPTE PteSrc = pPTSrc->a[iPTSrc];
2099	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2100	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2101	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx %s\n",
2102	GCPtrPage, PteSrc.n.u1Present,
2103	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2104	PteSrc.n.u1User & PdeSrc.n.u1User,
2105	(uint64_t)PteSrc.u,
2106	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2107	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2108	}
2109	}
2110	else /* MMIO or invalid page: emulated in #PF handler. */
2111	{
2112	LogFlow(("PGM_GCPHYS_2_PTR %RGp failed with %Rrc\n", GCPhys, rc));
2113	Assert(!SHW_PTE_IS_P(pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK]));
2114	}
2115	}
2116	else
2117	{
2118	/*
2119	* 4/2MB page - lazy syncing shadow 4K pages.
2120	* (There are many causes of getting here, it's no longer only CSAM.)
2121	*/
2122	/* Calculate the GC physical address of this 4KB shadow page. */
2123	GCPhys = PGM_A20_APPLY(pVCpu, GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc) \| (GCPtrPage & GST_BIG_PAGE_OFFSET_MASK));
2124	/* Find ram range. */
2125	PPGMPAGE pPage;
2126	int rc = pgmPhysGetPageEx(pVM, GCPhys, &pPage);
2127	if (RT_SUCCESS(rc))
2128	{
2129	AssertFatalMsg(!PGM_PAGE_IS_BALLOONED(pPage), ("Unexpected ballooned page at %RGp\n", GCPhys));
2130
2131	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
2132	/* Try to make the page writable if necessary. */
2133	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
2134	&& ( PGM_PAGE_IS_ZERO(pPage)
2135	\|\| ( PdeSrc.n.u1Write
2136	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
2137	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
2138	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
2139	# endif
2140	# ifdef VBOX_WITH_PAGE_SHARING
2141	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
2142	# endif
2143	)
2144	)
2145	)
2146	{
2147	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
2148	AssertRC(rc);
2149	}
2150	# endif
2151
2152	/*
2153	* Make shadow PTE entry.
2154	*/
2155	SHWPTE PteDst;
2156	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2157	PGM_BTH_NAME(SyncHandlerPte)(pVM, pPage, GST_GET_BIG_PDE_SHW_FLAGS_4_PTE(pVCpu, PdeSrc), &PteDst);
2158	else
2159	SHW_PTE_SET(PteDst, GST_GET_BIG_PDE_SHW_FLAGS_4_PTE(pVCpu, PdeSrc) \| PGM_PAGE_GET_HCPHYS(pPage));
2160
2161	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2162	if ( SHW_PTE_IS_P(PteDst)
2163	&& !SHW_PTE_IS_P(pPTDst->a[iPTDst]))
2164	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
2165
2166	/* Make sure only allocated pages are mapped writable. */
2167	if ( SHW_PTE_IS_P_RW(PteDst)
2168	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
2169	{
2170	/* Still applies to shared pages. */
2171	Assert(!PGM_PAGE_IS_ZERO(pPage));
2172	SHW_PTE_SET_RO(PteDst); /** @todo this isn't quite working yet... */
2173	Log3(("SyncPage: write-protecting %RGp pPage=%R[pgmpage] at %RGv\n", GCPhys, pPage, GCPtrPage));
2174	}
2175
2176	SHW_PTE_ATOMIC_SET2(pPTDst->a[iPTDst], PteDst);
2177
2178	/*
2179	* If the page is not flagged as dirty and is writable, then make it read-only
2180	* at PD level, so we can set the dirty bit when the page is modified.
2181	*
2182	* ASSUMES that page access handlers are implemented on page table entry level.
2183	* Thus we will first catch the dirty access and set PDE.D and restart. If
2184	* there is an access handler, we'll trap again and let it work on the problem.
2185	*/
2186	/** @todo r=bird: figure out why we need this here, SyncPT should've taken care of this already.
2187	* As for invlpg, it simply frees the whole shadow PT.
2188	* ...It's possibly because the guest clears it and the guest doesn't really tell us... */
2189	if ( !PdeSrc.b.u1Dirty
2190	&& PdeSrc.b.u1Write)
2191	{
2192	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageBig));
2193	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2194	PdeDst.n.u1Write = 0;
2195	}
2196	else
2197	{
2198	PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
2199	PdeDst.n.u1Write = PdeSrc.n.u1Write;
2200	}
2201	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2202	Log2(("SyncPage: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} GCPhys=%RGp%s\n",
2203	GCPtrPage, PdeSrc.n.u1Present, PdeSrc.n.u1Write, PdeSrc.n.u1User, (uint64_t)PdeSrc.u, GCPhys,
2204	PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2205	}
2206	else
2207	{
2208	LogFlow(("PGM_GCPHYS_2_PTR %RGp (big) failed with %Rrc\n", GCPhys, rc));
2209	/** @todo must wipe the shadow page table entry in this
2210	* case. */
2211	}
2212	}
2213	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2214	return VINF_SUCCESS;
2215	}
2216
2217	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPagePDNAs));
2218	}
2219	else if (fPdeValid)
2220	{
2221	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPagePDOutOfSync));
2222	Log2(("SyncPage: Out-Of-Sync PDE at %RGp PdeSrc=%RX64 PdeDst=%RX64 (GCPhys %RGp vs %RGp)\n",
2223	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, GCPhys));
2224	}
2225	else
2226	{
2227	/// @todo STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPagePDOutOfSyncAndInvalid));
2228	Log2(("SyncPage: Bad PDE at %RGp PdeSrc=%RX64 PdeDst=%RX64 (GCPhys %RGp vs %RGp)\n",
2229	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, GCPhys));
2230	}
2231
2232	/*
2233	* Mark the PDE not present. Restart the instruction and let #PF call SyncPT.
2234	* Yea, I'm lazy.
2235	*/
2236	pgmPoolFreeByPage(pPool, pShwPage, pShwPde->idx, iPDDst);
2237	ASMAtomicWriteSize(pPdeDst, 0);
2238
2239	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2240	PGM_INVL_VCPU_TLBS(pVCpu);
2241	return VINF_PGM_SYNCPAGE_MODIFIED_PDE;
2242
2243
2244	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2245	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2246	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2247	&& !defined(IN_RC)
2248	NOREF(PdeSrc);
2249
2250	# ifdef PGM_SYNC_N_PAGES
2251	/*
2252	* Get the shadow PDE, find the shadow page table in the pool.
2253	*/
2254	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2255	X86PDE PdeDst = pgmShwGet32BitPDE(pVCpu, GCPtrPage);
2256
2257	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2258	X86PDEPAE PdeDst = pgmShwGetPaePDE(pVCpu, GCPtrPage);
2259
2260	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2261	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2262	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64; NOREF(iPdpt);
2263	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
2264	X86PDEPAE PdeDst;
2265	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
2266
2267	int rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2268	AssertRCSuccessReturn(rc, rc);
2269	Assert(pPDDst && pPdptDst);
2270	PdeDst = pPDDst->a[iPDDst];
2271	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
2272	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2273	PEPTPD pPDDst;
2274	EPTPDE PdeDst;
2275
2276	int rc = pgmShwGetEPTPDPtr(pVCpu, GCPtrPage, NULL, &pPDDst);
2277	if (rc != VINF_SUCCESS)
2278	{
2279	AssertRC(rc);
2280	return rc;
2281	}
2282	Assert(pPDDst);
2283	PdeDst = pPDDst->a[iPDDst];
2284	# endif
2285	/* In the guest SMP case we could have blocked while another VCPU reused this page table. */
2286	if (!PdeDst.n.u1Present)
2287	{
2288	AssertMsg(pVM->cCpus > 1, ("Unexpected missing PDE %RX64\n", (uint64_t)PdeDst.u));
2289	Log(("CPU%d: SyncPage: Pde at %RGv changed behind our back!\n", pVCpu->idCpu, GCPtrPage));
2290	return VINF_SUCCESS; /* force the instruction to be executed again. */
2291	}
2292
2293	/* Can happen in the guest SMP case; other VCPU activated this PDE while we were blocking to handle the page fault. */
2294	if (PdeDst.n.u1Size)
2295	{
2296	Assert(pVM->pgm.s.fNestedPaging);
2297	Log(("CPU%d: SyncPage: Pde (big:%RX64) at %RGv changed behind our back!\n", pVCpu->idCpu, PdeDst.u, GCPtrPage));
2298	return VINF_SUCCESS;
2299	}
2300
2301	/* Mask away the page offset. */
2302	GCPtrPage &= ~((RTGCPTR)0xfff);
2303
2304	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
2305	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2306
2307	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
2308	if ( cPages > 1
2309	&& !(uErr & X86_TRAP_PF_P)
2310	&& !VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY))
2311	{
2312	/*
2313	* This code path is currently only taken when the caller is PGMTrap0eHandler
2314	* for non-present pages!
2315	*
2316	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
2317	* deal with locality.
2318	*/
2319	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2320	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2321	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
2322	iPTDst = 0;
2323	else
2324	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2325	for (; iPTDst < iPTDstEnd; iPTDst++)
2326	{
2327	if (!SHW_PTE_IS_P(pPTDst->a[iPTDst]))
2328	{
2329	RTGCPTR GCPtrCurPage = PGM_A20_APPLY(pVCpu, (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT))
2330	\| (iPTDst << PAGE_SHIFT));
2331
2332	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], GCPtrCurPage, pShwPage, iPTDst);
2333	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=1 RW=1 U=1} PteDst=%08llx%s\n",
2334	GCPtrCurPage,
2335	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2336	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2337
2338	if (RT_UNLIKELY(VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY)))
2339	break;
2340	}
2341	else
2342	Log4(("%RGv iPTDst=%x pPTDst->a[iPTDst] %RX64\n", (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT), iPTDst, SHW_PTE_LOG64(pPTDst->a[iPTDst]) ));
2343	}
2344	}
2345	else
2346	# endif /* PGM_SYNC_N_PAGES */
2347	{
2348	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2349	RTGCPTR GCPtrCurPage = PGM_A20_APPLY(pVCpu, (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT))
2350	\| (iPTDst << PAGE_SHIFT));
2351
2352	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], GCPtrCurPage, pShwPage, iPTDst);
2353
2354	Log2(("SyncPage: 4K %RGv PteSrc:{P=1 RW=1 U=1}PteDst=%08llx%s\n",
2355	GCPtrPage,
2356	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2357	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2358	}
2359	return VINF_SUCCESS;
2360
2361	#else
2362	NOREF(PdeSrc);
2363	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
2364	return VERR_PGM_NOT_USED_IN_MODE;
2365	#endif
2366	}
2367
2368
2369	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
2370
2371	/**
2372	* CheckPageFault helper for returning a page fault indicating a non-present
2373	* (NP) entry in the page translation structures.
2374	*
2375	* @returns VINF_EM_RAW_GUEST_TRAP.
2376	* @param pVCpu The cross context virtual CPU structure.
2377	* @param uErr The error code of the shadow fault. Corrections to
2378	* TRPM's copy will be made if necessary.
2379	* @param GCPtrPage For logging.
2380	* @param uPageFaultLevel For logging.
2381	*/
2382	DECLINLINE(int) PGM_BTH_NAME(CheckPageFaultReturnNP)(PVMCPU pVCpu, uint32_t uErr, RTGCPTR GCPtrPage, unsigned uPageFaultLevel)
2383	{
2384	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyTrackRealPF));
2385	AssertMsg(!(uErr & X86_TRAP_PF_P), ("%#x\n", uErr));
2386	AssertMsg(!(uErr & X86_TRAP_PF_RSVD), ("%#x\n", uErr));
2387	if (uErr & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P))
2388	TRPMSetErrorCode(pVCpu, uErr & ~(X86_TRAP_PF_RSVD \| X86_TRAP_PF_P));
2389
2390	Log(("CheckPageFault: real page fault (notp) at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2391	RT_NOREF_PV(GCPtrPage); RT_NOREF_PV(uPageFaultLevel);
2392	return VINF_EM_RAW_GUEST_TRAP;
2393	}
2394
2395
2396	/**
2397	* CheckPageFault helper for returning a page fault indicating a reserved bit
2398	* (RSVD) error in the page translation structures.
2399	*
2400	* @returns VINF_EM_RAW_GUEST_TRAP.
2401	* @param pVCpu The cross context virtual CPU structure.
2402	* @param uErr The error code of the shadow fault. Corrections to
2403	* TRPM's copy will be made if necessary.
2404	* @param GCPtrPage For logging.
2405	* @param uPageFaultLevel For logging.
2406	*/
2407	DECLINLINE(int) PGM_BTH_NAME(CheckPageFaultReturnRSVD)(PVMCPU pVCpu, uint32_t uErr, RTGCPTR GCPtrPage, unsigned uPageFaultLevel)
2408	{
2409	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyTrackRealPF));
2410	if ((uErr & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) != (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P))
2411	TRPMSetErrorCode(pVCpu, uErr \| X86_TRAP_PF_RSVD \| X86_TRAP_PF_P);
2412
2413	Log(("CheckPageFault: real page fault (rsvd) at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2414	RT_NOREF_PV(GCPtrPage); RT_NOREF_PV(uPageFaultLevel);
2415	return VINF_EM_RAW_GUEST_TRAP;
2416	}
2417
2418
2419	/**
2420	* CheckPageFault helper for returning a page protection fault (P).
2421	*
2422	* @returns VINF_EM_RAW_GUEST_TRAP.
2423	* @param pVCpu The cross context virtual CPU structure.
2424	* @param uErr The error code of the shadow fault. Corrections to
2425	* TRPM's copy will be made if necessary.
2426	* @param GCPtrPage For logging.
2427	* @param uPageFaultLevel For logging.
2428	*/
2429	DECLINLINE(int) PGM_BTH_NAME(CheckPageFaultReturnProt)(PVMCPU pVCpu, uint32_t uErr, RTGCPTR GCPtrPage, unsigned uPageFaultLevel)
2430	{
2431	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyTrackRealPF));
2432	AssertMsg(uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US \| X86_TRAP_PF_ID), ("%#x\n", uErr));
2433	if ((uErr & (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD)) != X86_TRAP_PF_P)
2434	TRPMSetErrorCode(pVCpu, (uErr & ~X86_TRAP_PF_RSVD) \| X86_TRAP_PF_P);
2435
2436	Log(("CheckPageFault: real page fault (prot) at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2437	RT_NOREF_PV(GCPtrPage); RT_NOREF_PV(uPageFaultLevel);
2438	return VINF_EM_RAW_GUEST_TRAP;
2439	}
2440
2441
2442	/**
2443	* Handle dirty bit tracking faults.
2444	*
2445	* @returns VBox status code.
2446	* @param pVCpu The cross context virtual CPU structure.
2447	* @param uErr Page fault error code.
2448	* @param pPdeSrc Guest page directory entry.
2449	* @param pPdeDst Shadow page directory entry.
2450	* @param GCPtrPage Guest context page address.
2451	*/
2452	static int PGM_BTH_NAME(CheckDirtyPageFault)(PVMCPU pVCpu, uint32_t uErr, PSHWPDE pPdeDst, GSTPDE const *pPdeSrc,
2453	RTGCPTR GCPtrPage)
2454	{
2455	PVM pVM = pVCpu->CTX_SUFF(pVM);
2456	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2457	NOREF(uErr);
2458
2459	PGM_LOCK_ASSERT_OWNER(pVM);
2460
2461	/*
2462	* Handle big page.
2463	*/
2464	if (pPdeSrc->b.u1Size && GST_IS_PSE_ACTIVE(pVCpu))
2465	{
2466	if ( pPdeDst->n.u1Present
2467	&& (pPdeDst->u & PGM_PDFLAGS_TRACK_DIRTY))
2468	{
2469	SHWPDE PdeDst = *pPdeDst;
2470
2471	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageTrap));
2472	Assert(pPdeSrc->b.u1Write);
2473
2474	/* Note: No need to invalidate this entry on other VCPUs as a stale TLB entry will not harm; write access will simply
2475	* fault again and take this path to only invalidate the entry (see below).
2476	*/
2477	PdeDst.n.u1Write = 1;
2478	PdeDst.n.u1Accessed = 1;
2479	PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
2480	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2481	PGM_INVL_BIG_PG(pVCpu, GCPtrPage);
2482	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2483	}
2484
2485	# ifdef IN_RING0
2486	/* Check for stale TLB entry; only applies to the SMP guest case. */
2487	if ( pVM->cCpus > 1
2488	&& pPdeDst->n.u1Write
2489	&& pPdeDst->n.u1Accessed)
2490	{
2491	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPdeDst->u & SHW_PDE_PG_MASK);
2492	if (pShwPage)
2493	{
2494	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2495	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2496	if (SHW_PTE_IS_P_RW(*pPteDst))
2497	{
2498	/* Stale TLB entry. */
2499	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageStale));
2500	PGM_INVL_PG(pVCpu, GCPtrPage);
2501	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2502	}
2503	}
2504	}
2505	# endif /* IN_RING0 */
2506	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2507	}
2508
2509	/*
2510	* Map the guest page table.
2511	*/
2512	PGSTPT pPTSrc;
2513	int rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GST_GET_PDE_GCPHYS(*pPdeSrc), &pPTSrc);
2514	if (RT_FAILURE(rc))
2515	{
2516	AssertRC(rc);
2517	return rc;
2518	}
2519
2520	if (pPdeDst->n.u1Present)
2521	{
2522	GSTPTE const *pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
2523	const GSTPTE PteSrc = *pPteSrc;
2524
2525	#ifdef VBOX_WITH_RAW_MODE_NOT_R0
2526	/* Bail out here as pgmPoolGetPage will return NULL and we'll crash below.
2527	* Our individual shadow handlers will provide more information and force a fatal exit.
2528	*/
2529	if ( !HMIsEnabled(pVM)
2530	&& MMHyperIsInsideArea(pVM, (RTGCPTR)GCPtrPage))
2531	{
2532	LogRel(("CheckPageFault: write to hypervisor region %RGv\n", GCPtrPage));
2533	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2534	}
2535	#endif
2536	/*
2537	* Map shadow page table.
2538	*/
2539	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPdeDst->u & SHW_PDE_PG_MASK);
2540	if (pShwPage)
2541	{
2542	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2543	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2544	if (SHW_PTE_IS_P(pPteDst)) /* @todo Optimize accessed bit emulation? */
2545	{
2546	if (SHW_PTE_IS_TRACK_DIRTY(*pPteDst))
2547	{
2548	PPGMPAGE pPage = pgmPhysGetPage(pVM, GST_GET_PTE_GCPHYS(PteSrc));
2549	SHWPTE PteDst = *pPteDst;
2550
2551	LogFlow(("DIRTY page trap addr=%RGv\n", GCPtrPage));
2552	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageTrap));
2553
2554	Assert(PteSrc.n.u1Write);
2555
2556	/* Note: No need to invalidate this entry on other VCPUs as a stale TLB
2557	* entry will not harm; write access will simply fault again and
2558	* take this path to only invalidate the entry.
2559	*/
2560	if (RT_LIKELY(pPage))
2561	{
2562	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2563	{
2564	//AssertMsgFailed(("%R[pgmpage] - we don't set PGM_PTFLAGS_TRACK_DIRTY for these pages\n", pPage));
2565	Assert(!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage));
2566	/* Assuming write handlers here as the PTE is present (otherwise we wouldn't be here). */
2567	SHW_PTE_SET_RO(PteDst);
2568	}
2569	else
2570	{
2571	if ( PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED
2572	&& PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
2573	{
2574	rc = pgmPhysPageMakeWritable(pVM, pPage, GST_GET_PTE_GCPHYS(PteSrc));
2575	AssertRC(rc);
2576	}
2577	if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED)
2578	SHW_PTE_SET_RW(PteDst);
2579	else
2580	{
2581	/* Still applies to shared pages. */
2582	Assert(!PGM_PAGE_IS_ZERO(pPage));
2583	SHW_PTE_SET_RO(PteDst);
2584	}
2585	}
2586	}
2587	else
2588	SHW_PTE_SET_RW(PteDst); /** @todo r=bird: This doesn't make sense to me. */
2589
2590	SHW_PTE_SET(PteDst, (SHW_PTE_GET_U(PteDst) \| X86_PTE_D \| X86_PTE_A) & ~(uint64_t)PGM_PTFLAGS_TRACK_DIRTY);
2591	SHW_PTE_ATOMIC_SET2(*pPteDst, PteDst);
2592	PGM_INVL_PG(pVCpu, GCPtrPage);
2593	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2594	}
2595
2596	# ifdef IN_RING0
2597	/* Check for stale TLB entry; only applies to the SMP guest case. */
2598	if ( pVM->cCpus > 1
2599	&& SHW_PTE_IS_RW(*pPteDst)
2600	&& SHW_PTE_IS_A(*pPteDst))
2601	{
2602	/* Stale TLB entry. */
2603	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageStale));
2604	PGM_INVL_PG(pVCpu, GCPtrPage);
2605	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2606	}
2607	# endif
2608	}
2609	}
2610	else
2611	AssertMsgFailed(("pgmPoolGetPageByHCPhys %RGp failed!\n", pPdeDst->u & SHW_PDE_PG_MASK));
2612	}
2613
2614	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2615	}
2616
2617	#endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
2618
2619
2620	/**
2621	* Sync a shadow page table.
2622	*
2623	* The shadow page table is not present in the shadow PDE.
2624	*
2625	* Handles mapping conflicts.
2626	*
2627	* This is called by VerifyAccessSyncPage, PrefetchPage, InvalidatePage (on
2628	* conflict), and Trap0eHandler.
2629	*
2630	* A precondition for this method is that the shadow PDE is not present. The
2631	* caller must take the PGM lock before checking this and continue to hold it
2632	* when calling this method.
2633	*
2634	* @returns VBox status code.
2635	* @param pVCpu The cross context virtual CPU structure.
2636	* @param iPDSrc Page directory index.
2637	* @param pPDSrc Source page directory (i.e. Guest OS page directory).
2638	* Assume this is a temporary mapping.
2639	* @param GCPtrPage GC Pointer of the page that caused the fault
2640	*/
2641	static int PGM_BTH_NAME(SyncPT)(PVMCPU pVCpu, unsigned iPDSrc, PGSTPD pPDSrc, RTGCPTR GCPtrPage)
2642	{
2643	PVM pVM = pVCpu->CTX_SUFF(pVM);
2644	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool); NOREF(pPool);
2645
2646	#if 0 /* rarely useful; leave for debugging. */
2647	STAM_COUNTER_INC(&pVCpu->pgm.s.StatSyncPtPD[iPDSrc]);
2648	#endif
2649	LogFlow(("SyncPT: GCPtrPage=%RGv\n", GCPtrPage)); RT_NOREF_PV(GCPtrPage);
2650
2651	PGM_LOCK_ASSERT_OWNER(pVM);
2652
2653	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
2654	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
2655	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
2656	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2657	&& PGM_SHW_TYPE != PGM_TYPE_EPT
2658
2659	int rc = VINF_SUCCESS;
2660
2661	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
2662
2663	/*
2664	* Some input validation first.
2665	*/
2666	AssertMsg(iPDSrc == ((GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK), ("iPDSrc=%x GCPtrPage=%RGv\n", iPDSrc, GCPtrPage));
2667
2668	/*
2669	* Get the relevant shadow PDE entry.
2670	*/
2671	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2672	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
2673	PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
2674
2675	/* Fetch the pgm pool shadow descriptor. */
2676	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
2677	Assert(pShwPde);
2678
2679	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2680	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2681	PPGMPOOLPAGE pShwPde = NULL;
2682	PX86PDPAE pPDDst;
2683	PSHWPDE pPdeDst;
2684
2685	/* Fetch the pgm pool shadow descriptor. */
2686	rc = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
2687	AssertRCSuccessReturn(rc, rc);
2688	Assert(pShwPde);
2689
2690	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
2691	pPdeDst = &pPDDst->a[iPDDst];
2692
2693	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2694	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
2695	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2696	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
2697	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
2698	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2699	AssertRCSuccessReturn(rc, rc);
2700	Assert(pPDDst);
2701	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2702	# endif
2703	SHWPDE PdeDst = *pPdeDst;
2704
2705	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2706	/* Fetch the pgm pool shadow descriptor. */
2707	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
2708	Assert(pShwPde);
2709	# endif
2710
2711	# ifndef PGM_WITHOUT_MAPPINGS
2712	/*
2713	* Check for conflicts.
2714	* RC: In case of a conflict we'll go to Ring-3 and do a full SyncCR3.
2715	* R3: Simply resolve the conflict.
2716	*/
2717	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
2718	{
2719	Assert(pgmMapAreMappingsEnabled(pVM));
2720	# ifndef IN_RING3
2721	Log(("SyncPT: Conflict at %RGv\n", GCPtrPage));
2722	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
2723	return VERR_ADDRESS_CONFLICT;
2724
2725	# else /* IN_RING3 */
2726	PPGMMAPPING pMapping = pgmGetMapping(pVM, (RTGCPTR)GCPtrPage);
2727	Assert(pMapping);
2728	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2729	rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2730	# elif PGM_GST_TYPE == PGM_TYPE_PAE
2731	rc = pgmR3SyncPTResolveConflictPAE(pVM, pMapping, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2732	# else
2733	AssertFailed(); NOREF(pMapping); /* can't happen for amd64 */
2734	# endif
2735	if (RT_FAILURE(rc))
2736	{
2737	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
2738	return rc;
2739	}
2740	PdeDst = *pPdeDst;
2741	# endif /* IN_RING3 */
2742	}
2743	# endif /* !PGM_WITHOUT_MAPPINGS */
2744	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
2745
2746	/*
2747	* Sync the page directory entry.
2748	*/
2749	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
2750	const bool fPageTable = !PdeSrc.b.u1Size \|\| !GST_IS_PSE_ACTIVE(pVCpu);
2751	if ( PdeSrc.n.u1Present
2752	&& (fPageTable ? GST_IS_PDE_VALID(pVCpu, PdeSrc) : GST_IS_BIG_PDE_VALID(pVCpu, PdeSrc)) )
2753	{
2754	/*
2755	* Allocate & map the page table.
2756	*/
2757	PSHWPT pPTDst;
2758	PPGMPOOLPAGE pShwPage;
2759	RTGCPHYS GCPhys;
2760	if (fPageTable)
2761	{
2762	GCPhys = GST_GET_PDE_GCPHYS(PdeSrc);
2763	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2764	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2765	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| ((iPDDst & 1) * (PAGE_SIZE / 2)));
2766	# endif
2767	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
2768	pShwPde->idx, iPDDst, false /fLockPage/,
2769	&pShwPage);
2770	}
2771	else
2772	{
2773	PGMPOOLACCESS enmAccess;
2774	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2775	const bool fNoExecute = PdeSrc.n.u1NoExecute && GST_IS_NX_ACTIVE(pVCpu);
2776	# else
2777	const bool fNoExecute = false;
2778	# endif
2779
2780	GCPhys = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
2781	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2782	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
2783	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| (GCPtrPage & (1 << X86_PD_PAE_SHIFT)));
2784	# endif
2785	/* Determine the right kind of large page to avoid incorrect cached entry reuse. */
2786	if (PdeSrc.n.u1User)
2787	{
2788	if (PdeSrc.n.u1Write)
2789	enmAccess = (fNoExecute) ? PGMPOOLACCESS_USER_RW_NX : PGMPOOLACCESS_USER_RW;
2790	else
2791	enmAccess = (fNoExecute) ? PGMPOOLACCESS_USER_R_NX : PGMPOOLACCESS_USER_R;
2792	}
2793	else
2794	{
2795	if (PdeSrc.n.u1Write)
2796	enmAccess = (fNoExecute) ? PGMPOOLACCESS_SUPERVISOR_RW_NX : PGMPOOLACCESS_SUPERVISOR_RW;
2797	else
2798	enmAccess = (fNoExecute) ? PGMPOOLACCESS_SUPERVISOR_R_NX : PGMPOOLACCESS_SUPERVISOR_R;
2799	}
2800	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_BIG, enmAccess, PGM_A20_IS_ENABLED(pVCpu),
2801	pShwPde->idx, iPDDst, false /fLockPage/,
2802	&pShwPage);
2803	}
2804	if (rc == VINF_SUCCESS)
2805	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2806	else if (rc == VINF_PGM_CACHED_PAGE)
2807	{
2808	/*
2809	* The PT was cached, just hook it up.
2810	*/
2811	if (fPageTable)
2812	PdeDst.u = pShwPage->Core.Key \| GST_GET_PDE_SHW_FLAGS(pVCpu, PdeSrc);
2813	else
2814	{
2815	PdeDst.u = pShwPage->Core.Key \| GST_GET_BIG_PDE_SHW_FLAGS(pVCpu, PdeSrc);
2816	/* (see explanation and assumptions further down.) */
2817	if ( !PdeSrc.b.u1Dirty
2818	&& PdeSrc.b.u1Write)
2819	{
2820	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageBig));
2821	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2822	PdeDst.b.u1Write = 0;
2823	}
2824	}
2825	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2826	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2827	return VINF_SUCCESS;
2828	}
2829	else if (rc == VERR_PGM_POOL_FLUSHED)
2830	{
2831	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2832	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2833	return VINF_PGM_SYNC_CR3;
2834	}
2835	else
2836	AssertMsgFailedReturn(("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
2837	/** @todo Why do we bother preserving X86_PDE_AVL_MASK here?
2838	* Both PGM_PDFLAGS_MAPPING and PGM_PDFLAGS_TRACK_DIRTY should be
2839	* irrelevant at this point. */
2840	PdeDst.u &= X86_PDE_AVL_MASK;
2841	PdeDst.u \|= pShwPage->Core.Key;
2842
2843	/*
2844	* Page directory has been accessed (this is a fault situation, remember).
2845	*/
2846	/** @todo
2847	* Well, when the caller is PrefetchPage or InvalidatePage is isn't a
2848	* fault situation. What's more, the Trap0eHandler has already set the
2849	* accessed bit. So, it's actually just VerifyAccessSyncPage which
2850	* might need setting the accessed flag.
2851	*
2852	* The best idea is to leave this change to the caller and add an
2853	* assertion that it's set already. */
2854	pPDSrc->a[iPDSrc].n.u1Accessed = 1;
2855	if (fPageTable)
2856	{
2857	/*
2858	* Page table - 4KB.
2859	*
2860	* Sync all or just a few entries depending on PGM_SYNC_N_PAGES.
2861	*/
2862	Log2(("SyncPT: 4K %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx}\n",
2863	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u));
2864	PGSTPT pPTSrc;
2865	rc = PGM_GCPHYS_2_PTR(pVM, GST_GET_PDE_GCPHYS(PdeSrc), &pPTSrc);
2866	if (RT_SUCCESS(rc))
2867	{
2868	/*
2869	* Start by syncing the page directory entry so CSAM's TLB trick works.
2870	*/
2871	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| X86_PDE_AVL_MASK))
2872	\| GST_GET_PDE_SHW_FLAGS(pVCpu, PdeSrc);
2873	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2874	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2875
2876	/*
2877	* Directory/page user or supervisor privilege: (same goes for read/write)
2878	*
2879	* Directory Page Combined
2880	* U/S U/S U/S
2881	* 0 0 0
2882	* 0 1 0
2883	* 1 0 0
2884	* 1 1 1
2885	*
2886	* Simple AND operation. Table listed for completeness.
2887	*
2888	*/
2889	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT4K));
2890	# ifdef PGM_SYNC_N_PAGES
2891	unsigned iPTBase = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2892	unsigned iPTDst = iPTBase;
2893	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2894	if (iPTDst <= PGM_SYNC_NR_PAGES / 2)
2895	iPTDst = 0;
2896	else
2897	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2898	# else /* !PGM_SYNC_N_PAGES */
2899	unsigned iPTDst = 0;
2900	const unsigned iPTDstEnd = RT_ELEMENTS(pPTDst->a);
2901	# endif /* !PGM_SYNC_N_PAGES */
2902	RTGCPTR GCPtrCur = (GCPtrPage & ~(RTGCPTR)((1 << SHW_PD_SHIFT) - 1))
2903	\| ((RTGCPTR)iPTDst << PAGE_SHIFT);
2904	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2905	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2906	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
2907	# else
2908	const unsigned offPTSrc = 0;
2909	# endif
2910	for (; iPTDst < iPTDstEnd; iPTDst++, GCPtrCur += PAGE_SIZE)
2911	{
2912	const unsigned iPTSrc = iPTDst + offPTSrc;
2913	const GSTPTE PteSrc = pPTSrc->a[iPTSrc];
2914
2915	if (PteSrc.n.u1Present)
2916	{
2917	# ifdef VBOX_WITH_RAW_MODE_NOT_R0
2918	/*
2919	* Assuming kernel code will be marked as supervisor - and not as user level
2920	* and executed using a conforming code selector - And marked as readonly.
2921	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
2922	*/
2923	PPGMPAGE pPage;
2924	if ( ((PdeSrc.u & pPTSrc->a[iPTSrc].u) & (X86_PTE_RW \| X86_PTE_US))
2925	\|\| !CSAMDoesPageNeedScanning(pVM, GCPtrCur)
2926	\|\| ( (pPage = pgmPhysGetPage(pVM, GST_GET_PTE_GCPHYS(PteSrc)))
2927	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2928	)
2929	# endif
2930	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2931	Log2(("SyncPT: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s dst.raw=%08llx iPTSrc=%x PdeSrc.u=%x physpte=%RGp\n",
2932	GCPtrCur,
2933	PteSrc.n.u1Present,
2934	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2935	PteSrc.n.u1User & PdeSrc.n.u1User,
2936	(uint64_t)PteSrc.u,
2937	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : "", SHW_PTE_LOG64(pPTDst->a[iPTDst]), iPTSrc, PdeSrc.au32[0],
2938	(RTGCPHYS)(GST_GET_PDE_GCPHYS(PdeSrc) + iPTSrc*sizeof(PteSrc)) ));
2939	}
2940	/* else: the page table was cleared by the pool */
2941	} /* for PTEs */
2942	}
2943	}
2944	else
2945	{
2946	/*
2947	* Big page - 2/4MB.
2948	*
2949	* We'll walk the ram range list in parallel and optimize lookups.
2950	* We will only sync one shadow page table at a time.
2951	*/
2952	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT4M));
2953
2954	/**
2955	* @todo It might be more efficient to sync only a part of the 4MB
2956	* page (similar to what we do for 4KB PDs).
2957	*/
2958
2959	/*
2960	* Start by syncing the page directory entry.
2961	*/
2962	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| (X86_PDE_AVL_MASK & ~PGM_PDFLAGS_TRACK_DIRTY)))
2963	\| GST_GET_BIG_PDE_SHW_FLAGS(pVCpu, PdeSrc);
2964
2965	/*
2966	* If the page is not flagged as dirty and is writable, then make it read-only
2967	* at PD level, so we can set the dirty bit when the page is modified.
2968	*
2969	* ASSUMES that page access handlers are implemented on page table entry level.
2970	* Thus we will first catch the dirty access and set PDE.D and restart. If
2971	* there is an access handler, we'll trap again and let it work on the problem.
2972	*/
2973	/** @todo move the above stuff to a section in the PGM documentation. */
2974	Assert(!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY));
2975	if ( !PdeSrc.b.u1Dirty
2976	&& PdeSrc.b.u1Write)
2977	{
2978	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageBig));
2979	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2980	PdeDst.b.u1Write = 0;
2981	}
2982	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2983	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2984
2985	/*
2986	* Fill the shadow page table.
2987	*/
2988	/* Get address and flags from the source PDE. */
2989	SHWPTE PteDstBase;
2990	SHW_PTE_SET(PteDstBase, GST_GET_BIG_PDE_SHW_FLAGS_4_PTE(pVCpu, PdeSrc));
2991
2992	/* Loop thru the entries in the shadow PT. */
2993	const RTGCPTR GCPtr = (GCPtrPage >> SHW_PD_SHIFT) << SHW_PD_SHIFT; NOREF(GCPtr);
2994	Log2(("SyncPT: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} Shw=%RGv GCPhys=%RGp %s\n",
2995	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u, GCPtr,
2996	GCPhys, PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2997	PPGMRAMRANGE pRam = pgmPhysGetRangeAtOrAbove(pVM, GCPhys);
2998	unsigned iPTDst = 0;
2999	while ( iPTDst < RT_ELEMENTS(pPTDst->a)
3000	&& !VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY))
3001	{
3002	if (pRam && GCPhys >= pRam->GCPhys)
3003	{
3004	# ifndef PGM_WITH_A20
3005	unsigned iHCPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
3006	# endif
3007	do
3008	{
3009	/* Make shadow PTE. */
3010	# ifdef PGM_WITH_A20
3011	PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
3012	# else
3013	PPGMPAGE pPage = &pRam->aPages[iHCPage];
3014	# endif
3015	SHWPTE PteDst;
3016
3017	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
3018	/* Try to make the page writable if necessary. */
3019	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
3020	&& ( PGM_PAGE_IS_ZERO(pPage)
3021	\|\| ( SHW_PTE_IS_RW(PteDstBase)
3022	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
3023	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
3024	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
3025	# endif
3026	# ifdef VBOX_WITH_PAGE_SHARING
3027	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
3028	# endif
3029	&& !PGM_PAGE_IS_BALLOONED(pPage))
3030	)
3031	)
3032	{
3033	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
3034	AssertRCReturn(rc, rc);
3035	if (VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY))
3036	break;
3037	}
3038	# endif
3039
3040	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
3041	PGM_BTH_NAME(SyncHandlerPte)(pVM, pPage, SHW_PTE_GET_U(PteDstBase), &PteDst);
3042	else if (PGM_PAGE_IS_BALLOONED(pPage))
3043	SHW_PTE_SET(PteDst, 0); /* Handle ballooned pages at #PF time. */
3044	# ifdef VBOX_WITH_RAW_MODE_NOT_R0
3045	/*
3046	* Assuming kernel code will be marked as supervisor and not as user level and executed
3047	* using a conforming code selector. Don't check for readonly, as that implies the whole
3048	* 4MB can be code or readonly data. Linux enables write access for its large pages.
3049	*/
3050	else if ( !PdeSrc.n.u1User
3051	&& CSAMDoesPageNeedScanning(pVM, GCPtr \| (iPTDst << SHW_PT_SHIFT)))
3052	SHW_PTE_SET(PteDst, 0);
3053	# endif
3054	else
3055	SHW_PTE_SET(PteDst, PGM_PAGE_GET_HCPHYS(pPage) \| SHW_PTE_GET_U(PteDstBase));
3056
3057	/* Only map writable pages writable. */
3058	if ( SHW_PTE_IS_P_RW(PteDst)
3059	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
3060	{
3061	/* Still applies to shared pages. */
3062	Assert(!PGM_PAGE_IS_ZERO(pPage));
3063	SHW_PTE_SET_RO(PteDst); /** @todo this isn't quite working yet... */
3064	Log3(("SyncPT: write-protecting %RGp pPage=%R[pgmpage] at %RGv\n", GCPhys, pPage, (RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT))));
3065	}
3066
3067	if (SHW_PTE_IS_P(PteDst))
3068	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
3069
3070	/* commit it (not atomic, new table) */
3071	pPTDst->a[iPTDst] = PteDst;
3072	Log4(("SyncPT: BIG %RGv PteDst:{P=%d RW=%d U=%d raw=%08llx}%s\n",
3073	(RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT)), SHW_PTE_IS_P(PteDst), SHW_PTE_IS_RW(PteDst), SHW_PTE_IS_US(PteDst), SHW_PTE_LOG64(PteDst),
3074	SHW_PTE_IS_TRACK_DIRTY(PteDst) ? " Track-Dirty" : ""));
3075
3076	/* advance */
3077	GCPhys += PAGE_SIZE;
3078	PGM_A20_APPLY_TO_VAR(pVCpu, GCPhys);
3079	# ifndef PGM_WITH_A20
3080	iHCPage++;
3081	# endif
3082	iPTDst++;
3083	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
3084	&& GCPhys <= pRam->GCPhysLast);
3085
3086	/* Advance ram range list. */
3087	while (pRam && GCPhys > pRam->GCPhysLast)
3088	pRam = pRam->CTX_SUFF(pNext);
3089	}
3090	else if (pRam)
3091	{
3092	Log(("Invalid pages at %RGp\n", GCPhys));
3093	do
3094	{
3095	SHW_PTE_SET(pPTDst->a[iPTDst], 0); /* Invalid page, we must handle them manually. */
3096	GCPhys += PAGE_SIZE;
3097	iPTDst++;
3098	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
3099	&& GCPhys < pRam->GCPhys);
3100	PGM_A20_APPLY_TO_VAR(pVCpu,GCPhys);
3101	}
3102	else
3103	{
3104	Log(("Invalid pages at %RGp (2)\n", GCPhys));
3105	for ( ; iPTDst < RT_ELEMENTS(pPTDst->a); iPTDst++)
3106	SHW_PTE_SET(pPTDst->a[iPTDst], 0); /* Invalid page, we must handle them manually. */
3107	}
3108	} /* while more PTEs */
3109	} /* 4KB / 4MB */
3110	}
3111	else
3112	AssertRelease(!PdeDst.n.u1Present);
3113
3114	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3115	if (RT_FAILURE(rc))
3116	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPTFailed));
3117	return rc;
3118
3119	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
3120	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
3121	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
3122	&& !defined(IN_RC)
3123	NOREF(iPDSrc); NOREF(pPDSrc);
3124
3125	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3126
3127	/*
3128	* Validate input a little bit.
3129	*/
3130	int rc = VINF_SUCCESS;
3131	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3132	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
3133	PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
3134
3135	/* Fetch the pgm pool shadow descriptor. */
3136	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
3137	Assert(pShwPde);
3138
3139	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3140	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
3141	PPGMPOOLPAGE pShwPde = NULL; /* initialized to shut up gcc */
3142	PX86PDPAE pPDDst;
3143	PSHWPDE pPdeDst;
3144
3145	/* Fetch the pgm pool shadow descriptor. */
3146	rc = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
3147	AssertRCSuccessReturn(rc, rc);
3148	Assert(pShwPde);
3149
3150	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
3151	pPdeDst = &pPDDst->a[iPDDst];
3152
3153	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3154	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3155	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
3156	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
3157	PX86PDPT pPdptDst= NULL; /* initialized to shut up gcc */
3158	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
3159	AssertRCSuccessReturn(rc, rc);
3160	Assert(pPDDst);
3161	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
3162
3163	/* Fetch the pgm pool shadow descriptor. */
3164	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
3165	Assert(pShwPde);
3166
3167	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
3168	const unsigned iPdpt = (GCPtrPage >> EPT_PDPT_SHIFT) & EPT_PDPT_MASK;
3169	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3170	PEPTPD pPDDst;
3171	PEPTPDPT pPdptDst;
3172
3173	rc = pgmShwGetEPTPDPtr(pVCpu, GCPtrPage, &pPdptDst, &pPDDst);
3174	if (rc != VINF_SUCCESS)
3175	{
3176	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3177	AssertRC(rc);
3178	return rc;
3179	}
3180	Assert(pPDDst);
3181	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
3182
3183	/* Fetch the pgm pool shadow descriptor. */
3184	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & EPT_PDPTE_PG_MASK);
3185	Assert(pShwPde);
3186	# endif
3187	SHWPDE PdeDst = *pPdeDst;
3188
3189	Assert(!(PdeDst.u & PGM_PDFLAGS_MAPPING));
3190	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
3191
3192	# if defined(PGM_WITH_LARGE_PAGES) && PGM_SHW_TYPE != PGM_TYPE_32BIT && PGM_SHW_TYPE != PGM_TYPE_PAE
3193	if (BTH_IS_NP_ACTIVE(pVM))
3194	{
3195	/* Check if we allocated a big page before for this 2 MB range. */
3196	PPGMPAGE pPage;
3197	rc = pgmPhysGetPageEx(pVM, PGM_A20_APPLY(pVCpu, GCPtrPage & X86_PDE2M_PAE_PG_MASK), &pPage);
3198	if (RT_SUCCESS(rc))
3199	{
3200	RTHCPHYS HCPhys = NIL_RTHCPHYS;
3201	if (PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE)
3202	{
3203	if (PGM_A20_IS_ENABLED(pVCpu))
3204	{
3205	STAM_REL_COUNTER_INC(&pVM->pgm.s.StatLargePageReused);
3206	AssertRelease(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
3207	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3208	}
3209	else
3210	{
3211	PGM_PAGE_SET_PDE_TYPE(pVM, pPage, PGM_PAGE_PDE_TYPE_PDE_DISABLED);
3212	pVM->pgm.s.cLargePagesDisabled++;
3213	}
3214	}
3215	else if ( PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE_DISABLED
3216	&& PGM_A20_IS_ENABLED(pVCpu))
3217	{
3218	/* Recheck the entire 2 MB range to see if we can use it again as a large page. */
3219	rc = pgmPhysRecheckLargePage(pVM, GCPtrPage, pPage);
3220	if (RT_SUCCESS(rc))
3221	{
3222	Assert(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
3223	Assert(PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE);
3224	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3225	}
3226	}
3227	else if ( PGMIsUsingLargePages(pVM)
3228	&& PGM_A20_IS_ENABLED(pVCpu))
3229	{
3230	rc = pgmPhysAllocLargePage(pVM, GCPtrPage);
3231	if (RT_SUCCESS(rc))
3232	{
3233	Assert(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
3234	Assert(PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE);
3235	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3236	}
3237	else
3238	LogFlow(("pgmPhysAllocLargePage failed with %Rrc\n", rc));
3239	}
3240
3241	if (HCPhys != NIL_RTHCPHYS)
3242	{
3243	PdeDst.u &= X86_PDE_AVL_MASK;
3244	PdeDst.u \|= HCPhys;
3245	PdeDst.n.u1Present = 1;
3246	PdeDst.n.u1Write = 1;
3247	PdeDst.b.u1Size = 1;
3248	# if PGM_SHW_TYPE == PGM_TYPE_EPT
3249	PdeDst.n.u1Execute = 1;
3250	PdeDst.b.u1IgnorePAT = 1;
3251	PdeDst.b.u3EMT = VMX_EPT_MEMTYPE_WB;
3252	# else
3253	PdeDst.n.u1User = 1;
3254	# endif
3255	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
3256
3257	Log(("SyncPT: Use large page at %RGp PDE=%RX64\n", GCPtrPage, PdeDst.u));
3258	/* Add a reference to the first page only. */
3259	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPde, PGM_PAGE_GET_TRACKING(pPage), pPage, iPDDst);
3260
3261	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3262	return VINF_SUCCESS;
3263	}
3264	}
3265	}
3266	# endif /* HC_ARCH_BITS == 64 */
3267
3268	/*
3269	* Allocate & map the page table.
3270	*/
3271	PSHWPT pPTDst;
3272	PPGMPOOLPAGE pShwPage;
3273	RTGCPHYS GCPhys;
3274
3275	/* Virtual address = physical address */
3276	GCPhys = PGM_A20_APPLY(pVCpu, GCPtrPage & X86_PAGE_4K_BASE_MASK);
3277	rc = pgmPoolAlloc(pVM, GCPhys & ~(RT_BIT_64(SHW_PD_SHIFT) - 1), BTH_PGMPOOLKIND_PT_FOR_PT, PGMPOOLACCESS_DONTCARE,
3278	PGM_A20_IS_ENABLED(pVCpu), pShwPde->idx, iPDDst, false /fLockPage/,
3279	&pShwPage);
3280	if ( rc == VINF_SUCCESS
3281	\|\| rc == VINF_PGM_CACHED_PAGE)
3282	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
3283	else
3284	{
3285	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3286	AssertMsgFailedReturn(("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
3287	}
3288
3289	if (rc == VINF_SUCCESS)
3290	{
3291	/* New page table; fully set it up. */
3292	Assert(pPTDst);
3293
3294	/* Mask away the page offset. */
3295	GCPtrPage &= ~(RTGCPTR)PAGE_OFFSET_MASK;
3296
3297	for (unsigned iPTDst = 0; iPTDst < RT_ELEMENTS(pPTDst->a); iPTDst++)
3298	{
3299	RTGCPTR GCPtrCurPage = PGM_A20_APPLY(pVCpu, (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT))
3300	\| (iPTDst << PAGE_SHIFT));
3301
3302	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], GCPtrCurPage, pShwPage, iPTDst);
3303	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=1 RW=1 U=1} PteDst=%08llx%s\n",
3304	GCPtrCurPage,
3305	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
3306	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
3307
3308	if (RT_UNLIKELY(VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY)))
3309	break;
3310	}
3311	}
3312	else
3313	rc = VINF_SUCCESS; /* Cached entry; assume it's still fully valid. */
3314
3315	/* Save the new PDE. */
3316	PdeDst.u &= X86_PDE_AVL_MASK;
3317	PdeDst.u \|= pShwPage->Core.Key;
3318	PdeDst.n.u1Present = 1;
3319	PdeDst.n.u1Write = 1;
3320	# if PGM_SHW_TYPE == PGM_TYPE_EPT
3321	PdeDst.n.u1Execute = 1;
3322	# else
3323	PdeDst.n.u1User = 1;
3324	PdeDst.n.u1Accessed = 1;
3325	# endif
3326	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
3327
3328	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3329	if (RT_FAILURE(rc))
3330	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPTFailed));
3331	return rc;
3332
3333	#else
3334	NOREF(iPDSrc); NOREF(pPDSrc);
3335	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_SHW_TYPE, PGM_GST_TYPE));
3336	return VERR_PGM_NOT_USED_IN_MODE;
3337	#endif
3338	}
3339
3340
3341
3342	/**
3343	* Prefetch a page/set of pages.
3344	*
3345	* Typically used to sync commonly used pages before entering raw mode
3346	* after a CR3 reload.
3347	*
3348	* @returns VBox status code.
3349	* @param pVCpu The cross context virtual CPU structure.
3350	* @param GCPtrPage Page to invalidate.
3351	*/
3352	PGM_BTH_DECL(int, PrefetchPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage)
3353	{
3354	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
3355	\|\| PGM_GST_TYPE == PGM_TYPE_REAL \
3356	\|\| PGM_GST_TYPE == PGM_TYPE_PROT \
3357	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3358	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64 ) \
3359	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
3360	&& PGM_SHW_TYPE != PGM_TYPE_EPT
3361
3362	/*
3363	* Check that all Guest levels thru the PDE are present, getting the
3364	* PD and PDE in the processes.
3365	*/
3366	int rc = VINF_SUCCESS;
3367	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3368	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3369	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
3370	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
3371	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3372	unsigned iPDSrc;
3373	X86PDPE PdpeSrc;
3374	PGSTPD pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtrPage, &iPDSrc, &PdpeSrc);
3375	if (!pPDSrc)
3376	return VINF_SUCCESS; /* not present */
3377	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
3378	unsigned iPDSrc;
3379	PX86PML4E pPml4eSrc;
3380	X86PDPE PdpeSrc;
3381	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3382	if (!pPDSrc)
3383	return VINF_SUCCESS; /* not present */
3384	# endif
3385	const GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
3386	# else
3387	PGSTPD pPDSrc = NULL;
3388	const unsigned iPDSrc = 0;
3389	GSTPDE PdeSrc;
3390
3391	PdeSrc.u = 0; /* faked so we don't have to #ifdef everything */
3392	PdeSrc.n.u1Present = 1;
3393	PdeSrc.n.u1Write = 1;
3394	PdeSrc.n.u1Accessed = 1;
3395	PdeSrc.n.u1User = 1;
3396	# endif
3397
3398	if (PdeSrc.n.u1Present && PdeSrc.n.u1Accessed)
3399	{
3400	PVM pVM = pVCpu->CTX_SUFF(pVM);
3401	pgmLock(pVM);
3402
3403	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3404	const X86PDE PdeDst = pgmShwGet32BitPDE(pVCpu, GCPtrPage);
3405	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3406	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3407	PX86PDPAE pPDDst;
3408	X86PDEPAE PdeDst;
3409	# if PGM_GST_TYPE != PGM_TYPE_PAE
3410	X86PDPE PdpeSrc;
3411
3412	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
3413	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
3414	# endif
3415	rc = pgmShwSyncPaePDPtr(pVCpu, GCPtrPage, PdpeSrc.u, &pPDDst);
3416	if (rc != VINF_SUCCESS)
3417	{
3418	pgmUnlock(pVM);
3419	AssertRC(rc);
3420	return rc;
3421	}
3422	Assert(pPDDst);
3423	PdeDst = pPDDst->a[iPDDst];
3424
3425	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3426	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3427	PX86PDPAE pPDDst;
3428	X86PDEPAE PdeDst;
3429
3430	# if PGM_GST_TYPE == PGM_TYPE_PROT
3431	/* AMD-V nested paging */
3432	X86PML4E Pml4eSrc;
3433	X86PDPE PdpeSrc;
3434	PX86PML4E pPml4eSrc = &Pml4eSrc;
3435
3436	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
3437	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A;
3438	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A;
3439	# endif
3440
3441	rc = pgmShwSyncLongModePDPtr(pVCpu, GCPtrPage, pPml4eSrc->u, PdpeSrc.u, &pPDDst);
3442	if (rc != VINF_SUCCESS)
3443	{
3444	pgmUnlock(pVM);
3445	AssertRC(rc);
3446	return rc;
3447	}
3448	Assert(pPDDst);
3449	PdeDst = pPDDst->a[iPDDst];
3450	# endif
3451	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
3452	{
3453	if (!PdeDst.n.u1Present)
3454	{
3455	/** @todo r=bird: This guy will set the A bit on the PDE,
3456	* probably harmless. */
3457	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
3458	}
3459	else
3460	{
3461	/* Note! We used to sync PGM_SYNC_NR_PAGES pages, which triggered assertions in CSAM, because
3462	* R/W attributes of nearby pages were reset. Not sure how that could happen. Anyway, it
3463	* makes no sense to prefetch more than one page.
3464	*/
3465	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
3466	if (RT_SUCCESS(rc))
3467	rc = VINF_SUCCESS;
3468	}
3469	}
3470	pgmUnlock(pVM);
3471	}
3472	return rc;
3473
3474	#elif PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3475	NOREF(pVCpu); NOREF(GCPtrPage);
3476	return VINF_SUCCESS; /* ignore */
3477	#else
3478	AssertCompile(0);
3479	#endif
3480	}
3481
3482
3483
3484
3485	/**
3486	* Syncs a page during a PGMVerifyAccess() call.
3487	*
3488	* @returns VBox status code (informational included).
3489	* @param pVCpu The cross context virtual CPU structure.
3490	* @param GCPtrPage The address of the page to sync.
3491	* @param fPage The effective guest page flags.
3492	* @param uErr The trap error code.
3493	* @remarks This will normally never be called on invalid guest page
3494	* translation entries.
3495	*/
3496	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fPage, unsigned uErr)
3497	{
3498	PVM pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
3499
3500	LogFlow(("VerifyAccessSyncPage: GCPtrPage=%RGv fPage=%#x uErr=%#x\n", GCPtrPage, fPage, uErr));
3501	RT_NOREF_PV(GCPtrPage); RT_NOREF_PV(fPage); RT_NOREF_PV(uErr);
3502
3503	Assert(!pVM->pgm.s.fNestedPaging);
3504	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
3505	\|\| PGM_GST_TYPE == PGM_TYPE_REAL \
3506	\|\| PGM_GST_TYPE == PGM_TYPE_PROT \
3507	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3508	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64 ) \
3509	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
3510	&& PGM_SHW_TYPE != PGM_TYPE_EPT
3511
3512	# ifdef VBOX_WITH_RAW_MODE_NOT_R0
3513	if (!(fPage & X86_PTE_US))
3514	{
3515	/*
3516	* Mark this page as safe.
3517	*/
3518	/** @todo not correct for pages that contain both code and data!! */
3519	Log(("CSAMMarkPage %RGv; scanned=%d\n", GCPtrPage, true));
3520	CSAMMarkPage(pVM, GCPtrPage, true);
3521	}
3522	# endif
3523
3524	/*
3525	* Get guest PD and index.
3526	*/
3527	/** @todo Performance: We've done all this a jiffy ago in the
3528	* PGMGstGetPage call. */
3529	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3530	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3531	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
3532	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
3533
3534	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3535	unsigned iPDSrc = 0;
3536	X86PDPE PdpeSrc;
3537	PGSTPD pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtrPage, &iPDSrc, &PdpeSrc);
3538	if (RT_UNLIKELY(!pPDSrc))
3539	{
3540	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
3541	return VINF_EM_RAW_GUEST_TRAP;
3542	}
3543
3544	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
3545	unsigned iPDSrc = 0; /* shut up gcc */
3546	PX86PML4E pPml4eSrc = NULL; /* ditto */
3547	X86PDPE PdpeSrc;
3548	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3549	if (RT_UNLIKELY(!pPDSrc))
3550	{
3551	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
3552	return VINF_EM_RAW_GUEST_TRAP;
3553	}
3554	# endif
3555
3556	# else /* !PGM_WITH_PAGING */
3557	PGSTPD pPDSrc = NULL;
3558	const unsigned iPDSrc = 0;
3559	# endif /* !PGM_WITH_PAGING */
3560	int rc = VINF_SUCCESS;
3561
3562	pgmLock(pVM);
3563
3564	/*
3565	* First check if the shadow pd is present.
3566	*/
3567	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3568	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
3569
3570	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3571	PX86PDEPAE pPdeDst;
3572	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3573	PX86PDPAE pPDDst;
3574	# if PGM_GST_TYPE != PGM_TYPE_PAE
3575	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
3576	X86PDPE PdpeSrc;
3577	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
3578	# endif
3579	rc = pgmShwSyncPaePDPtr(pVCpu, GCPtrPage, PdpeSrc.u, &pPDDst);
3580	if (rc != VINF_SUCCESS)
3581	{
3582	pgmUnlock(pVM);
3583	AssertRC(rc);
3584	return rc;
3585	}
3586	Assert(pPDDst);
3587	pPdeDst = &pPDDst->a[iPDDst];
3588
3589	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3590	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3591	PX86PDPAE pPDDst;
3592	PX86PDEPAE pPdeDst;
3593
3594	# if PGM_GST_TYPE == PGM_TYPE_PROT
3595	/* AMD-V nested paging: Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
3596	X86PML4E Pml4eSrc;
3597	X86PDPE PdpeSrc;
3598	PX86PML4E pPml4eSrc = &Pml4eSrc;
3599	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A;
3600	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A;
3601	# endif
3602
3603	rc = pgmShwSyncLongModePDPtr(pVCpu, GCPtrPage, pPml4eSrc->u, PdpeSrc.u, &pPDDst);
3604	if (rc != VINF_SUCCESS)
3605	{
3606	pgmUnlock(pVM);
3607	AssertRC(rc);
3608	return rc;
3609	}
3610	Assert(pPDDst);
3611	pPdeDst = &pPDDst->a[iPDDst];
3612	# endif
3613
3614	if (!pPdeDst->n.u1Present)
3615	{
3616	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
3617	if (rc != VINF_SUCCESS)
3618	{
3619	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
3620	pgmUnlock(pVM);
3621	AssertRC(rc);
3622	return rc;
3623	}
3624	}
3625
3626	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3627	/* Check for dirty bit fault */
3628	rc = PGM_BTH_NAME(CheckDirtyPageFault)(pVCpu, uErr, pPdeDst, &pPDSrc->a[iPDSrc], GCPtrPage);
3629	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
3630	Log(("PGMVerifyAccess: success (dirty)\n"));
3631	else
3632	# endif
3633	{
3634	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3635	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
3636	# else
3637	GSTPDE PdeSrc;
3638	PdeSrc.u = 0; /* faked so we don't have to #ifdef everything */
3639	PdeSrc.n.u1Present = 1;
3640	PdeSrc.n.u1Write = 1;
3641	PdeSrc.n.u1Accessed = 1;
3642	PdeSrc.n.u1User = 1;
3643	# endif
3644
3645	Assert(rc != VINF_EM_RAW_GUEST_TRAP);
3646	if (uErr & X86_TRAP_PF_US)
3647	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncUser));
3648	else /* supervisor */
3649	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
3650
3651	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
3652	if (RT_SUCCESS(rc))
3653	{
3654	/* Page was successfully synced */
3655	Log2(("PGMVerifyAccess: success (sync)\n"));
3656	rc = VINF_SUCCESS;
3657	}
3658	else
3659	{
3660	Log(("PGMVerifyAccess: access violation for %RGv rc=%Rrc\n", GCPtrPage, rc));
3661	rc = VINF_EM_RAW_GUEST_TRAP;
3662	}
3663	}
3664	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
3665	pgmUnlock(pVM);
3666	return rc;
3667
3668	#else /* PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED */
3669
3670	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
3671	return VERR_PGM_NOT_USED_IN_MODE;
3672	#endif /* PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED */
3673	}
3674
3675
3676	/**
3677	* Syncs the paging hierarchy starting at CR3.
3678	*
3679	* @returns VBox status code, R0/RC may return VINF_PGM_SYNC_CR3, no other
3680	* informational status codes.
3681	* @retval VERR_PGM_NO_HYPERVISOR_ADDRESS in raw-mode when we're unable to map
3682	* the VMM into guest context.
3683	* @param pVCpu The cross context virtual CPU structure.
3684	* @param cr0 Guest context CR0 register.
3685	* @param cr3 Guest context CR3 register. Not subjected to the A20
3686	* mask.
3687	* @param cr4 Guest context CR4 register.
3688	* @param fGlobal Including global page directories or not
3689	*/
3690	PGM_BTH_DECL(int, SyncCR3)(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
3691	{
3692	PVM pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
3693	NOREF(cr0); NOREF(cr3); NOREF(cr4); NOREF(fGlobal);
3694
3695	LogFlow(("SyncCR3 FF=%d fGlobal=%d\n", !!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3), fGlobal));
3696
3697	#if PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
3698
3699	pgmLock(pVM);
3700
3701	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
3702	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3703	if (pPool->cDirtyPages)
3704	pgmPoolResetDirtyPages(pVM);
3705	# endif
3706
3707	/*
3708	* Update page access handlers.
3709	* The virtual are always flushed, while the physical are only on demand.
3710	* WARNING: We are incorrectly not doing global flushing on Virtual Handler updates. We'll
3711	* have to look into that later because it will have a bad influence on the performance.
3712	* @note SvL: There's no need for that. Just invalidate the virtual range(s).
3713	* bird: Yes, but that won't work for aliases.
3714	*/
3715	/** @todo this MUST go away. See @bugref{1557}. */
3716	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3Handlers), h);
3717	PGM_GST_NAME(HandlerVirtualUpdate)(pVM, cr4);
3718	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3Handlers), h);
3719	pgmUnlock(pVM);
3720	#endif /* !NESTED && !EPT */
3721
3722	#if PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3723	/*
3724	* Nested / EPT - almost no work.
3725	*/
3726	Assert(!pgmMapAreMappingsEnabled(pVM));
3727	return VINF_SUCCESS;
3728
3729	#elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3730	/*
3731	* AMD64 (Shw & Gst) - No need to check all paging levels; we zero
3732	* out the shadow parts when the guest modifies its tables.
3733	*/
3734	Assert(!pgmMapAreMappingsEnabled(pVM));
3735	return VINF_SUCCESS;
3736
3737	#else /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
3738
3739	# ifndef PGM_WITHOUT_MAPPINGS
3740	/*
3741	* Check for and resolve conflicts with our guest mappings if they
3742	* are enabled and not fixed.
3743	*/
3744	if (pgmMapAreMappingsFloating(pVM))
3745	{
3746	int rc = pgmMapResolveConflicts(pVM);
3747	Assert(rc == VINF_SUCCESS \|\| rc == VINF_PGM_SYNC_CR3);
3748	if (rc == VINF_SUCCESS)
3749	{ /* likely */ }
3750	else if (rc == VINF_PGM_SYNC_CR3)
3751	{
3752	LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
3753	return VINF_PGM_SYNC_CR3;
3754	}
3755	else if (RT_FAILURE(rc))
3756	return rc;
3757	else
3758	AssertMsgFailed(("%Rrc\n", rc));
3759	}
3760	# else
3761	Assert(!pgmMapAreMappingsEnabled(pVM));
3762	# endif
3763	return VINF_SUCCESS;
3764	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
3765	}
3766
3767
3768
3769
3770	#ifdef VBOX_STRICT
3771	# ifdef IN_RC
3772	# undef AssertMsgFailed
3773	# define AssertMsgFailed Log
3774	# endif
3775
3776	/**
3777	* Checks that the shadow page table is in sync with the guest one.
3778	*
3779	* @returns The number of errors.
3780	* @param pVCpu The cross context virtual CPU structure.
3781	* @param cr3 Guest context CR3 register.
3782	* @param cr4 Guest context CR4 register.
3783	* @param GCPtr Where to start. Defaults to 0.
3784	* @param cb How much to check. Defaults to everything.
3785	*/
3786	PGM_BTH_DECL(unsigned, AssertCR3)(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb)
3787	{
3788	NOREF(pVCpu); NOREF(cr3); NOREF(cr4); NOREF(GCPtr); NOREF(cb);
3789	#if PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3790	return 0;
3791	#else
3792	unsigned cErrors = 0;
3793	PVM pVM = pVCpu->CTX_SUFF(pVM);
3794	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool); NOREF(pPool);
3795
3796	# if PGM_GST_TYPE == PGM_TYPE_PAE
3797	/** @todo currently broken; crashes below somewhere */
3798	AssertFailed();
3799	# endif
3800
3801	# if PGM_GST_TYPE == PGM_TYPE_32BIT \
3802	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3803	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
3804
3805	bool fBigPagesSupported = GST_IS_PSE_ACTIVE(pVCpu);
3806	PPGMCPU pPGM = &pVCpu->pgm.s;
3807	RTGCPHYS GCPhysGst; /* page address derived from the guest page tables. */
3808	RTHCPHYS HCPhysShw; /* page address derived from the shadow page tables. */
3809	# ifndef IN_RING0
3810	RTHCPHYS HCPhys; /* general usage. */
3811	# endif
3812	int rc;
3813
3814	/*
3815	* Check that the Guest CR3 and all its mappings are correct.
3816	*/
3817	AssertMsgReturn(pPGM->GCPhysCR3 == PGM_A20_APPLY(pVCpu, cr3 & GST_CR3_PAGE_MASK),
3818	("Invalid GCPhysCR3=%RGp cr3=%RGp\n", pPGM->GCPhysCR3, (RTGCPHYS)cr3),
3819	false);
3820	# if !defined(IN_RING0) && PGM_GST_TYPE != PGM_TYPE_AMD64
3821	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3822	rc = PGMShwGetPage(pVCpu, (RTRCUINTPTR)pPGM->pGst32BitPdRC, NULL, &HCPhysShw);
3823	# else
3824	rc = PGMShwGetPage(pVCpu, (RTRCUINTPTR)pPGM->pGstPaePdptRC, NULL, &HCPhysShw);
3825	# endif
3826	AssertRCReturn(rc, 1);
3827	HCPhys = NIL_RTHCPHYS;
3828	rc = pgmRamGCPhys2HCPhys(pVM, PGM_A20_APPLY(pVCpu, cr3 & GST_CR3_PAGE_MASK), &HCPhys);
3829	AssertMsgReturn(HCPhys == HCPhysShw, ("HCPhys=%RHp HCPhyswShw=%RHp (cr3)\n", HCPhys, HCPhysShw), false);
3830	# if PGM_GST_TYPE == PGM_TYPE_32BIT && defined(IN_RING3)
3831	pgmGstGet32bitPDPtr(pVCpu);
3832	RTGCPHYS GCPhys;
3833	rc = PGMR3DbgR3Ptr2GCPhys(pVM->pUVM, pPGM->pGst32BitPdR3, &GCPhys);
3834	AssertRCReturn(rc, 1);
3835	AssertMsgReturn(PGM_A20_APPLY(pVCpu, cr3 & GST_CR3_PAGE_MASK) == GCPhys, ("GCPhys=%RGp cr3=%RGp\n", GCPhys, (RTGCPHYS)cr3), false);
3836	# endif
3837	# endif /* !IN_RING0 */
3838
3839	/*
3840	* Get and check the Shadow CR3.
3841	*/
3842	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3843	unsigned cPDEs = X86_PG_ENTRIES;
3844	unsigned cIncrement = X86_PG_ENTRIES * PAGE_SIZE;
3845	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3846	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3847	unsigned cPDEs = X86_PG_PAE_ENTRIES * 4; /* treat it as a 2048 entry table. */
3848	# else
3849	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3850	# endif
3851	unsigned cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3852	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3853	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3854	unsigned cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3855	# endif
3856	if (cb != ~(RTGCPTR)0)
3857	cPDEs = RT_MIN(cb >> SHW_PD_SHIFT, 1);
3858
3859	/** @todo call the other two PGMAssert() functions. /
3860
3861	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3862	unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3863
3864	for (; iPml4 < X86_PG_PAE_ENTRIES; iPml4++)
3865	{
3866	PPGMPOOLPAGE pShwPdpt = NULL;
3867	PX86PML4E pPml4eSrc;
3868	PX86PML4E pPml4eDst;
3869	RTGCPHYS GCPhysPdptSrc;
3870
3871	pPml4eSrc = pgmGstGetLongModePML4EPtr(pVCpu, iPml4);
3872	pPml4eDst = pgmShwGetLongModePML4EPtr(pVCpu, iPml4);
3873
3874	/* Fetch the pgm pool shadow descriptor if the shadow pml4e is present. */
3875	if (!pPml4eDst->n.u1Present)
3876	{
3877	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3878	continue;
3879	}
3880
3881	pShwPdpt = pgmPoolGetPage(pPool, pPml4eDst->u & X86_PML4E_PG_MASK);
3882	GCPhysPdptSrc = PGM_A20_APPLY(pVCpu, pPml4eSrc->u & X86_PML4E_PG_MASK);
3883
3884	if (pPml4eSrc->n.u1Present != pPml4eDst->n.u1Present)
3885	{
3886	AssertMsgFailed(("Present bit doesn't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3887	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3888	cErrors++;
3889	continue;
3890	}
3891
3892	if (GCPhysPdptSrc != pShwPdpt->GCPhys)
3893	{
3894	AssertMsgFailed(("Physical address doesn't match! iPml4 %d pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, pPml4eDst->u, pPml4eSrc->u, pShwPdpt->GCPhys, GCPhysPdptSrc));
3895	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3896	cErrors++;
3897	continue;
3898	}
3899
3900	if ( pPml4eDst->n.u1User != pPml4eSrc->n.u1User
3901	\|\| pPml4eDst->n.u1Write != pPml4eSrc->n.u1Write
3902	\|\| pPml4eDst->n.u1NoExecute != pPml4eSrc->n.u1NoExecute)
3903	{
3904	AssertMsgFailed(("User/Write/NoExec bits don't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3905	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3906	cErrors++;
3907	continue;
3908	}
3909	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
3910	{
3911	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
3912
3913	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
3914	/*
3915	* Check the PDPTEs too.
3916	*/
3917	unsigned iPdpt = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
3918
3919	for (;iPdpt <= SHW_PDPT_MASK; iPdpt++)
3920	{
3921	unsigned iPDSrc = 0; /* initialized to shut up gcc */
3922	PPGMPOOLPAGE pShwPde = NULL;
3923	PX86PDPE pPdpeDst;
3924	RTGCPHYS GCPhysPdeSrc;
3925	X86PDPE PdpeSrc;
3926	PdpeSrc.u = 0; /* initialized to shut up gcc 4.5 */
3927	# if PGM_GST_TYPE == PGM_TYPE_PAE
3928	PGSTPD pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtr, &iPDSrc, &PdpeSrc);
3929	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(pVCpu);
3930	# else
3931	PX86PML4E pPml4eSrcIgn;
3932	PX86PDPT pPdptDst;
3933	PX86PDPAE pPDDst;
3934	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtr, &pPml4eSrcIgn, &PdpeSrc, &iPDSrc);
3935
3936	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtr, NULL, &pPdptDst, &pPDDst);
3937	if (rc != VINF_SUCCESS)
3938	{
3939	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
3940	GCPtr += 512 * _2M;
3941	continue; /* next PDPTE */
3942	}
3943	Assert(pPDDst);
3944	# endif
3945	Assert(iPDSrc == 0);
3946
3947	pPdpeDst = &pPdptDst->a[iPdpt];
3948
3949	if (!pPdpeDst->n.u1Present)
3950	{
3951	GCPtr += 512 * _2M;
3952	continue; /* next PDPTE */
3953	}
3954
3955	pShwPde = pgmPoolGetPage(pPool, pPdpeDst->u & X86_PDPE_PG_MASK);
3956	GCPhysPdeSrc = PGM_A20_APPLY(pVCpu, PdpeSrc.u & X86_PDPE_PG_MASK);
3957
3958	if (pPdpeDst->n.u1Present != PdpeSrc.n.u1Present)
3959	{
3960	AssertMsgFailed(("Present bit doesn't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3961	GCPtr += 512 * _2M;
3962	cErrors++;
3963	continue;
3964	}
3965
3966	if (GCPhysPdeSrc != pShwPde->GCPhys)
3967	{
3968	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3969	AssertMsgFailed(("Physical address doesn't match! iPml4 %d iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3970	# else
3971	AssertMsgFailed(("Physical address doesn't match! iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3972	# endif
3973	GCPtr += 512 * _2M;
3974	cErrors++;
3975	continue;
3976	}
3977
3978	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3979	if ( pPdpeDst->lm.u1User != PdpeSrc.lm.u1User
3980	\|\| pPdpeDst->lm.u1Write != PdpeSrc.lm.u1Write
3981	\|\| pPdpeDst->lm.u1NoExecute != PdpeSrc.lm.u1NoExecute)
3982	{
3983	AssertMsgFailed(("User/Write/NoExec bits don't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3984	GCPtr += 512 * _2M;
3985	cErrors++;
3986	continue;
3987	}
3988	# endif
3989
3990	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
3991	{
3992	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
3993	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3994	GSTPD const *pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
3995	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3996	PCX86PD pPDDst = pgmShwGet32BitPDPtr(pVCpu);
3997	# endif
3998	# endif /* PGM_GST_TYPE == PGM_TYPE_32BIT */
3999	/*
4000	* Iterate the shadow page directory.
4001	*/
4002	GCPtr = (GCPtr >> SHW_PD_SHIFT) << SHW_PD_SHIFT;
4003	unsigned iPDDst = (GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK;
4004
4005	for (;
4006	iPDDst < cPDEs;
4007	iPDDst++, GCPtr += cIncrement)
4008	{
4009	# if PGM_SHW_TYPE == PGM_TYPE_PAE
4010	const SHWPDE PdeDst = *pgmShwGetPaePDEPtr(pVCpu, GCPtr);
4011	# else
4012	const SHWPDE PdeDst = pPDDst->a[iPDDst];
4013	# endif
4014	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
4015	{
4016	Assert(pgmMapAreMappingsEnabled(pVM));
4017	if ((PdeDst.u & X86_PDE_AVL_MASK) != PGM_PDFLAGS_MAPPING)
4018	{
4019	AssertMsgFailed(("Mapping shall only have PGM_PDFLAGS_MAPPING set! PdeDst.u=%#RX64\n", (uint64_t)PdeDst.u));
4020	cErrors++;
4021	continue;
4022	}
4023	}
4024	else if ( (PdeDst.u & X86_PDE_P)
4025	\|\| ((PdeDst.u & (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY)) == (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY))
4026	)
4027	{
4028	HCPhysShw = PdeDst.u & SHW_PDE_PG_MASK;
4029	PPGMPOOLPAGE pPoolPage = pgmPoolGetPage(pPool, HCPhysShw);
4030	if (!pPoolPage)
4031	{
4032	AssertMsgFailed(("Invalid page table address %RHp at %RGv! PdeDst=%#RX64\n",
4033	HCPhysShw, GCPtr, (uint64_t)PdeDst.u));
4034	cErrors++;
4035	continue;
4036	}
4037	const SHWPT pPTDst = (const SHWPT )PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pPoolPage);
4038
4039	if (PdeDst.u & (X86_PDE4M_PWT \| X86_PDE4M_PCD))
4040	{
4041	AssertMsgFailed(("PDE flags PWT and/or PCD is set at %RGv! These flags are not virtualized! PdeDst=%#RX64\n",
4042	GCPtr, (uint64_t)PdeDst.u));
4043	cErrors++;
4044	}
4045
4046	if (PdeDst.u & (X86_PDE4M_G \| X86_PDE4M_D))
4047	{
4048	AssertMsgFailed(("4K PDE reserved flags at %RGv! PdeDst=%#RX64\n",
4049	GCPtr, (uint64_t)PdeDst.u));
4050	cErrors++;
4051	}
4052
4053	const GSTPDE PdeSrc = pPDSrc->a[(iPDDst >> (GST_PD_SHIFT - SHW_PD_SHIFT)) & GST_PD_MASK];
4054	if (!PdeSrc.n.u1Present)
4055	{
4056	AssertMsgFailed(("Guest PDE at %RGv is not present! PdeDst=%#RX64 PdeSrc=%#RX64\n",
4057	GCPtr, (uint64_t)PdeDst.u, (uint64_t)PdeSrc.u));
4058	cErrors++;
4059	continue;
4060	}
4061
4062	if ( !PdeSrc.b.u1Size
4063	\|\| !fBigPagesSupported)
4064	{
4065	GCPhysGst = GST_GET_PDE_GCPHYS(PdeSrc);
4066	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
4067	GCPhysGst = PGM_A20_APPLY(pVCpu, GCPhysGst \| ((iPDDst & 1) * (PAGE_SIZE / 2)));
4068	# endif
4069	}
4070	else
4071	{
4072	# if PGM_GST_TYPE == PGM_TYPE_32BIT
4073	if (PdeSrc.u & X86_PDE4M_PG_HIGH_MASK)
4074	{
4075	AssertMsgFailed(("Guest PDE at %RGv is using PSE36 or similar! PdeSrc=%#RX64\n",
4076	GCPtr, (uint64_t)PdeSrc.u));
4077	cErrors++;
4078	continue;
4079	}
4080	# endif
4081	GCPhysGst = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
4082	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
4083	GCPhysGst = PGM_A20_APPLY(pVCpu, GCPhysGst \| (GCPtr & RT_BIT(X86_PAGE_2M_SHIFT)));
4084	# endif
4085	}
4086
4087	if ( pPoolPage->enmKind
4088	!= (!PdeSrc.b.u1Size \|\| !fBigPagesSupported ? BTH_PGMPOOLKIND_PT_FOR_PT : BTH_PGMPOOLKIND_PT_FOR_BIG))
4089	{
4090	AssertMsgFailed(("Invalid shadow page table kind %d at %RGv! PdeSrc=%#RX64\n",
4091	pPoolPage->enmKind, GCPtr, (uint64_t)PdeSrc.u));
4092	cErrors++;
4093	}
4094
4095	PPGMPAGE pPhysPage = pgmPhysGetPage(pVM, GCPhysGst);
4096	if (!pPhysPage)
4097	{
4098	AssertMsgFailed(("Cannot find guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
4099	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
4100	cErrors++;
4101	continue;
4102	}
4103
4104	if (GCPhysGst != pPoolPage->GCPhys)
4105	{
4106	AssertMsgFailed(("GCPhysGst=%RGp != pPage->GCPhys=%RGp at %RGv\n",
4107	GCPhysGst, pPoolPage->GCPhys, GCPtr));
4108	cErrors++;
4109	continue;
4110	}
4111
4112	if ( !PdeSrc.b.u1Size
4113	\|\| !fBigPagesSupported)
4114	{
4115	/*
4116	* Page Table.
4117	*/
4118	const GSTPT *pPTSrc;
4119	rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, PGM_A20_APPLY(pVCpu, GCPhysGst & ~(RTGCPHYS)(PAGE_SIZE - 1)),
4120	&pPTSrc);
4121	if (RT_FAILURE(rc))
4122	{
4123	AssertMsgFailed(("Cannot map/convert guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
4124	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
4125	cErrors++;
4126	continue;
4127	}
4128	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/))
4129	!= (PdeDst.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/)))
4130	{
4131	/// @todo We get here a lot on out-of-sync CR3 entries. The access handler should zap them to avoid false alarms here!
4132	// (This problem will go away when/if we shadow multiple CR3s.)
4133	AssertMsgFailed(("4K PDE flags mismatch at %RGv! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4134	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4135	cErrors++;
4136	continue;
4137	}
4138	if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
4139	{
4140	AssertMsgFailed(("4K PDEs cannot have PGM_PDFLAGS_TRACK_DIRTY set! GCPtr=%RGv PdeDst=%#RX64\n",
4141	GCPtr, (uint64_t)PdeDst.u));
4142	cErrors++;
4143	continue;
4144	}
4145
4146	/* iterate the page table. */
4147	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
4148	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
4149	const unsigned offPTSrc = ((GCPtr >> SHW_PD_SHIFT) & 1) * 512;
4150	# else
4151	const unsigned offPTSrc = 0;
4152	# endif
4153	for (unsigned iPT = 0, off = 0;
4154	iPT < RT_ELEMENTS(pPTDst->a);
4155	iPT++, off += PAGE_SIZE)
4156	{
4157	const SHWPTE PteDst = pPTDst->a[iPT];
4158
4159	/* skip not-present and dirty tracked entries. */
4160	if (!(SHW_PTE_GET_U(PteDst) & (X86_PTE_P \| PGM_PTFLAGS_TRACK_DIRTY))) /** @todo deal with ALL handlers and CSAM !P pages! */
4161	continue;
4162	Assert(SHW_PTE_IS_P(PteDst));
4163
4164	const GSTPTE PteSrc = pPTSrc->a[iPT + offPTSrc];
4165	if (!PteSrc.n.u1Present)
4166	{
4167	# ifdef IN_RING3
4168	PGMAssertHandlerAndFlagsInSync(pVM);
4169	DBGFR3PagingDumpEx(pVM->pUVM, pVCpu->idCpu, DBGFPGDMP_FLAGS_CURRENT_CR3 \| DBGFPGDMP_FLAGS_CURRENT_MODE
4170	\| DBGFPGDMP_FLAGS_GUEST \| DBGFPGDMP_FLAGS_HEADER \| DBGFPGDMP_FLAGS_PRINT_CR3,
4171	0, 0, UINT64_MAX, 99, NULL);
4172	# endif
4173	AssertMsgFailed(("Out of sync (!P) PTE at %RGv! PteSrc=%#RX64 PteDst=%#RX64 pPTSrc=%RGv iPTSrc=%x PdeSrc=%x physpte=%RGp\n",
4174	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst), pPTSrc, iPT + offPTSrc, PdeSrc.au32[0],
4175	(uint64_t)GST_GET_PDE_GCPHYS(PdeSrc) + (iPT + offPTSrc) * sizeof(PteSrc)));
4176	cErrors++;
4177	continue;
4178	}
4179
4180	uint64_t fIgnoreFlags = GST_PTE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_G \| X86_PTE_D \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT;
4181	# if 1 /** @todo sync accessed bit properly... */
4182	fIgnoreFlags \|= X86_PTE_A;
4183	# endif
4184
4185	/* match the physical addresses */
4186	HCPhysShw = SHW_PTE_GET_HCPHYS(PteDst);
4187	GCPhysGst = GST_GET_PTE_GCPHYS(PteSrc);
4188
4189	# ifdef IN_RING3
4190	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
4191	if (RT_FAILURE(rc))
4192	{
4193	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4194	{
4195	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
4196	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4197	cErrors++;
4198	continue;
4199	}
4200	}
4201	else if (HCPhysShw != (HCPhys & SHW_PTE_PG_MASK))
4202	{
4203	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4204	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4205	cErrors++;
4206	continue;
4207	}
4208	# endif
4209
4210	pPhysPage = pgmPhysGetPage(pVM, GCPhysGst);
4211	if (!pPhysPage)
4212	{
4213	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
4214	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4215	{
4216	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
4217	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4218	cErrors++;
4219	continue;
4220	}
4221	# endif
4222	if (SHW_PTE_IS_RW(PteDst))
4223	{
4224	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4225	GCPtr + off, GCPhysGst, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4226	cErrors++;
4227	}
4228	fIgnoreFlags \|= X86_PTE_RW;
4229	}
4230	else if (HCPhysShw != PGM_PAGE_GET_HCPHYS(pPhysPage))
4231	{
4232	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp pPhysPage:%R[pgmpage] GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4233	GCPtr + off, HCPhysShw, pPhysPage, GCPhysGst, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4234	cErrors++;
4235	continue;
4236	}
4237
4238	/* flags */
4239	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
4240	{
4241	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
4242	{
4243	if (SHW_PTE_IS_RW(PteDst))
4244	{
4245	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! pPhysPage=%R[pgmpage] PteSrc=%#RX64 PteDst=%#RX64\n",
4246	GCPtr + off, pPhysPage, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4247	cErrors++;
4248	continue;
4249	}
4250	fIgnoreFlags \|= X86_PTE_RW;
4251	}
4252	else
4253	{
4254	if ( SHW_PTE_IS_P(PteDst)
4255	# if PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
4256	&& !PGM_PAGE_IS_MMIO(pPhysPage)
4257	# endif
4258	)
4259	{
4260	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! pPhysPage=%R[pgmpage] PteSrc=%#RX64 PteDst=%#RX64\n",
4261	GCPtr + off, pPhysPage, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4262	cErrors++;
4263	continue;
4264	}
4265	fIgnoreFlags \|= X86_PTE_P;
4266	}
4267	}
4268	else
4269	{
4270	if (!PteSrc.n.u1Dirty && PteSrc.n.u1Write)
4271	{
4272	if (SHW_PTE_IS_RW(PteDst))
4273	{
4274	AssertMsgFailed(("!DIRTY page at %RGv is writable! PteSrc=%#RX64 PteDst=%#RX64\n",
4275	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4276	cErrors++;
4277	continue;
4278	}
4279	if (!SHW_PTE_IS_TRACK_DIRTY(PteDst))
4280	{
4281	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4282	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4283	cErrors++;
4284	continue;
4285	}
4286	if (SHW_PTE_IS_D(PteDst))
4287	{
4288	AssertMsgFailed(("!DIRTY page at %RGv is marked DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4289	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4290	cErrors++;
4291	}
4292	# if 0 /** @todo sync access bit properly... */
4293	if (PteDst.n.u1Accessed != PteSrc.n.u1Accessed)
4294	{
4295	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4296	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4297	cErrors++;
4298	}
4299	fIgnoreFlags \|= X86_PTE_RW;
4300	# else
4301	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4302	# endif
4303	}
4304	else if (SHW_PTE_IS_TRACK_DIRTY(PteDst))
4305	{
4306	/* access bit emulation (not implemented). */
4307	if (PteSrc.n.u1Accessed \|\| SHW_PTE_IS_P(PteDst))
4308	{
4309	AssertMsgFailed(("PGM_PTFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PteSrc=%#RX64 PteDst=%#RX64\n",
4310	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4311	cErrors++;
4312	continue;
4313	}
4314	if (!SHW_PTE_IS_A(PteDst))
4315	{
4316	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PteSrc=%#RX64 PteDst=%#RX64\n",
4317	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4318	cErrors++;
4319	}
4320	fIgnoreFlags \|= X86_PTE_P;
4321	}
4322	# ifdef DEBUG_sandervl
4323	fIgnoreFlags \|= X86_PTE_D \| X86_PTE_A;
4324	# endif
4325	}
4326
4327	if ( (PteSrc.u & ~fIgnoreFlags) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags)
4328	&& (PteSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags)
4329	)
4330	{
4331	AssertMsgFailed(("Flags mismatch at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PteSrc=%#RX64 PteDst=%#RX64\n",
4332	GCPtr + off, (uint64_t)PteSrc.u & ~fIgnoreFlags, SHW_PTE_LOG64(PteDst) & ~fIgnoreFlags,
4333	fIgnoreFlags, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4334	cErrors++;
4335	continue;
4336	}
4337	} /* foreach PTE */
4338	}
4339	else
4340	{
4341	/*
4342	* Big Page.
4343	*/
4344	uint64_t fIgnoreFlags = X86_PDE_AVL_MASK \| GST_PDE_PG_MASK \| X86_PDE4M_G \| X86_PDE4M_D \| X86_PDE4M_PS \| X86_PDE4M_PWT \| X86_PDE4M_PCD;
4345	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
4346	{
4347	if (PdeDst.n.u1Write)
4348	{
4349	AssertMsgFailed(("!DIRTY page at %RGv is writable! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4350	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4351	cErrors++;
4352	continue;
4353	}
4354	if (!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY))
4355	{
4356	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4357	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4358	cErrors++;
4359	continue;
4360	}
4361	# if 0 /** @todo sync access bit properly... */
4362	if (PdeDst.n.u1Accessed != PdeSrc.b.u1Accessed)
4363	{
4364	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4365	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4366	cErrors++;
4367	}
4368	fIgnoreFlags \|= X86_PTE_RW;
4369	# else
4370	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4371	# endif
4372	}
4373	else if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
4374	{
4375	/* access bit emulation (not implemented). */
4376	if (PdeSrc.b.u1Accessed \|\| PdeDst.n.u1Present)
4377	{
4378	AssertMsgFailed(("PGM_PDFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4379	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4380	cErrors++;
4381	continue;
4382	}
4383	if (!PdeDst.n.u1Accessed)
4384	{
4385	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4386	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4387	cErrors++;
4388	}
4389	fIgnoreFlags \|= X86_PTE_P;
4390	}
4391
4392	if ((PdeSrc.u & ~fIgnoreFlags) != (PdeDst.u & ~fIgnoreFlags))
4393	{
4394	AssertMsgFailed(("Flags mismatch (B) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PdeDst=%#RX64\n",
4395	GCPtr, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PdeDst.u & ~fIgnoreFlags,
4396	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4397	cErrors++;
4398	}
4399
4400	/* iterate the page table. */
4401	for (unsigned iPT = 0, off = 0;
4402	iPT < RT_ELEMENTS(pPTDst->a);
4403	iPT++, off += PAGE_SIZE, GCPhysGst = PGM_A20_APPLY(pVCpu, GCPhysGst + PAGE_SIZE))
4404	{
4405	const SHWPTE PteDst = pPTDst->a[iPT];
4406
4407	if (SHW_PTE_IS_TRACK_DIRTY(PteDst))
4408	{
4409	AssertMsgFailed(("The PTE at %RGv emulating a 2/4M page is marked TRACK_DIRTY! PdeSrc=%#RX64 PteDst=%#RX64\n",
4410	GCPtr + off, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4411	cErrors++;
4412	}
4413
4414	/* skip not-present entries. */
4415	if (!SHW_PTE_IS_P(PteDst)) /** @todo deal with ALL handlers and CSAM !P pages! */
4416	continue;
4417
4418	fIgnoreFlags = X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT \| X86_PTE_D \| X86_PTE_A \| X86_PTE_G \| X86_PTE_PAE_NX;
4419
4420	/* match the physical addresses */
4421	HCPhysShw = SHW_PTE_GET_HCPHYS(PteDst);
4422
4423	# ifdef IN_RING3
4424	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
4425	if (RT_FAILURE(rc))
4426	{
4427	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4428	{
4429	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4430	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4431	cErrors++;
4432	}
4433	}
4434	else if (HCPhysShw != (HCPhys & X86_PTE_PAE_PG_MASK))
4435	{
4436	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4437	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4438	cErrors++;
4439	continue;
4440	}
4441	# endif
4442	pPhysPage = pgmPhysGetPage(pVM, GCPhysGst);
4443	if (!pPhysPage)
4444	{
4445	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
4446	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4447	{
4448	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4449	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4450	cErrors++;
4451	continue;
4452	}
4453	# endif
4454	if (SHW_PTE_IS_RW(PteDst))
4455	{
4456	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4457	GCPtr + off, GCPhysGst, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4458	cErrors++;
4459	}
4460	fIgnoreFlags \|= X86_PTE_RW;
4461	}
4462	else if (HCPhysShw != PGM_PAGE_GET_HCPHYS(pPhysPage))
4463	{
4464	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp pPhysPage=%R[pgmpage] GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4465	GCPtr + off, HCPhysShw, pPhysPage, GCPhysGst, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4466	cErrors++;
4467	continue;
4468	}
4469
4470	/* flags */
4471	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
4472	{
4473	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
4474	{
4475	if (PGM_PAGE_GET_HNDL_PHYS_STATE(pPhysPage) != PGM_PAGE_HNDL_PHYS_STATE_DISABLED)
4476	{
4477	if (SHW_PTE_IS_RW(PteDst))
4478	{
4479	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! pPhysPage=%R[pgmpage] PdeSrc=%#RX64 PteDst=%#RX64\n",
4480	GCPtr + off, pPhysPage, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4481	cErrors++;
4482	continue;
4483	}
4484	fIgnoreFlags \|= X86_PTE_RW;
4485	}
4486	}
4487	else
4488	{
4489	if ( SHW_PTE_IS_P(PteDst)
4490	# if PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
4491	&& !PGM_PAGE_IS_MMIO(pPhysPage)
4492	# endif
4493	)
4494	{
4495	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! pPhysPage=%R[pgmpage] PdeSrc=%#RX64 PteDst=%#RX64\n",
4496	GCPtr + off, pPhysPage, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4497	cErrors++;
4498	continue;
4499	}
4500	fIgnoreFlags \|= X86_PTE_P;
4501	}
4502	}
4503
4504	if ( (PdeSrc.u & ~fIgnoreFlags) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags)
4505	&& (PdeSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags) /* lazy phys handler dereg. */
4506	)
4507	{
4508	AssertMsgFailed(("Flags mismatch (BT) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PteDst=%#RX64\n",
4509	GCPtr + off, (uint64_t)PdeSrc.u & ~fIgnoreFlags, SHW_PTE_LOG64(PteDst) & ~fIgnoreFlags,
4510	fIgnoreFlags, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4511	cErrors++;
4512	continue;
4513	}
4514	} /* for each PTE */
4515	}
4516	}
4517	/* not present */
4518
4519	} /* for each PDE */
4520
4521	} /* for each PDPTE */
4522
4523	} /* for each PML4E */
4524
4525	# ifdef DEBUG
4526	if (cErrors)
4527	LogFlow(("AssertCR3: cErrors=%d\n", cErrors));
4528	# endif
4529	# endif /* GST is in {32BIT, PAE, AMD64} */
4530	return cErrors;
4531	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT */
4532	}
4533	#endif /* VBOX_STRICT */
4534
4535
4536	/**
4537	* Sets up the CR3 for shadow paging
4538	*
4539	* @returns Strict VBox status code.
4540	* @retval VINF_SUCCESS.
4541	*
4542	* @param pVCpu The cross context virtual CPU structure.
4543	* @param GCPhysCR3 The physical address in the CR3 register. (A20
4544	* mask already applied.)
4545	*/
4546	PGM_BTH_DECL(int, MapCR3)(PVMCPU pVCpu, RTGCPHYS GCPhysCR3)
4547	{
4548	PVM pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
4549
4550	/* Update guest paging info. */
4551	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
4552	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
4553	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
4554
4555	LogFlow(("MapCR3: %RGp\n", GCPhysCR3));
4556	PGM_A20_ASSERT_MASKED(pVCpu, GCPhysCR3);
4557
4558	/*
4559	* Map the page CR3 points at.
4560	*/
4561	RTHCPTR HCPtrGuestCR3;
4562	RTHCPHYS HCPhysGuestCR3;
4563	pgmLock(pVM);
4564	PPGMPAGE pPageCR3 = pgmPhysGetPage(pVM, GCPhysCR3);
4565	AssertReturn(pPageCR3, VERR_PGM_INVALID_CR3_ADDR);
4566	HCPhysGuestCR3 = PGM_PAGE_GET_HCPHYS(pPageCR3);
4567	/** @todo this needs some reworking wrt. locking? */
4568	# if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
4569	HCPtrGuestCR3 = NIL_RTHCPTR;
4570	int rc = VINF_SUCCESS;
4571	# else
4572	int rc = pgmPhysGCPhys2CCPtrInternalDepr(pVM, pPageCR3, GCPhysCR3 & GST_CR3_PAGE_MASK, (void )&HCPtrGuestCR3); / @todo r=bird: This GCPhysCR3 masking isn't necessary. */
4573	# endif
4574	pgmUnlock(pVM);
4575	if (RT_SUCCESS(rc))
4576	{
4577	rc = PGMMap(pVM, (RTGCPTR)pVM->pgm.s.GCPtrCR3Mapping, HCPhysGuestCR3, PAGE_SIZE, 0);
4578	if (RT_SUCCESS(rc))
4579	{
4580	# ifdef IN_RC
4581	PGM_INVL_PG(pVCpu, pVM->pgm.s.GCPtrCR3Mapping);
4582	# endif
4583	# if PGM_GST_TYPE == PGM_TYPE_32BIT
4584	pVCpu->pgm.s.pGst32BitPdR3 = (R3PTRTYPE(PX86PD))HCPtrGuestCR3;
4585	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4586	pVCpu->pgm.s.pGst32BitPdR0 = (R0PTRTYPE(PX86PD))HCPtrGuestCR3;
4587	# endif
4588	pVCpu->pgm.s.pGst32BitPdRC = (RCPTRTYPE(PX86PD))(RTRCUINTPTR)pVM->pgm.s.GCPtrCR3Mapping;
4589
4590	# elif PGM_GST_TYPE == PGM_TYPE_PAE
4591	unsigned off = GCPhysCR3 & GST_CR3_PAGE_MASK & PAGE_OFFSET_MASK;
4592	pVCpu->pgm.s.pGstPaePdptR3 = (R3PTRTYPE(PX86PDPT))HCPtrGuestCR3;
4593	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4594	pVCpu->pgm.s.pGstPaePdptR0 = (R0PTRTYPE(PX86PDPT))HCPtrGuestCR3;
4595	# endif
4596	pVCpu->pgm.s.pGstPaePdptRC = (RCPTRTYPE(PX86PDPT))((RTRCUINTPTR)pVM->pgm.s.GCPtrCR3Mapping + off);
4597	LogFlow(("Cached mapping %RRv\n", pVCpu->pgm.s.pGstPaePdptRC));
4598
4599	/*
4600	* Map the 4 PDs too.
4601	*/
4602	PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pVCpu);
4603	RTGCPTR GCPtr = pVM->pgm.s.GCPtrCR3Mapping + PAGE_SIZE;
4604	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++, GCPtr += PAGE_SIZE)
4605	{
4606	pVCpu->pgm.s.aGstPaePdpeRegs[i].u = pGuestPDPT->a[i].u;
4607	if (pGuestPDPT->a[i].n.u1Present)
4608	{
4609	RTHCPTR HCPtr;
4610	RTHCPHYS HCPhys;
4611	RTGCPHYS GCPhys = PGM_A20_APPLY(pVCpu, pGuestPDPT->a[i].u & X86_PDPE_PG_MASK);
4612	pgmLock(pVM);
4613	PPGMPAGE pPage = pgmPhysGetPage(pVM, GCPhys);
4614	AssertReturn(pPage, VERR_PGM_INVALID_PDPE_ADDR);
4615	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
4616	# if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
4617	HCPtr = NIL_RTHCPTR;
4618	int rc2 = VINF_SUCCESS;
4619	# else
4620	int rc2 = pgmPhysGCPhys2CCPtrInternalDepr(pVM, pPage, GCPhys, (void **)&HCPtr);
4621	# endif
4622	pgmUnlock(pVM);
4623	if (RT_SUCCESS(rc2))
4624	{
4625	rc = PGMMap(pVM, GCPtr, HCPhys, PAGE_SIZE, 0);
4626	AssertRCReturn(rc, rc);
4627
4628	pVCpu->pgm.s.apGstPaePDsR3[i] = (R3PTRTYPE(PX86PDPAE))HCPtr;
4629	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4630	pVCpu->pgm.s.apGstPaePDsR0[i] = (R0PTRTYPE(PX86PDPAE))HCPtr;
4631	# endif
4632	pVCpu->pgm.s.apGstPaePDsRC[i] = (RCPTRTYPE(PX86PDPAE))(RTRCUINTPTR)GCPtr;
4633	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = GCPhys;
4634	# ifdef IN_RC
4635	PGM_INVL_PG(pVCpu, GCPtr);
4636	# endif
4637	continue;
4638	}
4639	AssertMsgFailed(("pgmR3Gst32BitMapCR3: rc2=%d GCPhys=%RGp i=%d\n", rc2, GCPhys, i));
4640	}
4641
4642	pVCpu->pgm.s.apGstPaePDsR3[i] = 0;
4643	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4644	pVCpu->pgm.s.apGstPaePDsR0[i] = 0;
4645	# endif
4646	pVCpu->pgm.s.apGstPaePDsRC[i] = 0;
4647	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
4648	# ifdef IN_RC
4649	PGM_INVL_PG(pVCpu, GCPtr); /** @todo this shouldn't be necessary? */
4650	# endif
4651	}
4652
4653	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
4654	pVCpu->pgm.s.pGstAmd64Pml4R3 = (R3PTRTYPE(PX86PML4))HCPtrGuestCR3;
4655	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4656	pVCpu->pgm.s.pGstAmd64Pml4R0 = (R0PTRTYPE(PX86PML4))HCPtrGuestCR3;
4657	# endif
4658	# endif
4659	}
4660	else
4661	AssertMsgFailed(("rc=%Rrc GCPhysGuestPD=%RGp\n", rc, GCPhysCR3));
4662	}
4663	else
4664	AssertMsgFailed(("rc=%Rrc GCPhysGuestPD=%RGp\n", rc, GCPhysCR3));
4665
4666	#else /* prot/real stub */
4667	int rc = VINF_SUCCESS;
4668	#endif
4669
4670	/* Update shadow paging info for guest modes with paging (32, pae, 64). */
4671	# if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
4672	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
4673	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64) \
4674	&& ( PGM_GST_TYPE != PGM_TYPE_REAL \
4675	&& PGM_GST_TYPE != PGM_TYPE_PROT))
4676
4677	Assert(!pVM->pgm.s.fNestedPaging);
4678	PGM_A20_ASSERT_MASKED(pVCpu, GCPhysCR3);
4679
4680	/*
4681	* Update the shadow root page as well since that's not fixed.
4682	*/
4683	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4684	PPGMPOOLPAGE pOldShwPageCR3 = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
4685	PPGMPOOLPAGE pNewShwPageCR3;
4686
4687	pgmLock(pVM);
4688
4689	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
4690	if (pPool->cDirtyPages)
4691	pgmPoolResetDirtyPages(pVM);
4692	# endif
4693
4694	Assert(!(GCPhysCR3 >> (PAGE_SHIFT + 32)));
4695	rc = pgmPoolAlloc(pVM, GCPhysCR3 & GST_CR3_PAGE_MASK, BTH_PGMPOOLKIND_ROOT, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
4696	NIL_PGMPOOL_IDX, UINT32_MAX, true /fLockPage/,
4697	&pNewShwPageCR3);
4698	AssertFatalRC(rc);
4699	rc = VINF_SUCCESS;
4700
4701	# ifdef IN_RC
4702	/*
4703	* WARNING! We can't deal with jumps to ring 3 in the code below as the
4704	* state will be inconsistent! Flush important things now while
4705	* we still can and then make sure there are no ring-3 calls.
4706	*/
4707	# ifdef VBOX_WITH_REM
4708	REMNotifyHandlerPhysicalFlushIfAlmostFull(pVM, pVCpu);
4709	# endif
4710	VMMRZCallRing3Disable(pVCpu);
4711	# endif
4712
4713	pVCpu->pgm.s.CTX_SUFF(pShwPageCR3) = pNewShwPageCR3;
4714	# ifdef IN_RING0
4715	pVCpu->pgm.s.pShwPageCR3R3 = MMHyperCCToR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4716	pVCpu->pgm.s.pShwPageCR3RC = MMHyperCCToRC(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4717	# elif defined(IN_RC)
4718	pVCpu->pgm.s.pShwPageCR3R3 = MMHyperCCToR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4719	pVCpu->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4720	# else
4721	pVCpu->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4722	pVCpu->pgm.s.pShwPageCR3RC = MMHyperCCToRC(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4723	# endif
4724
4725	# ifndef PGM_WITHOUT_MAPPINGS
4726	/*
4727	* Apply all hypervisor mappings to the new CR3.
4728	* Note that SyncCR3 will be executed in case CR3 is changed in a guest paging mode; this will
4729	* make sure we check for conflicts in the new CR3 root.
4730	*/
4731	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
4732	Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL) \|\| VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
4733	# endif
4734	rc = pgmMapActivateCR3(pVM, pNewShwPageCR3);
4735	AssertRCReturn(rc, rc);
4736	# endif
4737
4738	/* Set the current hypervisor CR3. */
4739	CPUMSetHyperCR3(pVCpu, PGMGetHyperCR3(pVCpu));
4740	SELMShadowCR3Changed(pVM, pVCpu);
4741
4742	# ifdef IN_RC
4743	/* NOTE: The state is consistent again. */
4744	VMMRZCallRing3Enable(pVCpu);
4745	# endif
4746
4747	/* Clean up the old CR3 root. */
4748	if ( pOldShwPageCR3
4749	&& pOldShwPageCR3 != pNewShwPageCR3 /* @todo can happen due to incorrect syncing between REM & PGM; find the real cause */)
4750	{
4751	Assert(pOldShwPageCR3->enmKind != PGMPOOLKIND_FREE);
4752	# ifndef PGM_WITHOUT_MAPPINGS
4753	/* Remove the hypervisor mappings from the shadow page table. */
4754	pgmMapDeactivateCR3(pVM, pOldShwPageCR3);
4755	# endif
4756	/* Mark the page as unlocked; allow flushing again. */
4757	pgmPoolUnlockPage(pPool, pOldShwPageCR3);
4758
4759	pgmPoolFreeByPage(pPool, pOldShwPageCR3, NIL_PGMPOOL_IDX, UINT32_MAX);
4760	}
4761	pgmUnlock(pVM);
4762	# else
4763	NOREF(GCPhysCR3);
4764	# endif
4765
4766	return rc;
4767	}
4768
4769	/**
4770	* Unmaps the shadow CR3.
4771	*
4772	* @returns VBox status, no specials.
4773	* @param pVCpu The cross context virtual CPU structure.
4774	*/
4775	PGM_BTH_DECL(int, UnmapCR3)(PVMCPU pVCpu)
4776	{
4777	LogFlow(("UnmapCR3\n"));
4778
4779	int rc = VINF_SUCCESS;
4780	PVM pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
4781
4782	/*
4783	* Update guest paging info.
4784	*/
4785	#if PGM_GST_TYPE == PGM_TYPE_32BIT
4786	pVCpu->pgm.s.pGst32BitPdR3 = 0;
4787	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4788	pVCpu->pgm.s.pGst32BitPdR0 = 0;
4789	# endif
4790	pVCpu->pgm.s.pGst32BitPdRC = 0;
4791
4792	#elif PGM_GST_TYPE == PGM_TYPE_PAE
4793	pVCpu->pgm.s.pGstPaePdptR3 = 0;
4794	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4795	pVCpu->pgm.s.pGstPaePdptR0 = 0;
4796	# endif
4797	pVCpu->pgm.s.pGstPaePdptRC = 0;
4798	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
4799	{
4800	pVCpu->pgm.s.apGstPaePDsR3[i] = 0;
4801	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4802	pVCpu->pgm.s.apGstPaePDsR0[i] = 0;
4803	# endif
4804	pVCpu->pgm.s.apGstPaePDsRC[i] = 0;
4805	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
4806	}
4807
4808	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
4809	pVCpu->pgm.s.pGstAmd64Pml4R3 = 0;
4810	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4811	pVCpu->pgm.s.pGstAmd64Pml4R0 = 0;
4812	# endif
4813
4814	#else /* prot/real mode stub */
4815	/* nothing to do */
4816	#endif
4817
4818	#if !defined(IN_RC) /* In RC we rely on MapCR3 to do the shadow part for us at a safe time */
4819	/*
4820	* Update shadow paging info.
4821	*/
4822	# if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
4823	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
4824	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64))
4825
4826	# if PGM_GST_TYPE != PGM_TYPE_REAL
4827	Assert(!pVM->pgm.s.fNestedPaging);
4828	# endif
4829
4830	pgmLock(pVM);
4831
4832	# ifndef PGM_WITHOUT_MAPPINGS
4833	if (pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
4834	/* Remove the hypervisor mappings from the shadow page table. */
4835	pgmMapDeactivateCR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4836	# endif
4837
4838	if (pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
4839	{
4840	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4841
4842	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
4843	if (pPool->cDirtyPages)
4844	pgmPoolResetDirtyPages(pVM);
4845	# endif
4846
4847	/* Mark the page as unlocked; allow flushing again. */
4848	pgmPoolUnlockPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4849
4850	pgmPoolFreeByPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3), NIL_PGMPOOL_IDX, UINT32_MAX);
4851	pVCpu->pgm.s.pShwPageCR3R3 = 0;
4852	pVCpu->pgm.s.pShwPageCR3R0 = 0;
4853	pVCpu->pgm.s.pShwPageCR3RC = 0;
4854	}
4855	pgmUnlock(pVM);
4856	# endif
4857	#endif /* !IN_RC*/
4858
4859	return rc;
4860	}

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllBth.h@ 64468

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